2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
38 static int get_edp_pipe(struct intel_vgpu
*vgpu
)
40 u32 data
= vgpu_vreg(vgpu
, _TRANS_DDI_FUNC_CTL_EDP
);
43 switch (data
& TRANS_DDI_EDP_INPUT_MASK
) {
44 case TRANS_DDI_EDP_INPUT_A_ON
:
45 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
48 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
51 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
58 static int edp_pipe_is_enabled(struct intel_vgpu
*vgpu
)
60 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->dev_priv
;
62 if (!(vgpu_vreg(vgpu
, PIPECONF(_PIPE_EDP
)) & PIPECONF_ENABLE
))
65 if (!(vgpu_vreg(vgpu
, _TRANS_DDI_FUNC_CTL_EDP
) & TRANS_DDI_FUNC_ENABLE
))
70 static int pipe_is_enabled(struct intel_vgpu
*vgpu
, int pipe
)
72 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->dev_priv
;
74 if (WARN_ON(pipe
< PIPE_A
|| pipe
>= I915_MAX_PIPES
))
77 if (vgpu_vreg(vgpu
, PIPECONF(pipe
)) & PIPECONF_ENABLE
)
80 if (edp_pipe_is_enabled(vgpu
) &&
81 get_edp_pipe(vgpu
) == pipe
)
86 /* EDID with 1920x1200 as its resolution */
87 static unsigned char virtual_dp_monitor_edid
[] = {
89 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
90 /* Vendor & Product Identification */
91 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
92 /* Version & Revision */
94 /* Basic Display Parameters & Features */
95 0xa5, 0x34, 0x20, 0x78, 0x23,
96 /* Color Characteristics */
97 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
98 /* Established Timings: maximum resolution is 1024x768 */
102 * below new resolutions can be supported:
103 * 1920x1080, 1280x720, 1280x960, 1280x1024,
104 * 1440x900, 1600x1200, 1680x1050
106 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
107 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
108 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
109 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
110 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
111 /* 18 Byte Data Blocks 2: invalid */
112 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
113 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
114 /* 18 Byte Data Blocks 3: invalid */
115 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
116 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
117 /* 18 Byte Data Blocks 4: invalid */
118 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
119 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
120 /* Extension Block Count */
126 #define DPCD_HEADER_SIZE 0xb
128 static u8 dpcd_fix_data
[DPCD_HEADER_SIZE
] = {
129 0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
132 static void emulate_monitor_status_change(struct intel_vgpu
*vgpu
)
134 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->dev_priv
;
135 vgpu_vreg(vgpu
, SDEISR
) &= ~(SDE_PORTB_HOTPLUG_CPT
|
136 SDE_PORTC_HOTPLUG_CPT
|
137 SDE_PORTD_HOTPLUG_CPT
);
139 if (IS_SKYLAKE(dev_priv
))
140 vgpu_vreg(vgpu
, SDEISR
) &= ~(SDE_PORTA_HOTPLUG_SPT
|
141 SDE_PORTE_HOTPLUG_SPT
);
143 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_B
))
144 vgpu_vreg(vgpu
, SDEISR
) |= SDE_PORTB_HOTPLUG_CPT
;
146 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_C
))
147 vgpu_vreg(vgpu
, SDEISR
) |= SDE_PORTC_HOTPLUG_CPT
;
149 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_D
))
150 vgpu_vreg(vgpu
, SDEISR
) |= SDE_PORTD_HOTPLUG_CPT
;
152 if (IS_SKYLAKE(dev_priv
) &&
153 intel_vgpu_has_monitor_on_port(vgpu
, PORT_E
)) {
154 vgpu_vreg(vgpu
, SDEISR
) |= SDE_PORTE_HOTPLUG_SPT
;
157 if (intel_vgpu_has_monitor_on_port(vgpu
, PORT_A
)) {
158 if (IS_BROADWELL(dev_priv
))
159 vgpu_vreg(vgpu
, GEN8_DE_PORT_ISR
) |=
160 GEN8_PORT_DP_A_HOTPLUG
;
162 vgpu_vreg(vgpu
, SDEISR
) |= SDE_PORTA_HOTPLUG_SPT
;
166 static void clean_virtual_dp_monitor(struct intel_vgpu
*vgpu
, int port_num
)
168 struct intel_vgpu_port
*port
= intel_vgpu_port(vgpu
, port_num
);
177 static int setup_virtual_dp_monitor(struct intel_vgpu
*vgpu
, int port_num
,
180 struct intel_vgpu_port
*port
= intel_vgpu_port(vgpu
, port_num
);
182 port
->edid
= kzalloc(sizeof(*(port
->edid
)), GFP_KERNEL
);
186 port
->dpcd
= kzalloc(sizeof(*(port
->dpcd
)), GFP_KERNEL
);
192 memcpy(port
->edid
->edid_block
, virtual_dp_monitor_edid
,
194 port
->edid
->data_valid
= true;
196 memcpy(port
->dpcd
->data
, dpcd_fix_data
, DPCD_HEADER_SIZE
);
197 port
->dpcd
->data_valid
= true;
198 port
->dpcd
->data
[DPCD_SINK_COUNT
] = 0x1;
201 emulate_monitor_status_change(vgpu
);
206 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
207 * be turned on/off when a virtual pipe is enabled/disabled.
210 * This function is used to turn on/off vblank timer according to currently
211 * enabled/disabled virtual pipes.
214 void intel_gvt_check_vblank_emulation(struct intel_gvt
*gvt
)
216 struct intel_gvt_irq
*irq
= &gvt
->irq
;
217 struct intel_vgpu
*vgpu
;
218 bool have_enabled_pipe
= false;
221 if (WARN_ON(!mutex_is_locked(&gvt
->lock
)))
224 hrtimer_cancel(&irq
->vblank_timer
.timer
);
226 for_each_active_vgpu(gvt
, vgpu
, id
) {
227 for (pipe
= 0; pipe
< I915_MAX_PIPES
; pipe
++) {
229 pipe_is_enabled(vgpu
, pipe
);
230 if (have_enabled_pipe
)
235 if (have_enabled_pipe
)
236 hrtimer_start(&irq
->vblank_timer
.timer
,
237 ktime_add_ns(ktime_get(), irq
->vblank_timer
.period
),
241 static void emulate_vblank_on_pipe(struct intel_vgpu
*vgpu
, int pipe
)
243 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->dev_priv
;
244 struct intel_vgpu_irq
*irq
= &vgpu
->irq
;
245 int vblank_event
[] = {
246 [PIPE_A
] = PIPE_A_VBLANK
,
247 [PIPE_B
] = PIPE_B_VBLANK
,
248 [PIPE_C
] = PIPE_C_VBLANK
,
252 if (pipe
< PIPE_A
|| pipe
> PIPE_C
)
255 for_each_set_bit(event
, irq
->flip_done_event
[pipe
],
256 INTEL_GVT_EVENT_MAX
) {
257 clear_bit(event
, irq
->flip_done_event
[pipe
]);
258 if (!pipe_is_enabled(vgpu
, pipe
))
261 vgpu_vreg(vgpu
, PIPE_FLIPCOUNT_G4X(pipe
))++;
262 intel_vgpu_trigger_virtual_event(vgpu
, event
);
265 if (pipe_is_enabled(vgpu
, pipe
)) {
266 vgpu_vreg(vgpu
, PIPE_FRMCOUNT_G4X(pipe
))++;
267 intel_vgpu_trigger_virtual_event(vgpu
, vblank_event
[pipe
]);
271 static void emulate_vblank(struct intel_vgpu
*vgpu
)
275 for_each_pipe(vgpu
->gvt
->dev_priv
, pipe
)
276 emulate_vblank_on_pipe(vgpu
, pipe
);
280 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
283 * This function is used to trigger vblank interrupts for vGPUs on GVT device
286 void intel_gvt_emulate_vblank(struct intel_gvt
*gvt
)
288 struct intel_vgpu
*vgpu
;
291 if (WARN_ON(!mutex_is_locked(&gvt
->lock
)))
294 for_each_active_vgpu(gvt
, vgpu
, id
)
295 emulate_vblank(vgpu
);
299 * intel_vgpu_clean_display - clean vGPU virtual display emulation
302 * This function is used to clean vGPU virtual display emulation stuffs
305 void intel_vgpu_clean_display(struct intel_vgpu
*vgpu
)
307 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->dev_priv
;
309 if (IS_SKYLAKE(dev_priv
))
310 clean_virtual_dp_monitor(vgpu
, PORT_D
);
312 clean_virtual_dp_monitor(vgpu
, PORT_B
);
316 * intel_vgpu_init_display- initialize vGPU virtual display emulation
319 * This function is used to initialize vGPU virtual display emulation stuffs
322 * Zero on success, negative error code if failed.
325 int intel_vgpu_init_display(struct intel_vgpu
*vgpu
)
327 struct drm_i915_private
*dev_priv
= vgpu
->gvt
->dev_priv
;
329 intel_vgpu_init_i2c_edid(vgpu
);
331 if (IS_SKYLAKE(dev_priv
))
332 return setup_virtual_dp_monitor(vgpu
, PORT_D
, GVT_DP_D
);
334 return setup_virtual_dp_monitor(vgpu
, PORT_B
, GVT_DP_B
);
338 * intel_vgpu_reset_display- reset vGPU virtual display emulation
341 * This function is used to reset vGPU virtual display emulation stuffs
344 void intel_vgpu_reset_display(struct intel_vgpu
*vgpu
)
346 emulate_monitor_status_change(vgpu
);