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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / gvt / handlers.c
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include "i915_drv.h"
40 #include "gvt.h"
41 #include "i915_pvinfo.h"
42
43 /* XXX FIXME i915 has changed PP_XXX definition */
44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
49
50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51 {
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
58
59 return 0;
60 }
61
62 bool intel_gvt_match_device(struct intel_gvt *gvt,
63 unsigned long device)
64 {
65 return intel_gvt_get_device_type(gvt) & device;
66 }
67
68 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
69 void *p_data, unsigned int bytes)
70 {
71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
72 }
73
74 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
75 void *p_data, unsigned int bytes)
76 {
77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
78 }
79
80 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
81 unsigned int offset)
82 {
83 struct intel_gvt_mmio_info *e;
84
85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
86 if (e->offset == offset)
87 return e;
88 }
89 return NULL;
90 }
91
92 static int new_mmio_info(struct intel_gvt *gvt,
93 u32 offset, u8 flags, u32 size,
94 u32 addr_mask, u32 ro_mask, u32 device,
95 gvt_mmio_func read, gvt_mmio_func write)
96 {
97 struct intel_gvt_mmio_info *info, *p;
98 u32 start, end, i;
99
100 if (!intel_gvt_match_device(gvt, device))
101 return 0;
102
103 if (WARN_ON(!IS_ALIGNED(offset, 4)))
104 return -EINVAL;
105
106 start = offset;
107 end = offset + size;
108
109 for (i = start; i < end; i += 4) {
110 info = kzalloc(sizeof(*info), GFP_KERNEL);
111 if (!info)
112 return -ENOMEM;
113
114 info->offset = i;
115 p = find_mmio_info(gvt, info->offset);
116 if (p)
117 gvt_err("dup mmio definition offset %x\n",
118 info->offset);
119
120 info->ro_mask = ro_mask;
121 info->device = device;
122 info->read = read ? read : intel_vgpu_default_mmio_read;
123 info->write = write ? write : intel_vgpu_default_mmio_write;
124 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
125 INIT_HLIST_NODE(&info->node);
126 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
127 gvt->mmio.num_tracked_mmio++;
128 }
129 return 0;
130 }
131
132 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg)
133 {
134 enum intel_engine_id id;
135 struct intel_engine_cs *engine;
136
137 reg &= ~GENMASK(11, 0);
138 for_each_engine(engine, gvt->dev_priv, id) {
139 if (engine->mmio_base == reg)
140 return id;
141 }
142 return -1;
143 }
144
145 #define offset_to_fence_num(offset) \
146 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
147
148 #define fence_num_to_offset(num) \
149 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
150
151
152 static void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
153 {
154 switch (reason) {
155 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
156 pr_err("Detected your guest driver doesn't support GVT-g.\n");
157 break;
158 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
159 pr_err("Graphics resource is not enough for the guest\n");
160 default:
161 break;
162 }
163 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
164 vgpu->failsafe = true;
165 }
166
167 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
168 unsigned int fence_num, void *p_data, unsigned int bytes)
169 {
170 if (fence_num >= vgpu_fence_sz(vgpu)) {
171
172 /* When guest access oob fence regs without access
173 * pv_info first, we treat guest not supporting GVT,
174 * and we will let vgpu enter failsafe mode.
175 */
176 if (!vgpu->pv_notified)
177 enter_failsafe_mode(vgpu,
178 GVT_FAILSAFE_UNSUPPORTED_GUEST);
179
180 if (!vgpu->mmio.disable_warn_untrack) {
181 gvt_vgpu_err("found oob fence register access\n");
182 gvt_vgpu_err("total fence %d, access fence %d\n",
183 vgpu_fence_sz(vgpu), fence_num);
184 }
185 memset(p_data, 0, bytes);
186 return -EINVAL;
187 }
188 return 0;
189 }
190
191 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
192 void *p_data, unsigned int bytes)
193 {
194 int ret;
195
196 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
197 p_data, bytes);
198 if (ret)
199 return ret;
200 read_vreg(vgpu, off, p_data, bytes);
201 return 0;
202 }
203
204 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
205 void *p_data, unsigned int bytes)
206 {
207 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
208 unsigned int fence_num = offset_to_fence_num(off);
209 int ret;
210
211 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
212 if (ret)
213 return ret;
214 write_vreg(vgpu, off, p_data, bytes);
215
216 mmio_hw_access_pre(dev_priv);
217 intel_vgpu_write_fence(vgpu, fence_num,
218 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
219 mmio_hw_access_post(dev_priv);
220 return 0;
221 }
222
223 #define CALC_MODE_MASK_REG(old, new) \
224 (((new) & GENMASK(31, 16)) \
225 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
226 | ((new) & ((new) >> 16))))
227
228 static int mul_force_wake_write(struct intel_vgpu *vgpu,
229 unsigned int offset, void *p_data, unsigned int bytes)
230 {
231 u32 old, new;
232 uint32_t ack_reg_offset;
233
234 old = vgpu_vreg(vgpu, offset);
235 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
236
237 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
238 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
239 switch (offset) {
240 case FORCEWAKE_RENDER_GEN9_REG:
241 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
242 break;
243 case FORCEWAKE_BLITTER_GEN9_REG:
244 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
245 break;
246 case FORCEWAKE_MEDIA_GEN9_REG:
247 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
248 break;
249 default:
250 /*should not hit here*/
251 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
252 return -EINVAL;
253 }
254 } else {
255 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
256 }
257
258 vgpu_vreg(vgpu, offset) = new;
259 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
260 return 0;
261 }
262
263 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
264 void *p_data, unsigned int bytes)
265 {
266 unsigned int engine_mask = 0;
267 u32 data;
268
269 write_vreg(vgpu, offset, p_data, bytes);
270 data = vgpu_vreg(vgpu, offset);
271
272 if (data & GEN6_GRDOM_FULL) {
273 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
274 engine_mask = ALL_ENGINES;
275 } else {
276 if (data & GEN6_GRDOM_RENDER) {
277 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
278 engine_mask |= (1 << RCS);
279 }
280 if (data & GEN6_GRDOM_MEDIA) {
281 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
282 engine_mask |= (1 << VCS);
283 }
284 if (data & GEN6_GRDOM_BLT) {
285 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
286 engine_mask |= (1 << BCS);
287 }
288 if (data & GEN6_GRDOM_VECS) {
289 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
290 engine_mask |= (1 << VECS);
291 }
292 if (data & GEN8_GRDOM_MEDIA2) {
293 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
294 if (HAS_BSD2(vgpu->gvt->dev_priv))
295 engine_mask |= (1 << VCS2);
296 }
297 }
298
299 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
300
301 /* sw will wait for the device to ack the reset request */
302 vgpu_vreg(vgpu, offset) = 0;
303
304 return 0;
305 }
306
307 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
308 void *p_data, unsigned int bytes)
309 {
310 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
311 }
312
313 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
314 void *p_data, unsigned int bytes)
315 {
316 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
317 }
318
319 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
320 unsigned int offset, void *p_data, unsigned int bytes)
321 {
322 write_vreg(vgpu, offset, p_data, bytes);
323
324 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
325 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON;
326 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
327 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
328 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
329
330 } else
331 vgpu_vreg(vgpu, PCH_PP_STATUS) &=
332 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
333 | PP_CYCLE_DELAY_ACTIVE);
334 return 0;
335 }
336
337 static int transconf_mmio_write(struct intel_vgpu *vgpu,
338 unsigned int offset, void *p_data, unsigned int bytes)
339 {
340 write_vreg(vgpu, offset, p_data, bytes);
341
342 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
343 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
344 else
345 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
346 return 0;
347 }
348
349 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
350 void *p_data, unsigned int bytes)
351 {
352 write_vreg(vgpu, offset, p_data, bytes);
353
354 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
355 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
356 else
357 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
358
359 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
360 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
361 else
362 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
363
364 return 0;
365 }
366
367 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
368 void *p_data, unsigned int bytes)
369 {
370 switch (offset) {
371 case 0xe651c:
372 case 0xe661c:
373 case 0xe671c:
374 case 0xe681c:
375 vgpu_vreg(vgpu, offset) = 1 << 17;
376 break;
377 case 0xe6c04:
378 vgpu_vreg(vgpu, offset) = 0x3;
379 break;
380 case 0xe6e1c:
381 vgpu_vreg(vgpu, offset) = 0x2f << 16;
382 break;
383 default:
384 return -EINVAL;
385 }
386
387 read_vreg(vgpu, offset, p_data, bytes);
388 return 0;
389 }
390
391 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
392 void *p_data, unsigned int bytes)
393 {
394 u32 data;
395
396 write_vreg(vgpu, offset, p_data, bytes);
397 data = vgpu_vreg(vgpu, offset);
398
399 if (data & PIPECONF_ENABLE)
400 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
401 else
402 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
403 intel_gvt_check_vblank_emulation(vgpu->gvt);
404 return 0;
405 }
406
407 /* ascendingly sorted */
408 static i915_reg_t force_nonpriv_white_list[] = {
409 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
410 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
411 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
412 _MMIO(0x2690),
413 _MMIO(0x2694),
414 _MMIO(0x2698),
415 _MMIO(0x4de0),
416 _MMIO(0x4de4),
417 _MMIO(0x4dfc),
418 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
419 _MMIO(0x7014),
420 HDC_CHICKEN0,//_MMIO(0x7300)
421 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
422 _MMIO(0x7700),
423 _MMIO(0x7704),
424 _MMIO(0x7708),
425 _MMIO(0x770c),
426 _MMIO(0xb110),
427 GEN8_L3SQCREG4,//_MMIO(0xb118)
428 _MMIO(0xe100),
429 _MMIO(0xe18c),
430 _MMIO(0xe48c),
431 _MMIO(0xe5f4),
432 };
433
434 /* a simple bsearch */
435 static inline bool in_whitelist(unsigned int reg)
436 {
437 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
438 i915_reg_t *array = force_nonpriv_white_list;
439
440 while (left < right) {
441 int mid = (left + right)/2;
442
443 if (reg > array[mid].reg)
444 left = mid + 1;
445 else if (reg < array[mid].reg)
446 right = mid;
447 else
448 return true;
449 }
450 return false;
451 }
452
453 static int force_nonpriv_write(struct intel_vgpu *vgpu,
454 unsigned int offset, void *p_data, unsigned int bytes)
455 {
456 u32 reg_nonpriv = *(u32 *)p_data;
457 int ret = -EINVAL;
458
459 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
460 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
461 vgpu->id, offset, bytes);
462 return ret;
463 }
464
465 if (in_whitelist(reg_nonpriv)) {
466 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
467 bytes);
468 } else {
469 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
470 vgpu->id, reg_nonpriv);
471 }
472 return ret;
473 }
474
475 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
476 void *p_data, unsigned int bytes)
477 {
478 write_vreg(vgpu, offset, p_data, bytes);
479
480 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
481 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
482 } else {
483 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
484 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
485 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E))
486 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
487 }
488 return 0;
489 }
490
491 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
492 unsigned int offset, void *p_data, unsigned int bytes)
493 {
494 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
495 return 0;
496 }
497
498 #define FDI_LINK_TRAIN_PATTERN1 0
499 #define FDI_LINK_TRAIN_PATTERN2 1
500
501 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
502 {
503 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E));
504 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
505 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E));
506
507 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
508 (rx_ctl & FDI_RX_ENABLE) &&
509 (rx_ctl & FDI_AUTO_TRAINING) &&
510 (tx_ctl & DP_TP_CTL_ENABLE) &&
511 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
512 return 1;
513 else
514 return 0;
515 }
516
517 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
518 enum pipe pipe, unsigned int train_pattern)
519 {
520 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
521 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
522 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
523 unsigned int fdi_iir_check_bits;
524
525 fdi_rx_imr = FDI_RX_IMR(pipe);
526 fdi_tx_ctl = FDI_TX_CTL(pipe);
527 fdi_rx_ctl = FDI_RX_CTL(pipe);
528
529 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
530 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
531 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
532 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
533 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
534 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
535 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
536 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
537 } else {
538 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
539 return -EINVAL;
540 }
541
542 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
543 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
544
545 /* If imr bit has been masked */
546 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
547 return 0;
548
549 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
550 == fdi_tx_check_bits)
551 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
552 == fdi_rx_check_bits))
553 return 1;
554 else
555 return 0;
556 }
557
558 #define INVALID_INDEX (~0U)
559
560 static unsigned int calc_index(unsigned int offset, unsigned int start,
561 unsigned int next, unsigned int end, i915_reg_t i915_end)
562 {
563 unsigned int range = next - start;
564
565 if (!end)
566 end = i915_mmio_reg_offset(i915_end);
567 if (offset < start || offset > end)
568 return INVALID_INDEX;
569 offset -= start;
570 return offset / range;
571 }
572
573 #define FDI_RX_CTL_TO_PIPE(offset) \
574 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
575
576 #define FDI_TX_CTL_TO_PIPE(offset) \
577 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
578
579 #define FDI_RX_IMR_TO_PIPE(offset) \
580 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
581
582 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
583 unsigned int offset, void *p_data, unsigned int bytes)
584 {
585 i915_reg_t fdi_rx_iir;
586 unsigned int index;
587 int ret;
588
589 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
590 index = FDI_RX_CTL_TO_PIPE(offset);
591 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
592 index = FDI_TX_CTL_TO_PIPE(offset);
593 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
594 index = FDI_RX_IMR_TO_PIPE(offset);
595 else {
596 gvt_vgpu_err("Unsupport registers %x\n", offset);
597 return -EINVAL;
598 }
599
600 write_vreg(vgpu, offset, p_data, bytes);
601
602 fdi_rx_iir = FDI_RX_IIR(index);
603
604 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
605 if (ret < 0)
606 return ret;
607 if (ret)
608 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
609
610 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
611 if (ret < 0)
612 return ret;
613 if (ret)
614 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
615
616 if (offset == _FDI_RXA_CTL)
617 if (fdi_auto_training_started(vgpu))
618 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |=
619 DP_TP_STATUS_AUTOTRAIN_DONE;
620 return 0;
621 }
622
623 #define DP_TP_CTL_TO_PORT(offset) \
624 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
625
626 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
627 void *p_data, unsigned int bytes)
628 {
629 i915_reg_t status_reg;
630 unsigned int index;
631 u32 data;
632
633 write_vreg(vgpu, offset, p_data, bytes);
634
635 index = DP_TP_CTL_TO_PORT(offset);
636 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
637 if (data == 0x2) {
638 status_reg = DP_TP_STATUS(index);
639 vgpu_vreg(vgpu, status_reg) |= (1 << 25);
640 }
641 return 0;
642 }
643
644 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
645 unsigned int offset, void *p_data, unsigned int bytes)
646 {
647 u32 reg_val;
648 u32 sticky_mask;
649
650 reg_val = *((u32 *)p_data);
651 sticky_mask = GENMASK(27, 26) | (1 << 24);
652
653 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
654 (vgpu_vreg(vgpu, offset) & sticky_mask);
655 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
656 return 0;
657 }
658
659 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
660 unsigned int offset, void *p_data, unsigned int bytes)
661 {
662 u32 data;
663
664 write_vreg(vgpu, offset, p_data, bytes);
665 data = vgpu_vreg(vgpu, offset);
666
667 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
668 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
669 return 0;
670 }
671
672 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
673 unsigned int offset, void *p_data, unsigned int bytes)
674 {
675 u32 data;
676
677 write_vreg(vgpu, offset, p_data, bytes);
678 data = vgpu_vreg(vgpu, offset);
679
680 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
681 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
682 else
683 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
684 return 0;
685 }
686
687 #define DSPSURF_TO_PIPE(offset) \
688 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
689
690 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
691 void *p_data, unsigned int bytes)
692 {
693 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
694 unsigned int index = DSPSURF_TO_PIPE(offset);
695 i915_reg_t surflive_reg = DSPSURFLIVE(index);
696 int flip_event[] = {
697 [PIPE_A] = PRIMARY_A_FLIP_DONE,
698 [PIPE_B] = PRIMARY_B_FLIP_DONE,
699 [PIPE_C] = PRIMARY_C_FLIP_DONE,
700 };
701
702 write_vreg(vgpu, offset, p_data, bytes);
703 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
704
705 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
706 return 0;
707 }
708
709 #define SPRSURF_TO_PIPE(offset) \
710 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
711
712 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
713 void *p_data, unsigned int bytes)
714 {
715 unsigned int index = SPRSURF_TO_PIPE(offset);
716 i915_reg_t surflive_reg = SPRSURFLIVE(index);
717 int flip_event[] = {
718 [PIPE_A] = SPRITE_A_FLIP_DONE,
719 [PIPE_B] = SPRITE_B_FLIP_DONE,
720 [PIPE_C] = SPRITE_C_FLIP_DONE,
721 };
722
723 write_vreg(vgpu, offset, p_data, bytes);
724 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
725
726 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
727 return 0;
728 }
729
730 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
731 unsigned int reg)
732 {
733 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
734 enum intel_gvt_event_type event;
735
736 if (reg == _DPA_AUX_CH_CTL)
737 event = AUX_CHANNEL_A;
738 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
739 event = AUX_CHANNEL_B;
740 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
741 event = AUX_CHANNEL_C;
742 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
743 event = AUX_CHANNEL_D;
744 else {
745 WARN_ON(true);
746 return -EINVAL;
747 }
748
749 intel_vgpu_trigger_virtual_event(vgpu, event);
750 return 0;
751 }
752
753 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
754 unsigned int reg, int len, bool data_valid)
755 {
756 /* mark transaction done */
757 value |= DP_AUX_CH_CTL_DONE;
758 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
759 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
760
761 if (data_valid)
762 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
763 else
764 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
765
766 /* message size */
767 value &= ~(0xf << 20);
768 value |= (len << 20);
769 vgpu_vreg(vgpu, reg) = value;
770
771 if (value & DP_AUX_CH_CTL_INTERRUPT)
772 return trigger_aux_channel_interrupt(vgpu, reg);
773 return 0;
774 }
775
776 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
777 uint8_t t)
778 {
779 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
780 /* training pattern 1 for CR */
781 /* set LANE0_CR_DONE, LANE1_CR_DONE */
782 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
783 /* set LANE2_CR_DONE, LANE3_CR_DONE */
784 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
785 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
786 DPCD_TRAINING_PATTERN_2) {
787 /* training pattern 2 for EQ */
788 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
789 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
790 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
791 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
792 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
793 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
794 /* set INTERLANE_ALIGN_DONE */
795 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
796 DPCD_INTERLANE_ALIGN_DONE;
797 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
798 DPCD_LINK_TRAINING_DISABLED) {
799 /* finish link training */
800 /* set sink status as synchronized */
801 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
802 }
803 }
804
805 #define _REG_HSW_DP_AUX_CH_CTL(dp) \
806 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
807
808 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
809
810 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
811
812 #define dpy_is_valid_port(port) \
813 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
814
815 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
816 unsigned int offset, void *p_data, unsigned int bytes)
817 {
818 struct intel_vgpu_display *display = &vgpu->display;
819 int msg, addr, ctrl, op, len;
820 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
821 struct intel_vgpu_dpcd_data *dpcd = NULL;
822 struct intel_vgpu_port *port = NULL;
823 u32 data;
824
825 if (!dpy_is_valid_port(port_index)) {
826 gvt_vgpu_err("Unsupported DP port access!\n");
827 return 0;
828 }
829
830 write_vreg(vgpu, offset, p_data, bytes);
831 data = vgpu_vreg(vgpu, offset);
832
833 if ((IS_SKYLAKE(vgpu->gvt->dev_priv)
834 || IS_KABYLAKE(vgpu->gvt->dev_priv))
835 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
836 /* SKL DPB/C/D aux ctl register changed */
837 return 0;
838 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
839 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
840 /* write to the data registers */
841 return 0;
842 }
843
844 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
845 /* just want to clear the sticky bits */
846 vgpu_vreg(vgpu, offset) = 0;
847 return 0;
848 }
849
850 port = &display->ports[port_index];
851 dpcd = port->dpcd;
852
853 /* read out message from DATA1 register */
854 msg = vgpu_vreg(vgpu, offset + 4);
855 addr = (msg >> 8) & 0xffff;
856 ctrl = (msg >> 24) & 0xff;
857 len = msg & 0xff;
858 op = ctrl >> 4;
859
860 if (op == GVT_AUX_NATIVE_WRITE) {
861 int t;
862 uint8_t buf[16];
863
864 if ((addr + len + 1) >= DPCD_SIZE) {
865 /*
866 * Write request exceeds what we supported,
867 * DCPD spec: When a Source Device is writing a DPCD
868 * address not supported by the Sink Device, the Sink
869 * Device shall reply with AUX NACK and “M” equal to
870 * zero.
871 */
872
873 /* NAK the write */
874 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
875 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
876 return 0;
877 }
878
879 /*
880 * Write request format: (command + address) occupies
881 * 3 bytes, followed by (len + 1) bytes of data.
882 */
883 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
884 return -EINVAL;
885
886 /* unpack data from vreg to buf */
887 for (t = 0; t < 4; t++) {
888 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
889
890 buf[t * 4] = (r >> 24) & 0xff;
891 buf[t * 4 + 1] = (r >> 16) & 0xff;
892 buf[t * 4 + 2] = (r >> 8) & 0xff;
893 buf[t * 4 + 3] = r & 0xff;
894 }
895
896 /* write to virtual DPCD */
897 if (dpcd && dpcd->data_valid) {
898 for (t = 0; t <= len; t++) {
899 int p = addr + t;
900
901 dpcd->data[p] = buf[t];
902 /* check for link training */
903 if (p == DPCD_TRAINING_PATTERN_SET)
904 dp_aux_ch_ctl_link_training(dpcd,
905 buf[t]);
906 }
907 }
908
909 /* ACK the write */
910 vgpu_vreg(vgpu, offset + 4) = 0;
911 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
912 dpcd && dpcd->data_valid);
913 return 0;
914 }
915
916 if (op == GVT_AUX_NATIVE_READ) {
917 int idx, i, ret = 0;
918
919 if ((addr + len + 1) >= DPCD_SIZE) {
920 /*
921 * read request exceeds what we supported
922 * DPCD spec: A Sink Device receiving a Native AUX CH
923 * read request for an unsupported DPCD address must
924 * reply with an AUX ACK and read data set equal to
925 * zero instead of replying with AUX NACK.
926 */
927
928 /* ACK the READ*/
929 vgpu_vreg(vgpu, offset + 4) = 0;
930 vgpu_vreg(vgpu, offset + 8) = 0;
931 vgpu_vreg(vgpu, offset + 12) = 0;
932 vgpu_vreg(vgpu, offset + 16) = 0;
933 vgpu_vreg(vgpu, offset + 20) = 0;
934
935 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
936 true);
937 return 0;
938 }
939
940 for (idx = 1; idx <= 5; idx++) {
941 /* clear the data registers */
942 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
943 }
944
945 /*
946 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
947 */
948 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
949 return -EINVAL;
950
951 /* read from virtual DPCD to vreg */
952 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
953 if (dpcd && dpcd->data_valid) {
954 for (i = 1; i <= (len + 1); i++) {
955 int t;
956
957 t = dpcd->data[addr + i - 1];
958 t <<= (24 - 8 * (i % 4));
959 ret |= t;
960
961 if ((i % 4 == 3) || (i == (len + 1))) {
962 vgpu_vreg(vgpu, offset +
963 (i / 4 + 1) * 4) = ret;
964 ret = 0;
965 }
966 }
967 }
968 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
969 dpcd && dpcd->data_valid);
970 return 0;
971 }
972
973 /* i2c transaction starts */
974 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
975
976 if (data & DP_AUX_CH_CTL_INTERRUPT)
977 trigger_aux_channel_interrupt(vgpu, offset);
978 return 0;
979 }
980
981 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
982 void *p_data, unsigned int bytes)
983 {
984 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
985 write_vreg(vgpu, offset, p_data, bytes);
986 return 0;
987 }
988
989 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
990 void *p_data, unsigned int bytes)
991 {
992 bool vga_disable;
993
994 write_vreg(vgpu, offset, p_data, bytes);
995 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
996
997 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
998 vga_disable ? "Disable" : "Enable");
999 return 0;
1000 }
1001
1002 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1003 unsigned int sbi_offset)
1004 {
1005 struct intel_vgpu_display *display = &vgpu->display;
1006 int num = display->sbi.number;
1007 int i;
1008
1009 for (i = 0; i < num; ++i)
1010 if (display->sbi.registers[i].offset == sbi_offset)
1011 break;
1012
1013 if (i == num)
1014 return 0;
1015
1016 return display->sbi.registers[i].value;
1017 }
1018
1019 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1020 unsigned int offset, u32 value)
1021 {
1022 struct intel_vgpu_display *display = &vgpu->display;
1023 int num = display->sbi.number;
1024 int i;
1025
1026 for (i = 0; i < num; ++i) {
1027 if (display->sbi.registers[i].offset == offset)
1028 break;
1029 }
1030
1031 if (i == num) {
1032 if (num == SBI_REG_MAX) {
1033 gvt_vgpu_err("SBI caching meets maximum limits\n");
1034 return;
1035 }
1036 display->sbi.number++;
1037 }
1038
1039 display->sbi.registers[i].offset = offset;
1040 display->sbi.registers[i].value = value;
1041 }
1042
1043 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1044 void *p_data, unsigned int bytes)
1045 {
1046 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1047 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1048 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1049 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1050 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1051 sbi_offset);
1052 }
1053 read_vreg(vgpu, offset, p_data, bytes);
1054 return 0;
1055 }
1056
1057 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1058 void *p_data, unsigned int bytes)
1059 {
1060 u32 data;
1061
1062 write_vreg(vgpu, offset, p_data, bytes);
1063 data = vgpu_vreg(vgpu, offset);
1064
1065 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1066 data |= SBI_READY;
1067
1068 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1069 data |= SBI_RESPONSE_SUCCESS;
1070
1071 vgpu_vreg(vgpu, offset) = data;
1072
1073 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1074 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1075 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1076 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1077
1078 write_virtual_sbi_register(vgpu, sbi_offset,
1079 vgpu_vreg(vgpu, SBI_DATA));
1080 }
1081 return 0;
1082 }
1083
1084 #define _vgtif_reg(x) \
1085 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1086
1087 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1088 void *p_data, unsigned int bytes)
1089 {
1090 bool invalid_read = false;
1091
1092 read_vreg(vgpu, offset, p_data, bytes);
1093
1094 switch (offset) {
1095 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1096 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1097 invalid_read = true;
1098 break;
1099 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1100 _vgtif_reg(avail_rs.fence_num):
1101 if (offset + bytes >
1102 _vgtif_reg(avail_rs.fence_num) + 4)
1103 invalid_read = true;
1104 break;
1105 case 0x78010: /* vgt_caps */
1106 case 0x7881c:
1107 break;
1108 default:
1109 invalid_read = true;
1110 break;
1111 }
1112 if (invalid_read)
1113 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1114 offset, bytes, *(u32 *)p_data);
1115 vgpu->pv_notified = true;
1116 return 0;
1117 }
1118
1119 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1120 {
1121 int ret = 0;
1122
1123 switch (notification) {
1124 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1125 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3);
1126 break;
1127 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1128 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3);
1129 break;
1130 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1131 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4);
1132 break;
1133 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1134 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4);
1135 break;
1136 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1137 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1138 case 1: /* Remove this in guest driver. */
1139 break;
1140 default:
1141 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1142 }
1143 return ret;
1144 }
1145
1146 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1147 {
1148 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1149 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1150 char *env[3] = {NULL, NULL, NULL};
1151 char vmid_str[20];
1152 char display_ready_str[20];
1153
1154 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1155 env[0] = display_ready_str;
1156
1157 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1158 env[1] = vmid_str;
1159
1160 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1161 }
1162
1163 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1164 void *p_data, unsigned int bytes)
1165 {
1166 u32 data;
1167 int ret;
1168
1169 write_vreg(vgpu, offset, p_data, bytes);
1170 data = vgpu_vreg(vgpu, offset);
1171
1172 switch (offset) {
1173 case _vgtif_reg(display_ready):
1174 send_display_ready_uevent(vgpu, data ? 1 : 0);
1175 break;
1176 case _vgtif_reg(g2v_notify):
1177 ret = handle_g2v_notification(vgpu, data);
1178 break;
1179 /* add xhot and yhot to handled list to avoid error log */
1180 case 0x78830:
1181 case 0x78834:
1182 case _vgtif_reg(pdp[0].lo):
1183 case _vgtif_reg(pdp[0].hi):
1184 case _vgtif_reg(pdp[1].lo):
1185 case _vgtif_reg(pdp[1].hi):
1186 case _vgtif_reg(pdp[2].lo):
1187 case _vgtif_reg(pdp[2].hi):
1188 case _vgtif_reg(pdp[3].lo):
1189 case _vgtif_reg(pdp[3].hi):
1190 case _vgtif_reg(execlist_context_descriptor_lo):
1191 case _vgtif_reg(execlist_context_descriptor_hi):
1192 break;
1193 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1194 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1195 break;
1196 default:
1197 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1198 offset, bytes, data);
1199 break;
1200 }
1201 return 0;
1202 }
1203
1204 static int pf_write(struct intel_vgpu *vgpu,
1205 unsigned int offset, void *p_data, unsigned int bytes)
1206 {
1207 u32 val = *(u32 *)p_data;
1208
1209 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1210 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1211 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1212 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1213 vgpu->id);
1214 return 0;
1215 }
1216
1217 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1218 }
1219
1220 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1221 unsigned int offset, void *p_data, unsigned int bytes)
1222 {
1223 write_vreg(vgpu, offset, p_data, bytes);
1224
1225 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST)
1226 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED;
1227 else
1228 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED;
1229 return 0;
1230 }
1231
1232 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1233 unsigned int offset, void *p_data, unsigned int bytes)
1234 {
1235 write_vreg(vgpu, offset, p_data, bytes);
1236
1237 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1238 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1239 return 0;
1240 }
1241
1242 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1243 void *p_data, unsigned int bytes)
1244 {
1245 u32 mode;
1246
1247 write_vreg(vgpu, offset, p_data, bytes);
1248 mode = vgpu_vreg(vgpu, offset);
1249
1250 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1251 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
1252 vgpu->id);
1253 return 0;
1254 }
1255
1256 return 0;
1257 }
1258
1259 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1260 void *p_data, unsigned int bytes)
1261 {
1262 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1263 u32 trtte = *(u32 *)p_data;
1264
1265 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1266 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1267 vgpu->id);
1268 return -EINVAL;
1269 }
1270 write_vreg(vgpu, offset, p_data, bytes);
1271 /* TRTTE is not per-context */
1272
1273 mmio_hw_access_pre(dev_priv);
1274 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
1275 mmio_hw_access_post(dev_priv);
1276
1277 return 0;
1278 }
1279
1280 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1281 void *p_data, unsigned int bytes)
1282 {
1283 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1284 u32 val = *(u32 *)p_data;
1285
1286 if (val & 1) {
1287 /* unblock hw logic */
1288 mmio_hw_access_pre(dev_priv);
1289 I915_WRITE(_MMIO(offset), val);
1290 mmio_hw_access_post(dev_priv);
1291 }
1292 write_vreg(vgpu, offset, p_data, bytes);
1293 return 0;
1294 }
1295
1296 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1297 void *p_data, unsigned int bytes)
1298 {
1299 u32 v = 0;
1300
1301 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1302 v |= (1 << 0);
1303
1304 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1305 v |= (1 << 8);
1306
1307 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1308 v |= (1 << 16);
1309
1310 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1311 v |= (1 << 24);
1312
1313 vgpu_vreg(vgpu, offset) = v;
1314
1315 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1316 }
1317
1318 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1319 void *p_data, unsigned int bytes)
1320 {
1321 u32 value = *(u32 *)p_data;
1322 u32 cmd = value & 0xff;
1323 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
1324
1325 switch (cmd) {
1326 case GEN9_PCODE_READ_MEM_LATENCY:
1327 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1328 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
1329 /**
1330 * "Read memory latency" command on gen9.
1331 * Below memory latency values are read
1332 * from skylake platform.
1333 */
1334 if (!*data0)
1335 *data0 = 0x1e1a1100;
1336 else
1337 *data0 = 0x61514b3d;
1338 }
1339 break;
1340 case SKL_PCODE_CDCLK_CONTROL:
1341 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1342 || IS_KABYLAKE(vgpu->gvt->dev_priv))
1343 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1344 break;
1345 case GEN6_PCODE_READ_RC6VIDS:
1346 *data0 |= 0x1;
1347 break;
1348 }
1349
1350 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1351 vgpu->id, value, *data0);
1352 /**
1353 * PCODE_READY clear means ready for pcode read/write,
1354 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1355 * always emulate as pcode read/write success and ready for access
1356 * anytime, since we don't touch real physical registers here.
1357 */
1358 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1359 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1360 }
1361
1362 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1363 unsigned int offset, void *p_data, unsigned int bytes)
1364 {
1365 u32 v = *(u32 *)p_data;
1366
1367 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1368 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1369 v |= (v >> 1);
1370
1371 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1372 }
1373
1374 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1375 void *p_data, unsigned int bytes)
1376 {
1377 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1378 u32 v = *(u32 *)p_data;
1379
1380 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
1381 return intel_vgpu_default_mmio_write(vgpu,
1382 offset, p_data, bytes);
1383
1384 switch (offset) {
1385 case 0x4ddc:
1386 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1387 vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
1388 break;
1389 case 0x42080:
1390 /* bypass WaCompressedResourceDisplayNewHashMode */
1391 vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
1392 break;
1393 case 0xe194:
1394 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1395 vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
1396 break;
1397 case 0x7014:
1398 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1399 vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
1400 break;
1401 default:
1402 return -EINVAL;
1403 }
1404
1405 return 0;
1406 }
1407
1408 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1409 void *p_data, unsigned int bytes)
1410 {
1411 u32 v = *(u32 *)p_data;
1412
1413 /* other bits are MBZ. */
1414 v &= (1 << 31) | (1 << 30);
1415 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1416
1417 vgpu_vreg(vgpu, offset) = v;
1418
1419 return 0;
1420 }
1421
1422 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
1423 unsigned int offset, void *p_data, unsigned int bytes)
1424 {
1425 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1426
1427 mmio_hw_access_pre(dev_priv);
1428 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1429 mmio_hw_access_post(dev_priv);
1430 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1431 }
1432
1433 static int instdone_mmio_read(struct intel_vgpu *vgpu,
1434 unsigned int offset, void *p_data, unsigned int bytes)
1435 {
1436 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1437
1438 mmio_hw_access_pre(dev_priv);
1439 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1440 mmio_hw_access_post(dev_priv);
1441 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1442 }
1443
1444 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1445 void *p_data, unsigned int bytes)
1446 {
1447 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1448 struct intel_vgpu_execlist *execlist;
1449 u32 data = *(u32 *)p_data;
1450 int ret = 0;
1451
1452 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
1453 return -EINVAL;
1454
1455 execlist = &vgpu->execlist[ring_id];
1456
1457 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data;
1458 if (execlist->elsp_dwords.index == 3) {
1459 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
1460 if(ret)
1461 gvt_vgpu_err("fail submit workload on ring %d\n",
1462 ring_id);
1463 }
1464
1465 ++execlist->elsp_dwords.index;
1466 execlist->elsp_dwords.index &= 0x3;
1467 return ret;
1468 }
1469
1470 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1471 void *p_data, unsigned int bytes)
1472 {
1473 u32 data = *(u32 *)p_data;
1474 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1475 bool enable_execlist;
1476
1477 write_vreg(vgpu, offset, p_data, bytes);
1478
1479 /* when PPGTT mode enabled, we will check if guest has called
1480 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1481 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1482 */
1483 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1484 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1485 && !vgpu->pv_notified) {
1486 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1487 return 0;
1488 }
1489 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1490 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1491 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1492
1493 gvt_dbg_core("EXECLIST %s on ring %d\n",
1494 (enable_execlist ? "enabling" : "disabling"),
1495 ring_id);
1496
1497 if (enable_execlist)
1498 intel_vgpu_start_schedule(vgpu);
1499 }
1500 return 0;
1501 }
1502
1503 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1504 unsigned int offset, void *p_data, unsigned int bytes)
1505 {
1506 unsigned int id = 0;
1507
1508 write_vreg(vgpu, offset, p_data, bytes);
1509 vgpu_vreg(vgpu, offset) = 0;
1510
1511 switch (offset) {
1512 case 0x4260:
1513 id = RCS;
1514 break;
1515 case 0x4264:
1516 id = VCS;
1517 break;
1518 case 0x4268:
1519 id = VCS2;
1520 break;
1521 case 0x426c:
1522 id = BCS;
1523 break;
1524 case 0x4270:
1525 id = VECS;
1526 break;
1527 default:
1528 return -EINVAL;
1529 }
1530 set_bit(id, (void *)vgpu->tlb_handle_pending);
1531
1532 return 0;
1533 }
1534
1535 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1536 unsigned int offset, void *p_data, unsigned int bytes)
1537 {
1538 u32 data;
1539
1540 write_vreg(vgpu, offset, p_data, bytes);
1541 data = vgpu_vreg(vgpu, offset);
1542
1543 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1544 data |= RESET_CTL_READY_TO_RESET;
1545 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1546 data &= ~RESET_CTL_READY_TO_RESET;
1547
1548 vgpu_vreg(vgpu, offset) = data;
1549 return 0;
1550 }
1551
1552 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1553 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
1554 f, s, am, rm, d, r, w); \
1555 if (ret) \
1556 return ret; \
1557 } while (0)
1558
1559 #define MMIO_D(reg, d) \
1560 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1561
1562 #define MMIO_DH(reg, d, r, w) \
1563 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1564
1565 #define MMIO_DFH(reg, d, f, r, w) \
1566 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1567
1568 #define MMIO_GM(reg, d, r, w) \
1569 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1570
1571 #define MMIO_GM_RDR(reg, d, r, w) \
1572 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1573
1574 #define MMIO_RO(reg, d, f, rm, r, w) \
1575 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1576
1577 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1578 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1579 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1580 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1581 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1582 } while (0)
1583
1584 #define MMIO_RING_D(prefix, d) \
1585 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1586
1587 #define MMIO_RING_DFH(prefix, d, f, r, w) \
1588 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1589
1590 #define MMIO_RING_GM(prefix, d, r, w) \
1591 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1592
1593 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
1594 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1595
1596 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1597 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1598
1599 static int init_generic_mmio_info(struct intel_gvt *gvt)
1600 {
1601 struct drm_i915_private *dev_priv = gvt->dev_priv;
1602 int ret;
1603
1604 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1605 intel_vgpu_reg_imr_handler);
1606
1607 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1608 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1609 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1610 MMIO_D(SDEISR, D_ALL);
1611
1612 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
1613
1614 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1615 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1616 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1617 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1618
1619 #define RING_REG(base) (base + 0x28)
1620 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1621 #undef RING_REG
1622
1623 #define RING_REG(base) (base + 0x134)
1624 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1625 #undef RING_REG
1626
1627 #define RING_REG(base) (base + 0x6c)
1628 MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL);
1629 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL);
1630 #undef RING_REG
1631 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL);
1632
1633 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
1634 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1635 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL);
1636 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1637
1638 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1639 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1640 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1641 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1642 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1643
1644 /* RING MODE */
1645 #define RING_REG(base) (base + 0x29c)
1646 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1647 ring_mode_mmio_write);
1648 #undef RING_REG
1649
1650 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1651 NULL, NULL);
1652 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1653 NULL, NULL);
1654 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1655 ring_timestamp_mmio_read, NULL);
1656 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1657 ring_timestamp_mmio_read, NULL);
1658
1659 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1660 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1661 NULL, NULL);
1662 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1663 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1664 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1665
1666 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1667 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1668 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1669 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1670 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1671 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1672 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1673 NULL, NULL);
1674 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1675 skl_misc_ctl_write);
1676 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
1677 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
1678 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
1679 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL);
1680 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL);
1681 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL);
1682 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL);
1683 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1684 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1685 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1686
1687 /* display */
1688 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1689 MMIO_D(0x602a0, D_ALL);
1690
1691 MMIO_D(0x65050, D_ALL);
1692 MMIO_D(0x650b4, D_ALL);
1693
1694 MMIO_D(0xc4040, D_ALL);
1695 MMIO_D(DERRMR, D_ALL);
1696
1697 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1698 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1699 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1700 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1701
1702 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1703 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1704 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1705 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
1706
1707 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1708 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1709 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1710 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1711
1712 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1713 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1714 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1715 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1716
1717 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1718 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1719 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1720 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1721
1722 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1723 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1724 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1725
1726 MMIO_D(CURPOS(PIPE_A), D_ALL);
1727 MMIO_D(CURPOS(PIPE_B), D_ALL);
1728 MMIO_D(CURPOS(PIPE_C), D_ALL);
1729
1730 MMIO_D(CURBASE(PIPE_A), D_ALL);
1731 MMIO_D(CURBASE(PIPE_B), D_ALL);
1732 MMIO_D(CURBASE(PIPE_C), D_ALL);
1733
1734 MMIO_D(0x700ac, D_ALL);
1735 MMIO_D(0x710ac, D_ALL);
1736 MMIO_D(0x720ac, D_ALL);
1737
1738 MMIO_D(0x70090, D_ALL);
1739 MMIO_D(0x70094, D_ALL);
1740 MMIO_D(0x70098, D_ALL);
1741 MMIO_D(0x7009c, D_ALL);
1742
1743 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1744 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1745 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1746 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1747 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
1748 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
1749 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1750 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1751
1752 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1753 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1754 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1755 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1756 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
1757 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
1758 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1759 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1760
1761 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1762 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1763 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1764 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1765 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
1766 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
1767 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1768 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1769
1770 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1771 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1772 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1773 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1774 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1775 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1776 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
1777 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
1778 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1779 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1780 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1781 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1782
1783 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1784 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1785 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1786 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1787 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1788 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1789 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
1790 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
1791 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1792 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1793 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1794 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1795
1796 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1797 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1798 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1799 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1800 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1801 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1802 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
1803 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
1804 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1805 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1806 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1807 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1808
1809 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
1810 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
1811 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
1812 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
1813 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
1814 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
1815 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
1816 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
1817 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
1818
1819 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
1820 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
1821 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
1822 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
1823 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
1824 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
1825 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
1826 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
1827 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
1828
1829 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
1830 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
1831 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
1832 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
1833 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
1834 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
1835 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
1836 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
1837 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
1838
1839 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
1840 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
1841 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
1842 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
1843 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
1844 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
1845 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
1846 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
1847
1848 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
1849 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
1850 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
1851 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
1852 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
1853 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
1854 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
1855 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
1856
1857 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
1858 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
1859 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
1860 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
1861 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
1862 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
1863 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
1864 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
1865
1866 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
1867 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
1868 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
1869 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
1870 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
1871 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
1872 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
1873 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
1874
1875 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
1876 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
1877 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
1878 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
1879 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
1880 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
1881 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
1882 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
1883
1884 MMIO_D(PF_CTL(PIPE_A), D_ALL);
1885 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
1886 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
1887 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
1888 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
1889
1890 MMIO_D(PF_CTL(PIPE_B), D_ALL);
1891 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
1892 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
1893 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
1894 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
1895
1896 MMIO_D(PF_CTL(PIPE_C), D_ALL);
1897 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
1898 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
1899 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
1900 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
1901
1902 MMIO_D(WM0_PIPEA_ILK, D_ALL);
1903 MMIO_D(WM0_PIPEB_ILK, D_ALL);
1904 MMIO_D(WM0_PIPEC_IVB, D_ALL);
1905 MMIO_D(WM1_LP_ILK, D_ALL);
1906 MMIO_D(WM2_LP_ILK, D_ALL);
1907 MMIO_D(WM3_LP_ILK, D_ALL);
1908 MMIO_D(WM1S_LP_ILK, D_ALL);
1909 MMIO_D(WM2S_LP_IVB, D_ALL);
1910 MMIO_D(WM3S_LP_IVB, D_ALL);
1911
1912 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1913 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1914 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1915 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1916
1917 MMIO_D(0x48268, D_ALL);
1918
1919 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1920 gmbus_mmio_write);
1921 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
1922 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1923
1924 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1925 dp_aux_ch_ctl_mmio_write);
1926 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1927 dp_aux_ch_ctl_mmio_write);
1928 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1929 dp_aux_ch_ctl_mmio_write);
1930
1931 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
1932
1933 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1934 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
1935
1936 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1937 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1938 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1939 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1940 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1941 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1942 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1943 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1944 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1945
1946 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
1947 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
1948 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
1949 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
1950 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
1951 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
1952 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);
1953
1954 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL);
1955 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL);
1956 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL);
1957 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL);
1958 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL);
1959 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL);
1960 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL);
1961
1962 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL);
1963 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL);
1964 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL);
1965 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL);
1966 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL);
1967 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL);
1968 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL);
1969 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL);
1970
1971 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
1972 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
1973 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
1974
1975 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
1976 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
1977 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
1978
1979 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
1980 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
1981 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
1982
1983 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
1984 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
1985 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
1986
1987 MMIO_D(_FDI_RXA_MISC, D_ALL);
1988 MMIO_D(_FDI_RXB_MISC, D_ALL);
1989 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
1990 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
1991 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
1992 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
1993
1994 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
1995 MMIO_D(PCH_PP_DIVISOR, D_ALL);
1996 MMIO_D(PCH_PP_STATUS, D_ALL);
1997 MMIO_D(PCH_LVDS, D_ALL);
1998 MMIO_D(_PCH_DPLL_A, D_ALL);
1999 MMIO_D(_PCH_DPLL_B, D_ALL);
2000 MMIO_D(_PCH_FPA0, D_ALL);
2001 MMIO_D(_PCH_FPA1, D_ALL);
2002 MMIO_D(_PCH_FPB0, D_ALL);
2003 MMIO_D(_PCH_FPB1, D_ALL);
2004 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2005 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2006 MMIO_D(PCH_DPLL_SEL, D_ALL);
2007
2008 MMIO_D(0x61208, D_ALL);
2009 MMIO_D(0x6120c, D_ALL);
2010 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2011 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2012
2013 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL);
2014 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
2015 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
2016 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
2017 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL);
2018 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL);
2019
2020 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2021 PORTA_HOTPLUG_STATUS_MASK
2022 | PORTB_HOTPLUG_STATUS_MASK
2023 | PORTC_HOTPLUG_STATUS_MASK
2024 | PORTD_HOTPLUG_STATUS_MASK,
2025 NULL, NULL);
2026
2027 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2028 MMIO_D(FUSE_STRAP, D_ALL);
2029 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2030
2031 MMIO_D(DISP_ARB_CTL, D_ALL);
2032 MMIO_D(DISP_ARB_CTL2, D_ALL);
2033
2034 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2035 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2036 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2037
2038 MMIO_D(SOUTH_CHICKEN1, D_ALL);
2039 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2040 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
2041 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
2042 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2043 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
2044 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
2045
2046 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2047 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2048 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2049 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2050 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2051 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2052 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2053
2054 MMIO_D(IPS_CTL, D_ALL);
2055
2056 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2057 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2058 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2059 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2060 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2061 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2062 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2063 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2064 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2065 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2066 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2067 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2068 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2069
2070 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2071 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2072 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2073 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2074 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2075 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2076 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2077 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2078 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2079 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2080 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2081 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2082 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2083
2084 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2085 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2086 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2087 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2088 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2089 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2090 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2091 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2092 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2093 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2094 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2095 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2096 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2097
2098 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2099 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2100 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2101
2102 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2103 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2104 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2105
2106 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2107 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2108 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2109
2110 MMIO_D(0x60110, D_ALL);
2111 MMIO_D(0x61110, D_ALL);
2112 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2113 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2114 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2115 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2116 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2117 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2118 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2119 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2120 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2121
2122 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2123 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2124 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2125 MMIO_D(SPLL_CTL, D_ALL);
2126 MMIO_D(_WRPLL_CTL1, D_ALL);
2127 MMIO_D(_WRPLL_CTL2, D_ALL);
2128 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2129 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2130 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2131 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2132 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2133 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2134 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2135 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2136
2137 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2138 MMIO_D(0x46508, D_ALL);
2139
2140 MMIO_D(0x49080, D_ALL);
2141 MMIO_D(0x49180, D_ALL);
2142 MMIO_D(0x49280, D_ALL);
2143
2144 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2145 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2146 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2147
2148 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2149 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2150 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2151
2152 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2153 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2154 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2155
2156 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2157 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2158 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2159
2160 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2161 MMIO_D(SBI_ADDR, D_ALL);
2162 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2163 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2164 MMIO_D(PIXCLK_GATE, D_ALL);
2165
2166 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL,
2167 dp_aux_ch_ctl_mmio_write);
2168
2169 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2170 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2171 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2172 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2173 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2174
2175 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2176 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2177 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2178 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2179 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2180
2181 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2182 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2183 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2184 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2185 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2186
2187 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2188 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2189 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2190 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2191 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2192
2193 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2194 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2195
2196 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL);
2197 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL);
2198 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL);
2199 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL);
2200
2201 MMIO_D(_TRANSA_MSA_MISC, D_ALL);
2202 MMIO_D(_TRANSB_MSA_MISC, D_ALL);
2203 MMIO_D(_TRANSC_MSA_MISC, D_ALL);
2204 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL);
2205
2206 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2207 MMIO_D(FORCEWAKE_ACK, D_ALL);
2208 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2209 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2210 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2211 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2212 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2213 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2214 MMIO_D(ECOBUS, D_ALL);
2215 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2216 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2217 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2218 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2219 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2220 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2221 MMIO_D(GEN6_RPSTAT1, D_ALL);
2222 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2223 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2224 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2225 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2226 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2227 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2228 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2229 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2230 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2231 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2232 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2233 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2234 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2235 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2236 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2237 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2238 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2239 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2240 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2241 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2242 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2243 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2244 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2245 MMIO_DH(HSW_PWR_WELL_BIOS, D_BDW, NULL, power_well_ctl_mmio_write);
2246 MMIO_DH(HSW_PWR_WELL_DRIVER, D_BDW, NULL, power_well_ctl_mmio_write);
2247 MMIO_DH(HSW_PWR_WELL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
2248 MMIO_DH(HSW_PWR_WELL_DEBUG, D_BDW, NULL, power_well_ctl_mmio_write);
2249 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2250 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2251
2252 MMIO_D(RSTDBYCTL, D_ALL);
2253
2254 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2255 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2256 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2257
2258 MMIO_D(TILECTL, D_ALL);
2259
2260 MMIO_D(GEN6_UCGCTL1, D_ALL);
2261 MMIO_D(GEN6_UCGCTL2, D_ALL);
2262
2263 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2264
2265 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2266 MMIO_D(0x13812c, D_ALL);
2267 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2268 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2269 MMIO_D(HSW_IDICR, D_ALL);
2270 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2271
2272 MMIO_D(0x3c, D_ALL);
2273 MMIO_D(0x860, D_ALL);
2274 MMIO_D(ECOSKPD, D_ALL);
2275 MMIO_D(0x121d0, D_ALL);
2276 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2277 MMIO_D(0x41d0, D_ALL);
2278 MMIO_D(GAC_ECO_BITS, D_ALL);
2279 MMIO_D(0x6200, D_ALL);
2280 MMIO_D(0x6204, D_ALL);
2281 MMIO_D(0x6208, D_ALL);
2282 MMIO_D(0x7118, D_ALL);
2283 MMIO_D(0x7180, D_ALL);
2284 MMIO_D(0x7408, D_ALL);
2285 MMIO_D(0x7c00, D_ALL);
2286 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2287 MMIO_D(0x911c, D_ALL);
2288 MMIO_D(0x9120, D_ALL);
2289 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2290
2291 MMIO_D(GAB_CTL, D_ALL);
2292 MMIO_D(0x48800, D_ALL);
2293 MMIO_D(0xce044, D_ALL);
2294 MMIO_D(0xe6500, D_ALL);
2295 MMIO_D(0xe6504, D_ALL);
2296 MMIO_D(0xe6600, D_ALL);
2297 MMIO_D(0xe6604, D_ALL);
2298 MMIO_D(0xe6700, D_ALL);
2299 MMIO_D(0xe6704, D_ALL);
2300 MMIO_D(0xe6800, D_ALL);
2301 MMIO_D(0xe6804, D_ALL);
2302 MMIO_D(PCH_GMBUS4, D_ALL);
2303 MMIO_D(PCH_GMBUS5, D_ALL);
2304
2305 MMIO_D(0x902c, D_ALL);
2306 MMIO_D(0xec008, D_ALL);
2307 MMIO_D(0xec00c, D_ALL);
2308 MMIO_D(0xec008 + 0x18, D_ALL);
2309 MMIO_D(0xec00c + 0x18, D_ALL);
2310 MMIO_D(0xec008 + 0x18 * 2, D_ALL);
2311 MMIO_D(0xec00c + 0x18 * 2, D_ALL);
2312 MMIO_D(0xec008 + 0x18 * 3, D_ALL);
2313 MMIO_D(0xec00c + 0x18 * 3, D_ALL);
2314 MMIO_D(0xec408, D_ALL);
2315 MMIO_D(0xec40c, D_ALL);
2316 MMIO_D(0xec408 + 0x18, D_ALL);
2317 MMIO_D(0xec40c + 0x18, D_ALL);
2318 MMIO_D(0xec408 + 0x18 * 2, D_ALL);
2319 MMIO_D(0xec40c + 0x18 * 2, D_ALL);
2320 MMIO_D(0xec408 + 0x18 * 3, D_ALL);
2321 MMIO_D(0xec40c + 0x18 * 3, D_ALL);
2322 MMIO_D(0xfc810, D_ALL);
2323 MMIO_D(0xfc81c, D_ALL);
2324 MMIO_D(0xfc828, D_ALL);
2325 MMIO_D(0xfc834, D_ALL);
2326 MMIO_D(0xfcc00, D_ALL);
2327 MMIO_D(0xfcc0c, D_ALL);
2328 MMIO_D(0xfcc18, D_ALL);
2329 MMIO_D(0xfcc24, D_ALL);
2330 MMIO_D(0xfd000, D_ALL);
2331 MMIO_D(0xfd00c, D_ALL);
2332 MMIO_D(0xfd018, D_ALL);
2333 MMIO_D(0xfd024, D_ALL);
2334 MMIO_D(0xfd034, D_ALL);
2335
2336 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2337 MMIO_D(0x2054, D_ALL);
2338 MMIO_D(0x12054, D_ALL);
2339 MMIO_D(0x22054, D_ALL);
2340 MMIO_D(0x1a054, D_ALL);
2341
2342 MMIO_D(0x44070, D_ALL);
2343 MMIO_DFH(0x215c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2344 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2345 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2346 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2347 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2348
2349 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2350 MMIO_D(0x2b00, D_BDW_PLUS);
2351 MMIO_D(0x2360, D_BDW_PLUS);
2352 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2353 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2354 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2355
2356 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2357 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2358 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2359
2360 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2361 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2362 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2363 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2364 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2365 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2366 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2367 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2368 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2369 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2370 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2371 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2372 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2373 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2374 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2375 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2376 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2377
2378 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2379 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2380 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2381 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2382 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2383 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2384 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2385 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2386 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2387 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2388 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2389 return 0;
2390 }
2391
2392 static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2393 {
2394 struct drm_i915_private *dev_priv = gvt->dev_priv;
2395 int ret;
2396
2397 MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL,
2398 intel_vgpu_reg_imr_handler);
2399
2400 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2401 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2402 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2403 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2404
2405 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2406 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2407 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2408 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2409
2410 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2411 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2412 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2413 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2414
2415 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2416 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2417 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2418 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2419
2420 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2421 intel_vgpu_reg_imr_handler);
2422 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2423 intel_vgpu_reg_ier_handler);
2424 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2425 intel_vgpu_reg_iir_handler);
2426 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2427
2428 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2429 intel_vgpu_reg_imr_handler);
2430 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2431 intel_vgpu_reg_ier_handler);
2432 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2433 intel_vgpu_reg_iir_handler);
2434 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2435
2436 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2437 intel_vgpu_reg_imr_handler);
2438 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2439 intel_vgpu_reg_ier_handler);
2440 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2441 intel_vgpu_reg_iir_handler);
2442 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2443
2444 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2445 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2446 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2447 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2448
2449 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2450 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2451 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2452 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2453
2454 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2455 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2456 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2457 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2458
2459 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2460 intel_vgpu_reg_master_irq_handler);
2461
2462 MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2463 F_CMD_ACCESS, NULL, NULL);
2464 MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2465
2466 MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2467 NULL, NULL);
2468 MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2469 F_CMD_ACCESS, NULL, NULL);
2470 MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2471 MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2472 NULL, NULL);
2473 MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2474 F_CMD_ACCESS, NULL, NULL);
2475 MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2476 F_CMD_ACCESS, NULL, NULL);
2477 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2478 ring_mode_mmio_write);
2479 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2480 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2481 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2482 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2483 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2484 ring_timestamp_mmio_read, NULL);
2485
2486 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2487
2488 #define RING_REG(base) (base + 0xd0)
2489 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2490 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2491 ring_reset_ctl_write);
2492 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0,
2493 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2494 ring_reset_ctl_write);
2495 #undef RING_REG
2496
2497 #define RING_REG(base) (base + 0x230)
2498 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2499 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);
2500 #undef RING_REG
2501
2502 #define RING_REG(base) (base + 0x234)
2503 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2504 NULL, NULL);
2505 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0,
2506 ~0LL, D_BDW_PLUS, NULL, NULL);
2507 #undef RING_REG
2508
2509 #define RING_REG(base) (base + 0x244)
2510 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2511 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2512 NULL, NULL);
2513 #undef RING_REG
2514
2515 #define RING_REG(base) (base + 0x370)
2516 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2517 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,
2518 NULL, NULL);
2519 #undef RING_REG
2520
2521 #define RING_REG(base) (base + 0x3a0)
2522 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2523 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2524 #undef RING_REG
2525
2526 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2527 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2528 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2529 MMIO_D(0x1c1d0, D_BDW_PLUS);
2530 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2531 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2532 MMIO_D(0x1c054, D_BDW_PLUS);
2533
2534 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2535
2536 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2537 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2538
2539 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2540
2541 #define RING_REG(base) (base + 0x270)
2542 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2543 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2544 #undef RING_REG
2545
2546 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2547 MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2548
2549 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2550
2551 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2552 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2553 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2554
2555 MMIO_D(WM_MISC, D_BDW);
2556 MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
2557
2558 MMIO_D(0x66c00, D_BDW_PLUS);
2559 MMIO_D(0x66c04, D_BDW_PLUS);
2560
2561 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2562
2563 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2564 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2565 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2566
2567 MMIO_D(0xfdc, D_BDW_PLUS);
2568 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2569 NULL, NULL);
2570 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2571 NULL, NULL);
2572 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2573
2574 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL);
2575 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL);
2576 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2577 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL);
2578 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL);
2579 MMIO_D(0xb110, D_BDW);
2580
2581 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2582 NULL, force_nonpriv_write);
2583
2584 MMIO_D(0x22040, D_BDW_PLUS);
2585 MMIO_D(0x44484, D_BDW_PLUS);
2586 MMIO_D(0x4448c, D_BDW_PLUS);
2587
2588 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL);
2589 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2590
2591 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL);
2592
2593 MMIO_D(0x110000, D_BDW_PLUS);
2594
2595 MMIO_D(0x48400, D_BDW_PLUS);
2596
2597 MMIO_D(0x6e570, D_BDW_PLUS);
2598 MMIO_D(0x65f10, D_BDW_PLUS);
2599
2600 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2601 skl_misc_ctl_write);
2602 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2603 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2604 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2605
2606 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);
2607
2608 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2609 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2610 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2611 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2612 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2613 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2614 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2615 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2616 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2617 return 0;
2618 }
2619
2620 static int init_skl_mmio_info(struct intel_gvt *gvt)
2621 {
2622 struct drm_i915_private *dev_priv = gvt->dev_priv;
2623 int ret;
2624
2625 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2626 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2627 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2628 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2629 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2630 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2631
2632 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2633 dp_aux_ch_ctl_mmio_write);
2634 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2635 dp_aux_ch_ctl_mmio_write);
2636 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2637 dp_aux_ch_ctl_mmio_write);
2638
2639 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL_PLUS);
2640 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL_PLUS, NULL,
2641 skl_power_well_ctl_write);
2642 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write);
2643
2644 MMIO_D(0xa210, D_SKL_PLUS);
2645 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2646 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2647 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2648 MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write);
2649 MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write);
2650 MMIO_D(0x45504, D_SKL_PLUS);
2651 MMIO_D(0x45520, D_SKL_PLUS);
2652 MMIO_D(0x46000, D_SKL_PLUS);
2653 MMIO_DH(0x46010, D_SKL | D_KBL, NULL, skl_lcpll_write);
2654 MMIO_DH(0x46014, D_SKL | D_KBL, NULL, skl_lcpll_write);
2655 MMIO_D(0x6C040, D_SKL | D_KBL);
2656 MMIO_D(0x6C048, D_SKL | D_KBL);
2657 MMIO_D(0x6C050, D_SKL | D_KBL);
2658 MMIO_D(0x6C044, D_SKL | D_KBL);
2659 MMIO_D(0x6C04C, D_SKL | D_KBL);
2660 MMIO_D(0x6C054, D_SKL | D_KBL);
2661 MMIO_D(0x6c058, D_SKL | D_KBL);
2662 MMIO_D(0x6c05c, D_SKL | D_KBL);
2663 MMIO_DH(0X6c060, D_SKL | D_KBL, dpll_status_read, NULL);
2664
2665 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2666 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2667 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2668 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2669 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2670 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2671
2672 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2673 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2674 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2675 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2676 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2677 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2678
2679 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2680 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2681 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2682 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2683 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2684 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2685
2686 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2687 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2688 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2689 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2690
2691 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2692 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2693 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2694 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2695
2696 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2697 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2698 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2699 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2700
2701 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2702 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2703 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2704
2705 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2706 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2707 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2708
2709 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2710 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2711 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2712
2713 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2714 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2715 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2716
2717 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2718 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2719 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2720
2721 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2722 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2723 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2724
2725 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2726 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2727 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2728
2729 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2730 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2731 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2732
2733 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2734 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2735 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2736
2737 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2738 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2739 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2740 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2741
2742 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2743 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2744 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2745 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2746
2747 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2748 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2749 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2750 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2751
2752 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2753 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2754 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2755 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL_PLUS, NULL, NULL);
2756
2757 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2758 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2759 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2760 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL_PLUS, NULL, NULL);
2761
2762 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2763 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2764 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2765 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL_PLUS, NULL, NULL);
2766
2767 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2768 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2769 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2770 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL_PLUS, NULL, NULL);
2771
2772 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2773 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2774 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2775 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL_PLUS, NULL, NULL);
2776
2777 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2778 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2779 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2780 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL_PLUS, NULL, NULL);
2781
2782 MMIO_D(0x70380, D_SKL_PLUS);
2783 MMIO_D(0x71380, D_SKL_PLUS);
2784 MMIO_D(0x72380, D_SKL_PLUS);
2785 MMIO_D(0x7039c, D_SKL_PLUS);
2786
2787 MMIO_D(0x8f074, D_SKL | D_KBL);
2788 MMIO_D(0x8f004, D_SKL | D_KBL);
2789 MMIO_D(0x8f034, D_SKL | D_KBL);
2790
2791 MMIO_D(0xb11c, D_SKL | D_KBL);
2792
2793 MMIO_D(0x51000, D_SKL | D_KBL);
2794 MMIO_D(0x6c00c, D_SKL_PLUS);
2795
2796 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2797 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2798
2799 MMIO_D(0xd08, D_SKL_PLUS);
2800 MMIO_DFH(0x20e0, D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
2801 MMIO_DFH(0x20ec, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2802
2803 /* TRTT */
2804 MMIO_DFH(0x4de0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2805 MMIO_DFH(0x4de4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2806 MMIO_DFH(0x4de8, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2807 MMIO_DFH(0x4dec, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2808 MMIO_DFH(0x4df0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2809 MMIO_DFH(0x4df4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write);
2810 MMIO_DH(0x4dfc, D_SKL | D_KBL, NULL, gen9_trtt_chicken_write);
2811
2812 MMIO_D(0x45008, D_SKL | D_KBL);
2813
2814 MMIO_D(0x46430, D_SKL | D_KBL);
2815
2816 MMIO_D(0x46520, D_SKL | D_KBL);
2817
2818 MMIO_D(0xc403c, D_SKL | D_KBL);
2819 MMIO_D(0xb004, D_SKL_PLUS);
2820 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2821
2822 MMIO_D(0x65900, D_SKL_PLUS);
2823 MMIO_D(0x1082c0, D_SKL | D_KBL);
2824 MMIO_D(0x4068, D_SKL | D_KBL);
2825 MMIO_D(0x67054, D_SKL | D_KBL);
2826 MMIO_D(0x6e560, D_SKL | D_KBL);
2827 MMIO_D(0x6e554, D_SKL | D_KBL);
2828 MMIO_D(0x2b20, D_SKL | D_KBL);
2829 MMIO_D(0x65f00, D_SKL | D_KBL);
2830 MMIO_D(0x65f08, D_SKL | D_KBL);
2831 MMIO_D(0x320f0, D_SKL | D_KBL);
2832
2833 MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2834 MMIO_DFH(_REG_VECS_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2835 MMIO_D(0x70034, D_SKL_PLUS);
2836 MMIO_D(0x71034, D_SKL_PLUS);
2837 MMIO_D(0x72034, D_SKL_PLUS);
2838
2839 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL_PLUS);
2840 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL_PLUS);
2841 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL_PLUS);
2842 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL_PLUS);
2843 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS);
2844 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS);
2845
2846 MMIO_D(0x44500, D_SKL_PLUS);
2847 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2848 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
2849 NULL, NULL);
2850
2851 MMIO_D(0x4ab8, D_KBL);
2852 MMIO_D(0x940c, D_SKL_PLUS);
2853 MMIO_D(0x2248, D_SKL_PLUS | D_KBL);
2854 MMIO_D(0x4ab0, D_SKL | D_KBL);
2855 MMIO_D(0x20d4, D_SKL | D_KBL);
2856
2857 return 0;
2858 }
2859
2860 /* Special MMIO blocks. */
2861 static struct gvt_mmio_block {
2862 unsigned int device;
2863 i915_reg_t offset;
2864 unsigned int size;
2865 gvt_mmio_func read;
2866 gvt_mmio_func write;
2867 } gvt_mmio_blocks[] = {
2868 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
2869 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
2870 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
2871 pvinfo_mmio_read, pvinfo_mmio_write},
2872 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
2873 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
2874 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
2875 };
2876
2877 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2878 unsigned int offset)
2879 {
2880 unsigned long device = intel_gvt_get_device_type(gvt);
2881 struct gvt_mmio_block *block = gvt_mmio_blocks;
2882 int i;
2883
2884 for (i = 0; i < ARRAY_SIZE(gvt_mmio_blocks); i++, block++) {
2885 if (!(device & block->device))
2886 continue;
2887 if (offset >= INTEL_GVT_MMIO_OFFSET(block->offset) &&
2888 offset < INTEL_GVT_MMIO_OFFSET(block->offset) + block->size)
2889 return block;
2890 }
2891 return NULL;
2892 }
2893
2894 /**
2895 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2896 * @gvt: GVT device
2897 *
2898 * This function is called at the driver unloading stage, to clean up the MMIO
2899 * information table of GVT device
2900 *
2901 */
2902 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2903 {
2904 struct hlist_node *tmp;
2905 struct intel_gvt_mmio_info *e;
2906 int i;
2907
2908 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2909 kfree(e);
2910
2911 vfree(gvt->mmio.mmio_attribute);
2912 gvt->mmio.mmio_attribute = NULL;
2913 }
2914
2915 /**
2916 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2917 * @gvt: GVT device
2918 *
2919 * This function is called at the initialization stage, to setup the MMIO
2920 * information table for GVT device
2921 *
2922 * Returns:
2923 * zero on success, negative if failed.
2924 */
2925 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2926 {
2927 struct intel_gvt_device_info *info = &gvt->device_info;
2928 struct drm_i915_private *dev_priv = gvt->dev_priv;
2929 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
2930 int ret;
2931
2932 gvt->mmio.mmio_attribute = vzalloc(size);
2933 if (!gvt->mmio.mmio_attribute)
2934 return -ENOMEM;
2935
2936 ret = init_generic_mmio_info(gvt);
2937 if (ret)
2938 goto err;
2939
2940 if (IS_BROADWELL(dev_priv)) {
2941 ret = init_broadwell_mmio_info(gvt);
2942 if (ret)
2943 goto err;
2944 } else if (IS_SKYLAKE(dev_priv)
2945 || IS_KABYLAKE(dev_priv)) {
2946 ret = init_broadwell_mmio_info(gvt);
2947 if (ret)
2948 goto err;
2949 ret = init_skl_mmio_info(gvt);
2950 if (ret)
2951 goto err;
2952 }
2953
2954 gvt_dbg_mmio("traced %u virtual mmio registers\n",
2955 gvt->mmio.num_tracked_mmio);
2956 return 0;
2957 err:
2958 intel_gvt_clean_mmio_info(gvt);
2959 return ret;
2960 }
2961
2962
2963 /**
2964 * intel_vgpu_default_mmio_read - default MMIO read handler
2965 * @vgpu: a vGPU
2966 * @offset: access offset
2967 * @p_data: data return buffer
2968 * @bytes: access data length
2969 *
2970 * Returns:
2971 * Zero on success, negative error code if failed.
2972 */
2973 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
2974 void *p_data, unsigned int bytes)
2975 {
2976 read_vreg(vgpu, offset, p_data, bytes);
2977 return 0;
2978 }
2979
2980 /**
2981 * intel_t_default_mmio_write - default MMIO write handler
2982 * @vgpu: a vGPU
2983 * @offset: access offset
2984 * @p_data: write data buffer
2985 * @bytes: access data length
2986 *
2987 * Returns:
2988 * Zero on success, negative error code if failed.
2989 */
2990 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2991 void *p_data, unsigned int bytes)
2992 {
2993 write_vreg(vgpu, offset, p_data, bytes);
2994 return 0;
2995 }
2996
2997 /**
2998 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
2999 * force-nopriv register
3000 *
3001 * @gvt: a GVT device
3002 * @offset: register offset
3003 *
3004 * Returns:
3005 * True if the register is in force-nonpriv whitelist;
3006 * False if outside;
3007 */
3008 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3009 unsigned int offset)
3010 {
3011 return in_whitelist(offset);
3012 }
3013
3014 /**
3015 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3016 * @vgpu: a vGPU
3017 * @offset: register offset
3018 * @pdata: data buffer
3019 * @bytes: data length
3020 *
3021 * Returns:
3022 * Zero on success, negative error code if failed.
3023 */
3024 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3025 void *pdata, unsigned int bytes, bool is_read)
3026 {
3027 struct intel_gvt *gvt = vgpu->gvt;
3028 struct intel_gvt_mmio_info *mmio_info;
3029 struct gvt_mmio_block *mmio_block;
3030 gvt_mmio_func func;
3031 int ret;
3032
3033 if (WARN_ON(bytes > 4))
3034 return -EINVAL;
3035
3036 /*
3037 * Handle special MMIO blocks.
3038 */
3039 mmio_block = find_mmio_block(gvt, offset);
3040 if (mmio_block) {
3041 func = is_read ? mmio_block->read : mmio_block->write;
3042 if (func)
3043 return func(vgpu, offset, pdata, bytes);
3044 goto default_rw;
3045 }
3046
3047 /*
3048 * Normal tracked MMIOs.
3049 */
3050 mmio_info = find_mmio_info(gvt, offset);
3051 if (!mmio_info) {
3052 if (!vgpu->mmio.disable_warn_untrack)
3053 gvt_vgpu_err("untracked MMIO %08x len %d\n",
3054 offset, bytes);
3055 goto default_rw;
3056 }
3057
3058 if (is_read)
3059 return mmio_info->read(vgpu, offset, pdata, bytes);
3060 else {
3061 u64 ro_mask = mmio_info->ro_mask;
3062 u32 old_vreg = 0, old_sreg = 0;
3063 u64 data = 0;
3064
3065 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3066 old_vreg = vgpu_vreg(vgpu, offset);
3067 old_sreg = vgpu_sreg(vgpu, offset);
3068 }
3069
3070 if (likely(!ro_mask))
3071 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3072 else if (!~ro_mask) {
3073 gvt_vgpu_err("try to write RO reg %x\n", offset);
3074 return 0;
3075 } else {
3076 /* keep the RO bits in the virtual register */
3077 memcpy(&data, pdata, bytes);
3078 data &= ~ro_mask;
3079 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3080 ret = mmio_info->write(vgpu, offset, &data, bytes);
3081 }
3082
3083 /* higher 16bits of mode ctl regs are mask bits for change */
3084 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3085 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3086
3087 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3088 | (vgpu_vreg(vgpu, offset) & mask);
3089 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)
3090 | (vgpu_sreg(vgpu, offset) & mask);
3091 }
3092 }
3093
3094 return ret;
3095
3096 default_rw:
3097 return is_read ?
3098 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3099 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3100 }
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