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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / gvt / handlers.c
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include "i915_drv.h"
40 #include "gvt.h"
41 #include "i915_pvinfo.h"
42
43 /* XXX FIXME i915 has changed PP_XXX definition */
44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
49
50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51 {
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
58
59 return 0;
60 }
61
62 bool intel_gvt_match_device(struct intel_gvt *gvt,
63 unsigned long device)
64 {
65 return intel_gvt_get_device_type(gvt) & device;
66 }
67
68 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
69 void *p_data, unsigned int bytes)
70 {
71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
72 }
73
74 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
75 void *p_data, unsigned int bytes)
76 {
77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
78 }
79
80 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
81 unsigned int offset)
82 {
83 struct intel_gvt_mmio_info *e;
84
85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
86 if (e->offset == offset)
87 return e;
88 }
89 return NULL;
90 }
91
92 static int new_mmio_info(struct intel_gvt *gvt,
93 u32 offset, u8 flags, u32 size,
94 u32 addr_mask, u32 ro_mask, u32 device,
95 gvt_mmio_func read, gvt_mmio_func write)
96 {
97 struct intel_gvt_mmio_info *info, *p;
98 u32 start, end, i;
99
100 if (!intel_gvt_match_device(gvt, device))
101 return 0;
102
103 if (WARN_ON(!IS_ALIGNED(offset, 4)))
104 return -EINVAL;
105
106 start = offset;
107 end = offset + size;
108
109 for (i = start; i < end; i += 4) {
110 info = kzalloc(sizeof(*info), GFP_KERNEL);
111 if (!info)
112 return -ENOMEM;
113
114 info->offset = i;
115 p = find_mmio_info(gvt, info->offset);
116 if (p) {
117 WARN(1, "dup mmio definition offset %x\n",
118 info->offset);
119 kfree(info);
120
121 /* We return -EEXIST here to make GVT-g load fail.
122 * So duplicated MMIO can be found as soon as
123 * possible.
124 */
125 return -EEXIST;
126 }
127
128 info->ro_mask = ro_mask;
129 info->device = device;
130 info->read = read ? read : intel_vgpu_default_mmio_read;
131 info->write = write ? write : intel_vgpu_default_mmio_write;
132 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
133 INIT_HLIST_NODE(&info->node);
134 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
135 gvt->mmio.num_tracked_mmio++;
136 }
137 return 0;
138 }
139
140 /**
141 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
142 * @gvt: a GVT device
143 * @offset: register offset
144 *
145 * Returns:
146 * Ring ID on success, negative error code if failed.
147 */
148 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
149 unsigned int offset)
150 {
151 enum intel_engine_id id;
152 struct intel_engine_cs *engine;
153
154 offset &= ~GENMASK(11, 0);
155 for_each_engine(engine, gvt->dev_priv, id) {
156 if (engine->mmio_base == offset)
157 return id;
158 }
159 return -ENODEV;
160 }
161
162 #define offset_to_fence_num(offset) \
163 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
164
165 #define fence_num_to_offset(num) \
166 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
167
168
169 static void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
170 {
171 switch (reason) {
172 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
173 pr_err("Detected your guest driver doesn't support GVT-g.\n");
174 break;
175 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
176 pr_err("Graphics resource is not enough for the guest\n");
177 default:
178 break;
179 }
180 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
181 vgpu->failsafe = true;
182 }
183
184 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
185 unsigned int fence_num, void *p_data, unsigned int bytes)
186 {
187 if (fence_num >= vgpu_fence_sz(vgpu)) {
188
189 /* When guest access oob fence regs without access
190 * pv_info first, we treat guest not supporting GVT,
191 * and we will let vgpu enter failsafe mode.
192 */
193 if (!vgpu->pv_notified)
194 enter_failsafe_mode(vgpu,
195 GVT_FAILSAFE_UNSUPPORTED_GUEST);
196
197 if (!vgpu->mmio.disable_warn_untrack) {
198 gvt_vgpu_err("found oob fence register access\n");
199 gvt_vgpu_err("total fence %d, access fence %d\n",
200 vgpu_fence_sz(vgpu), fence_num);
201 }
202 memset(p_data, 0, bytes);
203 return -EINVAL;
204 }
205 return 0;
206 }
207
208 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
209 void *p_data, unsigned int bytes)
210 {
211 int ret;
212
213 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
214 p_data, bytes);
215 if (ret)
216 return ret;
217 read_vreg(vgpu, off, p_data, bytes);
218 return 0;
219 }
220
221 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
222 void *p_data, unsigned int bytes)
223 {
224 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
225 unsigned int fence_num = offset_to_fence_num(off);
226 int ret;
227
228 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
229 if (ret)
230 return ret;
231 write_vreg(vgpu, off, p_data, bytes);
232
233 mmio_hw_access_pre(dev_priv);
234 intel_vgpu_write_fence(vgpu, fence_num,
235 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
236 mmio_hw_access_post(dev_priv);
237 return 0;
238 }
239
240 #define CALC_MODE_MASK_REG(old, new) \
241 (((new) & GENMASK(31, 16)) \
242 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
243 | ((new) & ((new) >> 16))))
244
245 static int mul_force_wake_write(struct intel_vgpu *vgpu,
246 unsigned int offset, void *p_data, unsigned int bytes)
247 {
248 u32 old, new;
249 uint32_t ack_reg_offset;
250
251 old = vgpu_vreg(vgpu, offset);
252 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
253
254 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
255 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
256 switch (offset) {
257 case FORCEWAKE_RENDER_GEN9_REG:
258 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
259 break;
260 case FORCEWAKE_BLITTER_GEN9_REG:
261 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
262 break;
263 case FORCEWAKE_MEDIA_GEN9_REG:
264 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
265 break;
266 default:
267 /*should not hit here*/
268 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
269 return -EINVAL;
270 }
271 } else {
272 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
273 }
274
275 vgpu_vreg(vgpu, offset) = new;
276 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
277 return 0;
278 }
279
280 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
281 void *p_data, unsigned int bytes)
282 {
283 unsigned int engine_mask = 0;
284 u32 data;
285
286 write_vreg(vgpu, offset, p_data, bytes);
287 data = vgpu_vreg(vgpu, offset);
288
289 if (data & GEN6_GRDOM_FULL) {
290 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
291 engine_mask = ALL_ENGINES;
292 } else {
293 if (data & GEN6_GRDOM_RENDER) {
294 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
295 engine_mask |= (1 << RCS);
296 }
297 if (data & GEN6_GRDOM_MEDIA) {
298 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
299 engine_mask |= (1 << VCS);
300 }
301 if (data & GEN6_GRDOM_BLT) {
302 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
303 engine_mask |= (1 << BCS);
304 }
305 if (data & GEN6_GRDOM_VECS) {
306 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
307 engine_mask |= (1 << VECS);
308 }
309 if (data & GEN8_GRDOM_MEDIA2) {
310 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
311 if (HAS_BSD2(vgpu->gvt->dev_priv))
312 engine_mask |= (1 << VCS2);
313 }
314 }
315
316 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
317
318 /* sw will wait for the device to ack the reset request */
319 vgpu_vreg(vgpu, offset) = 0;
320
321 return 0;
322 }
323
324 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
325 void *p_data, unsigned int bytes)
326 {
327 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
328 }
329
330 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
331 void *p_data, unsigned int bytes)
332 {
333 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
334 }
335
336 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
337 unsigned int offset, void *p_data, unsigned int bytes)
338 {
339 write_vreg(vgpu, offset, p_data, bytes);
340
341 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
342 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON;
343 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
344 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
345 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
346
347 } else
348 vgpu_vreg(vgpu, PCH_PP_STATUS) &=
349 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
350 | PP_CYCLE_DELAY_ACTIVE);
351 return 0;
352 }
353
354 static int transconf_mmio_write(struct intel_vgpu *vgpu,
355 unsigned int offset, void *p_data, unsigned int bytes)
356 {
357 write_vreg(vgpu, offset, p_data, bytes);
358
359 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
360 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
361 else
362 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
363 return 0;
364 }
365
366 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
367 void *p_data, unsigned int bytes)
368 {
369 write_vreg(vgpu, offset, p_data, bytes);
370
371 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
372 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
373 else
374 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
375
376 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
377 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
378 else
379 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
380
381 return 0;
382 }
383
384 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
385 void *p_data, unsigned int bytes)
386 {
387 switch (offset) {
388 case 0xe651c:
389 case 0xe661c:
390 case 0xe671c:
391 case 0xe681c:
392 vgpu_vreg(vgpu, offset) = 1 << 17;
393 break;
394 case 0xe6c04:
395 vgpu_vreg(vgpu, offset) = 0x3;
396 break;
397 case 0xe6e1c:
398 vgpu_vreg(vgpu, offset) = 0x2f << 16;
399 break;
400 default:
401 return -EINVAL;
402 }
403
404 read_vreg(vgpu, offset, p_data, bytes);
405 return 0;
406 }
407
408 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
409 void *p_data, unsigned int bytes)
410 {
411 u32 data;
412
413 write_vreg(vgpu, offset, p_data, bytes);
414 data = vgpu_vreg(vgpu, offset);
415
416 if (data & PIPECONF_ENABLE)
417 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
418 else
419 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
420 intel_gvt_check_vblank_emulation(vgpu->gvt);
421 return 0;
422 }
423
424 /* ascendingly sorted */
425 static i915_reg_t force_nonpriv_white_list[] = {
426 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
427 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
428 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
429 _MMIO(0x2690),
430 _MMIO(0x2694),
431 _MMIO(0x2698),
432 _MMIO(0x4de0),
433 _MMIO(0x4de4),
434 _MMIO(0x4dfc),
435 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
436 _MMIO(0x7014),
437 HDC_CHICKEN0,//_MMIO(0x7300)
438 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
439 _MMIO(0x7700),
440 _MMIO(0x7704),
441 _MMIO(0x7708),
442 _MMIO(0x770c),
443 _MMIO(0xb110),
444 GEN8_L3SQCREG4,//_MMIO(0xb118)
445 _MMIO(0xe100),
446 _MMIO(0xe18c),
447 _MMIO(0xe48c),
448 _MMIO(0xe5f4),
449 };
450
451 /* a simple bsearch */
452 static inline bool in_whitelist(unsigned int reg)
453 {
454 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
455 i915_reg_t *array = force_nonpriv_white_list;
456
457 while (left < right) {
458 int mid = (left + right)/2;
459
460 if (reg > array[mid].reg)
461 left = mid + 1;
462 else if (reg < array[mid].reg)
463 right = mid;
464 else
465 return true;
466 }
467 return false;
468 }
469
470 static int force_nonpriv_write(struct intel_vgpu *vgpu,
471 unsigned int offset, void *p_data, unsigned int bytes)
472 {
473 u32 reg_nonpriv = *(u32 *)p_data;
474 int ret = -EINVAL;
475
476 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
477 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
478 vgpu->id, offset, bytes);
479 return ret;
480 }
481
482 if (in_whitelist(reg_nonpriv)) {
483 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
484 bytes);
485 } else {
486 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
487 vgpu->id, reg_nonpriv);
488 }
489 return ret;
490 }
491
492 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
493 void *p_data, unsigned int bytes)
494 {
495 write_vreg(vgpu, offset, p_data, bytes);
496
497 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
498 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
499 } else {
500 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
501 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
502 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E))
503 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
504 }
505 return 0;
506 }
507
508 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
509 unsigned int offset, void *p_data, unsigned int bytes)
510 {
511 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
512 return 0;
513 }
514
515 #define FDI_LINK_TRAIN_PATTERN1 0
516 #define FDI_LINK_TRAIN_PATTERN2 1
517
518 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
519 {
520 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E));
521 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
522 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E));
523
524 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
525 (rx_ctl & FDI_RX_ENABLE) &&
526 (rx_ctl & FDI_AUTO_TRAINING) &&
527 (tx_ctl & DP_TP_CTL_ENABLE) &&
528 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
529 return 1;
530 else
531 return 0;
532 }
533
534 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
535 enum pipe pipe, unsigned int train_pattern)
536 {
537 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
538 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
539 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
540 unsigned int fdi_iir_check_bits;
541
542 fdi_rx_imr = FDI_RX_IMR(pipe);
543 fdi_tx_ctl = FDI_TX_CTL(pipe);
544 fdi_rx_ctl = FDI_RX_CTL(pipe);
545
546 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
547 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
548 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
549 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
550 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
551 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
552 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
553 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
554 } else {
555 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
556 return -EINVAL;
557 }
558
559 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
560 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
561
562 /* If imr bit has been masked */
563 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
564 return 0;
565
566 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
567 == fdi_tx_check_bits)
568 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
569 == fdi_rx_check_bits))
570 return 1;
571 else
572 return 0;
573 }
574
575 #define INVALID_INDEX (~0U)
576
577 static unsigned int calc_index(unsigned int offset, unsigned int start,
578 unsigned int next, unsigned int end, i915_reg_t i915_end)
579 {
580 unsigned int range = next - start;
581
582 if (!end)
583 end = i915_mmio_reg_offset(i915_end);
584 if (offset < start || offset > end)
585 return INVALID_INDEX;
586 offset -= start;
587 return offset / range;
588 }
589
590 #define FDI_RX_CTL_TO_PIPE(offset) \
591 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
592
593 #define FDI_TX_CTL_TO_PIPE(offset) \
594 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
595
596 #define FDI_RX_IMR_TO_PIPE(offset) \
597 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
598
599 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
600 unsigned int offset, void *p_data, unsigned int bytes)
601 {
602 i915_reg_t fdi_rx_iir;
603 unsigned int index;
604 int ret;
605
606 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
607 index = FDI_RX_CTL_TO_PIPE(offset);
608 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
609 index = FDI_TX_CTL_TO_PIPE(offset);
610 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
611 index = FDI_RX_IMR_TO_PIPE(offset);
612 else {
613 gvt_vgpu_err("Unsupport registers %x\n", offset);
614 return -EINVAL;
615 }
616
617 write_vreg(vgpu, offset, p_data, bytes);
618
619 fdi_rx_iir = FDI_RX_IIR(index);
620
621 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
622 if (ret < 0)
623 return ret;
624 if (ret)
625 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
626
627 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
628 if (ret < 0)
629 return ret;
630 if (ret)
631 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
632
633 if (offset == _FDI_RXA_CTL)
634 if (fdi_auto_training_started(vgpu))
635 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |=
636 DP_TP_STATUS_AUTOTRAIN_DONE;
637 return 0;
638 }
639
640 #define DP_TP_CTL_TO_PORT(offset) \
641 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
642
643 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
644 void *p_data, unsigned int bytes)
645 {
646 i915_reg_t status_reg;
647 unsigned int index;
648 u32 data;
649
650 write_vreg(vgpu, offset, p_data, bytes);
651
652 index = DP_TP_CTL_TO_PORT(offset);
653 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
654 if (data == 0x2) {
655 status_reg = DP_TP_STATUS(index);
656 vgpu_vreg(vgpu, status_reg) |= (1 << 25);
657 }
658 return 0;
659 }
660
661 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
662 unsigned int offset, void *p_data, unsigned int bytes)
663 {
664 u32 reg_val;
665 u32 sticky_mask;
666
667 reg_val = *((u32 *)p_data);
668 sticky_mask = GENMASK(27, 26) | (1 << 24);
669
670 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
671 (vgpu_vreg(vgpu, offset) & sticky_mask);
672 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
673 return 0;
674 }
675
676 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
677 unsigned int offset, void *p_data, unsigned int bytes)
678 {
679 u32 data;
680
681 write_vreg(vgpu, offset, p_data, bytes);
682 data = vgpu_vreg(vgpu, offset);
683
684 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
685 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
686 return 0;
687 }
688
689 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
690 unsigned int offset, void *p_data, unsigned int bytes)
691 {
692 u32 data;
693
694 write_vreg(vgpu, offset, p_data, bytes);
695 data = vgpu_vreg(vgpu, offset);
696
697 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
698 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
699 else
700 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
701 return 0;
702 }
703
704 #define DSPSURF_TO_PIPE(offset) \
705 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
706
707 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
708 void *p_data, unsigned int bytes)
709 {
710 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
711 unsigned int index = DSPSURF_TO_PIPE(offset);
712 i915_reg_t surflive_reg = DSPSURFLIVE(index);
713 int flip_event[] = {
714 [PIPE_A] = PRIMARY_A_FLIP_DONE,
715 [PIPE_B] = PRIMARY_B_FLIP_DONE,
716 [PIPE_C] = PRIMARY_C_FLIP_DONE,
717 };
718
719 write_vreg(vgpu, offset, p_data, bytes);
720 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
721
722 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
723 return 0;
724 }
725
726 #define SPRSURF_TO_PIPE(offset) \
727 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
728
729 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
730 void *p_data, unsigned int bytes)
731 {
732 unsigned int index = SPRSURF_TO_PIPE(offset);
733 i915_reg_t surflive_reg = SPRSURFLIVE(index);
734 int flip_event[] = {
735 [PIPE_A] = SPRITE_A_FLIP_DONE,
736 [PIPE_B] = SPRITE_B_FLIP_DONE,
737 [PIPE_C] = SPRITE_C_FLIP_DONE,
738 };
739
740 write_vreg(vgpu, offset, p_data, bytes);
741 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
742
743 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
744 return 0;
745 }
746
747 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
748 unsigned int reg)
749 {
750 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
751 enum intel_gvt_event_type event;
752
753 if (reg == _DPA_AUX_CH_CTL)
754 event = AUX_CHANNEL_A;
755 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
756 event = AUX_CHANNEL_B;
757 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
758 event = AUX_CHANNEL_C;
759 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
760 event = AUX_CHANNEL_D;
761 else {
762 WARN_ON(true);
763 return -EINVAL;
764 }
765
766 intel_vgpu_trigger_virtual_event(vgpu, event);
767 return 0;
768 }
769
770 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
771 unsigned int reg, int len, bool data_valid)
772 {
773 /* mark transaction done */
774 value |= DP_AUX_CH_CTL_DONE;
775 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
776 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
777
778 if (data_valid)
779 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
780 else
781 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
782
783 /* message size */
784 value &= ~(0xf << 20);
785 value |= (len << 20);
786 vgpu_vreg(vgpu, reg) = value;
787
788 if (value & DP_AUX_CH_CTL_INTERRUPT)
789 return trigger_aux_channel_interrupt(vgpu, reg);
790 return 0;
791 }
792
793 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
794 uint8_t t)
795 {
796 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
797 /* training pattern 1 for CR */
798 /* set LANE0_CR_DONE, LANE1_CR_DONE */
799 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
800 /* set LANE2_CR_DONE, LANE3_CR_DONE */
801 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
802 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
803 DPCD_TRAINING_PATTERN_2) {
804 /* training pattern 2 for EQ */
805 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
806 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
807 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
808 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
809 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
810 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
811 /* set INTERLANE_ALIGN_DONE */
812 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
813 DPCD_INTERLANE_ALIGN_DONE;
814 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
815 DPCD_LINK_TRAINING_DISABLED) {
816 /* finish link training */
817 /* set sink status as synchronized */
818 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
819 }
820 }
821
822 #define _REG_HSW_DP_AUX_CH_CTL(dp) \
823 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
824
825 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
826
827 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
828
829 #define dpy_is_valid_port(port) \
830 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
831
832 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
833 unsigned int offset, void *p_data, unsigned int bytes)
834 {
835 struct intel_vgpu_display *display = &vgpu->display;
836 int msg, addr, ctrl, op, len;
837 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
838 struct intel_vgpu_dpcd_data *dpcd = NULL;
839 struct intel_vgpu_port *port = NULL;
840 u32 data;
841
842 if (!dpy_is_valid_port(port_index)) {
843 gvt_vgpu_err("Unsupported DP port access!\n");
844 return 0;
845 }
846
847 write_vreg(vgpu, offset, p_data, bytes);
848 data = vgpu_vreg(vgpu, offset);
849
850 if ((IS_SKYLAKE(vgpu->gvt->dev_priv)
851 || IS_KABYLAKE(vgpu->gvt->dev_priv))
852 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
853 /* SKL DPB/C/D aux ctl register changed */
854 return 0;
855 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
856 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
857 /* write to the data registers */
858 return 0;
859 }
860
861 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
862 /* just want to clear the sticky bits */
863 vgpu_vreg(vgpu, offset) = 0;
864 return 0;
865 }
866
867 port = &display->ports[port_index];
868 dpcd = port->dpcd;
869
870 /* read out message from DATA1 register */
871 msg = vgpu_vreg(vgpu, offset + 4);
872 addr = (msg >> 8) & 0xffff;
873 ctrl = (msg >> 24) & 0xff;
874 len = msg & 0xff;
875 op = ctrl >> 4;
876
877 if (op == GVT_AUX_NATIVE_WRITE) {
878 int t;
879 uint8_t buf[16];
880
881 if ((addr + len + 1) >= DPCD_SIZE) {
882 /*
883 * Write request exceeds what we supported,
884 * DCPD spec: When a Source Device is writing a DPCD
885 * address not supported by the Sink Device, the Sink
886 * Device shall reply with AUX NACK and “M” equal to
887 * zero.
888 */
889
890 /* NAK the write */
891 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
892 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
893 return 0;
894 }
895
896 /*
897 * Write request format: (command + address) occupies
898 * 3 bytes, followed by (len + 1) bytes of data.
899 */
900 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
901 return -EINVAL;
902
903 /* unpack data from vreg to buf */
904 for (t = 0; t < 4; t++) {
905 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
906
907 buf[t * 4] = (r >> 24) & 0xff;
908 buf[t * 4 + 1] = (r >> 16) & 0xff;
909 buf[t * 4 + 2] = (r >> 8) & 0xff;
910 buf[t * 4 + 3] = r & 0xff;
911 }
912
913 /* write to virtual DPCD */
914 if (dpcd && dpcd->data_valid) {
915 for (t = 0; t <= len; t++) {
916 int p = addr + t;
917
918 dpcd->data[p] = buf[t];
919 /* check for link training */
920 if (p == DPCD_TRAINING_PATTERN_SET)
921 dp_aux_ch_ctl_link_training(dpcd,
922 buf[t]);
923 }
924 }
925
926 /* ACK the write */
927 vgpu_vreg(vgpu, offset + 4) = 0;
928 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
929 dpcd && dpcd->data_valid);
930 return 0;
931 }
932
933 if (op == GVT_AUX_NATIVE_READ) {
934 int idx, i, ret = 0;
935
936 if ((addr + len + 1) >= DPCD_SIZE) {
937 /*
938 * read request exceeds what we supported
939 * DPCD spec: A Sink Device receiving a Native AUX CH
940 * read request for an unsupported DPCD address must
941 * reply with an AUX ACK and read data set equal to
942 * zero instead of replying with AUX NACK.
943 */
944
945 /* ACK the READ*/
946 vgpu_vreg(vgpu, offset + 4) = 0;
947 vgpu_vreg(vgpu, offset + 8) = 0;
948 vgpu_vreg(vgpu, offset + 12) = 0;
949 vgpu_vreg(vgpu, offset + 16) = 0;
950 vgpu_vreg(vgpu, offset + 20) = 0;
951
952 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
953 true);
954 return 0;
955 }
956
957 for (idx = 1; idx <= 5; idx++) {
958 /* clear the data registers */
959 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
960 }
961
962 /*
963 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
964 */
965 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
966 return -EINVAL;
967
968 /* read from virtual DPCD to vreg */
969 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
970 if (dpcd && dpcd->data_valid) {
971 for (i = 1; i <= (len + 1); i++) {
972 int t;
973
974 t = dpcd->data[addr + i - 1];
975 t <<= (24 - 8 * (i % 4));
976 ret |= t;
977
978 if ((i % 4 == 3) || (i == (len + 1))) {
979 vgpu_vreg(vgpu, offset +
980 (i / 4 + 1) * 4) = ret;
981 ret = 0;
982 }
983 }
984 }
985 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
986 dpcd && dpcd->data_valid);
987 return 0;
988 }
989
990 /* i2c transaction starts */
991 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
992
993 if (data & DP_AUX_CH_CTL_INTERRUPT)
994 trigger_aux_channel_interrupt(vgpu, offset);
995 return 0;
996 }
997
998 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
999 void *p_data, unsigned int bytes)
1000 {
1001 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1002 write_vreg(vgpu, offset, p_data, bytes);
1003 return 0;
1004 }
1005
1006 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1007 void *p_data, unsigned int bytes)
1008 {
1009 bool vga_disable;
1010
1011 write_vreg(vgpu, offset, p_data, bytes);
1012 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1013
1014 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1015 vga_disable ? "Disable" : "Enable");
1016 return 0;
1017 }
1018
1019 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1020 unsigned int sbi_offset)
1021 {
1022 struct intel_vgpu_display *display = &vgpu->display;
1023 int num = display->sbi.number;
1024 int i;
1025
1026 for (i = 0; i < num; ++i)
1027 if (display->sbi.registers[i].offset == sbi_offset)
1028 break;
1029
1030 if (i == num)
1031 return 0;
1032
1033 return display->sbi.registers[i].value;
1034 }
1035
1036 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1037 unsigned int offset, u32 value)
1038 {
1039 struct intel_vgpu_display *display = &vgpu->display;
1040 int num = display->sbi.number;
1041 int i;
1042
1043 for (i = 0; i < num; ++i) {
1044 if (display->sbi.registers[i].offset == offset)
1045 break;
1046 }
1047
1048 if (i == num) {
1049 if (num == SBI_REG_MAX) {
1050 gvt_vgpu_err("SBI caching meets maximum limits\n");
1051 return;
1052 }
1053 display->sbi.number++;
1054 }
1055
1056 display->sbi.registers[i].offset = offset;
1057 display->sbi.registers[i].value = value;
1058 }
1059
1060 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1061 void *p_data, unsigned int bytes)
1062 {
1063 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1064 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1065 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1066 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1067 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1068 sbi_offset);
1069 }
1070 read_vreg(vgpu, offset, p_data, bytes);
1071 return 0;
1072 }
1073
1074 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1075 void *p_data, unsigned int bytes)
1076 {
1077 u32 data;
1078
1079 write_vreg(vgpu, offset, p_data, bytes);
1080 data = vgpu_vreg(vgpu, offset);
1081
1082 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1083 data |= SBI_READY;
1084
1085 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1086 data |= SBI_RESPONSE_SUCCESS;
1087
1088 vgpu_vreg(vgpu, offset) = data;
1089
1090 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1091 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1092 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1093 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1094
1095 write_virtual_sbi_register(vgpu, sbi_offset,
1096 vgpu_vreg(vgpu, SBI_DATA));
1097 }
1098 return 0;
1099 }
1100
1101 #define _vgtif_reg(x) \
1102 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1103
1104 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1105 void *p_data, unsigned int bytes)
1106 {
1107 bool invalid_read = false;
1108
1109 read_vreg(vgpu, offset, p_data, bytes);
1110
1111 switch (offset) {
1112 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1113 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1114 invalid_read = true;
1115 break;
1116 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1117 _vgtif_reg(avail_rs.fence_num):
1118 if (offset + bytes >
1119 _vgtif_reg(avail_rs.fence_num) + 4)
1120 invalid_read = true;
1121 break;
1122 case 0x78010: /* vgt_caps */
1123 case 0x7881c:
1124 break;
1125 default:
1126 invalid_read = true;
1127 break;
1128 }
1129 if (invalid_read)
1130 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1131 offset, bytes, *(u32 *)p_data);
1132 vgpu->pv_notified = true;
1133 return 0;
1134 }
1135
1136 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1137 {
1138 int ret = 0;
1139
1140 switch (notification) {
1141 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1142 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3);
1143 break;
1144 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1145 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3);
1146 break;
1147 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1148 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4);
1149 break;
1150 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1151 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4);
1152 break;
1153 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1154 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1155 case 1: /* Remove this in guest driver. */
1156 break;
1157 default:
1158 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1159 }
1160 return ret;
1161 }
1162
1163 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1164 {
1165 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1166 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1167 char *env[3] = {NULL, NULL, NULL};
1168 char vmid_str[20];
1169 char display_ready_str[20];
1170
1171 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1172 env[0] = display_ready_str;
1173
1174 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1175 env[1] = vmid_str;
1176
1177 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1178 }
1179
1180 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1181 void *p_data, unsigned int bytes)
1182 {
1183 u32 data;
1184 int ret;
1185
1186 write_vreg(vgpu, offset, p_data, bytes);
1187 data = vgpu_vreg(vgpu, offset);
1188
1189 switch (offset) {
1190 case _vgtif_reg(display_ready):
1191 send_display_ready_uevent(vgpu, data ? 1 : 0);
1192 break;
1193 case _vgtif_reg(g2v_notify):
1194 ret = handle_g2v_notification(vgpu, data);
1195 break;
1196 /* add xhot and yhot to handled list to avoid error log */
1197 case 0x78830:
1198 case 0x78834:
1199 case _vgtif_reg(pdp[0].lo):
1200 case _vgtif_reg(pdp[0].hi):
1201 case _vgtif_reg(pdp[1].lo):
1202 case _vgtif_reg(pdp[1].hi):
1203 case _vgtif_reg(pdp[2].lo):
1204 case _vgtif_reg(pdp[2].hi):
1205 case _vgtif_reg(pdp[3].lo):
1206 case _vgtif_reg(pdp[3].hi):
1207 case _vgtif_reg(execlist_context_descriptor_lo):
1208 case _vgtif_reg(execlist_context_descriptor_hi):
1209 break;
1210 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1211 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1212 break;
1213 default:
1214 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1215 offset, bytes, data);
1216 break;
1217 }
1218 return 0;
1219 }
1220
1221 static int pf_write(struct intel_vgpu *vgpu,
1222 unsigned int offset, void *p_data, unsigned int bytes)
1223 {
1224 u32 val = *(u32 *)p_data;
1225
1226 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1227 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1228 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1229 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1230 vgpu->id);
1231 return 0;
1232 }
1233
1234 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1235 }
1236
1237 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1238 unsigned int offset, void *p_data, unsigned int bytes)
1239 {
1240 write_vreg(vgpu, offset, p_data, bytes);
1241
1242 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
1243 vgpu_vreg(vgpu, offset) |=
1244 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
1245 else
1246 vgpu_vreg(vgpu, offset) &=
1247 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
1248 return 0;
1249 }
1250
1251 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1252 unsigned int offset, void *p_data, unsigned int bytes)
1253 {
1254 write_vreg(vgpu, offset, p_data, bytes);
1255
1256 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1257 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1258 return 0;
1259 }
1260
1261 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1262 void *p_data, unsigned int bytes)
1263 {
1264 u32 mode;
1265
1266 write_vreg(vgpu, offset, p_data, bytes);
1267 mode = vgpu_vreg(vgpu, offset);
1268
1269 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1270 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
1271 vgpu->id);
1272 return 0;
1273 }
1274
1275 return 0;
1276 }
1277
1278 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1279 void *p_data, unsigned int bytes)
1280 {
1281 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1282 u32 trtte = *(u32 *)p_data;
1283
1284 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1285 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1286 vgpu->id);
1287 return -EINVAL;
1288 }
1289 write_vreg(vgpu, offset, p_data, bytes);
1290 /* TRTTE is not per-context */
1291
1292 mmio_hw_access_pre(dev_priv);
1293 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
1294 mmio_hw_access_post(dev_priv);
1295
1296 return 0;
1297 }
1298
1299 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1300 void *p_data, unsigned int bytes)
1301 {
1302 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1303 u32 val = *(u32 *)p_data;
1304
1305 if (val & 1) {
1306 /* unblock hw logic */
1307 mmio_hw_access_pre(dev_priv);
1308 I915_WRITE(_MMIO(offset), val);
1309 mmio_hw_access_post(dev_priv);
1310 }
1311 write_vreg(vgpu, offset, p_data, bytes);
1312 return 0;
1313 }
1314
1315 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1316 void *p_data, unsigned int bytes)
1317 {
1318 u32 v = 0;
1319
1320 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1321 v |= (1 << 0);
1322
1323 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1324 v |= (1 << 8);
1325
1326 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1327 v |= (1 << 16);
1328
1329 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1330 v |= (1 << 24);
1331
1332 vgpu_vreg(vgpu, offset) = v;
1333
1334 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1335 }
1336
1337 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1338 void *p_data, unsigned int bytes)
1339 {
1340 u32 value = *(u32 *)p_data;
1341 u32 cmd = value & 0xff;
1342 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
1343
1344 switch (cmd) {
1345 case GEN9_PCODE_READ_MEM_LATENCY:
1346 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1347 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
1348 /**
1349 * "Read memory latency" command on gen9.
1350 * Below memory latency values are read
1351 * from skylake platform.
1352 */
1353 if (!*data0)
1354 *data0 = 0x1e1a1100;
1355 else
1356 *data0 = 0x61514b3d;
1357 }
1358 break;
1359 case SKL_PCODE_CDCLK_CONTROL:
1360 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1361 || IS_KABYLAKE(vgpu->gvt->dev_priv))
1362 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1363 break;
1364 case GEN6_PCODE_READ_RC6VIDS:
1365 *data0 |= 0x1;
1366 break;
1367 }
1368
1369 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1370 vgpu->id, value, *data0);
1371 /**
1372 * PCODE_READY clear means ready for pcode read/write,
1373 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1374 * always emulate as pcode read/write success and ready for access
1375 * anytime, since we don't touch real physical registers here.
1376 */
1377 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1378 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1379 }
1380
1381 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1382 unsigned int offset, void *p_data, unsigned int bytes)
1383 {
1384 u32 v = *(u32 *)p_data;
1385
1386 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1387 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1388 v |= (v >> 1);
1389
1390 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1391 }
1392
1393 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1394 void *p_data, unsigned int bytes)
1395 {
1396 u32 v = *(u32 *)p_data;
1397
1398 /* other bits are MBZ. */
1399 v &= (1 << 31) | (1 << 30);
1400 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1401
1402 vgpu_vreg(vgpu, offset) = v;
1403
1404 return 0;
1405 }
1406
1407 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1408 unsigned int offset, void *p_data, unsigned int bytes)
1409 {
1410 struct intel_gvt *gvt = vgpu->gvt;
1411 struct drm_i915_private *dev_priv = gvt->dev_priv;
1412 int ring_id;
1413 u32 ring_base;
1414
1415 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset);
1416 /**
1417 * Read HW reg in following case
1418 * a. the offset isn't a ring mmio
1419 * b. the offset's ring is running on hw.
1420 * c. the offset is ring time stamp mmio
1421 */
1422 if (ring_id >= 0)
1423 ring_base = dev_priv->engine[ring_id]->mmio_base;
1424
1425 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] ||
1426 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) ||
1427 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) {
1428 mmio_hw_access_pre(dev_priv);
1429 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1430 mmio_hw_access_post(dev_priv);
1431 }
1432
1433 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1434 }
1435
1436 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1437 void *p_data, unsigned int bytes)
1438 {
1439 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1440 struct intel_vgpu_execlist *execlist;
1441 u32 data = *(u32 *)p_data;
1442 int ret = 0;
1443
1444 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
1445 return -EINVAL;
1446
1447 execlist = &vgpu->execlist[ring_id];
1448
1449 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data;
1450 if (execlist->elsp_dwords.index == 3) {
1451 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
1452 if(ret)
1453 gvt_vgpu_err("fail submit workload on ring %d\n",
1454 ring_id);
1455 }
1456
1457 ++execlist->elsp_dwords.index;
1458 execlist->elsp_dwords.index &= 0x3;
1459 return ret;
1460 }
1461
1462 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1463 void *p_data, unsigned int bytes)
1464 {
1465 u32 data = *(u32 *)p_data;
1466 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1467 bool enable_execlist;
1468
1469 write_vreg(vgpu, offset, p_data, bytes);
1470
1471 /* when PPGTT mode enabled, we will check if guest has called
1472 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1473 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1474 */
1475 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1476 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1477 && !vgpu->pv_notified) {
1478 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1479 return 0;
1480 }
1481 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1482 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1483 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1484
1485 gvt_dbg_core("EXECLIST %s on ring %d\n",
1486 (enable_execlist ? "enabling" : "disabling"),
1487 ring_id);
1488
1489 if (enable_execlist)
1490 intel_vgpu_start_schedule(vgpu);
1491 }
1492 return 0;
1493 }
1494
1495 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1496 unsigned int offset, void *p_data, unsigned int bytes)
1497 {
1498 unsigned int id = 0;
1499
1500 write_vreg(vgpu, offset, p_data, bytes);
1501 vgpu_vreg(vgpu, offset) = 0;
1502
1503 switch (offset) {
1504 case 0x4260:
1505 id = RCS;
1506 break;
1507 case 0x4264:
1508 id = VCS;
1509 break;
1510 case 0x4268:
1511 id = VCS2;
1512 break;
1513 case 0x426c:
1514 id = BCS;
1515 break;
1516 case 0x4270:
1517 id = VECS;
1518 break;
1519 default:
1520 return -EINVAL;
1521 }
1522 set_bit(id, (void *)vgpu->tlb_handle_pending);
1523
1524 return 0;
1525 }
1526
1527 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1528 unsigned int offset, void *p_data, unsigned int bytes)
1529 {
1530 u32 data;
1531
1532 write_vreg(vgpu, offset, p_data, bytes);
1533 data = vgpu_vreg(vgpu, offset);
1534
1535 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1536 data |= RESET_CTL_READY_TO_RESET;
1537 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1538 data &= ~RESET_CTL_READY_TO_RESET;
1539
1540 vgpu_vreg(vgpu, offset) = data;
1541 return 0;
1542 }
1543
1544 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1545 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
1546 f, s, am, rm, d, r, w); \
1547 if (ret) \
1548 return ret; \
1549 } while (0)
1550
1551 #define MMIO_D(reg, d) \
1552 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1553
1554 #define MMIO_DH(reg, d, r, w) \
1555 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1556
1557 #define MMIO_DFH(reg, d, f, r, w) \
1558 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1559
1560 #define MMIO_GM(reg, d, r, w) \
1561 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1562
1563 #define MMIO_GM_RDR(reg, d, r, w) \
1564 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1565
1566 #define MMIO_RO(reg, d, f, rm, r, w) \
1567 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1568
1569 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1570 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1571 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1572 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1573 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1574 if (HAS_BSD2(dev_priv)) \
1575 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1576 } while (0)
1577
1578 #define MMIO_RING_D(prefix, d) \
1579 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1580
1581 #define MMIO_RING_DFH(prefix, d, f, r, w) \
1582 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1583
1584 #define MMIO_RING_GM(prefix, d, r, w) \
1585 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1586
1587 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
1588 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1589
1590 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1591 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1592
1593 static int init_generic_mmio_info(struct intel_gvt *gvt)
1594 {
1595 struct drm_i915_private *dev_priv = gvt->dev_priv;
1596 int ret;
1597
1598 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1599 intel_vgpu_reg_imr_handler);
1600
1601 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1602 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1603 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1604 MMIO_D(SDEISR, D_ALL);
1605
1606 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
1607
1608 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1609 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1610 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1611 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1612
1613 #define RING_REG(base) (base + 0x28)
1614 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1615 #undef RING_REG
1616
1617 #define RING_REG(base) (base + 0x134)
1618 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1619 #undef RING_REG
1620
1621 #define RING_REG(base) (base + 0x6c)
1622 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1623 #undef RING_REG
1624 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1625
1626 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
1627 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1628 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL);
1629 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1630
1631 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1632 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1633 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1634 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
1635 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1636
1637 /* RING MODE */
1638 #define RING_REG(base) (base + 0x29c)
1639 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1640 ring_mode_mmio_write);
1641 #undef RING_REG
1642
1643 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1644 NULL, NULL);
1645 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1646 NULL, NULL);
1647 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1648 mmio_read_from_hw, NULL);
1649 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1650 mmio_read_from_hw, NULL);
1651
1652 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1653 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1654 NULL, NULL);
1655 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1656 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1657 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1658
1659 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1660 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1661 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1662 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1663 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1664 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1665 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1666 NULL, NULL);
1667 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1668 NULL, NULL);
1669 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
1670 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
1671 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
1672 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL);
1673 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL);
1674 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL);
1675 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL);
1676 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1677 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1678 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1679
1680 /* display */
1681 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1682 MMIO_D(0x602a0, D_ALL);
1683
1684 MMIO_D(0x65050, D_ALL);
1685 MMIO_D(0x650b4, D_ALL);
1686
1687 MMIO_D(0xc4040, D_ALL);
1688 MMIO_D(DERRMR, D_ALL);
1689
1690 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1691 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1692 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1693 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1694
1695 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1696 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1697 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1698 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
1699
1700 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1701 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1702 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1703 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1704
1705 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1706 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1707 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1708 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1709
1710 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1711 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1712 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1713 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1714
1715 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1716 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1717 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1718
1719 MMIO_D(CURPOS(PIPE_A), D_ALL);
1720 MMIO_D(CURPOS(PIPE_B), D_ALL);
1721 MMIO_D(CURPOS(PIPE_C), D_ALL);
1722
1723 MMIO_D(CURBASE(PIPE_A), D_ALL);
1724 MMIO_D(CURBASE(PIPE_B), D_ALL);
1725 MMIO_D(CURBASE(PIPE_C), D_ALL);
1726
1727 MMIO_D(0x700ac, D_ALL);
1728 MMIO_D(0x710ac, D_ALL);
1729 MMIO_D(0x720ac, D_ALL);
1730
1731 MMIO_D(0x70090, D_ALL);
1732 MMIO_D(0x70094, D_ALL);
1733 MMIO_D(0x70098, D_ALL);
1734 MMIO_D(0x7009c, D_ALL);
1735
1736 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1737 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1738 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1739 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1740 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
1741 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
1742 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1743 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1744
1745 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1746 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1747 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1748 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1749 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
1750 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
1751 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1752 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1753
1754 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1755 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1756 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1757 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1758 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
1759 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
1760 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1761 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1762
1763 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1764 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1765 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1766 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1767 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1768 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1769 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
1770 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
1771 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1772 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1773 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1774 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1775
1776 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1777 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1778 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1779 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1780 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1781 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1782 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
1783 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
1784 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1785 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1786 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1787 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1788
1789 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1790 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1791 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1792 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1793 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1794 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1795 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
1796 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
1797 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1798 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1799 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1800 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1801
1802 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
1803 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
1804 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
1805 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
1806 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
1807 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
1808 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
1809 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
1810 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
1811
1812 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
1813 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
1814 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
1815 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
1816 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
1817 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
1818 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
1819 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
1820 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
1821
1822 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
1823 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
1824 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
1825 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
1826 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
1827 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
1828 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
1829 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
1830 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
1831
1832 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
1833 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
1834 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
1835 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
1836 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
1837 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
1838 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
1839 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
1840
1841 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
1842 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
1843 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
1844 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
1845 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
1846 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
1847 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
1848 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
1849
1850 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
1851 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
1852 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
1853 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
1854 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
1855 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
1856 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
1857 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
1858
1859 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
1860 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
1861 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
1862 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
1863 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
1864 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
1865 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
1866 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
1867
1868 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
1869 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
1870 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
1871 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
1872 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
1873 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
1874 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
1875 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
1876
1877 MMIO_D(PF_CTL(PIPE_A), D_ALL);
1878 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
1879 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
1880 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
1881 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
1882
1883 MMIO_D(PF_CTL(PIPE_B), D_ALL);
1884 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
1885 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
1886 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
1887 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
1888
1889 MMIO_D(PF_CTL(PIPE_C), D_ALL);
1890 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
1891 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
1892 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
1893 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
1894
1895 MMIO_D(WM0_PIPEA_ILK, D_ALL);
1896 MMIO_D(WM0_PIPEB_ILK, D_ALL);
1897 MMIO_D(WM0_PIPEC_IVB, D_ALL);
1898 MMIO_D(WM1_LP_ILK, D_ALL);
1899 MMIO_D(WM2_LP_ILK, D_ALL);
1900 MMIO_D(WM3_LP_ILK, D_ALL);
1901 MMIO_D(WM1S_LP_ILK, D_ALL);
1902 MMIO_D(WM2S_LP_IVB, D_ALL);
1903 MMIO_D(WM3S_LP_IVB, D_ALL);
1904
1905 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1906 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1907 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1908 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1909
1910 MMIO_D(0x48268, D_ALL);
1911
1912 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1913 gmbus_mmio_write);
1914 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
1915 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1916
1917 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1918 dp_aux_ch_ctl_mmio_write);
1919 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1920 dp_aux_ch_ctl_mmio_write);
1921 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1922 dp_aux_ch_ctl_mmio_write);
1923
1924 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
1925
1926 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1927 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
1928
1929 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1930 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1931 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1932 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1933 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1934 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1935 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1936 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1937 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1938
1939 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
1940 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
1941 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
1942 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
1943 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
1944 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
1945 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);
1946
1947 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL);
1948 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL);
1949 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL);
1950 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL);
1951 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL);
1952 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL);
1953 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL);
1954
1955 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL);
1956 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL);
1957 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL);
1958 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL);
1959 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL);
1960 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL);
1961 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL);
1962 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL);
1963
1964 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
1965 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
1966 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
1967
1968 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
1969 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
1970 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
1971
1972 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
1973 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
1974 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
1975
1976 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
1977 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
1978 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
1979
1980 MMIO_D(_FDI_RXA_MISC, D_ALL);
1981 MMIO_D(_FDI_RXB_MISC, D_ALL);
1982 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
1983 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
1984 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
1985 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
1986
1987 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
1988 MMIO_D(PCH_PP_DIVISOR, D_ALL);
1989 MMIO_D(PCH_PP_STATUS, D_ALL);
1990 MMIO_D(PCH_LVDS, D_ALL);
1991 MMIO_D(_PCH_DPLL_A, D_ALL);
1992 MMIO_D(_PCH_DPLL_B, D_ALL);
1993 MMIO_D(_PCH_FPA0, D_ALL);
1994 MMIO_D(_PCH_FPA1, D_ALL);
1995 MMIO_D(_PCH_FPB0, D_ALL);
1996 MMIO_D(_PCH_FPB1, D_ALL);
1997 MMIO_D(PCH_DREF_CONTROL, D_ALL);
1998 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
1999 MMIO_D(PCH_DPLL_SEL, D_ALL);
2000
2001 MMIO_D(0x61208, D_ALL);
2002 MMIO_D(0x6120c, D_ALL);
2003 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2004 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2005
2006 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL);
2007 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
2008 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
2009 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
2010 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL);
2011 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL);
2012
2013 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2014 PORTA_HOTPLUG_STATUS_MASK
2015 | PORTB_HOTPLUG_STATUS_MASK
2016 | PORTC_HOTPLUG_STATUS_MASK
2017 | PORTD_HOTPLUG_STATUS_MASK,
2018 NULL, NULL);
2019
2020 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2021 MMIO_D(FUSE_STRAP, D_ALL);
2022 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2023
2024 MMIO_D(DISP_ARB_CTL, D_ALL);
2025 MMIO_D(DISP_ARB_CTL2, D_ALL);
2026
2027 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2028 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2029 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2030
2031 MMIO_D(SOUTH_CHICKEN1, D_ALL);
2032 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2033 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
2034 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
2035 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2036 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
2037 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
2038
2039 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2040 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2041 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2042 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2043 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2044 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2045 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2046
2047 MMIO_D(IPS_CTL, D_ALL);
2048
2049 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2050 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2051 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2052 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2053 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2054 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2055 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2056 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2057 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2058 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2059 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2060 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2061 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2062
2063 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2064 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2065 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2066 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2067 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2068 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2069 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2070 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2071 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2072 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2073 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2074 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2075 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2076
2077 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2078 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2079 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2080 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2081 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2082 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2083 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2084 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2085 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2086 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2087 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2088 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2089 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2090
2091 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2092 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2093 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2094
2095 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2096 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2097 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2098
2099 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2100 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2101 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2102
2103 MMIO_D(0x60110, D_ALL);
2104 MMIO_D(0x61110, D_ALL);
2105 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2106 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2107 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2108 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2109 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2110 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2111 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2112 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2113 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2114
2115 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2116 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2117 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2118 MMIO_D(SPLL_CTL, D_ALL);
2119 MMIO_D(_WRPLL_CTL1, D_ALL);
2120 MMIO_D(_WRPLL_CTL2, D_ALL);
2121 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2122 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2123 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2124 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2125 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2126 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2127 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2128 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2129
2130 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2131 MMIO_D(0x46508, D_ALL);
2132
2133 MMIO_D(0x49080, D_ALL);
2134 MMIO_D(0x49180, D_ALL);
2135 MMIO_D(0x49280, D_ALL);
2136
2137 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2138 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2139 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2140
2141 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2142 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2143 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2144
2145 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2146 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2147 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2148
2149 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2150 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2151 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2152
2153 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2154 MMIO_D(SBI_ADDR, D_ALL);
2155 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2156 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2157 MMIO_D(PIXCLK_GATE, D_ALL);
2158
2159 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL,
2160 dp_aux_ch_ctl_mmio_write);
2161
2162 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2163 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2164 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2165 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2166 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2167
2168 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2169 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2170 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2171 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2172 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2173
2174 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2175 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2176 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2177 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2178 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2179
2180 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2181 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2182 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2183 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2184 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2185
2186 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2187 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2188
2189 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL);
2190 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL);
2191 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL);
2192 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL);
2193
2194 MMIO_D(_TRANSA_MSA_MISC, D_ALL);
2195 MMIO_D(_TRANSB_MSA_MISC, D_ALL);
2196 MMIO_D(_TRANSC_MSA_MISC, D_ALL);
2197 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL);
2198
2199 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2200 MMIO_D(FORCEWAKE_ACK, D_ALL);
2201 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2202 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2203 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2204 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2205 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2206 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2207 MMIO_D(ECOBUS, D_ALL);
2208 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2209 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2210 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2211 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2212 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2213 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2214 MMIO_D(GEN6_RPSTAT1, D_ALL);
2215 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2216 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2217 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2218 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2219 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2220 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2221 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2222 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2223 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2224 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2225 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2226 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2227 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2228 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2229 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2230 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2231 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2232 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2233 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2234 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2235 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2236 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2237 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2238 /*
2239 * Use an arbitrary power well controlled by the PWR_WELL_CTL
2240 * register.
2241 */
2242 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2243 power_well_ctl_mmio_write);
2244 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2245 power_well_ctl_mmio_write);
2246 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
2247 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2248 power_well_ctl_mmio_write);
2249 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2250 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2251
2252 MMIO_D(RSTDBYCTL, D_ALL);
2253
2254 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2255 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2256 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2257
2258 MMIO_D(TILECTL, D_ALL);
2259
2260 MMIO_D(GEN6_UCGCTL1, D_ALL);
2261 MMIO_D(GEN6_UCGCTL2, D_ALL);
2262
2263 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2264
2265 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2266 MMIO_D(0x13812c, D_ALL);
2267 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2268 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2269 MMIO_D(HSW_IDICR, D_ALL);
2270 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2271
2272 MMIO_D(0x3c, D_ALL);
2273 MMIO_D(0x860, D_ALL);
2274 MMIO_D(ECOSKPD, D_ALL);
2275 MMIO_D(0x121d0, D_ALL);
2276 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2277 MMIO_D(0x41d0, D_ALL);
2278 MMIO_D(GAC_ECO_BITS, D_ALL);
2279 MMIO_D(0x6200, D_ALL);
2280 MMIO_D(0x6204, D_ALL);
2281 MMIO_D(0x6208, D_ALL);
2282 MMIO_D(0x7118, D_ALL);
2283 MMIO_D(0x7180, D_ALL);
2284 MMIO_D(0x7408, D_ALL);
2285 MMIO_D(0x7c00, D_ALL);
2286 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2287 MMIO_D(0x911c, D_ALL);
2288 MMIO_D(0x9120, D_ALL);
2289 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2290
2291 MMIO_D(GAB_CTL, D_ALL);
2292 MMIO_D(0x48800, D_ALL);
2293 MMIO_D(0xce044, D_ALL);
2294 MMIO_D(0xe6500, D_ALL);
2295 MMIO_D(0xe6504, D_ALL);
2296 MMIO_D(0xe6600, D_ALL);
2297 MMIO_D(0xe6604, D_ALL);
2298 MMIO_D(0xe6700, D_ALL);
2299 MMIO_D(0xe6704, D_ALL);
2300 MMIO_D(0xe6800, D_ALL);
2301 MMIO_D(0xe6804, D_ALL);
2302 MMIO_D(PCH_GMBUS4, D_ALL);
2303 MMIO_D(PCH_GMBUS5, D_ALL);
2304
2305 MMIO_D(0x902c, D_ALL);
2306 MMIO_D(0xec008, D_ALL);
2307 MMIO_D(0xec00c, D_ALL);
2308 MMIO_D(0xec008 + 0x18, D_ALL);
2309 MMIO_D(0xec00c + 0x18, D_ALL);
2310 MMIO_D(0xec008 + 0x18 * 2, D_ALL);
2311 MMIO_D(0xec00c + 0x18 * 2, D_ALL);
2312 MMIO_D(0xec008 + 0x18 * 3, D_ALL);
2313 MMIO_D(0xec00c + 0x18 * 3, D_ALL);
2314 MMIO_D(0xec408, D_ALL);
2315 MMIO_D(0xec40c, D_ALL);
2316 MMIO_D(0xec408 + 0x18, D_ALL);
2317 MMIO_D(0xec40c + 0x18, D_ALL);
2318 MMIO_D(0xec408 + 0x18 * 2, D_ALL);
2319 MMIO_D(0xec40c + 0x18 * 2, D_ALL);
2320 MMIO_D(0xec408 + 0x18 * 3, D_ALL);
2321 MMIO_D(0xec40c + 0x18 * 3, D_ALL);
2322 MMIO_D(0xfc810, D_ALL);
2323 MMIO_D(0xfc81c, D_ALL);
2324 MMIO_D(0xfc828, D_ALL);
2325 MMIO_D(0xfc834, D_ALL);
2326 MMIO_D(0xfcc00, D_ALL);
2327 MMIO_D(0xfcc0c, D_ALL);
2328 MMIO_D(0xfcc18, D_ALL);
2329 MMIO_D(0xfcc24, D_ALL);
2330 MMIO_D(0xfd000, D_ALL);
2331 MMIO_D(0xfd00c, D_ALL);
2332 MMIO_D(0xfd018, D_ALL);
2333 MMIO_D(0xfd024, D_ALL);
2334 MMIO_D(0xfd034, D_ALL);
2335
2336 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2337 MMIO_D(0x2054, D_ALL);
2338 MMIO_D(0x12054, D_ALL);
2339 MMIO_D(0x22054, D_ALL);
2340 MMIO_D(0x1a054, D_ALL);
2341
2342 MMIO_D(0x44070, D_ALL);
2343 MMIO_DFH(0x215c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2344 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2345 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2346 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2347 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2348
2349 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2350 MMIO_D(0x2b00, D_BDW_PLUS);
2351 MMIO_D(0x2360, D_BDW_PLUS);
2352 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2353 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2354 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2355
2356 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2357 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2358 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2359
2360 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2361 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2362 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2363 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2364 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2365 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2366 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2367 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2368 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2369 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2370 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2371 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2372 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2373 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2374 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2375 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2376 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2377
2378 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2379 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2380 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2381 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2382 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2383 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2384 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2385 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2386 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2387 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2388 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2389 return 0;
2390 }
2391
2392 static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2393 {
2394 struct drm_i915_private *dev_priv = gvt->dev_priv;
2395 int ret;
2396
2397 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2398 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2399 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2400 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2401
2402 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2403 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2404 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2405 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2406
2407 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2408 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2409 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2410 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2411
2412 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2413 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2414 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2415 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2416
2417 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2418 intel_vgpu_reg_imr_handler);
2419 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2420 intel_vgpu_reg_ier_handler);
2421 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2422 intel_vgpu_reg_iir_handler);
2423 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2424
2425 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2426 intel_vgpu_reg_imr_handler);
2427 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2428 intel_vgpu_reg_ier_handler);
2429 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2430 intel_vgpu_reg_iir_handler);
2431 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2432
2433 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2434 intel_vgpu_reg_imr_handler);
2435 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2436 intel_vgpu_reg_ier_handler);
2437 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2438 intel_vgpu_reg_iir_handler);
2439 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2440
2441 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2442 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2443 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2444 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2445
2446 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2447 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2448 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2449 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2450
2451 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2452 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2453 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2454 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2455
2456 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2457 intel_vgpu_reg_master_irq_handler);
2458
2459 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2460 mmio_read_from_hw, NULL);
2461
2462 #define RING_REG(base) (base + 0xd0)
2463 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2464 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2465 ring_reset_ctl_write);
2466 #undef RING_REG
2467
2468 #define RING_REG(base) (base + 0x230)
2469 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2470 #undef RING_REG
2471
2472 #define RING_REG(base) (base + 0x234)
2473 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2474 NULL, NULL);
2475 #undef RING_REG
2476
2477 #define RING_REG(base) (base + 0x244)
2478 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2479 #undef RING_REG
2480
2481 #define RING_REG(base) (base + 0x370)
2482 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2483 #undef RING_REG
2484
2485 #define RING_REG(base) (base + 0x3a0)
2486 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2487 #undef RING_REG
2488
2489 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2490 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2491 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2492 MMIO_D(0x1c1d0, D_BDW_PLUS);
2493 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2494 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2495 MMIO_D(0x1c054, D_BDW_PLUS);
2496
2497 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2498
2499 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2500 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2501
2502 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2503
2504 #define RING_REG(base) (base + 0x270)
2505 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2506 #undef RING_REG
2507
2508 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2509
2510 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2511
2512 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2513 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2514 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2515
2516 MMIO_D(WM_MISC, D_BDW);
2517 MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
2518
2519 MMIO_D(0x66c00, D_BDW_PLUS);
2520 MMIO_D(0x66c04, D_BDW_PLUS);
2521
2522 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2523
2524 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2525 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2526 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2527
2528 MMIO_D(0xfdc, D_BDW_PLUS);
2529 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2530 NULL, NULL);
2531 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2532 NULL, NULL);
2533 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2534
2535 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL);
2536 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL);
2537 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2538 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL);
2539 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL);
2540 MMIO_D(0xb110, D_BDW);
2541
2542 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2543 NULL, force_nonpriv_write);
2544
2545 MMIO_D(0x44484, D_BDW_PLUS);
2546 MMIO_D(0x4448c, D_BDW_PLUS);
2547
2548 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL);
2549 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2550
2551 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL);
2552
2553 MMIO_D(0x110000, D_BDW_PLUS);
2554
2555 MMIO_D(0x48400, D_BDW_PLUS);
2556
2557 MMIO_D(0x6e570, D_BDW_PLUS);
2558 MMIO_D(0x65f10, D_BDW_PLUS);
2559
2560 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2561 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2562 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2563 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2564
2565 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);
2566
2567 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2568 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2569 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2570 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2571 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2572 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2573 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2574 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2575 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2576 return 0;
2577 }
2578
2579 static int init_skl_mmio_info(struct intel_gvt *gvt)
2580 {
2581 struct drm_i915_private *dev_priv = gvt->dev_priv;
2582 int ret;
2583
2584 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2585 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2586 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2587 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2588 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2589 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2590
2591 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2592 dp_aux_ch_ctl_mmio_write);
2593 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2594 dp_aux_ch_ctl_mmio_write);
2595 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2596 dp_aux_ch_ctl_mmio_write);
2597
2598 /*
2599 * Use an arbitrary power well controlled by the PWR_WELL_CTL
2600 * register.
2601 */
2602 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
2603 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
2604 skl_power_well_ctl_write);
2605
2606 MMIO_D(0xa210, D_SKL_PLUS);
2607 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2608 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2609 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2610 MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, NULL);
2611 MMIO_DH(0x42080, D_SKL_PLUS, NULL, NULL);
2612 MMIO_D(0x45504, D_SKL_PLUS);
2613 MMIO_D(0x45520, D_SKL_PLUS);
2614 MMIO_D(0x46000, D_SKL_PLUS);
2615 MMIO_DH(0x46010, D_SKL | D_KBL, NULL, skl_lcpll_write);
2616 MMIO_DH(0x46014, D_SKL | D_KBL, NULL, skl_lcpll_write);
2617 MMIO_D(0x6C040, D_SKL | D_KBL);
2618 MMIO_D(0x6C048, D_SKL | D_KBL);
2619 MMIO_D(0x6C050, D_SKL | D_KBL);
2620 MMIO_D(0x6C044, D_SKL | D_KBL);
2621 MMIO_D(0x6C04C, D_SKL | D_KBL);
2622 MMIO_D(0x6C054, D_SKL | D_KBL);
2623 MMIO_D(0x6c058, D_SKL | D_KBL);
2624 MMIO_D(0x6c05c, D_SKL | D_KBL);
2625 MMIO_DH(0X6c060, D_SKL | D_KBL, dpll_status_read, NULL);
2626
2627 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2628 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2629 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2630 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2631 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2632 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2633
2634 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2635 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2636 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2637 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2638 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2639 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2640
2641 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2642 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2643 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2644 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2645 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2646 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2647
2648 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2649 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2650 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2651 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2652
2653 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2654 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2655 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2656 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2657
2658 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2659 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2660 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2661 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2662
2663 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2664 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2665 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2666
2667 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2668 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2669 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2670
2671 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2672 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2673 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2674
2675 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2676 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2677 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2678
2679 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2680 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2681 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2682
2683 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2684 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2685 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2686
2687 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2688 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2689 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2690
2691 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2692 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2693 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2694
2695 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2696 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2697 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2698
2699 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2700 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2701 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2702 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2703
2704 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2705 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2706 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2707 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2708
2709 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2710 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2711 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2712 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2713
2714 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2715 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2716 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2717 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL_PLUS, NULL, NULL);
2718
2719 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2720 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2721 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2722 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL_PLUS, NULL, NULL);
2723
2724 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2725 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2726 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2727 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL_PLUS, NULL, NULL);
2728
2729 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2730 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2731 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2732 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL_PLUS, NULL, NULL);
2733
2734 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2735 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2736 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2737 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL_PLUS, NULL, NULL);
2738
2739 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2740 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2741 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2742 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL_PLUS, NULL, NULL);
2743
2744 MMIO_D(0x70380, D_SKL_PLUS);
2745 MMIO_D(0x71380, D_SKL_PLUS);
2746 MMIO_D(0x72380, D_SKL_PLUS);
2747 MMIO_D(0x7039c, D_SKL_PLUS);
2748
2749 MMIO_D(0x8f074, D_SKL | D_KBL);
2750 MMIO_D(0x8f004, D_SKL | D_KBL);
2751 MMIO_D(0x8f034, D_SKL | D_KBL);
2752
2753 MMIO_D(0xb11c, D_SKL | D_KBL);
2754
2755 MMIO_D(0x51000, D_SKL | D_KBL);
2756 MMIO_D(0x6c00c, D_SKL_PLUS);
2757
2758 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2759 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2760
2761 MMIO_D(0xd08, D_SKL_PLUS);
2762 MMIO_DFH(0x20e0, D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
2763 MMIO_DFH(0x20ec, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2764
2765 /* TRTT */
2766 MMIO_DFH(0x4de0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2767 MMIO_DFH(0x4de4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2768 MMIO_DFH(0x4de8, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2769 MMIO_DFH(0x4dec, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2770 MMIO_DFH(0x4df0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2771 MMIO_DFH(0x4df4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write);
2772 MMIO_DH(0x4dfc, D_SKL | D_KBL, NULL, gen9_trtt_chicken_write);
2773
2774 MMIO_D(0x45008, D_SKL | D_KBL);
2775
2776 MMIO_D(0x46430, D_SKL | D_KBL);
2777
2778 MMIO_D(0x46520, D_SKL | D_KBL);
2779
2780 MMIO_D(0xc403c, D_SKL | D_KBL);
2781 MMIO_D(0xb004, D_SKL_PLUS);
2782 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2783
2784 MMIO_D(0x65900, D_SKL_PLUS);
2785 MMIO_D(0x1082c0, D_SKL | D_KBL);
2786 MMIO_D(0x4068, D_SKL | D_KBL);
2787 MMIO_D(0x67054, D_SKL | D_KBL);
2788 MMIO_D(0x6e560, D_SKL | D_KBL);
2789 MMIO_D(0x6e554, D_SKL | D_KBL);
2790 MMIO_D(0x2b20, D_SKL | D_KBL);
2791 MMIO_D(0x65f00, D_SKL | D_KBL);
2792 MMIO_D(0x65f08, D_SKL | D_KBL);
2793 MMIO_D(0x320f0, D_SKL | D_KBL);
2794
2795 MMIO_D(0x70034, D_SKL_PLUS);
2796 MMIO_D(0x71034, D_SKL_PLUS);
2797 MMIO_D(0x72034, D_SKL_PLUS);
2798
2799 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL_PLUS);
2800 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL_PLUS);
2801 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL_PLUS);
2802 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL_PLUS);
2803 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS);
2804 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS);
2805
2806 MMIO_D(0x44500, D_SKL_PLUS);
2807 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2808 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
2809 NULL, NULL);
2810
2811 MMIO_D(0x4ab8, D_KBL);
2812 MMIO_D(0x2248, D_SKL_PLUS | D_KBL);
2813
2814 return 0;
2815 }
2816
2817 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2818 unsigned int offset)
2819 {
2820 unsigned long device = intel_gvt_get_device_type(gvt);
2821 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2822 int num = gvt->mmio.num_mmio_block;
2823 int i;
2824
2825 for (i = 0; i < num; i++, block++) {
2826 if (!(device & block->device))
2827 continue;
2828 if (offset >= INTEL_GVT_MMIO_OFFSET(block->offset) &&
2829 offset < INTEL_GVT_MMIO_OFFSET(block->offset) + block->size)
2830 return block;
2831 }
2832 return NULL;
2833 }
2834
2835 /**
2836 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2837 * @gvt: GVT device
2838 *
2839 * This function is called at the driver unloading stage, to clean up the MMIO
2840 * information table of GVT device
2841 *
2842 */
2843 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2844 {
2845 struct hlist_node *tmp;
2846 struct intel_gvt_mmio_info *e;
2847 int i;
2848
2849 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2850 kfree(e);
2851
2852 vfree(gvt->mmio.mmio_attribute);
2853 gvt->mmio.mmio_attribute = NULL;
2854 }
2855
2856 /* Special MMIO blocks. */
2857 static struct gvt_mmio_block mmio_blocks[] = {
2858 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
2859 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
2860 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
2861 pvinfo_mmio_read, pvinfo_mmio_write},
2862 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
2863 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
2864 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
2865 };
2866
2867 /**
2868 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2869 * @gvt: GVT device
2870 *
2871 * This function is called at the initialization stage, to setup the MMIO
2872 * information table for GVT device
2873 *
2874 * Returns:
2875 * zero on success, negative if failed.
2876 */
2877 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2878 {
2879 struct intel_gvt_device_info *info = &gvt->device_info;
2880 struct drm_i915_private *dev_priv = gvt->dev_priv;
2881 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
2882 int ret;
2883
2884 gvt->mmio.mmio_attribute = vzalloc(size);
2885 if (!gvt->mmio.mmio_attribute)
2886 return -ENOMEM;
2887
2888 ret = init_generic_mmio_info(gvt);
2889 if (ret)
2890 goto err;
2891
2892 if (IS_BROADWELL(dev_priv)) {
2893 ret = init_broadwell_mmio_info(gvt);
2894 if (ret)
2895 goto err;
2896 } else if (IS_SKYLAKE(dev_priv)
2897 || IS_KABYLAKE(dev_priv)) {
2898 ret = init_broadwell_mmio_info(gvt);
2899 if (ret)
2900 goto err;
2901 ret = init_skl_mmio_info(gvt);
2902 if (ret)
2903 goto err;
2904 }
2905
2906 gvt->mmio.mmio_block = mmio_blocks;
2907 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
2908
2909 gvt_dbg_mmio("traced %u virtual mmio registers\n",
2910 gvt->mmio.num_tracked_mmio);
2911 return 0;
2912 err:
2913 intel_gvt_clean_mmio_info(gvt);
2914 return ret;
2915 }
2916
2917
2918 /**
2919 * intel_vgpu_default_mmio_read - default MMIO read handler
2920 * @vgpu: a vGPU
2921 * @offset: access offset
2922 * @p_data: data return buffer
2923 * @bytes: access data length
2924 *
2925 * Returns:
2926 * Zero on success, negative error code if failed.
2927 */
2928 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
2929 void *p_data, unsigned int bytes)
2930 {
2931 read_vreg(vgpu, offset, p_data, bytes);
2932 return 0;
2933 }
2934
2935 /**
2936 * intel_t_default_mmio_write - default MMIO write handler
2937 * @vgpu: a vGPU
2938 * @offset: access offset
2939 * @p_data: write data buffer
2940 * @bytes: access data length
2941 *
2942 * Returns:
2943 * Zero on success, negative error code if failed.
2944 */
2945 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2946 void *p_data, unsigned int bytes)
2947 {
2948 write_vreg(vgpu, offset, p_data, bytes);
2949 return 0;
2950 }
2951
2952 /**
2953 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
2954 * force-nopriv register
2955 *
2956 * @gvt: a GVT device
2957 * @offset: register offset
2958 *
2959 * Returns:
2960 * True if the register is in force-nonpriv whitelist;
2961 * False if outside;
2962 */
2963 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
2964 unsigned int offset)
2965 {
2966 return in_whitelist(offset);
2967 }
2968
2969 /**
2970 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
2971 * @vgpu: a vGPU
2972 * @offset: register offset
2973 * @pdata: data buffer
2974 * @bytes: data length
2975 *
2976 * Returns:
2977 * Zero on success, negative error code if failed.
2978 */
2979 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
2980 void *pdata, unsigned int bytes, bool is_read)
2981 {
2982 struct intel_gvt *gvt = vgpu->gvt;
2983 struct intel_gvt_mmio_info *mmio_info;
2984 struct gvt_mmio_block *mmio_block;
2985 gvt_mmio_func func;
2986 int ret;
2987
2988 if (WARN_ON(bytes > 8))
2989 return -EINVAL;
2990
2991 /*
2992 * Handle special MMIO blocks.
2993 */
2994 mmio_block = find_mmio_block(gvt, offset);
2995 if (mmio_block) {
2996 func = is_read ? mmio_block->read : mmio_block->write;
2997 if (func)
2998 return func(vgpu, offset, pdata, bytes);
2999 goto default_rw;
3000 }
3001
3002 /*
3003 * Normal tracked MMIOs.
3004 */
3005 mmio_info = find_mmio_info(gvt, offset);
3006 if (!mmio_info) {
3007 if (!vgpu->mmio.disable_warn_untrack)
3008 gvt_vgpu_err("untracked MMIO %08x len %d\n",
3009 offset, bytes);
3010 goto default_rw;
3011 }
3012
3013 if (is_read)
3014 return mmio_info->read(vgpu, offset, pdata, bytes);
3015 else {
3016 u64 ro_mask = mmio_info->ro_mask;
3017 u32 old_vreg = 0, old_sreg = 0;
3018 u64 data = 0;
3019
3020 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3021 old_vreg = vgpu_vreg(vgpu, offset);
3022 old_sreg = vgpu_sreg(vgpu, offset);
3023 }
3024
3025 if (likely(!ro_mask))
3026 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3027 else if (!~ro_mask) {
3028 gvt_vgpu_err("try to write RO reg %x\n", offset);
3029 return 0;
3030 } else {
3031 /* keep the RO bits in the virtual register */
3032 memcpy(&data, pdata, bytes);
3033 data &= ~ro_mask;
3034 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3035 ret = mmio_info->write(vgpu, offset, &data, bytes);
3036 }
3037
3038 /* higher 16bits of mode ctl regs are mask bits for change */
3039 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3040 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3041
3042 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3043 | (vgpu_vreg(vgpu, offset) & mask);
3044 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)
3045 | (vgpu_sreg(vgpu, offset) & mask);
3046 }
3047 }
3048
3049 return ret;
3050
3051 default_rw:
3052 return is_read ?
3053 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3054 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3055 }
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