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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/shli/md
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / i915 / gvt / handlers.c
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include "i915_drv.h"
40 #include "gvt.h"
41 #include "i915_pvinfo.h"
42
43 /* XXX FIXME i915 has changed PP_XXX definition */
44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
49
50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51 {
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
58
59 return 0;
60 }
61
62 bool intel_gvt_match_device(struct intel_gvt *gvt,
63 unsigned long device)
64 {
65 return intel_gvt_get_device_type(gvt) & device;
66 }
67
68 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
69 void *p_data, unsigned int bytes)
70 {
71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
72 }
73
74 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
75 void *p_data, unsigned int bytes)
76 {
77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
78 }
79
80 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
81 unsigned int offset)
82 {
83 struct intel_gvt_mmio_info *e;
84
85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
86 if (e->offset == offset)
87 return e;
88 }
89 return NULL;
90 }
91
92 static int new_mmio_info(struct intel_gvt *gvt,
93 u32 offset, u8 flags, u32 size,
94 u32 addr_mask, u32 ro_mask, u32 device,
95 gvt_mmio_func read, gvt_mmio_func write)
96 {
97 struct intel_gvt_mmio_info *info, *p;
98 u32 start, end, i;
99
100 if (!intel_gvt_match_device(gvt, device))
101 return 0;
102
103 if (WARN_ON(!IS_ALIGNED(offset, 4)))
104 return -EINVAL;
105
106 start = offset;
107 end = offset + size;
108
109 for (i = start; i < end; i += 4) {
110 info = kzalloc(sizeof(*info), GFP_KERNEL);
111 if (!info)
112 return -ENOMEM;
113
114 info->offset = i;
115 p = find_mmio_info(gvt, info->offset);
116 if (p) {
117 WARN(1, "dup mmio definition offset %x\n",
118 info->offset);
119 kfree(info);
120
121 /* We return -EEXIST here to make GVT-g load fail.
122 * So duplicated MMIO can be found as soon as
123 * possible.
124 */
125 return -EEXIST;
126 }
127
128 info->ro_mask = ro_mask;
129 info->device = device;
130 info->read = read ? read : intel_vgpu_default_mmio_read;
131 info->write = write ? write : intel_vgpu_default_mmio_write;
132 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
133 INIT_HLIST_NODE(&info->node);
134 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
135 gvt->mmio.num_tracked_mmio++;
136 }
137 return 0;
138 }
139
140 /**
141 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
142 * @gvt: a GVT device
143 * @offset: register offset
144 *
145 * Returns:
146 * Ring ID on success, negative error code if failed.
147 */
148 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
149 unsigned int offset)
150 {
151 enum intel_engine_id id;
152 struct intel_engine_cs *engine;
153
154 offset &= ~GENMASK(11, 0);
155 for_each_engine(engine, gvt->dev_priv, id) {
156 if (engine->mmio_base == offset)
157 return id;
158 }
159 return -ENODEV;
160 }
161
162 #define offset_to_fence_num(offset) \
163 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
164
165 #define fence_num_to_offset(num) \
166 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
167
168
169 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
170 {
171 switch (reason) {
172 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
173 pr_err("Detected your guest driver doesn't support GVT-g.\n");
174 break;
175 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
176 pr_err("Graphics resource is not enough for the guest\n");
177 break;
178 case GVT_FAILSAFE_GUEST_ERR:
179 pr_err("GVT Internal error for the guest\n");
180 break;
181 default:
182 break;
183 }
184 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
185 vgpu->failsafe = true;
186 }
187
188 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
189 unsigned int fence_num, void *p_data, unsigned int bytes)
190 {
191 unsigned int max_fence = vgpu_fence_sz(vgpu);
192
193 if (fence_num >= max_fence) {
194 gvt_vgpu_err("access oob fence reg %d/%d\n",
195 fence_num, max_fence);
196
197 /* When guest access oob fence regs without access
198 * pv_info first, we treat guest not supporting GVT,
199 * and we will let vgpu enter failsafe mode.
200 */
201 if (!vgpu->pv_notified)
202 enter_failsafe_mode(vgpu,
203 GVT_FAILSAFE_UNSUPPORTED_GUEST);
204
205 memset(p_data, 0, bytes);
206 return -EINVAL;
207 }
208 return 0;
209 }
210
211 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
212 void *p_data, unsigned int bytes)
213 {
214 int ret;
215
216 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
217 p_data, bytes);
218 if (ret)
219 return ret;
220 read_vreg(vgpu, off, p_data, bytes);
221 return 0;
222 }
223
224 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
225 void *p_data, unsigned int bytes)
226 {
227 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
228 unsigned int fence_num = offset_to_fence_num(off);
229 int ret;
230
231 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
232 if (ret)
233 return ret;
234 write_vreg(vgpu, off, p_data, bytes);
235
236 mmio_hw_access_pre(dev_priv);
237 intel_vgpu_write_fence(vgpu, fence_num,
238 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
239 mmio_hw_access_post(dev_priv);
240 return 0;
241 }
242
243 #define CALC_MODE_MASK_REG(old, new) \
244 (((new) & GENMASK(31, 16)) \
245 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
246 | ((new) & ((new) >> 16))))
247
248 static int mul_force_wake_write(struct intel_vgpu *vgpu,
249 unsigned int offset, void *p_data, unsigned int bytes)
250 {
251 u32 old, new;
252 uint32_t ack_reg_offset;
253
254 old = vgpu_vreg(vgpu, offset);
255 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
256
257 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
258 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
259 switch (offset) {
260 case FORCEWAKE_RENDER_GEN9_REG:
261 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
262 break;
263 case FORCEWAKE_BLITTER_GEN9_REG:
264 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
265 break;
266 case FORCEWAKE_MEDIA_GEN9_REG:
267 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
268 break;
269 default:
270 /*should not hit here*/
271 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
272 return -EINVAL;
273 }
274 } else {
275 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
276 }
277
278 vgpu_vreg(vgpu, offset) = new;
279 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
280 return 0;
281 }
282
283 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
284 void *p_data, unsigned int bytes)
285 {
286 unsigned int engine_mask = 0;
287 u32 data;
288
289 write_vreg(vgpu, offset, p_data, bytes);
290 data = vgpu_vreg(vgpu, offset);
291
292 if (data & GEN6_GRDOM_FULL) {
293 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
294 engine_mask = ALL_ENGINES;
295 } else {
296 if (data & GEN6_GRDOM_RENDER) {
297 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
298 engine_mask |= (1 << RCS);
299 }
300 if (data & GEN6_GRDOM_MEDIA) {
301 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
302 engine_mask |= (1 << VCS);
303 }
304 if (data & GEN6_GRDOM_BLT) {
305 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
306 engine_mask |= (1 << BCS);
307 }
308 if (data & GEN6_GRDOM_VECS) {
309 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
310 engine_mask |= (1 << VECS);
311 }
312 if (data & GEN8_GRDOM_MEDIA2) {
313 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
314 if (HAS_BSD2(vgpu->gvt->dev_priv))
315 engine_mask |= (1 << VCS2);
316 }
317 }
318
319 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
320
321 /* sw will wait for the device to ack the reset request */
322 vgpu_vreg(vgpu, offset) = 0;
323
324 return 0;
325 }
326
327 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
328 void *p_data, unsigned int bytes)
329 {
330 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
331 }
332
333 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
334 void *p_data, unsigned int bytes)
335 {
336 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
337 }
338
339 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
340 unsigned int offset, void *p_data, unsigned int bytes)
341 {
342 write_vreg(vgpu, offset, p_data, bytes);
343
344 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
345 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
346 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
347 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
348 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
349
350 } else
351 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
352 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
353 | PP_CYCLE_DELAY_ACTIVE);
354 return 0;
355 }
356
357 static int transconf_mmio_write(struct intel_vgpu *vgpu,
358 unsigned int offset, void *p_data, unsigned int bytes)
359 {
360 write_vreg(vgpu, offset, p_data, bytes);
361
362 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
363 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
364 else
365 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
366 return 0;
367 }
368
369 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
370 void *p_data, unsigned int bytes)
371 {
372 write_vreg(vgpu, offset, p_data, bytes);
373
374 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
375 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
376 else
377 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
378
379 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
380 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
381 else
382 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
383
384 return 0;
385 }
386
387 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
388 void *p_data, unsigned int bytes)
389 {
390 switch (offset) {
391 case 0xe651c:
392 case 0xe661c:
393 case 0xe671c:
394 case 0xe681c:
395 vgpu_vreg(vgpu, offset) = 1 << 17;
396 break;
397 case 0xe6c04:
398 vgpu_vreg(vgpu, offset) = 0x3;
399 break;
400 case 0xe6e1c:
401 vgpu_vreg(vgpu, offset) = 0x2f << 16;
402 break;
403 default:
404 return -EINVAL;
405 }
406
407 read_vreg(vgpu, offset, p_data, bytes);
408 return 0;
409 }
410
411 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
412 void *p_data, unsigned int bytes)
413 {
414 u32 data;
415
416 write_vreg(vgpu, offset, p_data, bytes);
417 data = vgpu_vreg(vgpu, offset);
418
419 if (data & PIPECONF_ENABLE)
420 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
421 else
422 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
423 intel_gvt_check_vblank_emulation(vgpu->gvt);
424 return 0;
425 }
426
427 /* ascendingly sorted */
428 static i915_reg_t force_nonpriv_white_list[] = {
429 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
430 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
431 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
432 _MMIO(0x2690),
433 _MMIO(0x2694),
434 _MMIO(0x2698),
435 _MMIO(0x4de0),
436 _MMIO(0x4de4),
437 _MMIO(0x4dfc),
438 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
439 _MMIO(0x7014),
440 HDC_CHICKEN0,//_MMIO(0x7300)
441 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
442 _MMIO(0x7700),
443 _MMIO(0x7704),
444 _MMIO(0x7708),
445 _MMIO(0x770c),
446 _MMIO(0xb110),
447 GEN8_L3SQCREG4,//_MMIO(0xb118)
448 _MMIO(0xe100),
449 _MMIO(0xe18c),
450 _MMIO(0xe48c),
451 _MMIO(0xe5f4),
452 };
453
454 /* a simple bsearch */
455 static inline bool in_whitelist(unsigned int reg)
456 {
457 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
458 i915_reg_t *array = force_nonpriv_white_list;
459
460 while (left < right) {
461 int mid = (left + right)/2;
462
463 if (reg > array[mid].reg)
464 left = mid + 1;
465 else if (reg < array[mid].reg)
466 right = mid;
467 else
468 return true;
469 }
470 return false;
471 }
472
473 static int force_nonpriv_write(struct intel_vgpu *vgpu,
474 unsigned int offset, void *p_data, unsigned int bytes)
475 {
476 u32 reg_nonpriv = *(u32 *)p_data;
477 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
478 u32 ring_base;
479 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
480 int ret = -EINVAL;
481
482 if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {
483 gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",
484 vgpu->id, ring_id, offset, bytes);
485 return ret;
486 }
487
488 ring_base = dev_priv->engine[ring_id]->mmio_base;
489
490 if (in_whitelist(reg_nonpriv) ||
491 reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
492 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
493 bytes);
494 } else
495 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
496 vgpu->id, reg_nonpriv, offset);
497
498 return 0;
499 }
500
501 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
502 void *p_data, unsigned int bytes)
503 {
504 write_vreg(vgpu, offset, p_data, bytes);
505
506 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
507 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
508 } else {
509 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
510 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
511 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
512 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
513 }
514 return 0;
515 }
516
517 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
518 unsigned int offset, void *p_data, unsigned int bytes)
519 {
520 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
521 return 0;
522 }
523
524 #define FDI_LINK_TRAIN_PATTERN1 0
525 #define FDI_LINK_TRAIN_PATTERN2 1
526
527 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
528 {
529 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
530 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
531 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
532
533 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
534 (rx_ctl & FDI_RX_ENABLE) &&
535 (rx_ctl & FDI_AUTO_TRAINING) &&
536 (tx_ctl & DP_TP_CTL_ENABLE) &&
537 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
538 return 1;
539 else
540 return 0;
541 }
542
543 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
544 enum pipe pipe, unsigned int train_pattern)
545 {
546 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
547 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
548 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
549 unsigned int fdi_iir_check_bits;
550
551 fdi_rx_imr = FDI_RX_IMR(pipe);
552 fdi_tx_ctl = FDI_TX_CTL(pipe);
553 fdi_rx_ctl = FDI_RX_CTL(pipe);
554
555 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
556 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
557 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
558 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
559 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
560 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
561 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
562 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
563 } else {
564 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
565 return -EINVAL;
566 }
567
568 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
569 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
570
571 /* If imr bit has been masked */
572 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
573 return 0;
574
575 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
576 == fdi_tx_check_bits)
577 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
578 == fdi_rx_check_bits))
579 return 1;
580 else
581 return 0;
582 }
583
584 #define INVALID_INDEX (~0U)
585
586 static unsigned int calc_index(unsigned int offset, unsigned int start,
587 unsigned int next, unsigned int end, i915_reg_t i915_end)
588 {
589 unsigned int range = next - start;
590
591 if (!end)
592 end = i915_mmio_reg_offset(i915_end);
593 if (offset < start || offset > end)
594 return INVALID_INDEX;
595 offset -= start;
596 return offset / range;
597 }
598
599 #define FDI_RX_CTL_TO_PIPE(offset) \
600 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
601
602 #define FDI_TX_CTL_TO_PIPE(offset) \
603 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
604
605 #define FDI_RX_IMR_TO_PIPE(offset) \
606 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
607
608 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
609 unsigned int offset, void *p_data, unsigned int bytes)
610 {
611 i915_reg_t fdi_rx_iir;
612 unsigned int index;
613 int ret;
614
615 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
616 index = FDI_RX_CTL_TO_PIPE(offset);
617 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
618 index = FDI_TX_CTL_TO_PIPE(offset);
619 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
620 index = FDI_RX_IMR_TO_PIPE(offset);
621 else {
622 gvt_vgpu_err("Unsupport registers %x\n", offset);
623 return -EINVAL;
624 }
625
626 write_vreg(vgpu, offset, p_data, bytes);
627
628 fdi_rx_iir = FDI_RX_IIR(index);
629
630 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
631 if (ret < 0)
632 return ret;
633 if (ret)
634 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
635
636 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
637 if (ret < 0)
638 return ret;
639 if (ret)
640 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
641
642 if (offset == _FDI_RXA_CTL)
643 if (fdi_auto_training_started(vgpu))
644 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
645 DP_TP_STATUS_AUTOTRAIN_DONE;
646 return 0;
647 }
648
649 #define DP_TP_CTL_TO_PORT(offset) \
650 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
651
652 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
653 void *p_data, unsigned int bytes)
654 {
655 i915_reg_t status_reg;
656 unsigned int index;
657 u32 data;
658
659 write_vreg(vgpu, offset, p_data, bytes);
660
661 index = DP_TP_CTL_TO_PORT(offset);
662 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
663 if (data == 0x2) {
664 status_reg = DP_TP_STATUS(index);
665 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
666 }
667 return 0;
668 }
669
670 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
671 unsigned int offset, void *p_data, unsigned int bytes)
672 {
673 u32 reg_val;
674 u32 sticky_mask;
675
676 reg_val = *((u32 *)p_data);
677 sticky_mask = GENMASK(27, 26) | (1 << 24);
678
679 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
680 (vgpu_vreg(vgpu, offset) & sticky_mask);
681 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
682 return 0;
683 }
684
685 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
686 unsigned int offset, void *p_data, unsigned int bytes)
687 {
688 u32 data;
689
690 write_vreg(vgpu, offset, p_data, bytes);
691 data = vgpu_vreg(vgpu, offset);
692
693 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
694 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
695 return 0;
696 }
697
698 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
699 unsigned int offset, void *p_data, unsigned int bytes)
700 {
701 u32 data;
702
703 write_vreg(vgpu, offset, p_data, bytes);
704 data = vgpu_vreg(vgpu, offset);
705
706 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
707 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
708 else
709 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
710 return 0;
711 }
712
713 #define DSPSURF_TO_PIPE(offset) \
714 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
715
716 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
717 void *p_data, unsigned int bytes)
718 {
719 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
720 unsigned int index = DSPSURF_TO_PIPE(offset);
721 i915_reg_t surflive_reg = DSPSURFLIVE(index);
722 int flip_event[] = {
723 [PIPE_A] = PRIMARY_A_FLIP_DONE,
724 [PIPE_B] = PRIMARY_B_FLIP_DONE,
725 [PIPE_C] = PRIMARY_C_FLIP_DONE,
726 };
727
728 write_vreg(vgpu, offset, p_data, bytes);
729 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
730
731 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
732 return 0;
733 }
734
735 #define SPRSURF_TO_PIPE(offset) \
736 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
737
738 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
739 void *p_data, unsigned int bytes)
740 {
741 unsigned int index = SPRSURF_TO_PIPE(offset);
742 i915_reg_t surflive_reg = SPRSURFLIVE(index);
743 int flip_event[] = {
744 [PIPE_A] = SPRITE_A_FLIP_DONE,
745 [PIPE_B] = SPRITE_B_FLIP_DONE,
746 [PIPE_C] = SPRITE_C_FLIP_DONE,
747 };
748
749 write_vreg(vgpu, offset, p_data, bytes);
750 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
751
752 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
753 return 0;
754 }
755
756 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
757 unsigned int reg)
758 {
759 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
760 enum intel_gvt_event_type event;
761
762 if (reg == _DPA_AUX_CH_CTL)
763 event = AUX_CHANNEL_A;
764 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
765 event = AUX_CHANNEL_B;
766 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
767 event = AUX_CHANNEL_C;
768 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
769 event = AUX_CHANNEL_D;
770 else {
771 WARN_ON(true);
772 return -EINVAL;
773 }
774
775 intel_vgpu_trigger_virtual_event(vgpu, event);
776 return 0;
777 }
778
779 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
780 unsigned int reg, int len, bool data_valid)
781 {
782 /* mark transaction done */
783 value |= DP_AUX_CH_CTL_DONE;
784 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
785 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
786
787 if (data_valid)
788 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
789 else
790 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
791
792 /* message size */
793 value &= ~(0xf << 20);
794 value |= (len << 20);
795 vgpu_vreg(vgpu, reg) = value;
796
797 if (value & DP_AUX_CH_CTL_INTERRUPT)
798 return trigger_aux_channel_interrupt(vgpu, reg);
799 return 0;
800 }
801
802 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
803 uint8_t t)
804 {
805 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
806 /* training pattern 1 for CR */
807 /* set LANE0_CR_DONE, LANE1_CR_DONE */
808 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
809 /* set LANE2_CR_DONE, LANE3_CR_DONE */
810 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
811 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
812 DPCD_TRAINING_PATTERN_2) {
813 /* training pattern 2 for EQ */
814 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
815 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
816 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
817 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
818 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
819 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
820 /* set INTERLANE_ALIGN_DONE */
821 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
822 DPCD_INTERLANE_ALIGN_DONE;
823 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
824 DPCD_LINK_TRAINING_DISABLED) {
825 /* finish link training */
826 /* set sink status as synchronized */
827 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
828 }
829 }
830
831 #define _REG_HSW_DP_AUX_CH_CTL(dp) \
832 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
833
834 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
835
836 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
837
838 #define dpy_is_valid_port(port) \
839 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
840
841 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
842 unsigned int offset, void *p_data, unsigned int bytes)
843 {
844 struct intel_vgpu_display *display = &vgpu->display;
845 int msg, addr, ctrl, op, len;
846 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
847 struct intel_vgpu_dpcd_data *dpcd = NULL;
848 struct intel_vgpu_port *port = NULL;
849 u32 data;
850
851 if (!dpy_is_valid_port(port_index)) {
852 gvt_vgpu_err("Unsupported DP port access!\n");
853 return 0;
854 }
855
856 write_vreg(vgpu, offset, p_data, bytes);
857 data = vgpu_vreg(vgpu, offset);
858
859 if ((IS_SKYLAKE(vgpu->gvt->dev_priv)
860 || IS_KABYLAKE(vgpu->gvt->dev_priv))
861 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
862 /* SKL DPB/C/D aux ctl register changed */
863 return 0;
864 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
865 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
866 /* write to the data registers */
867 return 0;
868 }
869
870 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
871 /* just want to clear the sticky bits */
872 vgpu_vreg(vgpu, offset) = 0;
873 return 0;
874 }
875
876 port = &display->ports[port_index];
877 dpcd = port->dpcd;
878
879 /* read out message from DATA1 register */
880 msg = vgpu_vreg(vgpu, offset + 4);
881 addr = (msg >> 8) & 0xffff;
882 ctrl = (msg >> 24) & 0xff;
883 len = msg & 0xff;
884 op = ctrl >> 4;
885
886 if (op == GVT_AUX_NATIVE_WRITE) {
887 int t;
888 uint8_t buf[16];
889
890 if ((addr + len + 1) >= DPCD_SIZE) {
891 /*
892 * Write request exceeds what we supported,
893 * DCPD spec: When a Source Device is writing a DPCD
894 * address not supported by the Sink Device, the Sink
895 * Device shall reply with AUX NACK and “M” equal to
896 * zero.
897 */
898
899 /* NAK the write */
900 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
901 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
902 return 0;
903 }
904
905 /*
906 * Write request format: (command + address) occupies
907 * 3 bytes, followed by (len + 1) bytes of data.
908 */
909 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
910 return -EINVAL;
911
912 /* unpack data from vreg to buf */
913 for (t = 0; t < 4; t++) {
914 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
915
916 buf[t * 4] = (r >> 24) & 0xff;
917 buf[t * 4 + 1] = (r >> 16) & 0xff;
918 buf[t * 4 + 2] = (r >> 8) & 0xff;
919 buf[t * 4 + 3] = r & 0xff;
920 }
921
922 /* write to virtual DPCD */
923 if (dpcd && dpcd->data_valid) {
924 for (t = 0; t <= len; t++) {
925 int p = addr + t;
926
927 dpcd->data[p] = buf[t];
928 /* check for link training */
929 if (p == DPCD_TRAINING_PATTERN_SET)
930 dp_aux_ch_ctl_link_training(dpcd,
931 buf[t]);
932 }
933 }
934
935 /* ACK the write */
936 vgpu_vreg(vgpu, offset + 4) = 0;
937 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
938 dpcd && dpcd->data_valid);
939 return 0;
940 }
941
942 if (op == GVT_AUX_NATIVE_READ) {
943 int idx, i, ret = 0;
944
945 if ((addr + len + 1) >= DPCD_SIZE) {
946 /*
947 * read request exceeds what we supported
948 * DPCD spec: A Sink Device receiving a Native AUX CH
949 * read request for an unsupported DPCD address must
950 * reply with an AUX ACK and read data set equal to
951 * zero instead of replying with AUX NACK.
952 */
953
954 /* ACK the READ*/
955 vgpu_vreg(vgpu, offset + 4) = 0;
956 vgpu_vreg(vgpu, offset + 8) = 0;
957 vgpu_vreg(vgpu, offset + 12) = 0;
958 vgpu_vreg(vgpu, offset + 16) = 0;
959 vgpu_vreg(vgpu, offset + 20) = 0;
960
961 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
962 true);
963 return 0;
964 }
965
966 for (idx = 1; idx <= 5; idx++) {
967 /* clear the data registers */
968 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
969 }
970
971 /*
972 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
973 */
974 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
975 return -EINVAL;
976
977 /* read from virtual DPCD to vreg */
978 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
979 if (dpcd && dpcd->data_valid) {
980 for (i = 1; i <= (len + 1); i++) {
981 int t;
982
983 t = dpcd->data[addr + i - 1];
984 t <<= (24 - 8 * (i % 4));
985 ret |= t;
986
987 if ((i % 4 == 3) || (i == (len + 1))) {
988 vgpu_vreg(vgpu, offset +
989 (i / 4 + 1) * 4) = ret;
990 ret = 0;
991 }
992 }
993 }
994 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
995 dpcd && dpcd->data_valid);
996 return 0;
997 }
998
999 /* i2c transaction starts */
1000 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1001
1002 if (data & DP_AUX_CH_CTL_INTERRUPT)
1003 trigger_aux_channel_interrupt(vgpu, offset);
1004 return 0;
1005 }
1006
1007 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1008 void *p_data, unsigned int bytes)
1009 {
1010 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1011 write_vreg(vgpu, offset, p_data, bytes);
1012 return 0;
1013 }
1014
1015 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1016 void *p_data, unsigned int bytes)
1017 {
1018 bool vga_disable;
1019
1020 write_vreg(vgpu, offset, p_data, bytes);
1021 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1022
1023 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1024 vga_disable ? "Disable" : "Enable");
1025 return 0;
1026 }
1027
1028 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1029 unsigned int sbi_offset)
1030 {
1031 struct intel_vgpu_display *display = &vgpu->display;
1032 int num = display->sbi.number;
1033 int i;
1034
1035 for (i = 0; i < num; ++i)
1036 if (display->sbi.registers[i].offset == sbi_offset)
1037 break;
1038
1039 if (i == num)
1040 return 0;
1041
1042 return display->sbi.registers[i].value;
1043 }
1044
1045 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1046 unsigned int offset, u32 value)
1047 {
1048 struct intel_vgpu_display *display = &vgpu->display;
1049 int num = display->sbi.number;
1050 int i;
1051
1052 for (i = 0; i < num; ++i) {
1053 if (display->sbi.registers[i].offset == offset)
1054 break;
1055 }
1056
1057 if (i == num) {
1058 if (num == SBI_REG_MAX) {
1059 gvt_vgpu_err("SBI caching meets maximum limits\n");
1060 return;
1061 }
1062 display->sbi.number++;
1063 }
1064
1065 display->sbi.registers[i].offset = offset;
1066 display->sbi.registers[i].value = value;
1067 }
1068
1069 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1070 void *p_data, unsigned int bytes)
1071 {
1072 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1073 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1074 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1075 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1076 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1077 sbi_offset);
1078 }
1079 read_vreg(vgpu, offset, p_data, bytes);
1080 return 0;
1081 }
1082
1083 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1084 void *p_data, unsigned int bytes)
1085 {
1086 u32 data;
1087
1088 write_vreg(vgpu, offset, p_data, bytes);
1089 data = vgpu_vreg(vgpu, offset);
1090
1091 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1092 data |= SBI_READY;
1093
1094 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1095 data |= SBI_RESPONSE_SUCCESS;
1096
1097 vgpu_vreg(vgpu, offset) = data;
1098
1099 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1100 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1101 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1102 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1103
1104 write_virtual_sbi_register(vgpu, sbi_offset,
1105 vgpu_vreg_t(vgpu, SBI_DATA));
1106 }
1107 return 0;
1108 }
1109
1110 #define _vgtif_reg(x) \
1111 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1112
1113 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1114 void *p_data, unsigned int bytes)
1115 {
1116 bool invalid_read = false;
1117
1118 read_vreg(vgpu, offset, p_data, bytes);
1119
1120 switch (offset) {
1121 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1122 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1123 invalid_read = true;
1124 break;
1125 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1126 _vgtif_reg(avail_rs.fence_num):
1127 if (offset + bytes >
1128 _vgtif_reg(avail_rs.fence_num) + 4)
1129 invalid_read = true;
1130 break;
1131 case 0x78010: /* vgt_caps */
1132 case 0x7881c:
1133 break;
1134 default:
1135 invalid_read = true;
1136 break;
1137 }
1138 if (invalid_read)
1139 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1140 offset, bytes, *(u32 *)p_data);
1141 vgpu->pv_notified = true;
1142 return 0;
1143 }
1144
1145 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1146 {
1147 intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1148 struct intel_vgpu_mm *mm;
1149 u64 *pdps;
1150
1151 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1152
1153 switch (notification) {
1154 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1155 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1156 /* fall through */
1157 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1158 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1159 return PTR_ERR_OR_ZERO(mm);
1160 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1161 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1162 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1163 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1164 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1165 case 1: /* Remove this in guest driver. */
1166 break;
1167 default:
1168 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1169 }
1170 return 0;
1171 }
1172
1173 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1174 {
1175 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1176 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1177 char *env[3] = {NULL, NULL, NULL};
1178 char vmid_str[20];
1179 char display_ready_str[20];
1180
1181 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1182 env[0] = display_ready_str;
1183
1184 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1185 env[1] = vmid_str;
1186
1187 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1188 }
1189
1190 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1191 void *p_data, unsigned int bytes)
1192 {
1193 u32 data;
1194 int ret;
1195
1196 write_vreg(vgpu, offset, p_data, bytes);
1197 data = vgpu_vreg(vgpu, offset);
1198
1199 switch (offset) {
1200 case _vgtif_reg(display_ready):
1201 send_display_ready_uevent(vgpu, data ? 1 : 0);
1202 break;
1203 case _vgtif_reg(g2v_notify):
1204 ret = handle_g2v_notification(vgpu, data);
1205 break;
1206 /* add xhot and yhot to handled list to avoid error log */
1207 case 0x78830:
1208 case 0x78834:
1209 case _vgtif_reg(pdp[0].lo):
1210 case _vgtif_reg(pdp[0].hi):
1211 case _vgtif_reg(pdp[1].lo):
1212 case _vgtif_reg(pdp[1].hi):
1213 case _vgtif_reg(pdp[2].lo):
1214 case _vgtif_reg(pdp[2].hi):
1215 case _vgtif_reg(pdp[3].lo):
1216 case _vgtif_reg(pdp[3].hi):
1217 case _vgtif_reg(execlist_context_descriptor_lo):
1218 case _vgtif_reg(execlist_context_descriptor_hi):
1219 break;
1220 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1221 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1222 break;
1223 default:
1224 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1225 offset, bytes, data);
1226 break;
1227 }
1228 return 0;
1229 }
1230
1231 static int pf_write(struct intel_vgpu *vgpu,
1232 unsigned int offset, void *p_data, unsigned int bytes)
1233 {
1234 u32 val = *(u32 *)p_data;
1235
1236 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1237 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1238 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1239 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1240 vgpu->id);
1241 return 0;
1242 }
1243
1244 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1245 }
1246
1247 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1248 unsigned int offset, void *p_data, unsigned int bytes)
1249 {
1250 write_vreg(vgpu, offset, p_data, bytes);
1251
1252 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
1253 vgpu_vreg(vgpu, offset) |=
1254 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
1255 else
1256 vgpu_vreg(vgpu, offset) &=
1257 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
1258 return 0;
1259 }
1260
1261 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1262 unsigned int offset, void *p_data, unsigned int bytes)
1263 {
1264 write_vreg(vgpu, offset, p_data, bytes);
1265
1266 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1267 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1268 return 0;
1269 }
1270
1271 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1272 void *p_data, unsigned int bytes)
1273 {
1274 u32 mode;
1275
1276 write_vreg(vgpu, offset, p_data, bytes);
1277 mode = vgpu_vreg(vgpu, offset);
1278
1279 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1280 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
1281 vgpu->id);
1282 return 0;
1283 }
1284
1285 return 0;
1286 }
1287
1288 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1289 void *p_data, unsigned int bytes)
1290 {
1291 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1292 u32 trtte = *(u32 *)p_data;
1293
1294 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1295 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1296 vgpu->id);
1297 return -EINVAL;
1298 }
1299 write_vreg(vgpu, offset, p_data, bytes);
1300 /* TRTTE is not per-context */
1301
1302 mmio_hw_access_pre(dev_priv);
1303 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
1304 mmio_hw_access_post(dev_priv);
1305
1306 return 0;
1307 }
1308
1309 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1310 void *p_data, unsigned int bytes)
1311 {
1312 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1313 u32 val = *(u32 *)p_data;
1314
1315 if (val & 1) {
1316 /* unblock hw logic */
1317 mmio_hw_access_pre(dev_priv);
1318 I915_WRITE(_MMIO(offset), val);
1319 mmio_hw_access_post(dev_priv);
1320 }
1321 write_vreg(vgpu, offset, p_data, bytes);
1322 return 0;
1323 }
1324
1325 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1326 void *p_data, unsigned int bytes)
1327 {
1328 u32 v = 0;
1329
1330 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1331 v |= (1 << 0);
1332
1333 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1334 v |= (1 << 8);
1335
1336 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1337 v |= (1 << 16);
1338
1339 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1340 v |= (1 << 24);
1341
1342 vgpu_vreg(vgpu, offset) = v;
1343
1344 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1345 }
1346
1347 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1348 void *p_data, unsigned int bytes)
1349 {
1350 u32 value = *(u32 *)p_data;
1351 u32 cmd = value & 0xff;
1352 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1353
1354 switch (cmd) {
1355 case GEN9_PCODE_READ_MEM_LATENCY:
1356 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1357 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {
1358 /**
1359 * "Read memory latency" command on gen9.
1360 * Below memory latency values are read
1361 * from skylake platform.
1362 */
1363 if (!*data0)
1364 *data0 = 0x1e1a1100;
1365 else
1366 *data0 = 0x61514b3d;
1367 }
1368 break;
1369 case SKL_PCODE_CDCLK_CONTROL:
1370 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
1371 || IS_KABYLAKE(vgpu->gvt->dev_priv))
1372 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1373 break;
1374 case GEN6_PCODE_READ_RC6VIDS:
1375 *data0 |= 0x1;
1376 break;
1377 }
1378
1379 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1380 vgpu->id, value, *data0);
1381 /**
1382 * PCODE_READY clear means ready for pcode read/write,
1383 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1384 * always emulate as pcode read/write success and ready for access
1385 * anytime, since we don't touch real physical registers here.
1386 */
1387 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1388 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1389 }
1390
1391 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1392 void *p_data, unsigned int bytes)
1393 {
1394 u32 value = *(u32 *)p_data;
1395 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1396
1397 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1398 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1399 offset, value);
1400 return -EINVAL;
1401 }
1402 /*
1403 * Need to emulate all the HWSP register write to ensure host can
1404 * update the VM CSB status correctly. Here listed registers can
1405 * support BDW, SKL or other platforms with same HWSP registers.
1406 */
1407 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) {
1408 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1409 offset);
1410 return -EINVAL;
1411 }
1412 vgpu->hws_pga[ring_id] = value;
1413 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1414 vgpu->id, value, offset);
1415
1416 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1417 }
1418
1419 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1420 unsigned int offset, void *p_data, unsigned int bytes)
1421 {
1422 u32 v = *(u32 *)p_data;
1423
1424 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1425 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1426 v |= (v >> 1);
1427
1428 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1429 }
1430
1431 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1432 void *p_data, unsigned int bytes)
1433 {
1434 u32 v = *(u32 *)p_data;
1435
1436 /* other bits are MBZ. */
1437 v &= (1 << 31) | (1 << 30);
1438 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1439
1440 vgpu_vreg(vgpu, offset) = v;
1441
1442 return 0;
1443 }
1444
1445 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1446 unsigned int offset, void *p_data, unsigned int bytes)
1447 {
1448 struct intel_gvt *gvt = vgpu->gvt;
1449 struct drm_i915_private *dev_priv = gvt->dev_priv;
1450 int ring_id;
1451 u32 ring_base;
1452
1453 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset);
1454 /**
1455 * Read HW reg in following case
1456 * a. the offset isn't a ring mmio
1457 * b. the offset's ring is running on hw.
1458 * c. the offset is ring time stamp mmio
1459 */
1460 if (ring_id >= 0)
1461 ring_base = dev_priv->engine[ring_id]->mmio_base;
1462
1463 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] ||
1464 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) ||
1465 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) {
1466 mmio_hw_access_pre(dev_priv);
1467 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1468 mmio_hw_access_post(dev_priv);
1469 }
1470
1471 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1472 }
1473
1474 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1475 void *p_data, unsigned int bytes)
1476 {
1477 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1478 struct intel_vgpu_execlist *execlist;
1479 u32 data = *(u32 *)p_data;
1480 int ret = 0;
1481
1482 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
1483 return -EINVAL;
1484
1485 execlist = &vgpu->submission.execlist[ring_id];
1486
1487 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
1488 if (execlist->elsp_dwords.index == 3) {
1489 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
1490 if(ret)
1491 gvt_vgpu_err("fail submit workload on ring %d\n",
1492 ring_id);
1493 }
1494
1495 ++execlist->elsp_dwords.index;
1496 execlist->elsp_dwords.index &= 0x3;
1497 return ret;
1498 }
1499
1500 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1501 void *p_data, unsigned int bytes)
1502 {
1503 u32 data = *(u32 *)p_data;
1504 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1505 bool enable_execlist;
1506 int ret;
1507
1508 write_vreg(vgpu, offset, p_data, bytes);
1509
1510 /* when PPGTT mode enabled, we will check if guest has called
1511 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1512 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1513 */
1514 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1515 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1516 && !vgpu->pv_notified) {
1517 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1518 return 0;
1519 }
1520 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1521 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1522 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1523
1524 gvt_dbg_core("EXECLIST %s on ring %d\n",
1525 (enable_execlist ? "enabling" : "disabling"),
1526 ring_id);
1527
1528 if (!enable_execlist)
1529 return 0;
1530
1531 ret = intel_vgpu_select_submission_ops(vgpu,
1532 ENGINE_MASK(ring_id),
1533 INTEL_VGPU_EXECLIST_SUBMISSION);
1534 if (ret)
1535 return ret;
1536
1537 intel_vgpu_start_schedule(vgpu);
1538 }
1539 return 0;
1540 }
1541
1542 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1543 unsigned int offset, void *p_data, unsigned int bytes)
1544 {
1545 unsigned int id = 0;
1546
1547 write_vreg(vgpu, offset, p_data, bytes);
1548 vgpu_vreg(vgpu, offset) = 0;
1549
1550 switch (offset) {
1551 case 0x4260:
1552 id = RCS;
1553 break;
1554 case 0x4264:
1555 id = VCS;
1556 break;
1557 case 0x4268:
1558 id = VCS2;
1559 break;
1560 case 0x426c:
1561 id = BCS;
1562 break;
1563 case 0x4270:
1564 id = VECS;
1565 break;
1566 default:
1567 return -EINVAL;
1568 }
1569 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
1570
1571 return 0;
1572 }
1573
1574 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1575 unsigned int offset, void *p_data, unsigned int bytes)
1576 {
1577 u32 data;
1578
1579 write_vreg(vgpu, offset, p_data, bytes);
1580 data = vgpu_vreg(vgpu, offset);
1581
1582 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1583 data |= RESET_CTL_READY_TO_RESET;
1584 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1585 data &= ~RESET_CTL_READY_TO_RESET;
1586
1587 vgpu_vreg(vgpu, offset) = data;
1588 return 0;
1589 }
1590
1591 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1592 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
1593 f, s, am, rm, d, r, w); \
1594 if (ret) \
1595 return ret; \
1596 } while (0)
1597
1598 #define MMIO_D(reg, d) \
1599 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1600
1601 #define MMIO_DH(reg, d, r, w) \
1602 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1603
1604 #define MMIO_DFH(reg, d, f, r, w) \
1605 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1606
1607 #define MMIO_GM(reg, d, r, w) \
1608 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1609
1610 #define MMIO_GM_RDR(reg, d, r, w) \
1611 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1612
1613 #define MMIO_RO(reg, d, f, rm, r, w) \
1614 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1615
1616 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1617 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1618 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1619 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1620 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1621 if (HAS_BSD2(dev_priv)) \
1622 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
1623 } while (0)
1624
1625 #define MMIO_RING_D(prefix, d) \
1626 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1627
1628 #define MMIO_RING_DFH(prefix, d, f, r, w) \
1629 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1630
1631 #define MMIO_RING_GM(prefix, d, r, w) \
1632 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1633
1634 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
1635 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1636
1637 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1638 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1639
1640 static int init_generic_mmio_info(struct intel_gvt *gvt)
1641 {
1642 struct drm_i915_private *dev_priv = gvt->dev_priv;
1643 int ret;
1644
1645 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1646 intel_vgpu_reg_imr_handler);
1647
1648 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1649 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1650 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1651 MMIO_D(SDEISR, D_ALL);
1652
1653 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
1654
1655 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1656 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1657 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1658 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1659
1660 #define RING_REG(base) _MMIO((base) + 0x28)
1661 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1662 #undef RING_REG
1663
1664 #define RING_REG(base) _MMIO((base) + 0x134)
1665 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
1666 #undef RING_REG
1667
1668 #define RING_REG(base) _MMIO((base) + 0x6c)
1669 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
1670 #undef RING_REG
1671 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
1672
1673 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
1674 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1675 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
1676 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1677
1678 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1679 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1680 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1681 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
1682 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
1683
1684 /* RING MODE */
1685 #define RING_REG(base) _MMIO((base) + 0x29c)
1686 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1687 ring_mode_mmio_write);
1688 #undef RING_REG
1689
1690 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1691 NULL, NULL);
1692 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1693 NULL, NULL);
1694 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1695 mmio_read_from_hw, NULL);
1696 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1697 mmio_read_from_hw, NULL);
1698
1699 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1700 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1701 NULL, NULL);
1702 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1703 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1704 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1705
1706 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1707 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1708 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1709 MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1710 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1711 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1712 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1713 NULL, NULL);
1714 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1715 NULL, NULL);
1716 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
1717 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
1718 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
1719 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
1720 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
1721 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
1722 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
1723 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1724 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1725 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1726
1727 /* display */
1728 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1729 MMIO_D(_MMIO(0x602a0), D_ALL);
1730
1731 MMIO_D(_MMIO(0x65050), D_ALL);
1732 MMIO_D(_MMIO(0x650b4), D_ALL);
1733
1734 MMIO_D(_MMIO(0xc4040), D_ALL);
1735 MMIO_D(DERRMR, D_ALL);
1736
1737 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1738 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1739 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1740 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1741
1742 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1743 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1744 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1745 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
1746
1747 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1748 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1749 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1750 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1751
1752 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1753 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1754 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1755 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1756
1757 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1758 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1759 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1760 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1761
1762 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1763 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1764 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1765
1766 MMIO_D(CURPOS(PIPE_A), D_ALL);
1767 MMIO_D(CURPOS(PIPE_B), D_ALL);
1768 MMIO_D(CURPOS(PIPE_C), D_ALL);
1769
1770 MMIO_D(CURBASE(PIPE_A), D_ALL);
1771 MMIO_D(CURBASE(PIPE_B), D_ALL);
1772 MMIO_D(CURBASE(PIPE_C), D_ALL);
1773
1774 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
1775 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
1776 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
1777
1778 MMIO_D(_MMIO(0x700ac), D_ALL);
1779 MMIO_D(_MMIO(0x710ac), D_ALL);
1780 MMIO_D(_MMIO(0x720ac), D_ALL);
1781
1782 MMIO_D(_MMIO(0x70090), D_ALL);
1783 MMIO_D(_MMIO(0x70094), D_ALL);
1784 MMIO_D(_MMIO(0x70098), D_ALL);
1785 MMIO_D(_MMIO(0x7009c), D_ALL);
1786
1787 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1788 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1789 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1790 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1791 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
1792 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
1793 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1794 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1795
1796 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1797 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1798 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1799 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1800 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
1801 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
1802 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1803 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1804
1805 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1806 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1807 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1808 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1809 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
1810 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
1811 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1812 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1813
1814 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1815 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1816 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1817 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1818 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1819 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1820 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
1821 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
1822 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1823 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1824 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1825 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1826
1827 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1828 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1829 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1830 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1831 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1832 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1833 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
1834 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
1835 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1836 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1837 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1838 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1839
1840 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1841 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1842 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1843 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1844 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1845 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1846 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
1847 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
1848 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1849 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1850 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1851 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1852
1853 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
1854 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
1855 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
1856 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
1857 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
1858 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
1859 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
1860 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
1861 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
1862
1863 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
1864 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
1865 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
1866 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
1867 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
1868 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
1869 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
1870 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
1871 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
1872
1873 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
1874 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
1875 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
1876 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
1877 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
1878 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
1879 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
1880 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
1881 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
1882
1883 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
1884 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
1885 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
1886 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
1887 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
1888 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
1889 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
1890 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
1891
1892 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
1893 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
1894 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
1895 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
1896 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
1897 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
1898 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
1899 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
1900
1901 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
1902 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
1903 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
1904 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
1905 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
1906 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
1907 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
1908 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
1909
1910 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
1911 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
1912 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
1913 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
1914 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
1915 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
1916 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
1917 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
1918
1919 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
1920 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
1921 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
1922 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
1923 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
1924 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
1925 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
1926 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
1927
1928 MMIO_D(PF_CTL(PIPE_A), D_ALL);
1929 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
1930 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
1931 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
1932 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
1933
1934 MMIO_D(PF_CTL(PIPE_B), D_ALL);
1935 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
1936 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
1937 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
1938 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
1939
1940 MMIO_D(PF_CTL(PIPE_C), D_ALL);
1941 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
1942 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
1943 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
1944 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
1945
1946 MMIO_D(WM0_PIPEA_ILK, D_ALL);
1947 MMIO_D(WM0_PIPEB_ILK, D_ALL);
1948 MMIO_D(WM0_PIPEC_IVB, D_ALL);
1949 MMIO_D(WM1_LP_ILK, D_ALL);
1950 MMIO_D(WM2_LP_ILK, D_ALL);
1951 MMIO_D(WM3_LP_ILK, D_ALL);
1952 MMIO_D(WM1S_LP_ILK, D_ALL);
1953 MMIO_D(WM2S_LP_IVB, D_ALL);
1954 MMIO_D(WM3S_LP_IVB, D_ALL);
1955
1956 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1957 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1958 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1959 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1960
1961 MMIO_D(_MMIO(0x48268), D_ALL);
1962
1963 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1964 gmbus_mmio_write);
1965 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
1966 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1967
1968 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1969 dp_aux_ch_ctl_mmio_write);
1970 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1971 dp_aux_ch_ctl_mmio_write);
1972 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1973 dp_aux_ch_ctl_mmio_write);
1974
1975 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
1976
1977 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
1978 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
1979
1980 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1981 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1982 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1983 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1984 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1985 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1986 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1987 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1988 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1989
1990 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
1991 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
1992 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
1993 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
1994 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
1995 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
1996 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
1997
1998 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
1999 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
2000 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
2001 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
2002 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
2003 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
2004 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
2005
2006 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2007 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2008 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2009 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2010 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2011 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2012 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2013 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
2014
2015 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2016 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2017 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2018
2019 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2020 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2021 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2022
2023 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2024 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2025 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2026
2027 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2028 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2029 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2030
2031 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2032 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2033 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2034 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2035 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2036 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
2037
2038 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2039 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2040 MMIO_D(PCH_PP_STATUS, D_ALL);
2041 MMIO_D(PCH_LVDS, D_ALL);
2042 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2043 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2044 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2045 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2046 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2047 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
2048 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2049 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2050 MMIO_D(PCH_DPLL_SEL, D_ALL);
2051
2052 MMIO_D(_MMIO(0x61208), D_ALL);
2053 MMIO_D(_MMIO(0x6120c), D_ALL);
2054 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2055 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2056
2057 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2058 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2059 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2060 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2061 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2062 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2063
2064 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2065 PORTA_HOTPLUG_STATUS_MASK
2066 | PORTB_HOTPLUG_STATUS_MASK
2067 | PORTC_HOTPLUG_STATUS_MASK
2068 | PORTD_HOTPLUG_STATUS_MASK,
2069 NULL, NULL);
2070
2071 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2072 MMIO_D(FUSE_STRAP, D_ALL);
2073 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2074
2075 MMIO_D(DISP_ARB_CTL, D_ALL);
2076 MMIO_D(DISP_ARB_CTL2, D_ALL);
2077
2078 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2079 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2080 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2081
2082 MMIO_D(SOUTH_CHICKEN1, D_ALL);
2083 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2084 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2085 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
2086 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
2087 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2088 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
2089
2090 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2091 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2092 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2093 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2094 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2095 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2096 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2097
2098 MMIO_D(IPS_CTL, D_ALL);
2099
2100 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2101 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2102 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2103 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2104 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2105 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2106 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2107 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2108 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2109 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2110 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2111 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2112 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2113
2114 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2115 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2116 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2117 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2118 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2119 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2120 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2121 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2122 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2123 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2124 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2125 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2126 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2127
2128 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2129 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2130 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2131 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2132 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2133 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2134 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2135 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2136 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2137 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2138 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2139 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2140 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2141
2142 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2143 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2144 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2145
2146 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2147 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2148 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2149
2150 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2151 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2152 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2153
2154 MMIO_D(_MMIO(0x60110), D_ALL);
2155 MMIO_D(_MMIO(0x61110), D_ALL);
2156 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2157 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2158 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2159 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2160 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2161 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2162 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2163 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2164 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2165
2166 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2167 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2168 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2169 MMIO_D(SPLL_CTL, D_ALL);
2170 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2171 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
2172 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2173 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2174 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2175 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2176 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2177 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2178 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2179 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2180
2181 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2182 MMIO_D(_MMIO(0x46508), D_ALL);
2183
2184 MMIO_D(_MMIO(0x49080), D_ALL);
2185 MMIO_D(_MMIO(0x49180), D_ALL);
2186 MMIO_D(_MMIO(0x49280), D_ALL);
2187
2188 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2189 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2190 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2191
2192 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2193 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2194 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2195
2196 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2197 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2198 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2199
2200 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2201 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2202 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2203
2204 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2205 MMIO_D(SBI_ADDR, D_ALL);
2206 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2207 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2208 MMIO_D(PIXCLK_GATE, D_ALL);
2209
2210 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
2211 dp_aux_ch_ctl_mmio_write);
2212
2213 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2214 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2215 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2216 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2217 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2218
2219 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2220 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2221 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2222 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2223 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2224
2225 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2226 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2227 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2228 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2229 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2230
2231 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2232 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2233 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2234 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2235 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2236
2237 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2238 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2239 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
2240
2241 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2242 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2243 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2244 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2245
2246 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2247 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2248 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2249 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
2250
2251 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2252 MMIO_D(FORCEWAKE_ACK, D_ALL);
2253 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2254 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2255 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2256 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2257 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2258 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2259 MMIO_D(ECOBUS, D_ALL);
2260 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2261 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2262 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2263 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2264 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2265 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2266 MMIO_D(GEN6_RPSTAT1, D_ALL);
2267 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2268 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2269 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2270 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2271 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2272 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2273 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2274 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2275 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2276 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2277 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2278 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2279 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2280 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2281 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2282 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2283 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2284 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2285 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2286 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2287 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2288 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2289 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2290 /*
2291 * Use an arbitrary power well controlled by the PWR_WELL_CTL
2292 * register.
2293 */
2294 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2295 power_well_ctl_mmio_write);
2296 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2297 power_well_ctl_mmio_write);
2298 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
2299 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2300 power_well_ctl_mmio_write);
2301 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2302 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2303
2304 MMIO_D(RSTDBYCTL, D_ALL);
2305
2306 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2307 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2308 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2309
2310 MMIO_D(TILECTL, D_ALL);
2311
2312 MMIO_D(GEN6_UCGCTL1, D_ALL);
2313 MMIO_D(GEN6_UCGCTL2, D_ALL);
2314
2315 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2316
2317 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2318 MMIO_D(_MMIO(0x13812c), D_ALL);
2319 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2320 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2321 MMIO_D(HSW_IDICR, D_ALL);
2322 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2323
2324 MMIO_D(_MMIO(0x3c), D_ALL);
2325 MMIO_D(_MMIO(0x860), D_ALL);
2326 MMIO_D(ECOSKPD, D_ALL);
2327 MMIO_D(_MMIO(0x121d0), D_ALL);
2328 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2329 MMIO_D(_MMIO(0x41d0), D_ALL);
2330 MMIO_D(GAC_ECO_BITS, D_ALL);
2331 MMIO_D(_MMIO(0x6200), D_ALL);
2332 MMIO_D(_MMIO(0x6204), D_ALL);
2333 MMIO_D(_MMIO(0x6208), D_ALL);
2334 MMIO_D(_MMIO(0x7118), D_ALL);
2335 MMIO_D(_MMIO(0x7180), D_ALL);
2336 MMIO_D(_MMIO(0x7408), D_ALL);
2337 MMIO_D(_MMIO(0x7c00), D_ALL);
2338 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2339 MMIO_D(_MMIO(0x911c), D_ALL);
2340 MMIO_D(_MMIO(0x9120), D_ALL);
2341 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2342
2343 MMIO_D(GAB_CTL, D_ALL);
2344 MMIO_D(_MMIO(0x48800), D_ALL);
2345 MMIO_D(_MMIO(0xce044), D_ALL);
2346 MMIO_D(_MMIO(0xe6500), D_ALL);
2347 MMIO_D(_MMIO(0xe6504), D_ALL);
2348 MMIO_D(_MMIO(0xe6600), D_ALL);
2349 MMIO_D(_MMIO(0xe6604), D_ALL);
2350 MMIO_D(_MMIO(0xe6700), D_ALL);
2351 MMIO_D(_MMIO(0xe6704), D_ALL);
2352 MMIO_D(_MMIO(0xe6800), D_ALL);
2353 MMIO_D(_MMIO(0xe6804), D_ALL);
2354 MMIO_D(PCH_GMBUS4, D_ALL);
2355 MMIO_D(PCH_GMBUS5, D_ALL);
2356
2357 MMIO_D(_MMIO(0x902c), D_ALL);
2358 MMIO_D(_MMIO(0xec008), D_ALL);
2359 MMIO_D(_MMIO(0xec00c), D_ALL);
2360 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2361 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2362 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2363 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2364 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2365 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2366 MMIO_D(_MMIO(0xec408), D_ALL);
2367 MMIO_D(_MMIO(0xec40c), D_ALL);
2368 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2369 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2370 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2371 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2372 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2373 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2374 MMIO_D(_MMIO(0xfc810), D_ALL);
2375 MMIO_D(_MMIO(0xfc81c), D_ALL);
2376 MMIO_D(_MMIO(0xfc828), D_ALL);
2377 MMIO_D(_MMIO(0xfc834), D_ALL);
2378 MMIO_D(_MMIO(0xfcc00), D_ALL);
2379 MMIO_D(_MMIO(0xfcc0c), D_ALL);
2380 MMIO_D(_MMIO(0xfcc18), D_ALL);
2381 MMIO_D(_MMIO(0xfcc24), D_ALL);
2382 MMIO_D(_MMIO(0xfd000), D_ALL);
2383 MMIO_D(_MMIO(0xfd00c), D_ALL);
2384 MMIO_D(_MMIO(0xfd018), D_ALL);
2385 MMIO_D(_MMIO(0xfd024), D_ALL);
2386 MMIO_D(_MMIO(0xfd034), D_ALL);
2387
2388 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2389 MMIO_D(_MMIO(0x2054), D_ALL);
2390 MMIO_D(_MMIO(0x12054), D_ALL);
2391 MMIO_D(_MMIO(0x22054), D_ALL);
2392 MMIO_D(_MMIO(0x1a054), D_ALL);
2393
2394 MMIO_D(_MMIO(0x44070), D_ALL);
2395 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2396 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2397 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2398 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2399 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2400
2401 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2402 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2403 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2404 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2405 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2406 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2407
2408 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2409 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2410 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2411
2412 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2413 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2414 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2415 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2416 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2417 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2418 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2419 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2420 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2421 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2422 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2423 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2424 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2425 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2426 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2427 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2428 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2429
2430 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2431 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2432 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2433 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2434 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2435 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2436 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2437 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2438 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2439 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2440 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2441 return 0;
2442 }
2443
2444 static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2445 {
2446 struct drm_i915_private *dev_priv = gvt->dev_priv;
2447 int ret;
2448
2449 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2450 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2451 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2452 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2453
2454 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2455 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2456 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2457 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2458
2459 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2460 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2461 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2462 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2463
2464 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2465 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2466 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2467 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2468
2469 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2470 intel_vgpu_reg_imr_handler);
2471 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2472 intel_vgpu_reg_ier_handler);
2473 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2474 intel_vgpu_reg_iir_handler);
2475 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2476
2477 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2478 intel_vgpu_reg_imr_handler);
2479 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2480 intel_vgpu_reg_ier_handler);
2481 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2482 intel_vgpu_reg_iir_handler);
2483 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2484
2485 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2486 intel_vgpu_reg_imr_handler);
2487 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2488 intel_vgpu_reg_ier_handler);
2489 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2490 intel_vgpu_reg_iir_handler);
2491 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2492
2493 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2494 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2495 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2496 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2497
2498 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2499 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2500 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2501 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2502
2503 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2504 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2505 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2506 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2507
2508 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2509 intel_vgpu_reg_master_irq_handler);
2510
2511 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2512 mmio_read_from_hw, NULL);
2513
2514 #define RING_REG(base) _MMIO((base) + 0xd0)
2515 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2516 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2517 ring_reset_ctl_write);
2518 #undef RING_REG
2519
2520 #define RING_REG(base) _MMIO((base) + 0x230)
2521 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2522 #undef RING_REG
2523
2524 #define RING_REG(base) _MMIO((base) + 0x234)
2525 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2526 NULL, NULL);
2527 #undef RING_REG
2528
2529 #define RING_REG(base) _MMIO((base) + 0x244)
2530 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2531 #undef RING_REG
2532
2533 #define RING_REG(base) _MMIO((base) + 0x370)
2534 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2535 #undef RING_REG
2536
2537 #define RING_REG(base) _MMIO((base) + 0x3a0)
2538 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2539 #undef RING_REG
2540
2541 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2542 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2543 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2544 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
2545 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2546 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2547 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
2548
2549 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2550
2551 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2552 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2553
2554 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2555
2556 #define RING_REG(base) _MMIO((base) + 0x270)
2557 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2558 #undef RING_REG
2559
2560 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2561
2562 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2563
2564 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2565 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2566 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2567
2568 MMIO_D(WM_MISC, D_BDW);
2569 MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW);
2570
2571 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
2572 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2573 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
2574
2575 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2576
2577 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2578 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2579 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2580
2581 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
2582 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2583 NULL, NULL);
2584 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2585 NULL, NULL);
2586 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2587
2588 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2589 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2590 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2591 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2592 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2593 MMIO_D(_MMIO(0xb110), D_BDW);
2594
2595 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2596 NULL, force_nonpriv_write);
2597
2598 MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2599 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
2600
2601 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2602 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2603
2604 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2605
2606 MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
2607
2608 MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
2609
2610 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2611 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
2612
2613 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2614 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2615 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2616 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2617
2618 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2619
2620 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2621 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2622 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2623 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2624 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2625 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2626 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2627 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2628 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2629 return 0;
2630 }
2631
2632 static int init_skl_mmio_info(struct intel_gvt *gvt)
2633 {
2634 struct drm_i915_private *dev_priv = gvt->dev_priv;
2635 int ret;
2636
2637 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2638 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2639 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2640 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2641 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2642 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2643
2644 MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2645 dp_aux_ch_ctl_mmio_write);
2646 MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2647 dp_aux_ch_ctl_mmio_write);
2648 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2649 dp_aux_ch_ctl_mmio_write);
2650
2651 /*
2652 * Use an arbitrary power well controlled by the PWR_WELL_CTL
2653 * register.
2654 */
2655 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
2656 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
2657 skl_power_well_ctl_write);
2658
2659 MMIO_D(_MMIO(0xa210), D_SKL_PLUS);
2660 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2661 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2662 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2663 MMIO_DH(_MMIO(0x4ddc), D_SKL_PLUS, NULL, NULL);
2664 MMIO_DH(_MMIO(0x42080), D_SKL_PLUS, NULL, NULL);
2665 MMIO_D(_MMIO(0x45504), D_SKL_PLUS);
2666 MMIO_D(_MMIO(0x45520), D_SKL_PLUS);
2667 MMIO_D(_MMIO(0x46000), D_SKL_PLUS);
2668 MMIO_DH(_MMIO(0x46010), D_SKL | D_KBL, NULL, skl_lcpll_write);
2669 MMIO_DH(_MMIO(0x46014), D_SKL | D_KBL, NULL, skl_lcpll_write);
2670 MMIO_D(_MMIO(0x6C040), D_SKL | D_KBL);
2671 MMIO_D(_MMIO(0x6C048), D_SKL | D_KBL);
2672 MMIO_D(_MMIO(0x6C050), D_SKL | D_KBL);
2673 MMIO_D(_MMIO(0x6C044), D_SKL | D_KBL);
2674 MMIO_D(_MMIO(0x6C04C), D_SKL | D_KBL);
2675 MMIO_D(_MMIO(0x6C054), D_SKL | D_KBL);
2676 MMIO_D(_MMIO(0x6c058), D_SKL | D_KBL);
2677 MMIO_D(_MMIO(0x6c05c), D_SKL | D_KBL);
2678 MMIO_DH(_MMIO(0x6c060), D_SKL | D_KBL, dpll_status_read, NULL);
2679
2680 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2681 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2682 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2683 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2684 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2685 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2686
2687 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2688 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2689 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2690 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2691 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2692 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2693
2694 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2695 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2696 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2697 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2698 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2699 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2700
2701 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2702 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2703 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2704 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2705
2706 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2707 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2708 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2709 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2710
2711 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2712 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2713 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2714 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2715
2716 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2717 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2718 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2719
2720 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2721 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2722 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2723
2724 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2725 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2726 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2727
2728 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2729 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2730 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2731
2732 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2733 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2734 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2735
2736 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2737 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2738 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2739
2740 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2741 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2742 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2743
2744 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2745 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2746 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2747
2748 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2749 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2750 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2751
2752 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2753 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2754 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2755 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2756
2757 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2758 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2759 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2760 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2761
2762 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2763 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2764 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2765 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2766
2767 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
2768 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
2769 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
2770 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
2771
2772 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
2773 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
2774 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
2775 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
2776
2777 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
2778 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
2779 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
2780 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
2781
2782 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
2783 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
2784 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
2785 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
2786
2787 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
2788 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
2789 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
2790 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
2791
2792 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
2793 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
2794 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
2795 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
2796
2797 MMIO_D(_MMIO(0x70380), D_SKL_PLUS);
2798 MMIO_D(_MMIO(0x71380), D_SKL_PLUS);
2799 MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
2800 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
2801 MMIO_D(_MMIO(0x7039c), D_SKL_PLUS);
2802
2803 MMIO_D(_MMIO(0x8f074), D_SKL | D_KBL);
2804 MMIO_D(_MMIO(0x8f004), D_SKL | D_KBL);
2805 MMIO_D(_MMIO(0x8f034), D_SKL | D_KBL);
2806
2807 MMIO_D(_MMIO(0xb11c), D_SKL | D_KBL);
2808
2809 MMIO_D(_MMIO(0x51000), D_SKL | D_KBL);
2810 MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS);
2811
2812 MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2813 MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
2814
2815 MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
2816 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
2817 MMIO_D(RC6_LOCATION, D_SKL_PLUS);
2818 MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
2819 MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2820
2821 /* TRTT */
2822 MMIO_DFH(_MMIO(0x4de0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2823 MMIO_DFH(_MMIO(0x4de4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2824 MMIO_DFH(_MMIO(0x4de8), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2825 MMIO_DFH(_MMIO(0x4dec), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2826 MMIO_DFH(_MMIO(0x4df0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
2827 MMIO_DFH(_MMIO(0x4df4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write);
2828 MMIO_DH(_MMIO(0x4dfc), D_SKL | D_KBL, NULL, gen9_trtt_chicken_write);
2829
2830 MMIO_D(_MMIO(0x45008), D_SKL | D_KBL);
2831
2832 MMIO_D(_MMIO(0x46430), D_SKL | D_KBL);
2833
2834 MMIO_D(_MMIO(0x46520), D_SKL | D_KBL);
2835
2836 MMIO_D(_MMIO(0xc403c), D_SKL | D_KBL);
2837 MMIO_D(_MMIO(0xb004), D_SKL_PLUS);
2838 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2839
2840 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
2841 MMIO_D(_MMIO(0x1082c0), D_SKL | D_KBL);
2842 MMIO_D(_MMIO(0x4068), D_SKL | D_KBL);
2843 MMIO_D(_MMIO(0x67054), D_SKL | D_KBL);
2844 MMIO_D(_MMIO(0x6e560), D_SKL | D_KBL);
2845 MMIO_D(_MMIO(0x6e554), D_SKL | D_KBL);
2846 MMIO_D(_MMIO(0x2b20), D_SKL | D_KBL);
2847 MMIO_D(_MMIO(0x65f00), D_SKL | D_KBL);
2848 MMIO_D(_MMIO(0x65f08), D_SKL | D_KBL);
2849 MMIO_D(_MMIO(0x320f0), D_SKL | D_KBL);
2850
2851 MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
2852 MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
2853 MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
2854
2855 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
2856 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
2857 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
2858 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
2859 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
2860 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
2861 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
2862 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
2863 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
2864
2865 MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
2866 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2867 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
2868 NULL, NULL);
2869
2870 MMIO_D(_MMIO(0x4ab8), D_KBL);
2871 MMIO_D(_MMIO(0x2248), D_SKL_PLUS | D_KBL);
2872
2873 return 0;
2874 }
2875
2876 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2877 unsigned int offset)
2878 {
2879 unsigned long device = intel_gvt_get_device_type(gvt);
2880 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2881 int num = gvt->mmio.num_mmio_block;
2882 int i;
2883
2884 for (i = 0; i < num; i++, block++) {
2885 if (!(device & block->device))
2886 continue;
2887 if (offset >= i915_mmio_reg_offset(block->offset) &&
2888 offset < i915_mmio_reg_offset(block->offset) + block->size)
2889 return block;
2890 }
2891 return NULL;
2892 }
2893
2894 /**
2895 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2896 * @gvt: GVT device
2897 *
2898 * This function is called at the driver unloading stage, to clean up the MMIO
2899 * information table of GVT device
2900 *
2901 */
2902 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2903 {
2904 struct hlist_node *tmp;
2905 struct intel_gvt_mmio_info *e;
2906 int i;
2907
2908 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2909 kfree(e);
2910
2911 vfree(gvt->mmio.mmio_attribute);
2912 gvt->mmio.mmio_attribute = NULL;
2913 }
2914
2915 /* Special MMIO blocks. */
2916 static struct gvt_mmio_block mmio_blocks[] = {
2917 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
2918 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
2919 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
2920 pvinfo_mmio_read, pvinfo_mmio_write},
2921 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
2922 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
2923 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
2924 };
2925
2926 /**
2927 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2928 * @gvt: GVT device
2929 *
2930 * This function is called at the initialization stage, to setup the MMIO
2931 * information table for GVT device
2932 *
2933 * Returns:
2934 * zero on success, negative if failed.
2935 */
2936 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2937 {
2938 struct intel_gvt_device_info *info = &gvt->device_info;
2939 struct drm_i915_private *dev_priv = gvt->dev_priv;
2940 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
2941 int ret;
2942
2943 gvt->mmio.mmio_attribute = vzalloc(size);
2944 if (!gvt->mmio.mmio_attribute)
2945 return -ENOMEM;
2946
2947 ret = init_generic_mmio_info(gvt);
2948 if (ret)
2949 goto err;
2950
2951 if (IS_BROADWELL(dev_priv)) {
2952 ret = init_broadwell_mmio_info(gvt);
2953 if (ret)
2954 goto err;
2955 } else if (IS_SKYLAKE(dev_priv)
2956 || IS_KABYLAKE(dev_priv)) {
2957 ret = init_broadwell_mmio_info(gvt);
2958 if (ret)
2959 goto err;
2960 ret = init_skl_mmio_info(gvt);
2961 if (ret)
2962 goto err;
2963 }
2964
2965 gvt->mmio.mmio_block = mmio_blocks;
2966 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
2967
2968 return 0;
2969 err:
2970 intel_gvt_clean_mmio_info(gvt);
2971 return ret;
2972 }
2973
2974 /**
2975 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
2976 * @gvt: a GVT device
2977 * @handler: the handler
2978 * @data: private data given to handler
2979 *
2980 * Returns:
2981 * Zero on success, negative error code if failed.
2982 */
2983 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
2984 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
2985 void *data)
2986 {
2987 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2988 struct intel_gvt_mmio_info *e;
2989 int i, j, ret;
2990
2991 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
2992 ret = handler(gvt, e->offset, data);
2993 if (ret)
2994 return ret;
2995 }
2996
2997 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
2998 for (j = 0; j < block->size; j += 4) {
2999 ret = handler(gvt,
3000 i915_mmio_reg_offset(block->offset) + j,
3001 data);
3002 if (ret)
3003 return ret;
3004 }
3005 }
3006 return 0;
3007 }
3008
3009 /**
3010 * intel_vgpu_default_mmio_read - default MMIO read handler
3011 * @vgpu: a vGPU
3012 * @offset: access offset
3013 * @p_data: data return buffer
3014 * @bytes: access data length
3015 *
3016 * Returns:
3017 * Zero on success, negative error code if failed.
3018 */
3019 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3020 void *p_data, unsigned int bytes)
3021 {
3022 read_vreg(vgpu, offset, p_data, bytes);
3023 return 0;
3024 }
3025
3026 /**
3027 * intel_t_default_mmio_write - default MMIO write handler
3028 * @vgpu: a vGPU
3029 * @offset: access offset
3030 * @p_data: write data buffer
3031 * @bytes: access data length
3032 *
3033 * Returns:
3034 * Zero on success, negative error code if failed.
3035 */
3036 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3037 void *p_data, unsigned int bytes)
3038 {
3039 write_vreg(vgpu, offset, p_data, bytes);
3040 return 0;
3041 }
3042
3043 /**
3044 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3045 * force-nopriv register
3046 *
3047 * @gvt: a GVT device
3048 * @offset: register offset
3049 *
3050 * Returns:
3051 * True if the register is in force-nonpriv whitelist;
3052 * False if outside;
3053 */
3054 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3055 unsigned int offset)
3056 {
3057 return in_whitelist(offset);
3058 }
3059
3060 /**
3061 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3062 * @vgpu: a vGPU
3063 * @offset: register offset
3064 * @pdata: data buffer
3065 * @bytes: data length
3066 *
3067 * Returns:
3068 * Zero on success, negative error code if failed.
3069 */
3070 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3071 void *pdata, unsigned int bytes, bool is_read)
3072 {
3073 struct intel_gvt *gvt = vgpu->gvt;
3074 struct intel_gvt_mmio_info *mmio_info;
3075 struct gvt_mmio_block *mmio_block;
3076 gvt_mmio_func func;
3077 int ret;
3078
3079 if (WARN_ON(bytes > 8))
3080 return -EINVAL;
3081
3082 /*
3083 * Handle special MMIO blocks.
3084 */
3085 mmio_block = find_mmio_block(gvt, offset);
3086 if (mmio_block) {
3087 func = is_read ? mmio_block->read : mmio_block->write;
3088 if (func)
3089 return func(vgpu, offset, pdata, bytes);
3090 goto default_rw;
3091 }
3092
3093 /*
3094 * Normal tracked MMIOs.
3095 */
3096 mmio_info = find_mmio_info(gvt, offset);
3097 if (!mmio_info) {
3098 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3099 goto default_rw;
3100 }
3101
3102 if (is_read)
3103 return mmio_info->read(vgpu, offset, pdata, bytes);
3104 else {
3105 u64 ro_mask = mmio_info->ro_mask;
3106 u32 old_vreg = 0, old_sreg = 0;
3107 u64 data = 0;
3108
3109 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3110 old_vreg = vgpu_vreg(vgpu, offset);
3111 old_sreg = vgpu_sreg(vgpu, offset);
3112 }
3113
3114 if (likely(!ro_mask))
3115 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3116 else if (!~ro_mask) {
3117 gvt_vgpu_err("try to write RO reg %x\n", offset);
3118 return 0;
3119 } else {
3120 /* keep the RO bits in the virtual register */
3121 memcpy(&data, pdata, bytes);
3122 data &= ~ro_mask;
3123 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3124 ret = mmio_info->write(vgpu, offset, &data, bytes);
3125 }
3126
3127 /* higher 16bits of mode ctl regs are mask bits for change */
3128 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3129 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3130
3131 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3132 | (vgpu_vreg(vgpu, offset) & mask);
3133 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)
3134 | (vgpu_sreg(vgpu, offset) & mask);
3135 }
3136 }
3137
3138 return ret;
3139
3140 default_rw:
3141 return is_read ?
3142 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3143 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3144 }
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