drivers/gpu/drm/i915/gvt/mmio.h

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Dexuan Cui
  27  *
  28  * Contributors:
  29  *    Tina Zhang <tina.zhang@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Niu Bing <bing.niu@intel.com>
  32  *    Zhi Wang <zhi.a.wang@intel.com>
  33  *
  34  */
  35
  36 #ifndef _GVT_MMIO_H_
  37 #define _GVT_MMIO_H_
  38
  39 struct intel_gvt;
  40 struct intel_vgpu;
  41
  42 #define D_SNB   (1 << 0)
  43 #define D_IVB   (1 << 1)
  44 #define D_HSW   (1 << 2)
  45 #define D_BDW   (1 << 3)
  46 #define D_SKL   (1 << 4)
  47
  48 #define D_GEN9PLUS      (D_SKL)
  49 #define D_GEN8PLUS      (D_BDW | D_SKL)
  50 #define D_GEN75PLUS     (D_HSW | D_BDW | D_SKL)
  51 #define D_GEN7PLUS      (D_IVB | D_HSW | D_BDW | D_SKL)
  52
  53 #define D_SKL_PLUS      (D_SKL)
  54 #define D_BDW_PLUS      (D_BDW | D_SKL)
  55 #define D_HSW_PLUS      (D_HSW | D_BDW | D_SKL)
  56 #define D_IVB_PLUS      (D_IVB | D_HSW | D_BDW | D_SKL)
  57
  58 #define D_PRE_BDW       (D_SNB | D_IVB | D_HSW)
  59 #define D_PRE_SKL       (D_SNB | D_IVB | D_HSW | D_BDW)
  60 #define D_ALL           (D_SNB | D_IVB | D_HSW | D_BDW | D_SKL)
  61
  62 struct intel_gvt_mmio_info {
  63         u32 offset;
  64         u32 size;
  65         u32 length;
  66         u32 addr_mask;
  67         u64 ro_mask;
  68         u32 device;
  69         int (*read)(struct intel_vgpu *, unsigned int, void *, unsigned int);
  70         int (*write)(struct intel_vgpu *, unsigned int, void *, unsigned int);
  71         u32 addr_range;
  72         struct hlist_node node;
  73 };
  74
  75 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
  76 bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
  77
  78 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
  79 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
  80
  81 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
  82                                                      unsigned int offset);
  83 #define INTEL_GVT_MMIO_OFFSET(reg) ({ \
  84         typeof(reg) __reg = reg; \
  85         u32 *offset = (u32 *)&__reg; \
  86         *offset; \
  87 })
  88
  89 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
  90 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu);
  91 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
  92
  93 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);
  94
  95 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
  96                                 void *p_data, unsigned int bytes);
  97 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
  98                                 void *p_data, unsigned int bytes);
  99 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt,
 100                                   unsigned int offset);
 101 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, unsigned int offset);
 102 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset);
 103 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt,
 104                                      unsigned int offset);
 105 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset);
 106 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
 107                                  void *p_data, unsigned int bytes);
 108 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 109                                   void *p_data, unsigned int bytes);
 110 #endif