2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Zhi Wang <zhi.a.wang@intel.com>
27 * Ping Gao <ping.a.gao@intel.com>
28 * Tina Zhang <tina.zhang@intel.com>
29 * Chanbin Du <changbin.du@intel.com>
30 * Min He <min.he@intel.com>
31 * Bing Niu <bing.niu@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
36 #include <linux/kthread.h>
41 #define RING_CTX_OFF(x) \
42 offsetof(struct execlist_ring_context, x)
44 static void set_context_pdp_root_pointer(
45 struct execlist_ring_context
*ring_context
,
48 struct execlist_mmio_pair
*pdp_pair
= &ring_context
->pdp3_UDW
;
51 for (i
= 0; i
< 8; i
++)
52 pdp_pair
[i
].val
= pdp
[7 - i
];
55 static int populate_shadow_context(struct intel_vgpu_workload
*workload
)
57 struct intel_vgpu
*vgpu
= workload
->vgpu
;
58 struct intel_gvt
*gvt
= vgpu
->gvt
;
59 int ring_id
= workload
->ring_id
;
60 struct i915_gem_context
*shadow_ctx
= workload
->vgpu
->shadow_ctx
;
61 struct drm_i915_gem_object
*ctx_obj
=
62 shadow_ctx
->engine
[ring_id
].state
->obj
;
63 struct execlist_ring_context
*shadow_ring_context
;
66 unsigned long context_gpa
, context_page_num
;
69 gvt_dbg_sched("ring id %d workload lrca %x", ring_id
,
70 workload
->ctx_desc
.lrca
);
72 context_page_num
= intel_lr_context_size(
73 gvt
->dev_priv
->engine
[ring_id
]);
75 context_page_num
= context_page_num
>> PAGE_SHIFT
;
77 if (IS_BROADWELL(gvt
->dev_priv
) && ring_id
== RCS
)
78 context_page_num
= 19;
82 while (i
< context_page_num
) {
83 context_gpa
= intel_vgpu_gma_to_gpa(vgpu
->gtt
.ggtt_mm
,
84 (u32
)((workload
->ctx_desc
.lrca
+ i
) <<
86 if (context_gpa
== INTEL_GVT_INVALID_ADDR
) {
87 gvt_err("Invalid guest context descriptor\n");
91 page
= i915_gem_object_get_page(ctx_obj
, LRC_PPHWSP_PN
+ i
);
93 intel_gvt_hypervisor_read_gpa(vgpu
, context_gpa
, dst
,
99 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
100 shadow_ring_context
= kmap(page
);
102 #define COPY_REG(name) \
103 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
104 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
107 COPY_REG(ctx_timestamp
);
109 if (ring_id
== RCS
) {
110 COPY_REG(bb_per_ctx_ptr
);
111 COPY_REG(rcs_indirect_ctx
);
112 COPY_REG(rcs_indirect_ctx_offset
);
116 set_context_pdp_root_pointer(shadow_ring_context
,
117 workload
->shadow_mm
->shadow_page_table
);
119 intel_gvt_hypervisor_read_gpa(vgpu
,
120 workload
->ring_context_gpa
+
121 sizeof(*shadow_ring_context
),
122 (void *)shadow_ring_context
+
123 sizeof(*shadow_ring_context
),
124 GTT_PAGE_SIZE
- sizeof(*shadow_ring_context
));
130 static int shadow_context_status_change(struct notifier_block
*nb
,
131 unsigned long action
, void *data
)
133 struct intel_vgpu
*vgpu
= container_of(nb
,
134 struct intel_vgpu
, shadow_ctx_notifier_block
);
135 struct drm_i915_gem_request
*req
=
136 (struct drm_i915_gem_request
*)data
;
137 struct intel_gvt_workload_scheduler
*scheduler
=
138 &vgpu
->gvt
->scheduler
;
139 struct intel_vgpu_workload
*workload
=
140 scheduler
->current_workload
[req
->engine
->id
];
142 if (unlikely(!workload
))
146 case INTEL_CONTEXT_SCHEDULE_IN
:
147 intel_gvt_load_render_mmio(workload
->vgpu
,
149 atomic_set(&workload
->shadow_ctx_active
, 1);
151 case INTEL_CONTEXT_SCHEDULE_OUT
:
152 intel_gvt_restore_render_mmio(workload
->vgpu
,
154 /* If the status is -EINPROGRESS means this workload
155 * doesn't meet any issue during dispatching so when
156 * get the SCHEDULE_OUT set the status to be zero for
157 * good. If the status is NOT -EINPROGRESS means there
158 * is something wrong happened during dispatching and
159 * the status should not be set to zero
161 if (workload
->status
== -EINPROGRESS
)
162 workload
->status
= 0;
163 atomic_set(&workload
->shadow_ctx_active
, 0);
169 wake_up(&workload
->shadow_ctx_status_wq
);
173 static int dispatch_workload(struct intel_vgpu_workload
*workload
)
175 int ring_id
= workload
->ring_id
;
176 struct i915_gem_context
*shadow_ctx
= workload
->vgpu
->shadow_ctx
;
177 struct drm_i915_private
*dev_priv
= workload
->vgpu
->gvt
->dev_priv
;
178 struct drm_i915_gem_request
*rq
;
181 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
184 shadow_ctx
->desc_template
&= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT
);
185 shadow_ctx
->desc_template
|= workload
->ctx_desc
.addressing_mode
<<
186 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
188 mutex_lock(&dev_priv
->drm
.struct_mutex
);
190 rq
= i915_gem_request_alloc(dev_priv
->engine
[ring_id
], shadow_ctx
);
192 gvt_err("fail to allocate gem request\n");
197 gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id
, rq
);
199 workload
->req
= i915_gem_request_get(rq
);
201 ret
= intel_gvt_scan_and_shadow_workload(workload
);
205 ret
= intel_gvt_scan_and_shadow_wa_ctx(&workload
->wa_ctx
);
209 ret
= populate_shadow_context(workload
);
213 if (workload
->prepare
) {
214 ret
= workload
->prepare(workload
);
219 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
220 ring_id
, workload
->req
);
223 workload
->dispatched
= true;
226 workload
->status
= ret
;
228 if (!IS_ERR_OR_NULL(rq
))
229 i915_add_request_no_flush(rq
);
230 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
234 static struct intel_vgpu_workload
*pick_next_workload(
235 struct intel_gvt
*gvt
, int ring_id
)
237 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
238 struct intel_vgpu_workload
*workload
= NULL
;
240 mutex_lock(&gvt
->lock
);
243 * no current vgpu / will be scheduled out / no workload
246 if (!scheduler
->current_vgpu
) {
247 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id
);
251 if (scheduler
->need_reschedule
) {
252 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id
);
256 if (list_empty(workload_q_head(scheduler
->current_vgpu
, ring_id
))) {
257 gvt_dbg_sched("ring id %d stop - no available workload\n",
263 * still have current workload, maybe the workload disptacher
264 * fail to submit it for some reason, resubmit it.
266 if (scheduler
->current_workload
[ring_id
]) {
267 workload
= scheduler
->current_workload
[ring_id
];
268 gvt_dbg_sched("ring id %d still have current workload %p\n",
274 * pick a workload as current workload
275 * once current workload is set, schedule policy routines
276 * will wait the current workload is finished when trying to
277 * schedule out a vgpu.
279 scheduler
->current_workload
[ring_id
] = container_of(
280 workload_q_head(scheduler
->current_vgpu
, ring_id
)->next
,
281 struct intel_vgpu_workload
, list
);
283 workload
= scheduler
->current_workload
[ring_id
];
285 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id
, workload
);
287 atomic_inc(&workload
->vgpu
->running_workload_num
);
289 mutex_unlock(&gvt
->lock
);
293 static void update_guest_context(struct intel_vgpu_workload
*workload
)
295 struct intel_vgpu
*vgpu
= workload
->vgpu
;
296 struct intel_gvt
*gvt
= vgpu
->gvt
;
297 int ring_id
= workload
->ring_id
;
298 struct i915_gem_context
*shadow_ctx
= workload
->vgpu
->shadow_ctx
;
299 struct drm_i915_gem_object
*ctx_obj
=
300 shadow_ctx
->engine
[ring_id
].state
->obj
;
301 struct execlist_ring_context
*shadow_ring_context
;
304 unsigned long context_gpa
, context_page_num
;
307 gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id
,
308 workload
->ctx_desc
.lrca
);
310 context_page_num
= intel_lr_context_size(
311 gvt
->dev_priv
->engine
[ring_id
]);
313 context_page_num
= context_page_num
>> PAGE_SHIFT
;
315 if (IS_BROADWELL(gvt
->dev_priv
) && ring_id
== RCS
)
316 context_page_num
= 19;
320 while (i
< context_page_num
) {
321 context_gpa
= intel_vgpu_gma_to_gpa(vgpu
->gtt
.ggtt_mm
,
322 (u32
)((workload
->ctx_desc
.lrca
+ i
) <<
324 if (context_gpa
== INTEL_GVT_INVALID_ADDR
) {
325 gvt_err("invalid guest context descriptor\n");
329 page
= i915_gem_object_get_page(ctx_obj
, LRC_PPHWSP_PN
+ i
);
331 intel_gvt_hypervisor_write_gpa(vgpu
, context_gpa
, src
,
337 intel_gvt_hypervisor_write_gpa(vgpu
, workload
->ring_context_gpa
+
338 RING_CTX_OFF(ring_header
.val
), &workload
->rb_tail
, 4);
340 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
341 shadow_ring_context
= kmap(page
);
343 #define COPY_REG(name) \
344 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
345 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
348 COPY_REG(ctx_timestamp
);
352 intel_gvt_hypervisor_write_gpa(vgpu
,
353 workload
->ring_context_gpa
+
354 sizeof(*shadow_ring_context
),
355 (void *)shadow_ring_context
+
356 sizeof(*shadow_ring_context
),
357 GTT_PAGE_SIZE
- sizeof(*shadow_ring_context
));
362 static void complete_current_workload(struct intel_gvt
*gvt
, int ring_id
)
364 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
365 struct intel_vgpu_workload
*workload
;
366 struct intel_vgpu
*vgpu
;
369 mutex_lock(&gvt
->lock
);
371 workload
= scheduler
->current_workload
[ring_id
];
372 vgpu
= workload
->vgpu
;
374 /* For the workload w/ request, needs to wait for the context
375 * switch to make sure request is completed.
376 * For the workload w/o request, directly complete the workload.
379 wait_event(workload
->shadow_ctx_status_wq
,
380 !atomic_read(&workload
->shadow_ctx_active
));
382 i915_gem_request_put(fetch_and_zero(&workload
->req
));
384 if (!workload
->status
&& !vgpu
->resetting
) {
385 update_guest_context(workload
);
387 for_each_set_bit(event
, workload
->pending_events
,
389 intel_vgpu_trigger_virtual_event(vgpu
, event
);
393 gvt_dbg_sched("ring id %d complete workload %p status %d\n",
394 ring_id
, workload
, workload
->status
);
396 scheduler
->current_workload
[ring_id
] = NULL
;
398 list_del_init(&workload
->list
);
399 workload
->complete(workload
);
401 atomic_dec(&vgpu
->running_workload_num
);
402 wake_up(&scheduler
->workload_complete_wq
);
403 mutex_unlock(&gvt
->lock
);
406 struct workload_thread_param
{
407 struct intel_gvt
*gvt
;
411 static DEFINE_MUTEX(scheduler_mutex
);
413 static int workload_thread(void *priv
)
415 struct workload_thread_param
*p
= (struct workload_thread_param
*)priv
;
416 struct intel_gvt
*gvt
= p
->gvt
;
417 int ring_id
= p
->ring_id
;
418 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
419 struct intel_vgpu_workload
*workload
= NULL
;
421 bool need_force_wake
= IS_SKYLAKE(gvt
->dev_priv
);
422 DEFINE_WAIT_FUNC(wait
, woken_wake_function
);
426 gvt_dbg_core("workload thread for ring %d started\n", ring_id
);
428 while (!kthread_should_stop()) {
429 add_wait_queue(&scheduler
->waitq
[ring_id
], &wait
);
431 workload
= pick_next_workload(gvt
, ring_id
);
434 wait_woken(&wait
, TASK_INTERRUPTIBLE
,
435 MAX_SCHEDULE_TIMEOUT
);
436 } while (!kthread_should_stop());
437 remove_wait_queue(&scheduler
->waitq
[ring_id
], &wait
);
442 mutex_lock(&scheduler_mutex
);
444 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
445 workload
->ring_id
, workload
,
448 intel_runtime_pm_get(gvt
->dev_priv
);
450 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
451 workload
->ring_id
, workload
);
454 intel_uncore_forcewake_get(gvt
->dev_priv
,
457 mutex_lock(&gvt
->lock
);
458 ret
= dispatch_workload(workload
);
459 mutex_unlock(&gvt
->lock
);
462 gvt_err("fail to dispatch workload, skip\n");
466 gvt_dbg_sched("ring id %d wait workload %p\n",
467 workload
->ring_id
, workload
);
469 i915_wait_request(workload
->req
,
470 0, MAX_SCHEDULE_TIMEOUT
);
471 /* I915 has replay mechanism and a request will be replayed
472 * if there is i915 reset. So the seqno will be updated anyway.
473 * If the seqno is not updated yet after waiting, which means
474 * the replay may still be in progress and we can wait again.
476 if (!i915_gem_request_completed(workload
->req
)) {
477 gvt_dbg_sched("workload %p not completed, wait again\n",
483 gvt_dbg_sched("will complete workload %p, status: %d\n",
484 workload
, workload
->status
);
486 complete_current_workload(gvt
, ring_id
);
489 intel_uncore_forcewake_put(gvt
->dev_priv
,
492 intel_runtime_pm_put(gvt
->dev_priv
);
494 mutex_unlock(&scheduler_mutex
);
500 void intel_gvt_wait_vgpu_idle(struct intel_vgpu
*vgpu
)
502 struct intel_gvt
*gvt
= vgpu
->gvt
;
503 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
505 if (atomic_read(&vgpu
->running_workload_num
)) {
506 gvt_dbg_sched("wait vgpu idle\n");
508 wait_event(scheduler
->workload_complete_wq
,
509 !atomic_read(&vgpu
->running_workload_num
));
513 void intel_gvt_clean_workload_scheduler(struct intel_gvt
*gvt
)
515 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
518 gvt_dbg_core("clean workload scheduler\n");
520 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
521 if (scheduler
->thread
[i
]) {
522 kthread_stop(scheduler
->thread
[i
]);
523 scheduler
->thread
[i
] = NULL
;
528 int intel_gvt_init_workload_scheduler(struct intel_gvt
*gvt
)
530 struct intel_gvt_workload_scheduler
*scheduler
= &gvt
->scheduler
;
531 struct workload_thread_param
*param
= NULL
;
535 gvt_dbg_core("init workload scheduler\n");
537 init_waitqueue_head(&scheduler
->workload_complete_wq
);
539 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
540 /* check ring mask at init time */
541 if (!HAS_ENGINE(gvt
->dev_priv
, i
))
544 init_waitqueue_head(&scheduler
->waitq
[i
]);
546 param
= kzalloc(sizeof(*param
), GFP_KERNEL
);
555 scheduler
->thread
[i
] = kthread_run(workload_thread
, param
,
556 "gvt workload %d", i
);
557 if (IS_ERR(scheduler
->thread
[i
])) {
558 gvt_err("fail to create workload thread\n");
559 ret
= PTR_ERR(scheduler
->thread
[i
]);
565 intel_gvt_clean_workload_scheduler(gvt
);
571 void intel_vgpu_clean_gvt_context(struct intel_vgpu
*vgpu
)
573 atomic_notifier_chain_unregister(&vgpu
->shadow_ctx
->status_notifier
,
574 &vgpu
->shadow_ctx_notifier_block
);
576 i915_gem_context_put_unlocked(vgpu
->shadow_ctx
);
579 int intel_vgpu_init_gvt_context(struct intel_vgpu
*vgpu
)
581 atomic_set(&vgpu
->running_workload_num
, 0);
583 vgpu
->shadow_ctx
= i915_gem_context_create_gvt(
584 &vgpu
->gvt
->dev_priv
->drm
);
585 if (IS_ERR(vgpu
->shadow_ctx
))
586 return PTR_ERR(vgpu
->shadow_ctx
);
588 vgpu
->shadow_ctx
->engine
[RCS
].initialised
= true;
590 vgpu
->shadow_ctx_notifier_block
.notifier_call
=
591 shadow_context_status_change
;
593 atomic_notifier_chain_register(&vgpu
->shadow_ctx
->status_notifier
,
594 &vgpu
->shadow_ctx_notifier_block
);