]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/i915/i915_debugfs.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'drm-amdkfd-next-2017-10-18' of git://people.freedesktop.org/~gabbayo/linux...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/debugfs.h>
30 #include <linux/sort.h>
31 #include <linux/sched/mm.h>
32 #include "intel_drv.h"
33 #include "i915_guc_submission.h"
34
35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
36 {
37 return to_i915(node->minor->dev);
38 }
39
40 static __always_inline void seq_print_param(struct seq_file *m,
41 const char *name,
42 const char *type,
43 const void *x)
44 {
45 if (!__builtin_strcmp(type, "bool"))
46 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
47 else if (!__builtin_strcmp(type, "int"))
48 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
49 else if (!__builtin_strcmp(type, "unsigned int"))
50 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
51 else if (!__builtin_strcmp(type, "char *"))
52 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
53 else
54 BUILD_BUG();
55 }
56
57 static int i915_capabilities(struct seq_file *m, void *data)
58 {
59 struct drm_i915_private *dev_priv = node_to_i915(m->private);
60 const struct intel_device_info *info = INTEL_INFO(dev_priv);
61
62 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
63 seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
64 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
65
66 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
67 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
68 #undef PRINT_FLAG
69
70 kernel_param_lock(THIS_MODULE);
71 #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
72 I915_PARAMS_FOR_EACH(PRINT_PARAM);
73 #undef PRINT_PARAM
74 kernel_param_unlock(THIS_MODULE);
75
76 return 0;
77 }
78
79 static char get_active_flag(struct drm_i915_gem_object *obj)
80 {
81 return i915_gem_object_is_active(obj) ? '*' : ' ';
82 }
83
84 static char get_pin_flag(struct drm_i915_gem_object *obj)
85 {
86 return obj->pin_display ? 'p' : ' ';
87 }
88
89 static char get_tiling_flag(struct drm_i915_gem_object *obj)
90 {
91 switch (i915_gem_object_get_tiling(obj)) {
92 default:
93 case I915_TILING_NONE: return ' ';
94 case I915_TILING_X: return 'X';
95 case I915_TILING_Y: return 'Y';
96 }
97 }
98
99 static char get_global_flag(struct drm_i915_gem_object *obj)
100 {
101 return obj->userfault_count ? 'g' : ' ';
102 }
103
104 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
105 {
106 return obj->mm.mapping ? 'M' : ' ';
107 }
108
109 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
110 {
111 u64 size = 0;
112 struct i915_vma *vma;
113
114 list_for_each_entry(vma, &obj->vma_list, obj_link) {
115 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
116 size += vma->node.size;
117 }
118
119 return size;
120 }
121
122 static const char *
123 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
124 {
125 size_t x = 0;
126
127 switch (page_sizes) {
128 case 0:
129 return "";
130 case I915_GTT_PAGE_SIZE_4K:
131 return "4K";
132 case I915_GTT_PAGE_SIZE_64K:
133 return "64K";
134 case I915_GTT_PAGE_SIZE_2M:
135 return "2M";
136 default:
137 if (!buf)
138 return "M";
139
140 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
141 x += snprintf(buf + x, len - x, "2M, ");
142 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
143 x += snprintf(buf + x, len - x, "64K, ");
144 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
145 x += snprintf(buf + x, len - x, "4K, ");
146 buf[x-2] = '\0';
147
148 return buf;
149 }
150 }
151
152 static void
153 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
154 {
155 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
156 struct intel_engine_cs *engine;
157 struct i915_vma *vma;
158 unsigned int frontbuffer_bits;
159 int pin_count = 0;
160
161 lockdep_assert_held(&obj->base.dev->struct_mutex);
162
163 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
164 &obj->base,
165 get_active_flag(obj),
166 get_pin_flag(obj),
167 get_tiling_flag(obj),
168 get_global_flag(obj),
169 get_pin_mapped_flag(obj),
170 obj->base.size / 1024,
171 obj->base.read_domains,
172 obj->base.write_domain,
173 i915_cache_level_str(dev_priv, obj->cache_level),
174 obj->mm.dirty ? " dirty" : "",
175 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
176 if (obj->base.name)
177 seq_printf(m, " (name: %d)", obj->base.name);
178 list_for_each_entry(vma, &obj->vma_list, obj_link) {
179 if (i915_vma_is_pinned(vma))
180 pin_count++;
181 }
182 seq_printf(m, " (pinned x %d)", pin_count);
183 if (obj->pin_display)
184 seq_printf(m, " (display)");
185 list_for_each_entry(vma, &obj->vma_list, obj_link) {
186 if (!drm_mm_node_allocated(&vma->node))
187 continue;
188
189 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
190 i915_vma_is_ggtt(vma) ? "g" : "pp",
191 vma->node.start, vma->node.size,
192 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
193 if (i915_vma_is_ggtt(vma)) {
194 switch (vma->ggtt_view.type) {
195 case I915_GGTT_VIEW_NORMAL:
196 seq_puts(m, ", normal");
197 break;
198
199 case I915_GGTT_VIEW_PARTIAL:
200 seq_printf(m, ", partial [%08llx+%x]",
201 vma->ggtt_view.partial.offset << PAGE_SHIFT,
202 vma->ggtt_view.partial.size << PAGE_SHIFT);
203 break;
204
205 case I915_GGTT_VIEW_ROTATED:
206 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
207 vma->ggtt_view.rotated.plane[0].width,
208 vma->ggtt_view.rotated.plane[0].height,
209 vma->ggtt_view.rotated.plane[0].stride,
210 vma->ggtt_view.rotated.plane[0].offset,
211 vma->ggtt_view.rotated.plane[1].width,
212 vma->ggtt_view.rotated.plane[1].height,
213 vma->ggtt_view.rotated.plane[1].stride,
214 vma->ggtt_view.rotated.plane[1].offset);
215 break;
216
217 default:
218 MISSING_CASE(vma->ggtt_view.type);
219 break;
220 }
221 }
222 if (vma->fence)
223 seq_printf(m, " , fence: %d%s",
224 vma->fence->id,
225 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
226 seq_puts(m, ")");
227 }
228 if (obj->stolen)
229 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
230
231 engine = i915_gem_object_last_write_engine(obj);
232 if (engine)
233 seq_printf(m, " (%s)", engine->name);
234
235 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
236 if (frontbuffer_bits)
237 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
238 }
239
240 static int obj_rank_by_stolen(const void *A, const void *B)
241 {
242 const struct drm_i915_gem_object *a =
243 *(const struct drm_i915_gem_object **)A;
244 const struct drm_i915_gem_object *b =
245 *(const struct drm_i915_gem_object **)B;
246
247 if (a->stolen->start < b->stolen->start)
248 return -1;
249 if (a->stolen->start > b->stolen->start)
250 return 1;
251 return 0;
252 }
253
254 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
255 {
256 struct drm_i915_private *dev_priv = node_to_i915(m->private);
257 struct drm_device *dev = &dev_priv->drm;
258 struct drm_i915_gem_object **objects;
259 struct drm_i915_gem_object *obj;
260 u64 total_obj_size, total_gtt_size;
261 unsigned long total, count, n;
262 int ret;
263
264 total = READ_ONCE(dev_priv->mm.object_count);
265 objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
266 if (!objects)
267 return -ENOMEM;
268
269 ret = mutex_lock_interruptible(&dev->struct_mutex);
270 if (ret)
271 goto out;
272
273 total_obj_size = total_gtt_size = count = 0;
274 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
275 if (count == total)
276 break;
277
278 if (obj->stolen == NULL)
279 continue;
280
281 objects[count++] = obj;
282 total_obj_size += obj->base.size;
283 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
284
285 }
286 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
287 if (count == total)
288 break;
289
290 if (obj->stolen == NULL)
291 continue;
292
293 objects[count++] = obj;
294 total_obj_size += obj->base.size;
295 }
296
297 sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
298
299 seq_puts(m, "Stolen:\n");
300 for (n = 0; n < count; n++) {
301 seq_puts(m, " ");
302 describe_obj(m, objects[n]);
303 seq_putc(m, '\n');
304 }
305 seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
306 count, total_obj_size, total_gtt_size);
307
308 mutex_unlock(&dev->struct_mutex);
309 out:
310 kvfree(objects);
311 return ret;
312 }
313
314 struct file_stats {
315 struct drm_i915_file_private *file_priv;
316 unsigned long count;
317 u64 total, unbound;
318 u64 global, shared;
319 u64 active, inactive;
320 };
321
322 static int per_file_stats(int id, void *ptr, void *data)
323 {
324 struct drm_i915_gem_object *obj = ptr;
325 struct file_stats *stats = data;
326 struct i915_vma *vma;
327
328 lockdep_assert_held(&obj->base.dev->struct_mutex);
329
330 stats->count++;
331 stats->total += obj->base.size;
332 if (!obj->bind_count)
333 stats->unbound += obj->base.size;
334 if (obj->base.name || obj->base.dma_buf)
335 stats->shared += obj->base.size;
336
337 list_for_each_entry(vma, &obj->vma_list, obj_link) {
338 if (!drm_mm_node_allocated(&vma->node))
339 continue;
340
341 if (i915_vma_is_ggtt(vma)) {
342 stats->global += vma->node.size;
343 } else {
344 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
345
346 if (ppgtt->base.file != stats->file_priv)
347 continue;
348 }
349
350 if (i915_vma_is_active(vma))
351 stats->active += vma->node.size;
352 else
353 stats->inactive += vma->node.size;
354 }
355
356 return 0;
357 }
358
359 #define print_file_stats(m, name, stats) do { \
360 if (stats.count) \
361 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
362 name, \
363 stats.count, \
364 stats.total, \
365 stats.active, \
366 stats.inactive, \
367 stats.global, \
368 stats.shared, \
369 stats.unbound); \
370 } while (0)
371
372 static void print_batch_pool_stats(struct seq_file *m,
373 struct drm_i915_private *dev_priv)
374 {
375 struct drm_i915_gem_object *obj;
376 struct file_stats stats;
377 struct intel_engine_cs *engine;
378 enum intel_engine_id id;
379 int j;
380
381 memset(&stats, 0, sizeof(stats));
382
383 for_each_engine(engine, dev_priv, id) {
384 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
385 list_for_each_entry(obj,
386 &engine->batch_pool.cache_list[j],
387 batch_pool_link)
388 per_file_stats(0, obj, &stats);
389 }
390 }
391
392 print_file_stats(m, "[k]batch pool", stats);
393 }
394
395 static int per_file_ctx_stats(int id, void *ptr, void *data)
396 {
397 struct i915_gem_context *ctx = ptr;
398 int n;
399
400 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
401 if (ctx->engine[n].state)
402 per_file_stats(0, ctx->engine[n].state->obj, data);
403 if (ctx->engine[n].ring)
404 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
405 }
406
407 return 0;
408 }
409
410 static void print_context_stats(struct seq_file *m,
411 struct drm_i915_private *dev_priv)
412 {
413 struct drm_device *dev = &dev_priv->drm;
414 struct file_stats stats;
415 struct drm_file *file;
416
417 memset(&stats, 0, sizeof(stats));
418
419 mutex_lock(&dev->struct_mutex);
420 if (dev_priv->kernel_context)
421 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
422
423 list_for_each_entry(file, &dev->filelist, lhead) {
424 struct drm_i915_file_private *fpriv = file->driver_priv;
425 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
426 }
427 mutex_unlock(&dev->struct_mutex);
428
429 print_file_stats(m, "[k]contexts", stats);
430 }
431
432 static int i915_gem_object_info(struct seq_file *m, void *data)
433 {
434 struct drm_i915_private *dev_priv = node_to_i915(m->private);
435 struct drm_device *dev = &dev_priv->drm;
436 struct i915_ggtt *ggtt = &dev_priv->ggtt;
437 u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
438 u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
439 struct drm_i915_gem_object *obj;
440 unsigned int page_sizes = 0;
441 struct drm_file *file;
442 char buf[80];
443 int ret;
444
445 ret = mutex_lock_interruptible(&dev->struct_mutex);
446 if (ret)
447 return ret;
448
449 seq_printf(m, "%u objects, %llu bytes\n",
450 dev_priv->mm.object_count,
451 dev_priv->mm.object_memory);
452
453 size = count = 0;
454 mapped_size = mapped_count = 0;
455 purgeable_size = purgeable_count = 0;
456 huge_size = huge_count = 0;
457 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
458 size += obj->base.size;
459 ++count;
460
461 if (obj->mm.madv == I915_MADV_DONTNEED) {
462 purgeable_size += obj->base.size;
463 ++purgeable_count;
464 }
465
466 if (obj->mm.mapping) {
467 mapped_count++;
468 mapped_size += obj->base.size;
469 }
470
471 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
472 huge_count++;
473 huge_size += obj->base.size;
474 page_sizes |= obj->mm.page_sizes.sg;
475 }
476 }
477 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
478
479 size = count = dpy_size = dpy_count = 0;
480 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
481 size += obj->base.size;
482 ++count;
483
484 if (obj->pin_display) {
485 dpy_size += obj->base.size;
486 ++dpy_count;
487 }
488
489 if (obj->mm.madv == I915_MADV_DONTNEED) {
490 purgeable_size += obj->base.size;
491 ++purgeable_count;
492 }
493
494 if (obj->mm.mapping) {
495 mapped_count++;
496 mapped_size += obj->base.size;
497 }
498
499 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
500 huge_count++;
501 huge_size += obj->base.size;
502 page_sizes |= obj->mm.page_sizes.sg;
503 }
504 }
505 seq_printf(m, "%u bound objects, %llu bytes\n",
506 count, size);
507 seq_printf(m, "%u purgeable objects, %llu bytes\n",
508 purgeable_count, purgeable_size);
509 seq_printf(m, "%u mapped objects, %llu bytes\n",
510 mapped_count, mapped_size);
511 seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
512 huge_count,
513 stringify_page_sizes(page_sizes, buf, sizeof(buf)),
514 huge_size);
515 seq_printf(m, "%u display objects (pinned), %llu bytes\n",
516 dpy_count, dpy_size);
517
518 seq_printf(m, "%llu [%llu] gtt total\n",
519 ggtt->base.total, ggtt->mappable_end);
520 seq_printf(m, "Supported page sizes: %s\n",
521 stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
522 buf, sizeof(buf)));
523
524 seq_putc(m, '\n');
525 print_batch_pool_stats(m, dev_priv);
526 mutex_unlock(&dev->struct_mutex);
527
528 mutex_lock(&dev->filelist_mutex);
529 print_context_stats(m, dev_priv);
530 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
531 struct file_stats stats;
532 struct drm_i915_file_private *file_priv = file->driver_priv;
533 struct drm_i915_gem_request *request;
534 struct task_struct *task;
535
536 mutex_lock(&dev->struct_mutex);
537
538 memset(&stats, 0, sizeof(stats));
539 stats.file_priv = file->driver_priv;
540 spin_lock(&file->table_lock);
541 idr_for_each(&file->object_idr, per_file_stats, &stats);
542 spin_unlock(&file->table_lock);
543 /*
544 * Although we have a valid reference on file->pid, that does
545 * not guarantee that the task_struct who called get_pid() is
546 * still alive (e.g. get_pid(current) => fork() => exit()).
547 * Therefore, we need to protect this ->comm access using RCU.
548 */
549 request = list_first_entry_or_null(&file_priv->mm.request_list,
550 struct drm_i915_gem_request,
551 client_link);
552 rcu_read_lock();
553 task = pid_task(request && request->ctx->pid ?
554 request->ctx->pid : file->pid,
555 PIDTYPE_PID);
556 print_file_stats(m, task ? task->comm : "<unknown>", stats);
557 rcu_read_unlock();
558
559 mutex_unlock(&dev->struct_mutex);
560 }
561 mutex_unlock(&dev->filelist_mutex);
562
563 return 0;
564 }
565
566 static int i915_gem_gtt_info(struct seq_file *m, void *data)
567 {
568 struct drm_info_node *node = m->private;
569 struct drm_i915_private *dev_priv = node_to_i915(node);
570 struct drm_device *dev = &dev_priv->drm;
571 bool show_pin_display_only = !!node->info_ent->data;
572 struct drm_i915_gem_object *obj;
573 u64 total_obj_size, total_gtt_size;
574 int count, ret;
575
576 ret = mutex_lock_interruptible(&dev->struct_mutex);
577 if (ret)
578 return ret;
579
580 total_obj_size = total_gtt_size = count = 0;
581 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
582 if (show_pin_display_only && !obj->pin_display)
583 continue;
584
585 seq_puts(m, " ");
586 describe_obj(m, obj);
587 seq_putc(m, '\n');
588 total_obj_size += obj->base.size;
589 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
590 count++;
591 }
592
593 mutex_unlock(&dev->struct_mutex);
594
595 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
596 count, total_obj_size, total_gtt_size);
597
598 return 0;
599 }
600
601 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
602 {
603 struct drm_i915_private *dev_priv = node_to_i915(m->private);
604 struct drm_device *dev = &dev_priv->drm;
605 struct drm_i915_gem_object *obj;
606 struct intel_engine_cs *engine;
607 enum intel_engine_id id;
608 int total = 0;
609 int ret, j;
610
611 ret = mutex_lock_interruptible(&dev->struct_mutex);
612 if (ret)
613 return ret;
614
615 for_each_engine(engine, dev_priv, id) {
616 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
617 int count;
618
619 count = 0;
620 list_for_each_entry(obj,
621 &engine->batch_pool.cache_list[j],
622 batch_pool_link)
623 count++;
624 seq_printf(m, "%s cache[%d]: %d objects\n",
625 engine->name, j, count);
626
627 list_for_each_entry(obj,
628 &engine->batch_pool.cache_list[j],
629 batch_pool_link) {
630 seq_puts(m, " ");
631 describe_obj(m, obj);
632 seq_putc(m, '\n');
633 }
634
635 total += count;
636 }
637 }
638
639 seq_printf(m, "total: %d\n", total);
640
641 mutex_unlock(&dev->struct_mutex);
642
643 return 0;
644 }
645
646 static void print_request(struct seq_file *m,
647 struct drm_i915_gem_request *rq,
648 const char *prefix)
649 {
650 seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
651 rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
652 rq->priotree.priority,
653 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
654 rq->timeline->common->name);
655 }
656
657 static int i915_gem_request_info(struct seq_file *m, void *data)
658 {
659 struct drm_i915_private *dev_priv = node_to_i915(m->private);
660 struct drm_device *dev = &dev_priv->drm;
661 struct drm_i915_gem_request *req;
662 struct intel_engine_cs *engine;
663 enum intel_engine_id id;
664 int ret, any;
665
666 ret = mutex_lock_interruptible(&dev->struct_mutex);
667 if (ret)
668 return ret;
669
670 any = 0;
671 for_each_engine(engine, dev_priv, id) {
672 int count;
673
674 count = 0;
675 list_for_each_entry(req, &engine->timeline->requests, link)
676 count++;
677 if (count == 0)
678 continue;
679
680 seq_printf(m, "%s requests: %d\n", engine->name, count);
681 list_for_each_entry(req, &engine->timeline->requests, link)
682 print_request(m, req, " ");
683
684 any++;
685 }
686 mutex_unlock(&dev->struct_mutex);
687
688 if (any == 0)
689 seq_puts(m, "No requests\n");
690
691 return 0;
692 }
693
694 static void i915_ring_seqno_info(struct seq_file *m,
695 struct intel_engine_cs *engine)
696 {
697 struct intel_breadcrumbs *b = &engine->breadcrumbs;
698 struct rb_node *rb;
699
700 seq_printf(m, "Current sequence (%s): %x\n",
701 engine->name, intel_engine_get_seqno(engine));
702
703 spin_lock_irq(&b->rb_lock);
704 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
705 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
706
707 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
708 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
709 }
710 spin_unlock_irq(&b->rb_lock);
711 }
712
713 static int i915_gem_seqno_info(struct seq_file *m, void *data)
714 {
715 struct drm_i915_private *dev_priv = node_to_i915(m->private);
716 struct intel_engine_cs *engine;
717 enum intel_engine_id id;
718
719 for_each_engine(engine, dev_priv, id)
720 i915_ring_seqno_info(m, engine);
721
722 return 0;
723 }
724
725
726 static int i915_interrupt_info(struct seq_file *m, void *data)
727 {
728 struct drm_i915_private *dev_priv = node_to_i915(m->private);
729 struct intel_engine_cs *engine;
730 enum intel_engine_id id;
731 int i, pipe;
732
733 intel_runtime_pm_get(dev_priv);
734
735 if (IS_CHERRYVIEW(dev_priv)) {
736 seq_printf(m, "Master Interrupt Control:\t%08x\n",
737 I915_READ(GEN8_MASTER_IRQ));
738
739 seq_printf(m, "Display IER:\t%08x\n",
740 I915_READ(VLV_IER));
741 seq_printf(m, "Display IIR:\t%08x\n",
742 I915_READ(VLV_IIR));
743 seq_printf(m, "Display IIR_RW:\t%08x\n",
744 I915_READ(VLV_IIR_RW));
745 seq_printf(m, "Display IMR:\t%08x\n",
746 I915_READ(VLV_IMR));
747 for_each_pipe(dev_priv, pipe) {
748 enum intel_display_power_domain power_domain;
749
750 power_domain = POWER_DOMAIN_PIPE(pipe);
751 if (!intel_display_power_get_if_enabled(dev_priv,
752 power_domain)) {
753 seq_printf(m, "Pipe %c power disabled\n",
754 pipe_name(pipe));
755 continue;
756 }
757
758 seq_printf(m, "Pipe %c stat:\t%08x\n",
759 pipe_name(pipe),
760 I915_READ(PIPESTAT(pipe)));
761
762 intel_display_power_put(dev_priv, power_domain);
763 }
764
765 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
766 seq_printf(m, "Port hotplug:\t%08x\n",
767 I915_READ(PORT_HOTPLUG_EN));
768 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
769 I915_READ(VLV_DPFLIPSTAT));
770 seq_printf(m, "DPINVGTT:\t%08x\n",
771 I915_READ(DPINVGTT));
772 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
773
774 for (i = 0; i < 4; i++) {
775 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
776 i, I915_READ(GEN8_GT_IMR(i)));
777 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
778 i, I915_READ(GEN8_GT_IIR(i)));
779 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
780 i, I915_READ(GEN8_GT_IER(i)));
781 }
782
783 seq_printf(m, "PCU interrupt mask:\t%08x\n",
784 I915_READ(GEN8_PCU_IMR));
785 seq_printf(m, "PCU interrupt identity:\t%08x\n",
786 I915_READ(GEN8_PCU_IIR));
787 seq_printf(m, "PCU interrupt enable:\t%08x\n",
788 I915_READ(GEN8_PCU_IER));
789 } else if (INTEL_GEN(dev_priv) >= 8) {
790 seq_printf(m, "Master Interrupt Control:\t%08x\n",
791 I915_READ(GEN8_MASTER_IRQ));
792
793 for (i = 0; i < 4; i++) {
794 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
795 i, I915_READ(GEN8_GT_IMR(i)));
796 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
797 i, I915_READ(GEN8_GT_IIR(i)));
798 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IER(i)));
800 }
801
802 for_each_pipe(dev_priv, pipe) {
803 enum intel_display_power_domain power_domain;
804
805 power_domain = POWER_DOMAIN_PIPE(pipe);
806 if (!intel_display_power_get_if_enabled(dev_priv,
807 power_domain)) {
808 seq_printf(m, "Pipe %c power disabled\n",
809 pipe_name(pipe));
810 continue;
811 }
812 seq_printf(m, "Pipe %c IMR:\t%08x\n",
813 pipe_name(pipe),
814 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
815 seq_printf(m, "Pipe %c IIR:\t%08x\n",
816 pipe_name(pipe),
817 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
818 seq_printf(m, "Pipe %c IER:\t%08x\n",
819 pipe_name(pipe),
820 I915_READ(GEN8_DE_PIPE_IER(pipe)));
821
822 intel_display_power_put(dev_priv, power_domain);
823 }
824
825 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
826 I915_READ(GEN8_DE_PORT_IMR));
827 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
828 I915_READ(GEN8_DE_PORT_IIR));
829 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
830 I915_READ(GEN8_DE_PORT_IER));
831
832 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
833 I915_READ(GEN8_DE_MISC_IMR));
834 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
835 I915_READ(GEN8_DE_MISC_IIR));
836 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
837 I915_READ(GEN8_DE_MISC_IER));
838
839 seq_printf(m, "PCU interrupt mask:\t%08x\n",
840 I915_READ(GEN8_PCU_IMR));
841 seq_printf(m, "PCU interrupt identity:\t%08x\n",
842 I915_READ(GEN8_PCU_IIR));
843 seq_printf(m, "PCU interrupt enable:\t%08x\n",
844 I915_READ(GEN8_PCU_IER));
845 } else if (IS_VALLEYVIEW(dev_priv)) {
846 seq_printf(m, "Display IER:\t%08x\n",
847 I915_READ(VLV_IER));
848 seq_printf(m, "Display IIR:\t%08x\n",
849 I915_READ(VLV_IIR));
850 seq_printf(m, "Display IIR_RW:\t%08x\n",
851 I915_READ(VLV_IIR_RW));
852 seq_printf(m, "Display IMR:\t%08x\n",
853 I915_READ(VLV_IMR));
854 for_each_pipe(dev_priv, pipe) {
855 enum intel_display_power_domain power_domain;
856
857 power_domain = POWER_DOMAIN_PIPE(pipe);
858 if (!intel_display_power_get_if_enabled(dev_priv,
859 power_domain)) {
860 seq_printf(m, "Pipe %c power disabled\n",
861 pipe_name(pipe));
862 continue;
863 }
864
865 seq_printf(m, "Pipe %c stat:\t%08x\n",
866 pipe_name(pipe),
867 I915_READ(PIPESTAT(pipe)));
868 intel_display_power_put(dev_priv, power_domain);
869 }
870
871 seq_printf(m, "Master IER:\t%08x\n",
872 I915_READ(VLV_MASTER_IER));
873
874 seq_printf(m, "Render IER:\t%08x\n",
875 I915_READ(GTIER));
876 seq_printf(m, "Render IIR:\t%08x\n",
877 I915_READ(GTIIR));
878 seq_printf(m, "Render IMR:\t%08x\n",
879 I915_READ(GTIMR));
880
881 seq_printf(m, "PM IER:\t\t%08x\n",
882 I915_READ(GEN6_PMIER));
883 seq_printf(m, "PM IIR:\t\t%08x\n",
884 I915_READ(GEN6_PMIIR));
885 seq_printf(m, "PM IMR:\t\t%08x\n",
886 I915_READ(GEN6_PMIMR));
887
888 seq_printf(m, "Port hotplug:\t%08x\n",
889 I915_READ(PORT_HOTPLUG_EN));
890 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
891 I915_READ(VLV_DPFLIPSTAT));
892 seq_printf(m, "DPINVGTT:\t%08x\n",
893 I915_READ(DPINVGTT));
894
895 } else if (!HAS_PCH_SPLIT(dev_priv)) {
896 seq_printf(m, "Interrupt enable: %08x\n",
897 I915_READ(IER));
898 seq_printf(m, "Interrupt identity: %08x\n",
899 I915_READ(IIR));
900 seq_printf(m, "Interrupt mask: %08x\n",
901 I915_READ(IMR));
902 for_each_pipe(dev_priv, pipe)
903 seq_printf(m, "Pipe %c stat: %08x\n",
904 pipe_name(pipe),
905 I915_READ(PIPESTAT(pipe)));
906 } else {
907 seq_printf(m, "North Display Interrupt enable: %08x\n",
908 I915_READ(DEIER));
909 seq_printf(m, "North Display Interrupt identity: %08x\n",
910 I915_READ(DEIIR));
911 seq_printf(m, "North Display Interrupt mask: %08x\n",
912 I915_READ(DEIMR));
913 seq_printf(m, "South Display Interrupt enable: %08x\n",
914 I915_READ(SDEIER));
915 seq_printf(m, "South Display Interrupt identity: %08x\n",
916 I915_READ(SDEIIR));
917 seq_printf(m, "South Display Interrupt mask: %08x\n",
918 I915_READ(SDEIMR));
919 seq_printf(m, "Graphics Interrupt enable: %08x\n",
920 I915_READ(GTIER));
921 seq_printf(m, "Graphics Interrupt identity: %08x\n",
922 I915_READ(GTIIR));
923 seq_printf(m, "Graphics Interrupt mask: %08x\n",
924 I915_READ(GTIMR));
925 }
926 for_each_engine(engine, dev_priv, id) {
927 if (INTEL_GEN(dev_priv) >= 6) {
928 seq_printf(m,
929 "Graphics Interrupt mask (%s): %08x\n",
930 engine->name, I915_READ_IMR(engine));
931 }
932 i915_ring_seqno_info(m, engine);
933 }
934 intel_runtime_pm_put(dev_priv);
935
936 return 0;
937 }
938
939 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
940 {
941 struct drm_i915_private *dev_priv = node_to_i915(m->private);
942 struct drm_device *dev = &dev_priv->drm;
943 int i, ret;
944
945 ret = mutex_lock_interruptible(&dev->struct_mutex);
946 if (ret)
947 return ret;
948
949 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
950 for (i = 0; i < dev_priv->num_fence_regs; i++) {
951 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
952
953 seq_printf(m, "Fence %d, pin count = %d, object = ",
954 i, dev_priv->fence_regs[i].pin_count);
955 if (!vma)
956 seq_puts(m, "unused");
957 else
958 describe_obj(m, vma->obj);
959 seq_putc(m, '\n');
960 }
961
962 mutex_unlock(&dev->struct_mutex);
963 return 0;
964 }
965
966 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
967 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
968 size_t count, loff_t *pos)
969 {
970 struct i915_gpu_state *error = file->private_data;
971 struct drm_i915_error_state_buf str;
972 ssize_t ret;
973 loff_t tmp;
974
975 if (!error)
976 return 0;
977
978 ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
979 if (ret)
980 return ret;
981
982 ret = i915_error_state_to_str(&str, error);
983 if (ret)
984 goto out;
985
986 tmp = 0;
987 ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
988 if (ret < 0)
989 goto out;
990
991 *pos = str.start + ret;
992 out:
993 i915_error_state_buf_release(&str);
994 return ret;
995 }
996
997 static int gpu_state_release(struct inode *inode, struct file *file)
998 {
999 i915_gpu_state_put(file->private_data);
1000 return 0;
1001 }
1002
1003 static int i915_gpu_info_open(struct inode *inode, struct file *file)
1004 {
1005 struct drm_i915_private *i915 = inode->i_private;
1006 struct i915_gpu_state *gpu;
1007
1008 intel_runtime_pm_get(i915);
1009 gpu = i915_capture_gpu_state(i915);
1010 intel_runtime_pm_put(i915);
1011 if (!gpu)
1012 return -ENOMEM;
1013
1014 file->private_data = gpu;
1015 return 0;
1016 }
1017
1018 static const struct file_operations i915_gpu_info_fops = {
1019 .owner = THIS_MODULE,
1020 .open = i915_gpu_info_open,
1021 .read = gpu_state_read,
1022 .llseek = default_llseek,
1023 .release = gpu_state_release,
1024 };
1025
1026 static ssize_t
1027 i915_error_state_write(struct file *filp,
1028 const char __user *ubuf,
1029 size_t cnt,
1030 loff_t *ppos)
1031 {
1032 struct i915_gpu_state *error = filp->private_data;
1033
1034 if (!error)
1035 return 0;
1036
1037 DRM_DEBUG_DRIVER("Resetting error state\n");
1038 i915_reset_error_state(error->i915);
1039
1040 return cnt;
1041 }
1042
1043 static int i915_error_state_open(struct inode *inode, struct file *file)
1044 {
1045 file->private_data = i915_first_error_state(inode->i_private);
1046 return 0;
1047 }
1048
1049 static const struct file_operations i915_error_state_fops = {
1050 .owner = THIS_MODULE,
1051 .open = i915_error_state_open,
1052 .read = gpu_state_read,
1053 .write = i915_error_state_write,
1054 .llseek = default_llseek,
1055 .release = gpu_state_release,
1056 };
1057 #endif
1058
1059 static int
1060 i915_next_seqno_set(void *data, u64 val)
1061 {
1062 struct drm_i915_private *dev_priv = data;
1063 struct drm_device *dev = &dev_priv->drm;
1064 int ret;
1065
1066 ret = mutex_lock_interruptible(&dev->struct_mutex);
1067 if (ret)
1068 return ret;
1069
1070 ret = i915_gem_set_global_seqno(dev, val);
1071 mutex_unlock(&dev->struct_mutex);
1072
1073 return ret;
1074 }
1075
1076 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1077 NULL, i915_next_seqno_set,
1078 "0x%llx\n");
1079
1080 static int i915_frequency_info(struct seq_file *m, void *unused)
1081 {
1082 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1083 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1084 int ret = 0;
1085
1086 intel_runtime_pm_get(dev_priv);
1087
1088 if (IS_GEN5(dev_priv)) {
1089 u16 rgvswctl = I915_READ16(MEMSWCTL);
1090 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1091
1092 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1093 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1094 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1095 MEMSTAT_VID_SHIFT);
1096 seq_printf(m, "Current P-state: %d\n",
1097 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1098 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1099 u32 rpmodectl, freq_sts;
1100
1101 mutex_lock(&dev_priv->pcu_lock);
1102
1103 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1104 seq_printf(m, "Video Turbo Mode: %s\n",
1105 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1106 seq_printf(m, "HW control enabled: %s\n",
1107 yesno(rpmodectl & GEN6_RP_ENABLE));
1108 seq_printf(m, "SW control enabled: %s\n",
1109 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1110 GEN6_RP_MEDIA_SW_MODE));
1111
1112 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1113 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1114 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1115
1116 seq_printf(m, "actual GPU freq: %d MHz\n",
1117 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1118
1119 seq_printf(m, "current GPU freq: %d MHz\n",
1120 intel_gpu_freq(dev_priv, rps->cur_freq));
1121
1122 seq_printf(m, "max GPU freq: %d MHz\n",
1123 intel_gpu_freq(dev_priv, rps->max_freq));
1124
1125 seq_printf(m, "min GPU freq: %d MHz\n",
1126 intel_gpu_freq(dev_priv, rps->min_freq));
1127
1128 seq_printf(m, "idle GPU freq: %d MHz\n",
1129 intel_gpu_freq(dev_priv, rps->idle_freq));
1130
1131 seq_printf(m,
1132 "efficient (RPe) frequency: %d MHz\n",
1133 intel_gpu_freq(dev_priv, rps->efficient_freq));
1134 mutex_unlock(&dev_priv->pcu_lock);
1135 } else if (INTEL_GEN(dev_priv) >= 6) {
1136 u32 rp_state_limits;
1137 u32 gt_perf_status;
1138 u32 rp_state_cap;
1139 u32 rpmodectl, rpinclimit, rpdeclimit;
1140 u32 rpstat, cagf, reqf;
1141 u32 rpupei, rpcurup, rpprevup;
1142 u32 rpdownei, rpcurdown, rpprevdown;
1143 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1144 int max_freq;
1145
1146 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1147 if (IS_GEN9_LP(dev_priv)) {
1148 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1149 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1150 } else {
1151 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1152 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1153 }
1154
1155 /* RPSTAT1 is in the GT power well */
1156 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1157
1158 reqf = I915_READ(GEN6_RPNSWREQ);
1159 if (INTEL_GEN(dev_priv) >= 9)
1160 reqf >>= 23;
1161 else {
1162 reqf &= ~GEN6_TURBO_DISABLE;
1163 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1164 reqf >>= 24;
1165 else
1166 reqf >>= 25;
1167 }
1168 reqf = intel_gpu_freq(dev_priv, reqf);
1169
1170 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1171 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1172 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1173
1174 rpstat = I915_READ(GEN6_RPSTAT1);
1175 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1176 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1177 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1178 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1179 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1180 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1181 if (INTEL_GEN(dev_priv) >= 9)
1182 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1183 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1184 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1185 else
1186 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1187 cagf = intel_gpu_freq(dev_priv, cagf);
1188
1189 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1190
1191 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1192 pm_ier = I915_READ(GEN6_PMIER);
1193 pm_imr = I915_READ(GEN6_PMIMR);
1194 pm_isr = I915_READ(GEN6_PMISR);
1195 pm_iir = I915_READ(GEN6_PMIIR);
1196 pm_mask = I915_READ(GEN6_PMINTRMSK);
1197 } else {
1198 pm_ier = I915_READ(GEN8_GT_IER(2));
1199 pm_imr = I915_READ(GEN8_GT_IMR(2));
1200 pm_isr = I915_READ(GEN8_GT_ISR(2));
1201 pm_iir = I915_READ(GEN8_GT_IIR(2));
1202 pm_mask = I915_READ(GEN6_PMINTRMSK);
1203 }
1204 seq_printf(m, "Video Turbo Mode: %s\n",
1205 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1206 seq_printf(m, "HW control enabled: %s\n",
1207 yesno(rpmodectl & GEN6_RP_ENABLE));
1208 seq_printf(m, "SW control enabled: %s\n",
1209 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1210 GEN6_RP_MEDIA_SW_MODE));
1211 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1212 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1213 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1214 rps->pm_intrmsk_mbz);
1215 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1216 seq_printf(m, "Render p-state ratio: %d\n",
1217 (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1218 seq_printf(m, "Render p-state VID: %d\n",
1219 gt_perf_status & 0xff);
1220 seq_printf(m, "Render p-state limit: %d\n",
1221 rp_state_limits & 0xff);
1222 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1223 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1224 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1225 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1226 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1227 seq_printf(m, "CAGF: %dMHz\n", cagf);
1228 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1229 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1230 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1231 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1232 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1233 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1234 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1235
1236 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1237 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1238 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1239 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1240 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1241 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1242 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1243
1244 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1245 rp_state_cap >> 16) & 0xff;
1246 max_freq *= (IS_GEN9_BC(dev_priv) ||
1247 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1248 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1249 intel_gpu_freq(dev_priv, max_freq));
1250
1251 max_freq = (rp_state_cap & 0xff00) >> 8;
1252 max_freq *= (IS_GEN9_BC(dev_priv) ||
1253 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1254 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1255 intel_gpu_freq(dev_priv, max_freq));
1256
1257 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1258 rp_state_cap >> 0) & 0xff;
1259 max_freq *= (IS_GEN9_BC(dev_priv) ||
1260 IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1261 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1262 intel_gpu_freq(dev_priv, max_freq));
1263 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1264 intel_gpu_freq(dev_priv, rps->max_freq));
1265
1266 seq_printf(m, "Current freq: %d MHz\n",
1267 intel_gpu_freq(dev_priv, rps->cur_freq));
1268 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1269 seq_printf(m, "Idle freq: %d MHz\n",
1270 intel_gpu_freq(dev_priv, rps->idle_freq));
1271 seq_printf(m, "Min freq: %d MHz\n",
1272 intel_gpu_freq(dev_priv, rps->min_freq));
1273 seq_printf(m, "Boost freq: %d MHz\n",
1274 intel_gpu_freq(dev_priv, rps->boost_freq));
1275 seq_printf(m, "Max freq: %d MHz\n",
1276 intel_gpu_freq(dev_priv, rps->max_freq));
1277 seq_printf(m,
1278 "efficient (RPe) frequency: %d MHz\n",
1279 intel_gpu_freq(dev_priv, rps->efficient_freq));
1280 } else {
1281 seq_puts(m, "no P-state info available\n");
1282 }
1283
1284 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1285 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1286 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1287
1288 intel_runtime_pm_put(dev_priv);
1289 return ret;
1290 }
1291
1292 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1293 struct seq_file *m,
1294 struct intel_instdone *instdone)
1295 {
1296 int slice;
1297 int subslice;
1298
1299 seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1300 instdone->instdone);
1301
1302 if (INTEL_GEN(dev_priv) <= 3)
1303 return;
1304
1305 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1306 instdone->slice_common);
1307
1308 if (INTEL_GEN(dev_priv) <= 6)
1309 return;
1310
1311 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1312 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1313 slice, subslice, instdone->sampler[slice][subslice]);
1314
1315 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1316 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1317 slice, subslice, instdone->row[slice][subslice]);
1318 }
1319
1320 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1321 {
1322 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1323 struct intel_engine_cs *engine;
1324 u64 acthd[I915_NUM_ENGINES];
1325 u32 seqno[I915_NUM_ENGINES];
1326 struct intel_instdone instdone;
1327 enum intel_engine_id id;
1328
1329 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1330 seq_puts(m, "Wedged\n");
1331 if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1332 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1333 if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1334 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1335 if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1336 seq_puts(m, "Waiter holding struct mutex\n");
1337 if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1338 seq_puts(m, "struct_mutex blocked for reset\n");
1339
1340 if (!i915_modparams.enable_hangcheck) {
1341 seq_puts(m, "Hangcheck disabled\n");
1342 return 0;
1343 }
1344
1345 intel_runtime_pm_get(dev_priv);
1346
1347 for_each_engine(engine, dev_priv, id) {
1348 acthd[id] = intel_engine_get_active_head(engine);
1349 seqno[id] = intel_engine_get_seqno(engine);
1350 }
1351
1352 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1353
1354 intel_runtime_pm_put(dev_priv);
1355
1356 if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1357 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1358 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1359 jiffies));
1360 else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1361 seq_puts(m, "Hangcheck active, work pending\n");
1362 else
1363 seq_puts(m, "Hangcheck inactive\n");
1364
1365 seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1366
1367 for_each_engine(engine, dev_priv, id) {
1368 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1369 struct rb_node *rb;
1370
1371 seq_printf(m, "%s:\n", engine->name);
1372 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1373 engine->hangcheck.seqno, seqno[id],
1374 intel_engine_last_submit(engine),
1375 engine->timeline->inflight_seqnos);
1376 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1377 yesno(intel_engine_has_waiter(engine)),
1378 yesno(test_bit(engine->id,
1379 &dev_priv->gpu_error.missed_irq_rings)),
1380 yesno(engine->hangcheck.stalled));
1381
1382 spin_lock_irq(&b->rb_lock);
1383 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1384 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1385
1386 seq_printf(m, "\t%s [%d] waiting for %x\n",
1387 w->tsk->comm, w->tsk->pid, w->seqno);
1388 }
1389 spin_unlock_irq(&b->rb_lock);
1390
1391 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1392 (long long)engine->hangcheck.acthd,
1393 (long long)acthd[id]);
1394 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1395 hangcheck_action_to_str(engine->hangcheck.action),
1396 engine->hangcheck.action,
1397 jiffies_to_msecs(jiffies -
1398 engine->hangcheck.action_timestamp));
1399
1400 if (engine->id == RCS) {
1401 seq_puts(m, "\tinstdone read =\n");
1402
1403 i915_instdone_info(dev_priv, m, &instdone);
1404
1405 seq_puts(m, "\tinstdone accu =\n");
1406
1407 i915_instdone_info(dev_priv, m,
1408 &engine->hangcheck.instdone);
1409 }
1410 }
1411
1412 return 0;
1413 }
1414
1415 static int i915_reset_info(struct seq_file *m, void *unused)
1416 {
1417 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1418 struct i915_gpu_error *error = &dev_priv->gpu_error;
1419 struct intel_engine_cs *engine;
1420 enum intel_engine_id id;
1421
1422 seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1423
1424 for_each_engine(engine, dev_priv, id) {
1425 seq_printf(m, "%s = %u\n", engine->name,
1426 i915_reset_engine_count(error, engine));
1427 }
1428
1429 return 0;
1430 }
1431
1432 static int ironlake_drpc_info(struct seq_file *m)
1433 {
1434 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1435 u32 rgvmodectl, rstdbyctl;
1436 u16 crstandvid;
1437
1438 rgvmodectl = I915_READ(MEMMODECTL);
1439 rstdbyctl = I915_READ(RSTDBYCTL);
1440 crstandvid = I915_READ16(CRSTANDVID);
1441
1442 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1443 seq_printf(m, "Boost freq: %d\n",
1444 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1445 MEMMODE_BOOST_FREQ_SHIFT);
1446 seq_printf(m, "HW control enabled: %s\n",
1447 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1448 seq_printf(m, "SW control enabled: %s\n",
1449 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1450 seq_printf(m, "Gated voltage change: %s\n",
1451 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1452 seq_printf(m, "Starting frequency: P%d\n",
1453 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1454 seq_printf(m, "Max P-state: P%d\n",
1455 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1456 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1457 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1458 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1459 seq_printf(m, "Render standby enabled: %s\n",
1460 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1461 seq_puts(m, "Current RS state: ");
1462 switch (rstdbyctl & RSX_STATUS_MASK) {
1463 case RSX_STATUS_ON:
1464 seq_puts(m, "on\n");
1465 break;
1466 case RSX_STATUS_RC1:
1467 seq_puts(m, "RC1\n");
1468 break;
1469 case RSX_STATUS_RC1E:
1470 seq_puts(m, "RC1E\n");
1471 break;
1472 case RSX_STATUS_RS1:
1473 seq_puts(m, "RS1\n");
1474 break;
1475 case RSX_STATUS_RS2:
1476 seq_puts(m, "RS2 (RC6)\n");
1477 break;
1478 case RSX_STATUS_RS3:
1479 seq_puts(m, "RC3 (RC6+)\n");
1480 break;
1481 default:
1482 seq_puts(m, "unknown\n");
1483 break;
1484 }
1485
1486 return 0;
1487 }
1488
1489 static int i915_forcewake_domains(struct seq_file *m, void *data)
1490 {
1491 struct drm_i915_private *i915 = node_to_i915(m->private);
1492 struct intel_uncore_forcewake_domain *fw_domain;
1493 unsigned int tmp;
1494
1495 seq_printf(m, "user.bypass_count = %u\n",
1496 i915->uncore.user_forcewake.count);
1497
1498 for_each_fw_domain(fw_domain, i915, tmp)
1499 seq_printf(m, "%s.wake_count = %u\n",
1500 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1501 READ_ONCE(fw_domain->wake_count));
1502
1503 return 0;
1504 }
1505
1506 static void print_rc6_res(struct seq_file *m,
1507 const char *title,
1508 const i915_reg_t reg)
1509 {
1510 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1511
1512 seq_printf(m, "%s %u (%llu us)\n",
1513 title, I915_READ(reg),
1514 intel_rc6_residency_us(dev_priv, reg));
1515 }
1516
1517 static int vlv_drpc_info(struct seq_file *m)
1518 {
1519 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1520 u32 rcctl1, pw_status;
1521
1522 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1523 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1524
1525 seq_printf(m, "RC6 Enabled: %s\n",
1526 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1527 GEN6_RC_CTL_EI_MODE(1))));
1528 seq_printf(m, "Render Power Well: %s\n",
1529 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1530 seq_printf(m, "Media Power Well: %s\n",
1531 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1532
1533 print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1534 print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1535
1536 return i915_forcewake_domains(m, NULL);
1537 }
1538
1539 static int gen6_drpc_info(struct seq_file *m)
1540 {
1541 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1542 u32 gt_core_status, rcctl1, rc6vids = 0;
1543 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1544 unsigned forcewake_count;
1545 int count = 0;
1546
1547 forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
1548 if (forcewake_count) {
1549 seq_puts(m, "RC information inaccurate because somebody "
1550 "holds a forcewake reference \n");
1551 } else {
1552 /* NB: we cannot use forcewake, else we read the wrong values */
1553 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1554 udelay(10);
1555 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1556 }
1557
1558 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1559 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1560
1561 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1562 if (INTEL_GEN(dev_priv) >= 9) {
1563 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1564 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1565 }
1566
1567 mutex_lock(&dev_priv->pcu_lock);
1568 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1569 mutex_unlock(&dev_priv->pcu_lock);
1570
1571 seq_printf(m, "RC1e Enabled: %s\n",
1572 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1573 seq_printf(m, "RC6 Enabled: %s\n",
1574 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1575 if (INTEL_GEN(dev_priv) >= 9) {
1576 seq_printf(m, "Render Well Gating Enabled: %s\n",
1577 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1578 seq_printf(m, "Media Well Gating Enabled: %s\n",
1579 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1580 }
1581 seq_printf(m, "Deep RC6 Enabled: %s\n",
1582 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1583 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1584 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1585 seq_puts(m, "Current RC state: ");
1586 switch (gt_core_status & GEN6_RCn_MASK) {
1587 case GEN6_RC0:
1588 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1589 seq_puts(m, "Core Power Down\n");
1590 else
1591 seq_puts(m, "on\n");
1592 break;
1593 case GEN6_RC3:
1594 seq_puts(m, "RC3\n");
1595 break;
1596 case GEN6_RC6:
1597 seq_puts(m, "RC6\n");
1598 break;
1599 case GEN6_RC7:
1600 seq_puts(m, "RC7\n");
1601 break;
1602 default:
1603 seq_puts(m, "Unknown\n");
1604 break;
1605 }
1606
1607 seq_printf(m, "Core Power Down: %s\n",
1608 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1609 if (INTEL_GEN(dev_priv) >= 9) {
1610 seq_printf(m, "Render Power Well: %s\n",
1611 (gen9_powergate_status &
1612 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1613 seq_printf(m, "Media Power Well: %s\n",
1614 (gen9_powergate_status &
1615 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1616 }
1617
1618 /* Not exactly sure what this is */
1619 print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1620 GEN6_GT_GFX_RC6_LOCKED);
1621 print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1622 print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1623 print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1624
1625 seq_printf(m, "RC6 voltage: %dmV\n",
1626 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1627 seq_printf(m, "RC6+ voltage: %dmV\n",
1628 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1629 seq_printf(m, "RC6++ voltage: %dmV\n",
1630 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1631 return i915_forcewake_domains(m, NULL);
1632 }
1633
1634 static int i915_drpc_info(struct seq_file *m, void *unused)
1635 {
1636 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1637 int err;
1638
1639 intel_runtime_pm_get(dev_priv);
1640
1641 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1642 err = vlv_drpc_info(m);
1643 else if (INTEL_GEN(dev_priv) >= 6)
1644 err = gen6_drpc_info(m);
1645 else
1646 err = ironlake_drpc_info(m);
1647
1648 intel_runtime_pm_put(dev_priv);
1649
1650 return err;
1651 }
1652
1653 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1654 {
1655 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1656
1657 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1658 dev_priv->fb_tracking.busy_bits);
1659
1660 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1661 dev_priv->fb_tracking.flip_bits);
1662
1663 return 0;
1664 }
1665
1666 static int i915_fbc_status(struct seq_file *m, void *unused)
1667 {
1668 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1669
1670 if (!HAS_FBC(dev_priv)) {
1671 seq_puts(m, "FBC unsupported on this chipset\n");
1672 return 0;
1673 }
1674
1675 intel_runtime_pm_get(dev_priv);
1676 mutex_lock(&dev_priv->fbc.lock);
1677
1678 if (intel_fbc_is_active(dev_priv))
1679 seq_puts(m, "FBC enabled\n");
1680 else
1681 seq_printf(m, "FBC disabled: %s\n",
1682 dev_priv->fbc.no_fbc_reason);
1683
1684 if (intel_fbc_is_active(dev_priv)) {
1685 u32 mask;
1686
1687 if (INTEL_GEN(dev_priv) >= 8)
1688 mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1689 else if (INTEL_GEN(dev_priv) >= 7)
1690 mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1691 else if (INTEL_GEN(dev_priv) >= 5)
1692 mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1693 else if (IS_G4X(dev_priv))
1694 mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1695 else
1696 mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1697 FBC_STAT_COMPRESSED);
1698
1699 seq_printf(m, "Compressing: %s\n", yesno(mask));
1700 }
1701
1702 mutex_unlock(&dev_priv->fbc.lock);
1703 intel_runtime_pm_put(dev_priv);
1704
1705 return 0;
1706 }
1707
1708 static int i915_fbc_false_color_get(void *data, u64 *val)
1709 {
1710 struct drm_i915_private *dev_priv = data;
1711
1712 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1713 return -ENODEV;
1714
1715 *val = dev_priv->fbc.false_color;
1716
1717 return 0;
1718 }
1719
1720 static int i915_fbc_false_color_set(void *data, u64 val)
1721 {
1722 struct drm_i915_private *dev_priv = data;
1723 u32 reg;
1724
1725 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1726 return -ENODEV;
1727
1728 mutex_lock(&dev_priv->fbc.lock);
1729
1730 reg = I915_READ(ILK_DPFC_CONTROL);
1731 dev_priv->fbc.false_color = val;
1732
1733 I915_WRITE(ILK_DPFC_CONTROL, val ?
1734 (reg | FBC_CTL_FALSE_COLOR) :
1735 (reg & ~FBC_CTL_FALSE_COLOR));
1736
1737 mutex_unlock(&dev_priv->fbc.lock);
1738 return 0;
1739 }
1740
1741 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1742 i915_fbc_false_color_get, i915_fbc_false_color_set,
1743 "%llu\n");
1744
1745 static int i915_ips_status(struct seq_file *m, void *unused)
1746 {
1747 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1748
1749 if (!HAS_IPS(dev_priv)) {
1750 seq_puts(m, "not supported\n");
1751 return 0;
1752 }
1753
1754 intel_runtime_pm_get(dev_priv);
1755
1756 seq_printf(m, "Enabled by kernel parameter: %s\n",
1757 yesno(i915_modparams.enable_ips));
1758
1759 if (INTEL_GEN(dev_priv) >= 8) {
1760 seq_puts(m, "Currently: unknown\n");
1761 } else {
1762 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1763 seq_puts(m, "Currently: enabled\n");
1764 else
1765 seq_puts(m, "Currently: disabled\n");
1766 }
1767
1768 intel_runtime_pm_put(dev_priv);
1769
1770 return 0;
1771 }
1772
1773 static int i915_sr_status(struct seq_file *m, void *unused)
1774 {
1775 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1776 bool sr_enabled = false;
1777
1778 intel_runtime_pm_get(dev_priv);
1779 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1780
1781 if (INTEL_GEN(dev_priv) >= 9)
1782 /* no global SR status; inspect per-plane WM */;
1783 else if (HAS_PCH_SPLIT(dev_priv))
1784 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1785 else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1786 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1787 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1788 else if (IS_I915GM(dev_priv))
1789 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1790 else if (IS_PINEVIEW(dev_priv))
1791 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1792 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1793 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1794
1795 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1796 intel_runtime_pm_put(dev_priv);
1797
1798 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1799
1800 return 0;
1801 }
1802
1803 static int i915_emon_status(struct seq_file *m, void *unused)
1804 {
1805 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1806 struct drm_device *dev = &dev_priv->drm;
1807 unsigned long temp, chipset, gfx;
1808 int ret;
1809
1810 if (!IS_GEN5(dev_priv))
1811 return -ENODEV;
1812
1813 ret = mutex_lock_interruptible(&dev->struct_mutex);
1814 if (ret)
1815 return ret;
1816
1817 temp = i915_mch_val(dev_priv);
1818 chipset = i915_chipset_val(dev_priv);
1819 gfx = i915_gfx_val(dev_priv);
1820 mutex_unlock(&dev->struct_mutex);
1821
1822 seq_printf(m, "GMCH temp: %ld\n", temp);
1823 seq_printf(m, "Chipset power: %ld\n", chipset);
1824 seq_printf(m, "GFX power: %ld\n", gfx);
1825 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1826
1827 return 0;
1828 }
1829
1830 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1831 {
1832 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1833 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1834 int ret = 0;
1835 int gpu_freq, ia_freq;
1836 unsigned int max_gpu_freq, min_gpu_freq;
1837
1838 if (!HAS_LLC(dev_priv)) {
1839 seq_puts(m, "unsupported on this chipset\n");
1840 return 0;
1841 }
1842
1843 intel_runtime_pm_get(dev_priv);
1844
1845 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1846 if (ret)
1847 goto out;
1848
1849 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1850 /* Convert GT frequency to 50 HZ units */
1851 min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
1852 max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
1853 } else {
1854 min_gpu_freq = rps->min_freq_softlimit;
1855 max_gpu_freq = rps->max_freq_softlimit;
1856 }
1857
1858 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1859
1860 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1861 ia_freq = gpu_freq;
1862 sandybridge_pcode_read(dev_priv,
1863 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1864 &ia_freq);
1865 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1866 intel_gpu_freq(dev_priv, (gpu_freq *
1867 (IS_GEN9_BC(dev_priv) ||
1868 IS_CANNONLAKE(dev_priv) ?
1869 GEN9_FREQ_SCALER : 1))),
1870 ((ia_freq >> 0) & 0xff) * 100,
1871 ((ia_freq >> 8) & 0xff) * 100);
1872 }
1873
1874 mutex_unlock(&dev_priv->pcu_lock);
1875
1876 out:
1877 intel_runtime_pm_put(dev_priv);
1878 return ret;
1879 }
1880
1881 static int i915_opregion(struct seq_file *m, void *unused)
1882 {
1883 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1884 struct drm_device *dev = &dev_priv->drm;
1885 struct intel_opregion *opregion = &dev_priv->opregion;
1886 int ret;
1887
1888 ret = mutex_lock_interruptible(&dev->struct_mutex);
1889 if (ret)
1890 goto out;
1891
1892 if (opregion->header)
1893 seq_write(m, opregion->header, OPREGION_SIZE);
1894
1895 mutex_unlock(&dev->struct_mutex);
1896
1897 out:
1898 return 0;
1899 }
1900
1901 static int i915_vbt(struct seq_file *m, void *unused)
1902 {
1903 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1904
1905 if (opregion->vbt)
1906 seq_write(m, opregion->vbt, opregion->vbt_size);
1907
1908 return 0;
1909 }
1910
1911 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1912 {
1913 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1914 struct drm_device *dev = &dev_priv->drm;
1915 struct intel_framebuffer *fbdev_fb = NULL;
1916 struct drm_framebuffer *drm_fb;
1917 int ret;
1918
1919 ret = mutex_lock_interruptible(&dev->struct_mutex);
1920 if (ret)
1921 return ret;
1922
1923 #ifdef CONFIG_DRM_FBDEV_EMULATION
1924 if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1925 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1926
1927 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1928 fbdev_fb->base.width,
1929 fbdev_fb->base.height,
1930 fbdev_fb->base.format->depth,
1931 fbdev_fb->base.format->cpp[0] * 8,
1932 fbdev_fb->base.modifier,
1933 drm_framebuffer_read_refcount(&fbdev_fb->base));
1934 describe_obj(m, fbdev_fb->obj);
1935 seq_putc(m, '\n');
1936 }
1937 #endif
1938
1939 mutex_lock(&dev->mode_config.fb_lock);
1940 drm_for_each_fb(drm_fb, dev) {
1941 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1942 if (fb == fbdev_fb)
1943 continue;
1944
1945 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1946 fb->base.width,
1947 fb->base.height,
1948 fb->base.format->depth,
1949 fb->base.format->cpp[0] * 8,
1950 fb->base.modifier,
1951 drm_framebuffer_read_refcount(&fb->base));
1952 describe_obj(m, fb->obj);
1953 seq_putc(m, '\n');
1954 }
1955 mutex_unlock(&dev->mode_config.fb_lock);
1956 mutex_unlock(&dev->struct_mutex);
1957
1958 return 0;
1959 }
1960
1961 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1962 {
1963 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1964 ring->space, ring->head, ring->tail);
1965 }
1966
1967 static int i915_context_status(struct seq_file *m, void *unused)
1968 {
1969 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1970 struct drm_device *dev = &dev_priv->drm;
1971 struct intel_engine_cs *engine;
1972 struct i915_gem_context *ctx;
1973 enum intel_engine_id id;
1974 int ret;
1975
1976 ret = mutex_lock_interruptible(&dev->struct_mutex);
1977 if (ret)
1978 return ret;
1979
1980 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1981 seq_printf(m, "HW context %u ", ctx->hw_id);
1982 if (ctx->pid) {
1983 struct task_struct *task;
1984
1985 task = get_pid_task(ctx->pid, PIDTYPE_PID);
1986 if (task) {
1987 seq_printf(m, "(%s [%d]) ",
1988 task->comm, task->pid);
1989 put_task_struct(task);
1990 }
1991 } else if (IS_ERR(ctx->file_priv)) {
1992 seq_puts(m, "(deleted) ");
1993 } else {
1994 seq_puts(m, "(kernel) ");
1995 }
1996
1997 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1998 seq_putc(m, '\n');
1999
2000 for_each_engine(engine, dev_priv, id) {
2001 struct intel_context *ce = &ctx->engine[engine->id];
2002
2003 seq_printf(m, "%s: ", engine->name);
2004 seq_putc(m, ce->initialised ? 'I' : 'i');
2005 if (ce->state)
2006 describe_obj(m, ce->state->obj);
2007 if (ce->ring)
2008 describe_ctx_ring(m, ce->ring);
2009 seq_putc(m, '\n');
2010 }
2011
2012 seq_putc(m, '\n');
2013 }
2014
2015 mutex_unlock(&dev->struct_mutex);
2016
2017 return 0;
2018 }
2019
2020 static void i915_dump_lrc_obj(struct seq_file *m,
2021 struct i915_gem_context *ctx,
2022 struct intel_engine_cs *engine)
2023 {
2024 struct i915_vma *vma = ctx->engine[engine->id].state;
2025 struct page *page;
2026 int j;
2027
2028 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2029
2030 if (!vma) {
2031 seq_puts(m, "\tFake context\n");
2032 return;
2033 }
2034
2035 if (vma->flags & I915_VMA_GLOBAL_BIND)
2036 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2037 i915_ggtt_offset(vma));
2038
2039 if (i915_gem_object_pin_pages(vma->obj)) {
2040 seq_puts(m, "\tFailed to get pages for context object\n\n");
2041 return;
2042 }
2043
2044 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2045 if (page) {
2046 u32 *reg_state = kmap_atomic(page);
2047
2048 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2049 seq_printf(m,
2050 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2051 j * 4,
2052 reg_state[j], reg_state[j + 1],
2053 reg_state[j + 2], reg_state[j + 3]);
2054 }
2055 kunmap_atomic(reg_state);
2056 }
2057
2058 i915_gem_object_unpin_pages(vma->obj);
2059 seq_putc(m, '\n');
2060 }
2061
2062 static int i915_dump_lrc(struct seq_file *m, void *unused)
2063 {
2064 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2065 struct drm_device *dev = &dev_priv->drm;
2066 struct intel_engine_cs *engine;
2067 struct i915_gem_context *ctx;
2068 enum intel_engine_id id;
2069 int ret;
2070
2071 if (!i915_modparams.enable_execlists) {
2072 seq_printf(m, "Logical Ring Contexts are disabled\n");
2073 return 0;
2074 }
2075
2076 ret = mutex_lock_interruptible(&dev->struct_mutex);
2077 if (ret)
2078 return ret;
2079
2080 list_for_each_entry(ctx, &dev_priv->contexts.list, link)
2081 for_each_engine(engine, dev_priv, id)
2082 i915_dump_lrc_obj(m, ctx, engine);
2083
2084 mutex_unlock(&dev->struct_mutex);
2085
2086 return 0;
2087 }
2088
2089 static const char *swizzle_string(unsigned swizzle)
2090 {
2091 switch (swizzle) {
2092 case I915_BIT_6_SWIZZLE_NONE:
2093 return "none";
2094 case I915_BIT_6_SWIZZLE_9:
2095 return "bit9";
2096 case I915_BIT_6_SWIZZLE_9_10:
2097 return "bit9/bit10";
2098 case I915_BIT_6_SWIZZLE_9_11:
2099 return "bit9/bit11";
2100 case I915_BIT_6_SWIZZLE_9_10_11:
2101 return "bit9/bit10/bit11";
2102 case I915_BIT_6_SWIZZLE_9_17:
2103 return "bit9/bit17";
2104 case I915_BIT_6_SWIZZLE_9_10_17:
2105 return "bit9/bit10/bit17";
2106 case I915_BIT_6_SWIZZLE_UNKNOWN:
2107 return "unknown";
2108 }
2109
2110 return "bug";
2111 }
2112
2113 static int i915_swizzle_info(struct seq_file *m, void *data)
2114 {
2115 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2116
2117 intel_runtime_pm_get(dev_priv);
2118
2119 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2120 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2121 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2122 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2123
2124 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2125 seq_printf(m, "DDC = 0x%08x\n",
2126 I915_READ(DCC));
2127 seq_printf(m, "DDC2 = 0x%08x\n",
2128 I915_READ(DCC2));
2129 seq_printf(m, "C0DRB3 = 0x%04x\n",
2130 I915_READ16(C0DRB3));
2131 seq_printf(m, "C1DRB3 = 0x%04x\n",
2132 I915_READ16(C1DRB3));
2133 } else if (INTEL_GEN(dev_priv) >= 6) {
2134 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2135 I915_READ(MAD_DIMM_C0));
2136 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2137 I915_READ(MAD_DIMM_C1));
2138 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2139 I915_READ(MAD_DIMM_C2));
2140 seq_printf(m, "TILECTL = 0x%08x\n",
2141 I915_READ(TILECTL));
2142 if (INTEL_GEN(dev_priv) >= 8)
2143 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2144 I915_READ(GAMTARBMODE));
2145 else
2146 seq_printf(m, "ARB_MODE = 0x%08x\n",
2147 I915_READ(ARB_MODE));
2148 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2149 I915_READ(DISP_ARB_CTL));
2150 }
2151
2152 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2153 seq_puts(m, "L-shaped memory detected\n");
2154
2155 intel_runtime_pm_put(dev_priv);
2156
2157 return 0;
2158 }
2159
2160 static int per_file_ctx(int id, void *ptr, void *data)
2161 {
2162 struct i915_gem_context *ctx = ptr;
2163 struct seq_file *m = data;
2164 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2165
2166 if (!ppgtt) {
2167 seq_printf(m, " no ppgtt for context %d\n",
2168 ctx->user_handle);
2169 return 0;
2170 }
2171
2172 if (i915_gem_context_is_default(ctx))
2173 seq_puts(m, " default context:\n");
2174 else
2175 seq_printf(m, " context %d:\n", ctx->user_handle);
2176 ppgtt->debug_dump(ppgtt, m);
2177
2178 return 0;
2179 }
2180
2181 static void gen8_ppgtt_info(struct seq_file *m,
2182 struct drm_i915_private *dev_priv)
2183 {
2184 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2185 struct intel_engine_cs *engine;
2186 enum intel_engine_id id;
2187 int i;
2188
2189 if (!ppgtt)
2190 return;
2191
2192 for_each_engine(engine, dev_priv, id) {
2193 seq_printf(m, "%s\n", engine->name);
2194 for (i = 0; i < 4; i++) {
2195 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2196 pdp <<= 32;
2197 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2198 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2199 }
2200 }
2201 }
2202
2203 static void gen6_ppgtt_info(struct seq_file *m,
2204 struct drm_i915_private *dev_priv)
2205 {
2206 struct intel_engine_cs *engine;
2207 enum intel_engine_id id;
2208
2209 if (IS_GEN6(dev_priv))
2210 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2211
2212 for_each_engine(engine, dev_priv, id) {
2213 seq_printf(m, "%s\n", engine->name);
2214 if (IS_GEN7(dev_priv))
2215 seq_printf(m, "GFX_MODE: 0x%08x\n",
2216 I915_READ(RING_MODE_GEN7(engine)));
2217 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2218 I915_READ(RING_PP_DIR_BASE(engine)));
2219 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2220 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2221 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2222 I915_READ(RING_PP_DIR_DCLV(engine)));
2223 }
2224 if (dev_priv->mm.aliasing_ppgtt) {
2225 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2226
2227 seq_puts(m, "aliasing PPGTT:\n");
2228 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2229
2230 ppgtt->debug_dump(ppgtt, m);
2231 }
2232
2233 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2234 }
2235
2236 static int i915_ppgtt_info(struct seq_file *m, void *data)
2237 {
2238 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2239 struct drm_device *dev = &dev_priv->drm;
2240 struct drm_file *file;
2241 int ret;
2242
2243 mutex_lock(&dev->filelist_mutex);
2244 ret = mutex_lock_interruptible(&dev->struct_mutex);
2245 if (ret)
2246 goto out_unlock;
2247
2248 intel_runtime_pm_get(dev_priv);
2249
2250 if (INTEL_GEN(dev_priv) >= 8)
2251 gen8_ppgtt_info(m, dev_priv);
2252 else if (INTEL_GEN(dev_priv) >= 6)
2253 gen6_ppgtt_info(m, dev_priv);
2254
2255 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2256 struct drm_i915_file_private *file_priv = file->driver_priv;
2257 struct task_struct *task;
2258
2259 task = get_pid_task(file->pid, PIDTYPE_PID);
2260 if (!task) {
2261 ret = -ESRCH;
2262 goto out_rpm;
2263 }
2264 seq_printf(m, "\nproc: %s\n", task->comm);
2265 put_task_struct(task);
2266 idr_for_each(&file_priv->context_idr, per_file_ctx,
2267 (void *)(unsigned long)m);
2268 }
2269
2270 out_rpm:
2271 intel_runtime_pm_put(dev_priv);
2272 mutex_unlock(&dev->struct_mutex);
2273 out_unlock:
2274 mutex_unlock(&dev->filelist_mutex);
2275 return ret;
2276 }
2277
2278 static int count_irq_waiters(struct drm_i915_private *i915)
2279 {
2280 struct intel_engine_cs *engine;
2281 enum intel_engine_id id;
2282 int count = 0;
2283
2284 for_each_engine(engine, i915, id)
2285 count += intel_engine_has_waiter(engine);
2286
2287 return count;
2288 }
2289
2290 static const char *rps_power_to_str(unsigned int power)
2291 {
2292 static const char * const strings[] = {
2293 [LOW_POWER] = "low power",
2294 [BETWEEN] = "mixed",
2295 [HIGH_POWER] = "high power",
2296 };
2297
2298 if (power >= ARRAY_SIZE(strings) || !strings[power])
2299 return "unknown";
2300
2301 return strings[power];
2302 }
2303
2304 static int i915_rps_boost_info(struct seq_file *m, void *data)
2305 {
2306 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2307 struct drm_device *dev = &dev_priv->drm;
2308 struct intel_rps *rps = &dev_priv->gt_pm.rps;
2309 struct drm_file *file;
2310
2311 seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2312 seq_printf(m, "GPU busy? %s [%d requests]\n",
2313 yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2314 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2315 seq_printf(m, "Boosts outstanding? %d\n",
2316 atomic_read(&rps->num_waiters));
2317 seq_printf(m, "Frequency requested %d\n",
2318 intel_gpu_freq(dev_priv, rps->cur_freq));
2319 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2320 intel_gpu_freq(dev_priv, rps->min_freq),
2321 intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2322 intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2323 intel_gpu_freq(dev_priv, rps->max_freq));
2324 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2325 intel_gpu_freq(dev_priv, rps->idle_freq),
2326 intel_gpu_freq(dev_priv, rps->efficient_freq),
2327 intel_gpu_freq(dev_priv, rps->boost_freq));
2328
2329 mutex_lock(&dev->filelist_mutex);
2330 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2331 struct drm_i915_file_private *file_priv = file->driver_priv;
2332 struct task_struct *task;
2333
2334 rcu_read_lock();
2335 task = pid_task(file->pid, PIDTYPE_PID);
2336 seq_printf(m, "%s [%d]: %d boosts\n",
2337 task ? task->comm : "<unknown>",
2338 task ? task->pid : -1,
2339 atomic_read(&file_priv->rps_client.boosts));
2340 rcu_read_unlock();
2341 }
2342 seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2343 atomic_read(&rps->boosts));
2344 mutex_unlock(&dev->filelist_mutex);
2345
2346 if (INTEL_GEN(dev_priv) >= 6 &&
2347 rps->enabled &&
2348 dev_priv->gt.active_requests) {
2349 u32 rpup, rpupei;
2350 u32 rpdown, rpdownei;
2351
2352 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2353 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2354 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2355 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2356 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2357 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2358
2359 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2360 rps_power_to_str(rps->power));
2361 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2362 rpup && rpupei ? 100 * rpup / rpupei : 0,
2363 rps->up_threshold);
2364 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2365 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2366 rps->down_threshold);
2367 } else {
2368 seq_puts(m, "\nRPS Autotuning inactive\n");
2369 }
2370
2371 return 0;
2372 }
2373
2374 static int i915_llc(struct seq_file *m, void *data)
2375 {
2376 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2377 const bool edram = INTEL_GEN(dev_priv) > 8;
2378
2379 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2380 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2381 intel_uncore_edram_size(dev_priv)/1024/1024);
2382
2383 return 0;
2384 }
2385
2386 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2387 {
2388 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2389 struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
2390
2391 if (!HAS_HUC_UCODE(dev_priv))
2392 return 0;
2393
2394 seq_puts(m, "HuC firmware status:\n");
2395 seq_printf(m, "\tpath: %s\n", huc_fw->path);
2396 seq_printf(m, "\tfetch: %s\n",
2397 intel_uc_fw_status_repr(huc_fw->fetch_status));
2398 seq_printf(m, "\tload: %s\n",
2399 intel_uc_fw_status_repr(huc_fw->load_status));
2400 seq_printf(m, "\tversion wanted: %d.%d\n",
2401 huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
2402 seq_printf(m, "\tversion found: %d.%d\n",
2403 huc_fw->major_ver_found, huc_fw->minor_ver_found);
2404 seq_printf(m, "\theader: offset is %d; size = %d\n",
2405 huc_fw->header_offset, huc_fw->header_size);
2406 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2407 huc_fw->ucode_offset, huc_fw->ucode_size);
2408 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2409 huc_fw->rsa_offset, huc_fw->rsa_size);
2410
2411 intel_runtime_pm_get(dev_priv);
2412 seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2413 intel_runtime_pm_put(dev_priv);
2414
2415 return 0;
2416 }
2417
2418 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2419 {
2420 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2421 struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
2422 u32 tmp, i;
2423
2424 if (!HAS_GUC_UCODE(dev_priv))
2425 return 0;
2426
2427 seq_printf(m, "GuC firmware status:\n");
2428 seq_printf(m, "\tpath: %s\n",
2429 guc_fw->path);
2430 seq_printf(m, "\tfetch: %s\n",
2431 intel_uc_fw_status_repr(guc_fw->fetch_status));
2432 seq_printf(m, "\tload: %s\n",
2433 intel_uc_fw_status_repr(guc_fw->load_status));
2434 seq_printf(m, "\tversion wanted: %d.%d\n",
2435 guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
2436 seq_printf(m, "\tversion found: %d.%d\n",
2437 guc_fw->major_ver_found, guc_fw->minor_ver_found);
2438 seq_printf(m, "\theader: offset is %d; size = %d\n",
2439 guc_fw->header_offset, guc_fw->header_size);
2440 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2441 guc_fw->ucode_offset, guc_fw->ucode_size);
2442 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2443 guc_fw->rsa_offset, guc_fw->rsa_size);
2444
2445 intel_runtime_pm_get(dev_priv);
2446
2447 tmp = I915_READ(GUC_STATUS);
2448
2449 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2450 seq_printf(m, "\tBootrom status = 0x%x\n",
2451 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2452 seq_printf(m, "\tuKernel status = 0x%x\n",
2453 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2454 seq_printf(m, "\tMIA Core status = 0x%x\n",
2455 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2456 seq_puts(m, "\nScratch registers:\n");
2457 for (i = 0; i < 16; i++)
2458 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2459
2460 intel_runtime_pm_put(dev_priv);
2461
2462 return 0;
2463 }
2464
2465 static void i915_guc_log_info(struct seq_file *m,
2466 struct drm_i915_private *dev_priv)
2467 {
2468 struct intel_guc *guc = &dev_priv->guc;
2469
2470 seq_puts(m, "\nGuC logging stats:\n");
2471
2472 seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
2473 guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2474 guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2475
2476 seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
2477 guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2478 guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2479
2480 seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2481 guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2482 guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2483
2484 seq_printf(m, "\tTotal flush interrupt count: %u\n",
2485 guc->log.flush_interrupt_count);
2486
2487 seq_printf(m, "\tCapture miss count: %u\n",
2488 guc->log.capture_miss_count);
2489 }
2490
2491 static void i915_guc_client_info(struct seq_file *m,
2492 struct drm_i915_private *dev_priv,
2493 struct i915_guc_client *client)
2494 {
2495 struct intel_engine_cs *engine;
2496 enum intel_engine_id id;
2497 uint64_t tot = 0;
2498
2499 seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2500 client->priority, client->stage_id, client->proc_desc_offset);
2501 seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2502 client->doorbell_id, client->doorbell_offset);
2503
2504 for_each_engine(engine, dev_priv, id) {
2505 u64 submissions = client->submissions[id];
2506 tot += submissions;
2507 seq_printf(m, "\tSubmissions: %llu %s\n",
2508 submissions, engine->name);
2509 }
2510 seq_printf(m, "\tTotal: %llu\n", tot);
2511 }
2512
2513 static bool check_guc_submission(struct seq_file *m)
2514 {
2515 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2516 const struct intel_guc *guc = &dev_priv->guc;
2517
2518 if (!guc->execbuf_client) {
2519 seq_printf(m, "GuC submission %s\n",
2520 HAS_GUC_SCHED(dev_priv) ?
2521 "disabled" :
2522 "not supported");
2523 return false;
2524 }
2525
2526 return true;
2527 }
2528
2529 static int i915_guc_info(struct seq_file *m, void *data)
2530 {
2531 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2532 const struct intel_guc *guc = &dev_priv->guc;
2533
2534 if (!check_guc_submission(m))
2535 return 0;
2536
2537 seq_printf(m, "Doorbell map:\n");
2538 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2539 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2540
2541 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2542 i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2543
2544 i915_guc_log_info(m, dev_priv);
2545
2546 /* Add more as required ... */
2547
2548 return 0;
2549 }
2550
2551 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2552 {
2553 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2554 const struct intel_guc *guc = &dev_priv->guc;
2555 struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2556 struct i915_guc_client *client = guc->execbuf_client;
2557 unsigned int tmp;
2558 int index;
2559
2560 if (!check_guc_submission(m))
2561 return 0;
2562
2563 for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2564 struct intel_engine_cs *engine;
2565
2566 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2567 continue;
2568
2569 seq_printf(m, "GuC stage descriptor %u:\n", index);
2570 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2571 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2572 seq_printf(m, "\tPriority: %d\n", desc->priority);
2573 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2574 seq_printf(m, "\tEngines used: 0x%x\n",
2575 desc->engines_used);
2576 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2577 desc->db_trigger_phy,
2578 desc->db_trigger_cpu,
2579 desc->db_trigger_uk);
2580 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2581 desc->process_desc);
2582 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2583 desc->wq_addr, desc->wq_size);
2584 seq_putc(m, '\n');
2585
2586 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2587 u32 guc_engine_id = engine->guc_id;
2588 struct guc_execlist_context *lrc =
2589 &desc->lrc[guc_engine_id];
2590
2591 seq_printf(m, "\t%s LRC:\n", engine->name);
2592 seq_printf(m, "\t\tContext desc: 0x%x\n",
2593 lrc->context_desc);
2594 seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2595 seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2596 seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2597 seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2598 seq_putc(m, '\n');
2599 }
2600 }
2601
2602 return 0;
2603 }
2604
2605 static int i915_guc_log_dump(struct seq_file *m, void *data)
2606 {
2607 struct drm_info_node *node = m->private;
2608 struct drm_i915_private *dev_priv = node_to_i915(node);
2609 bool dump_load_err = !!node->info_ent->data;
2610 struct drm_i915_gem_object *obj = NULL;
2611 u32 *log;
2612 int i = 0;
2613
2614 if (dump_load_err)
2615 obj = dev_priv->guc.load_err_log;
2616 else if (dev_priv->guc.log.vma)
2617 obj = dev_priv->guc.log.vma->obj;
2618
2619 if (!obj)
2620 return 0;
2621
2622 log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2623 if (IS_ERR(log)) {
2624 DRM_DEBUG("Failed to pin object\n");
2625 seq_puts(m, "(log data unaccessible)\n");
2626 return PTR_ERR(log);
2627 }
2628
2629 for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2630 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2631 *(log + i), *(log + i + 1),
2632 *(log + i + 2), *(log + i + 3));
2633
2634 seq_putc(m, '\n');
2635
2636 i915_gem_object_unpin_map(obj);
2637
2638 return 0;
2639 }
2640
2641 static int i915_guc_log_control_get(void *data, u64 *val)
2642 {
2643 struct drm_i915_private *dev_priv = data;
2644
2645 if (!dev_priv->guc.log.vma)
2646 return -EINVAL;
2647
2648 *val = i915_modparams.guc_log_level;
2649
2650 return 0;
2651 }
2652
2653 static int i915_guc_log_control_set(void *data, u64 val)
2654 {
2655 struct drm_i915_private *dev_priv = data;
2656 int ret;
2657
2658 if (!dev_priv->guc.log.vma)
2659 return -EINVAL;
2660
2661 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
2662 if (ret)
2663 return ret;
2664
2665 intel_runtime_pm_get(dev_priv);
2666 ret = i915_guc_log_control(dev_priv, val);
2667 intel_runtime_pm_put(dev_priv);
2668
2669 mutex_unlock(&dev_priv->drm.struct_mutex);
2670 return ret;
2671 }
2672
2673 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2674 i915_guc_log_control_get, i915_guc_log_control_set,
2675 "%lld\n");
2676
2677 static const char *psr2_live_status(u32 val)
2678 {
2679 static const char * const live_status[] = {
2680 "IDLE",
2681 "CAPTURE",
2682 "CAPTURE_FS",
2683 "SLEEP",
2684 "BUFON_FW",
2685 "ML_UP",
2686 "SU_STANDBY",
2687 "FAST_SLEEP",
2688 "DEEP_SLEEP",
2689 "BUF_ON",
2690 "TG_ON"
2691 };
2692
2693 val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2694 if (val < ARRAY_SIZE(live_status))
2695 return live_status[val];
2696
2697 return "unknown";
2698 }
2699
2700 static int i915_edp_psr_status(struct seq_file *m, void *data)
2701 {
2702 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2703 u32 psrperf = 0;
2704 u32 stat[3];
2705 enum pipe pipe;
2706 bool enabled = false;
2707
2708 if (!HAS_PSR(dev_priv)) {
2709 seq_puts(m, "PSR not supported\n");
2710 return 0;
2711 }
2712
2713 intel_runtime_pm_get(dev_priv);
2714
2715 mutex_lock(&dev_priv->psr.lock);
2716 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2717 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2718 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2719 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2720 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2721 dev_priv->psr.busy_frontbuffer_bits);
2722 seq_printf(m, "Re-enable work scheduled: %s\n",
2723 yesno(work_busy(&dev_priv->psr.work.work)));
2724
2725 if (HAS_DDI(dev_priv)) {
2726 if (dev_priv->psr.psr2_support)
2727 enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2728 else
2729 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2730 } else {
2731 for_each_pipe(dev_priv, pipe) {
2732 enum transcoder cpu_transcoder =
2733 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2734 enum intel_display_power_domain power_domain;
2735
2736 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2737 if (!intel_display_power_get_if_enabled(dev_priv,
2738 power_domain))
2739 continue;
2740
2741 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2742 VLV_EDP_PSR_CURR_STATE_MASK;
2743 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2744 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2745 enabled = true;
2746
2747 intel_display_power_put(dev_priv, power_domain);
2748 }
2749 }
2750
2751 seq_printf(m, "Main link in standby mode: %s\n",
2752 yesno(dev_priv->psr.link_standby));
2753
2754 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2755
2756 if (!HAS_DDI(dev_priv))
2757 for_each_pipe(dev_priv, pipe) {
2758 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2759 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2760 seq_printf(m, " pipe %c", pipe_name(pipe));
2761 }
2762 seq_puts(m, "\n");
2763
2764 /*
2765 * VLV/CHV PSR has no kind of performance counter
2766 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2767 */
2768 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2769 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2770 EDP_PSR_PERF_CNT_MASK;
2771
2772 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2773 }
2774 if (dev_priv->psr.psr2_support) {
2775 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2776
2777 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2778 psr2, psr2_live_status(psr2));
2779 }
2780 mutex_unlock(&dev_priv->psr.lock);
2781
2782 intel_runtime_pm_put(dev_priv);
2783 return 0;
2784 }
2785
2786 static int i915_sink_crc(struct seq_file *m, void *data)
2787 {
2788 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2789 struct drm_device *dev = &dev_priv->drm;
2790 struct intel_connector *connector;
2791 struct drm_connector_list_iter conn_iter;
2792 struct intel_dp *intel_dp = NULL;
2793 int ret;
2794 u8 crc[6];
2795
2796 drm_modeset_lock_all(dev);
2797 drm_connector_list_iter_begin(dev, &conn_iter);
2798 for_each_intel_connector_iter(connector, &conn_iter) {
2799 struct drm_crtc *crtc;
2800
2801 if (!connector->base.state->best_encoder)
2802 continue;
2803
2804 crtc = connector->base.state->crtc;
2805 if (!crtc->state->active)
2806 continue;
2807
2808 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2809 continue;
2810
2811 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2812
2813 ret = intel_dp_sink_crc(intel_dp, crc);
2814 if (ret)
2815 goto out;
2816
2817 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2818 crc[0], crc[1], crc[2],
2819 crc[3], crc[4], crc[5]);
2820 goto out;
2821 }
2822 ret = -ENODEV;
2823 out:
2824 drm_connector_list_iter_end(&conn_iter);
2825 drm_modeset_unlock_all(dev);
2826 return ret;
2827 }
2828
2829 static int i915_energy_uJ(struct seq_file *m, void *data)
2830 {
2831 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2832 unsigned long long power;
2833 u32 units;
2834
2835 if (INTEL_GEN(dev_priv) < 6)
2836 return -ENODEV;
2837
2838 intel_runtime_pm_get(dev_priv);
2839
2840 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2841 intel_runtime_pm_put(dev_priv);
2842 return -ENODEV;
2843 }
2844
2845 units = (power & 0x1f00) >> 8;
2846 power = I915_READ(MCH_SECP_NRG_STTS);
2847 power = (1000000 * power) >> units; /* convert to uJ */
2848
2849 intel_runtime_pm_put(dev_priv);
2850
2851 seq_printf(m, "%llu", power);
2852
2853 return 0;
2854 }
2855
2856 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2857 {
2858 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2859 struct pci_dev *pdev = dev_priv->drm.pdev;
2860
2861 if (!HAS_RUNTIME_PM(dev_priv))
2862 seq_puts(m, "Runtime power management not supported\n");
2863
2864 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2865 seq_printf(m, "IRQs disabled: %s\n",
2866 yesno(!intel_irqs_enabled(dev_priv)));
2867 #ifdef CONFIG_PM
2868 seq_printf(m, "Usage count: %d\n",
2869 atomic_read(&dev_priv->drm.dev->power.usage_count));
2870 #else
2871 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2872 #endif
2873 seq_printf(m, "PCI device power state: %s [%d]\n",
2874 pci_power_name(pdev->current_state),
2875 pdev->current_state);
2876
2877 return 0;
2878 }
2879
2880 static int i915_power_domain_info(struct seq_file *m, void *unused)
2881 {
2882 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2883 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2884 int i;
2885
2886 mutex_lock(&power_domains->lock);
2887
2888 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2889 for (i = 0; i < power_domains->power_well_count; i++) {
2890 struct i915_power_well *power_well;
2891 enum intel_display_power_domain power_domain;
2892
2893 power_well = &power_domains->power_wells[i];
2894 seq_printf(m, "%-25s %d\n", power_well->name,
2895 power_well->count);
2896
2897 for_each_power_domain(power_domain, power_well->domains)
2898 seq_printf(m, " %-23s %d\n",
2899 intel_display_power_domain_str(power_domain),
2900 power_domains->domain_use_count[power_domain]);
2901 }
2902
2903 mutex_unlock(&power_domains->lock);
2904
2905 return 0;
2906 }
2907
2908 static int i915_dmc_info(struct seq_file *m, void *unused)
2909 {
2910 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2911 struct intel_csr *csr;
2912
2913 if (!HAS_CSR(dev_priv)) {
2914 seq_puts(m, "not supported\n");
2915 return 0;
2916 }
2917
2918 csr = &dev_priv->csr;
2919
2920 intel_runtime_pm_get(dev_priv);
2921
2922 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2923 seq_printf(m, "path: %s\n", csr->fw_path);
2924
2925 if (!csr->dmc_payload)
2926 goto out;
2927
2928 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2929 CSR_VERSION_MINOR(csr->version));
2930
2931 if (IS_KABYLAKE(dev_priv) ||
2932 (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2933 seq_printf(m, "DC3 -> DC5 count: %d\n",
2934 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2935 seq_printf(m, "DC5 -> DC6 count: %d\n",
2936 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2937 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2938 seq_printf(m, "DC3 -> DC5 count: %d\n",
2939 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2940 }
2941
2942 out:
2943 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2944 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2945 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2946
2947 intel_runtime_pm_put(dev_priv);
2948
2949 return 0;
2950 }
2951
2952 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2953 struct drm_display_mode *mode)
2954 {
2955 int i;
2956
2957 for (i = 0; i < tabs; i++)
2958 seq_putc(m, '\t');
2959
2960 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2961 mode->base.id, mode->name,
2962 mode->vrefresh, mode->clock,
2963 mode->hdisplay, mode->hsync_start,
2964 mode->hsync_end, mode->htotal,
2965 mode->vdisplay, mode->vsync_start,
2966 mode->vsync_end, mode->vtotal,
2967 mode->type, mode->flags);
2968 }
2969
2970 static void intel_encoder_info(struct seq_file *m,
2971 struct intel_crtc *intel_crtc,
2972 struct intel_encoder *intel_encoder)
2973 {
2974 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2975 struct drm_device *dev = &dev_priv->drm;
2976 struct drm_crtc *crtc = &intel_crtc->base;
2977 struct intel_connector *intel_connector;
2978 struct drm_encoder *encoder;
2979
2980 encoder = &intel_encoder->base;
2981 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2982 encoder->base.id, encoder->name);
2983 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2984 struct drm_connector *connector = &intel_connector->base;
2985 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2986 connector->base.id,
2987 connector->name,
2988 drm_get_connector_status_name(connector->status));
2989 if (connector->status == connector_status_connected) {
2990 struct drm_display_mode *mode = &crtc->mode;
2991 seq_printf(m, ", mode:\n");
2992 intel_seq_print_mode(m, 2, mode);
2993 } else {
2994 seq_putc(m, '\n');
2995 }
2996 }
2997 }
2998
2999 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3000 {
3001 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3002 struct drm_device *dev = &dev_priv->drm;
3003 struct drm_crtc *crtc = &intel_crtc->base;
3004 struct intel_encoder *intel_encoder;
3005 struct drm_plane_state *plane_state = crtc->primary->state;
3006 struct drm_framebuffer *fb = plane_state->fb;
3007
3008 if (fb)
3009 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
3010 fb->base.id, plane_state->src_x >> 16,
3011 plane_state->src_y >> 16, fb->width, fb->height);
3012 else
3013 seq_puts(m, "\tprimary plane disabled\n");
3014 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3015 intel_encoder_info(m, intel_crtc, intel_encoder);
3016 }
3017
3018 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
3019 {
3020 struct drm_display_mode *mode = panel->fixed_mode;
3021
3022 seq_printf(m, "\tfixed mode:\n");
3023 intel_seq_print_mode(m, 2, mode);
3024 }
3025
3026 static void intel_dp_info(struct seq_file *m,
3027 struct intel_connector *intel_connector)
3028 {
3029 struct intel_encoder *intel_encoder = intel_connector->encoder;
3030 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3031
3032 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
3033 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
3034 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
3035 intel_panel_info(m, &intel_connector->panel);
3036
3037 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
3038 &intel_dp->aux);
3039 }
3040
3041 static void intel_dp_mst_info(struct seq_file *m,
3042 struct intel_connector *intel_connector)
3043 {
3044 struct intel_encoder *intel_encoder = intel_connector->encoder;
3045 struct intel_dp_mst_encoder *intel_mst =
3046 enc_to_mst(&intel_encoder->base);
3047 struct intel_digital_port *intel_dig_port = intel_mst->primary;
3048 struct intel_dp *intel_dp = &intel_dig_port->dp;
3049 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
3050 intel_connector->port);
3051
3052 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
3053 }
3054
3055 static void intel_hdmi_info(struct seq_file *m,
3056 struct intel_connector *intel_connector)
3057 {
3058 struct intel_encoder *intel_encoder = intel_connector->encoder;
3059 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
3060
3061 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
3062 }
3063
3064 static void intel_lvds_info(struct seq_file *m,
3065 struct intel_connector *intel_connector)
3066 {
3067 intel_panel_info(m, &intel_connector->panel);
3068 }
3069
3070 static void intel_connector_info(struct seq_file *m,
3071 struct drm_connector *connector)
3072 {
3073 struct intel_connector *intel_connector = to_intel_connector(connector);
3074 struct intel_encoder *intel_encoder = intel_connector->encoder;
3075 struct drm_display_mode *mode;
3076
3077 seq_printf(m, "connector %d: type %s, status: %s\n",
3078 connector->base.id, connector->name,
3079 drm_get_connector_status_name(connector->status));
3080 if (connector->status == connector_status_connected) {
3081 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3082 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3083 connector->display_info.width_mm,
3084 connector->display_info.height_mm);
3085 seq_printf(m, "\tsubpixel order: %s\n",
3086 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3087 seq_printf(m, "\tCEA rev: %d\n",
3088 connector->display_info.cea_rev);
3089 }
3090
3091 if (!intel_encoder)
3092 return;
3093
3094 switch (connector->connector_type) {
3095 case DRM_MODE_CONNECTOR_DisplayPort:
3096 case DRM_MODE_CONNECTOR_eDP:
3097 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3098 intel_dp_mst_info(m, intel_connector);
3099 else
3100 intel_dp_info(m, intel_connector);
3101 break;
3102 case DRM_MODE_CONNECTOR_LVDS:
3103 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3104 intel_lvds_info(m, intel_connector);
3105 break;
3106 case DRM_MODE_CONNECTOR_HDMIA:
3107 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3108 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3109 intel_hdmi_info(m, intel_connector);
3110 break;
3111 default:
3112 break;
3113 }
3114
3115 seq_printf(m, "\tmodes:\n");
3116 list_for_each_entry(mode, &connector->modes, head)
3117 intel_seq_print_mode(m, 2, mode);
3118 }
3119
3120 static const char *plane_type(enum drm_plane_type type)
3121 {
3122 switch (type) {
3123 case DRM_PLANE_TYPE_OVERLAY:
3124 return "OVL";
3125 case DRM_PLANE_TYPE_PRIMARY:
3126 return "PRI";
3127 case DRM_PLANE_TYPE_CURSOR:
3128 return "CUR";
3129 /*
3130 * Deliberately omitting default: to generate compiler warnings
3131 * when a new drm_plane_type gets added.
3132 */
3133 }
3134
3135 return "unknown";
3136 }
3137
3138 static const char *plane_rotation(unsigned int rotation)
3139 {
3140 static char buf[48];
3141 /*
3142 * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3143 * will print them all to visualize if the values are misused
3144 */
3145 snprintf(buf, sizeof(buf),
3146 "%s%s%s%s%s%s(0x%08x)",
3147 (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3148 (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3149 (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3150 (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3151 (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3152 (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3153 rotation);
3154
3155 return buf;
3156 }
3157
3158 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3159 {
3160 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3161 struct drm_device *dev = &dev_priv->drm;
3162 struct intel_plane *intel_plane;
3163
3164 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3165 struct drm_plane_state *state;
3166 struct drm_plane *plane = &intel_plane->base;
3167 struct drm_format_name_buf format_name;
3168
3169 if (!plane->state) {
3170 seq_puts(m, "plane->state is NULL!\n");
3171 continue;
3172 }
3173
3174 state = plane->state;
3175
3176 if (state->fb) {
3177 drm_get_format_name(state->fb->format->format,
3178 &format_name);
3179 } else {
3180 sprintf(format_name.str, "N/A");
3181 }
3182
3183 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3184 plane->base.id,
3185 plane_type(intel_plane->base.type),
3186 state->crtc_x, state->crtc_y,
3187 state->crtc_w, state->crtc_h,
3188 (state->src_x >> 16),
3189 ((state->src_x & 0xffff) * 15625) >> 10,
3190 (state->src_y >> 16),
3191 ((state->src_y & 0xffff) * 15625) >> 10,
3192 (state->src_w >> 16),
3193 ((state->src_w & 0xffff) * 15625) >> 10,
3194 (state->src_h >> 16),
3195 ((state->src_h & 0xffff) * 15625) >> 10,
3196 format_name.str,
3197 plane_rotation(state->rotation));
3198 }
3199 }
3200
3201 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3202 {
3203 struct intel_crtc_state *pipe_config;
3204 int num_scalers = intel_crtc->num_scalers;
3205 int i;
3206
3207 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3208
3209 /* Not all platformas have a scaler */
3210 if (num_scalers) {
3211 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3212 num_scalers,
3213 pipe_config->scaler_state.scaler_users,
3214 pipe_config->scaler_state.scaler_id);
3215
3216 for (i = 0; i < num_scalers; i++) {
3217 struct intel_scaler *sc =
3218 &pipe_config->scaler_state.scalers[i];
3219
3220 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3221 i, yesno(sc->in_use), sc->mode);
3222 }
3223 seq_puts(m, "\n");
3224 } else {
3225 seq_puts(m, "\tNo scalers available on this platform\n");
3226 }
3227 }
3228
3229 static int i915_display_info(struct seq_file *m, void *unused)
3230 {
3231 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3232 struct drm_device *dev = &dev_priv->drm;
3233 struct intel_crtc *crtc;
3234 struct drm_connector *connector;
3235 struct drm_connector_list_iter conn_iter;
3236
3237 intel_runtime_pm_get(dev_priv);
3238 seq_printf(m, "CRTC info\n");
3239 seq_printf(m, "---------\n");
3240 for_each_intel_crtc(dev, crtc) {
3241 struct intel_crtc_state *pipe_config;
3242
3243 drm_modeset_lock(&crtc->base.mutex, NULL);
3244 pipe_config = to_intel_crtc_state(crtc->base.state);
3245
3246 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3247 crtc->base.base.id, pipe_name(crtc->pipe),
3248 yesno(pipe_config->base.active),
3249 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3250 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3251
3252 if (pipe_config->base.active) {
3253 struct intel_plane *cursor =
3254 to_intel_plane(crtc->base.cursor);
3255
3256 intel_crtc_info(m, crtc);
3257
3258 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3259 yesno(cursor->base.state->visible),
3260 cursor->base.state->crtc_x,
3261 cursor->base.state->crtc_y,
3262 cursor->base.state->crtc_w,
3263 cursor->base.state->crtc_h,
3264 cursor->cursor.base);
3265 intel_scaler_info(m, crtc);
3266 intel_plane_info(m, crtc);
3267 }
3268
3269 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3270 yesno(!crtc->cpu_fifo_underrun_disabled),
3271 yesno(!crtc->pch_fifo_underrun_disabled));
3272 drm_modeset_unlock(&crtc->base.mutex);
3273 }
3274
3275 seq_printf(m, "\n");
3276 seq_printf(m, "Connector info\n");
3277 seq_printf(m, "--------------\n");
3278 mutex_lock(&dev->mode_config.mutex);
3279 drm_connector_list_iter_begin(dev, &conn_iter);
3280 drm_for_each_connector_iter(connector, &conn_iter)
3281 intel_connector_info(m, connector);
3282 drm_connector_list_iter_end(&conn_iter);
3283 mutex_unlock(&dev->mode_config.mutex);
3284
3285 intel_runtime_pm_put(dev_priv);
3286
3287 return 0;
3288 }
3289
3290 static int i915_engine_info(struct seq_file *m, void *unused)
3291 {
3292 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3293 struct intel_engine_cs *engine;
3294 enum intel_engine_id id;
3295 struct drm_printer p;
3296
3297 intel_runtime_pm_get(dev_priv);
3298
3299 seq_printf(m, "GT awake? %s\n",
3300 yesno(dev_priv->gt.awake));
3301 seq_printf(m, "Global active requests: %d\n",
3302 dev_priv->gt.active_requests);
3303
3304 p = drm_seq_file_printer(m);
3305 for_each_engine(engine, dev_priv, id)
3306 intel_engine_dump(engine, &p);
3307
3308 intel_runtime_pm_put(dev_priv);
3309
3310 return 0;
3311 }
3312
3313 static int i915_semaphore_status(struct seq_file *m, void *unused)
3314 {
3315 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3316 struct drm_device *dev = &dev_priv->drm;
3317 struct intel_engine_cs *engine;
3318 int num_rings = INTEL_INFO(dev_priv)->num_rings;
3319 enum intel_engine_id id;
3320 int j, ret;
3321
3322 if (!i915_modparams.semaphores) {
3323 seq_puts(m, "Semaphores are disabled\n");
3324 return 0;
3325 }
3326
3327 ret = mutex_lock_interruptible(&dev->struct_mutex);
3328 if (ret)
3329 return ret;
3330 intel_runtime_pm_get(dev_priv);
3331
3332 if (IS_BROADWELL(dev_priv)) {
3333 struct page *page;
3334 uint64_t *seqno;
3335
3336 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3337
3338 seqno = (uint64_t *)kmap_atomic(page);
3339 for_each_engine(engine, dev_priv, id) {
3340 uint64_t offset;
3341
3342 seq_printf(m, "%s\n", engine->name);
3343
3344 seq_puts(m, " Last signal:");
3345 for (j = 0; j < num_rings; j++) {
3346 offset = id * I915_NUM_ENGINES + j;
3347 seq_printf(m, "0x%08llx (0x%02llx) ",
3348 seqno[offset], offset * 8);
3349 }
3350 seq_putc(m, '\n');
3351
3352 seq_puts(m, " Last wait: ");
3353 for (j = 0; j < num_rings; j++) {
3354 offset = id + (j * I915_NUM_ENGINES);
3355 seq_printf(m, "0x%08llx (0x%02llx) ",
3356 seqno[offset], offset * 8);
3357 }
3358 seq_putc(m, '\n');
3359
3360 }
3361 kunmap_atomic(seqno);
3362 } else {
3363 seq_puts(m, " Last signal:");
3364 for_each_engine(engine, dev_priv, id)
3365 for (j = 0; j < num_rings; j++)
3366 seq_printf(m, "0x%08x\n",
3367 I915_READ(engine->semaphore.mbox.signal[j]));
3368 seq_putc(m, '\n');
3369 }
3370
3371 intel_runtime_pm_put(dev_priv);
3372 mutex_unlock(&dev->struct_mutex);
3373 return 0;
3374 }
3375
3376 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3377 {
3378 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3379 struct drm_device *dev = &dev_priv->drm;
3380 int i;
3381
3382 drm_modeset_lock_all(dev);
3383 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3384 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3385
3386 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3387 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3388 pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3389 seq_printf(m, " tracked hardware state:\n");
3390 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
3391 seq_printf(m, " dpll_md: 0x%08x\n",
3392 pll->state.hw_state.dpll_md);
3393 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
3394 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
3395 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
3396 }
3397 drm_modeset_unlock_all(dev);
3398
3399 return 0;
3400 }
3401
3402 static int i915_wa_registers(struct seq_file *m, void *unused)
3403 {
3404 int i;
3405 int ret;
3406 struct intel_engine_cs *engine;
3407 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3408 struct drm_device *dev = &dev_priv->drm;
3409 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3410 enum intel_engine_id id;
3411
3412 ret = mutex_lock_interruptible(&dev->struct_mutex);
3413 if (ret)
3414 return ret;
3415
3416 intel_runtime_pm_get(dev_priv);
3417
3418 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3419 for_each_engine(engine, dev_priv, id)
3420 seq_printf(m, "HW whitelist count for %s: %d\n",
3421 engine->name, workarounds->hw_whitelist_count[id]);
3422 for (i = 0; i < workarounds->count; ++i) {
3423 i915_reg_t addr;
3424 u32 mask, value, read;
3425 bool ok;
3426
3427 addr = workarounds->reg[i].addr;
3428 mask = workarounds->reg[i].mask;
3429 value = workarounds->reg[i].value;
3430 read = I915_READ(addr);
3431 ok = (value & mask) == (read & mask);
3432 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3433 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3434 }
3435
3436 intel_runtime_pm_put(dev_priv);
3437 mutex_unlock(&dev->struct_mutex);
3438
3439 return 0;
3440 }
3441
3442 static int i915_ipc_status_show(struct seq_file *m, void *data)
3443 {
3444 struct drm_i915_private *dev_priv = m->private;
3445
3446 seq_printf(m, "Isochronous Priority Control: %s\n",
3447 yesno(dev_priv->ipc_enabled));
3448 return 0;
3449 }
3450
3451 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3452 {
3453 struct drm_i915_private *dev_priv = inode->i_private;
3454
3455 if (!HAS_IPC(dev_priv))
3456 return -ENODEV;
3457
3458 return single_open(file, i915_ipc_status_show, dev_priv);
3459 }
3460
3461 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3462 size_t len, loff_t *offp)
3463 {
3464 struct seq_file *m = file->private_data;
3465 struct drm_i915_private *dev_priv = m->private;
3466 int ret;
3467 bool enable;
3468
3469 ret = kstrtobool_from_user(ubuf, len, &enable);
3470 if (ret < 0)
3471 return ret;
3472
3473 intel_runtime_pm_get(dev_priv);
3474 if (!dev_priv->ipc_enabled && enable)
3475 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3476 dev_priv->wm.distrust_bios_wm = true;
3477 dev_priv->ipc_enabled = enable;
3478 intel_enable_ipc(dev_priv);
3479 intel_runtime_pm_put(dev_priv);
3480
3481 return len;
3482 }
3483
3484 static const struct file_operations i915_ipc_status_fops = {
3485 .owner = THIS_MODULE,
3486 .open = i915_ipc_status_open,
3487 .read = seq_read,
3488 .llseek = seq_lseek,
3489 .release = single_release,
3490 .write = i915_ipc_status_write
3491 };
3492
3493 static int i915_ddb_info(struct seq_file *m, void *unused)
3494 {
3495 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3496 struct drm_device *dev = &dev_priv->drm;
3497 struct skl_ddb_allocation *ddb;
3498 struct skl_ddb_entry *entry;
3499 enum pipe pipe;
3500 int plane;
3501
3502 if (INTEL_GEN(dev_priv) < 9)
3503 return 0;
3504
3505 drm_modeset_lock_all(dev);
3506
3507 ddb = &dev_priv->wm.skl_hw.ddb;
3508
3509 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3510
3511 for_each_pipe(dev_priv, pipe) {
3512 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3513
3514 for_each_universal_plane(dev_priv, pipe, plane) {
3515 entry = &ddb->plane[pipe][plane];
3516 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3517 entry->start, entry->end,
3518 skl_ddb_entry_size(entry));
3519 }
3520
3521 entry = &ddb->plane[pipe][PLANE_CURSOR];
3522 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3523 entry->end, skl_ddb_entry_size(entry));
3524 }
3525
3526 drm_modeset_unlock_all(dev);
3527
3528 return 0;
3529 }
3530
3531 static void drrs_status_per_crtc(struct seq_file *m,
3532 struct drm_device *dev,
3533 struct intel_crtc *intel_crtc)
3534 {
3535 struct drm_i915_private *dev_priv = to_i915(dev);
3536 struct i915_drrs *drrs = &dev_priv->drrs;
3537 int vrefresh = 0;
3538 struct drm_connector *connector;
3539 struct drm_connector_list_iter conn_iter;
3540
3541 drm_connector_list_iter_begin(dev, &conn_iter);
3542 drm_for_each_connector_iter(connector, &conn_iter) {
3543 if (connector->state->crtc != &intel_crtc->base)
3544 continue;
3545
3546 seq_printf(m, "%s:\n", connector->name);
3547 }
3548 drm_connector_list_iter_end(&conn_iter);
3549
3550 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3551 seq_puts(m, "\tVBT: DRRS_type: Static");
3552 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3553 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3554 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3555 seq_puts(m, "\tVBT: DRRS_type: None");
3556 else
3557 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3558
3559 seq_puts(m, "\n\n");
3560
3561 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3562 struct intel_panel *panel;
3563
3564 mutex_lock(&drrs->mutex);
3565 /* DRRS Supported */
3566 seq_puts(m, "\tDRRS Supported: Yes\n");
3567
3568 /* disable_drrs() will make drrs->dp NULL */
3569 if (!drrs->dp) {
3570 seq_puts(m, "Idleness DRRS: Disabled");
3571 mutex_unlock(&drrs->mutex);
3572 return;
3573 }
3574
3575 panel = &drrs->dp->attached_connector->panel;
3576 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3577 drrs->busy_frontbuffer_bits);
3578
3579 seq_puts(m, "\n\t\t");
3580 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3581 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3582 vrefresh = panel->fixed_mode->vrefresh;
3583 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3584 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3585 vrefresh = panel->downclock_mode->vrefresh;
3586 } else {
3587 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3588 drrs->refresh_rate_type);
3589 mutex_unlock(&drrs->mutex);
3590 return;
3591 }
3592 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3593
3594 seq_puts(m, "\n\t\t");
3595 mutex_unlock(&drrs->mutex);
3596 } else {
3597 /* DRRS not supported. Print the VBT parameter*/
3598 seq_puts(m, "\tDRRS Supported : No");
3599 }
3600 seq_puts(m, "\n");
3601 }
3602
3603 static int i915_drrs_status(struct seq_file *m, void *unused)
3604 {
3605 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3606 struct drm_device *dev = &dev_priv->drm;
3607 struct intel_crtc *intel_crtc;
3608 int active_crtc_cnt = 0;
3609
3610 drm_modeset_lock_all(dev);
3611 for_each_intel_crtc(dev, intel_crtc) {
3612 if (intel_crtc->base.state->active) {
3613 active_crtc_cnt++;
3614 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3615
3616 drrs_status_per_crtc(m, dev, intel_crtc);
3617 }
3618 }
3619 drm_modeset_unlock_all(dev);
3620
3621 if (!active_crtc_cnt)
3622 seq_puts(m, "No active crtc found\n");
3623
3624 return 0;
3625 }
3626
3627 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3628 {
3629 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3630 struct drm_device *dev = &dev_priv->drm;
3631 struct intel_encoder *intel_encoder;
3632 struct intel_digital_port *intel_dig_port;
3633 struct drm_connector *connector;
3634 struct drm_connector_list_iter conn_iter;
3635
3636 drm_connector_list_iter_begin(dev, &conn_iter);
3637 drm_for_each_connector_iter(connector, &conn_iter) {
3638 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3639 continue;
3640
3641 intel_encoder = intel_attached_encoder(connector);
3642 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3643 continue;
3644
3645 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3646 if (!intel_dig_port->dp.can_mst)
3647 continue;
3648
3649 seq_printf(m, "MST Source Port %c\n",
3650 port_name(intel_dig_port->port));
3651 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3652 }
3653 drm_connector_list_iter_end(&conn_iter);
3654
3655 return 0;
3656 }
3657
3658 static ssize_t i915_displayport_test_active_write(struct file *file,
3659 const char __user *ubuf,
3660 size_t len, loff_t *offp)
3661 {
3662 char *input_buffer;
3663 int status = 0;
3664 struct drm_device *dev;
3665 struct drm_connector *connector;
3666 struct drm_connector_list_iter conn_iter;
3667 struct intel_dp *intel_dp;
3668 int val = 0;
3669
3670 dev = ((struct seq_file *)file->private_data)->private;
3671
3672 if (len == 0)
3673 return 0;
3674
3675 input_buffer = memdup_user_nul(ubuf, len);
3676 if (IS_ERR(input_buffer))
3677 return PTR_ERR(input_buffer);
3678
3679 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3680
3681 drm_connector_list_iter_begin(dev, &conn_iter);
3682 drm_for_each_connector_iter(connector, &conn_iter) {
3683 struct intel_encoder *encoder;
3684
3685 if (connector->connector_type !=
3686 DRM_MODE_CONNECTOR_DisplayPort)
3687 continue;
3688
3689 encoder = to_intel_encoder(connector->encoder);
3690 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3691 continue;
3692
3693 if (encoder && connector->status == connector_status_connected) {
3694 intel_dp = enc_to_intel_dp(&encoder->base);
3695 status = kstrtoint(input_buffer, 10, &val);
3696 if (status < 0)
3697 break;
3698 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3699 /* To prevent erroneous activation of the compliance
3700 * testing code, only accept an actual value of 1 here
3701 */
3702 if (val == 1)
3703 intel_dp->compliance.test_active = 1;
3704 else
3705 intel_dp->compliance.test_active = 0;
3706 }
3707 }
3708 drm_connector_list_iter_end(&conn_iter);
3709 kfree(input_buffer);
3710 if (status < 0)
3711 return status;
3712
3713 *offp += len;
3714 return len;
3715 }
3716
3717 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3718 {
3719 struct drm_device *dev = m->private;
3720 struct drm_connector *connector;
3721 struct drm_connector_list_iter conn_iter;
3722 struct intel_dp *intel_dp;
3723
3724 drm_connector_list_iter_begin(dev, &conn_iter);
3725 drm_for_each_connector_iter(connector, &conn_iter) {
3726 struct intel_encoder *encoder;
3727
3728 if (connector->connector_type !=
3729 DRM_MODE_CONNECTOR_DisplayPort)
3730 continue;
3731
3732 encoder = to_intel_encoder(connector->encoder);
3733 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3734 continue;
3735
3736 if (encoder && connector->status == connector_status_connected) {
3737 intel_dp = enc_to_intel_dp(&encoder->base);
3738 if (intel_dp->compliance.test_active)
3739 seq_puts(m, "1");
3740 else
3741 seq_puts(m, "0");
3742 } else
3743 seq_puts(m, "0");
3744 }
3745 drm_connector_list_iter_end(&conn_iter);
3746
3747 return 0;
3748 }
3749
3750 static int i915_displayport_test_active_open(struct inode *inode,
3751 struct file *file)
3752 {
3753 struct drm_i915_private *dev_priv = inode->i_private;
3754
3755 return single_open(file, i915_displayport_test_active_show,
3756 &dev_priv->drm);
3757 }
3758
3759 static const struct file_operations i915_displayport_test_active_fops = {
3760 .owner = THIS_MODULE,
3761 .open = i915_displayport_test_active_open,
3762 .read = seq_read,
3763 .llseek = seq_lseek,
3764 .release = single_release,
3765 .write = i915_displayport_test_active_write
3766 };
3767
3768 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3769 {
3770 struct drm_device *dev = m->private;
3771 struct drm_connector *connector;
3772 struct drm_connector_list_iter conn_iter;
3773 struct intel_dp *intel_dp;
3774
3775 drm_connector_list_iter_begin(dev, &conn_iter);
3776 drm_for_each_connector_iter(connector, &conn_iter) {
3777 struct intel_encoder *encoder;
3778
3779 if (connector->connector_type !=
3780 DRM_MODE_CONNECTOR_DisplayPort)
3781 continue;
3782
3783 encoder = to_intel_encoder(connector->encoder);
3784 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3785 continue;
3786
3787 if (encoder && connector->status == connector_status_connected) {
3788 intel_dp = enc_to_intel_dp(&encoder->base);
3789 if (intel_dp->compliance.test_type ==
3790 DP_TEST_LINK_EDID_READ)
3791 seq_printf(m, "%lx",
3792 intel_dp->compliance.test_data.edid);
3793 else if (intel_dp->compliance.test_type ==
3794 DP_TEST_LINK_VIDEO_PATTERN) {
3795 seq_printf(m, "hdisplay: %d\n",
3796 intel_dp->compliance.test_data.hdisplay);
3797 seq_printf(m, "vdisplay: %d\n",
3798 intel_dp->compliance.test_data.vdisplay);
3799 seq_printf(m, "bpc: %u\n",
3800 intel_dp->compliance.test_data.bpc);
3801 }
3802 } else
3803 seq_puts(m, "0");
3804 }
3805 drm_connector_list_iter_end(&conn_iter);
3806
3807 return 0;
3808 }
3809 static int i915_displayport_test_data_open(struct inode *inode,
3810 struct file *file)
3811 {
3812 struct drm_i915_private *dev_priv = inode->i_private;
3813
3814 return single_open(file, i915_displayport_test_data_show,
3815 &dev_priv->drm);
3816 }
3817
3818 static const struct file_operations i915_displayport_test_data_fops = {
3819 .owner = THIS_MODULE,
3820 .open = i915_displayport_test_data_open,
3821 .read = seq_read,
3822 .llseek = seq_lseek,
3823 .release = single_release
3824 };
3825
3826 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3827 {
3828 struct drm_device *dev = m->private;
3829 struct drm_connector *connector;
3830 struct drm_connector_list_iter conn_iter;
3831 struct intel_dp *intel_dp;
3832
3833 drm_connector_list_iter_begin(dev, &conn_iter);
3834 drm_for_each_connector_iter(connector, &conn_iter) {
3835 struct intel_encoder *encoder;
3836
3837 if (connector->connector_type !=
3838 DRM_MODE_CONNECTOR_DisplayPort)
3839 continue;
3840
3841 encoder = to_intel_encoder(connector->encoder);
3842 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3843 continue;
3844
3845 if (encoder && connector->status == connector_status_connected) {
3846 intel_dp = enc_to_intel_dp(&encoder->base);
3847 seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3848 } else
3849 seq_puts(m, "0");
3850 }
3851 drm_connector_list_iter_end(&conn_iter);
3852
3853 return 0;
3854 }
3855
3856 static int i915_displayport_test_type_open(struct inode *inode,
3857 struct file *file)
3858 {
3859 struct drm_i915_private *dev_priv = inode->i_private;
3860
3861 return single_open(file, i915_displayport_test_type_show,
3862 &dev_priv->drm);
3863 }
3864
3865 static const struct file_operations i915_displayport_test_type_fops = {
3866 .owner = THIS_MODULE,
3867 .open = i915_displayport_test_type_open,
3868 .read = seq_read,
3869 .llseek = seq_lseek,
3870 .release = single_release
3871 };
3872
3873 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3874 {
3875 struct drm_i915_private *dev_priv = m->private;
3876 struct drm_device *dev = &dev_priv->drm;
3877 int level;
3878 int num_levels;
3879
3880 if (IS_CHERRYVIEW(dev_priv))
3881 num_levels = 3;
3882 else if (IS_VALLEYVIEW(dev_priv))
3883 num_levels = 1;
3884 else if (IS_G4X(dev_priv))
3885 num_levels = 3;
3886 else
3887 num_levels = ilk_wm_max_level(dev_priv) + 1;
3888
3889 drm_modeset_lock_all(dev);
3890
3891 for (level = 0; level < num_levels; level++) {
3892 unsigned int latency = wm[level];
3893
3894 /*
3895 * - WM1+ latency values in 0.5us units
3896 * - latencies are in us on gen9/vlv/chv
3897 */
3898 if (INTEL_GEN(dev_priv) >= 9 ||
3899 IS_VALLEYVIEW(dev_priv) ||
3900 IS_CHERRYVIEW(dev_priv) ||
3901 IS_G4X(dev_priv))
3902 latency *= 10;
3903 else if (level > 0)
3904 latency *= 5;
3905
3906 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3907 level, wm[level], latency / 10, latency % 10);
3908 }
3909
3910 drm_modeset_unlock_all(dev);
3911 }
3912
3913 static int pri_wm_latency_show(struct seq_file *m, void *data)
3914 {
3915 struct drm_i915_private *dev_priv = m->private;
3916 const uint16_t *latencies;
3917
3918 if (INTEL_GEN(dev_priv) >= 9)
3919 latencies = dev_priv->wm.skl_latency;
3920 else
3921 latencies = dev_priv->wm.pri_latency;
3922
3923 wm_latency_show(m, latencies);
3924
3925 return 0;
3926 }
3927
3928 static int spr_wm_latency_show(struct seq_file *m, void *data)
3929 {
3930 struct drm_i915_private *dev_priv = m->private;
3931 const uint16_t *latencies;
3932
3933 if (INTEL_GEN(dev_priv) >= 9)
3934 latencies = dev_priv->wm.skl_latency;
3935 else
3936 latencies = dev_priv->wm.spr_latency;
3937
3938 wm_latency_show(m, latencies);
3939
3940 return 0;
3941 }
3942
3943 static int cur_wm_latency_show(struct seq_file *m, void *data)
3944 {
3945 struct drm_i915_private *dev_priv = m->private;
3946 const uint16_t *latencies;
3947
3948 if (INTEL_GEN(dev_priv) >= 9)
3949 latencies = dev_priv->wm.skl_latency;
3950 else
3951 latencies = dev_priv->wm.cur_latency;
3952
3953 wm_latency_show(m, latencies);
3954
3955 return 0;
3956 }
3957
3958 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3959 {
3960 struct drm_i915_private *dev_priv = inode->i_private;
3961
3962 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3963 return -ENODEV;
3964
3965 return single_open(file, pri_wm_latency_show, dev_priv);
3966 }
3967
3968 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3969 {
3970 struct drm_i915_private *dev_priv = inode->i_private;
3971
3972 if (HAS_GMCH_DISPLAY(dev_priv))
3973 return -ENODEV;
3974
3975 return single_open(file, spr_wm_latency_show, dev_priv);
3976 }
3977
3978 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3979 {
3980 struct drm_i915_private *dev_priv = inode->i_private;
3981
3982 if (HAS_GMCH_DISPLAY(dev_priv))
3983 return -ENODEV;
3984
3985 return single_open(file, cur_wm_latency_show, dev_priv);
3986 }
3987
3988 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3989 size_t len, loff_t *offp, uint16_t wm[8])
3990 {
3991 struct seq_file *m = file->private_data;
3992 struct drm_i915_private *dev_priv = m->private;
3993 struct drm_device *dev = &dev_priv->drm;
3994 uint16_t new[8] = { 0 };
3995 int num_levels;
3996 int level;
3997 int ret;
3998 char tmp[32];
3999
4000 if (IS_CHERRYVIEW(dev_priv))
4001 num_levels = 3;
4002 else if (IS_VALLEYVIEW(dev_priv))
4003 num_levels = 1;
4004 else if (IS_G4X(dev_priv))
4005 num_levels = 3;
4006 else
4007 num_levels = ilk_wm_max_level(dev_priv) + 1;
4008
4009 if (len >= sizeof(tmp))
4010 return -EINVAL;
4011
4012 if (copy_from_user(tmp, ubuf, len))
4013 return -EFAULT;
4014
4015 tmp[len] = '\0';
4016
4017 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4018 &new[0], &new[1], &new[2], &new[3],
4019 &new[4], &new[5], &new[6], &new[7]);
4020 if (ret != num_levels)
4021 return -EINVAL;
4022
4023 drm_modeset_lock_all(dev);
4024
4025 for (level = 0; level < num_levels; level++)
4026 wm[level] = new[level];
4027
4028 drm_modeset_unlock_all(dev);
4029
4030 return len;
4031 }
4032
4033
4034 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4035 size_t len, loff_t *offp)
4036 {
4037 struct seq_file *m = file->private_data;
4038 struct drm_i915_private *dev_priv = m->private;
4039 uint16_t *latencies;
4040
4041 if (INTEL_GEN(dev_priv) >= 9)
4042 latencies = dev_priv->wm.skl_latency;
4043 else
4044 latencies = dev_priv->wm.pri_latency;
4045
4046 return wm_latency_write(file, ubuf, len, offp, latencies);
4047 }
4048
4049 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4050 size_t len, loff_t *offp)
4051 {
4052 struct seq_file *m = file->private_data;
4053 struct drm_i915_private *dev_priv = m->private;
4054 uint16_t *latencies;
4055
4056 if (INTEL_GEN(dev_priv) >= 9)
4057 latencies = dev_priv->wm.skl_latency;
4058 else
4059 latencies = dev_priv->wm.spr_latency;
4060
4061 return wm_latency_write(file, ubuf, len, offp, latencies);
4062 }
4063
4064 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4065 size_t len, loff_t *offp)
4066 {
4067 struct seq_file *m = file->private_data;
4068 struct drm_i915_private *dev_priv = m->private;
4069 uint16_t *latencies;
4070
4071 if (INTEL_GEN(dev_priv) >= 9)
4072 latencies = dev_priv->wm.skl_latency;
4073 else
4074 latencies = dev_priv->wm.cur_latency;
4075
4076 return wm_latency_write(file, ubuf, len, offp, latencies);
4077 }
4078
4079 static const struct file_operations i915_pri_wm_latency_fops = {
4080 .owner = THIS_MODULE,
4081 .open = pri_wm_latency_open,
4082 .read = seq_read,
4083 .llseek = seq_lseek,
4084 .release = single_release,
4085 .write = pri_wm_latency_write
4086 };
4087
4088 static const struct file_operations i915_spr_wm_latency_fops = {
4089 .owner = THIS_MODULE,
4090 .open = spr_wm_latency_open,
4091 .read = seq_read,
4092 .llseek = seq_lseek,
4093 .release = single_release,
4094 .write = spr_wm_latency_write
4095 };
4096
4097 static const struct file_operations i915_cur_wm_latency_fops = {
4098 .owner = THIS_MODULE,
4099 .open = cur_wm_latency_open,
4100 .read = seq_read,
4101 .llseek = seq_lseek,
4102 .release = single_release,
4103 .write = cur_wm_latency_write
4104 };
4105
4106 static int
4107 i915_wedged_get(void *data, u64 *val)
4108 {
4109 struct drm_i915_private *dev_priv = data;
4110
4111 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4112
4113 return 0;
4114 }
4115
4116 static int
4117 i915_wedged_set(void *data, u64 val)
4118 {
4119 struct drm_i915_private *i915 = data;
4120 struct intel_engine_cs *engine;
4121 unsigned int tmp;
4122
4123 /*
4124 * There is no safeguard against this debugfs entry colliding
4125 * with the hangcheck calling same i915_handle_error() in
4126 * parallel, causing an explosion. For now we assume that the
4127 * test harness is responsible enough not to inject gpu hangs
4128 * while it is writing to 'i915_wedged'
4129 */
4130
4131 if (i915_reset_backoff(&i915->gpu_error))
4132 return -EAGAIN;
4133
4134 for_each_engine_masked(engine, i915, val, tmp) {
4135 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4136 engine->hangcheck.stalled = true;
4137 }
4138
4139 i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
4140
4141 wait_on_bit(&i915->gpu_error.flags,
4142 I915_RESET_HANDOFF,
4143 TASK_UNINTERRUPTIBLE);
4144
4145 return 0;
4146 }
4147
4148 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4149 i915_wedged_get, i915_wedged_set,
4150 "%llu\n");
4151
4152 static int
4153 fault_irq_set(struct drm_i915_private *i915,
4154 unsigned long *irq,
4155 unsigned long val)
4156 {
4157 int err;
4158
4159 err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4160 if (err)
4161 return err;
4162
4163 err = i915_gem_wait_for_idle(i915,
4164 I915_WAIT_LOCKED |
4165 I915_WAIT_INTERRUPTIBLE);
4166 if (err)
4167 goto err_unlock;
4168
4169 *irq = val;
4170 mutex_unlock(&i915->drm.struct_mutex);
4171
4172 /* Flush idle worker to disarm irq */
4173 drain_delayed_work(&i915->gt.idle_work);
4174
4175 return 0;
4176
4177 err_unlock:
4178 mutex_unlock(&i915->drm.struct_mutex);
4179 return err;
4180 }
4181
4182 static int
4183 i915_ring_missed_irq_get(void *data, u64 *val)
4184 {
4185 struct drm_i915_private *dev_priv = data;
4186
4187 *val = dev_priv->gpu_error.missed_irq_rings;
4188 return 0;
4189 }
4190
4191 static int
4192 i915_ring_missed_irq_set(void *data, u64 val)
4193 {
4194 struct drm_i915_private *i915 = data;
4195
4196 return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4197 }
4198
4199 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4200 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4201 "0x%08llx\n");
4202
4203 static int
4204 i915_ring_test_irq_get(void *data, u64 *val)
4205 {
4206 struct drm_i915_private *dev_priv = data;
4207
4208 *val = dev_priv->gpu_error.test_irq_rings;
4209
4210 return 0;
4211 }
4212
4213 static int
4214 i915_ring_test_irq_set(void *data, u64 val)
4215 {
4216 struct drm_i915_private *i915 = data;
4217
4218 val &= INTEL_INFO(i915)->ring_mask;
4219 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4220
4221 return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4222 }
4223
4224 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4225 i915_ring_test_irq_get, i915_ring_test_irq_set,
4226 "0x%08llx\n");
4227
4228 #define DROP_UNBOUND 0x1
4229 #define DROP_BOUND 0x2
4230 #define DROP_RETIRE 0x4
4231 #define DROP_ACTIVE 0x8
4232 #define DROP_FREED 0x10
4233 #define DROP_SHRINK_ALL 0x20
4234 #define DROP_ALL (DROP_UNBOUND | \
4235 DROP_BOUND | \
4236 DROP_RETIRE | \
4237 DROP_ACTIVE | \
4238 DROP_FREED | \
4239 DROP_SHRINK_ALL)
4240 static int
4241 i915_drop_caches_get(void *data, u64 *val)
4242 {
4243 *val = DROP_ALL;
4244
4245 return 0;
4246 }
4247
4248 static int
4249 i915_drop_caches_set(void *data, u64 val)
4250 {
4251 struct drm_i915_private *dev_priv = data;
4252 struct drm_device *dev = &dev_priv->drm;
4253 int ret = 0;
4254
4255 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4256
4257 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4258 * on ioctls on -EAGAIN. */
4259 if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4260 ret = mutex_lock_interruptible(&dev->struct_mutex);
4261 if (ret)
4262 return ret;
4263
4264 if (val & DROP_ACTIVE)
4265 ret = i915_gem_wait_for_idle(dev_priv,
4266 I915_WAIT_INTERRUPTIBLE |
4267 I915_WAIT_LOCKED);
4268
4269 if (val & DROP_RETIRE)
4270 i915_gem_retire_requests(dev_priv);
4271
4272 mutex_unlock(&dev->struct_mutex);
4273 }
4274
4275 fs_reclaim_acquire(GFP_KERNEL);
4276 if (val & DROP_BOUND)
4277 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4278
4279 if (val & DROP_UNBOUND)
4280 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4281
4282 if (val & DROP_SHRINK_ALL)
4283 i915_gem_shrink_all(dev_priv);
4284 fs_reclaim_release(GFP_KERNEL);
4285
4286 if (val & DROP_FREED) {
4287 synchronize_rcu();
4288 i915_gem_drain_freed_objects(dev_priv);
4289 }
4290
4291 return ret;
4292 }
4293
4294 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4295 i915_drop_caches_get, i915_drop_caches_set,
4296 "0x%08llx\n");
4297
4298 static int
4299 i915_max_freq_get(void *data, u64 *val)
4300 {
4301 struct drm_i915_private *dev_priv = data;
4302
4303 if (INTEL_GEN(dev_priv) < 6)
4304 return -ENODEV;
4305
4306 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
4307 return 0;
4308 }
4309
4310 static int
4311 i915_max_freq_set(void *data, u64 val)
4312 {
4313 struct drm_i915_private *dev_priv = data;
4314 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4315 u32 hw_max, hw_min;
4316 int ret;
4317
4318 if (INTEL_GEN(dev_priv) < 6)
4319 return -ENODEV;
4320
4321 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4322
4323 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4324 if (ret)
4325 return ret;
4326
4327 /*
4328 * Turbo will still be enabled, but won't go above the set value.
4329 */
4330 val = intel_freq_opcode(dev_priv, val);
4331
4332 hw_max = rps->max_freq;
4333 hw_min = rps->min_freq;
4334
4335 if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
4336 mutex_unlock(&dev_priv->pcu_lock);
4337 return -EINVAL;
4338 }
4339
4340 rps->max_freq_softlimit = val;
4341
4342 if (intel_set_rps(dev_priv, val))
4343 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4344
4345 mutex_unlock(&dev_priv->pcu_lock);
4346
4347 return 0;
4348 }
4349
4350 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4351 i915_max_freq_get, i915_max_freq_set,
4352 "%llu\n");
4353
4354 static int
4355 i915_min_freq_get(void *data, u64 *val)
4356 {
4357 struct drm_i915_private *dev_priv = data;
4358
4359 if (INTEL_GEN(dev_priv) < 6)
4360 return -ENODEV;
4361
4362 *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
4363 return 0;
4364 }
4365
4366 static int
4367 i915_min_freq_set(void *data, u64 val)
4368 {
4369 struct drm_i915_private *dev_priv = data;
4370 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4371 u32 hw_max, hw_min;
4372 int ret;
4373
4374 if (INTEL_GEN(dev_priv) < 6)
4375 return -ENODEV;
4376
4377 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4378
4379 ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4380 if (ret)
4381 return ret;
4382
4383 /*
4384 * Turbo will still be enabled, but won't go below the set value.
4385 */
4386 val = intel_freq_opcode(dev_priv, val);
4387
4388 hw_max = rps->max_freq;
4389 hw_min = rps->min_freq;
4390
4391 if (val < hw_min ||
4392 val > hw_max || val > rps->max_freq_softlimit) {
4393 mutex_unlock(&dev_priv->pcu_lock);
4394 return -EINVAL;
4395 }
4396
4397 rps->min_freq_softlimit = val;
4398
4399 if (intel_set_rps(dev_priv, val))
4400 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4401
4402 mutex_unlock(&dev_priv->pcu_lock);
4403
4404 return 0;
4405 }
4406
4407 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4408 i915_min_freq_get, i915_min_freq_set,
4409 "%llu\n");
4410
4411 static int
4412 i915_cache_sharing_get(void *data, u64 *val)
4413 {
4414 struct drm_i915_private *dev_priv = data;
4415 u32 snpcr;
4416
4417 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4418 return -ENODEV;
4419
4420 intel_runtime_pm_get(dev_priv);
4421
4422 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4423
4424 intel_runtime_pm_put(dev_priv);
4425
4426 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4427
4428 return 0;
4429 }
4430
4431 static int
4432 i915_cache_sharing_set(void *data, u64 val)
4433 {
4434 struct drm_i915_private *dev_priv = data;
4435 u32 snpcr;
4436
4437 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4438 return -ENODEV;
4439
4440 if (val > 3)
4441 return -EINVAL;
4442
4443 intel_runtime_pm_get(dev_priv);
4444 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4445
4446 /* Update the cache sharing policy here as well */
4447 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4448 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4449 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4450 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4451
4452 intel_runtime_pm_put(dev_priv);
4453 return 0;
4454 }
4455
4456 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4457 i915_cache_sharing_get, i915_cache_sharing_set,
4458 "%llu\n");
4459
4460 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4461 struct sseu_dev_info *sseu)
4462 {
4463 int ss_max = 2;
4464 int ss;
4465 u32 sig1[ss_max], sig2[ss_max];
4466
4467 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4468 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4469 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4470 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4471
4472 for (ss = 0; ss < ss_max; ss++) {
4473 unsigned int eu_cnt;
4474
4475 if (sig1[ss] & CHV_SS_PG_ENABLE)
4476 /* skip disabled subslice */
4477 continue;
4478
4479 sseu->slice_mask = BIT(0);
4480 sseu->subslice_mask |= BIT(ss);
4481 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4482 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4483 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4484 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4485 sseu->eu_total += eu_cnt;
4486 sseu->eu_per_subslice = max_t(unsigned int,
4487 sseu->eu_per_subslice, eu_cnt);
4488 }
4489 }
4490
4491 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4492 struct sseu_dev_info *sseu)
4493 {
4494 int s_max = 3, ss_max = 4;
4495 int s, ss;
4496 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4497
4498 /* BXT has a single slice and at most 3 subslices. */
4499 if (IS_GEN9_LP(dev_priv)) {
4500 s_max = 1;
4501 ss_max = 3;
4502 }
4503
4504 for (s = 0; s < s_max; s++) {
4505 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4506 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4507 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4508 }
4509
4510 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4511 GEN9_PGCTL_SSA_EU19_ACK |
4512 GEN9_PGCTL_SSA_EU210_ACK |
4513 GEN9_PGCTL_SSA_EU311_ACK;
4514 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4515 GEN9_PGCTL_SSB_EU19_ACK |
4516 GEN9_PGCTL_SSB_EU210_ACK |
4517 GEN9_PGCTL_SSB_EU311_ACK;
4518
4519 for (s = 0; s < s_max; s++) {
4520 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4521 /* skip disabled slice */
4522 continue;
4523
4524 sseu->slice_mask |= BIT(s);
4525
4526 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
4527 sseu->subslice_mask =
4528 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4529
4530 for (ss = 0; ss < ss_max; ss++) {
4531 unsigned int eu_cnt;
4532
4533 if (IS_GEN9_LP(dev_priv)) {
4534 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4535 /* skip disabled subslice */
4536 continue;
4537
4538 sseu->subslice_mask |= BIT(ss);
4539 }
4540
4541 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4542 eu_mask[ss%2]);
4543 sseu->eu_total += eu_cnt;
4544 sseu->eu_per_subslice = max_t(unsigned int,
4545 sseu->eu_per_subslice,
4546 eu_cnt);
4547 }
4548 }
4549 }
4550
4551 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4552 struct sseu_dev_info *sseu)
4553 {
4554 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4555 int s;
4556
4557 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4558
4559 if (sseu->slice_mask) {
4560 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4561 sseu->eu_per_subslice =
4562 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4563 sseu->eu_total = sseu->eu_per_subslice *
4564 sseu_subslice_total(sseu);
4565
4566 /* subtract fused off EU(s) from enabled slice(s) */
4567 for (s = 0; s < fls(sseu->slice_mask); s++) {
4568 u8 subslice_7eu =
4569 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4570
4571 sseu->eu_total -= hweight8(subslice_7eu);
4572 }
4573 }
4574 }
4575
4576 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4577 const struct sseu_dev_info *sseu)
4578 {
4579 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4580 const char *type = is_available_info ? "Available" : "Enabled";
4581
4582 seq_printf(m, " %s Slice Mask: %04x\n", type,
4583 sseu->slice_mask);
4584 seq_printf(m, " %s Slice Total: %u\n", type,
4585 hweight8(sseu->slice_mask));
4586 seq_printf(m, " %s Subslice Total: %u\n", type,
4587 sseu_subslice_total(sseu));
4588 seq_printf(m, " %s Subslice Mask: %04x\n", type,
4589 sseu->subslice_mask);
4590 seq_printf(m, " %s Subslice Per Slice: %u\n", type,
4591 hweight8(sseu->subslice_mask));
4592 seq_printf(m, " %s EU Total: %u\n", type,
4593 sseu->eu_total);
4594 seq_printf(m, " %s EU Per Subslice: %u\n", type,
4595 sseu->eu_per_subslice);
4596
4597 if (!is_available_info)
4598 return;
4599
4600 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4601 if (HAS_POOLED_EU(dev_priv))
4602 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
4603
4604 seq_printf(m, " Has Slice Power Gating: %s\n",
4605 yesno(sseu->has_slice_pg));
4606 seq_printf(m, " Has Subslice Power Gating: %s\n",
4607 yesno(sseu->has_subslice_pg));
4608 seq_printf(m, " Has EU Power Gating: %s\n",
4609 yesno(sseu->has_eu_pg));
4610 }
4611
4612 static int i915_sseu_status(struct seq_file *m, void *unused)
4613 {
4614 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4615 struct sseu_dev_info sseu;
4616
4617 if (INTEL_GEN(dev_priv) < 8)
4618 return -ENODEV;
4619
4620 seq_puts(m, "SSEU Device Info\n");
4621 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4622
4623 seq_puts(m, "SSEU Device Status\n");
4624 memset(&sseu, 0, sizeof(sseu));
4625
4626 intel_runtime_pm_get(dev_priv);
4627
4628 if (IS_CHERRYVIEW(dev_priv)) {
4629 cherryview_sseu_device_status(dev_priv, &sseu);
4630 } else if (IS_BROADWELL(dev_priv)) {
4631 broadwell_sseu_device_status(dev_priv, &sseu);
4632 } else if (INTEL_GEN(dev_priv) >= 9) {
4633 gen9_sseu_device_status(dev_priv, &sseu);
4634 }
4635
4636 intel_runtime_pm_put(dev_priv);
4637
4638 i915_print_sseu_info(m, false, &sseu);
4639
4640 return 0;
4641 }
4642
4643 static int i915_forcewake_open(struct inode *inode, struct file *file)
4644 {
4645 struct drm_i915_private *i915 = inode->i_private;
4646
4647 if (INTEL_GEN(i915) < 6)
4648 return 0;
4649
4650 intel_runtime_pm_get(i915);
4651 intel_uncore_forcewake_user_get(i915);
4652
4653 return 0;
4654 }
4655
4656 static int i915_forcewake_release(struct inode *inode, struct file *file)
4657 {
4658 struct drm_i915_private *i915 = inode->i_private;
4659
4660 if (INTEL_GEN(i915) < 6)
4661 return 0;
4662
4663 intel_uncore_forcewake_user_put(i915);
4664 intel_runtime_pm_put(i915);
4665
4666 return 0;
4667 }
4668
4669 static const struct file_operations i915_forcewake_fops = {
4670 .owner = THIS_MODULE,
4671 .open = i915_forcewake_open,
4672 .release = i915_forcewake_release,
4673 };
4674
4675 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4676 {
4677 struct drm_i915_private *dev_priv = m->private;
4678 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4679
4680 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4681 seq_printf(m, "Detected: %s\n",
4682 yesno(delayed_work_pending(&hotplug->reenable_work)));
4683
4684 return 0;
4685 }
4686
4687 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4688 const char __user *ubuf, size_t len,
4689 loff_t *offp)
4690 {
4691 struct seq_file *m = file->private_data;
4692 struct drm_i915_private *dev_priv = m->private;
4693 struct i915_hotplug *hotplug = &dev_priv->hotplug;
4694 unsigned int new_threshold;
4695 int i;
4696 char *newline;
4697 char tmp[16];
4698
4699 if (len >= sizeof(tmp))
4700 return -EINVAL;
4701
4702 if (copy_from_user(tmp, ubuf, len))
4703 return -EFAULT;
4704
4705 tmp[len] = '\0';
4706
4707 /* Strip newline, if any */
4708 newline = strchr(tmp, '\n');
4709 if (newline)
4710 *newline = '\0';
4711
4712 if (strcmp(tmp, "reset") == 0)
4713 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4714 else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4715 return -EINVAL;
4716
4717 if (new_threshold > 0)
4718 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4719 new_threshold);
4720 else
4721 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4722
4723 spin_lock_irq(&dev_priv->irq_lock);
4724 hotplug->hpd_storm_threshold = new_threshold;
4725 /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4726 for_each_hpd_pin(i)
4727 hotplug->stats[i].count = 0;
4728 spin_unlock_irq(&dev_priv->irq_lock);
4729
4730 /* Re-enable hpd immediately if we were in an irq storm */
4731 flush_delayed_work(&dev_priv->hotplug.reenable_work);
4732
4733 return len;
4734 }
4735
4736 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4737 {
4738 return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4739 }
4740
4741 static const struct file_operations i915_hpd_storm_ctl_fops = {
4742 .owner = THIS_MODULE,
4743 .open = i915_hpd_storm_ctl_open,
4744 .read = seq_read,
4745 .llseek = seq_lseek,
4746 .release = single_release,
4747 .write = i915_hpd_storm_ctl_write
4748 };
4749
4750 static const struct drm_info_list i915_debugfs_list[] = {
4751 {"i915_capabilities", i915_capabilities, 0},
4752 {"i915_gem_objects", i915_gem_object_info, 0},
4753 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4754 {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
4755 {"i915_gem_stolen", i915_gem_stolen_list_info },
4756 {"i915_gem_request", i915_gem_request_info, 0},
4757 {"i915_gem_seqno", i915_gem_seqno_info, 0},
4758 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4759 {"i915_gem_interrupt", i915_interrupt_info, 0},
4760 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4761 {"i915_guc_info", i915_guc_info, 0},
4762 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4763 {"i915_guc_log_dump", i915_guc_log_dump, 0},
4764 {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4765 {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4766 {"i915_huc_load_status", i915_huc_load_status_info, 0},
4767 {"i915_frequency_info", i915_frequency_info, 0},
4768 {"i915_hangcheck_info", i915_hangcheck_info, 0},
4769 {"i915_reset_info", i915_reset_info, 0},
4770 {"i915_drpc_info", i915_drpc_info, 0},
4771 {"i915_emon_status", i915_emon_status, 0},
4772 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4773 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4774 {"i915_fbc_status", i915_fbc_status, 0},
4775 {"i915_ips_status", i915_ips_status, 0},
4776 {"i915_sr_status", i915_sr_status, 0},
4777 {"i915_opregion", i915_opregion, 0},
4778 {"i915_vbt", i915_vbt, 0},
4779 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4780 {"i915_context_status", i915_context_status, 0},
4781 {"i915_dump_lrc", i915_dump_lrc, 0},
4782 {"i915_forcewake_domains", i915_forcewake_domains, 0},
4783 {"i915_swizzle_info", i915_swizzle_info, 0},
4784 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4785 {"i915_llc", i915_llc, 0},
4786 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4787 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4788 {"i915_energy_uJ", i915_energy_uJ, 0},
4789 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4790 {"i915_power_domain_info", i915_power_domain_info, 0},
4791 {"i915_dmc_info", i915_dmc_info, 0},
4792 {"i915_display_info", i915_display_info, 0},
4793 {"i915_engine_info", i915_engine_info, 0},
4794 {"i915_semaphore_status", i915_semaphore_status, 0},
4795 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4796 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4797 {"i915_wa_registers", i915_wa_registers, 0},
4798 {"i915_ddb_info", i915_ddb_info, 0},
4799 {"i915_sseu_status", i915_sseu_status, 0},
4800 {"i915_drrs_status", i915_drrs_status, 0},
4801 {"i915_rps_boost_info", i915_rps_boost_info, 0},
4802 };
4803 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4804
4805 static const struct i915_debugfs_files {
4806 const char *name;
4807 const struct file_operations *fops;
4808 } i915_debugfs_files[] = {
4809 {"i915_wedged", &i915_wedged_fops},
4810 {"i915_max_freq", &i915_max_freq_fops},
4811 {"i915_min_freq", &i915_min_freq_fops},
4812 {"i915_cache_sharing", &i915_cache_sharing_fops},
4813 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4814 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4815 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4816 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4817 {"i915_error_state", &i915_error_state_fops},
4818 {"i915_gpu_info", &i915_gpu_info_fops},
4819 #endif
4820 {"i915_next_seqno", &i915_next_seqno_fops},
4821 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4822 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4823 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4824 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4825 {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4826 {"i915_dp_test_data", &i915_displayport_test_data_fops},
4827 {"i915_dp_test_type", &i915_displayport_test_type_fops},
4828 {"i915_dp_test_active", &i915_displayport_test_active_fops},
4829 {"i915_guc_log_control", &i915_guc_log_control_fops},
4830 {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4831 {"i915_ipc_status", &i915_ipc_status_fops}
4832 };
4833
4834 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4835 {
4836 struct drm_minor *minor = dev_priv->drm.primary;
4837 struct dentry *ent;
4838 int ret, i;
4839
4840 ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4841 minor->debugfs_root, to_i915(minor->dev),
4842 &i915_forcewake_fops);
4843 if (!ent)
4844 return -ENOMEM;
4845
4846 ret = intel_pipe_crc_create(minor);
4847 if (ret)
4848 return ret;
4849
4850 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4851 ent = debugfs_create_file(i915_debugfs_files[i].name,
4852 S_IRUGO | S_IWUSR,
4853 minor->debugfs_root,
4854 to_i915(minor->dev),
4855 i915_debugfs_files[i].fops);
4856 if (!ent)
4857 return -ENOMEM;
4858 }
4859
4860 return drm_debugfs_create_files(i915_debugfs_list,
4861 I915_DEBUGFS_ENTRIES,
4862 minor->debugfs_root, minor);
4863 }
4864
4865 struct dpcd_block {
4866 /* DPCD dump start address. */
4867 unsigned int offset;
4868 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4869 unsigned int end;
4870 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4871 size_t size;
4872 /* Only valid for eDP. */
4873 bool edp;
4874 };
4875
4876 static const struct dpcd_block i915_dpcd_debug[] = {
4877 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4878 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4879 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4880 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4881 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4882 { .offset = DP_SET_POWER },
4883 { .offset = DP_EDP_DPCD_REV },
4884 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4885 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4886 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4887 };
4888
4889 static int i915_dpcd_show(struct seq_file *m, void *data)
4890 {
4891 struct drm_connector *connector = m->private;
4892 struct intel_dp *intel_dp =
4893 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4894 uint8_t buf[16];
4895 ssize_t err;
4896 int i;
4897
4898 if (connector->status != connector_status_connected)
4899 return -ENODEV;
4900
4901 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4902 const struct dpcd_block *b = &i915_dpcd_debug[i];
4903 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4904
4905 if (b->edp &&
4906 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4907 continue;
4908
4909 /* low tech for now */
4910 if (WARN_ON(size > sizeof(buf)))
4911 continue;
4912
4913 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4914 if (err <= 0) {
4915 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4916 size, b->offset, err);
4917 continue;
4918 }
4919
4920 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4921 }
4922
4923 return 0;
4924 }
4925
4926 static int i915_dpcd_open(struct inode *inode, struct file *file)
4927 {
4928 return single_open(file, i915_dpcd_show, inode->i_private);
4929 }
4930
4931 static const struct file_operations i915_dpcd_fops = {
4932 .owner = THIS_MODULE,
4933 .open = i915_dpcd_open,
4934 .read = seq_read,
4935 .llseek = seq_lseek,
4936 .release = single_release,
4937 };
4938
4939 static int i915_panel_show(struct seq_file *m, void *data)
4940 {
4941 struct drm_connector *connector = m->private;
4942 struct intel_dp *intel_dp =
4943 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4944
4945 if (connector->status != connector_status_connected)
4946 return -ENODEV;
4947
4948 seq_printf(m, "Panel power up delay: %d\n",
4949 intel_dp->panel_power_up_delay);
4950 seq_printf(m, "Panel power down delay: %d\n",
4951 intel_dp->panel_power_down_delay);
4952 seq_printf(m, "Backlight on delay: %d\n",
4953 intel_dp->backlight_on_delay);
4954 seq_printf(m, "Backlight off delay: %d\n",
4955 intel_dp->backlight_off_delay);
4956
4957 return 0;
4958 }
4959
4960 static int i915_panel_open(struct inode *inode, struct file *file)
4961 {
4962 return single_open(file, i915_panel_show, inode->i_private);
4963 }
4964
4965 static const struct file_operations i915_panel_fops = {
4966 .owner = THIS_MODULE,
4967 .open = i915_panel_open,
4968 .read = seq_read,
4969 .llseek = seq_lseek,
4970 .release = single_release,
4971 };
4972
4973 /**
4974 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4975 * @connector: pointer to a registered drm_connector
4976 *
4977 * Cleanup will be done by drm_connector_unregister() through a call to
4978 * drm_debugfs_connector_remove().
4979 *
4980 * Returns 0 on success, negative error codes on error.
4981 */
4982 int i915_debugfs_connector_add(struct drm_connector *connector)
4983 {
4984 struct dentry *root = connector->debugfs_entry;
4985
4986 /* The connector must have been registered beforehands. */
4987 if (!root)
4988 return -ENODEV;
4989
4990 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4991 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4992 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4993 connector, &i915_dpcd_fops);
4994
4995 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4996 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4997 connector, &i915_panel_fops);
4998
4999 return 0;
5000 }
ubuntu-bionic-kernel mirror