2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
43 static inline struct drm_i915_private
*node_to_i915(struct drm_info_node
*node
)
45 return to_i915(node
->minor
->dev
);
48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
49 * allocated we need to hook into the minor for release. */
51 drm_add_fake_info_node(struct drm_minor
*minor
,
55 struct drm_info_node
*node
;
57 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
65 node
->info_ent
= (void *)key
;
67 mutex_lock(&minor
->debugfs_lock
);
68 list_add(&node
->list
, &minor
->debugfs_list
);
69 mutex_unlock(&minor
->debugfs_lock
);
74 static int i915_capabilities(struct seq_file
*m
, void *data
)
76 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
77 const struct intel_device_info
*info
= INTEL_INFO(dev_priv
);
79 seq_printf(m
, "gen: %d\n", INTEL_GEN(dev_priv
));
80 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev_priv
));
81 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
82 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
);
88 static char get_active_flag(struct drm_i915_gem_object
*obj
)
90 return i915_gem_object_is_active(obj
) ? '*' : ' ';
93 static char get_pin_flag(struct drm_i915_gem_object
*obj
)
95 return obj
->pin_display
? 'p' : ' ';
98 static char get_tiling_flag(struct drm_i915_gem_object
*obj
)
100 switch (i915_gem_object_get_tiling(obj
)) {
102 case I915_TILING_NONE
: return ' ';
103 case I915_TILING_X
: return 'X';
104 case I915_TILING_Y
: return 'Y';
108 static char get_global_flag(struct drm_i915_gem_object
*obj
)
110 return obj
->fault_mappable
? 'g' : ' ';
113 static char get_pin_mapped_flag(struct drm_i915_gem_object
*obj
)
115 return obj
->mapping
? 'M' : ' ';
118 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
121 struct i915_vma
*vma
;
123 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
124 if (i915_vma_is_ggtt(vma
) && drm_mm_node_allocated(&vma
->node
))
125 size
+= vma
->node
.size
;
132 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
134 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
135 struct intel_engine_cs
*engine
;
136 struct i915_vma
*vma
;
137 unsigned int frontbuffer_bits
;
139 enum intel_engine_id id
;
141 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
143 seq_printf(m
, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
145 get_active_flag(obj
),
147 get_tiling_flag(obj
),
148 get_global_flag(obj
),
149 get_pin_mapped_flag(obj
),
150 obj
->base
.size
/ 1024,
151 obj
->base
.read_domains
,
152 obj
->base
.write_domain
);
153 for_each_engine(engine
, dev_priv
, id
)
155 i915_gem_active_get_seqno(&obj
->last_read
[id
],
156 &obj
->base
.dev
->struct_mutex
));
157 seq_printf(m
, "] %x %s%s%s",
158 i915_gem_active_get_seqno(&obj
->last_write
,
159 &obj
->base
.dev
->struct_mutex
),
160 i915_cache_level_str(dev_priv
, obj
->cache_level
),
161 obj
->dirty
? " dirty" : "",
162 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
164 seq_printf(m
, " (name: %d)", obj
->base
.name
);
165 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
166 if (i915_vma_is_pinned(vma
))
169 seq_printf(m
, " (pinned x %d)", pin_count
);
170 if (obj
->pin_display
)
171 seq_printf(m
, " (display)");
172 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
173 if (!drm_mm_node_allocated(&vma
->node
))
176 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
177 i915_vma_is_ggtt(vma
) ? "g" : "pp",
178 vma
->node
.start
, vma
->node
.size
);
179 if (i915_vma_is_ggtt(vma
))
180 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
182 seq_printf(m
, " , fence: %d%s",
184 i915_gem_active_isset(&vma
->last_fence
) ? "*" : "");
188 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
190 engine
= i915_gem_active_get_engine(&obj
->last_write
,
191 &dev_priv
->drm
.struct_mutex
);
193 seq_printf(m
, " (%s)", engine
->name
);
195 frontbuffer_bits
= atomic_read(&obj
->frontbuffer_bits
);
196 if (frontbuffer_bits
)
197 seq_printf(m
, " (frontbuffer: 0x%03x)", frontbuffer_bits
);
200 static int obj_rank_by_stolen(void *priv
,
201 struct list_head
*A
, struct list_head
*B
)
203 struct drm_i915_gem_object
*a
=
204 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
205 struct drm_i915_gem_object
*b
=
206 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
208 if (a
->stolen
->start
< b
->stolen
->start
)
210 if (a
->stolen
->start
> b
->stolen
->start
)
215 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
217 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
218 struct drm_device
*dev
= &dev_priv
->drm
;
219 struct drm_i915_gem_object
*obj
;
220 u64 total_obj_size
, total_gtt_size
;
224 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
228 total_obj_size
= total_gtt_size
= count
= 0;
229 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
230 if (obj
->stolen
== NULL
)
233 list_add(&obj
->obj_exec_link
, &stolen
);
235 total_obj_size
+= obj
->base
.size
;
236 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
239 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
240 if (obj
->stolen
== NULL
)
243 list_add(&obj
->obj_exec_link
, &stolen
);
245 total_obj_size
+= obj
->base
.size
;
248 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
249 seq_puts(m
, "Stolen:\n");
250 while (!list_empty(&stolen
)) {
251 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
253 describe_obj(m
, obj
);
255 list_del_init(&obj
->obj_exec_link
);
257 mutex_unlock(&dev
->struct_mutex
);
259 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
260 count
, total_obj_size
, total_gtt_size
);
265 struct drm_i915_file_private
*file_priv
;
269 u64 active
, inactive
;
272 static int per_file_stats(int id
, void *ptr
, void *data
)
274 struct drm_i915_gem_object
*obj
= ptr
;
275 struct file_stats
*stats
= data
;
276 struct i915_vma
*vma
;
279 stats
->total
+= obj
->base
.size
;
280 if (!obj
->bind_count
)
281 stats
->unbound
+= obj
->base
.size
;
282 if (obj
->base
.name
|| obj
->base
.dma_buf
)
283 stats
->shared
+= obj
->base
.size
;
285 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
286 if (!drm_mm_node_allocated(&vma
->node
))
289 if (i915_vma_is_ggtt(vma
)) {
290 stats
->global
+= vma
->node
.size
;
292 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vma
->vm
);
294 if (ppgtt
->base
.file
!= stats
->file_priv
)
298 if (i915_vma_is_active(vma
))
299 stats
->active
+= vma
->node
.size
;
301 stats
->inactive
+= vma
->node
.size
;
307 #define print_file_stats(m, name, stats) do { \
309 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
320 static void print_batch_pool_stats(struct seq_file
*m
,
321 struct drm_i915_private
*dev_priv
)
323 struct drm_i915_gem_object
*obj
;
324 struct file_stats stats
;
325 struct intel_engine_cs
*engine
;
326 enum intel_engine_id id
;
329 memset(&stats
, 0, sizeof(stats
));
331 for_each_engine(engine
, dev_priv
, id
) {
332 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
333 list_for_each_entry(obj
,
334 &engine
->batch_pool
.cache_list
[j
],
336 per_file_stats(0, obj
, &stats
);
340 print_file_stats(m
, "[k]batch pool", stats
);
343 static int per_file_ctx_stats(int id
, void *ptr
, void *data
)
345 struct i915_gem_context
*ctx
= ptr
;
348 for (n
= 0; n
< ARRAY_SIZE(ctx
->engine
); n
++) {
349 if (ctx
->engine
[n
].state
)
350 per_file_stats(0, ctx
->engine
[n
].state
->obj
, data
);
351 if (ctx
->engine
[n
].ring
)
352 per_file_stats(0, ctx
->engine
[n
].ring
->vma
->obj
, data
);
358 static void print_context_stats(struct seq_file
*m
,
359 struct drm_i915_private
*dev_priv
)
361 struct drm_device
*dev
= &dev_priv
->drm
;
362 struct file_stats stats
;
363 struct drm_file
*file
;
365 memset(&stats
, 0, sizeof(stats
));
367 mutex_lock(&dev
->struct_mutex
);
368 if (dev_priv
->kernel_context
)
369 per_file_ctx_stats(0, dev_priv
->kernel_context
, &stats
);
371 list_for_each_entry(file
, &dev
->filelist
, lhead
) {
372 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
373 idr_for_each(&fpriv
->context_idr
, per_file_ctx_stats
, &stats
);
375 mutex_unlock(&dev
->struct_mutex
);
377 print_file_stats(m
, "[k]contexts", stats
);
380 static int i915_gem_object_info(struct seq_file
*m
, void *data
)
382 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
383 struct drm_device
*dev
= &dev_priv
->drm
;
384 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
385 u32 count
, mapped_count
, purgeable_count
, dpy_count
;
386 u64 size
, mapped_size
, purgeable_size
, dpy_size
;
387 struct drm_i915_gem_object
*obj
;
388 struct drm_file
*file
;
391 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
395 seq_printf(m
, "%u objects, %llu bytes\n",
396 dev_priv
->mm
.object_count
,
397 dev_priv
->mm
.object_memory
);
400 mapped_size
= mapped_count
= 0;
401 purgeable_size
= purgeable_count
= 0;
402 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
403 size
+= obj
->base
.size
;
406 if (obj
->madv
== I915_MADV_DONTNEED
) {
407 purgeable_size
+= obj
->base
.size
;
413 mapped_size
+= obj
->base
.size
;
416 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
418 size
= count
= dpy_size
= dpy_count
= 0;
419 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
420 size
+= obj
->base
.size
;
423 if (obj
->pin_display
) {
424 dpy_size
+= obj
->base
.size
;
428 if (obj
->madv
== I915_MADV_DONTNEED
) {
429 purgeable_size
+= obj
->base
.size
;
435 mapped_size
+= obj
->base
.size
;
438 seq_printf(m
, "%u bound objects, %llu bytes\n",
440 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
441 purgeable_count
, purgeable_size
);
442 seq_printf(m
, "%u mapped objects, %llu bytes\n",
443 mapped_count
, mapped_size
);
444 seq_printf(m
, "%u display objects (pinned), %llu bytes\n",
445 dpy_count
, dpy_size
);
447 seq_printf(m
, "%llu [%llu] gtt total\n",
448 ggtt
->base
.total
, ggtt
->mappable_end
- ggtt
->base
.start
);
451 print_batch_pool_stats(m
, dev_priv
);
452 mutex_unlock(&dev
->struct_mutex
);
454 mutex_lock(&dev
->filelist_mutex
);
455 print_context_stats(m
, dev_priv
);
456 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
457 struct file_stats stats
;
458 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
459 struct drm_i915_gem_request
*request
;
460 struct task_struct
*task
;
462 memset(&stats
, 0, sizeof(stats
));
463 stats
.file_priv
= file
->driver_priv
;
464 spin_lock(&file
->table_lock
);
465 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
466 spin_unlock(&file
->table_lock
);
468 * Although we have a valid reference on file->pid, that does
469 * not guarantee that the task_struct who called get_pid() is
470 * still alive (e.g. get_pid(current) => fork() => exit()).
471 * Therefore, we need to protect this ->comm access using RCU.
473 mutex_lock(&dev
->struct_mutex
);
474 request
= list_first_entry_or_null(&file_priv
->mm
.request_list
,
475 struct drm_i915_gem_request
,
478 task
= pid_task(request
&& request
->ctx
->pid
?
479 request
->ctx
->pid
: file
->pid
,
481 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
483 mutex_unlock(&dev
->struct_mutex
);
485 mutex_unlock(&dev
->filelist_mutex
);
490 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
492 struct drm_info_node
*node
= m
->private;
493 struct drm_i915_private
*dev_priv
= node_to_i915(node
);
494 struct drm_device
*dev
= &dev_priv
->drm
;
495 bool show_pin_display_only
= !!node
->info_ent
->data
;
496 struct drm_i915_gem_object
*obj
;
497 u64 total_obj_size
, total_gtt_size
;
500 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
504 total_obj_size
= total_gtt_size
= count
= 0;
505 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
506 if (show_pin_display_only
&& !obj
->pin_display
)
510 describe_obj(m
, obj
);
512 total_obj_size
+= obj
->base
.size
;
513 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
517 mutex_unlock(&dev
->struct_mutex
);
519 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
520 count
, total_obj_size
, total_gtt_size
);
525 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
527 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
528 struct drm_device
*dev
= &dev_priv
->drm
;
529 struct intel_crtc
*crtc
;
532 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
536 for_each_intel_crtc(dev
, crtc
) {
537 const char pipe
= pipe_name(crtc
->pipe
);
538 const char plane
= plane_name(crtc
->plane
);
539 struct intel_flip_work
*work
;
541 spin_lock_irq(&dev
->event_lock
);
542 work
= crtc
->flip_work
;
544 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
550 pending
= atomic_read(&work
->pending
);
552 seq_printf(m
, "Flip ioctl preparing on pipe %c (plane %c)\n",
555 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
558 if (work
->flip_queued_req
) {
559 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(work
->flip_queued_req
);
561 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
563 i915_gem_request_get_seqno(work
->flip_queued_req
),
564 dev_priv
->next_seqno
,
565 intel_engine_get_seqno(engine
),
566 i915_gem_request_completed(work
->flip_queued_req
));
568 seq_printf(m
, "Flip not associated with any ring\n");
569 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
570 work
->flip_queued_vblank
,
571 work
->flip_ready_vblank
,
572 intel_crtc_get_vblank_counter(crtc
));
573 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
575 if (INTEL_GEN(dev_priv
) >= 4)
576 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
578 addr
= I915_READ(DSPADDR(crtc
->plane
));
579 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
581 if (work
->pending_flip_obj
) {
582 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
583 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
586 spin_unlock_irq(&dev
->event_lock
);
589 mutex_unlock(&dev
->struct_mutex
);
594 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
596 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
597 struct drm_device
*dev
= &dev_priv
->drm
;
598 struct drm_i915_gem_object
*obj
;
599 struct intel_engine_cs
*engine
;
600 enum intel_engine_id id
;
604 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
608 for_each_engine(engine
, dev_priv
, id
) {
609 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
613 list_for_each_entry(obj
,
614 &engine
->batch_pool
.cache_list
[j
],
617 seq_printf(m
, "%s cache[%d]: %d objects\n",
618 engine
->name
, j
, count
);
620 list_for_each_entry(obj
,
621 &engine
->batch_pool
.cache_list
[j
],
624 describe_obj(m
, obj
);
632 seq_printf(m
, "total: %d\n", total
);
634 mutex_unlock(&dev
->struct_mutex
);
639 static void print_request(struct seq_file
*m
,
640 struct drm_i915_gem_request
*rq
,
643 struct pid
*pid
= rq
->ctx
->pid
;
644 struct task_struct
*task
;
647 task
= pid
? pid_task(pid
, PIDTYPE_PID
) : NULL
;
648 seq_printf(m
, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix
,
649 rq
->fence
.seqno
, rq
->ctx
->hw_id
, rq
->fence
.seqno
,
650 jiffies_to_msecs(jiffies
- rq
->emitted_jiffies
),
651 task
? task
->comm
: "<unknown>",
652 task
? task
->pid
: -1);
656 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
658 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
659 struct drm_device
*dev
= &dev_priv
->drm
;
660 struct drm_i915_gem_request
*req
;
661 struct intel_engine_cs
*engine
;
662 enum intel_engine_id id
;
665 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
670 for_each_engine(engine
, dev_priv
, id
) {
674 list_for_each_entry(req
, &engine
->request_list
, link
)
679 seq_printf(m
, "%s requests: %d\n", engine
->name
, count
);
680 list_for_each_entry(req
, &engine
->request_list
, link
)
681 print_request(m
, req
, " ");
685 mutex_unlock(&dev
->struct_mutex
);
688 seq_puts(m
, "No requests\n");
693 static void i915_ring_seqno_info(struct seq_file
*m
,
694 struct intel_engine_cs
*engine
)
696 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
699 seq_printf(m
, "Current sequence (%s): %x\n",
700 engine
->name
, intel_engine_get_seqno(engine
));
703 for (rb
= rb_first(&b
->waiters
); rb
; rb
= rb_next(rb
)) {
704 struct intel_wait
*w
= container_of(rb
, typeof(*w
), node
);
706 seq_printf(m
, "Waiting (%s): %s [%d] on %x\n",
707 engine
->name
, w
->tsk
->comm
, w
->tsk
->pid
, w
->seqno
);
709 spin_unlock(&b
->lock
);
712 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
714 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
715 struct intel_engine_cs
*engine
;
716 enum intel_engine_id id
;
718 for_each_engine(engine
, dev_priv
, id
)
719 i915_ring_seqno_info(m
, engine
);
725 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
727 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
728 struct intel_engine_cs
*engine
;
729 enum intel_engine_id id
;
732 intel_runtime_pm_get(dev_priv
);
734 if (IS_CHERRYVIEW(dev_priv
)) {
735 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
736 I915_READ(GEN8_MASTER_IRQ
));
738 seq_printf(m
, "Display IER:\t%08x\n",
740 seq_printf(m
, "Display IIR:\t%08x\n",
742 seq_printf(m
, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW
));
744 seq_printf(m
, "Display IMR:\t%08x\n",
746 for_each_pipe(dev_priv
, pipe
)
747 seq_printf(m
, "Pipe %c stat:\t%08x\n",
749 I915_READ(PIPESTAT(pipe
)));
751 seq_printf(m
, "Port hotplug:\t%08x\n",
752 I915_READ(PORT_HOTPLUG_EN
));
753 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
754 I915_READ(VLV_DPFLIPSTAT
));
755 seq_printf(m
, "DPINVGTT:\t%08x\n",
756 I915_READ(DPINVGTT
));
758 for (i
= 0; i
< 4; i
++) {
759 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
760 i
, I915_READ(GEN8_GT_IMR(i
)));
761 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
762 i
, I915_READ(GEN8_GT_IIR(i
)));
763 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
764 i
, I915_READ(GEN8_GT_IER(i
)));
767 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
768 I915_READ(GEN8_PCU_IMR
));
769 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
770 I915_READ(GEN8_PCU_IIR
));
771 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
772 I915_READ(GEN8_PCU_IER
));
773 } else if (INTEL_GEN(dev_priv
) >= 8) {
774 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ
));
777 for (i
= 0; i
< 4; i
++) {
778 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
779 i
, I915_READ(GEN8_GT_IMR(i
)));
780 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
781 i
, I915_READ(GEN8_GT_IIR(i
)));
782 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
783 i
, I915_READ(GEN8_GT_IER(i
)));
786 for_each_pipe(dev_priv
, pipe
) {
787 enum intel_display_power_domain power_domain
;
789 power_domain
= POWER_DOMAIN_PIPE(pipe
);
790 if (!intel_display_power_get_if_enabled(dev_priv
,
792 seq_printf(m
, "Pipe %c power disabled\n",
796 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
798 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
799 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
801 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
802 seq_printf(m
, "Pipe %c IER:\t%08x\n",
804 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
806 intel_display_power_put(dev_priv
, power_domain
);
809 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
810 I915_READ(GEN8_DE_PORT_IMR
));
811 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
812 I915_READ(GEN8_DE_PORT_IIR
));
813 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
814 I915_READ(GEN8_DE_PORT_IER
));
816 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
817 I915_READ(GEN8_DE_MISC_IMR
));
818 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
819 I915_READ(GEN8_DE_MISC_IIR
));
820 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
821 I915_READ(GEN8_DE_MISC_IER
));
823 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
824 I915_READ(GEN8_PCU_IMR
));
825 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
826 I915_READ(GEN8_PCU_IIR
));
827 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
828 I915_READ(GEN8_PCU_IER
));
829 } else if (IS_VALLEYVIEW(dev_priv
)) {
830 seq_printf(m
, "Display IER:\t%08x\n",
832 seq_printf(m
, "Display IIR:\t%08x\n",
834 seq_printf(m
, "Display IIR_RW:\t%08x\n",
835 I915_READ(VLV_IIR_RW
));
836 seq_printf(m
, "Display IMR:\t%08x\n",
838 for_each_pipe(dev_priv
, pipe
)
839 seq_printf(m
, "Pipe %c stat:\t%08x\n",
841 I915_READ(PIPESTAT(pipe
)));
843 seq_printf(m
, "Master IER:\t%08x\n",
844 I915_READ(VLV_MASTER_IER
));
846 seq_printf(m
, "Render IER:\t%08x\n",
848 seq_printf(m
, "Render IIR:\t%08x\n",
850 seq_printf(m
, "Render IMR:\t%08x\n",
853 seq_printf(m
, "PM IER:\t\t%08x\n",
854 I915_READ(GEN6_PMIER
));
855 seq_printf(m
, "PM IIR:\t\t%08x\n",
856 I915_READ(GEN6_PMIIR
));
857 seq_printf(m
, "PM IMR:\t\t%08x\n",
858 I915_READ(GEN6_PMIMR
));
860 seq_printf(m
, "Port hotplug:\t%08x\n",
861 I915_READ(PORT_HOTPLUG_EN
));
862 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
863 I915_READ(VLV_DPFLIPSTAT
));
864 seq_printf(m
, "DPINVGTT:\t%08x\n",
865 I915_READ(DPINVGTT
));
867 } else if (!HAS_PCH_SPLIT(dev_priv
)) {
868 seq_printf(m
, "Interrupt enable: %08x\n",
870 seq_printf(m
, "Interrupt identity: %08x\n",
872 seq_printf(m
, "Interrupt mask: %08x\n",
874 for_each_pipe(dev_priv
, pipe
)
875 seq_printf(m
, "Pipe %c stat: %08x\n",
877 I915_READ(PIPESTAT(pipe
)));
879 seq_printf(m
, "North Display Interrupt enable: %08x\n",
881 seq_printf(m
, "North Display Interrupt identity: %08x\n",
883 seq_printf(m
, "North Display Interrupt mask: %08x\n",
885 seq_printf(m
, "South Display Interrupt enable: %08x\n",
887 seq_printf(m
, "South Display Interrupt identity: %08x\n",
889 seq_printf(m
, "South Display Interrupt mask: %08x\n",
891 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
893 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
895 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
898 for_each_engine(engine
, dev_priv
, id
) {
899 if (INTEL_GEN(dev_priv
) >= 6) {
901 "Graphics Interrupt mask (%s): %08x\n",
902 engine
->name
, I915_READ_IMR(engine
));
904 i915_ring_seqno_info(m
, engine
);
906 intel_runtime_pm_put(dev_priv
);
911 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
913 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
914 struct drm_device
*dev
= &dev_priv
->drm
;
917 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
921 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
922 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
923 struct i915_vma
*vma
= dev_priv
->fence_regs
[i
].vma
;
925 seq_printf(m
, "Fence %d, pin count = %d, object = ",
926 i
, dev_priv
->fence_regs
[i
].pin_count
);
928 seq_puts(m
, "unused");
930 describe_obj(m
, vma
->obj
);
934 mutex_unlock(&dev
->struct_mutex
);
938 static int i915_hws_info(struct seq_file
*m
, void *data
)
940 struct drm_info_node
*node
= m
->private;
941 struct drm_i915_private
*dev_priv
= node_to_i915(node
);
942 struct intel_engine_cs
*engine
;
946 engine
= dev_priv
->engine
[(uintptr_t)node
->info_ent
->data
];
947 hws
= engine
->status_page
.page_addr
;
951 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
952 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
954 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
959 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
962 i915_error_state_write(struct file
*filp
,
963 const char __user
*ubuf
,
967 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
969 DRM_DEBUG_DRIVER("Resetting error state\n");
970 i915_destroy_error_state(error_priv
->dev
);
975 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
977 struct drm_i915_private
*dev_priv
= inode
->i_private
;
978 struct i915_error_state_file_priv
*error_priv
;
980 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
984 error_priv
->dev
= &dev_priv
->drm
;
986 i915_error_state_get(&dev_priv
->drm
, error_priv
);
988 file
->private_data
= error_priv
;
993 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
995 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
997 i915_error_state_put(error_priv
);
1003 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1004 size_t count
, loff_t
*pos
)
1006 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1007 struct drm_i915_error_state_buf error_str
;
1009 ssize_t ret_count
= 0;
1012 ret
= i915_error_state_buf_init(&error_str
,
1013 to_i915(error_priv
->dev
), count
, *pos
);
1017 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1021 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1028 *pos
= error_str
.start
+ ret_count
;
1030 i915_error_state_buf_release(&error_str
);
1031 return ret
?: ret_count
;
1034 static const struct file_operations i915_error_state_fops
= {
1035 .owner
= THIS_MODULE
,
1036 .open
= i915_error_state_open
,
1037 .read
= i915_error_state_read
,
1038 .write
= i915_error_state_write
,
1039 .llseek
= default_llseek
,
1040 .release
= i915_error_state_release
,
1046 i915_next_seqno_get(void *data
, u64
*val
)
1048 struct drm_i915_private
*dev_priv
= data
;
1051 ret
= mutex_lock_interruptible(&dev_priv
->drm
.struct_mutex
);
1055 *val
= dev_priv
->next_seqno
;
1056 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
1062 i915_next_seqno_set(void *data
, u64 val
)
1064 struct drm_i915_private
*dev_priv
= data
;
1065 struct drm_device
*dev
= &dev_priv
->drm
;
1068 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1072 ret
= i915_gem_set_seqno(dev
, val
);
1073 mutex_unlock(&dev
->struct_mutex
);
1078 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1079 i915_next_seqno_get
, i915_next_seqno_set
,
1082 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1084 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1085 struct drm_device
*dev
= &dev_priv
->drm
;
1088 intel_runtime_pm_get(dev_priv
);
1090 if (IS_GEN5(dev_priv
)) {
1091 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1092 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1094 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1095 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1096 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1098 seq_printf(m
, "Current P-state: %d\n",
1099 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1100 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1103 mutex_lock(&dev_priv
->rps
.hw_lock
);
1104 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1105 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1106 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1108 seq_printf(m
, "actual GPU freq: %d MHz\n",
1109 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1111 seq_printf(m
, "current GPU freq: %d MHz\n",
1112 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1114 seq_printf(m
, "max GPU freq: %d MHz\n",
1115 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1117 seq_printf(m
, "min GPU freq: %d MHz\n",
1118 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1120 seq_printf(m
, "idle GPU freq: %d MHz\n",
1121 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1124 "efficient (RPe) frequency: %d MHz\n",
1125 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1126 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1127 } else if (INTEL_GEN(dev_priv
) >= 6) {
1128 u32 rp_state_limits
;
1131 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1132 u32 rpstat
, cagf
, reqf
;
1133 u32 rpupei
, rpcurup
, rpprevup
;
1134 u32 rpdownei
, rpcurdown
, rpprevdown
;
1135 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1138 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1139 if (IS_BROXTON(dev_priv
)) {
1140 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1141 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1143 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1144 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1147 /* RPSTAT1 is in the GT power well */
1148 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1152 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1154 reqf
= I915_READ(GEN6_RPNSWREQ
);
1155 if (IS_GEN9(dev_priv
))
1158 reqf
&= ~GEN6_TURBO_DISABLE
;
1159 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1164 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1166 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1167 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1168 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1170 rpstat
= I915_READ(GEN6_RPSTAT1
);
1171 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
) & GEN6_CURICONT_MASK
;
1172 rpcurup
= I915_READ(GEN6_RP_CUR_UP
) & GEN6_CURBSYTAVG_MASK
;
1173 rpprevup
= I915_READ(GEN6_RP_PREV_UP
) & GEN6_CURBSYTAVG_MASK
;
1174 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
) & GEN6_CURIAVG_MASK
;
1175 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1176 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1177 if (IS_GEN9(dev_priv
))
1178 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1179 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1180 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1182 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1183 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1185 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1186 mutex_unlock(&dev
->struct_mutex
);
1188 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)) {
1189 pm_ier
= I915_READ(GEN6_PMIER
);
1190 pm_imr
= I915_READ(GEN6_PMIMR
);
1191 pm_isr
= I915_READ(GEN6_PMISR
);
1192 pm_iir
= I915_READ(GEN6_PMIIR
);
1193 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1195 pm_ier
= I915_READ(GEN8_GT_IER(2));
1196 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1197 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1198 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1199 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1201 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1202 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1203 seq_printf(m
, "pm_intr_keep: 0x%08x\n", dev_priv
->rps
.pm_intr_keep
);
1204 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1205 seq_printf(m
, "Render p-state ratio: %d\n",
1206 (gt_perf_status
& (IS_GEN9(dev_priv
) ? 0x1ff00 : 0xff00)) >> 8);
1207 seq_printf(m
, "Render p-state VID: %d\n",
1208 gt_perf_status
& 0xff);
1209 seq_printf(m
, "Render p-state limit: %d\n",
1210 rp_state_limits
& 0xff);
1211 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1212 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1213 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1214 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1215 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1216 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1217 seq_printf(m
, "RP CUR UP EI: %d (%dus)\n",
1218 rpupei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpupei
));
1219 seq_printf(m
, "RP CUR UP: %d (%dus)\n",
1220 rpcurup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurup
));
1221 seq_printf(m
, "RP PREV UP: %d (%dus)\n",
1222 rpprevup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevup
));
1223 seq_printf(m
, "Up threshold: %d%%\n",
1224 dev_priv
->rps
.up_threshold
);
1226 seq_printf(m
, "RP CUR DOWN EI: %d (%dus)\n",
1227 rpdownei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpdownei
));
1228 seq_printf(m
, "RP CUR DOWN: %d (%dus)\n",
1229 rpcurdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurdown
));
1230 seq_printf(m
, "RP PREV DOWN: %d (%dus)\n",
1231 rpprevdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevdown
));
1232 seq_printf(m
, "Down threshold: %d%%\n",
1233 dev_priv
->rps
.down_threshold
);
1235 max_freq
= (IS_BROXTON(dev_priv
) ? rp_state_cap
>> 0 :
1236 rp_state_cap
>> 16) & 0xff;
1237 max_freq
*= (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ?
1238 GEN9_FREQ_SCALER
: 1);
1239 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1240 intel_gpu_freq(dev_priv
, max_freq
));
1242 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1243 max_freq
*= (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ?
1244 GEN9_FREQ_SCALER
: 1);
1245 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1246 intel_gpu_freq(dev_priv
, max_freq
));
1248 max_freq
= (IS_BROXTON(dev_priv
) ? rp_state_cap
>> 16 :
1249 rp_state_cap
>> 0) & 0xff;
1250 max_freq
*= (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ?
1251 GEN9_FREQ_SCALER
: 1);
1252 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1253 intel_gpu_freq(dev_priv
, max_freq
));
1254 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1255 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1257 seq_printf(m
, "Current freq: %d MHz\n",
1258 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1259 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1260 seq_printf(m
, "Idle freq: %d MHz\n",
1261 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1262 seq_printf(m
, "Min freq: %d MHz\n",
1263 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1264 seq_printf(m
, "Boost freq: %d MHz\n",
1265 intel_gpu_freq(dev_priv
, dev_priv
->rps
.boost_freq
));
1266 seq_printf(m
, "Max freq: %d MHz\n",
1267 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1269 "efficient (RPe) frequency: %d MHz\n",
1270 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1272 seq_puts(m
, "no P-state info available\n");
1275 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1276 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1277 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1280 intel_runtime_pm_put(dev_priv
);
1284 static void i915_instdone_info(struct drm_i915_private
*dev_priv
,
1286 struct intel_instdone
*instdone
)
1291 seq_printf(m
, "\t\tINSTDONE: 0x%08x\n",
1292 instdone
->instdone
);
1294 if (INTEL_GEN(dev_priv
) <= 3)
1297 seq_printf(m
, "\t\tSC_INSTDONE: 0x%08x\n",
1298 instdone
->slice_common
);
1300 if (INTEL_GEN(dev_priv
) <= 6)
1303 for_each_instdone_slice_subslice(dev_priv
, slice
, subslice
)
1304 seq_printf(m
, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1305 slice
, subslice
, instdone
->sampler
[slice
][subslice
]);
1307 for_each_instdone_slice_subslice(dev_priv
, slice
, subslice
)
1308 seq_printf(m
, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1309 slice
, subslice
, instdone
->row
[slice
][subslice
]);
1312 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1314 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1315 struct intel_engine_cs
*engine
;
1316 u64 acthd
[I915_NUM_ENGINES
];
1317 u32 seqno
[I915_NUM_ENGINES
];
1318 struct intel_instdone instdone
;
1319 enum intel_engine_id id
;
1321 if (test_bit(I915_WEDGED
, &dev_priv
->gpu_error
.flags
))
1322 seq_printf(m
, "Wedged\n");
1323 if (test_bit(I915_RESET_IN_PROGRESS
, &dev_priv
->gpu_error
.flags
))
1324 seq_printf(m
, "Reset in progress\n");
1325 if (waitqueue_active(&dev_priv
->gpu_error
.wait_queue
))
1326 seq_printf(m
, "Waiter holding struct mutex\n");
1327 if (waitqueue_active(&dev_priv
->gpu_error
.reset_queue
))
1328 seq_printf(m
, "struct_mutex blocked for reset\n");
1330 if (!i915
.enable_hangcheck
) {
1331 seq_printf(m
, "Hangcheck disabled\n");
1335 intel_runtime_pm_get(dev_priv
);
1337 for_each_engine(engine
, dev_priv
, id
) {
1338 acthd
[id
] = intel_engine_get_active_head(engine
);
1339 seqno
[id
] = intel_engine_get_seqno(engine
);
1342 intel_engine_get_instdone(dev_priv
->engine
[RCS
], &instdone
);
1344 intel_runtime_pm_put(dev_priv
);
1346 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1347 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1348 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1351 seq_printf(m
, "Hangcheck inactive\n");
1353 for_each_engine(engine
, dev_priv
, id
) {
1354 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
1357 seq_printf(m
, "%s:\n", engine
->name
);
1358 seq_printf(m
, "\tseqno = %x [current %x, last %x]\n",
1359 engine
->hangcheck
.seqno
,
1361 engine
->last_submitted_seqno
);
1362 seq_printf(m
, "\twaiters? %s, fake irq active? %s\n",
1363 yesno(intel_engine_has_waiter(engine
)),
1364 yesno(test_bit(engine
->id
,
1365 &dev_priv
->gpu_error
.missed_irq_rings
)));
1366 spin_lock(&b
->lock
);
1367 for (rb
= rb_first(&b
->waiters
); rb
; rb
= rb_next(rb
)) {
1368 struct intel_wait
*w
= container_of(rb
, typeof(*w
), node
);
1370 seq_printf(m
, "\t%s [%d] waiting for %x\n",
1371 w
->tsk
->comm
, w
->tsk
->pid
, w
->seqno
);
1373 spin_unlock(&b
->lock
);
1375 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1376 (long long)engine
->hangcheck
.acthd
,
1377 (long long)acthd
[id
]);
1378 seq_printf(m
, "\tscore = %d\n", engine
->hangcheck
.score
);
1379 seq_printf(m
, "\taction = %d\n", engine
->hangcheck
.action
);
1381 if (engine
->id
== RCS
) {
1382 seq_puts(m
, "\tinstdone read =\n");
1384 i915_instdone_info(dev_priv
, m
, &instdone
);
1386 seq_puts(m
, "\tinstdone accu =\n");
1388 i915_instdone_info(dev_priv
, m
,
1389 &engine
->hangcheck
.instdone
);
1396 static int ironlake_drpc_info(struct seq_file
*m
)
1398 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1399 struct drm_device
*dev
= &dev_priv
->drm
;
1400 u32 rgvmodectl
, rstdbyctl
;
1404 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1407 intel_runtime_pm_get(dev_priv
);
1409 rgvmodectl
= I915_READ(MEMMODECTL
);
1410 rstdbyctl
= I915_READ(RSTDBYCTL
);
1411 crstandvid
= I915_READ16(CRSTANDVID
);
1413 intel_runtime_pm_put(dev_priv
);
1414 mutex_unlock(&dev
->struct_mutex
);
1416 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1417 seq_printf(m
, "Boost freq: %d\n",
1418 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1419 MEMMODE_BOOST_FREQ_SHIFT
);
1420 seq_printf(m
, "HW control enabled: %s\n",
1421 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1422 seq_printf(m
, "SW control enabled: %s\n",
1423 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1424 seq_printf(m
, "Gated voltage change: %s\n",
1425 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1426 seq_printf(m
, "Starting frequency: P%d\n",
1427 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1428 seq_printf(m
, "Max P-state: P%d\n",
1429 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1430 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1431 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1432 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1433 seq_printf(m
, "Render standby enabled: %s\n",
1434 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1435 seq_puts(m
, "Current RS state: ");
1436 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1438 seq_puts(m
, "on\n");
1440 case RSX_STATUS_RC1
:
1441 seq_puts(m
, "RC1\n");
1443 case RSX_STATUS_RC1E
:
1444 seq_puts(m
, "RC1E\n");
1446 case RSX_STATUS_RS1
:
1447 seq_puts(m
, "RS1\n");
1449 case RSX_STATUS_RS2
:
1450 seq_puts(m
, "RS2 (RC6)\n");
1452 case RSX_STATUS_RS3
:
1453 seq_puts(m
, "RC3 (RC6+)\n");
1456 seq_puts(m
, "unknown\n");
1463 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1465 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1466 struct intel_uncore_forcewake_domain
*fw_domain
;
1468 spin_lock_irq(&dev_priv
->uncore
.lock
);
1469 for_each_fw_domain(fw_domain
, dev_priv
) {
1470 seq_printf(m
, "%s.wake_count = %u\n",
1471 intel_uncore_forcewake_domain_to_str(fw_domain
->id
),
1472 fw_domain
->wake_count
);
1474 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1479 static int vlv_drpc_info(struct seq_file
*m
)
1481 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1482 u32 rpmodectl1
, rcctl1
, pw_status
;
1484 intel_runtime_pm_get(dev_priv
);
1486 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1487 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1488 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1490 intel_runtime_pm_put(dev_priv
);
1492 seq_printf(m
, "Video Turbo Mode: %s\n",
1493 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1494 seq_printf(m
, "Turbo enabled: %s\n",
1495 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1496 seq_printf(m
, "HW control enabled: %s\n",
1497 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1498 seq_printf(m
, "SW control enabled: %s\n",
1499 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1500 GEN6_RP_MEDIA_SW_MODE
));
1501 seq_printf(m
, "RC6 Enabled: %s\n",
1502 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1503 GEN6_RC_CTL_EI_MODE(1))));
1504 seq_printf(m
, "Render Power Well: %s\n",
1505 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1506 seq_printf(m
, "Media Power Well: %s\n",
1507 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1509 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1510 I915_READ(VLV_GT_RENDER_RC6
));
1511 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1512 I915_READ(VLV_GT_MEDIA_RC6
));
1514 return i915_forcewake_domains(m
, NULL
);
1517 static int gen6_drpc_info(struct seq_file
*m
)
1519 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1520 struct drm_device
*dev
= &dev_priv
->drm
;
1521 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1522 u32 gen9_powergate_enable
= 0, gen9_powergate_status
= 0;
1523 unsigned forcewake_count
;
1526 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1529 intel_runtime_pm_get(dev_priv
);
1531 spin_lock_irq(&dev_priv
->uncore
.lock
);
1532 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1533 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1535 if (forcewake_count
) {
1536 seq_puts(m
, "RC information inaccurate because somebody "
1537 "holds a forcewake reference \n");
1539 /* NB: we cannot use forcewake, else we read the wrong values */
1540 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1542 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1545 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1546 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1548 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1549 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1550 if (INTEL_GEN(dev_priv
) >= 9) {
1551 gen9_powergate_enable
= I915_READ(GEN9_PG_ENABLE
);
1552 gen9_powergate_status
= I915_READ(GEN9_PWRGT_DOMAIN_STATUS
);
1554 mutex_unlock(&dev
->struct_mutex
);
1555 mutex_lock(&dev_priv
->rps
.hw_lock
);
1556 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1557 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1559 intel_runtime_pm_put(dev_priv
);
1561 seq_printf(m
, "Video Turbo Mode: %s\n",
1562 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1563 seq_printf(m
, "HW control enabled: %s\n",
1564 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1565 seq_printf(m
, "SW control enabled: %s\n",
1566 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1567 GEN6_RP_MEDIA_SW_MODE
));
1568 seq_printf(m
, "RC1e Enabled: %s\n",
1569 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1570 seq_printf(m
, "RC6 Enabled: %s\n",
1571 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1572 if (INTEL_GEN(dev_priv
) >= 9) {
1573 seq_printf(m
, "Render Well Gating Enabled: %s\n",
1574 yesno(gen9_powergate_enable
& GEN9_RENDER_PG_ENABLE
));
1575 seq_printf(m
, "Media Well Gating Enabled: %s\n",
1576 yesno(gen9_powergate_enable
& GEN9_MEDIA_PG_ENABLE
));
1578 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1579 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1580 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1581 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1582 seq_puts(m
, "Current RC state: ");
1583 switch (gt_core_status
& GEN6_RCn_MASK
) {
1585 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1586 seq_puts(m
, "Core Power Down\n");
1588 seq_puts(m
, "on\n");
1591 seq_puts(m
, "RC3\n");
1594 seq_puts(m
, "RC6\n");
1597 seq_puts(m
, "RC7\n");
1600 seq_puts(m
, "Unknown\n");
1604 seq_printf(m
, "Core Power Down: %s\n",
1605 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1606 if (INTEL_GEN(dev_priv
) >= 9) {
1607 seq_printf(m
, "Render Power Well: %s\n",
1608 (gen9_powergate_status
&
1609 GEN9_PWRGT_RENDER_STATUS_MASK
) ? "Up" : "Down");
1610 seq_printf(m
, "Media Power Well: %s\n",
1611 (gen9_powergate_status
&
1612 GEN9_PWRGT_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1615 /* Not exactly sure what this is */
1616 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1617 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1618 seq_printf(m
, "RC6 residency since boot: %u\n",
1619 I915_READ(GEN6_GT_GFX_RC6
));
1620 seq_printf(m
, "RC6+ residency since boot: %u\n",
1621 I915_READ(GEN6_GT_GFX_RC6p
));
1622 seq_printf(m
, "RC6++ residency since boot: %u\n",
1623 I915_READ(GEN6_GT_GFX_RC6pp
));
1625 seq_printf(m
, "RC6 voltage: %dmV\n",
1626 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1627 seq_printf(m
, "RC6+ voltage: %dmV\n",
1628 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1629 seq_printf(m
, "RC6++ voltage: %dmV\n",
1630 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1631 return i915_forcewake_domains(m
, NULL
);
1634 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1636 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1638 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1639 return vlv_drpc_info(m
);
1640 else if (INTEL_GEN(dev_priv
) >= 6)
1641 return gen6_drpc_info(m
);
1643 return ironlake_drpc_info(m
);
1646 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1648 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1650 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1651 dev_priv
->fb_tracking
.busy_bits
);
1653 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1654 dev_priv
->fb_tracking
.flip_bits
);
1659 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1661 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1663 if (!HAS_FBC(dev_priv
)) {
1664 seq_puts(m
, "FBC unsupported on this chipset\n");
1668 intel_runtime_pm_get(dev_priv
);
1669 mutex_lock(&dev_priv
->fbc
.lock
);
1671 if (intel_fbc_is_active(dev_priv
))
1672 seq_puts(m
, "FBC enabled\n");
1674 seq_printf(m
, "FBC disabled: %s\n",
1675 dev_priv
->fbc
.no_fbc_reason
);
1677 if (intel_fbc_is_active(dev_priv
) &&
1678 INTEL_GEN(dev_priv
) >= 7)
1679 seq_printf(m
, "Compressing: %s\n",
1680 yesno(I915_READ(FBC_STATUS2
) &
1681 FBC_COMPRESSION_MASK
));
1683 mutex_unlock(&dev_priv
->fbc
.lock
);
1684 intel_runtime_pm_put(dev_priv
);
1689 static int i915_fbc_fc_get(void *data
, u64
*val
)
1691 struct drm_i915_private
*dev_priv
= data
;
1693 if (INTEL_GEN(dev_priv
) < 7 || !HAS_FBC(dev_priv
))
1696 *val
= dev_priv
->fbc
.false_color
;
1701 static int i915_fbc_fc_set(void *data
, u64 val
)
1703 struct drm_i915_private
*dev_priv
= data
;
1706 if (INTEL_GEN(dev_priv
) < 7 || !HAS_FBC(dev_priv
))
1709 mutex_lock(&dev_priv
->fbc
.lock
);
1711 reg
= I915_READ(ILK_DPFC_CONTROL
);
1712 dev_priv
->fbc
.false_color
= val
;
1714 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1715 (reg
| FBC_CTL_FALSE_COLOR
) :
1716 (reg
& ~FBC_CTL_FALSE_COLOR
));
1718 mutex_unlock(&dev_priv
->fbc
.lock
);
1722 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1723 i915_fbc_fc_get
, i915_fbc_fc_set
,
1726 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1728 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1730 if (!HAS_IPS(dev_priv
)) {
1731 seq_puts(m
, "not supported\n");
1735 intel_runtime_pm_get(dev_priv
);
1737 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1738 yesno(i915
.enable_ips
));
1740 if (INTEL_GEN(dev_priv
) >= 8) {
1741 seq_puts(m
, "Currently: unknown\n");
1743 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1744 seq_puts(m
, "Currently: enabled\n");
1746 seq_puts(m
, "Currently: disabled\n");
1749 intel_runtime_pm_put(dev_priv
);
1754 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1756 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1757 bool sr_enabled
= false;
1759 intel_runtime_pm_get(dev_priv
);
1761 if (HAS_PCH_SPLIT(dev_priv
))
1762 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1763 else if (IS_CRESTLINE(dev_priv
) || IS_G4X(dev_priv
) ||
1764 IS_I945G(dev_priv
) || IS_I945GM(dev_priv
))
1765 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1766 else if (IS_I915GM(dev_priv
))
1767 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1768 else if (IS_PINEVIEW(dev_priv
))
1769 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1770 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1771 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1773 intel_runtime_pm_put(dev_priv
);
1775 seq_printf(m
, "self-refresh: %s\n",
1776 sr_enabled
? "enabled" : "disabled");
1781 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1783 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1784 struct drm_device
*dev
= &dev_priv
->drm
;
1785 unsigned long temp
, chipset
, gfx
;
1788 if (!IS_GEN5(dev_priv
))
1791 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1795 temp
= i915_mch_val(dev_priv
);
1796 chipset
= i915_chipset_val(dev_priv
);
1797 gfx
= i915_gfx_val(dev_priv
);
1798 mutex_unlock(&dev
->struct_mutex
);
1800 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1801 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1802 seq_printf(m
, "GFX power: %ld\n", gfx
);
1803 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1808 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1810 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1812 int gpu_freq
, ia_freq
;
1813 unsigned int max_gpu_freq
, min_gpu_freq
;
1815 if (!HAS_LLC(dev_priv
)) {
1816 seq_puts(m
, "unsupported on this chipset\n");
1820 intel_runtime_pm_get(dev_priv
);
1822 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1826 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
1827 /* Convert GT frequency to 50 HZ units */
1829 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1831 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1833 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1834 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1837 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1839 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1841 sandybridge_pcode_read(dev_priv
,
1842 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1844 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1845 intel_gpu_freq(dev_priv
, (gpu_freq
*
1846 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
) ?
1847 GEN9_FREQ_SCALER
: 1))),
1848 ((ia_freq
>> 0) & 0xff) * 100,
1849 ((ia_freq
>> 8) & 0xff) * 100);
1852 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1855 intel_runtime_pm_put(dev_priv
);
1859 static int i915_opregion(struct seq_file
*m
, void *unused
)
1861 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1862 struct drm_device
*dev
= &dev_priv
->drm
;
1863 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1866 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1870 if (opregion
->header
)
1871 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1873 mutex_unlock(&dev
->struct_mutex
);
1879 static int i915_vbt(struct seq_file
*m
, void *unused
)
1881 struct intel_opregion
*opregion
= &node_to_i915(m
->private)->opregion
;
1884 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1889 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1891 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1892 struct drm_device
*dev
= &dev_priv
->drm
;
1893 struct intel_framebuffer
*fbdev_fb
= NULL
;
1894 struct drm_framebuffer
*drm_fb
;
1897 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1901 #ifdef CONFIG_DRM_FBDEV_EMULATION
1902 if (dev_priv
->fbdev
) {
1903 fbdev_fb
= to_intel_framebuffer(dev_priv
->fbdev
->helper
.fb
);
1905 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1906 fbdev_fb
->base
.width
,
1907 fbdev_fb
->base
.height
,
1908 fbdev_fb
->base
.depth
,
1909 fbdev_fb
->base
.bits_per_pixel
,
1910 fbdev_fb
->base
.modifier
[0],
1911 drm_framebuffer_read_refcount(&fbdev_fb
->base
));
1912 describe_obj(m
, fbdev_fb
->obj
);
1917 mutex_lock(&dev
->mode_config
.fb_lock
);
1918 drm_for_each_fb(drm_fb
, dev
) {
1919 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1923 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1927 fb
->base
.bits_per_pixel
,
1928 fb
->base
.modifier
[0],
1929 drm_framebuffer_read_refcount(&fb
->base
));
1930 describe_obj(m
, fb
->obj
);
1933 mutex_unlock(&dev
->mode_config
.fb_lock
);
1934 mutex_unlock(&dev
->struct_mutex
);
1939 static void describe_ctx_ring(struct seq_file
*m
, struct intel_ring
*ring
)
1941 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1942 ring
->space
, ring
->head
, ring
->tail
,
1943 ring
->last_retired_head
);
1946 static int i915_context_status(struct seq_file
*m
, void *unused
)
1948 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
1949 struct drm_device
*dev
= &dev_priv
->drm
;
1950 struct intel_engine_cs
*engine
;
1951 struct i915_gem_context
*ctx
;
1952 enum intel_engine_id id
;
1955 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1959 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1960 seq_printf(m
, "HW context %u ", ctx
->hw_id
);
1962 struct task_struct
*task
;
1964 task
= get_pid_task(ctx
->pid
, PIDTYPE_PID
);
1966 seq_printf(m
, "(%s [%d]) ",
1967 task
->comm
, task
->pid
);
1968 put_task_struct(task
);
1970 } else if (IS_ERR(ctx
->file_priv
)) {
1971 seq_puts(m
, "(deleted) ");
1973 seq_puts(m
, "(kernel) ");
1976 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
1979 for_each_engine(engine
, dev_priv
, id
) {
1980 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
1982 seq_printf(m
, "%s: ", engine
->name
);
1983 seq_putc(m
, ce
->initialised
? 'I' : 'i');
1985 describe_obj(m
, ce
->state
->obj
);
1987 describe_ctx_ring(m
, ce
->ring
);
1994 mutex_unlock(&dev
->struct_mutex
);
1999 static void i915_dump_lrc_obj(struct seq_file
*m
,
2000 struct i915_gem_context
*ctx
,
2001 struct intel_engine_cs
*engine
)
2003 struct i915_vma
*vma
= ctx
->engine
[engine
->id
].state
;
2007 seq_printf(m
, "CONTEXT: %s %u\n", engine
->name
, ctx
->hw_id
);
2010 seq_puts(m
, "\tFake context\n");
2014 if (vma
->flags
& I915_VMA_GLOBAL_BIND
)
2015 seq_printf(m
, "\tBound in GGTT at 0x%08x\n",
2016 i915_ggtt_offset(vma
));
2018 if (i915_gem_object_get_pages(vma
->obj
)) {
2019 seq_puts(m
, "\tFailed to get pages for context object\n\n");
2023 page
= i915_gem_object_get_page(vma
->obj
, LRC_STATE_PN
);
2025 u32
*reg_state
= kmap_atomic(page
);
2027 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2029 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2031 reg_state
[j
], reg_state
[j
+ 1],
2032 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2034 kunmap_atomic(reg_state
);
2040 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2042 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2043 struct drm_device
*dev
= &dev_priv
->drm
;
2044 struct intel_engine_cs
*engine
;
2045 struct i915_gem_context
*ctx
;
2046 enum intel_engine_id id
;
2049 if (!i915
.enable_execlists
) {
2050 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2054 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2058 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2059 for_each_engine(engine
, dev_priv
, id
)
2060 i915_dump_lrc_obj(m
, ctx
, engine
);
2062 mutex_unlock(&dev
->struct_mutex
);
2067 static const char *swizzle_string(unsigned swizzle
)
2070 case I915_BIT_6_SWIZZLE_NONE
:
2072 case I915_BIT_6_SWIZZLE_9
:
2074 case I915_BIT_6_SWIZZLE_9_10
:
2075 return "bit9/bit10";
2076 case I915_BIT_6_SWIZZLE_9_11
:
2077 return "bit9/bit11";
2078 case I915_BIT_6_SWIZZLE_9_10_11
:
2079 return "bit9/bit10/bit11";
2080 case I915_BIT_6_SWIZZLE_9_17
:
2081 return "bit9/bit17";
2082 case I915_BIT_6_SWIZZLE_9_10_17
:
2083 return "bit9/bit10/bit17";
2084 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2091 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2093 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2094 struct drm_device
*dev
= &dev_priv
->drm
;
2097 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2100 intel_runtime_pm_get(dev_priv
);
2102 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2103 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2104 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2105 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2107 if (IS_GEN3(dev_priv
) || IS_GEN4(dev_priv
)) {
2108 seq_printf(m
, "DDC = 0x%08x\n",
2110 seq_printf(m
, "DDC2 = 0x%08x\n",
2112 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2113 I915_READ16(C0DRB3
));
2114 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2115 I915_READ16(C1DRB3
));
2116 } else if (INTEL_GEN(dev_priv
) >= 6) {
2117 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2118 I915_READ(MAD_DIMM_C0
));
2119 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2120 I915_READ(MAD_DIMM_C1
));
2121 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2122 I915_READ(MAD_DIMM_C2
));
2123 seq_printf(m
, "TILECTL = 0x%08x\n",
2124 I915_READ(TILECTL
));
2125 if (INTEL_GEN(dev_priv
) >= 8)
2126 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2127 I915_READ(GAMTARBMODE
));
2129 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2130 I915_READ(ARB_MODE
));
2131 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2132 I915_READ(DISP_ARB_CTL
));
2135 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2136 seq_puts(m
, "L-shaped memory detected\n");
2138 intel_runtime_pm_put(dev_priv
);
2139 mutex_unlock(&dev
->struct_mutex
);
2144 static int per_file_ctx(int id
, void *ptr
, void *data
)
2146 struct i915_gem_context
*ctx
= ptr
;
2147 struct seq_file
*m
= data
;
2148 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2151 seq_printf(m
, " no ppgtt for context %d\n",
2156 if (i915_gem_context_is_default(ctx
))
2157 seq_puts(m
, " default context:\n");
2159 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2160 ppgtt
->debug_dump(ppgtt
, m
);
2165 static void gen8_ppgtt_info(struct seq_file
*m
,
2166 struct drm_i915_private
*dev_priv
)
2168 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2169 struct intel_engine_cs
*engine
;
2170 enum intel_engine_id id
;
2176 for_each_engine(engine
, dev_priv
, id
) {
2177 seq_printf(m
, "%s\n", engine
->name
);
2178 for (i
= 0; i
< 4; i
++) {
2179 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(engine
, i
));
2181 pdp
|= I915_READ(GEN8_RING_PDP_LDW(engine
, i
));
2182 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2187 static void gen6_ppgtt_info(struct seq_file
*m
,
2188 struct drm_i915_private
*dev_priv
)
2190 struct intel_engine_cs
*engine
;
2191 enum intel_engine_id id
;
2193 if (IS_GEN6(dev_priv
))
2194 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2196 for_each_engine(engine
, dev_priv
, id
) {
2197 seq_printf(m
, "%s\n", engine
->name
);
2198 if (IS_GEN7(dev_priv
))
2199 seq_printf(m
, "GFX_MODE: 0x%08x\n",
2200 I915_READ(RING_MODE_GEN7(engine
)));
2201 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n",
2202 I915_READ(RING_PP_DIR_BASE(engine
)));
2203 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n",
2204 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
2205 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n",
2206 I915_READ(RING_PP_DIR_DCLV(engine
)));
2208 if (dev_priv
->mm
.aliasing_ppgtt
) {
2209 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2211 seq_puts(m
, "aliasing PPGTT:\n");
2212 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2214 ppgtt
->debug_dump(ppgtt
, m
);
2217 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2220 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2222 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2223 struct drm_device
*dev
= &dev_priv
->drm
;
2224 struct drm_file
*file
;
2227 mutex_lock(&dev
->filelist_mutex
);
2228 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2232 intel_runtime_pm_get(dev_priv
);
2234 if (INTEL_GEN(dev_priv
) >= 8)
2235 gen8_ppgtt_info(m
, dev_priv
);
2236 else if (INTEL_GEN(dev_priv
) >= 6)
2237 gen6_ppgtt_info(m
, dev_priv
);
2239 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2240 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2241 struct task_struct
*task
;
2243 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2248 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2249 put_task_struct(task
);
2250 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2251 (void *)(unsigned long)m
);
2255 intel_runtime_pm_put(dev_priv
);
2256 mutex_unlock(&dev
->struct_mutex
);
2258 mutex_unlock(&dev
->filelist_mutex
);
2262 static int count_irq_waiters(struct drm_i915_private
*i915
)
2264 struct intel_engine_cs
*engine
;
2265 enum intel_engine_id id
;
2268 for_each_engine(engine
, i915
, id
)
2269 count
+= intel_engine_has_waiter(engine
);
2274 static const char *rps_power_to_str(unsigned int power
)
2276 static const char * const strings
[] = {
2277 [LOW_POWER
] = "low power",
2278 [BETWEEN
] = "mixed",
2279 [HIGH_POWER
] = "high power",
2282 if (power
>= ARRAY_SIZE(strings
) || !strings
[power
])
2285 return strings
[power
];
2288 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2290 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2291 struct drm_device
*dev
= &dev_priv
->drm
;
2292 struct drm_file
*file
;
2294 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2295 seq_printf(m
, "GPU busy? %s [%x]\n",
2296 yesno(dev_priv
->gt
.awake
), dev_priv
->gt
.active_engines
);
2297 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2298 seq_printf(m
, "Frequency requested %d\n",
2299 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
2300 seq_printf(m
, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2301 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2302 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2303 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2304 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2305 seq_printf(m
, " idle:%d, efficient:%d, boost:%d\n",
2306 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
),
2307 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
2308 intel_gpu_freq(dev_priv
, dev_priv
->rps
.boost_freq
));
2310 mutex_lock(&dev
->filelist_mutex
);
2311 spin_lock(&dev_priv
->rps
.client_lock
);
2312 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2313 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2314 struct task_struct
*task
;
2317 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2318 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2319 task
? task
->comm
: "<unknown>",
2320 task
? task
->pid
: -1,
2321 file_priv
->rps
.boosts
,
2322 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2325 seq_printf(m
, "Kernel (anonymous) boosts: %d\n", dev_priv
->rps
.boosts
);
2326 spin_unlock(&dev_priv
->rps
.client_lock
);
2327 mutex_unlock(&dev
->filelist_mutex
);
2329 if (INTEL_GEN(dev_priv
) >= 6 &&
2330 dev_priv
->rps
.enabled
&&
2331 dev_priv
->gt
.active_engines
) {
2333 u32 rpdown
, rpdownei
;
2335 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
2336 rpup
= I915_READ_FW(GEN6_RP_CUR_UP
) & GEN6_RP_EI_MASK
;
2337 rpupei
= I915_READ_FW(GEN6_RP_CUR_UP_EI
) & GEN6_RP_EI_MASK
;
2338 rpdown
= I915_READ_FW(GEN6_RP_CUR_DOWN
) & GEN6_RP_EI_MASK
;
2339 rpdownei
= I915_READ_FW(GEN6_RP_CUR_DOWN_EI
) & GEN6_RP_EI_MASK
;
2340 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
2342 seq_printf(m
, "\nRPS Autotuning (current \"%s\" window):\n",
2343 rps_power_to_str(dev_priv
->rps
.power
));
2344 seq_printf(m
, " Avg. up: %d%% [above threshold? %d%%]\n",
2345 100 * rpup
/ rpupei
,
2346 dev_priv
->rps
.up_threshold
);
2347 seq_printf(m
, " Avg. down: %d%% [below threshold? %d%%]\n",
2348 100 * rpdown
/ rpdownei
,
2349 dev_priv
->rps
.down_threshold
);
2351 seq_puts(m
, "\nRPS Autotuning inactive\n");
2357 static int i915_llc(struct seq_file
*m
, void *data
)
2359 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2360 const bool edram
= INTEL_GEN(dev_priv
) > 8;
2362 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev_priv
)));
2363 seq_printf(m
, "%s: %lluMB\n", edram
? "eDRAM" : "eLLC",
2364 intel_uncore_edram_size(dev_priv
)/1024/1024);
2369 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2371 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2372 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2375 if (!HAS_GUC_UCODE(dev_priv
))
2378 seq_printf(m
, "GuC firmware status:\n");
2379 seq_printf(m
, "\tpath: %s\n",
2380 guc_fw
->guc_fw_path
);
2381 seq_printf(m
, "\tfetch: %s\n",
2382 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2383 seq_printf(m
, "\tload: %s\n",
2384 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2385 seq_printf(m
, "\tversion wanted: %d.%d\n",
2386 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2387 seq_printf(m
, "\tversion found: %d.%d\n",
2388 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2389 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2390 guc_fw
->header_offset
, guc_fw
->header_size
);
2391 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2392 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2393 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2394 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2396 tmp
= I915_READ(GUC_STATUS
);
2398 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2399 seq_printf(m
, "\tBootrom status = 0x%x\n",
2400 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2401 seq_printf(m
, "\tuKernel status = 0x%x\n",
2402 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2403 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2404 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2405 seq_puts(m
, "\nScratch registers:\n");
2406 for (i
= 0; i
< 16; i
++)
2407 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2412 static void i915_guc_client_info(struct seq_file
*m
,
2413 struct drm_i915_private
*dev_priv
,
2414 struct i915_guc_client
*client
)
2416 struct intel_engine_cs
*engine
;
2417 enum intel_engine_id id
;
2420 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2421 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2422 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2423 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2424 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2425 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2427 seq_printf(m
, "\tWork queue full: %u\n", client
->no_wq_space
);
2428 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2429 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2431 for_each_engine(engine
, dev_priv
, id
) {
2432 u64 submissions
= client
->submissions
[id
];
2434 seq_printf(m
, "\tSubmissions: %llu %s\n",
2435 submissions
, engine
->name
);
2437 seq_printf(m
, "\tTotal: %llu\n", tot
);
2440 static int i915_guc_info(struct seq_file
*m
, void *data
)
2442 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2443 struct drm_device
*dev
= &dev_priv
->drm
;
2444 struct intel_guc guc
;
2445 struct i915_guc_client client
= {};
2446 struct intel_engine_cs
*engine
;
2447 enum intel_engine_id id
;
2450 if (!HAS_GUC_SCHED(dev_priv
))
2453 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2456 /* Take a local copy of the GuC data, so we can dump it at leisure */
2457 guc
= dev_priv
->guc
;
2458 if (guc
.execbuf_client
)
2459 client
= *guc
.execbuf_client
;
2461 mutex_unlock(&dev
->struct_mutex
);
2463 seq_printf(m
, "Doorbell map:\n");
2464 seq_printf(m
, "\t%*pb\n", GUC_MAX_DOORBELLS
, guc
.doorbell_bitmap
);
2465 seq_printf(m
, "Doorbell next cacheline: 0x%x\n\n", guc
.db_cacheline
);
2467 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2468 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2469 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2470 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2471 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2473 seq_printf(m
, "\nGuC submissions:\n");
2474 for_each_engine(engine
, dev_priv
, id
) {
2475 u64 submissions
= guc
.submissions
[id
];
2476 total
+= submissions
;
2477 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2478 engine
->name
, submissions
, guc
.last_seqno
[id
]);
2480 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2482 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2483 i915_guc_client_info(m
, dev_priv
, &client
);
2485 /* Add more as required ... */
2490 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2492 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2493 struct drm_i915_gem_object
*obj
;
2496 if (!dev_priv
->guc
.log_vma
)
2499 obj
= dev_priv
->guc
.log_vma
->obj
;
2500 for (pg
= 0; pg
< obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2501 u32
*log
= kmap_atomic(i915_gem_object_get_page(obj
, pg
));
2503 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2504 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2505 *(log
+ i
), *(log
+ i
+ 1),
2506 *(log
+ i
+ 2), *(log
+ i
+ 3));
2516 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2518 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2522 bool enabled
= false;
2524 if (!HAS_PSR(dev_priv
)) {
2525 seq_puts(m
, "PSR not supported\n");
2529 intel_runtime_pm_get(dev_priv
);
2531 mutex_lock(&dev_priv
->psr
.lock
);
2532 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2533 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2534 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2535 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2536 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2537 dev_priv
->psr
.busy_frontbuffer_bits
);
2538 seq_printf(m
, "Re-enable work scheduled: %s\n",
2539 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2541 if (HAS_DDI(dev_priv
))
2542 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2544 for_each_pipe(dev_priv
, pipe
) {
2545 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2546 VLV_EDP_PSR_CURR_STATE_MASK
;
2547 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2548 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2553 seq_printf(m
, "Main link in standby mode: %s\n",
2554 yesno(dev_priv
->psr
.link_standby
));
2556 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2558 if (!HAS_DDI(dev_priv
))
2559 for_each_pipe(dev_priv
, pipe
) {
2560 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2561 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2562 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2567 * VLV/CHV PSR has no kind of performance counter
2568 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2570 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2571 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2572 EDP_PSR_PERF_CNT_MASK
;
2574 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2576 mutex_unlock(&dev_priv
->psr
.lock
);
2578 intel_runtime_pm_put(dev_priv
);
2582 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2584 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2585 struct drm_device
*dev
= &dev_priv
->drm
;
2586 struct intel_connector
*connector
;
2587 struct intel_dp
*intel_dp
= NULL
;
2591 drm_modeset_lock_all(dev
);
2592 for_each_intel_connector(dev
, connector
) {
2593 struct drm_crtc
*crtc
;
2595 if (!connector
->base
.state
->best_encoder
)
2598 crtc
= connector
->base
.state
->crtc
;
2599 if (!crtc
->state
->active
)
2602 if (connector
->base
.connector_type
!= DRM_MODE_CONNECTOR_eDP
)
2605 intel_dp
= enc_to_intel_dp(connector
->base
.state
->best_encoder
);
2607 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2611 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2612 crc
[0], crc
[1], crc
[2],
2613 crc
[3], crc
[4], crc
[5]);
2618 drm_modeset_unlock_all(dev
);
2622 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2624 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2628 if (INTEL_GEN(dev_priv
) < 6)
2631 intel_runtime_pm_get(dev_priv
);
2633 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2634 power
= (power
& 0x1f00) >> 8;
2635 units
= 1000000 / (1 << power
); /* convert to uJ */
2636 power
= I915_READ(MCH_SECP_NRG_STTS
);
2639 intel_runtime_pm_put(dev_priv
);
2641 seq_printf(m
, "%llu", (long long unsigned)power
);
2646 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2648 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2649 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2651 if (!HAS_RUNTIME_PM(dev_priv
))
2652 seq_puts(m
, "Runtime power management not supported\n");
2654 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->gt
.awake
));
2655 seq_printf(m
, "IRQs disabled: %s\n",
2656 yesno(!intel_irqs_enabled(dev_priv
)));
2658 seq_printf(m
, "Usage count: %d\n",
2659 atomic_read(&dev_priv
->drm
.dev
->power
.usage_count
));
2661 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2663 seq_printf(m
, "PCI device power state: %s [%d]\n",
2664 pci_power_name(pdev
->current_state
),
2665 pdev
->current_state
);
2670 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2672 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2673 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2676 mutex_lock(&power_domains
->lock
);
2678 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2679 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2680 struct i915_power_well
*power_well
;
2681 enum intel_display_power_domain power_domain
;
2683 power_well
= &power_domains
->power_wells
[i
];
2684 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2687 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2689 if (!(BIT(power_domain
) & power_well
->domains
))
2692 seq_printf(m
, " %-23s %d\n",
2693 intel_display_power_domain_str(power_domain
),
2694 power_domains
->domain_use_count
[power_domain
]);
2698 mutex_unlock(&power_domains
->lock
);
2703 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2705 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2706 struct intel_csr
*csr
;
2708 if (!HAS_CSR(dev_priv
)) {
2709 seq_puts(m
, "not supported\n");
2713 csr
= &dev_priv
->csr
;
2715 intel_runtime_pm_get(dev_priv
);
2717 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2718 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2720 if (!csr
->dmc_payload
)
2723 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2724 CSR_VERSION_MINOR(csr
->version
));
2726 if (IS_SKYLAKE(dev_priv
) && csr
->version
>= CSR_VERSION(1, 6)) {
2727 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2728 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2729 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2730 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2731 } else if (IS_BROXTON(dev_priv
) && csr
->version
>= CSR_VERSION(1, 4)) {
2732 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2733 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2737 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2738 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2739 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2741 intel_runtime_pm_put(dev_priv
);
2746 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2747 struct drm_display_mode
*mode
)
2751 for (i
= 0; i
< tabs
; i
++)
2754 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2755 mode
->base
.id
, mode
->name
,
2756 mode
->vrefresh
, mode
->clock
,
2757 mode
->hdisplay
, mode
->hsync_start
,
2758 mode
->hsync_end
, mode
->htotal
,
2759 mode
->vdisplay
, mode
->vsync_start
,
2760 mode
->vsync_end
, mode
->vtotal
,
2761 mode
->type
, mode
->flags
);
2764 static void intel_encoder_info(struct seq_file
*m
,
2765 struct intel_crtc
*intel_crtc
,
2766 struct intel_encoder
*intel_encoder
)
2768 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2769 struct drm_device
*dev
= &dev_priv
->drm
;
2770 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2771 struct intel_connector
*intel_connector
;
2772 struct drm_encoder
*encoder
;
2774 encoder
= &intel_encoder
->base
;
2775 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2776 encoder
->base
.id
, encoder
->name
);
2777 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2778 struct drm_connector
*connector
= &intel_connector
->base
;
2779 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2782 drm_get_connector_status_name(connector
->status
));
2783 if (connector
->status
== connector_status_connected
) {
2784 struct drm_display_mode
*mode
= &crtc
->mode
;
2785 seq_printf(m
, ", mode:\n");
2786 intel_seq_print_mode(m
, 2, mode
);
2793 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2795 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2796 struct drm_device
*dev
= &dev_priv
->drm
;
2797 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2798 struct intel_encoder
*intel_encoder
;
2799 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2800 struct drm_framebuffer
*fb
= plane_state
->fb
;
2803 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2804 fb
->base
.id
, plane_state
->src_x
>> 16,
2805 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2807 seq_puts(m
, "\tprimary plane disabled\n");
2808 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2809 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2812 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2814 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2816 seq_printf(m
, "\tfixed mode:\n");
2817 intel_seq_print_mode(m
, 2, mode
);
2820 static void intel_dp_info(struct seq_file
*m
,
2821 struct intel_connector
*intel_connector
)
2823 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2824 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2826 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2827 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2828 if (intel_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)
2829 intel_panel_info(m
, &intel_connector
->panel
);
2831 drm_dp_downstream_debug(m
, intel_dp
->dpcd
, intel_dp
->downstream_ports
,
2835 static void intel_hdmi_info(struct seq_file
*m
,
2836 struct intel_connector
*intel_connector
)
2838 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2839 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2841 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2844 static void intel_lvds_info(struct seq_file
*m
,
2845 struct intel_connector
*intel_connector
)
2847 intel_panel_info(m
, &intel_connector
->panel
);
2850 static void intel_connector_info(struct seq_file
*m
,
2851 struct drm_connector
*connector
)
2853 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2854 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2855 struct drm_display_mode
*mode
;
2857 seq_printf(m
, "connector %d: type %s, status: %s\n",
2858 connector
->base
.id
, connector
->name
,
2859 drm_get_connector_status_name(connector
->status
));
2860 if (connector
->status
== connector_status_connected
) {
2861 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2862 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2863 connector
->display_info
.width_mm
,
2864 connector
->display_info
.height_mm
);
2865 seq_printf(m
, "\tsubpixel order: %s\n",
2866 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2867 seq_printf(m
, "\tCEA rev: %d\n",
2868 connector
->display_info
.cea_rev
);
2871 if (!intel_encoder
|| intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
2874 switch (connector
->connector_type
) {
2875 case DRM_MODE_CONNECTOR_DisplayPort
:
2876 case DRM_MODE_CONNECTOR_eDP
:
2877 intel_dp_info(m
, intel_connector
);
2879 case DRM_MODE_CONNECTOR_LVDS
:
2880 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2881 intel_lvds_info(m
, intel_connector
);
2883 case DRM_MODE_CONNECTOR_HDMIA
:
2884 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
||
2885 intel_encoder
->type
== INTEL_OUTPUT_UNKNOWN
)
2886 intel_hdmi_info(m
, intel_connector
);
2892 seq_printf(m
, "\tmodes:\n");
2893 list_for_each_entry(mode
, &connector
->modes
, head
)
2894 intel_seq_print_mode(m
, 2, mode
);
2897 static bool cursor_active(struct drm_i915_private
*dev_priv
, int pipe
)
2901 if (IS_845G(dev_priv
) || IS_I865G(dev_priv
))
2902 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2904 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2909 static bool cursor_position(struct drm_i915_private
*dev_priv
,
2910 int pipe
, int *x
, int *y
)
2914 pos
= I915_READ(CURPOS(pipe
));
2916 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2917 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2920 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2921 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2924 return cursor_active(dev_priv
, pipe
);
2927 static const char *plane_type(enum drm_plane_type type
)
2930 case DRM_PLANE_TYPE_OVERLAY
:
2932 case DRM_PLANE_TYPE_PRIMARY
:
2934 case DRM_PLANE_TYPE_CURSOR
:
2937 * Deliberately omitting default: to generate compiler warnings
2938 * when a new drm_plane_type gets added.
2945 static const char *plane_rotation(unsigned int rotation
)
2947 static char buf
[48];
2949 * According to doc only one DRM_ROTATE_ is allowed but this
2950 * will print them all to visualize if the values are misused
2952 snprintf(buf
, sizeof(buf
),
2953 "%s%s%s%s%s%s(0x%08x)",
2954 (rotation
& DRM_ROTATE_0
) ? "0 " : "",
2955 (rotation
& DRM_ROTATE_90
) ? "90 " : "",
2956 (rotation
& DRM_ROTATE_180
) ? "180 " : "",
2957 (rotation
& DRM_ROTATE_270
) ? "270 " : "",
2958 (rotation
& DRM_REFLECT_X
) ? "FLIPX " : "",
2959 (rotation
& DRM_REFLECT_Y
) ? "FLIPY " : "",
2965 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2967 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
2968 struct drm_device
*dev
= &dev_priv
->drm
;
2969 struct intel_plane
*intel_plane
;
2971 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2972 struct drm_plane_state
*state
;
2973 struct drm_plane
*plane
= &intel_plane
->base
;
2976 if (!plane
->state
) {
2977 seq_puts(m
, "plane->state is NULL!\n");
2981 state
= plane
->state
;
2984 format_name
= drm_get_format_name(state
->fb
->pixel_format
);
2986 format_name
= kstrdup("N/A", GFP_KERNEL
);
2989 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
2991 plane_type(intel_plane
->base
.type
),
2992 state
->crtc_x
, state
->crtc_y
,
2993 state
->crtc_w
, state
->crtc_h
,
2994 (state
->src_x
>> 16),
2995 ((state
->src_x
& 0xffff) * 15625) >> 10,
2996 (state
->src_y
>> 16),
2997 ((state
->src_y
& 0xffff) * 15625) >> 10,
2998 (state
->src_w
>> 16),
2999 ((state
->src_w
& 0xffff) * 15625) >> 10,
3000 (state
->src_h
>> 16),
3001 ((state
->src_h
& 0xffff) * 15625) >> 10,
3003 plane_rotation(state
->rotation
));
3009 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3011 struct intel_crtc_state
*pipe_config
;
3012 int num_scalers
= intel_crtc
->num_scalers
;
3015 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3017 /* Not all platformas have a scaler */
3019 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3021 pipe_config
->scaler_state
.scaler_users
,
3022 pipe_config
->scaler_state
.scaler_id
);
3024 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3025 struct intel_scaler
*sc
=
3026 &pipe_config
->scaler_state
.scalers
[i
];
3028 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3029 i
, yesno(sc
->in_use
), sc
->mode
);
3033 seq_puts(m
, "\tNo scalers available on this platform\n");
3037 static int i915_display_info(struct seq_file
*m
, void *unused
)
3039 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3040 struct drm_device
*dev
= &dev_priv
->drm
;
3041 struct intel_crtc
*crtc
;
3042 struct drm_connector
*connector
;
3044 intel_runtime_pm_get(dev_priv
);
3045 drm_modeset_lock_all(dev
);
3046 seq_printf(m
, "CRTC info\n");
3047 seq_printf(m
, "---------\n");
3048 for_each_intel_crtc(dev
, crtc
) {
3050 struct intel_crtc_state
*pipe_config
;
3053 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3055 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3056 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3057 yesno(pipe_config
->base
.active
),
3058 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3059 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3061 if (pipe_config
->base
.active
) {
3062 intel_crtc_info(m
, crtc
);
3064 active
= cursor_position(dev_priv
, crtc
->pipe
, &x
, &y
);
3065 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3066 yesno(crtc
->cursor_base
),
3067 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3068 crtc
->base
.cursor
->state
->crtc_h
,
3069 crtc
->cursor_addr
, yesno(active
));
3070 intel_scaler_info(m
, crtc
);
3071 intel_plane_info(m
, crtc
);
3074 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3075 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3076 yesno(!crtc
->pch_fifo_underrun_disabled
));
3079 seq_printf(m
, "\n");
3080 seq_printf(m
, "Connector info\n");
3081 seq_printf(m
, "--------------\n");
3082 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3083 intel_connector_info(m
, connector
);
3085 drm_modeset_unlock_all(dev
);
3086 intel_runtime_pm_put(dev_priv
);
3091 static int i915_engine_info(struct seq_file
*m
, void *unused
)
3093 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3094 struct intel_engine_cs
*engine
;
3095 enum intel_engine_id id
;
3097 for_each_engine(engine
, dev_priv
, id
) {
3098 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
3099 struct drm_i915_gem_request
*rq
;
3103 seq_printf(m
, "%s\n", engine
->name
);
3104 seq_printf(m
, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3105 intel_engine_get_seqno(engine
),
3106 engine
->last_submitted_seqno
,
3107 engine
->hangcheck
.seqno
,
3108 engine
->hangcheck
.score
);
3112 seq_printf(m
, "\tRequests:\n");
3114 rq
= list_first_entry(&engine
->request_list
,
3115 struct drm_i915_gem_request
, link
);
3116 if (&rq
->link
!= &engine
->request_list
)
3117 print_request(m
, rq
, "\t\tfirst ");
3119 rq
= list_last_entry(&engine
->request_list
,
3120 struct drm_i915_gem_request
, link
);
3121 if (&rq
->link
!= &engine
->request_list
)
3122 print_request(m
, rq
, "\t\tlast ");
3124 rq
= i915_gem_find_active_request(engine
);
3126 print_request(m
, rq
, "\t\tactive ");
3128 "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3129 rq
->head
, rq
->postfix
, rq
->tail
,
3130 rq
->batch
? upper_32_bits(rq
->batch
->node
.start
) : ~0u,
3131 rq
->batch
? lower_32_bits(rq
->batch
->node
.start
) : ~0u);
3134 seq_printf(m
, "\tRING_START: 0x%08x [0x%08x]\n",
3135 I915_READ(RING_START(engine
->mmio_base
)),
3136 rq
? i915_ggtt_offset(rq
->ring
->vma
) : 0);
3137 seq_printf(m
, "\tRING_HEAD: 0x%08x [0x%08x]\n",
3138 I915_READ(RING_HEAD(engine
->mmio_base
)) & HEAD_ADDR
,
3139 rq
? rq
->ring
->head
: 0);
3140 seq_printf(m
, "\tRING_TAIL: 0x%08x [0x%08x]\n",
3141 I915_READ(RING_TAIL(engine
->mmio_base
)) & TAIL_ADDR
,
3142 rq
? rq
->ring
->tail
: 0);
3143 seq_printf(m
, "\tRING_CTL: 0x%08x [%s]\n",
3144 I915_READ(RING_CTL(engine
->mmio_base
)),
3145 I915_READ(RING_CTL(engine
->mmio_base
)) & (RING_WAIT
| RING_WAIT_SEMAPHORE
) ? "waiting" : "");
3149 addr
= intel_engine_get_active_head(engine
);
3150 seq_printf(m
, "\tACTHD: 0x%08x_%08x\n",
3151 upper_32_bits(addr
), lower_32_bits(addr
));
3152 addr
= intel_engine_get_last_batch_head(engine
);
3153 seq_printf(m
, "\tBBADDR: 0x%08x_%08x\n",
3154 upper_32_bits(addr
), lower_32_bits(addr
));
3156 if (i915
.enable_execlists
) {
3157 u32 ptr
, read
, write
;
3159 seq_printf(m
, "\tExeclist status: 0x%08x %08x\n",
3160 I915_READ(RING_EXECLIST_STATUS_LO(engine
)),
3161 I915_READ(RING_EXECLIST_STATUS_HI(engine
)));
3163 ptr
= I915_READ(RING_CONTEXT_STATUS_PTR(engine
));
3164 read
= GEN8_CSB_READ_PTR(ptr
);
3165 write
= GEN8_CSB_WRITE_PTR(ptr
);
3166 seq_printf(m
, "\tExeclist CSB read %d, write %d\n",
3168 if (read
>= GEN8_CSB_ENTRIES
)
3170 if (write
>= GEN8_CSB_ENTRIES
)
3173 write
+= GEN8_CSB_ENTRIES
;
3174 while (read
< write
) {
3175 unsigned int idx
= ++read
% GEN8_CSB_ENTRIES
;
3177 seq_printf(m
, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3179 I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine
, idx
)),
3180 I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine
, idx
)));
3184 rq
= READ_ONCE(engine
->execlist_port
[0].request
);
3186 print_request(m
, rq
, "\t\tELSP[0] ");
3188 seq_printf(m
, "\t\tELSP[0] idle\n");
3189 rq
= READ_ONCE(engine
->execlist_port
[1].request
);
3191 print_request(m
, rq
, "\t\tELSP[1] ");
3193 seq_printf(m
, "\t\tELSP[1] idle\n");
3195 } else if (INTEL_GEN(dev_priv
) > 6) {
3196 seq_printf(m
, "\tPP_DIR_BASE: 0x%08x\n",
3197 I915_READ(RING_PP_DIR_BASE(engine
)));
3198 seq_printf(m
, "\tPP_DIR_BASE_READ: 0x%08x\n",
3199 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
3200 seq_printf(m
, "\tPP_DIR_DCLV: 0x%08x\n",
3201 I915_READ(RING_PP_DIR_DCLV(engine
)));
3204 spin_lock(&b
->lock
);
3205 for (rb
= rb_first(&b
->waiters
); rb
; rb
= rb_next(rb
)) {
3206 struct intel_wait
*w
= container_of(rb
, typeof(*w
), node
);
3208 seq_printf(m
, "\t%s [%d] waiting for %x\n",
3209 w
->tsk
->comm
, w
->tsk
->pid
, w
->seqno
);
3211 spin_unlock(&b
->lock
);
3219 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3221 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3222 struct drm_device
*dev
= &dev_priv
->drm
;
3223 struct intel_engine_cs
*engine
;
3224 int num_rings
= INTEL_INFO(dev_priv
)->num_rings
;
3225 enum intel_engine_id id
;
3228 if (!i915
.semaphores
) {
3229 seq_puts(m
, "Semaphores are disabled\n");
3233 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3236 intel_runtime_pm_get(dev_priv
);
3238 if (IS_BROADWELL(dev_priv
)) {
3242 page
= i915_gem_object_get_page(dev_priv
->semaphore
->obj
, 0);
3244 seqno
= (uint64_t *)kmap_atomic(page
);
3245 for_each_engine(engine
, dev_priv
, id
) {
3248 seq_printf(m
, "%s\n", engine
->name
);
3250 seq_puts(m
, " Last signal:");
3251 for (j
= 0; j
< num_rings
; j
++) {
3252 offset
= id
* I915_NUM_ENGINES
+ j
;
3253 seq_printf(m
, "0x%08llx (0x%02llx) ",
3254 seqno
[offset
], offset
* 8);
3258 seq_puts(m
, " Last wait: ");
3259 for (j
= 0; j
< num_rings
; j
++) {
3260 offset
= id
+ (j
* I915_NUM_ENGINES
);
3261 seq_printf(m
, "0x%08llx (0x%02llx) ",
3262 seqno
[offset
], offset
* 8);
3267 kunmap_atomic(seqno
);
3269 seq_puts(m
, " Last signal:");
3270 for_each_engine(engine
, dev_priv
, id
)
3271 for (j
= 0; j
< num_rings
; j
++)
3272 seq_printf(m
, "0x%08x\n",
3273 I915_READ(engine
->semaphore
.mbox
.signal
[j
]));
3277 seq_puts(m
, "\nSync seqno:\n");
3278 for_each_engine(engine
, dev_priv
, id
) {
3279 for (j
= 0; j
< num_rings
; j
++)
3280 seq_printf(m
, " 0x%08x ",
3281 engine
->semaphore
.sync_seqno
[j
]);
3286 intel_runtime_pm_put(dev_priv
);
3287 mutex_unlock(&dev
->struct_mutex
);
3291 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3293 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3294 struct drm_device
*dev
= &dev_priv
->drm
;
3297 drm_modeset_lock_all(dev
);
3298 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3299 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3301 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3302 seq_printf(m
, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3303 pll
->config
.crtc_mask
, pll
->active_mask
, yesno(pll
->on
));
3304 seq_printf(m
, " tracked hardware state:\n");
3305 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3306 seq_printf(m
, " dpll_md: 0x%08x\n",
3307 pll
->config
.hw_state
.dpll_md
);
3308 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3309 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3310 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3312 drm_modeset_unlock_all(dev
);
3317 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3321 struct intel_engine_cs
*engine
;
3322 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3323 struct drm_device
*dev
= &dev_priv
->drm
;
3324 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3325 enum intel_engine_id id
;
3327 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3331 intel_runtime_pm_get(dev_priv
);
3333 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3334 for_each_engine(engine
, dev_priv
, id
)
3335 seq_printf(m
, "HW whitelist count for %s: %d\n",
3336 engine
->name
, workarounds
->hw_whitelist_count
[id
]);
3337 for (i
= 0; i
< workarounds
->count
; ++i
) {
3339 u32 mask
, value
, read
;
3342 addr
= workarounds
->reg
[i
].addr
;
3343 mask
= workarounds
->reg
[i
].mask
;
3344 value
= workarounds
->reg
[i
].value
;
3345 read
= I915_READ(addr
);
3346 ok
= (value
& mask
) == (read
& mask
);
3347 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3348 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3351 intel_runtime_pm_put(dev_priv
);
3352 mutex_unlock(&dev
->struct_mutex
);
3357 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3359 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3360 struct drm_device
*dev
= &dev_priv
->drm
;
3361 struct skl_ddb_allocation
*ddb
;
3362 struct skl_ddb_entry
*entry
;
3366 if (INTEL_GEN(dev_priv
) < 9)
3369 drm_modeset_lock_all(dev
);
3371 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3373 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3375 for_each_pipe(dev_priv
, pipe
) {
3376 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3378 for_each_plane(dev_priv
, pipe
, plane
) {
3379 entry
= &ddb
->plane
[pipe
][plane
];
3380 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3381 entry
->start
, entry
->end
,
3382 skl_ddb_entry_size(entry
));
3385 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3386 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3387 entry
->end
, skl_ddb_entry_size(entry
));
3390 drm_modeset_unlock_all(dev
);
3395 static void drrs_status_per_crtc(struct seq_file
*m
,
3396 struct drm_device
*dev
,
3397 struct intel_crtc
*intel_crtc
)
3399 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3400 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3402 struct drm_connector
*connector
;
3404 drm_for_each_connector(connector
, dev
) {
3405 if (connector
->state
->crtc
!= &intel_crtc
->base
)
3408 seq_printf(m
, "%s:\n", connector
->name
);
3411 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3412 seq_puts(m
, "\tVBT: DRRS_type: Static");
3413 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3414 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3415 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3416 seq_puts(m
, "\tVBT: DRRS_type: None");
3418 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3420 seq_puts(m
, "\n\n");
3422 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3423 struct intel_panel
*panel
;
3425 mutex_lock(&drrs
->mutex
);
3426 /* DRRS Supported */
3427 seq_puts(m
, "\tDRRS Supported: Yes\n");
3429 /* disable_drrs() will make drrs->dp NULL */
3431 seq_puts(m
, "Idleness DRRS: Disabled");
3432 mutex_unlock(&drrs
->mutex
);
3436 panel
= &drrs
->dp
->attached_connector
->panel
;
3437 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3438 drrs
->busy_frontbuffer_bits
);
3440 seq_puts(m
, "\n\t\t");
3441 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3442 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3443 vrefresh
= panel
->fixed_mode
->vrefresh
;
3444 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3445 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3446 vrefresh
= panel
->downclock_mode
->vrefresh
;
3448 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3449 drrs
->refresh_rate_type
);
3450 mutex_unlock(&drrs
->mutex
);
3453 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3455 seq_puts(m
, "\n\t\t");
3456 mutex_unlock(&drrs
->mutex
);
3458 /* DRRS not supported. Print the VBT parameter*/
3459 seq_puts(m
, "\tDRRS Supported : No");
3464 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3466 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3467 struct drm_device
*dev
= &dev_priv
->drm
;
3468 struct intel_crtc
*intel_crtc
;
3469 int active_crtc_cnt
= 0;
3471 drm_modeset_lock_all(dev
);
3472 for_each_intel_crtc(dev
, intel_crtc
) {
3473 if (intel_crtc
->base
.state
->active
) {
3475 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3477 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3480 drm_modeset_unlock_all(dev
);
3482 if (!active_crtc_cnt
)
3483 seq_puts(m
, "No active crtc found\n");
3488 struct pipe_crc_info
{
3490 struct drm_i915_private
*dev_priv
;
3494 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3496 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
3497 struct drm_device
*dev
= &dev_priv
->drm
;
3498 struct intel_encoder
*intel_encoder
;
3499 struct intel_digital_port
*intel_dig_port
;
3500 struct drm_connector
*connector
;
3502 drm_modeset_lock_all(dev
);
3503 drm_for_each_connector(connector
, dev
) {
3504 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_DisplayPort
)
3507 intel_encoder
= intel_attached_encoder(connector
);
3508 if (!intel_encoder
|| intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
3511 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
3512 if (!intel_dig_port
->dp
.can_mst
)
3515 seq_printf(m
, "MST Source Port %c\n",
3516 port_name(intel_dig_port
->port
));
3517 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3519 drm_modeset_unlock_all(dev
);
3523 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3525 struct pipe_crc_info
*info
= inode
->i_private
;
3526 struct drm_i915_private
*dev_priv
= info
->dev_priv
;
3527 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3529 if (info
->pipe
>= INTEL_INFO(dev_priv
)->num_pipes
)
3532 spin_lock_irq(&pipe_crc
->lock
);
3534 if (pipe_crc
->opened
) {
3535 spin_unlock_irq(&pipe_crc
->lock
);
3536 return -EBUSY
; /* already open */
3539 pipe_crc
->opened
= true;
3540 filep
->private_data
= inode
->i_private
;
3542 spin_unlock_irq(&pipe_crc
->lock
);
3547 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3549 struct pipe_crc_info
*info
= inode
->i_private
;
3550 struct drm_i915_private
*dev_priv
= info
->dev_priv
;
3551 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3553 spin_lock_irq(&pipe_crc
->lock
);
3554 pipe_crc
->opened
= false;
3555 spin_unlock_irq(&pipe_crc
->lock
);
3560 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3561 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3562 /* account for \'0' */
3563 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3565 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3567 assert_spin_locked(&pipe_crc
->lock
);
3568 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3569 INTEL_PIPE_CRC_ENTRIES_NR
);
3573 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3576 struct pipe_crc_info
*info
= filep
->private_data
;
3577 struct drm_i915_private
*dev_priv
= info
->dev_priv
;
3578 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3579 char buf
[PIPE_CRC_BUFFER_LEN
];
3584 * Don't allow user space to provide buffers not big enough to hold
3587 if (count
< PIPE_CRC_LINE_LEN
)
3590 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3593 /* nothing to read */
3594 spin_lock_irq(&pipe_crc
->lock
);
3595 while (pipe_crc_data_count(pipe_crc
) == 0) {
3598 if (filep
->f_flags
& O_NONBLOCK
) {
3599 spin_unlock_irq(&pipe_crc
->lock
);
3603 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3604 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3606 spin_unlock_irq(&pipe_crc
->lock
);
3611 /* We now have one or more entries to read */
3612 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3615 while (n_entries
> 0) {
3616 struct intel_pipe_crc_entry
*entry
=
3617 &pipe_crc
->entries
[pipe_crc
->tail
];
3619 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3620 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3623 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3624 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3626 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3627 "%8u %8x %8x %8x %8x %8x\n",
3628 entry
->frame
, entry
->crc
[0],
3629 entry
->crc
[1], entry
->crc
[2],
3630 entry
->crc
[3], entry
->crc
[4]);
3632 spin_unlock_irq(&pipe_crc
->lock
);
3634 if (copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
))
3637 user_buf
+= PIPE_CRC_LINE_LEN
;
3640 spin_lock_irq(&pipe_crc
->lock
);
3643 spin_unlock_irq(&pipe_crc
->lock
);
3648 static const struct file_operations i915_pipe_crc_fops
= {
3649 .owner
= THIS_MODULE
,
3650 .open
= i915_pipe_crc_open
,
3651 .read
= i915_pipe_crc_read
,
3652 .release
= i915_pipe_crc_release
,
3655 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3657 .name
= "i915_pipe_A_crc",
3661 .name
= "i915_pipe_B_crc",
3665 .name
= "i915_pipe_C_crc",
3670 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3673 struct drm_i915_private
*dev_priv
= to_i915(minor
->dev
);
3675 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3677 info
->dev_priv
= dev_priv
;
3678 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3679 &i915_pipe_crc_fops
);
3683 return drm_add_fake_info_node(minor
, ent
, info
);
3686 static const char * const pipe_crc_sources
[] = {
3699 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3701 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3702 return pipe_crc_sources
[source
];
3705 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3707 struct drm_i915_private
*dev_priv
= m
->private;
3710 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3711 seq_printf(m
, "%c %s\n", pipe_name(i
),
3712 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3717 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3719 return single_open(file
, display_crc_ctl_show
, inode
->i_private
);
3722 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3725 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3726 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3729 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3730 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3732 case INTEL_PIPE_CRC_SOURCE_NONE
:
3742 static int i9xx_pipe_crc_auto_source(struct drm_i915_private
*dev_priv
,
3744 enum intel_pipe_crc_source
*source
)
3746 struct drm_device
*dev
= &dev_priv
->drm
;
3747 struct intel_encoder
*encoder
;
3748 struct intel_crtc
*crtc
;
3749 struct intel_digital_port
*dig_port
;
3752 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3754 drm_modeset_lock_all(dev
);
3755 for_each_intel_encoder(dev
, encoder
) {
3756 if (!encoder
->base
.crtc
)
3759 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3761 if (crtc
->pipe
!= pipe
)
3764 switch (encoder
->type
) {
3765 case INTEL_OUTPUT_TVOUT
:
3766 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3768 case INTEL_OUTPUT_DP
:
3769 case INTEL_OUTPUT_EDP
:
3770 dig_port
= enc_to_dig_port(&encoder
->base
);
3771 switch (dig_port
->port
) {
3773 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3776 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3779 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3782 WARN(1, "nonexisting DP port %c\n",
3783 port_name(dig_port
->port
));
3791 drm_modeset_unlock_all(dev
);
3796 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv
,
3798 enum intel_pipe_crc_source
*source
,
3801 bool need_stable_symbols
= false;
3803 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3804 int ret
= i9xx_pipe_crc_auto_source(dev_priv
, pipe
, source
);
3810 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3811 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3813 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3814 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3815 need_stable_symbols
= true;
3817 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3818 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3819 need_stable_symbols
= true;
3821 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3822 if (!IS_CHERRYVIEW(dev_priv
))
3824 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3825 need_stable_symbols
= true;
3827 case INTEL_PIPE_CRC_SOURCE_NONE
:
3835 * When the pipe CRC tap point is after the transcoders we need
3836 * to tweak symbol-level features to produce a deterministic series of
3837 * symbols for a given frame. We need to reset those features only once
3838 * a frame (instead of every nth symbol):
3839 * - DC-balance: used to ensure a better clock recovery from the data
3841 * - DisplayPort scrambling: used for EMI reduction
3843 if (need_stable_symbols
) {
3844 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3846 tmp
|= DC_BALANCE_RESET_VLV
;
3849 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3852 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3855 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3860 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3866 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv
,
3868 enum intel_pipe_crc_source
*source
,
3871 bool need_stable_symbols
= false;
3873 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3874 int ret
= i9xx_pipe_crc_auto_source(dev_priv
, pipe
, source
);
3880 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3881 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3883 case INTEL_PIPE_CRC_SOURCE_TV
:
3884 if (!SUPPORTS_TV(dev_priv
))
3886 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3888 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3889 if (!IS_G4X(dev_priv
))
3891 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3892 need_stable_symbols
= true;
3894 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3895 if (!IS_G4X(dev_priv
))
3897 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3898 need_stable_symbols
= true;
3900 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3901 if (!IS_G4X(dev_priv
))
3903 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3904 need_stable_symbols
= true;
3906 case INTEL_PIPE_CRC_SOURCE_NONE
:
3914 * When the pipe CRC tap point is after the transcoders we need
3915 * to tweak symbol-level features to produce a deterministic series of
3916 * symbols for a given frame. We need to reset those features only once
3917 * a frame (instead of every nth symbol):
3918 * - DC-balance: used to ensure a better clock recovery from the data
3920 * - DisplayPort scrambling: used for EMI reduction
3922 if (need_stable_symbols
) {
3923 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3925 WARN_ON(!IS_G4X(dev_priv
));
3927 I915_WRITE(PORT_DFT_I9XX
,
3928 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3931 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3933 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3935 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3941 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private
*dev_priv
,
3944 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3948 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3951 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3954 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3959 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3960 tmp
&= ~DC_BALANCE_RESET_VLV
;
3961 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3965 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private
*dev_priv
,
3968 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3971 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3973 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3974 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3976 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3977 I915_WRITE(PORT_DFT_I9XX
,
3978 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3982 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3985 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3986 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3989 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3990 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3992 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3993 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3995 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3996 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3998 case INTEL_PIPE_CRC_SOURCE_NONE
:
4008 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private
*dev_priv
,
4011 struct drm_device
*dev
= &dev_priv
->drm
;
4012 struct intel_crtc
*crtc
=
4013 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
4014 struct intel_crtc_state
*pipe_config
;
4015 struct drm_atomic_state
*state
;
4018 drm_modeset_lock_all(dev
);
4019 state
= drm_atomic_state_alloc(dev
);
4025 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
4026 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
4027 if (IS_ERR(pipe_config
)) {
4028 ret
= PTR_ERR(pipe_config
);
4032 pipe_config
->pch_pfit
.force_thru
= enable
;
4033 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
4034 pipe_config
->pch_pfit
.enabled
!= enable
)
4035 pipe_config
->base
.connectors_changed
= true;
4037 ret
= drm_atomic_commit(state
);
4039 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
4040 drm_modeset_unlock_all(dev
);
4041 drm_atomic_state_put(state
);
4044 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv
,
4046 enum intel_pipe_crc_source
*source
,
4049 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
4050 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
4053 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
4054 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
4056 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
4057 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
4059 case INTEL_PIPE_CRC_SOURCE_PF
:
4060 if (IS_HASWELL(dev_priv
) && pipe
== PIPE_A
)
4061 hsw_trans_edp_pipe_A_crc_wa(dev_priv
, true);
4063 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
4065 case INTEL_PIPE_CRC_SOURCE_NONE
:
4075 static int pipe_crc_set_source(struct drm_i915_private
*dev_priv
,
4077 enum intel_pipe_crc_source source
)
4079 struct drm_device
*dev
= &dev_priv
->drm
;
4080 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4081 struct intel_crtc
*crtc
=
4082 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
4083 enum intel_display_power_domain power_domain
;
4084 u32 val
= 0; /* shut up gcc */
4087 if (pipe_crc
->source
== source
)
4090 /* forbid changing the source without going back to 'none' */
4091 if (pipe_crc
->source
&& source
)
4094 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4095 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4096 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4100 if (IS_GEN2(dev_priv
))
4101 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4102 else if (INTEL_GEN(dev_priv
) < 5)
4103 ret
= i9xx_pipe_crc_ctl_reg(dev_priv
, pipe
, &source
, &val
);
4104 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4105 ret
= vlv_pipe_crc_ctl_reg(dev_priv
, pipe
, &source
, &val
);
4106 else if (IS_GEN5(dev_priv
) || IS_GEN6(dev_priv
))
4107 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4109 ret
= ivb_pipe_crc_ctl_reg(dev_priv
, pipe
, &source
, &val
);
4114 /* none -> real source transition */
4116 struct intel_pipe_crc_entry
*entries
;
4118 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4119 pipe_name(pipe
), pipe_crc_source_name(source
));
4121 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4122 sizeof(pipe_crc
->entries
[0]),
4130 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4131 * enabled and disabled dynamically based on package C states,
4132 * user space can't make reliable use of the CRCs, so let's just
4133 * completely disable it.
4135 hsw_disable_ips(crtc
);
4137 spin_lock_irq(&pipe_crc
->lock
);
4138 kfree(pipe_crc
->entries
);
4139 pipe_crc
->entries
= entries
;
4142 spin_unlock_irq(&pipe_crc
->lock
);
4145 pipe_crc
->source
= source
;
4147 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4148 POSTING_READ(PIPE_CRC_CTL(pipe
));
4150 /* real source -> none transition */
4151 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4152 struct intel_pipe_crc_entry
*entries
;
4153 struct intel_crtc
*crtc
=
4154 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4156 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4159 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4160 if (crtc
->base
.state
->active
)
4161 intel_wait_for_vblank(dev
, pipe
);
4162 drm_modeset_unlock(&crtc
->base
.mutex
);
4164 spin_lock_irq(&pipe_crc
->lock
);
4165 entries
= pipe_crc
->entries
;
4166 pipe_crc
->entries
= NULL
;
4169 spin_unlock_irq(&pipe_crc
->lock
);
4173 if (IS_G4X(dev_priv
))
4174 g4x_undo_pipe_scramble_reset(dev_priv
, pipe
);
4175 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4176 vlv_undo_pipe_scramble_reset(dev_priv
, pipe
);
4177 else if (IS_HASWELL(dev_priv
) && pipe
== PIPE_A
)
4178 hsw_trans_edp_pipe_A_crc_wa(dev_priv
, false);
4180 hsw_enable_ips(crtc
);
4186 intel_display_power_put(dev_priv
, power_domain
);
4192 * Parse pipe CRC command strings:
4193 * command: wsp* object wsp+ name wsp+ source wsp*
4196 * source: (none | plane1 | plane2 | pf)
4197 * wsp: (#0x20 | #0x9 | #0xA)+
4200 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4201 * "pipe A none" -> Stop CRC
4203 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4210 /* skip leading white space */
4211 buf
= skip_spaces(buf
);
4213 break; /* end of buffer */
4215 /* find end of word */
4216 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4219 if (n_words
== max_words
) {
4220 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4222 return -EINVAL
; /* ran out of words[] before bytes */
4227 words
[n_words
++] = buf
;
4234 enum intel_pipe_crc_object
{
4235 PIPE_CRC_OBJECT_PIPE
,
4238 static const char * const pipe_crc_objects
[] = {
4243 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4247 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4248 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4256 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4258 const char name
= buf
[0];
4260 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4269 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4273 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4274 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4282 static int display_crc_ctl_parse(struct drm_i915_private
*dev_priv
,
4283 char *buf
, size_t len
)
4287 char *words
[N_WORDS
];
4289 enum intel_pipe_crc_object object
;
4290 enum intel_pipe_crc_source source
;
4292 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4293 if (n_words
!= N_WORDS
) {
4294 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4299 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4300 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4304 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4305 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4309 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4310 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4314 return pipe_crc_set_source(dev_priv
, pipe
, source
);
4317 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4318 size_t len
, loff_t
*offp
)
4320 struct seq_file
*m
= file
->private_data
;
4321 struct drm_i915_private
*dev_priv
= m
->private;
4328 if (len
> PAGE_SIZE
- 1) {
4329 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4334 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4338 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4344 ret
= display_crc_ctl_parse(dev_priv
, tmpbuf
, len
);
4355 static const struct file_operations i915_display_crc_ctl_fops
= {
4356 .owner
= THIS_MODULE
,
4357 .open
= display_crc_ctl_open
,
4359 .llseek
= seq_lseek
,
4360 .release
= single_release
,
4361 .write
= display_crc_ctl_write
4364 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4365 const char __user
*ubuf
,
4366 size_t len
, loff_t
*offp
)
4370 struct drm_device
*dev
;
4371 struct drm_connector
*connector
;
4372 struct list_head
*connector_list
;
4373 struct intel_dp
*intel_dp
;
4376 dev
= ((struct seq_file
*)file
->private_data
)->private;
4378 connector_list
= &dev
->mode_config
.connector_list
;
4383 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4387 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4392 input_buffer
[len
] = '\0';
4393 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4395 list_for_each_entry(connector
, connector_list
, head
) {
4396 if (connector
->connector_type
!=
4397 DRM_MODE_CONNECTOR_DisplayPort
)
4400 if (connector
->status
== connector_status_connected
&&
4401 connector
->encoder
!= NULL
) {
4402 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4403 status
= kstrtoint(input_buffer
, 10, &val
);
4406 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4407 /* To prevent erroneous activation of the compliance
4408 * testing code, only accept an actual value of 1 here
4411 intel_dp
->compliance_test_active
= 1;
4413 intel_dp
->compliance_test_active
= 0;
4417 kfree(input_buffer
);
4425 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4427 struct drm_device
*dev
= m
->private;
4428 struct drm_connector
*connector
;
4429 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4430 struct intel_dp
*intel_dp
;
4432 list_for_each_entry(connector
, connector_list
, head
) {
4433 if (connector
->connector_type
!=
4434 DRM_MODE_CONNECTOR_DisplayPort
)
4437 if (connector
->status
== connector_status_connected
&&
4438 connector
->encoder
!= NULL
) {
4439 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4440 if (intel_dp
->compliance_test_active
)
4451 static int i915_displayport_test_active_open(struct inode
*inode
,
4454 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4456 return single_open(file
, i915_displayport_test_active_show
,
4460 static const struct file_operations i915_displayport_test_active_fops
= {
4461 .owner
= THIS_MODULE
,
4462 .open
= i915_displayport_test_active_open
,
4464 .llseek
= seq_lseek
,
4465 .release
= single_release
,
4466 .write
= i915_displayport_test_active_write
4469 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4471 struct drm_device
*dev
= m
->private;
4472 struct drm_connector
*connector
;
4473 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4474 struct intel_dp
*intel_dp
;
4476 list_for_each_entry(connector
, connector_list
, head
) {
4477 if (connector
->connector_type
!=
4478 DRM_MODE_CONNECTOR_DisplayPort
)
4481 if (connector
->status
== connector_status_connected
&&
4482 connector
->encoder
!= NULL
) {
4483 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4484 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4491 static int i915_displayport_test_data_open(struct inode
*inode
,
4494 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4496 return single_open(file
, i915_displayport_test_data_show
,
4500 static const struct file_operations i915_displayport_test_data_fops
= {
4501 .owner
= THIS_MODULE
,
4502 .open
= i915_displayport_test_data_open
,
4504 .llseek
= seq_lseek
,
4505 .release
= single_release
4508 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4510 struct drm_device
*dev
= m
->private;
4511 struct drm_connector
*connector
;
4512 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4513 struct intel_dp
*intel_dp
;
4515 list_for_each_entry(connector
, connector_list
, head
) {
4516 if (connector
->connector_type
!=
4517 DRM_MODE_CONNECTOR_DisplayPort
)
4520 if (connector
->status
== connector_status_connected
&&
4521 connector
->encoder
!= NULL
) {
4522 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4523 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4531 static int i915_displayport_test_type_open(struct inode
*inode
,
4534 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4536 return single_open(file
, i915_displayport_test_type_show
,
4540 static const struct file_operations i915_displayport_test_type_fops
= {
4541 .owner
= THIS_MODULE
,
4542 .open
= i915_displayport_test_type_open
,
4544 .llseek
= seq_lseek
,
4545 .release
= single_release
4548 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4550 struct drm_i915_private
*dev_priv
= m
->private;
4551 struct drm_device
*dev
= &dev_priv
->drm
;
4555 if (IS_CHERRYVIEW(dev_priv
))
4557 else if (IS_VALLEYVIEW(dev_priv
))
4560 num_levels
= ilk_wm_max_level(dev_priv
) + 1;
4562 drm_modeset_lock_all(dev
);
4564 for (level
= 0; level
< num_levels
; level
++) {
4565 unsigned int latency
= wm
[level
];
4568 * - WM1+ latency values in 0.5us units
4569 * - latencies are in us on gen9/vlv/chv
4571 if (INTEL_GEN(dev_priv
) >= 9 || IS_VALLEYVIEW(dev_priv
) ||
4572 IS_CHERRYVIEW(dev_priv
))
4577 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4578 level
, wm
[level
], latency
/ 10, latency
% 10);
4581 drm_modeset_unlock_all(dev
);
4584 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4586 struct drm_i915_private
*dev_priv
= m
->private;
4587 const uint16_t *latencies
;
4589 if (INTEL_GEN(dev_priv
) >= 9)
4590 latencies
= dev_priv
->wm
.skl_latency
;
4592 latencies
= dev_priv
->wm
.pri_latency
;
4594 wm_latency_show(m
, latencies
);
4599 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4601 struct drm_i915_private
*dev_priv
= m
->private;
4602 const uint16_t *latencies
;
4604 if (INTEL_GEN(dev_priv
) >= 9)
4605 latencies
= dev_priv
->wm
.skl_latency
;
4607 latencies
= dev_priv
->wm
.spr_latency
;
4609 wm_latency_show(m
, latencies
);
4614 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4616 struct drm_i915_private
*dev_priv
= m
->private;
4617 const uint16_t *latencies
;
4619 if (INTEL_GEN(dev_priv
) >= 9)
4620 latencies
= dev_priv
->wm
.skl_latency
;
4622 latencies
= dev_priv
->wm
.cur_latency
;
4624 wm_latency_show(m
, latencies
);
4629 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4631 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4633 if (INTEL_GEN(dev_priv
) < 5)
4636 return single_open(file
, pri_wm_latency_show
, dev_priv
);
4639 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4641 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4643 if (HAS_GMCH_DISPLAY(dev_priv
))
4646 return single_open(file
, spr_wm_latency_show
, dev_priv
);
4649 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4651 struct drm_i915_private
*dev_priv
= inode
->i_private
;
4653 if (HAS_GMCH_DISPLAY(dev_priv
))
4656 return single_open(file
, cur_wm_latency_show
, dev_priv
);
4659 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4660 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4662 struct seq_file
*m
= file
->private_data
;
4663 struct drm_i915_private
*dev_priv
= m
->private;
4664 struct drm_device
*dev
= &dev_priv
->drm
;
4665 uint16_t new[8] = { 0 };
4671 if (IS_CHERRYVIEW(dev_priv
))
4673 else if (IS_VALLEYVIEW(dev_priv
))
4676 num_levels
= ilk_wm_max_level(dev_priv
) + 1;
4678 if (len
>= sizeof(tmp
))
4681 if (copy_from_user(tmp
, ubuf
, len
))
4686 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4687 &new[0], &new[1], &new[2], &new[3],
4688 &new[4], &new[5], &new[6], &new[7]);
4689 if (ret
!= num_levels
)
4692 drm_modeset_lock_all(dev
);
4694 for (level
= 0; level
< num_levels
; level
++)
4695 wm
[level
] = new[level
];
4697 drm_modeset_unlock_all(dev
);
4703 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4704 size_t len
, loff_t
*offp
)
4706 struct seq_file
*m
= file
->private_data
;
4707 struct drm_i915_private
*dev_priv
= m
->private;
4708 uint16_t *latencies
;
4710 if (INTEL_GEN(dev_priv
) >= 9)
4711 latencies
= dev_priv
->wm
.skl_latency
;
4713 latencies
= dev_priv
->wm
.pri_latency
;
4715 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4718 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4719 size_t len
, loff_t
*offp
)
4721 struct seq_file
*m
= file
->private_data
;
4722 struct drm_i915_private
*dev_priv
= m
->private;
4723 uint16_t *latencies
;
4725 if (INTEL_GEN(dev_priv
) >= 9)
4726 latencies
= dev_priv
->wm
.skl_latency
;
4728 latencies
= dev_priv
->wm
.spr_latency
;
4730 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4733 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4734 size_t len
, loff_t
*offp
)
4736 struct seq_file
*m
= file
->private_data
;
4737 struct drm_i915_private
*dev_priv
= m
->private;
4738 uint16_t *latencies
;
4740 if (INTEL_GEN(dev_priv
) >= 9)
4741 latencies
= dev_priv
->wm
.skl_latency
;
4743 latencies
= dev_priv
->wm
.cur_latency
;
4745 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4748 static const struct file_operations i915_pri_wm_latency_fops
= {
4749 .owner
= THIS_MODULE
,
4750 .open
= pri_wm_latency_open
,
4752 .llseek
= seq_lseek
,
4753 .release
= single_release
,
4754 .write
= pri_wm_latency_write
4757 static const struct file_operations i915_spr_wm_latency_fops
= {
4758 .owner
= THIS_MODULE
,
4759 .open
= spr_wm_latency_open
,
4761 .llseek
= seq_lseek
,
4762 .release
= single_release
,
4763 .write
= spr_wm_latency_write
4766 static const struct file_operations i915_cur_wm_latency_fops
= {
4767 .owner
= THIS_MODULE
,
4768 .open
= cur_wm_latency_open
,
4770 .llseek
= seq_lseek
,
4771 .release
= single_release
,
4772 .write
= cur_wm_latency_write
4776 i915_wedged_get(void *data
, u64
*val
)
4778 struct drm_i915_private
*dev_priv
= data
;
4780 *val
= i915_terminally_wedged(&dev_priv
->gpu_error
);
4786 i915_wedged_set(void *data
, u64 val
)
4788 struct drm_i915_private
*dev_priv
= data
;
4791 * There is no safeguard against this debugfs entry colliding
4792 * with the hangcheck calling same i915_handle_error() in
4793 * parallel, causing an explosion. For now we assume that the
4794 * test harness is responsible enough not to inject gpu hangs
4795 * while it is writing to 'i915_wedged'
4798 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4801 intel_runtime_pm_get(dev_priv
);
4803 i915_handle_error(dev_priv
, val
,
4804 "Manually setting wedged to %llu", val
);
4806 intel_runtime_pm_put(dev_priv
);
4811 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4812 i915_wedged_get
, i915_wedged_set
,
4816 i915_ring_missed_irq_get(void *data
, u64
*val
)
4818 struct drm_i915_private
*dev_priv
= data
;
4820 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4825 i915_ring_missed_irq_set(void *data
, u64 val
)
4827 struct drm_i915_private
*dev_priv
= data
;
4828 struct drm_device
*dev
= &dev_priv
->drm
;
4831 /* Lock against concurrent debugfs callers */
4832 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4835 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4836 mutex_unlock(&dev
->struct_mutex
);
4841 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4842 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4846 i915_ring_test_irq_get(void *data
, u64
*val
)
4848 struct drm_i915_private
*dev_priv
= data
;
4850 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4856 i915_ring_test_irq_set(void *data
, u64 val
)
4858 struct drm_i915_private
*dev_priv
= data
;
4860 val
&= INTEL_INFO(dev_priv
)->ring_mask
;
4861 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4862 dev_priv
->gpu_error
.test_irq_rings
= val
;
4867 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4868 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4871 #define DROP_UNBOUND 0x1
4872 #define DROP_BOUND 0x2
4873 #define DROP_RETIRE 0x4
4874 #define DROP_ACTIVE 0x8
4875 #define DROP_ALL (DROP_UNBOUND | \
4880 i915_drop_caches_get(void *data
, u64
*val
)
4888 i915_drop_caches_set(void *data
, u64 val
)
4890 struct drm_i915_private
*dev_priv
= data
;
4891 struct drm_device
*dev
= &dev_priv
->drm
;
4894 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4896 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4897 * on ioctls on -EAGAIN. */
4898 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4902 if (val
& DROP_ACTIVE
) {
4903 ret
= i915_gem_wait_for_idle(dev_priv
,
4904 I915_WAIT_INTERRUPTIBLE
|
4910 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4911 i915_gem_retire_requests(dev_priv
);
4913 if (val
& DROP_BOUND
)
4914 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4916 if (val
& DROP_UNBOUND
)
4917 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4920 mutex_unlock(&dev
->struct_mutex
);
4925 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4926 i915_drop_caches_get
, i915_drop_caches_set
,
4930 i915_max_freq_get(void *data
, u64
*val
)
4932 struct drm_i915_private
*dev_priv
= data
;
4934 if (INTEL_GEN(dev_priv
) < 6)
4937 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4942 i915_max_freq_set(void *data
, u64 val
)
4944 struct drm_i915_private
*dev_priv
= data
;
4948 if (INTEL_GEN(dev_priv
) < 6)
4951 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4953 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4958 * Turbo will still be enabled, but won't go above the set value.
4960 val
= intel_freq_opcode(dev_priv
, val
);
4962 hw_max
= dev_priv
->rps
.max_freq
;
4963 hw_min
= dev_priv
->rps
.min_freq
;
4965 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4966 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4970 dev_priv
->rps
.max_freq_softlimit
= val
;
4972 intel_set_rps(dev_priv
, val
);
4974 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4979 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4980 i915_max_freq_get
, i915_max_freq_set
,
4984 i915_min_freq_get(void *data
, u64
*val
)
4986 struct drm_i915_private
*dev_priv
= data
;
4988 if (INTEL_GEN(dev_priv
) < 6)
4991 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4996 i915_min_freq_set(void *data
, u64 val
)
4998 struct drm_i915_private
*dev_priv
= data
;
5002 if (INTEL_GEN(dev_priv
) < 6)
5005 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
5007 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5012 * Turbo will still be enabled, but won't go below the set value.
5014 val
= intel_freq_opcode(dev_priv
, val
);
5016 hw_max
= dev_priv
->rps
.max_freq
;
5017 hw_min
= dev_priv
->rps
.min_freq
;
5020 val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5021 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5025 dev_priv
->rps
.min_freq_softlimit
= val
;
5027 intel_set_rps(dev_priv
, val
);
5029 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5034 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5035 i915_min_freq_get
, i915_min_freq_set
,
5039 i915_cache_sharing_get(void *data
, u64
*val
)
5041 struct drm_i915_private
*dev_priv
= data
;
5042 struct drm_device
*dev
= &dev_priv
->drm
;
5046 if (!(IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)))
5049 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5052 intel_runtime_pm_get(dev_priv
);
5054 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5056 intel_runtime_pm_put(dev_priv
);
5057 mutex_unlock(&dev
->struct_mutex
);
5059 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5065 i915_cache_sharing_set(void *data
, u64 val
)
5067 struct drm_i915_private
*dev_priv
= data
;
5070 if (!(IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)))
5076 intel_runtime_pm_get(dev_priv
);
5077 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5079 /* Update the cache sharing policy here as well */
5080 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5081 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5082 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5083 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5085 intel_runtime_pm_put(dev_priv
);
5089 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5090 i915_cache_sharing_get
, i915_cache_sharing_set
,
5093 static void cherryview_sseu_device_status(struct drm_i915_private
*dev_priv
,
5094 struct sseu_dev_info
*sseu
)
5098 u32 sig1
[ss_max
], sig2
[ss_max
];
5100 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5101 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5102 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5103 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5105 for (ss
= 0; ss
< ss_max
; ss
++) {
5106 unsigned int eu_cnt
;
5108 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5109 /* skip disabled subslice */
5112 sseu
->slice_mask
= BIT(0);
5113 sseu
->subslice_mask
|= BIT(ss
);
5114 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5115 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5116 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5117 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5118 sseu
->eu_total
+= eu_cnt
;
5119 sseu
->eu_per_subslice
= max_t(unsigned int,
5120 sseu
->eu_per_subslice
, eu_cnt
);
5124 static void gen9_sseu_device_status(struct drm_i915_private
*dev_priv
,
5125 struct sseu_dev_info
*sseu
)
5127 int s_max
= 3, ss_max
= 4;
5129 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5131 /* BXT has a single slice and at most 3 subslices. */
5132 if (IS_BROXTON(dev_priv
)) {
5137 for (s
= 0; s
< s_max
; s
++) {
5138 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5139 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5140 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5143 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5144 GEN9_PGCTL_SSA_EU19_ACK
|
5145 GEN9_PGCTL_SSA_EU210_ACK
|
5146 GEN9_PGCTL_SSA_EU311_ACK
;
5147 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5148 GEN9_PGCTL_SSB_EU19_ACK
|
5149 GEN9_PGCTL_SSB_EU210_ACK
|
5150 GEN9_PGCTL_SSB_EU311_ACK
;
5152 for (s
= 0; s
< s_max
; s
++) {
5153 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5154 /* skip disabled slice */
5157 sseu
->slice_mask
|= BIT(s
);
5159 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
5160 sseu
->subslice_mask
=
5161 INTEL_INFO(dev_priv
)->sseu
.subslice_mask
;
5163 for (ss
= 0; ss
< ss_max
; ss
++) {
5164 unsigned int eu_cnt
;
5166 if (IS_BROXTON(dev_priv
)) {
5167 if (!(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5168 /* skip disabled subslice */
5171 sseu
->subslice_mask
|= BIT(ss
);
5174 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5176 sseu
->eu_total
+= eu_cnt
;
5177 sseu
->eu_per_subslice
= max_t(unsigned int,
5178 sseu
->eu_per_subslice
,
5184 static void broadwell_sseu_device_status(struct drm_i915_private
*dev_priv
,
5185 struct sseu_dev_info
*sseu
)
5187 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5190 sseu
->slice_mask
= slice_info
& GEN8_LSLICESTAT_MASK
;
5192 if (sseu
->slice_mask
) {
5193 sseu
->subslice_mask
= INTEL_INFO(dev_priv
)->sseu
.subslice_mask
;
5194 sseu
->eu_per_subslice
=
5195 INTEL_INFO(dev_priv
)->sseu
.eu_per_subslice
;
5196 sseu
->eu_total
= sseu
->eu_per_subslice
*
5197 sseu_subslice_total(sseu
);
5199 /* subtract fused off EU(s) from enabled slice(s) */
5200 for (s
= 0; s
< fls(sseu
->slice_mask
); s
++) {
5202 INTEL_INFO(dev_priv
)->sseu
.subslice_7eu
[s
];
5204 sseu
->eu_total
-= hweight8(subslice_7eu
);
5209 static void i915_print_sseu_info(struct seq_file
*m
, bool is_available_info
,
5210 const struct sseu_dev_info
*sseu
)
5212 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
5213 const char *type
= is_available_info
? "Available" : "Enabled";
5215 seq_printf(m
, " %s Slice Mask: %04x\n", type
,
5217 seq_printf(m
, " %s Slice Total: %u\n", type
,
5218 hweight8(sseu
->slice_mask
));
5219 seq_printf(m
, " %s Subslice Total: %u\n", type
,
5220 sseu_subslice_total(sseu
));
5221 seq_printf(m
, " %s Subslice Mask: %04x\n", type
,
5222 sseu
->subslice_mask
);
5223 seq_printf(m
, " %s Subslice Per Slice: %u\n", type
,
5224 hweight8(sseu
->subslice_mask
));
5225 seq_printf(m
, " %s EU Total: %u\n", type
,
5227 seq_printf(m
, " %s EU Per Subslice: %u\n", type
,
5228 sseu
->eu_per_subslice
);
5230 if (!is_available_info
)
5233 seq_printf(m
, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv
)));
5234 if (HAS_POOLED_EU(dev_priv
))
5235 seq_printf(m
, " Min EU in pool: %u\n", sseu
->min_eu_in_pool
);
5237 seq_printf(m
, " Has Slice Power Gating: %s\n",
5238 yesno(sseu
->has_slice_pg
));
5239 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5240 yesno(sseu
->has_subslice_pg
));
5241 seq_printf(m
, " Has EU Power Gating: %s\n",
5242 yesno(sseu
->has_eu_pg
));
5245 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5247 struct drm_i915_private
*dev_priv
= node_to_i915(m
->private);
5248 struct sseu_dev_info sseu
;
5250 if (INTEL_GEN(dev_priv
) < 8)
5253 seq_puts(m
, "SSEU Device Info\n");
5254 i915_print_sseu_info(m
, true, &INTEL_INFO(dev_priv
)->sseu
);
5256 seq_puts(m
, "SSEU Device Status\n");
5257 memset(&sseu
, 0, sizeof(sseu
));
5259 intel_runtime_pm_get(dev_priv
);
5261 if (IS_CHERRYVIEW(dev_priv
)) {
5262 cherryview_sseu_device_status(dev_priv
, &sseu
);
5263 } else if (IS_BROADWELL(dev_priv
)) {
5264 broadwell_sseu_device_status(dev_priv
, &sseu
);
5265 } else if (INTEL_GEN(dev_priv
) >= 9) {
5266 gen9_sseu_device_status(dev_priv
, &sseu
);
5269 intel_runtime_pm_put(dev_priv
);
5271 i915_print_sseu_info(m
, false, &sseu
);
5276 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5278 struct drm_i915_private
*dev_priv
= inode
->i_private
;
5280 if (INTEL_GEN(dev_priv
) < 6)
5283 intel_runtime_pm_get(dev_priv
);
5284 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5289 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5291 struct drm_i915_private
*dev_priv
= inode
->i_private
;
5293 if (INTEL_GEN(dev_priv
) < 6)
5296 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5297 intel_runtime_pm_put(dev_priv
);
5302 static const struct file_operations i915_forcewake_fops
= {
5303 .owner
= THIS_MODULE
,
5304 .open
= i915_forcewake_open
,
5305 .release
= i915_forcewake_release
,
5308 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5312 ent
= debugfs_create_file("i915_forcewake_user",
5314 root
, to_i915(minor
->dev
),
5315 &i915_forcewake_fops
);
5319 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5322 static int i915_debugfs_create(struct dentry
*root
,
5323 struct drm_minor
*minor
,
5325 const struct file_operations
*fops
)
5329 ent
= debugfs_create_file(name
,
5331 root
, to_i915(minor
->dev
),
5336 return drm_add_fake_info_node(minor
, ent
, fops
);
5339 static const struct drm_info_list i915_debugfs_list
[] = {
5340 {"i915_capabilities", i915_capabilities
, 0},
5341 {"i915_gem_objects", i915_gem_object_info
, 0},
5342 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5343 {"i915_gem_pin_display", i915_gem_gtt_info
, 0, (void *)1},
5344 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5345 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5346 {"i915_gem_request", i915_gem_request_info
, 0},
5347 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5348 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5349 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5350 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5351 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5352 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5353 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5354 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5355 {"i915_guc_info", i915_guc_info
, 0},
5356 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5357 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5358 {"i915_frequency_info", i915_frequency_info
, 0},
5359 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5360 {"i915_drpc_info", i915_drpc_info
, 0},
5361 {"i915_emon_status", i915_emon_status
, 0},
5362 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5363 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5364 {"i915_fbc_status", i915_fbc_status
, 0},
5365 {"i915_ips_status", i915_ips_status
, 0},
5366 {"i915_sr_status", i915_sr_status
, 0},
5367 {"i915_opregion", i915_opregion
, 0},
5368 {"i915_vbt", i915_vbt
, 0},
5369 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5370 {"i915_context_status", i915_context_status
, 0},
5371 {"i915_dump_lrc", i915_dump_lrc
, 0},
5372 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5373 {"i915_swizzle_info", i915_swizzle_info
, 0},
5374 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5375 {"i915_llc", i915_llc
, 0},
5376 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5377 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5378 {"i915_energy_uJ", i915_energy_uJ
, 0},
5379 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5380 {"i915_power_domain_info", i915_power_domain_info
, 0},
5381 {"i915_dmc_info", i915_dmc_info
, 0},
5382 {"i915_display_info", i915_display_info
, 0},
5383 {"i915_engine_info", i915_engine_info
, 0},
5384 {"i915_semaphore_status", i915_semaphore_status
, 0},
5385 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5386 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5387 {"i915_wa_registers", i915_wa_registers
, 0},
5388 {"i915_ddb_info", i915_ddb_info
, 0},
5389 {"i915_sseu_status", i915_sseu_status
, 0},
5390 {"i915_drrs_status", i915_drrs_status
, 0},
5391 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5393 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5395 static const struct i915_debugfs_files
{
5397 const struct file_operations
*fops
;
5398 } i915_debugfs_files
[] = {
5399 {"i915_wedged", &i915_wedged_fops
},
5400 {"i915_max_freq", &i915_max_freq_fops
},
5401 {"i915_min_freq", &i915_min_freq_fops
},
5402 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5403 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5404 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5405 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5406 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5407 {"i915_error_state", &i915_error_state_fops
},
5409 {"i915_next_seqno", &i915_next_seqno_fops
},
5410 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5411 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5412 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5413 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5414 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5415 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5416 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5417 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5420 void intel_display_crc_init(struct drm_i915_private
*dev_priv
)
5424 for_each_pipe(dev_priv
, pipe
) {
5425 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5427 pipe_crc
->opened
= false;
5428 spin_lock_init(&pipe_crc
->lock
);
5429 init_waitqueue_head(&pipe_crc
->wq
);
5433 int i915_debugfs_register(struct drm_i915_private
*dev_priv
)
5435 struct drm_minor
*minor
= dev_priv
->drm
.primary
;
5438 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5442 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5443 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5448 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5449 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5450 i915_debugfs_files
[i
].name
,
5451 i915_debugfs_files
[i
].fops
);
5456 return drm_debugfs_create_files(i915_debugfs_list
,
5457 I915_DEBUGFS_ENTRIES
,
5458 minor
->debugfs_root
, minor
);
5461 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
)
5463 struct drm_minor
*minor
= dev_priv
->drm
.primary
;
5466 drm_debugfs_remove_files(i915_debugfs_list
,
5467 I915_DEBUGFS_ENTRIES
, minor
);
5469 drm_debugfs_remove_files((struct drm_info_list
*)&i915_forcewake_fops
,
5472 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5473 struct drm_info_list
*info_list
=
5474 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5476 drm_debugfs_remove_files(info_list
, 1, minor
);
5479 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5480 struct drm_info_list
*info_list
=
5481 (struct drm_info_list
*)i915_debugfs_files
[i
].fops
;
5483 drm_debugfs_remove_files(info_list
, 1, minor
);
5488 /* DPCD dump start address. */
5489 unsigned int offset
;
5490 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5492 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5494 /* Only valid for eDP. */
5498 static const struct dpcd_block i915_dpcd_debug
[] = {
5499 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5500 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5501 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5502 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5503 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5504 { .offset
= DP_SET_POWER
},
5505 { .offset
= DP_EDP_DPCD_REV
},
5506 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5507 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5508 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5511 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5513 struct drm_connector
*connector
= m
->private;
5514 struct intel_dp
*intel_dp
=
5515 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5520 if (connector
->status
!= connector_status_connected
)
5523 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5524 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5525 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5528 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5531 /* low tech for now */
5532 if (WARN_ON(size
> sizeof(buf
)))
5535 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5537 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5538 size
, b
->offset
, err
);
5542 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5548 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5550 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5553 static const struct file_operations i915_dpcd_fops
= {
5554 .owner
= THIS_MODULE
,
5555 .open
= i915_dpcd_open
,
5557 .llseek
= seq_lseek
,
5558 .release
= single_release
,
5561 static int i915_panel_show(struct seq_file
*m
, void *data
)
5563 struct drm_connector
*connector
= m
->private;
5564 struct intel_dp
*intel_dp
=
5565 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5567 if (connector
->status
!= connector_status_connected
)
5570 seq_printf(m
, "Panel power up delay: %d\n",
5571 intel_dp
->panel_power_up_delay
);
5572 seq_printf(m
, "Panel power down delay: %d\n",
5573 intel_dp
->panel_power_down_delay
);
5574 seq_printf(m
, "Backlight on delay: %d\n",
5575 intel_dp
->backlight_on_delay
);
5576 seq_printf(m
, "Backlight off delay: %d\n",
5577 intel_dp
->backlight_off_delay
);
5582 static int i915_panel_open(struct inode
*inode
, struct file
*file
)
5584 return single_open(file
, i915_panel_show
, inode
->i_private
);
5587 static const struct file_operations i915_panel_fops
= {
5588 .owner
= THIS_MODULE
,
5589 .open
= i915_panel_open
,
5591 .llseek
= seq_lseek
,
5592 .release
= single_release
,
5596 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5597 * @connector: pointer to a registered drm_connector
5599 * Cleanup will be done by drm_connector_unregister() through a call to
5600 * drm_debugfs_connector_remove().
5602 * Returns 0 on success, negative error codes on error.
5604 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5606 struct dentry
*root
= connector
->debugfs_entry
;
5608 /* The connector must have been registered beforehands. */
5612 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5613 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5614 debugfs_create_file("i915_dpcd", S_IRUGO
, root
,
5615 connector
, &i915_dpcd_fops
);
5617 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5618 debugfs_create_file("i915_panel_timings", S_IRUGO
, root
,
5619 connector
, &i915_panel_fops
);