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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->pin_display)
95 return "p";
96 else
97 return " ";
98 }
99
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
101 {
102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
108 }
109
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111 {
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
113 }
114
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116 {
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
124 }
125
126 return size;
127 }
128
129 static void
130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131 {
132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
134 struct i915_vma *vma;
135 int pin_count = 0;
136 int i;
137
138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
139 &obj->base,
140 obj->active ? "*" : " ",
141 get_pin_flag(obj),
142 get_tiling_flag(obj),
143 get_global_flag(obj),
144 obj->base.size / 1024,
145 obj->base.read_domains,
146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
148 seq_printf(m, "%x ",
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 if (obj->base.name)
157 seq_printf(m, " (name: %d)", obj->base.name);
158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
159 if (vma->pin_count > 0)
160 pin_count++;
161 }
162 seq_printf(m, " (pinned x %d)", pin_count);
163 if (obj->pin_display)
164 seq_printf(m, " (display)");
165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
173 else
174 seq_puts(m, ")");
175 }
176 if (obj->stolen)
177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
178 if (obj->pin_display || obj->fault_mappable) {
179 char s[3], *t = s;
180 if (obj->pin_display)
181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
187 if (obj->last_write_req != NULL)
188 seq_printf(m, " (%s)",
189 i915_gem_request_get_ring(obj->last_write_req)->name);
190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
192 }
193
194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
195 {
196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199 }
200
201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
202 {
203 struct drm_info_node *node = m->private;
204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
206 struct drm_device *dev = node->minor->dev;
207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
209 struct i915_vma *vma;
210 u64 total_obj_size, total_gtt_size;
211 int count, ret;
212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
216
217 /* FIXME: the user of this interface might want more than just GGTT */
218 switch (list) {
219 case ACTIVE_LIST:
220 seq_puts(m, "Active:\n");
221 head = &vm->active_list;
222 break;
223 case INACTIVE_LIST:
224 seq_puts(m, "Inactive:\n");
225 head = &vm->inactive_list;
226 break;
227 default:
228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
230 }
231
232 total_obj_size = total_gtt_size = count = 0;
233 list_for_each_entry(vma, head, mm_list) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
239 count++;
240 }
241 mutex_unlock(&dev->struct_mutex);
242
243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count, total_obj_size, total_gtt_size);
245 return 0;
246 }
247
248 static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250 {
251 struct drm_i915_gem_object *a =
252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
253 struct drm_i915_gem_object *b =
254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
255
256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
261 }
262
263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264 {
265 struct drm_info_node *node = m->private;
266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
269 u64 total_obj_size, total_gtt_size;
270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
282 list_add(&obj->obj_exec_link, &stolen);
283
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
292 list_add(&obj->obj_exec_link, &stolen);
293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
304 list_del_init(&obj->obj_exec_link);
305 }
306 mutex_unlock(&dev->struct_mutex);
307
308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
310 return 0;
311 }
312
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
316 ++count; \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
319 ++mappable_count; \
320 } \
321 } \
322 } while (0)
323
324 struct file_stats {
325 struct drm_i915_file_private *file_priv;
326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
330 };
331
332 static int per_file_stats(int id, void *ptr, void *data)
333 {
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
336 struct i915_vma *vma;
337
338 stats->count++;
339 stats->total += obj->base.size;
340
341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, vma_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (i915_is_ggtt(vma->vm)) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
357 if (ppgtt->file_priv != stats->file_priv)
358 continue;
359
360 if (obj->active) /* XXX per-vma statistic */
361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
367 } else {
368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
370 if (obj->active)
371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
376 }
377
378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
381 return 0;
382 }
383
384 #define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395 } while (0)
396
397 static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399 {
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
402 struct intel_engine_cs *ring;
403 int i, j;
404
405 memset(&stats, 0, sizeof(stats));
406
407 for_each_ring(ring, dev_priv, i) {
408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &ring->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
414 }
415
416 print_file_stats(m, "[k]batch pool", stats);
417 }
418
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428 } while (0)
429
430 static int i915_gem_object_info(struct seq_file *m, void* data)
431 {
432 struct drm_info_node *node = m->private;
433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
435 u32 count, mappable_count, purgeable_count;
436 u64 size, mappable_size, purgeable_size;
437 struct drm_i915_gem_object *obj;
438 struct i915_address_space *vm = &dev_priv->gtt.base;
439 struct drm_file *file;
440 struct i915_vma *vma;
441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
452 count_objects(&dev_priv->mm.bound_list, global_list);
453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
457 count_vmas(&vm->active_list, mm_list);
458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count, mappable_count, size, mappable_size);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_vmas(&vm->inactive_list, mm_list);
463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = purgeable_size = purgeable_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
468 size += obj->base.size, ++count;
469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
473
474 size = count = mappable_size = mappable_count = 0;
475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
476 if (obj->fault_mappable) {
477 size += i915_gem_obj_ggtt_size(obj);
478 ++count;
479 }
480 if (obj->pin_display) {
481 mappable_size += i915_gem_obj_ggtt_size(obj);
482 ++mappable_count;
483 }
484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
488 }
489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
490 purgeable_count, purgeable_size);
491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count, mappable_size);
493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
494 count, size);
495
496 seq_printf(m, "%llu [%llu] gtt total\n",
497 dev_priv->gtt.base.total,
498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
499
500 seq_putc(m, '\n');
501 print_batch_pool_stats(m, dev_priv);
502 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
503 struct file_stats stats;
504 struct task_struct *task;
505
506 memset(&stats, 0, sizeof(stats));
507 stats.file_priv = file->driver_priv;
508 spin_lock(&file->table_lock);
509 idr_for_each(&file->object_idr, per_file_stats, &stats);
510 spin_unlock(&file->table_lock);
511 /*
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
516 */
517 rcu_read_lock();
518 task = pid_task(file->pid, PIDTYPE_PID);
519 print_file_stats(m, task ? task->comm : "<unknown>", stats);
520 rcu_read_unlock();
521 }
522
523 mutex_unlock(&dev->struct_mutex);
524
525 return 0;
526 }
527
528 static int i915_gem_gtt_info(struct seq_file *m, void *data)
529 {
530 struct drm_info_node *node = m->private;
531 struct drm_device *dev = node->minor->dev;
532 uintptr_t list = (uintptr_t) node->info_ent->data;
533 struct drm_i915_private *dev_priv = dev->dev_private;
534 struct drm_i915_gem_object *obj;
535 u64 total_obj_size, total_gtt_size;
536 int count, ret;
537
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
539 if (ret)
540 return ret;
541
542 total_obj_size = total_gtt_size = count = 0;
543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
545 continue;
546
547 seq_puts(m, " ");
548 describe_obj(m, obj);
549 seq_putc(m, '\n');
550 total_obj_size += obj->base.size;
551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
552 count++;
553 }
554
555 mutex_unlock(&dev->struct_mutex);
556
557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
558 count, total_obj_size, total_gtt_size);
559
560 return 0;
561 }
562
563 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
564 {
565 struct drm_info_node *node = m->private;
566 struct drm_device *dev = node->minor->dev;
567 struct drm_i915_private *dev_priv = dev->dev_private;
568 struct intel_crtc *crtc;
569 int ret;
570
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
572 if (ret)
573 return ret;
574
575 for_each_intel_crtc(dev, crtc) {
576 const char pipe = pipe_name(crtc->pipe);
577 const char plane = plane_name(crtc->plane);
578 struct intel_unpin_work *work;
579
580 spin_lock_irq(&dev->event_lock);
581 work = crtc->unpin_work;
582 if (work == NULL) {
583 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
584 pipe, plane);
585 } else {
586 u32 addr;
587
588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
590 pipe, plane);
591 } else {
592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
593 pipe, plane);
594 }
595 if (work->flip_queued_req) {
596 struct intel_engine_cs *ring =
597 i915_gem_request_get_ring(work->flip_queued_req);
598
599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
600 ring->name,
601 i915_gem_request_get_seqno(work->flip_queued_req),
602 dev_priv->next_seqno,
603 ring->get_seqno(ring, true),
604 i915_gem_request_completed(work->flip_queued_req, true));
605 } else
606 seq_printf(m, "Flip not associated with any ring\n");
607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work->flip_queued_vblank,
609 work->flip_ready_vblank,
610 drm_crtc_vblank_count(&crtc->base));
611 if (work->enable_stall_check)
612 seq_puts(m, "Stall check enabled, ");
613 else
614 seq_puts(m, "Stall check waiting for page flip ioctl, ");
615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
616
617 if (INTEL_INFO(dev)->gen >= 4)
618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
619 else
620 addr = I915_READ(DSPADDR(crtc->plane));
621 seq_printf(m, "Current scanout address 0x%08x\n", addr);
622
623 if (work->pending_flip_obj) {
624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
626 }
627 }
628 spin_unlock_irq(&dev->event_lock);
629 }
630
631 mutex_unlock(&dev->struct_mutex);
632
633 return 0;
634 }
635
636 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
637 {
638 struct drm_info_node *node = m->private;
639 struct drm_device *dev = node->minor->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_i915_gem_object *obj;
642 struct intel_engine_cs *ring;
643 int total = 0;
644 int ret, i, j;
645
646 ret = mutex_lock_interruptible(&dev->struct_mutex);
647 if (ret)
648 return ret;
649
650 for_each_ring(ring, dev_priv, i) {
651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
652 int count;
653
654 count = 0;
655 list_for_each_entry(obj,
656 &ring->batch_pool.cache_list[j],
657 batch_pool_link)
658 count++;
659 seq_printf(m, "%s cache[%d]: %d objects\n",
660 ring->name, j, count);
661
662 list_for_each_entry(obj,
663 &ring->batch_pool.cache_list[j],
664 batch_pool_link) {
665 seq_puts(m, " ");
666 describe_obj(m, obj);
667 seq_putc(m, '\n');
668 }
669
670 total += count;
671 }
672 }
673
674 seq_printf(m, "total: %d\n", total);
675
676 mutex_unlock(&dev->struct_mutex);
677
678 return 0;
679 }
680
681 static int i915_gem_request_info(struct seq_file *m, void *data)
682 {
683 struct drm_info_node *node = m->private;
684 struct drm_device *dev = node->minor->dev;
685 struct drm_i915_private *dev_priv = dev->dev_private;
686 struct intel_engine_cs *ring;
687 struct drm_i915_gem_request *req;
688 int ret, any, i;
689
690 ret = mutex_lock_interruptible(&dev->struct_mutex);
691 if (ret)
692 return ret;
693
694 any = 0;
695 for_each_ring(ring, dev_priv, i) {
696 int count;
697
698 count = 0;
699 list_for_each_entry(req, &ring->request_list, list)
700 count++;
701 if (count == 0)
702 continue;
703
704 seq_printf(m, "%s requests: %d\n", ring->name, count);
705 list_for_each_entry(req, &ring->request_list, list) {
706 struct task_struct *task;
707
708 rcu_read_lock();
709 task = NULL;
710 if (req->pid)
711 task = pid_task(req->pid, PIDTYPE_PID);
712 seq_printf(m, " %x @ %d: %s [%d]\n",
713 req->seqno,
714 (int) (jiffies - req->emitted_jiffies),
715 task ? task->comm : "<unknown>",
716 task ? task->pid : -1);
717 rcu_read_unlock();
718 }
719
720 any++;
721 }
722 mutex_unlock(&dev->struct_mutex);
723
724 if (any == 0)
725 seq_puts(m, "No requests\n");
726
727 return 0;
728 }
729
730 static void i915_ring_seqno_info(struct seq_file *m,
731 struct intel_engine_cs *ring)
732 {
733 if (ring->get_seqno) {
734 seq_printf(m, "Current sequence (%s): %x\n",
735 ring->name, ring->get_seqno(ring, false));
736 }
737 }
738
739 static int i915_gem_seqno_info(struct seq_file *m, void *data)
740 {
741 struct drm_info_node *node = m->private;
742 struct drm_device *dev = node->minor->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct intel_engine_cs *ring;
745 int ret, i;
746
747 ret = mutex_lock_interruptible(&dev->struct_mutex);
748 if (ret)
749 return ret;
750 intel_runtime_pm_get(dev_priv);
751
752 for_each_ring(ring, dev_priv, i)
753 i915_ring_seqno_info(m, ring);
754
755 intel_runtime_pm_put(dev_priv);
756 mutex_unlock(&dev->struct_mutex);
757
758 return 0;
759 }
760
761
762 static int i915_interrupt_info(struct seq_file *m, void *data)
763 {
764 struct drm_info_node *node = m->private;
765 struct drm_device *dev = node->minor->dev;
766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct intel_engine_cs *ring;
768 int ret, i, pipe;
769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
773 intel_runtime_pm_get(dev_priv);
774
775 if (IS_CHERRYVIEW(dev)) {
776 seq_printf(m, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ));
778
779 seq_printf(m, "Display IER:\t%08x\n",
780 I915_READ(VLV_IER));
781 seq_printf(m, "Display IIR:\t%08x\n",
782 I915_READ(VLV_IIR));
783 seq_printf(m, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW));
785 seq_printf(m, "Display IMR:\t%08x\n",
786 I915_READ(VLV_IMR));
787 for_each_pipe(dev_priv, pipe)
788 seq_printf(m, "Pipe %c stat:\t%08x\n",
789 pipe_name(pipe),
790 I915_READ(PIPESTAT(pipe)));
791
792 seq_printf(m, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN));
794 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT));
796 seq_printf(m, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 seq_printf(m, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR));
810 seq_printf(m, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR));
812 seq_printf(m, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER));
814 } else if (INTEL_INFO(dev)->gen >= 8) {
815 seq_printf(m, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ));
817
818 for (i = 0; i < 4; i++) {
819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IMR(i)));
821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IIR(i)));
823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
824 i, I915_READ(GEN8_GT_IER(i)));
825 }
826
827 for_each_pipe(dev_priv, pipe) {
828 if (!intel_display_power_is_enabled(dev_priv,
829 POWER_DOMAIN_PIPE(pipe))) {
830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
840 seq_printf(m, "Pipe %c IER:\t%08x\n",
841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
843 }
844
845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR));
847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR));
849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER));
851
852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR));
854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR));
856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER));
858
859 seq_printf(m, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR));
861 seq_printf(m, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR));
863 seq_printf(m, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER));
865 } else if (IS_VALLEYVIEW(dev)) {
866 seq_printf(m, "Display IER:\t%08x\n",
867 I915_READ(VLV_IER));
868 seq_printf(m, "Display IIR:\t%08x\n",
869 I915_READ(VLV_IIR));
870 seq_printf(m, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW));
872 seq_printf(m, "Display IMR:\t%08x\n",
873 I915_READ(VLV_IMR));
874 for_each_pipe(dev_priv, pipe)
875 seq_printf(m, "Pipe %c stat:\t%08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
878
879 seq_printf(m, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER));
881
882 seq_printf(m, "Render IER:\t%08x\n",
883 I915_READ(GTIER));
884 seq_printf(m, "Render IIR:\t%08x\n",
885 I915_READ(GTIIR));
886 seq_printf(m, "Render IMR:\t%08x\n",
887 I915_READ(GTIMR));
888
889 seq_printf(m, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER));
891 seq_printf(m, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR));
893 seq_printf(m, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR));
895
896 seq_printf(m, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN));
898 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT));
900 seq_printf(m, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT));
902
903 } else if (!HAS_PCH_SPLIT(dev)) {
904 seq_printf(m, "Interrupt enable: %08x\n",
905 I915_READ(IER));
906 seq_printf(m, "Interrupt identity: %08x\n",
907 I915_READ(IIR));
908 seq_printf(m, "Interrupt mask: %08x\n",
909 I915_READ(IMR));
910 for_each_pipe(dev_priv, pipe)
911 seq_printf(m, "Pipe %c stat: %08x\n",
912 pipe_name(pipe),
913 I915_READ(PIPESTAT(pipe)));
914 } else {
915 seq_printf(m, "North Display Interrupt enable: %08x\n",
916 I915_READ(DEIER));
917 seq_printf(m, "North Display Interrupt identity: %08x\n",
918 I915_READ(DEIIR));
919 seq_printf(m, "North Display Interrupt mask: %08x\n",
920 I915_READ(DEIMR));
921 seq_printf(m, "South Display Interrupt enable: %08x\n",
922 I915_READ(SDEIER));
923 seq_printf(m, "South Display Interrupt identity: %08x\n",
924 I915_READ(SDEIIR));
925 seq_printf(m, "South Display Interrupt mask: %08x\n",
926 I915_READ(SDEIMR));
927 seq_printf(m, "Graphics Interrupt enable: %08x\n",
928 I915_READ(GTIER));
929 seq_printf(m, "Graphics Interrupt identity: %08x\n",
930 I915_READ(GTIIR));
931 seq_printf(m, "Graphics Interrupt mask: %08x\n",
932 I915_READ(GTIMR));
933 }
934 for_each_ring(ring, dev_priv, i) {
935 if (INTEL_INFO(dev)->gen >= 6) {
936 seq_printf(m,
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring->name, I915_READ_IMR(ring));
939 }
940 i915_ring_seqno_info(m, ring);
941 }
942 intel_runtime_pm_put(dev_priv);
943 mutex_unlock(&dev->struct_mutex);
944
945 return 0;
946 }
947
948 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
949 {
950 struct drm_info_node *node = m->private;
951 struct drm_device *dev = node->minor->dev;
952 struct drm_i915_private *dev_priv = dev->dev_private;
953 int i, ret;
954
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
956 if (ret)
957 return ret;
958
959 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
960 for (i = 0; i < dev_priv->num_fence_regs; i++) {
961 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
962
963 seq_printf(m, "Fence %d, pin count = %d, object = ",
964 i, dev_priv->fence_regs[i].pin_count);
965 if (obj == NULL)
966 seq_puts(m, "unused");
967 else
968 describe_obj(m, obj);
969 seq_putc(m, '\n');
970 }
971
972 mutex_unlock(&dev->struct_mutex);
973 return 0;
974 }
975
976 static int i915_hws_info(struct seq_file *m, void *data)
977 {
978 struct drm_info_node *node = m->private;
979 struct drm_device *dev = node->minor->dev;
980 struct drm_i915_private *dev_priv = dev->dev_private;
981 struct intel_engine_cs *ring;
982 const u32 *hws;
983 int i;
984
985 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
986 hws = ring->status_page.page_addr;
987 if (hws == NULL)
988 return 0;
989
990 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
991 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
992 i * 4,
993 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
994 }
995 return 0;
996 }
997
998 static ssize_t
999 i915_error_state_write(struct file *filp,
1000 const char __user *ubuf,
1001 size_t cnt,
1002 loff_t *ppos)
1003 {
1004 struct i915_error_state_file_priv *error_priv = filp->private_data;
1005 struct drm_device *dev = error_priv->dev;
1006 int ret;
1007
1008 DRM_DEBUG_DRIVER("Resetting error state\n");
1009
1010 ret = mutex_lock_interruptible(&dev->struct_mutex);
1011 if (ret)
1012 return ret;
1013
1014 i915_destroy_error_state(dev);
1015 mutex_unlock(&dev->struct_mutex);
1016
1017 return cnt;
1018 }
1019
1020 static int i915_error_state_open(struct inode *inode, struct file *file)
1021 {
1022 struct drm_device *dev = inode->i_private;
1023 struct i915_error_state_file_priv *error_priv;
1024
1025 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1026 if (!error_priv)
1027 return -ENOMEM;
1028
1029 error_priv->dev = dev;
1030
1031 i915_error_state_get(dev, error_priv);
1032
1033 file->private_data = error_priv;
1034
1035 return 0;
1036 }
1037
1038 static int i915_error_state_release(struct inode *inode, struct file *file)
1039 {
1040 struct i915_error_state_file_priv *error_priv = file->private_data;
1041
1042 i915_error_state_put(error_priv);
1043 kfree(error_priv);
1044
1045 return 0;
1046 }
1047
1048 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1049 size_t count, loff_t *pos)
1050 {
1051 struct i915_error_state_file_priv *error_priv = file->private_data;
1052 struct drm_i915_error_state_buf error_str;
1053 loff_t tmp_pos = 0;
1054 ssize_t ret_count = 0;
1055 int ret;
1056
1057 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1058 if (ret)
1059 return ret;
1060
1061 ret = i915_error_state_to_str(&error_str, error_priv);
1062 if (ret)
1063 goto out;
1064
1065 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1066 error_str.buf,
1067 error_str.bytes);
1068
1069 if (ret_count < 0)
1070 ret = ret_count;
1071 else
1072 *pos = error_str.start + ret_count;
1073 out:
1074 i915_error_state_buf_release(&error_str);
1075 return ret ?: ret_count;
1076 }
1077
1078 static const struct file_operations i915_error_state_fops = {
1079 .owner = THIS_MODULE,
1080 .open = i915_error_state_open,
1081 .read = i915_error_state_read,
1082 .write = i915_error_state_write,
1083 .llseek = default_llseek,
1084 .release = i915_error_state_release,
1085 };
1086
1087 static int
1088 i915_next_seqno_get(void *data, u64 *val)
1089 {
1090 struct drm_device *dev = data;
1091 struct drm_i915_private *dev_priv = dev->dev_private;
1092 int ret;
1093
1094 ret = mutex_lock_interruptible(&dev->struct_mutex);
1095 if (ret)
1096 return ret;
1097
1098 *val = dev_priv->next_seqno;
1099 mutex_unlock(&dev->struct_mutex);
1100
1101 return 0;
1102 }
1103
1104 static int
1105 i915_next_seqno_set(void *data, u64 val)
1106 {
1107 struct drm_device *dev = data;
1108 int ret;
1109
1110 ret = mutex_lock_interruptible(&dev->struct_mutex);
1111 if (ret)
1112 return ret;
1113
1114 ret = i915_gem_set_seqno(dev, val);
1115 mutex_unlock(&dev->struct_mutex);
1116
1117 return ret;
1118 }
1119
1120 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1121 i915_next_seqno_get, i915_next_seqno_set,
1122 "0x%llx\n");
1123
1124 static int i915_frequency_info(struct seq_file *m, void *unused)
1125 {
1126 struct drm_info_node *node = m->private;
1127 struct drm_device *dev = node->minor->dev;
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129 int ret = 0;
1130
1131 intel_runtime_pm_get(dev_priv);
1132
1133 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1134
1135 if (IS_GEN5(dev)) {
1136 u16 rgvswctl = I915_READ16(MEMSWCTL);
1137 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1138
1139 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1140 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1141 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1142 MEMSTAT_VID_SHIFT);
1143 seq_printf(m, "Current P-state: %d\n",
1144 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1145 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1146 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1147 u32 rp_state_limits;
1148 u32 gt_perf_status;
1149 u32 rp_state_cap;
1150 u32 rpmodectl, rpinclimit, rpdeclimit;
1151 u32 rpstat, cagf, reqf;
1152 u32 rpupei, rpcurup, rpprevup;
1153 u32 rpdownei, rpcurdown, rpprevdown;
1154 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1155 int max_freq;
1156
1157 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1158 if (IS_BROXTON(dev)) {
1159 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1160 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1161 } else {
1162 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1163 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1164 }
1165
1166 /* RPSTAT1 is in the GT power well */
1167 ret = mutex_lock_interruptible(&dev->struct_mutex);
1168 if (ret)
1169 goto out;
1170
1171 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1172
1173 reqf = I915_READ(GEN6_RPNSWREQ);
1174 if (IS_GEN9(dev))
1175 reqf >>= 23;
1176 else {
1177 reqf &= ~GEN6_TURBO_DISABLE;
1178 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1179 reqf >>= 24;
1180 else
1181 reqf >>= 25;
1182 }
1183 reqf = intel_gpu_freq(dev_priv, reqf);
1184
1185 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1186 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1187 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1188
1189 rpstat = I915_READ(GEN6_RPSTAT1);
1190 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1191 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1192 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1193 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1194 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1195 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1196 if (IS_GEN9(dev))
1197 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1198 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1199 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1200 else
1201 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1202 cagf = intel_gpu_freq(dev_priv, cagf);
1203
1204 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1205 mutex_unlock(&dev->struct_mutex);
1206
1207 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1208 pm_ier = I915_READ(GEN6_PMIER);
1209 pm_imr = I915_READ(GEN6_PMIMR);
1210 pm_isr = I915_READ(GEN6_PMISR);
1211 pm_iir = I915_READ(GEN6_PMIIR);
1212 pm_mask = I915_READ(GEN6_PMINTRMSK);
1213 } else {
1214 pm_ier = I915_READ(GEN8_GT_IER(2));
1215 pm_imr = I915_READ(GEN8_GT_IMR(2));
1216 pm_isr = I915_READ(GEN8_GT_ISR(2));
1217 pm_iir = I915_READ(GEN8_GT_IIR(2));
1218 pm_mask = I915_READ(GEN6_PMINTRMSK);
1219 }
1220 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1221 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1222 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1223 seq_printf(m, "Render p-state ratio: %d\n",
1224 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1225 seq_printf(m, "Render p-state VID: %d\n",
1226 gt_perf_status & 0xff);
1227 seq_printf(m, "Render p-state limit: %d\n",
1228 rp_state_limits & 0xff);
1229 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1230 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1231 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1232 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1233 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1234 seq_printf(m, "CAGF: %dMHz\n", cagf);
1235 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1236 GEN6_CURICONT_MASK);
1237 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1238 GEN6_CURBSYTAVG_MASK);
1239 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1240 GEN6_CURBSYTAVG_MASK);
1241 seq_printf(m, "Up threshold: %d%%\n",
1242 dev_priv->rps.up_threshold);
1243
1244 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1245 GEN6_CURIAVG_MASK);
1246 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1247 GEN6_CURBSYTAVG_MASK);
1248 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1249 GEN6_CURBSYTAVG_MASK);
1250 seq_printf(m, "Down threshold: %d%%\n",
1251 dev_priv->rps.down_threshold);
1252
1253 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1254 rp_state_cap >> 16) & 0xff;
1255 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1256 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1257 intel_gpu_freq(dev_priv, max_freq));
1258
1259 max_freq = (rp_state_cap & 0xff00) >> 8;
1260 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1261 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1262 intel_gpu_freq(dev_priv, max_freq));
1263
1264 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1265 rp_state_cap >> 0) & 0xff;
1266 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1267 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1268 intel_gpu_freq(dev_priv, max_freq));
1269 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1270 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1271
1272 seq_printf(m, "Current freq: %d MHz\n",
1273 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1274 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1275 seq_printf(m, "Idle freq: %d MHz\n",
1276 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1277 seq_printf(m, "Min freq: %d MHz\n",
1278 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1279 seq_printf(m, "Max freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1281 seq_printf(m,
1282 "efficient (RPe) frequency: %d MHz\n",
1283 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 u32 freq_sts;
1286
1287 mutex_lock(&dev_priv->rps.hw_lock);
1288 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1289 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1290 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1291
1292 seq_printf(m, "actual GPU freq: %d MHz\n",
1293 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1294
1295 seq_printf(m, "current GPU freq: %d MHz\n",
1296 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1297
1298 seq_printf(m, "max GPU freq: %d MHz\n",
1299 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1300
1301 seq_printf(m, "min GPU freq: %d MHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1303
1304 seq_printf(m, "idle GPU freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1306
1307 seq_printf(m,
1308 "efficient (RPe) frequency: %d MHz\n",
1309 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1310 mutex_unlock(&dev_priv->rps.hw_lock);
1311 } else {
1312 seq_puts(m, "no P-state info available\n");
1313 }
1314
1315 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1316 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1317 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1318
1319 out:
1320 intel_runtime_pm_put(dev_priv);
1321 return ret;
1322 }
1323
1324 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1325 {
1326 struct drm_info_node *node = m->private;
1327 struct drm_device *dev = node->minor->dev;
1328 struct drm_i915_private *dev_priv = dev->dev_private;
1329 struct intel_engine_cs *ring;
1330 u64 acthd[I915_NUM_RINGS];
1331 u32 seqno[I915_NUM_RINGS];
1332 int i;
1333
1334 if (!i915.enable_hangcheck) {
1335 seq_printf(m, "Hangcheck disabled\n");
1336 return 0;
1337 }
1338
1339 intel_runtime_pm_get(dev_priv);
1340
1341 for_each_ring(ring, dev_priv, i) {
1342 seqno[i] = ring->get_seqno(ring, false);
1343 acthd[i] = intel_ring_get_active_head(ring);
1344 }
1345
1346 intel_runtime_pm_put(dev_priv);
1347
1348 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1349 seq_printf(m, "Hangcheck active, fires in %dms\n",
1350 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1351 jiffies));
1352 } else
1353 seq_printf(m, "Hangcheck inactive\n");
1354
1355 for_each_ring(ring, dev_priv, i) {
1356 seq_printf(m, "%s:\n", ring->name);
1357 seq_printf(m, "\tseqno = %x [current %x]\n",
1358 ring->hangcheck.seqno, seqno[i]);
1359 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1360 (long long)ring->hangcheck.acthd,
1361 (long long)acthd[i]);
1362 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1363 (long long)ring->hangcheck.max_acthd);
1364 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1365 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1366 }
1367
1368 return 0;
1369 }
1370
1371 static int ironlake_drpc_info(struct seq_file *m)
1372 {
1373 struct drm_info_node *node = m->private;
1374 struct drm_device *dev = node->minor->dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 u32 rgvmodectl, rstdbyctl;
1377 u16 crstandvid;
1378 int ret;
1379
1380 ret = mutex_lock_interruptible(&dev->struct_mutex);
1381 if (ret)
1382 return ret;
1383 intel_runtime_pm_get(dev_priv);
1384
1385 rgvmodectl = I915_READ(MEMMODECTL);
1386 rstdbyctl = I915_READ(RSTDBYCTL);
1387 crstandvid = I915_READ16(CRSTANDVID);
1388
1389 intel_runtime_pm_put(dev_priv);
1390 mutex_unlock(&dev->struct_mutex);
1391
1392 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1393 seq_printf(m, "Boost freq: %d\n",
1394 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1395 MEMMODE_BOOST_FREQ_SHIFT);
1396 seq_printf(m, "HW control enabled: %s\n",
1397 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1398 seq_printf(m, "SW control enabled: %s\n",
1399 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1400 seq_printf(m, "Gated voltage change: %s\n",
1401 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1402 seq_printf(m, "Starting frequency: P%d\n",
1403 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1404 seq_printf(m, "Max P-state: P%d\n",
1405 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1406 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1407 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1408 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1409 seq_printf(m, "Render standby enabled: %s\n",
1410 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1411 seq_puts(m, "Current RS state: ");
1412 switch (rstdbyctl & RSX_STATUS_MASK) {
1413 case RSX_STATUS_ON:
1414 seq_puts(m, "on\n");
1415 break;
1416 case RSX_STATUS_RC1:
1417 seq_puts(m, "RC1\n");
1418 break;
1419 case RSX_STATUS_RC1E:
1420 seq_puts(m, "RC1E\n");
1421 break;
1422 case RSX_STATUS_RS1:
1423 seq_puts(m, "RS1\n");
1424 break;
1425 case RSX_STATUS_RS2:
1426 seq_puts(m, "RS2 (RC6)\n");
1427 break;
1428 case RSX_STATUS_RS3:
1429 seq_puts(m, "RC3 (RC6+)\n");
1430 break;
1431 default:
1432 seq_puts(m, "unknown\n");
1433 break;
1434 }
1435
1436 return 0;
1437 }
1438
1439 static int i915_forcewake_domains(struct seq_file *m, void *data)
1440 {
1441 struct drm_info_node *node = m->private;
1442 struct drm_device *dev = node->minor->dev;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 struct intel_uncore_forcewake_domain *fw_domain;
1445 int i;
1446
1447 spin_lock_irq(&dev_priv->uncore.lock);
1448 for_each_fw_domain(fw_domain, dev_priv, i) {
1449 seq_printf(m, "%s.wake_count = %u\n",
1450 intel_uncore_forcewake_domain_to_str(i),
1451 fw_domain->wake_count);
1452 }
1453 spin_unlock_irq(&dev_priv->uncore.lock);
1454
1455 return 0;
1456 }
1457
1458 static int vlv_drpc_info(struct seq_file *m)
1459 {
1460 struct drm_info_node *node = m->private;
1461 struct drm_device *dev = node->minor->dev;
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 u32 rpmodectl1, rcctl1, pw_status;
1464
1465 intel_runtime_pm_get(dev_priv);
1466
1467 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1468 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1469 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1470
1471 intel_runtime_pm_put(dev_priv);
1472
1473 seq_printf(m, "Video Turbo Mode: %s\n",
1474 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1475 seq_printf(m, "Turbo enabled: %s\n",
1476 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1477 seq_printf(m, "HW control enabled: %s\n",
1478 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1479 seq_printf(m, "SW control enabled: %s\n",
1480 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1481 GEN6_RP_MEDIA_SW_MODE));
1482 seq_printf(m, "RC6 Enabled: %s\n",
1483 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1484 GEN6_RC_CTL_EI_MODE(1))));
1485 seq_printf(m, "Render Power Well: %s\n",
1486 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1487 seq_printf(m, "Media Power Well: %s\n",
1488 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1489
1490 seq_printf(m, "Render RC6 residency since boot: %u\n",
1491 I915_READ(VLV_GT_RENDER_RC6));
1492 seq_printf(m, "Media RC6 residency since boot: %u\n",
1493 I915_READ(VLV_GT_MEDIA_RC6));
1494
1495 return i915_forcewake_domains(m, NULL);
1496 }
1497
1498 static int gen6_drpc_info(struct seq_file *m)
1499 {
1500 struct drm_info_node *node = m->private;
1501 struct drm_device *dev = node->minor->dev;
1502 struct drm_i915_private *dev_priv = dev->dev_private;
1503 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1504 unsigned forcewake_count;
1505 int count = 0, ret;
1506
1507 ret = mutex_lock_interruptible(&dev->struct_mutex);
1508 if (ret)
1509 return ret;
1510 intel_runtime_pm_get(dev_priv);
1511
1512 spin_lock_irq(&dev_priv->uncore.lock);
1513 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1514 spin_unlock_irq(&dev_priv->uncore.lock);
1515
1516 if (forcewake_count) {
1517 seq_puts(m, "RC information inaccurate because somebody "
1518 "holds a forcewake reference \n");
1519 } else {
1520 /* NB: we cannot use forcewake, else we read the wrong values */
1521 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1522 udelay(10);
1523 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1524 }
1525
1526 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1527 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1528
1529 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1530 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1531 mutex_unlock(&dev->struct_mutex);
1532 mutex_lock(&dev_priv->rps.hw_lock);
1533 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1534 mutex_unlock(&dev_priv->rps.hw_lock);
1535
1536 intel_runtime_pm_put(dev_priv);
1537
1538 seq_printf(m, "Video Turbo Mode: %s\n",
1539 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1540 seq_printf(m, "HW control enabled: %s\n",
1541 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1542 seq_printf(m, "SW control enabled: %s\n",
1543 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1544 GEN6_RP_MEDIA_SW_MODE));
1545 seq_printf(m, "RC1e Enabled: %s\n",
1546 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1547 seq_printf(m, "RC6 Enabled: %s\n",
1548 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1549 seq_printf(m, "Deep RC6 Enabled: %s\n",
1550 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1551 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1552 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1553 seq_puts(m, "Current RC state: ");
1554 switch (gt_core_status & GEN6_RCn_MASK) {
1555 case GEN6_RC0:
1556 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1557 seq_puts(m, "Core Power Down\n");
1558 else
1559 seq_puts(m, "on\n");
1560 break;
1561 case GEN6_RC3:
1562 seq_puts(m, "RC3\n");
1563 break;
1564 case GEN6_RC6:
1565 seq_puts(m, "RC6\n");
1566 break;
1567 case GEN6_RC7:
1568 seq_puts(m, "RC7\n");
1569 break;
1570 default:
1571 seq_puts(m, "Unknown\n");
1572 break;
1573 }
1574
1575 seq_printf(m, "Core Power Down: %s\n",
1576 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1577
1578 /* Not exactly sure what this is */
1579 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1580 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1581 seq_printf(m, "RC6 residency since boot: %u\n",
1582 I915_READ(GEN6_GT_GFX_RC6));
1583 seq_printf(m, "RC6+ residency since boot: %u\n",
1584 I915_READ(GEN6_GT_GFX_RC6p));
1585 seq_printf(m, "RC6++ residency since boot: %u\n",
1586 I915_READ(GEN6_GT_GFX_RC6pp));
1587
1588 seq_printf(m, "RC6 voltage: %dmV\n",
1589 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1590 seq_printf(m, "RC6+ voltage: %dmV\n",
1591 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1592 seq_printf(m, "RC6++ voltage: %dmV\n",
1593 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1594 return 0;
1595 }
1596
1597 static int i915_drpc_info(struct seq_file *m, void *unused)
1598 {
1599 struct drm_info_node *node = m->private;
1600 struct drm_device *dev = node->minor->dev;
1601
1602 if (IS_VALLEYVIEW(dev))
1603 return vlv_drpc_info(m);
1604 else if (INTEL_INFO(dev)->gen >= 6)
1605 return gen6_drpc_info(m);
1606 else
1607 return ironlake_drpc_info(m);
1608 }
1609
1610 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1611 {
1612 struct drm_info_node *node = m->private;
1613 struct drm_device *dev = node->minor->dev;
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615
1616 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1617 dev_priv->fb_tracking.busy_bits);
1618
1619 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1620 dev_priv->fb_tracking.flip_bits);
1621
1622 return 0;
1623 }
1624
1625 static int i915_fbc_status(struct seq_file *m, void *unused)
1626 {
1627 struct drm_info_node *node = m->private;
1628 struct drm_device *dev = node->minor->dev;
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630
1631 if (!HAS_FBC(dev)) {
1632 seq_puts(m, "FBC unsupported on this chipset\n");
1633 return 0;
1634 }
1635
1636 intel_runtime_pm_get(dev_priv);
1637 mutex_lock(&dev_priv->fbc.lock);
1638
1639 if (intel_fbc_enabled(dev_priv))
1640 seq_puts(m, "FBC enabled\n");
1641 else
1642 seq_printf(m, "FBC disabled: %s\n",
1643 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1644
1645 if (INTEL_INFO(dev_priv)->gen >= 7)
1646 seq_printf(m, "Compressing: %s\n",
1647 yesno(I915_READ(FBC_STATUS2) &
1648 FBC_COMPRESSION_MASK));
1649
1650 mutex_unlock(&dev_priv->fbc.lock);
1651 intel_runtime_pm_put(dev_priv);
1652
1653 return 0;
1654 }
1655
1656 static int i915_fbc_fc_get(void *data, u64 *val)
1657 {
1658 struct drm_device *dev = data;
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1662 return -ENODEV;
1663
1664 *val = dev_priv->fbc.false_color;
1665
1666 return 0;
1667 }
1668
1669 static int i915_fbc_fc_set(void *data, u64 val)
1670 {
1671 struct drm_device *dev = data;
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 u32 reg;
1674
1675 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1676 return -ENODEV;
1677
1678 mutex_lock(&dev_priv->fbc.lock);
1679
1680 reg = I915_READ(ILK_DPFC_CONTROL);
1681 dev_priv->fbc.false_color = val;
1682
1683 I915_WRITE(ILK_DPFC_CONTROL, val ?
1684 (reg | FBC_CTL_FALSE_COLOR) :
1685 (reg & ~FBC_CTL_FALSE_COLOR));
1686
1687 mutex_unlock(&dev_priv->fbc.lock);
1688 return 0;
1689 }
1690
1691 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1692 i915_fbc_fc_get, i915_fbc_fc_set,
1693 "%llu\n");
1694
1695 static int i915_ips_status(struct seq_file *m, void *unused)
1696 {
1697 struct drm_info_node *node = m->private;
1698 struct drm_device *dev = node->minor->dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700
1701 if (!HAS_IPS(dev)) {
1702 seq_puts(m, "not supported\n");
1703 return 0;
1704 }
1705
1706 intel_runtime_pm_get(dev_priv);
1707
1708 seq_printf(m, "Enabled by kernel parameter: %s\n",
1709 yesno(i915.enable_ips));
1710
1711 if (INTEL_INFO(dev)->gen >= 8) {
1712 seq_puts(m, "Currently: unknown\n");
1713 } else {
1714 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1715 seq_puts(m, "Currently: enabled\n");
1716 else
1717 seq_puts(m, "Currently: disabled\n");
1718 }
1719
1720 intel_runtime_pm_put(dev_priv);
1721
1722 return 0;
1723 }
1724
1725 static int i915_sr_status(struct seq_file *m, void *unused)
1726 {
1727 struct drm_info_node *node = m->private;
1728 struct drm_device *dev = node->minor->dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730 bool sr_enabled = false;
1731
1732 intel_runtime_pm_get(dev_priv);
1733
1734 if (HAS_PCH_SPLIT(dev))
1735 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1736 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1737 IS_I945G(dev) || IS_I945GM(dev))
1738 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1739 else if (IS_I915GM(dev))
1740 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1741 else if (IS_PINEVIEW(dev))
1742 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1743 else if (IS_VALLEYVIEW(dev))
1744 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1745
1746 intel_runtime_pm_put(dev_priv);
1747
1748 seq_printf(m, "self-refresh: %s\n",
1749 sr_enabled ? "enabled" : "disabled");
1750
1751 return 0;
1752 }
1753
1754 static int i915_emon_status(struct seq_file *m, void *unused)
1755 {
1756 struct drm_info_node *node = m->private;
1757 struct drm_device *dev = node->minor->dev;
1758 struct drm_i915_private *dev_priv = dev->dev_private;
1759 unsigned long temp, chipset, gfx;
1760 int ret;
1761
1762 if (!IS_GEN5(dev))
1763 return -ENODEV;
1764
1765 ret = mutex_lock_interruptible(&dev->struct_mutex);
1766 if (ret)
1767 return ret;
1768
1769 temp = i915_mch_val(dev_priv);
1770 chipset = i915_chipset_val(dev_priv);
1771 gfx = i915_gfx_val(dev_priv);
1772 mutex_unlock(&dev->struct_mutex);
1773
1774 seq_printf(m, "GMCH temp: %ld\n", temp);
1775 seq_printf(m, "Chipset power: %ld\n", chipset);
1776 seq_printf(m, "GFX power: %ld\n", gfx);
1777 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1778
1779 return 0;
1780 }
1781
1782 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1783 {
1784 struct drm_info_node *node = m->private;
1785 struct drm_device *dev = node->minor->dev;
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787 int ret = 0;
1788 int gpu_freq, ia_freq;
1789 unsigned int max_gpu_freq, min_gpu_freq;
1790
1791 if (!HAS_CORE_RING_FREQ(dev)) {
1792 seq_puts(m, "unsupported on this chipset\n");
1793 return 0;
1794 }
1795
1796 intel_runtime_pm_get(dev_priv);
1797
1798 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1799
1800 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1801 if (ret)
1802 goto out;
1803
1804 if (IS_SKYLAKE(dev)) {
1805 /* Convert GT frequency to 50 HZ units */
1806 min_gpu_freq =
1807 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1808 max_gpu_freq =
1809 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1810 } else {
1811 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1812 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1813 }
1814
1815 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1816
1817 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1818 ia_freq = gpu_freq;
1819 sandybridge_pcode_read(dev_priv,
1820 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1821 &ia_freq);
1822 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1823 intel_gpu_freq(dev_priv, (gpu_freq *
1824 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
1825 ((ia_freq >> 0) & 0xff) * 100,
1826 ((ia_freq >> 8) & 0xff) * 100);
1827 }
1828
1829 mutex_unlock(&dev_priv->rps.hw_lock);
1830
1831 out:
1832 intel_runtime_pm_put(dev_priv);
1833 return ret;
1834 }
1835
1836 static int i915_opregion(struct seq_file *m, void *unused)
1837 {
1838 struct drm_info_node *node = m->private;
1839 struct drm_device *dev = node->minor->dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct intel_opregion *opregion = &dev_priv->opregion;
1842 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1843 int ret;
1844
1845 if (data == NULL)
1846 return -ENOMEM;
1847
1848 ret = mutex_lock_interruptible(&dev->struct_mutex);
1849 if (ret)
1850 goto out;
1851
1852 if (opregion->header) {
1853 memcpy(data, opregion->header, OPREGION_SIZE);
1854 seq_write(m, data, OPREGION_SIZE);
1855 }
1856
1857 mutex_unlock(&dev->struct_mutex);
1858
1859 out:
1860 kfree(data);
1861 return 0;
1862 }
1863
1864 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1865 {
1866 struct drm_info_node *node = m->private;
1867 struct drm_device *dev = node->minor->dev;
1868 struct intel_fbdev *ifbdev = NULL;
1869 struct intel_framebuffer *fb;
1870 struct drm_framebuffer *drm_fb;
1871
1872 #ifdef CONFIG_DRM_FBDEV_EMULATION
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874
1875 ifbdev = dev_priv->fbdev;
1876 fb = to_intel_framebuffer(ifbdev->helper.fb);
1877
1878 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1879 fb->base.width,
1880 fb->base.height,
1881 fb->base.depth,
1882 fb->base.bits_per_pixel,
1883 fb->base.modifier[0],
1884 atomic_read(&fb->base.refcount.refcount));
1885 describe_obj(m, fb->obj);
1886 seq_putc(m, '\n');
1887 #endif
1888
1889 mutex_lock(&dev->mode_config.fb_lock);
1890 drm_for_each_fb(drm_fb, dev) {
1891 fb = to_intel_framebuffer(drm_fb);
1892 if (ifbdev && &fb->base == ifbdev->helper.fb)
1893 continue;
1894
1895 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1896 fb->base.width,
1897 fb->base.height,
1898 fb->base.depth,
1899 fb->base.bits_per_pixel,
1900 fb->base.modifier[0],
1901 atomic_read(&fb->base.refcount.refcount));
1902 describe_obj(m, fb->obj);
1903 seq_putc(m, '\n');
1904 }
1905 mutex_unlock(&dev->mode_config.fb_lock);
1906
1907 return 0;
1908 }
1909
1910 static void describe_ctx_ringbuf(struct seq_file *m,
1911 struct intel_ringbuffer *ringbuf)
1912 {
1913 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1914 ringbuf->space, ringbuf->head, ringbuf->tail,
1915 ringbuf->last_retired_head);
1916 }
1917
1918 static int i915_context_status(struct seq_file *m, void *unused)
1919 {
1920 struct drm_info_node *node = m->private;
1921 struct drm_device *dev = node->minor->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_engine_cs *ring;
1924 struct intel_context *ctx;
1925 int ret, i;
1926
1927 ret = mutex_lock_interruptible(&dev->struct_mutex);
1928 if (ret)
1929 return ret;
1930
1931 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1932 if (!i915.enable_execlists &&
1933 ctx->legacy_hw_ctx.rcs_state == NULL)
1934 continue;
1935
1936 seq_puts(m, "HW context ");
1937 describe_ctx(m, ctx);
1938 for_each_ring(ring, dev_priv, i) {
1939 if (ring->default_context == ctx)
1940 seq_printf(m, "(default context %s) ",
1941 ring->name);
1942 }
1943
1944 if (i915.enable_execlists) {
1945 seq_putc(m, '\n');
1946 for_each_ring(ring, dev_priv, i) {
1947 struct drm_i915_gem_object *ctx_obj =
1948 ctx->engine[i].state;
1949 struct intel_ringbuffer *ringbuf =
1950 ctx->engine[i].ringbuf;
1951
1952 seq_printf(m, "%s: ", ring->name);
1953 if (ctx_obj)
1954 describe_obj(m, ctx_obj);
1955 if (ringbuf)
1956 describe_ctx_ringbuf(m, ringbuf);
1957 seq_putc(m, '\n');
1958 }
1959 } else {
1960 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1961 }
1962
1963 seq_putc(m, '\n');
1964 }
1965
1966 mutex_unlock(&dev->struct_mutex);
1967
1968 return 0;
1969 }
1970
1971 static void i915_dump_lrc_obj(struct seq_file *m,
1972 struct intel_engine_cs *ring,
1973 struct drm_i915_gem_object *ctx_obj)
1974 {
1975 struct page *page;
1976 uint32_t *reg_state;
1977 int j;
1978 unsigned long ggtt_offset = 0;
1979
1980 if (ctx_obj == NULL) {
1981 seq_printf(m, "Context on %s with no gem object\n",
1982 ring->name);
1983 return;
1984 }
1985
1986 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1987 intel_execlists_ctx_id(ctx_obj));
1988
1989 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1990 seq_puts(m, "\tNot bound in GGTT\n");
1991 else
1992 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1993
1994 if (i915_gem_object_get_pages(ctx_obj)) {
1995 seq_puts(m, "\tFailed to get pages for context object\n");
1996 return;
1997 }
1998
1999 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2000 if (!WARN_ON(page == NULL)) {
2001 reg_state = kmap_atomic(page);
2002
2003 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2004 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2005 ggtt_offset + 4096 + (j * 4),
2006 reg_state[j], reg_state[j + 1],
2007 reg_state[j + 2], reg_state[j + 3]);
2008 }
2009 kunmap_atomic(reg_state);
2010 }
2011
2012 seq_putc(m, '\n');
2013 }
2014
2015 static int i915_dump_lrc(struct seq_file *m, void *unused)
2016 {
2017 struct drm_info_node *node = (struct drm_info_node *) m->private;
2018 struct drm_device *dev = node->minor->dev;
2019 struct drm_i915_private *dev_priv = dev->dev_private;
2020 struct intel_engine_cs *ring;
2021 struct intel_context *ctx;
2022 int ret, i;
2023
2024 if (!i915.enable_execlists) {
2025 seq_printf(m, "Logical Ring Contexts are disabled\n");
2026 return 0;
2027 }
2028
2029 ret = mutex_lock_interruptible(&dev->struct_mutex);
2030 if (ret)
2031 return ret;
2032
2033 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2034 for_each_ring(ring, dev_priv, i) {
2035 if (ring->default_context != ctx)
2036 i915_dump_lrc_obj(m, ring,
2037 ctx->engine[i].state);
2038 }
2039 }
2040
2041 mutex_unlock(&dev->struct_mutex);
2042
2043 return 0;
2044 }
2045
2046 static int i915_execlists(struct seq_file *m, void *data)
2047 {
2048 struct drm_info_node *node = (struct drm_info_node *)m->private;
2049 struct drm_device *dev = node->minor->dev;
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 struct intel_engine_cs *ring;
2052 u32 status_pointer;
2053 u8 read_pointer;
2054 u8 write_pointer;
2055 u32 status;
2056 u32 ctx_id;
2057 struct list_head *cursor;
2058 int ring_id, i;
2059 int ret;
2060
2061 if (!i915.enable_execlists) {
2062 seq_puts(m, "Logical Ring Contexts are disabled\n");
2063 return 0;
2064 }
2065
2066 ret = mutex_lock_interruptible(&dev->struct_mutex);
2067 if (ret)
2068 return ret;
2069
2070 intel_runtime_pm_get(dev_priv);
2071
2072 for_each_ring(ring, dev_priv, ring_id) {
2073 struct drm_i915_gem_request *head_req = NULL;
2074 int count = 0;
2075 unsigned long flags;
2076
2077 seq_printf(m, "%s\n", ring->name);
2078
2079 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2080 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2081 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2082 status, ctx_id);
2083
2084 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2085 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2086
2087 read_pointer = ring->next_context_status_buffer;
2088 write_pointer = status_pointer & 0x07;
2089 if (read_pointer > write_pointer)
2090 write_pointer += 6;
2091 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2092 read_pointer, write_pointer);
2093
2094 for (i = 0; i < 6; i++) {
2095 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2096 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2097
2098 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2099 i, status, ctx_id);
2100 }
2101
2102 spin_lock_irqsave(&ring->execlist_lock, flags);
2103 list_for_each(cursor, &ring->execlist_queue)
2104 count++;
2105 head_req = list_first_entry_or_null(&ring->execlist_queue,
2106 struct drm_i915_gem_request, execlist_link);
2107 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2108
2109 seq_printf(m, "\t%d requests in queue\n", count);
2110 if (head_req) {
2111 struct drm_i915_gem_object *ctx_obj;
2112
2113 ctx_obj = head_req->ctx->engine[ring_id].state;
2114 seq_printf(m, "\tHead request id: %u\n",
2115 intel_execlists_ctx_id(ctx_obj));
2116 seq_printf(m, "\tHead request tail: %u\n",
2117 head_req->tail);
2118 }
2119
2120 seq_putc(m, '\n');
2121 }
2122
2123 intel_runtime_pm_put(dev_priv);
2124 mutex_unlock(&dev->struct_mutex);
2125
2126 return 0;
2127 }
2128
2129 static const char *swizzle_string(unsigned swizzle)
2130 {
2131 switch (swizzle) {
2132 case I915_BIT_6_SWIZZLE_NONE:
2133 return "none";
2134 case I915_BIT_6_SWIZZLE_9:
2135 return "bit9";
2136 case I915_BIT_6_SWIZZLE_9_10:
2137 return "bit9/bit10";
2138 case I915_BIT_6_SWIZZLE_9_11:
2139 return "bit9/bit11";
2140 case I915_BIT_6_SWIZZLE_9_10_11:
2141 return "bit9/bit10/bit11";
2142 case I915_BIT_6_SWIZZLE_9_17:
2143 return "bit9/bit17";
2144 case I915_BIT_6_SWIZZLE_9_10_17:
2145 return "bit9/bit10/bit17";
2146 case I915_BIT_6_SWIZZLE_UNKNOWN:
2147 return "unknown";
2148 }
2149
2150 return "bug";
2151 }
2152
2153 static int i915_swizzle_info(struct seq_file *m, void *data)
2154 {
2155 struct drm_info_node *node = m->private;
2156 struct drm_device *dev = node->minor->dev;
2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 int ret;
2159
2160 ret = mutex_lock_interruptible(&dev->struct_mutex);
2161 if (ret)
2162 return ret;
2163 intel_runtime_pm_get(dev_priv);
2164
2165 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2166 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2167 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2168 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2169
2170 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2171 seq_printf(m, "DDC = 0x%08x\n",
2172 I915_READ(DCC));
2173 seq_printf(m, "DDC2 = 0x%08x\n",
2174 I915_READ(DCC2));
2175 seq_printf(m, "C0DRB3 = 0x%04x\n",
2176 I915_READ16(C0DRB3));
2177 seq_printf(m, "C1DRB3 = 0x%04x\n",
2178 I915_READ16(C1DRB3));
2179 } else if (INTEL_INFO(dev)->gen >= 6) {
2180 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2181 I915_READ(MAD_DIMM_C0));
2182 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2183 I915_READ(MAD_DIMM_C1));
2184 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2185 I915_READ(MAD_DIMM_C2));
2186 seq_printf(m, "TILECTL = 0x%08x\n",
2187 I915_READ(TILECTL));
2188 if (INTEL_INFO(dev)->gen >= 8)
2189 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2190 I915_READ(GAMTARBMODE));
2191 else
2192 seq_printf(m, "ARB_MODE = 0x%08x\n",
2193 I915_READ(ARB_MODE));
2194 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2195 I915_READ(DISP_ARB_CTL));
2196 }
2197
2198 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2199 seq_puts(m, "L-shaped memory detected\n");
2200
2201 intel_runtime_pm_put(dev_priv);
2202 mutex_unlock(&dev->struct_mutex);
2203
2204 return 0;
2205 }
2206
2207 static int per_file_ctx(int id, void *ptr, void *data)
2208 {
2209 struct intel_context *ctx = ptr;
2210 struct seq_file *m = data;
2211 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2212
2213 if (!ppgtt) {
2214 seq_printf(m, " no ppgtt for context %d\n",
2215 ctx->user_handle);
2216 return 0;
2217 }
2218
2219 if (i915_gem_context_is_default(ctx))
2220 seq_puts(m, " default context:\n");
2221 else
2222 seq_printf(m, " context %d:\n", ctx->user_handle);
2223 ppgtt->debug_dump(ppgtt, m);
2224
2225 return 0;
2226 }
2227
2228 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2229 {
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 struct intel_engine_cs *ring;
2232 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2233 int unused, i;
2234
2235 if (!ppgtt)
2236 return;
2237
2238 for_each_ring(ring, dev_priv, unused) {
2239 seq_printf(m, "%s\n", ring->name);
2240 for (i = 0; i < 4; i++) {
2241 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2242 pdp <<= 32;
2243 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2244 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2245 }
2246 }
2247 }
2248
2249 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2250 {
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2252 struct intel_engine_cs *ring;
2253 int i;
2254
2255 if (INTEL_INFO(dev)->gen == 6)
2256 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2257
2258 for_each_ring(ring, dev_priv, i) {
2259 seq_printf(m, "%s\n", ring->name);
2260 if (INTEL_INFO(dev)->gen == 7)
2261 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2262 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2263 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2264 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2265 }
2266 if (dev_priv->mm.aliasing_ppgtt) {
2267 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2268
2269 seq_puts(m, "aliasing PPGTT:\n");
2270 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2271
2272 ppgtt->debug_dump(ppgtt, m);
2273 }
2274
2275 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2276 }
2277
2278 static int i915_ppgtt_info(struct seq_file *m, void *data)
2279 {
2280 struct drm_info_node *node = m->private;
2281 struct drm_device *dev = node->minor->dev;
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_file *file;
2284
2285 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2286 if (ret)
2287 return ret;
2288 intel_runtime_pm_get(dev_priv);
2289
2290 if (INTEL_INFO(dev)->gen >= 8)
2291 gen8_ppgtt_info(m, dev);
2292 else if (INTEL_INFO(dev)->gen >= 6)
2293 gen6_ppgtt_info(m, dev);
2294
2295 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2296 struct drm_i915_file_private *file_priv = file->driver_priv;
2297 struct task_struct *task;
2298
2299 task = get_pid_task(file->pid, PIDTYPE_PID);
2300 if (!task) {
2301 ret = -ESRCH;
2302 goto out_put;
2303 }
2304 seq_printf(m, "\nproc: %s\n", task->comm);
2305 put_task_struct(task);
2306 idr_for_each(&file_priv->context_idr, per_file_ctx,
2307 (void *)(unsigned long)m);
2308 }
2309
2310 out_put:
2311 intel_runtime_pm_put(dev_priv);
2312 mutex_unlock(&dev->struct_mutex);
2313
2314 return ret;
2315 }
2316
2317 static int count_irq_waiters(struct drm_i915_private *i915)
2318 {
2319 struct intel_engine_cs *ring;
2320 int count = 0;
2321 int i;
2322
2323 for_each_ring(ring, i915, i)
2324 count += ring->irq_refcount;
2325
2326 return count;
2327 }
2328
2329 static int i915_rps_boost_info(struct seq_file *m, void *data)
2330 {
2331 struct drm_info_node *node = m->private;
2332 struct drm_device *dev = node->minor->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct drm_file *file;
2335
2336 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2337 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2338 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2339 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2340 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2341 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2342 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2343 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2344 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2345 spin_lock(&dev_priv->rps.client_lock);
2346 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2347 struct drm_i915_file_private *file_priv = file->driver_priv;
2348 struct task_struct *task;
2349
2350 rcu_read_lock();
2351 task = pid_task(file->pid, PIDTYPE_PID);
2352 seq_printf(m, "%s [%d]: %d boosts%s\n",
2353 task ? task->comm : "<unknown>",
2354 task ? task->pid : -1,
2355 file_priv->rps.boosts,
2356 list_empty(&file_priv->rps.link) ? "" : ", active");
2357 rcu_read_unlock();
2358 }
2359 seq_printf(m, "Semaphore boosts: %d%s\n",
2360 dev_priv->rps.semaphores.boosts,
2361 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2362 seq_printf(m, "MMIO flip boosts: %d%s\n",
2363 dev_priv->rps.mmioflips.boosts,
2364 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2365 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2366 spin_unlock(&dev_priv->rps.client_lock);
2367
2368 return 0;
2369 }
2370
2371 static int i915_llc(struct seq_file *m, void *data)
2372 {
2373 struct drm_info_node *node = m->private;
2374 struct drm_device *dev = node->minor->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376
2377 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2378 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2379 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2380
2381 return 0;
2382 }
2383
2384 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2385 {
2386 struct drm_info_node *node = m->private;
2387 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2388 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2389 u32 tmp, i;
2390
2391 if (!HAS_GUC_UCODE(dev_priv->dev))
2392 return 0;
2393
2394 seq_printf(m, "GuC firmware status:\n");
2395 seq_printf(m, "\tpath: %s\n",
2396 guc_fw->guc_fw_path);
2397 seq_printf(m, "\tfetch: %s\n",
2398 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2399 seq_printf(m, "\tload: %s\n",
2400 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2401 seq_printf(m, "\tversion wanted: %d.%d\n",
2402 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2403 seq_printf(m, "\tversion found: %d.%d\n",
2404 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2405
2406 tmp = I915_READ(GUC_STATUS);
2407
2408 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2409 seq_printf(m, "\tBootrom status = 0x%x\n",
2410 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2411 seq_printf(m, "\tuKernel status = 0x%x\n",
2412 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2413 seq_printf(m, "\tMIA Core status = 0x%x\n",
2414 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2415 seq_puts(m, "\nScratch registers:\n");
2416 for (i = 0; i < 16; i++)
2417 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2418
2419 return 0;
2420 }
2421
2422 static void i915_guc_client_info(struct seq_file *m,
2423 struct drm_i915_private *dev_priv,
2424 struct i915_guc_client *client)
2425 {
2426 struct intel_engine_cs *ring;
2427 uint64_t tot = 0;
2428 uint32_t i;
2429
2430 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2431 client->priority, client->ctx_index, client->proc_desc_offset);
2432 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2433 client->doorbell_id, client->doorbell_offset, client->cookie);
2434 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2435 client->wq_size, client->wq_offset, client->wq_tail);
2436
2437 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2438 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2439 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2440
2441 for_each_ring(ring, dev_priv, i) {
2442 seq_printf(m, "\tSubmissions: %llu %s\n",
2443 client->submissions[i],
2444 ring->name);
2445 tot += client->submissions[i];
2446 }
2447 seq_printf(m, "\tTotal: %llu\n", tot);
2448 }
2449
2450 static int i915_guc_info(struct seq_file *m, void *data)
2451 {
2452 struct drm_info_node *node = m->private;
2453 struct drm_device *dev = node->minor->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_guc guc;
2456 struct i915_guc_client client = {};
2457 struct intel_engine_cs *ring;
2458 enum intel_ring_id i;
2459 u64 total = 0;
2460
2461 if (!HAS_GUC_SCHED(dev_priv->dev))
2462 return 0;
2463
2464 /* Take a local copy of the GuC data, so we can dump it at leisure */
2465 spin_lock(&dev_priv->guc.host2guc_lock);
2466 guc = dev_priv->guc;
2467 if (guc.execbuf_client) {
2468 spin_lock(&guc.execbuf_client->wq_lock);
2469 client = *guc.execbuf_client;
2470 spin_unlock(&guc.execbuf_client->wq_lock);
2471 }
2472 spin_unlock(&dev_priv->guc.host2guc_lock);
2473
2474 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2475 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2476 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2477 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2478 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2479
2480 seq_printf(m, "\nGuC submissions:\n");
2481 for_each_ring(ring, dev_priv, i) {
2482 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2483 ring->name, guc.submissions[i],
2484 guc.last_seqno[i], guc.last_seqno[i]);
2485 total += guc.submissions[i];
2486 }
2487 seq_printf(m, "\t%s: %llu\n", "Total", total);
2488
2489 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2490 i915_guc_client_info(m, dev_priv, &client);
2491
2492 /* Add more as required ... */
2493
2494 return 0;
2495 }
2496
2497 static int i915_guc_log_dump(struct seq_file *m, void *data)
2498 {
2499 struct drm_info_node *node = m->private;
2500 struct drm_device *dev = node->minor->dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2503 u32 *log;
2504 int i = 0, pg;
2505
2506 if (!log_obj)
2507 return 0;
2508
2509 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2510 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2511
2512 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2513 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2514 *(log + i), *(log + i + 1),
2515 *(log + i + 2), *(log + i + 3));
2516
2517 kunmap_atomic(log);
2518 }
2519
2520 seq_putc(m, '\n');
2521
2522 return 0;
2523 }
2524
2525 static int i915_edp_psr_status(struct seq_file *m, void *data)
2526 {
2527 struct drm_info_node *node = m->private;
2528 struct drm_device *dev = node->minor->dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 u32 psrperf = 0;
2531 u32 stat[3];
2532 enum pipe pipe;
2533 bool enabled = false;
2534
2535 if (!HAS_PSR(dev)) {
2536 seq_puts(m, "PSR not supported\n");
2537 return 0;
2538 }
2539
2540 intel_runtime_pm_get(dev_priv);
2541
2542 mutex_lock(&dev_priv->psr.lock);
2543 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2544 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2545 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2546 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2547 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2548 dev_priv->psr.busy_frontbuffer_bits);
2549 seq_printf(m, "Re-enable work scheduled: %s\n",
2550 yesno(work_busy(&dev_priv->psr.work.work)));
2551
2552 if (HAS_DDI(dev))
2553 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2554 else {
2555 for_each_pipe(dev_priv, pipe) {
2556 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2557 VLV_EDP_PSR_CURR_STATE_MASK;
2558 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2559 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2560 enabled = true;
2561 }
2562 }
2563 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2564
2565 if (!HAS_DDI(dev))
2566 for_each_pipe(dev_priv, pipe) {
2567 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2568 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2569 seq_printf(m, " pipe %c", pipe_name(pipe));
2570 }
2571 seq_puts(m, "\n");
2572
2573 /* CHV PSR has no kind of performance counter */
2574 if (HAS_DDI(dev)) {
2575 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2576 EDP_PSR_PERF_CNT_MASK;
2577
2578 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2579 }
2580 mutex_unlock(&dev_priv->psr.lock);
2581
2582 intel_runtime_pm_put(dev_priv);
2583 return 0;
2584 }
2585
2586 static int i915_sink_crc(struct seq_file *m, void *data)
2587 {
2588 struct drm_info_node *node = m->private;
2589 struct drm_device *dev = node->minor->dev;
2590 struct intel_encoder *encoder;
2591 struct intel_connector *connector;
2592 struct intel_dp *intel_dp = NULL;
2593 int ret;
2594 u8 crc[6];
2595
2596 drm_modeset_lock_all(dev);
2597 for_each_intel_connector(dev, connector) {
2598
2599 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2600 continue;
2601
2602 if (!connector->base.encoder)
2603 continue;
2604
2605 encoder = to_intel_encoder(connector->base.encoder);
2606 if (encoder->type != INTEL_OUTPUT_EDP)
2607 continue;
2608
2609 intel_dp = enc_to_intel_dp(&encoder->base);
2610
2611 ret = intel_dp_sink_crc(intel_dp, crc);
2612 if (ret)
2613 goto out;
2614
2615 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2616 crc[0], crc[1], crc[2],
2617 crc[3], crc[4], crc[5]);
2618 goto out;
2619 }
2620 ret = -ENODEV;
2621 out:
2622 drm_modeset_unlock_all(dev);
2623 return ret;
2624 }
2625
2626 static int i915_energy_uJ(struct seq_file *m, void *data)
2627 {
2628 struct drm_info_node *node = m->private;
2629 struct drm_device *dev = node->minor->dev;
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631 u64 power;
2632 u32 units;
2633
2634 if (INTEL_INFO(dev)->gen < 6)
2635 return -ENODEV;
2636
2637 intel_runtime_pm_get(dev_priv);
2638
2639 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2640 power = (power & 0x1f00) >> 8;
2641 units = 1000000 / (1 << power); /* convert to uJ */
2642 power = I915_READ(MCH_SECP_NRG_STTS);
2643 power *= units;
2644
2645 intel_runtime_pm_put(dev_priv);
2646
2647 seq_printf(m, "%llu", (long long unsigned)power);
2648
2649 return 0;
2650 }
2651
2652 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2653 {
2654 struct drm_info_node *node = m->private;
2655 struct drm_device *dev = node->minor->dev;
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657
2658 if (!HAS_RUNTIME_PM(dev)) {
2659 seq_puts(m, "not supported\n");
2660 return 0;
2661 }
2662
2663 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2664 seq_printf(m, "IRQs disabled: %s\n",
2665 yesno(!intel_irqs_enabled(dev_priv)));
2666 #ifdef CONFIG_PM
2667 seq_printf(m, "Usage count: %d\n",
2668 atomic_read(&dev->dev->power.usage_count));
2669 #else
2670 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2671 #endif
2672
2673 return 0;
2674 }
2675
2676 static const char *power_domain_str(enum intel_display_power_domain domain)
2677 {
2678 switch (domain) {
2679 case POWER_DOMAIN_PIPE_A:
2680 return "PIPE_A";
2681 case POWER_DOMAIN_PIPE_B:
2682 return "PIPE_B";
2683 case POWER_DOMAIN_PIPE_C:
2684 return "PIPE_C";
2685 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2686 return "PIPE_A_PANEL_FITTER";
2687 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2688 return "PIPE_B_PANEL_FITTER";
2689 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2690 return "PIPE_C_PANEL_FITTER";
2691 case POWER_DOMAIN_TRANSCODER_A:
2692 return "TRANSCODER_A";
2693 case POWER_DOMAIN_TRANSCODER_B:
2694 return "TRANSCODER_B";
2695 case POWER_DOMAIN_TRANSCODER_C:
2696 return "TRANSCODER_C";
2697 case POWER_DOMAIN_TRANSCODER_EDP:
2698 return "TRANSCODER_EDP";
2699 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2700 return "PORT_DDI_A_2_LANES";
2701 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2702 return "PORT_DDI_A_4_LANES";
2703 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2704 return "PORT_DDI_B_2_LANES";
2705 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2706 return "PORT_DDI_B_4_LANES";
2707 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2708 return "PORT_DDI_C_2_LANES";
2709 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2710 return "PORT_DDI_C_4_LANES";
2711 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2712 return "PORT_DDI_D_2_LANES";
2713 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2714 return "PORT_DDI_D_4_LANES";
2715 case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2716 return "PORT_DDI_E_2_LANES";
2717 case POWER_DOMAIN_PORT_DSI:
2718 return "PORT_DSI";
2719 case POWER_DOMAIN_PORT_CRT:
2720 return "PORT_CRT";
2721 case POWER_DOMAIN_PORT_OTHER:
2722 return "PORT_OTHER";
2723 case POWER_DOMAIN_VGA:
2724 return "VGA";
2725 case POWER_DOMAIN_AUDIO:
2726 return "AUDIO";
2727 case POWER_DOMAIN_PLLS:
2728 return "PLLS";
2729 case POWER_DOMAIN_AUX_A:
2730 return "AUX_A";
2731 case POWER_DOMAIN_AUX_B:
2732 return "AUX_B";
2733 case POWER_DOMAIN_AUX_C:
2734 return "AUX_C";
2735 case POWER_DOMAIN_AUX_D:
2736 return "AUX_D";
2737 case POWER_DOMAIN_GMBUS:
2738 return "GMBUS";
2739 case POWER_DOMAIN_INIT:
2740 return "INIT";
2741 default:
2742 MISSING_CASE(domain);
2743 return "?";
2744 }
2745 }
2746
2747 static int i915_power_domain_info(struct seq_file *m, void *unused)
2748 {
2749 struct drm_info_node *node = m->private;
2750 struct drm_device *dev = node->minor->dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2753 int i;
2754
2755 mutex_lock(&power_domains->lock);
2756
2757 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2758 for (i = 0; i < power_domains->power_well_count; i++) {
2759 struct i915_power_well *power_well;
2760 enum intel_display_power_domain power_domain;
2761
2762 power_well = &power_domains->power_wells[i];
2763 seq_printf(m, "%-25s %d\n", power_well->name,
2764 power_well->count);
2765
2766 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2767 power_domain++) {
2768 if (!(BIT(power_domain) & power_well->domains))
2769 continue;
2770
2771 seq_printf(m, " %-23s %d\n",
2772 power_domain_str(power_domain),
2773 power_domains->domain_use_count[power_domain]);
2774 }
2775 }
2776
2777 mutex_unlock(&power_domains->lock);
2778
2779 return 0;
2780 }
2781
2782 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2783 struct drm_display_mode *mode)
2784 {
2785 int i;
2786
2787 for (i = 0; i < tabs; i++)
2788 seq_putc(m, '\t');
2789
2790 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2791 mode->base.id, mode->name,
2792 mode->vrefresh, mode->clock,
2793 mode->hdisplay, mode->hsync_start,
2794 mode->hsync_end, mode->htotal,
2795 mode->vdisplay, mode->vsync_start,
2796 mode->vsync_end, mode->vtotal,
2797 mode->type, mode->flags);
2798 }
2799
2800 static void intel_encoder_info(struct seq_file *m,
2801 struct intel_crtc *intel_crtc,
2802 struct intel_encoder *intel_encoder)
2803 {
2804 struct drm_info_node *node = m->private;
2805 struct drm_device *dev = node->minor->dev;
2806 struct drm_crtc *crtc = &intel_crtc->base;
2807 struct intel_connector *intel_connector;
2808 struct drm_encoder *encoder;
2809
2810 encoder = &intel_encoder->base;
2811 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2812 encoder->base.id, encoder->name);
2813 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2814 struct drm_connector *connector = &intel_connector->base;
2815 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2816 connector->base.id,
2817 connector->name,
2818 drm_get_connector_status_name(connector->status));
2819 if (connector->status == connector_status_connected) {
2820 struct drm_display_mode *mode = &crtc->mode;
2821 seq_printf(m, ", mode:\n");
2822 intel_seq_print_mode(m, 2, mode);
2823 } else {
2824 seq_putc(m, '\n');
2825 }
2826 }
2827 }
2828
2829 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2830 {
2831 struct drm_info_node *node = m->private;
2832 struct drm_device *dev = node->minor->dev;
2833 struct drm_crtc *crtc = &intel_crtc->base;
2834 struct intel_encoder *intel_encoder;
2835 struct drm_plane_state *plane_state = crtc->primary->state;
2836 struct drm_framebuffer *fb = plane_state->fb;
2837
2838 if (fb)
2839 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2840 fb->base.id, plane_state->src_x >> 16,
2841 plane_state->src_y >> 16, fb->width, fb->height);
2842 else
2843 seq_puts(m, "\tprimary plane disabled\n");
2844 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2845 intel_encoder_info(m, intel_crtc, intel_encoder);
2846 }
2847
2848 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2849 {
2850 struct drm_display_mode *mode = panel->fixed_mode;
2851
2852 seq_printf(m, "\tfixed mode:\n");
2853 intel_seq_print_mode(m, 2, mode);
2854 }
2855
2856 static void intel_dp_info(struct seq_file *m,
2857 struct intel_connector *intel_connector)
2858 {
2859 struct intel_encoder *intel_encoder = intel_connector->encoder;
2860 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2861
2862 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2863 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2864 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2865 intel_panel_info(m, &intel_connector->panel);
2866 }
2867
2868 static void intel_hdmi_info(struct seq_file *m,
2869 struct intel_connector *intel_connector)
2870 {
2871 struct intel_encoder *intel_encoder = intel_connector->encoder;
2872 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2873
2874 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2875 }
2876
2877 static void intel_lvds_info(struct seq_file *m,
2878 struct intel_connector *intel_connector)
2879 {
2880 intel_panel_info(m, &intel_connector->panel);
2881 }
2882
2883 static void intel_connector_info(struct seq_file *m,
2884 struct drm_connector *connector)
2885 {
2886 struct intel_connector *intel_connector = to_intel_connector(connector);
2887 struct intel_encoder *intel_encoder = intel_connector->encoder;
2888 struct drm_display_mode *mode;
2889
2890 seq_printf(m, "connector %d: type %s, status: %s\n",
2891 connector->base.id, connector->name,
2892 drm_get_connector_status_name(connector->status));
2893 if (connector->status == connector_status_connected) {
2894 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2895 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2896 connector->display_info.width_mm,
2897 connector->display_info.height_mm);
2898 seq_printf(m, "\tsubpixel order: %s\n",
2899 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2900 seq_printf(m, "\tCEA rev: %d\n",
2901 connector->display_info.cea_rev);
2902 }
2903 if (intel_encoder) {
2904 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2905 intel_encoder->type == INTEL_OUTPUT_EDP)
2906 intel_dp_info(m, intel_connector);
2907 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2908 intel_hdmi_info(m, intel_connector);
2909 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2910 intel_lvds_info(m, intel_connector);
2911 }
2912
2913 seq_printf(m, "\tmodes:\n");
2914 list_for_each_entry(mode, &connector->modes, head)
2915 intel_seq_print_mode(m, 2, mode);
2916 }
2917
2918 static bool cursor_active(struct drm_device *dev, int pipe)
2919 {
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 u32 state;
2922
2923 if (IS_845G(dev) || IS_I865G(dev))
2924 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2925 else
2926 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2927
2928 return state;
2929 }
2930
2931 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2932 {
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 u32 pos;
2935
2936 pos = I915_READ(CURPOS(pipe));
2937
2938 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2939 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2940 *x = -*x;
2941
2942 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2943 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2944 *y = -*y;
2945
2946 return cursor_active(dev, pipe);
2947 }
2948
2949 static int i915_display_info(struct seq_file *m, void *unused)
2950 {
2951 struct drm_info_node *node = m->private;
2952 struct drm_device *dev = node->minor->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 struct intel_crtc *crtc;
2955 struct drm_connector *connector;
2956
2957 intel_runtime_pm_get(dev_priv);
2958 drm_modeset_lock_all(dev);
2959 seq_printf(m, "CRTC info\n");
2960 seq_printf(m, "---------\n");
2961 for_each_intel_crtc(dev, crtc) {
2962 bool active;
2963 struct intel_crtc_state *pipe_config;
2964 int x, y;
2965
2966 pipe_config = to_intel_crtc_state(crtc->base.state);
2967
2968 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2969 crtc->base.base.id, pipe_name(crtc->pipe),
2970 yesno(pipe_config->base.active),
2971 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2972 if (pipe_config->base.active) {
2973 intel_crtc_info(m, crtc);
2974
2975 active = cursor_position(dev, crtc->pipe, &x, &y);
2976 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2977 yesno(crtc->cursor_base),
2978 x, y, crtc->base.cursor->state->crtc_w,
2979 crtc->base.cursor->state->crtc_h,
2980 crtc->cursor_addr, yesno(active));
2981 }
2982
2983 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2984 yesno(!crtc->cpu_fifo_underrun_disabled),
2985 yesno(!crtc->pch_fifo_underrun_disabled));
2986 }
2987
2988 seq_printf(m, "\n");
2989 seq_printf(m, "Connector info\n");
2990 seq_printf(m, "--------------\n");
2991 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2992 intel_connector_info(m, connector);
2993 }
2994 drm_modeset_unlock_all(dev);
2995 intel_runtime_pm_put(dev_priv);
2996
2997 return 0;
2998 }
2999
3000 static int i915_semaphore_status(struct seq_file *m, void *unused)
3001 {
3002 struct drm_info_node *node = (struct drm_info_node *) m->private;
3003 struct drm_device *dev = node->minor->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_engine_cs *ring;
3006 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3007 int i, j, ret;
3008
3009 if (!i915_semaphore_is_enabled(dev)) {
3010 seq_puts(m, "Semaphores are disabled\n");
3011 return 0;
3012 }
3013
3014 ret = mutex_lock_interruptible(&dev->struct_mutex);
3015 if (ret)
3016 return ret;
3017 intel_runtime_pm_get(dev_priv);
3018
3019 if (IS_BROADWELL(dev)) {
3020 struct page *page;
3021 uint64_t *seqno;
3022
3023 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3024
3025 seqno = (uint64_t *)kmap_atomic(page);
3026 for_each_ring(ring, dev_priv, i) {
3027 uint64_t offset;
3028
3029 seq_printf(m, "%s\n", ring->name);
3030
3031 seq_puts(m, " Last signal:");
3032 for (j = 0; j < num_rings; j++) {
3033 offset = i * I915_NUM_RINGS + j;
3034 seq_printf(m, "0x%08llx (0x%02llx) ",
3035 seqno[offset], offset * 8);
3036 }
3037 seq_putc(m, '\n');
3038
3039 seq_puts(m, " Last wait: ");
3040 for (j = 0; j < num_rings; j++) {
3041 offset = i + (j * I915_NUM_RINGS);
3042 seq_printf(m, "0x%08llx (0x%02llx) ",
3043 seqno[offset], offset * 8);
3044 }
3045 seq_putc(m, '\n');
3046
3047 }
3048 kunmap_atomic(seqno);
3049 } else {
3050 seq_puts(m, " Last signal:");
3051 for_each_ring(ring, dev_priv, i)
3052 for (j = 0; j < num_rings; j++)
3053 seq_printf(m, "0x%08x\n",
3054 I915_READ(ring->semaphore.mbox.signal[j]));
3055 seq_putc(m, '\n');
3056 }
3057
3058 seq_puts(m, "\nSync seqno:\n");
3059 for_each_ring(ring, dev_priv, i) {
3060 for (j = 0; j < num_rings; j++) {
3061 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3062 }
3063 seq_putc(m, '\n');
3064 }
3065 seq_putc(m, '\n');
3066
3067 intel_runtime_pm_put(dev_priv);
3068 mutex_unlock(&dev->struct_mutex);
3069 return 0;
3070 }
3071
3072 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3073 {
3074 struct drm_info_node *node = (struct drm_info_node *) m->private;
3075 struct drm_device *dev = node->minor->dev;
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 int i;
3078
3079 drm_modeset_lock_all(dev);
3080 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3081 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3082
3083 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3084 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3085 pll->config.crtc_mask, pll->active, yesno(pll->on));
3086 seq_printf(m, " tracked hardware state:\n");
3087 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3088 seq_printf(m, " dpll_md: 0x%08x\n",
3089 pll->config.hw_state.dpll_md);
3090 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3091 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3092 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3093 }
3094 drm_modeset_unlock_all(dev);
3095
3096 return 0;
3097 }
3098
3099 static int i915_wa_registers(struct seq_file *m, void *unused)
3100 {
3101 int i;
3102 int ret;
3103 struct drm_info_node *node = (struct drm_info_node *) m->private;
3104 struct drm_device *dev = node->minor->dev;
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106
3107 ret = mutex_lock_interruptible(&dev->struct_mutex);
3108 if (ret)
3109 return ret;
3110
3111 intel_runtime_pm_get(dev_priv);
3112
3113 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3114 for (i = 0; i < dev_priv->workarounds.count; ++i) {
3115 u32 addr, mask, value, read;
3116 bool ok;
3117
3118 addr = dev_priv->workarounds.reg[i].addr;
3119 mask = dev_priv->workarounds.reg[i].mask;
3120 value = dev_priv->workarounds.reg[i].value;
3121 read = I915_READ(addr);
3122 ok = (value & mask) == (read & mask);
3123 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3124 addr, value, mask, read, ok ? "OK" : "FAIL");
3125 }
3126
3127 intel_runtime_pm_put(dev_priv);
3128 mutex_unlock(&dev->struct_mutex);
3129
3130 return 0;
3131 }
3132
3133 static int i915_ddb_info(struct seq_file *m, void *unused)
3134 {
3135 struct drm_info_node *node = m->private;
3136 struct drm_device *dev = node->minor->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct skl_ddb_allocation *ddb;
3139 struct skl_ddb_entry *entry;
3140 enum pipe pipe;
3141 int plane;
3142
3143 if (INTEL_INFO(dev)->gen < 9)
3144 return 0;
3145
3146 drm_modeset_lock_all(dev);
3147
3148 ddb = &dev_priv->wm.skl_hw.ddb;
3149
3150 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3151
3152 for_each_pipe(dev_priv, pipe) {
3153 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3154
3155 for_each_plane(dev_priv, pipe, plane) {
3156 entry = &ddb->plane[pipe][plane];
3157 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3158 entry->start, entry->end,
3159 skl_ddb_entry_size(entry));
3160 }
3161
3162 entry = &ddb->plane[pipe][PLANE_CURSOR];
3163 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3164 entry->end, skl_ddb_entry_size(entry));
3165 }
3166
3167 drm_modeset_unlock_all(dev);
3168
3169 return 0;
3170 }
3171
3172 static void drrs_status_per_crtc(struct seq_file *m,
3173 struct drm_device *dev, struct intel_crtc *intel_crtc)
3174 {
3175 struct intel_encoder *intel_encoder;
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct i915_drrs *drrs = &dev_priv->drrs;
3178 int vrefresh = 0;
3179
3180 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3181 /* Encoder connected on this CRTC */
3182 switch (intel_encoder->type) {
3183 case INTEL_OUTPUT_EDP:
3184 seq_puts(m, "eDP:\n");
3185 break;
3186 case INTEL_OUTPUT_DSI:
3187 seq_puts(m, "DSI:\n");
3188 break;
3189 case INTEL_OUTPUT_HDMI:
3190 seq_puts(m, "HDMI:\n");
3191 break;
3192 case INTEL_OUTPUT_DISPLAYPORT:
3193 seq_puts(m, "DP:\n");
3194 break;
3195 default:
3196 seq_printf(m, "Other encoder (id=%d).\n",
3197 intel_encoder->type);
3198 return;
3199 }
3200 }
3201
3202 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3203 seq_puts(m, "\tVBT: DRRS_type: Static");
3204 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3205 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3206 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3207 seq_puts(m, "\tVBT: DRRS_type: None");
3208 else
3209 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3210
3211 seq_puts(m, "\n\n");
3212
3213 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3214 struct intel_panel *panel;
3215
3216 mutex_lock(&drrs->mutex);
3217 /* DRRS Supported */
3218 seq_puts(m, "\tDRRS Supported: Yes\n");
3219
3220 /* disable_drrs() will make drrs->dp NULL */
3221 if (!drrs->dp) {
3222 seq_puts(m, "Idleness DRRS: Disabled");
3223 mutex_unlock(&drrs->mutex);
3224 return;
3225 }
3226
3227 panel = &drrs->dp->attached_connector->panel;
3228 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3229 drrs->busy_frontbuffer_bits);
3230
3231 seq_puts(m, "\n\t\t");
3232 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3233 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3234 vrefresh = panel->fixed_mode->vrefresh;
3235 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3236 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3237 vrefresh = panel->downclock_mode->vrefresh;
3238 } else {
3239 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3240 drrs->refresh_rate_type);
3241 mutex_unlock(&drrs->mutex);
3242 return;
3243 }
3244 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3245
3246 seq_puts(m, "\n\t\t");
3247 mutex_unlock(&drrs->mutex);
3248 } else {
3249 /* DRRS not supported. Print the VBT parameter*/
3250 seq_puts(m, "\tDRRS Supported : No");
3251 }
3252 seq_puts(m, "\n");
3253 }
3254
3255 static int i915_drrs_status(struct seq_file *m, void *unused)
3256 {
3257 struct drm_info_node *node = m->private;
3258 struct drm_device *dev = node->minor->dev;
3259 struct intel_crtc *intel_crtc;
3260 int active_crtc_cnt = 0;
3261
3262 for_each_intel_crtc(dev, intel_crtc) {
3263 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3264
3265 if (intel_crtc->base.state->active) {
3266 active_crtc_cnt++;
3267 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3268
3269 drrs_status_per_crtc(m, dev, intel_crtc);
3270 }
3271
3272 drm_modeset_unlock(&intel_crtc->base.mutex);
3273 }
3274
3275 if (!active_crtc_cnt)
3276 seq_puts(m, "No active crtc found\n");
3277
3278 return 0;
3279 }
3280
3281 struct pipe_crc_info {
3282 const char *name;
3283 struct drm_device *dev;
3284 enum pipe pipe;
3285 };
3286
3287 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3288 {
3289 struct drm_info_node *node = (struct drm_info_node *) m->private;
3290 struct drm_device *dev = node->minor->dev;
3291 struct drm_encoder *encoder;
3292 struct intel_encoder *intel_encoder;
3293 struct intel_digital_port *intel_dig_port;
3294 drm_modeset_lock_all(dev);
3295 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3296 intel_encoder = to_intel_encoder(encoder);
3297 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3298 continue;
3299 intel_dig_port = enc_to_dig_port(encoder);
3300 if (!intel_dig_port->dp.can_mst)
3301 continue;
3302
3303 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3304 }
3305 drm_modeset_unlock_all(dev);
3306 return 0;
3307 }
3308
3309 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3310 {
3311 struct pipe_crc_info *info = inode->i_private;
3312 struct drm_i915_private *dev_priv = info->dev->dev_private;
3313 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3314
3315 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3316 return -ENODEV;
3317
3318 spin_lock_irq(&pipe_crc->lock);
3319
3320 if (pipe_crc->opened) {
3321 spin_unlock_irq(&pipe_crc->lock);
3322 return -EBUSY; /* already open */
3323 }
3324
3325 pipe_crc->opened = true;
3326 filep->private_data = inode->i_private;
3327
3328 spin_unlock_irq(&pipe_crc->lock);
3329
3330 return 0;
3331 }
3332
3333 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3334 {
3335 struct pipe_crc_info *info = inode->i_private;
3336 struct drm_i915_private *dev_priv = info->dev->dev_private;
3337 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3338
3339 spin_lock_irq(&pipe_crc->lock);
3340 pipe_crc->opened = false;
3341 spin_unlock_irq(&pipe_crc->lock);
3342
3343 return 0;
3344 }
3345
3346 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3347 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3348 /* account for \'0' */
3349 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3350
3351 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3352 {
3353 assert_spin_locked(&pipe_crc->lock);
3354 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3355 INTEL_PIPE_CRC_ENTRIES_NR);
3356 }
3357
3358 static ssize_t
3359 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3360 loff_t *pos)
3361 {
3362 struct pipe_crc_info *info = filep->private_data;
3363 struct drm_device *dev = info->dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3366 char buf[PIPE_CRC_BUFFER_LEN];
3367 int n_entries;
3368 ssize_t bytes_read;
3369
3370 /*
3371 * Don't allow user space to provide buffers not big enough to hold
3372 * a line of data.
3373 */
3374 if (count < PIPE_CRC_LINE_LEN)
3375 return -EINVAL;
3376
3377 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3378 return 0;
3379
3380 /* nothing to read */
3381 spin_lock_irq(&pipe_crc->lock);
3382 while (pipe_crc_data_count(pipe_crc) == 0) {
3383 int ret;
3384
3385 if (filep->f_flags & O_NONBLOCK) {
3386 spin_unlock_irq(&pipe_crc->lock);
3387 return -EAGAIN;
3388 }
3389
3390 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3391 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3392 if (ret) {
3393 spin_unlock_irq(&pipe_crc->lock);
3394 return ret;
3395 }
3396 }
3397
3398 /* We now have one or more entries to read */
3399 n_entries = count / PIPE_CRC_LINE_LEN;
3400
3401 bytes_read = 0;
3402 while (n_entries > 0) {
3403 struct intel_pipe_crc_entry *entry =
3404 &pipe_crc->entries[pipe_crc->tail];
3405 int ret;
3406
3407 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3408 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3409 break;
3410
3411 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3412 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3413
3414 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3415 "%8u %8x %8x %8x %8x %8x\n",
3416 entry->frame, entry->crc[0],
3417 entry->crc[1], entry->crc[2],
3418 entry->crc[3], entry->crc[4]);
3419
3420 spin_unlock_irq(&pipe_crc->lock);
3421
3422 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3423 if (ret == PIPE_CRC_LINE_LEN)
3424 return -EFAULT;
3425
3426 user_buf += PIPE_CRC_LINE_LEN;
3427 n_entries--;
3428
3429 spin_lock_irq(&pipe_crc->lock);
3430 }
3431
3432 spin_unlock_irq(&pipe_crc->lock);
3433
3434 return bytes_read;
3435 }
3436
3437 static const struct file_operations i915_pipe_crc_fops = {
3438 .owner = THIS_MODULE,
3439 .open = i915_pipe_crc_open,
3440 .read = i915_pipe_crc_read,
3441 .release = i915_pipe_crc_release,
3442 };
3443
3444 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3445 {
3446 .name = "i915_pipe_A_crc",
3447 .pipe = PIPE_A,
3448 },
3449 {
3450 .name = "i915_pipe_B_crc",
3451 .pipe = PIPE_B,
3452 },
3453 {
3454 .name = "i915_pipe_C_crc",
3455 .pipe = PIPE_C,
3456 },
3457 };
3458
3459 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3460 enum pipe pipe)
3461 {
3462 struct drm_device *dev = minor->dev;
3463 struct dentry *ent;
3464 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3465
3466 info->dev = dev;
3467 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3468 &i915_pipe_crc_fops);
3469 if (!ent)
3470 return -ENOMEM;
3471
3472 return drm_add_fake_info_node(minor, ent, info);
3473 }
3474
3475 static const char * const pipe_crc_sources[] = {
3476 "none",
3477 "plane1",
3478 "plane2",
3479 "pf",
3480 "pipe",
3481 "TV",
3482 "DP-B",
3483 "DP-C",
3484 "DP-D",
3485 "auto",
3486 };
3487
3488 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3489 {
3490 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3491 return pipe_crc_sources[source];
3492 }
3493
3494 static int display_crc_ctl_show(struct seq_file *m, void *data)
3495 {
3496 struct drm_device *dev = m->private;
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 int i;
3499
3500 for (i = 0; i < I915_MAX_PIPES; i++)
3501 seq_printf(m, "%c %s\n", pipe_name(i),
3502 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3503
3504 return 0;
3505 }
3506
3507 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3508 {
3509 struct drm_device *dev = inode->i_private;
3510
3511 return single_open(file, display_crc_ctl_show, dev);
3512 }
3513
3514 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3515 uint32_t *val)
3516 {
3517 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3518 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3519
3520 switch (*source) {
3521 case INTEL_PIPE_CRC_SOURCE_PIPE:
3522 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3523 break;
3524 case INTEL_PIPE_CRC_SOURCE_NONE:
3525 *val = 0;
3526 break;
3527 default:
3528 return -EINVAL;
3529 }
3530
3531 return 0;
3532 }
3533
3534 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3535 enum intel_pipe_crc_source *source)
3536 {
3537 struct intel_encoder *encoder;
3538 struct intel_crtc *crtc;
3539 struct intel_digital_port *dig_port;
3540 int ret = 0;
3541
3542 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3543
3544 drm_modeset_lock_all(dev);
3545 for_each_intel_encoder(dev, encoder) {
3546 if (!encoder->base.crtc)
3547 continue;
3548
3549 crtc = to_intel_crtc(encoder->base.crtc);
3550
3551 if (crtc->pipe != pipe)
3552 continue;
3553
3554 switch (encoder->type) {
3555 case INTEL_OUTPUT_TVOUT:
3556 *source = INTEL_PIPE_CRC_SOURCE_TV;
3557 break;
3558 case INTEL_OUTPUT_DISPLAYPORT:
3559 case INTEL_OUTPUT_EDP:
3560 dig_port = enc_to_dig_port(&encoder->base);
3561 switch (dig_port->port) {
3562 case PORT_B:
3563 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3564 break;
3565 case PORT_C:
3566 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3567 break;
3568 case PORT_D:
3569 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3570 break;
3571 default:
3572 WARN(1, "nonexisting DP port %c\n",
3573 port_name(dig_port->port));
3574 break;
3575 }
3576 break;
3577 default:
3578 break;
3579 }
3580 }
3581 drm_modeset_unlock_all(dev);
3582
3583 return ret;
3584 }
3585
3586 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3587 enum pipe pipe,
3588 enum intel_pipe_crc_source *source,
3589 uint32_t *val)
3590 {
3591 struct drm_i915_private *dev_priv = dev->dev_private;
3592 bool need_stable_symbols = false;
3593
3594 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3595 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3596 if (ret)
3597 return ret;
3598 }
3599
3600 switch (*source) {
3601 case INTEL_PIPE_CRC_SOURCE_PIPE:
3602 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3603 break;
3604 case INTEL_PIPE_CRC_SOURCE_DP_B:
3605 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3606 need_stable_symbols = true;
3607 break;
3608 case INTEL_PIPE_CRC_SOURCE_DP_C:
3609 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3610 need_stable_symbols = true;
3611 break;
3612 case INTEL_PIPE_CRC_SOURCE_DP_D:
3613 if (!IS_CHERRYVIEW(dev))
3614 return -EINVAL;
3615 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3616 need_stable_symbols = true;
3617 break;
3618 case INTEL_PIPE_CRC_SOURCE_NONE:
3619 *val = 0;
3620 break;
3621 default:
3622 return -EINVAL;
3623 }
3624
3625 /*
3626 * When the pipe CRC tap point is after the transcoders we need
3627 * to tweak symbol-level features to produce a deterministic series of
3628 * symbols for a given frame. We need to reset those features only once
3629 * a frame (instead of every nth symbol):
3630 * - DC-balance: used to ensure a better clock recovery from the data
3631 * link (SDVO)
3632 * - DisplayPort scrambling: used for EMI reduction
3633 */
3634 if (need_stable_symbols) {
3635 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3636
3637 tmp |= DC_BALANCE_RESET_VLV;
3638 switch (pipe) {
3639 case PIPE_A:
3640 tmp |= PIPE_A_SCRAMBLE_RESET;
3641 break;
3642 case PIPE_B:
3643 tmp |= PIPE_B_SCRAMBLE_RESET;
3644 break;
3645 case PIPE_C:
3646 tmp |= PIPE_C_SCRAMBLE_RESET;
3647 break;
3648 default:
3649 return -EINVAL;
3650 }
3651 I915_WRITE(PORT_DFT2_G4X, tmp);
3652 }
3653
3654 return 0;
3655 }
3656
3657 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3658 enum pipe pipe,
3659 enum intel_pipe_crc_source *source,
3660 uint32_t *val)
3661 {
3662 struct drm_i915_private *dev_priv = dev->dev_private;
3663 bool need_stable_symbols = false;
3664
3665 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3666 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3667 if (ret)
3668 return ret;
3669 }
3670
3671 switch (*source) {
3672 case INTEL_PIPE_CRC_SOURCE_PIPE:
3673 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3674 break;
3675 case INTEL_PIPE_CRC_SOURCE_TV:
3676 if (!SUPPORTS_TV(dev))
3677 return -EINVAL;
3678 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3679 break;
3680 case INTEL_PIPE_CRC_SOURCE_DP_B:
3681 if (!IS_G4X(dev))
3682 return -EINVAL;
3683 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3684 need_stable_symbols = true;
3685 break;
3686 case INTEL_PIPE_CRC_SOURCE_DP_C:
3687 if (!IS_G4X(dev))
3688 return -EINVAL;
3689 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3690 need_stable_symbols = true;
3691 break;
3692 case INTEL_PIPE_CRC_SOURCE_DP_D:
3693 if (!IS_G4X(dev))
3694 return -EINVAL;
3695 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3696 need_stable_symbols = true;
3697 break;
3698 case INTEL_PIPE_CRC_SOURCE_NONE:
3699 *val = 0;
3700 break;
3701 default:
3702 return -EINVAL;
3703 }
3704
3705 /*
3706 * When the pipe CRC tap point is after the transcoders we need
3707 * to tweak symbol-level features to produce a deterministic series of
3708 * symbols for a given frame. We need to reset those features only once
3709 * a frame (instead of every nth symbol):
3710 * - DC-balance: used to ensure a better clock recovery from the data
3711 * link (SDVO)
3712 * - DisplayPort scrambling: used for EMI reduction
3713 */
3714 if (need_stable_symbols) {
3715 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3716
3717 WARN_ON(!IS_G4X(dev));
3718
3719 I915_WRITE(PORT_DFT_I9XX,
3720 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3721
3722 if (pipe == PIPE_A)
3723 tmp |= PIPE_A_SCRAMBLE_RESET;
3724 else
3725 tmp |= PIPE_B_SCRAMBLE_RESET;
3726
3727 I915_WRITE(PORT_DFT2_G4X, tmp);
3728 }
3729
3730 return 0;
3731 }
3732
3733 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3734 enum pipe pipe)
3735 {
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3738
3739 switch (pipe) {
3740 case PIPE_A:
3741 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3742 break;
3743 case PIPE_B:
3744 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3745 break;
3746 case PIPE_C:
3747 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3748 break;
3749 default:
3750 return;
3751 }
3752 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3753 tmp &= ~DC_BALANCE_RESET_VLV;
3754 I915_WRITE(PORT_DFT2_G4X, tmp);
3755
3756 }
3757
3758 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3759 enum pipe pipe)
3760 {
3761 struct drm_i915_private *dev_priv = dev->dev_private;
3762 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3763
3764 if (pipe == PIPE_A)
3765 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3766 else
3767 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3768 I915_WRITE(PORT_DFT2_G4X, tmp);
3769
3770 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3771 I915_WRITE(PORT_DFT_I9XX,
3772 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3773 }
3774 }
3775
3776 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3777 uint32_t *val)
3778 {
3779 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3780 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3781
3782 switch (*source) {
3783 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3784 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3785 break;
3786 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3787 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3788 break;
3789 case INTEL_PIPE_CRC_SOURCE_PIPE:
3790 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3791 break;
3792 case INTEL_PIPE_CRC_SOURCE_NONE:
3793 *val = 0;
3794 break;
3795 default:
3796 return -EINVAL;
3797 }
3798
3799 return 0;
3800 }
3801
3802 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3803 {
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 struct intel_crtc *crtc =
3806 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3807 struct intel_crtc_state *pipe_config;
3808 struct drm_atomic_state *state;
3809 int ret = 0;
3810
3811 drm_modeset_lock_all(dev);
3812 state = drm_atomic_state_alloc(dev);
3813 if (!state) {
3814 ret = -ENOMEM;
3815 goto out;
3816 }
3817
3818 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3819 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3820 if (IS_ERR(pipe_config)) {
3821 ret = PTR_ERR(pipe_config);
3822 goto out;
3823 }
3824
3825 pipe_config->pch_pfit.force_thru = enable;
3826 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3827 pipe_config->pch_pfit.enabled != enable)
3828 pipe_config->base.connectors_changed = true;
3829
3830 ret = drm_atomic_commit(state);
3831 out:
3832 drm_modeset_unlock_all(dev);
3833 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3834 if (ret)
3835 drm_atomic_state_free(state);
3836 }
3837
3838 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3839 enum pipe pipe,
3840 enum intel_pipe_crc_source *source,
3841 uint32_t *val)
3842 {
3843 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3844 *source = INTEL_PIPE_CRC_SOURCE_PF;
3845
3846 switch (*source) {
3847 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3848 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3849 break;
3850 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3851 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3852 break;
3853 case INTEL_PIPE_CRC_SOURCE_PF:
3854 if (IS_HASWELL(dev) && pipe == PIPE_A)
3855 hsw_trans_edp_pipe_A_crc_wa(dev, true);
3856
3857 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3858 break;
3859 case INTEL_PIPE_CRC_SOURCE_NONE:
3860 *val = 0;
3861 break;
3862 default:
3863 return -EINVAL;
3864 }
3865
3866 return 0;
3867 }
3868
3869 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3870 enum intel_pipe_crc_source source)
3871 {
3872 struct drm_i915_private *dev_priv = dev->dev_private;
3873 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3874 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3875 pipe));
3876 u32 val = 0; /* shut up gcc */
3877 int ret;
3878
3879 if (pipe_crc->source == source)
3880 return 0;
3881
3882 /* forbid changing the source without going back to 'none' */
3883 if (pipe_crc->source && source)
3884 return -EINVAL;
3885
3886 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3887 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3888 return -EIO;
3889 }
3890
3891 if (IS_GEN2(dev))
3892 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3893 else if (INTEL_INFO(dev)->gen < 5)
3894 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3895 else if (IS_VALLEYVIEW(dev))
3896 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3897 else if (IS_GEN5(dev) || IS_GEN6(dev))
3898 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3899 else
3900 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3901
3902 if (ret != 0)
3903 return ret;
3904
3905 /* none -> real source transition */
3906 if (source) {
3907 struct intel_pipe_crc_entry *entries;
3908
3909 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3910 pipe_name(pipe), pipe_crc_source_name(source));
3911
3912 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3913 sizeof(pipe_crc->entries[0]),
3914 GFP_KERNEL);
3915 if (!entries)
3916 return -ENOMEM;
3917
3918 /*
3919 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3920 * enabled and disabled dynamically based on package C states,
3921 * user space can't make reliable use of the CRCs, so let's just
3922 * completely disable it.
3923 */
3924 hsw_disable_ips(crtc);
3925
3926 spin_lock_irq(&pipe_crc->lock);
3927 kfree(pipe_crc->entries);
3928 pipe_crc->entries = entries;
3929 pipe_crc->head = 0;
3930 pipe_crc->tail = 0;
3931 spin_unlock_irq(&pipe_crc->lock);
3932 }
3933
3934 pipe_crc->source = source;
3935
3936 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3937 POSTING_READ(PIPE_CRC_CTL(pipe));
3938
3939 /* real source -> none transition */
3940 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3941 struct intel_pipe_crc_entry *entries;
3942 struct intel_crtc *crtc =
3943 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3944
3945 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3946 pipe_name(pipe));
3947
3948 drm_modeset_lock(&crtc->base.mutex, NULL);
3949 if (crtc->base.state->active)
3950 intel_wait_for_vblank(dev, pipe);
3951 drm_modeset_unlock(&crtc->base.mutex);
3952
3953 spin_lock_irq(&pipe_crc->lock);
3954 entries = pipe_crc->entries;
3955 pipe_crc->entries = NULL;
3956 pipe_crc->head = 0;
3957 pipe_crc->tail = 0;
3958 spin_unlock_irq(&pipe_crc->lock);
3959
3960 kfree(entries);
3961
3962 if (IS_G4X(dev))
3963 g4x_undo_pipe_scramble_reset(dev, pipe);
3964 else if (IS_VALLEYVIEW(dev))
3965 vlv_undo_pipe_scramble_reset(dev, pipe);
3966 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3967 hsw_trans_edp_pipe_A_crc_wa(dev, false);
3968
3969 hsw_enable_ips(crtc);
3970 }
3971
3972 return 0;
3973 }
3974
3975 /*
3976 * Parse pipe CRC command strings:
3977 * command: wsp* object wsp+ name wsp+ source wsp*
3978 * object: 'pipe'
3979 * name: (A | B | C)
3980 * source: (none | plane1 | plane2 | pf)
3981 * wsp: (#0x20 | #0x9 | #0xA)+
3982 *
3983 * eg.:
3984 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3985 * "pipe A none" -> Stop CRC
3986 */
3987 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3988 {
3989 int n_words = 0;
3990
3991 while (*buf) {
3992 char *end;
3993
3994 /* skip leading white space */
3995 buf = skip_spaces(buf);
3996 if (!*buf)
3997 break; /* end of buffer */
3998
3999 /* find end of word */
4000 for (end = buf; *end && !isspace(*end); end++)
4001 ;
4002
4003 if (n_words == max_words) {
4004 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4005 max_words);
4006 return -EINVAL; /* ran out of words[] before bytes */
4007 }
4008
4009 if (*end)
4010 *end++ = '\0';
4011 words[n_words++] = buf;
4012 buf = end;
4013 }
4014
4015 return n_words;
4016 }
4017
4018 enum intel_pipe_crc_object {
4019 PIPE_CRC_OBJECT_PIPE,
4020 };
4021
4022 static const char * const pipe_crc_objects[] = {
4023 "pipe",
4024 };
4025
4026 static int
4027 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4028 {
4029 int i;
4030
4031 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4032 if (!strcmp(buf, pipe_crc_objects[i])) {
4033 *o = i;
4034 return 0;
4035 }
4036
4037 return -EINVAL;
4038 }
4039
4040 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4041 {
4042 const char name = buf[0];
4043
4044 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4045 return -EINVAL;
4046
4047 *pipe = name - 'A';
4048
4049 return 0;
4050 }
4051
4052 static int
4053 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4054 {
4055 int i;
4056
4057 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4058 if (!strcmp(buf, pipe_crc_sources[i])) {
4059 *s = i;
4060 return 0;
4061 }
4062
4063 return -EINVAL;
4064 }
4065
4066 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4067 {
4068 #define N_WORDS 3
4069 int n_words;
4070 char *words[N_WORDS];
4071 enum pipe pipe;
4072 enum intel_pipe_crc_object object;
4073 enum intel_pipe_crc_source source;
4074
4075 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4076 if (n_words != N_WORDS) {
4077 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4078 N_WORDS);
4079 return -EINVAL;
4080 }
4081
4082 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4083 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4084 return -EINVAL;
4085 }
4086
4087 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4088 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4089 return -EINVAL;
4090 }
4091
4092 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4093 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4094 return -EINVAL;
4095 }
4096
4097 return pipe_crc_set_source(dev, pipe, source);
4098 }
4099
4100 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4101 size_t len, loff_t *offp)
4102 {
4103 struct seq_file *m = file->private_data;
4104 struct drm_device *dev = m->private;
4105 char *tmpbuf;
4106 int ret;
4107
4108 if (len == 0)
4109 return 0;
4110
4111 if (len > PAGE_SIZE - 1) {
4112 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4113 PAGE_SIZE);
4114 return -E2BIG;
4115 }
4116
4117 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4118 if (!tmpbuf)
4119 return -ENOMEM;
4120
4121 if (copy_from_user(tmpbuf, ubuf, len)) {
4122 ret = -EFAULT;
4123 goto out;
4124 }
4125 tmpbuf[len] = '\0';
4126
4127 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4128
4129 out:
4130 kfree(tmpbuf);
4131 if (ret < 0)
4132 return ret;
4133
4134 *offp += len;
4135 return len;
4136 }
4137
4138 static const struct file_operations i915_display_crc_ctl_fops = {
4139 .owner = THIS_MODULE,
4140 .open = display_crc_ctl_open,
4141 .read = seq_read,
4142 .llseek = seq_lseek,
4143 .release = single_release,
4144 .write = display_crc_ctl_write
4145 };
4146
4147 static ssize_t i915_displayport_test_active_write(struct file *file,
4148 const char __user *ubuf,
4149 size_t len, loff_t *offp)
4150 {
4151 char *input_buffer;
4152 int status = 0;
4153 struct drm_device *dev;
4154 struct drm_connector *connector;
4155 struct list_head *connector_list;
4156 struct intel_dp *intel_dp;
4157 int val = 0;
4158
4159 dev = ((struct seq_file *)file->private_data)->private;
4160
4161 connector_list = &dev->mode_config.connector_list;
4162
4163 if (len == 0)
4164 return 0;
4165
4166 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4167 if (!input_buffer)
4168 return -ENOMEM;
4169
4170 if (copy_from_user(input_buffer, ubuf, len)) {
4171 status = -EFAULT;
4172 goto out;
4173 }
4174
4175 input_buffer[len] = '\0';
4176 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4177
4178 list_for_each_entry(connector, connector_list, head) {
4179
4180 if (connector->connector_type !=
4181 DRM_MODE_CONNECTOR_DisplayPort)
4182 continue;
4183
4184 if (connector->status == connector_status_connected &&
4185 connector->encoder != NULL) {
4186 intel_dp = enc_to_intel_dp(connector->encoder);
4187 status = kstrtoint(input_buffer, 10, &val);
4188 if (status < 0)
4189 goto out;
4190 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4191 /* To prevent erroneous activation of the compliance
4192 * testing code, only accept an actual value of 1 here
4193 */
4194 if (val == 1)
4195 intel_dp->compliance_test_active = 1;
4196 else
4197 intel_dp->compliance_test_active = 0;
4198 }
4199 }
4200 out:
4201 kfree(input_buffer);
4202 if (status < 0)
4203 return status;
4204
4205 *offp += len;
4206 return len;
4207 }
4208
4209 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4210 {
4211 struct drm_device *dev = m->private;
4212 struct drm_connector *connector;
4213 struct list_head *connector_list = &dev->mode_config.connector_list;
4214 struct intel_dp *intel_dp;
4215
4216 list_for_each_entry(connector, connector_list, head) {
4217
4218 if (connector->connector_type !=
4219 DRM_MODE_CONNECTOR_DisplayPort)
4220 continue;
4221
4222 if (connector->status == connector_status_connected &&
4223 connector->encoder != NULL) {
4224 intel_dp = enc_to_intel_dp(connector->encoder);
4225 if (intel_dp->compliance_test_active)
4226 seq_puts(m, "1");
4227 else
4228 seq_puts(m, "0");
4229 } else
4230 seq_puts(m, "0");
4231 }
4232
4233 return 0;
4234 }
4235
4236 static int i915_displayport_test_active_open(struct inode *inode,
4237 struct file *file)
4238 {
4239 struct drm_device *dev = inode->i_private;
4240
4241 return single_open(file, i915_displayport_test_active_show, dev);
4242 }
4243
4244 static const struct file_operations i915_displayport_test_active_fops = {
4245 .owner = THIS_MODULE,
4246 .open = i915_displayport_test_active_open,
4247 .read = seq_read,
4248 .llseek = seq_lseek,
4249 .release = single_release,
4250 .write = i915_displayport_test_active_write
4251 };
4252
4253 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4254 {
4255 struct drm_device *dev = m->private;
4256 struct drm_connector *connector;
4257 struct list_head *connector_list = &dev->mode_config.connector_list;
4258 struct intel_dp *intel_dp;
4259
4260 list_for_each_entry(connector, connector_list, head) {
4261
4262 if (connector->connector_type !=
4263 DRM_MODE_CONNECTOR_DisplayPort)
4264 continue;
4265
4266 if (connector->status == connector_status_connected &&
4267 connector->encoder != NULL) {
4268 intel_dp = enc_to_intel_dp(connector->encoder);
4269 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4270 } else
4271 seq_puts(m, "0");
4272 }
4273
4274 return 0;
4275 }
4276 static int i915_displayport_test_data_open(struct inode *inode,
4277 struct file *file)
4278 {
4279 struct drm_device *dev = inode->i_private;
4280
4281 return single_open(file, i915_displayport_test_data_show, dev);
4282 }
4283
4284 static const struct file_operations i915_displayport_test_data_fops = {
4285 .owner = THIS_MODULE,
4286 .open = i915_displayport_test_data_open,
4287 .read = seq_read,
4288 .llseek = seq_lseek,
4289 .release = single_release
4290 };
4291
4292 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4293 {
4294 struct drm_device *dev = m->private;
4295 struct drm_connector *connector;
4296 struct list_head *connector_list = &dev->mode_config.connector_list;
4297 struct intel_dp *intel_dp;
4298
4299 list_for_each_entry(connector, connector_list, head) {
4300
4301 if (connector->connector_type !=
4302 DRM_MODE_CONNECTOR_DisplayPort)
4303 continue;
4304
4305 if (connector->status == connector_status_connected &&
4306 connector->encoder != NULL) {
4307 intel_dp = enc_to_intel_dp(connector->encoder);
4308 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4309 } else
4310 seq_puts(m, "0");
4311 }
4312
4313 return 0;
4314 }
4315
4316 static int i915_displayport_test_type_open(struct inode *inode,
4317 struct file *file)
4318 {
4319 struct drm_device *dev = inode->i_private;
4320
4321 return single_open(file, i915_displayport_test_type_show, dev);
4322 }
4323
4324 static const struct file_operations i915_displayport_test_type_fops = {
4325 .owner = THIS_MODULE,
4326 .open = i915_displayport_test_type_open,
4327 .read = seq_read,
4328 .llseek = seq_lseek,
4329 .release = single_release
4330 };
4331
4332 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4333 {
4334 struct drm_device *dev = m->private;
4335 int level;
4336 int num_levels;
4337
4338 if (IS_CHERRYVIEW(dev))
4339 num_levels = 3;
4340 else if (IS_VALLEYVIEW(dev))
4341 num_levels = 1;
4342 else
4343 num_levels = ilk_wm_max_level(dev) + 1;
4344
4345 drm_modeset_lock_all(dev);
4346
4347 for (level = 0; level < num_levels; level++) {
4348 unsigned int latency = wm[level];
4349
4350 /*
4351 * - WM1+ latency values in 0.5us units
4352 * - latencies are in us on gen9/vlv/chv
4353 */
4354 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4355 latency *= 10;
4356 else if (level > 0)
4357 latency *= 5;
4358
4359 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4360 level, wm[level], latency / 10, latency % 10);
4361 }
4362
4363 drm_modeset_unlock_all(dev);
4364 }
4365
4366 static int pri_wm_latency_show(struct seq_file *m, void *data)
4367 {
4368 struct drm_device *dev = m->private;
4369 struct drm_i915_private *dev_priv = dev->dev_private;
4370 const uint16_t *latencies;
4371
4372 if (INTEL_INFO(dev)->gen >= 9)
4373 latencies = dev_priv->wm.skl_latency;
4374 else
4375 latencies = to_i915(dev)->wm.pri_latency;
4376
4377 wm_latency_show(m, latencies);
4378
4379 return 0;
4380 }
4381
4382 static int spr_wm_latency_show(struct seq_file *m, void *data)
4383 {
4384 struct drm_device *dev = m->private;
4385 struct drm_i915_private *dev_priv = dev->dev_private;
4386 const uint16_t *latencies;
4387
4388 if (INTEL_INFO(dev)->gen >= 9)
4389 latencies = dev_priv->wm.skl_latency;
4390 else
4391 latencies = to_i915(dev)->wm.spr_latency;
4392
4393 wm_latency_show(m, latencies);
4394
4395 return 0;
4396 }
4397
4398 static int cur_wm_latency_show(struct seq_file *m, void *data)
4399 {
4400 struct drm_device *dev = m->private;
4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402 const uint16_t *latencies;
4403
4404 if (INTEL_INFO(dev)->gen >= 9)
4405 latencies = dev_priv->wm.skl_latency;
4406 else
4407 latencies = to_i915(dev)->wm.cur_latency;
4408
4409 wm_latency_show(m, latencies);
4410
4411 return 0;
4412 }
4413
4414 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4415 {
4416 struct drm_device *dev = inode->i_private;
4417
4418 if (INTEL_INFO(dev)->gen < 5)
4419 return -ENODEV;
4420
4421 return single_open(file, pri_wm_latency_show, dev);
4422 }
4423
4424 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4425 {
4426 struct drm_device *dev = inode->i_private;
4427
4428 if (HAS_GMCH_DISPLAY(dev))
4429 return -ENODEV;
4430
4431 return single_open(file, spr_wm_latency_show, dev);
4432 }
4433
4434 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4435 {
4436 struct drm_device *dev = inode->i_private;
4437
4438 if (HAS_GMCH_DISPLAY(dev))
4439 return -ENODEV;
4440
4441 return single_open(file, cur_wm_latency_show, dev);
4442 }
4443
4444 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4445 size_t len, loff_t *offp, uint16_t wm[8])
4446 {
4447 struct seq_file *m = file->private_data;
4448 struct drm_device *dev = m->private;
4449 uint16_t new[8] = { 0 };
4450 int num_levels;
4451 int level;
4452 int ret;
4453 char tmp[32];
4454
4455 if (IS_CHERRYVIEW(dev))
4456 num_levels = 3;
4457 else if (IS_VALLEYVIEW(dev))
4458 num_levels = 1;
4459 else
4460 num_levels = ilk_wm_max_level(dev) + 1;
4461
4462 if (len >= sizeof(tmp))
4463 return -EINVAL;
4464
4465 if (copy_from_user(tmp, ubuf, len))
4466 return -EFAULT;
4467
4468 tmp[len] = '\0';
4469
4470 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4471 &new[0], &new[1], &new[2], &new[3],
4472 &new[4], &new[5], &new[6], &new[7]);
4473 if (ret != num_levels)
4474 return -EINVAL;
4475
4476 drm_modeset_lock_all(dev);
4477
4478 for (level = 0; level < num_levels; level++)
4479 wm[level] = new[level];
4480
4481 drm_modeset_unlock_all(dev);
4482
4483 return len;
4484 }
4485
4486
4487 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4488 size_t len, loff_t *offp)
4489 {
4490 struct seq_file *m = file->private_data;
4491 struct drm_device *dev = m->private;
4492 struct drm_i915_private *dev_priv = dev->dev_private;
4493 uint16_t *latencies;
4494
4495 if (INTEL_INFO(dev)->gen >= 9)
4496 latencies = dev_priv->wm.skl_latency;
4497 else
4498 latencies = to_i915(dev)->wm.pri_latency;
4499
4500 return wm_latency_write(file, ubuf, len, offp, latencies);
4501 }
4502
4503 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4504 size_t len, loff_t *offp)
4505 {
4506 struct seq_file *m = file->private_data;
4507 struct drm_device *dev = m->private;
4508 struct drm_i915_private *dev_priv = dev->dev_private;
4509 uint16_t *latencies;
4510
4511 if (INTEL_INFO(dev)->gen >= 9)
4512 latencies = dev_priv->wm.skl_latency;
4513 else
4514 latencies = to_i915(dev)->wm.spr_latency;
4515
4516 return wm_latency_write(file, ubuf, len, offp, latencies);
4517 }
4518
4519 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4520 size_t len, loff_t *offp)
4521 {
4522 struct seq_file *m = file->private_data;
4523 struct drm_device *dev = m->private;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 uint16_t *latencies;
4526
4527 if (INTEL_INFO(dev)->gen >= 9)
4528 latencies = dev_priv->wm.skl_latency;
4529 else
4530 latencies = to_i915(dev)->wm.cur_latency;
4531
4532 return wm_latency_write(file, ubuf, len, offp, latencies);
4533 }
4534
4535 static const struct file_operations i915_pri_wm_latency_fops = {
4536 .owner = THIS_MODULE,
4537 .open = pri_wm_latency_open,
4538 .read = seq_read,
4539 .llseek = seq_lseek,
4540 .release = single_release,
4541 .write = pri_wm_latency_write
4542 };
4543
4544 static const struct file_operations i915_spr_wm_latency_fops = {
4545 .owner = THIS_MODULE,
4546 .open = spr_wm_latency_open,
4547 .read = seq_read,
4548 .llseek = seq_lseek,
4549 .release = single_release,
4550 .write = spr_wm_latency_write
4551 };
4552
4553 static const struct file_operations i915_cur_wm_latency_fops = {
4554 .owner = THIS_MODULE,
4555 .open = cur_wm_latency_open,
4556 .read = seq_read,
4557 .llseek = seq_lseek,
4558 .release = single_release,
4559 .write = cur_wm_latency_write
4560 };
4561
4562 static int
4563 i915_wedged_get(void *data, u64 *val)
4564 {
4565 struct drm_device *dev = data;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567
4568 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4569
4570 return 0;
4571 }
4572
4573 static int
4574 i915_wedged_set(void *data, u64 val)
4575 {
4576 struct drm_device *dev = data;
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578
4579 /*
4580 * There is no safeguard against this debugfs entry colliding
4581 * with the hangcheck calling same i915_handle_error() in
4582 * parallel, causing an explosion. For now we assume that the
4583 * test harness is responsible enough not to inject gpu hangs
4584 * while it is writing to 'i915_wedged'
4585 */
4586
4587 if (i915_reset_in_progress(&dev_priv->gpu_error))
4588 return -EAGAIN;
4589
4590 intel_runtime_pm_get(dev_priv);
4591
4592 i915_handle_error(dev, val,
4593 "Manually setting wedged to %llu", val);
4594
4595 intel_runtime_pm_put(dev_priv);
4596
4597 return 0;
4598 }
4599
4600 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4601 i915_wedged_get, i915_wedged_set,
4602 "%llu\n");
4603
4604 static int
4605 i915_ring_stop_get(void *data, u64 *val)
4606 {
4607 struct drm_device *dev = data;
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609
4610 *val = dev_priv->gpu_error.stop_rings;
4611
4612 return 0;
4613 }
4614
4615 static int
4616 i915_ring_stop_set(void *data, u64 val)
4617 {
4618 struct drm_device *dev = data;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620 int ret;
4621
4622 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4623
4624 ret = mutex_lock_interruptible(&dev->struct_mutex);
4625 if (ret)
4626 return ret;
4627
4628 dev_priv->gpu_error.stop_rings = val;
4629 mutex_unlock(&dev->struct_mutex);
4630
4631 return 0;
4632 }
4633
4634 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4635 i915_ring_stop_get, i915_ring_stop_set,
4636 "0x%08llx\n");
4637
4638 static int
4639 i915_ring_missed_irq_get(void *data, u64 *val)
4640 {
4641 struct drm_device *dev = data;
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4643
4644 *val = dev_priv->gpu_error.missed_irq_rings;
4645 return 0;
4646 }
4647
4648 static int
4649 i915_ring_missed_irq_set(void *data, u64 val)
4650 {
4651 struct drm_device *dev = data;
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 int ret;
4654
4655 /* Lock against concurrent debugfs callers */
4656 ret = mutex_lock_interruptible(&dev->struct_mutex);
4657 if (ret)
4658 return ret;
4659 dev_priv->gpu_error.missed_irq_rings = val;
4660 mutex_unlock(&dev->struct_mutex);
4661
4662 return 0;
4663 }
4664
4665 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4666 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4667 "0x%08llx\n");
4668
4669 static int
4670 i915_ring_test_irq_get(void *data, u64 *val)
4671 {
4672 struct drm_device *dev = data;
4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674
4675 *val = dev_priv->gpu_error.test_irq_rings;
4676
4677 return 0;
4678 }
4679
4680 static int
4681 i915_ring_test_irq_set(void *data, u64 val)
4682 {
4683 struct drm_device *dev = data;
4684 struct drm_i915_private *dev_priv = dev->dev_private;
4685 int ret;
4686
4687 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4688
4689 /* Lock against concurrent debugfs callers */
4690 ret = mutex_lock_interruptible(&dev->struct_mutex);
4691 if (ret)
4692 return ret;
4693
4694 dev_priv->gpu_error.test_irq_rings = val;
4695 mutex_unlock(&dev->struct_mutex);
4696
4697 return 0;
4698 }
4699
4700 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4701 i915_ring_test_irq_get, i915_ring_test_irq_set,
4702 "0x%08llx\n");
4703
4704 #define DROP_UNBOUND 0x1
4705 #define DROP_BOUND 0x2
4706 #define DROP_RETIRE 0x4
4707 #define DROP_ACTIVE 0x8
4708 #define DROP_ALL (DROP_UNBOUND | \
4709 DROP_BOUND | \
4710 DROP_RETIRE | \
4711 DROP_ACTIVE)
4712 static int
4713 i915_drop_caches_get(void *data, u64 *val)
4714 {
4715 *val = DROP_ALL;
4716
4717 return 0;
4718 }
4719
4720 static int
4721 i915_drop_caches_set(void *data, u64 val)
4722 {
4723 struct drm_device *dev = data;
4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725 int ret;
4726
4727 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4728
4729 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4730 * on ioctls on -EAGAIN. */
4731 ret = mutex_lock_interruptible(&dev->struct_mutex);
4732 if (ret)
4733 return ret;
4734
4735 if (val & DROP_ACTIVE) {
4736 ret = i915_gpu_idle(dev);
4737 if (ret)
4738 goto unlock;
4739 }
4740
4741 if (val & (DROP_RETIRE | DROP_ACTIVE))
4742 i915_gem_retire_requests(dev);
4743
4744 if (val & DROP_BOUND)
4745 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4746
4747 if (val & DROP_UNBOUND)
4748 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4749
4750 unlock:
4751 mutex_unlock(&dev->struct_mutex);
4752
4753 return ret;
4754 }
4755
4756 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4757 i915_drop_caches_get, i915_drop_caches_set,
4758 "0x%08llx\n");
4759
4760 static int
4761 i915_max_freq_get(void *data, u64 *val)
4762 {
4763 struct drm_device *dev = data;
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765 int ret;
4766
4767 if (INTEL_INFO(dev)->gen < 6)
4768 return -ENODEV;
4769
4770 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4771
4772 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4773 if (ret)
4774 return ret;
4775
4776 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4777 mutex_unlock(&dev_priv->rps.hw_lock);
4778
4779 return 0;
4780 }
4781
4782 static int
4783 i915_max_freq_set(void *data, u64 val)
4784 {
4785 struct drm_device *dev = data;
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787 u32 hw_max, hw_min;
4788 int ret;
4789
4790 if (INTEL_INFO(dev)->gen < 6)
4791 return -ENODEV;
4792
4793 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4794
4795 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4796
4797 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4798 if (ret)
4799 return ret;
4800
4801 /*
4802 * Turbo will still be enabled, but won't go above the set value.
4803 */
4804 val = intel_freq_opcode(dev_priv, val);
4805
4806 hw_max = dev_priv->rps.max_freq;
4807 hw_min = dev_priv->rps.min_freq;
4808
4809 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4810 mutex_unlock(&dev_priv->rps.hw_lock);
4811 return -EINVAL;
4812 }
4813
4814 dev_priv->rps.max_freq_softlimit = val;
4815
4816 intel_set_rps(dev, val);
4817
4818 mutex_unlock(&dev_priv->rps.hw_lock);
4819
4820 return 0;
4821 }
4822
4823 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4824 i915_max_freq_get, i915_max_freq_set,
4825 "%llu\n");
4826
4827 static int
4828 i915_min_freq_get(void *data, u64 *val)
4829 {
4830 struct drm_device *dev = data;
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 int ret;
4833
4834 if (INTEL_INFO(dev)->gen < 6)
4835 return -ENODEV;
4836
4837 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4838
4839 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4840 if (ret)
4841 return ret;
4842
4843 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4844 mutex_unlock(&dev_priv->rps.hw_lock);
4845
4846 return 0;
4847 }
4848
4849 static int
4850 i915_min_freq_set(void *data, u64 val)
4851 {
4852 struct drm_device *dev = data;
4853 struct drm_i915_private *dev_priv = dev->dev_private;
4854 u32 hw_max, hw_min;
4855 int ret;
4856
4857 if (INTEL_INFO(dev)->gen < 6)
4858 return -ENODEV;
4859
4860 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4861
4862 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4863
4864 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4865 if (ret)
4866 return ret;
4867
4868 /*
4869 * Turbo will still be enabled, but won't go below the set value.
4870 */
4871 val = intel_freq_opcode(dev_priv, val);
4872
4873 hw_max = dev_priv->rps.max_freq;
4874 hw_min = dev_priv->rps.min_freq;
4875
4876 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4877 mutex_unlock(&dev_priv->rps.hw_lock);
4878 return -EINVAL;
4879 }
4880
4881 dev_priv->rps.min_freq_softlimit = val;
4882
4883 intel_set_rps(dev, val);
4884
4885 mutex_unlock(&dev_priv->rps.hw_lock);
4886
4887 return 0;
4888 }
4889
4890 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4891 i915_min_freq_get, i915_min_freq_set,
4892 "%llu\n");
4893
4894 static int
4895 i915_cache_sharing_get(void *data, u64 *val)
4896 {
4897 struct drm_device *dev = data;
4898 struct drm_i915_private *dev_priv = dev->dev_private;
4899 u32 snpcr;
4900 int ret;
4901
4902 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4903 return -ENODEV;
4904
4905 ret = mutex_lock_interruptible(&dev->struct_mutex);
4906 if (ret)
4907 return ret;
4908 intel_runtime_pm_get(dev_priv);
4909
4910 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4911
4912 intel_runtime_pm_put(dev_priv);
4913 mutex_unlock(&dev_priv->dev->struct_mutex);
4914
4915 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4916
4917 return 0;
4918 }
4919
4920 static int
4921 i915_cache_sharing_set(void *data, u64 val)
4922 {
4923 struct drm_device *dev = data;
4924 struct drm_i915_private *dev_priv = dev->dev_private;
4925 u32 snpcr;
4926
4927 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4928 return -ENODEV;
4929
4930 if (val > 3)
4931 return -EINVAL;
4932
4933 intel_runtime_pm_get(dev_priv);
4934 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4935
4936 /* Update the cache sharing policy here as well */
4937 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4938 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4939 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4940 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4941
4942 intel_runtime_pm_put(dev_priv);
4943 return 0;
4944 }
4945
4946 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4947 i915_cache_sharing_get, i915_cache_sharing_set,
4948 "%llu\n");
4949
4950 struct sseu_dev_status {
4951 unsigned int slice_total;
4952 unsigned int subslice_total;
4953 unsigned int subslice_per_slice;
4954 unsigned int eu_total;
4955 unsigned int eu_per_subslice;
4956 };
4957
4958 static void cherryview_sseu_device_status(struct drm_device *dev,
4959 struct sseu_dev_status *stat)
4960 {
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 int ss_max = 2;
4963 int ss;
4964 u32 sig1[ss_max], sig2[ss_max];
4965
4966 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4967 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4968 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4969 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4970
4971 for (ss = 0; ss < ss_max; ss++) {
4972 unsigned int eu_cnt;
4973
4974 if (sig1[ss] & CHV_SS_PG_ENABLE)
4975 /* skip disabled subslice */
4976 continue;
4977
4978 stat->slice_total = 1;
4979 stat->subslice_per_slice++;
4980 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4981 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4982 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4983 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4984 stat->eu_total += eu_cnt;
4985 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4986 }
4987 stat->subslice_total = stat->subslice_per_slice;
4988 }
4989
4990 static void gen9_sseu_device_status(struct drm_device *dev,
4991 struct sseu_dev_status *stat)
4992 {
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 int s_max = 3, ss_max = 4;
4995 int s, ss;
4996 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4997
4998 /* BXT has a single slice and at most 3 subslices. */
4999 if (IS_BROXTON(dev)) {
5000 s_max = 1;
5001 ss_max = 3;
5002 }
5003
5004 for (s = 0; s < s_max; s++) {
5005 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5006 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5007 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5008 }
5009
5010 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5011 GEN9_PGCTL_SSA_EU19_ACK |
5012 GEN9_PGCTL_SSA_EU210_ACK |
5013 GEN9_PGCTL_SSA_EU311_ACK;
5014 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5015 GEN9_PGCTL_SSB_EU19_ACK |
5016 GEN9_PGCTL_SSB_EU210_ACK |
5017 GEN9_PGCTL_SSB_EU311_ACK;
5018
5019 for (s = 0; s < s_max; s++) {
5020 unsigned int ss_cnt = 0;
5021
5022 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5023 /* skip disabled slice */
5024 continue;
5025
5026 stat->slice_total++;
5027
5028 if (IS_SKYLAKE(dev))
5029 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5030
5031 for (ss = 0; ss < ss_max; ss++) {
5032 unsigned int eu_cnt;
5033
5034 if (IS_BROXTON(dev) &&
5035 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5036 /* skip disabled subslice */
5037 continue;
5038
5039 if (IS_BROXTON(dev))
5040 ss_cnt++;
5041
5042 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5043 eu_mask[ss%2]);
5044 stat->eu_total += eu_cnt;
5045 stat->eu_per_subslice = max(stat->eu_per_subslice,
5046 eu_cnt);
5047 }
5048
5049 stat->subslice_total += ss_cnt;
5050 stat->subslice_per_slice = max(stat->subslice_per_slice,
5051 ss_cnt);
5052 }
5053 }
5054
5055 static void broadwell_sseu_device_status(struct drm_device *dev,
5056 struct sseu_dev_status *stat)
5057 {
5058 struct drm_i915_private *dev_priv = dev->dev_private;
5059 int s;
5060 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5061
5062 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5063
5064 if (stat->slice_total) {
5065 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5066 stat->subslice_total = stat->slice_total *
5067 stat->subslice_per_slice;
5068 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5069 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5070
5071 /* subtract fused off EU(s) from enabled slice(s) */
5072 for (s = 0; s < stat->slice_total; s++) {
5073 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5074
5075 stat->eu_total -= hweight8(subslice_7eu);
5076 }
5077 }
5078 }
5079
5080 static int i915_sseu_status(struct seq_file *m, void *unused)
5081 {
5082 struct drm_info_node *node = (struct drm_info_node *) m->private;
5083 struct drm_device *dev = node->minor->dev;
5084 struct sseu_dev_status stat;
5085
5086 if (INTEL_INFO(dev)->gen < 8)
5087 return -ENODEV;
5088
5089 seq_puts(m, "SSEU Device Info\n");
5090 seq_printf(m, " Available Slice Total: %u\n",
5091 INTEL_INFO(dev)->slice_total);
5092 seq_printf(m, " Available Subslice Total: %u\n",
5093 INTEL_INFO(dev)->subslice_total);
5094 seq_printf(m, " Available Subslice Per Slice: %u\n",
5095 INTEL_INFO(dev)->subslice_per_slice);
5096 seq_printf(m, " Available EU Total: %u\n",
5097 INTEL_INFO(dev)->eu_total);
5098 seq_printf(m, " Available EU Per Subslice: %u\n",
5099 INTEL_INFO(dev)->eu_per_subslice);
5100 seq_printf(m, " Has Slice Power Gating: %s\n",
5101 yesno(INTEL_INFO(dev)->has_slice_pg));
5102 seq_printf(m, " Has Subslice Power Gating: %s\n",
5103 yesno(INTEL_INFO(dev)->has_subslice_pg));
5104 seq_printf(m, " Has EU Power Gating: %s\n",
5105 yesno(INTEL_INFO(dev)->has_eu_pg));
5106
5107 seq_puts(m, "SSEU Device Status\n");
5108 memset(&stat, 0, sizeof(stat));
5109 if (IS_CHERRYVIEW(dev)) {
5110 cherryview_sseu_device_status(dev, &stat);
5111 } else if (IS_BROADWELL(dev)) {
5112 broadwell_sseu_device_status(dev, &stat);
5113 } else if (INTEL_INFO(dev)->gen >= 9) {
5114 gen9_sseu_device_status(dev, &stat);
5115 }
5116 seq_printf(m, " Enabled Slice Total: %u\n",
5117 stat.slice_total);
5118 seq_printf(m, " Enabled Subslice Total: %u\n",
5119 stat.subslice_total);
5120 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5121 stat.subslice_per_slice);
5122 seq_printf(m, " Enabled EU Total: %u\n",
5123 stat.eu_total);
5124 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5125 stat.eu_per_subslice);
5126
5127 return 0;
5128 }
5129
5130 static int i915_forcewake_open(struct inode *inode, struct file *file)
5131 {
5132 struct drm_device *dev = inode->i_private;
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134
5135 if (INTEL_INFO(dev)->gen < 6)
5136 return 0;
5137
5138 intel_runtime_pm_get(dev_priv);
5139 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5140
5141 return 0;
5142 }
5143
5144 static int i915_forcewake_release(struct inode *inode, struct file *file)
5145 {
5146 struct drm_device *dev = inode->i_private;
5147 struct drm_i915_private *dev_priv = dev->dev_private;
5148
5149 if (INTEL_INFO(dev)->gen < 6)
5150 return 0;
5151
5152 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5153 intel_runtime_pm_put(dev_priv);
5154
5155 return 0;
5156 }
5157
5158 static const struct file_operations i915_forcewake_fops = {
5159 .owner = THIS_MODULE,
5160 .open = i915_forcewake_open,
5161 .release = i915_forcewake_release,
5162 };
5163
5164 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5165 {
5166 struct drm_device *dev = minor->dev;
5167 struct dentry *ent;
5168
5169 ent = debugfs_create_file("i915_forcewake_user",
5170 S_IRUSR,
5171 root, dev,
5172 &i915_forcewake_fops);
5173 if (!ent)
5174 return -ENOMEM;
5175
5176 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5177 }
5178
5179 static int i915_debugfs_create(struct dentry *root,
5180 struct drm_minor *minor,
5181 const char *name,
5182 const struct file_operations *fops)
5183 {
5184 struct drm_device *dev = minor->dev;
5185 struct dentry *ent;
5186
5187 ent = debugfs_create_file(name,
5188 S_IRUGO | S_IWUSR,
5189 root, dev,
5190 fops);
5191 if (!ent)
5192 return -ENOMEM;
5193
5194 return drm_add_fake_info_node(minor, ent, fops);
5195 }
5196
5197 static const struct drm_info_list i915_debugfs_list[] = {
5198 {"i915_capabilities", i915_capabilities, 0},
5199 {"i915_gem_objects", i915_gem_object_info, 0},
5200 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5201 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5202 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5203 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5204 {"i915_gem_stolen", i915_gem_stolen_list_info },
5205 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5206 {"i915_gem_request", i915_gem_request_info, 0},
5207 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5208 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5209 {"i915_gem_interrupt", i915_interrupt_info, 0},
5210 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5211 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5212 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5213 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5214 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5215 {"i915_guc_info", i915_guc_info, 0},
5216 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5217 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5218 {"i915_frequency_info", i915_frequency_info, 0},
5219 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5220 {"i915_drpc_info", i915_drpc_info, 0},
5221 {"i915_emon_status", i915_emon_status, 0},
5222 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5223 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5224 {"i915_fbc_status", i915_fbc_status, 0},
5225 {"i915_ips_status", i915_ips_status, 0},
5226 {"i915_sr_status", i915_sr_status, 0},
5227 {"i915_opregion", i915_opregion, 0},
5228 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5229 {"i915_context_status", i915_context_status, 0},
5230 {"i915_dump_lrc", i915_dump_lrc, 0},
5231 {"i915_execlists", i915_execlists, 0},
5232 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5233 {"i915_swizzle_info", i915_swizzle_info, 0},
5234 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5235 {"i915_llc", i915_llc, 0},
5236 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5237 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5238 {"i915_energy_uJ", i915_energy_uJ, 0},
5239 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5240 {"i915_power_domain_info", i915_power_domain_info, 0},
5241 {"i915_display_info", i915_display_info, 0},
5242 {"i915_semaphore_status", i915_semaphore_status, 0},
5243 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5244 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5245 {"i915_wa_registers", i915_wa_registers, 0},
5246 {"i915_ddb_info", i915_ddb_info, 0},
5247 {"i915_sseu_status", i915_sseu_status, 0},
5248 {"i915_drrs_status", i915_drrs_status, 0},
5249 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5250 };
5251 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5252
5253 static const struct i915_debugfs_files {
5254 const char *name;
5255 const struct file_operations *fops;
5256 } i915_debugfs_files[] = {
5257 {"i915_wedged", &i915_wedged_fops},
5258 {"i915_max_freq", &i915_max_freq_fops},
5259 {"i915_min_freq", &i915_min_freq_fops},
5260 {"i915_cache_sharing", &i915_cache_sharing_fops},
5261 {"i915_ring_stop", &i915_ring_stop_fops},
5262 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5263 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5264 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5265 {"i915_error_state", &i915_error_state_fops},
5266 {"i915_next_seqno", &i915_next_seqno_fops},
5267 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5268 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5269 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5270 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5271 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5272 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5273 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5274 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5275 };
5276
5277 void intel_display_crc_init(struct drm_device *dev)
5278 {
5279 struct drm_i915_private *dev_priv = dev->dev_private;
5280 enum pipe pipe;
5281
5282 for_each_pipe(dev_priv, pipe) {
5283 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5284
5285 pipe_crc->opened = false;
5286 spin_lock_init(&pipe_crc->lock);
5287 init_waitqueue_head(&pipe_crc->wq);
5288 }
5289 }
5290
5291 int i915_debugfs_init(struct drm_minor *minor)
5292 {
5293 int ret, i;
5294
5295 ret = i915_forcewake_create(minor->debugfs_root, minor);
5296 if (ret)
5297 return ret;
5298
5299 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5300 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5301 if (ret)
5302 return ret;
5303 }
5304
5305 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5306 ret = i915_debugfs_create(minor->debugfs_root, minor,
5307 i915_debugfs_files[i].name,
5308 i915_debugfs_files[i].fops);
5309 if (ret)
5310 return ret;
5311 }
5312
5313 return drm_debugfs_create_files(i915_debugfs_list,
5314 I915_DEBUGFS_ENTRIES,
5315 minor->debugfs_root, minor);
5316 }
5317
5318 void i915_debugfs_cleanup(struct drm_minor *minor)
5319 {
5320 int i;
5321
5322 drm_debugfs_remove_files(i915_debugfs_list,
5323 I915_DEBUGFS_ENTRIES, minor);
5324
5325 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5326 1, minor);
5327
5328 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5329 struct drm_info_list *info_list =
5330 (struct drm_info_list *)&i915_pipe_crc_data[i];
5331
5332 drm_debugfs_remove_files(info_list, 1, minor);
5333 }
5334
5335 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5336 struct drm_info_list *info_list =
5337 (struct drm_info_list *) i915_debugfs_files[i].fops;
5338
5339 drm_debugfs_remove_files(info_list, 1, minor);
5340 }
5341 }
5342
5343 struct dpcd_block {
5344 /* DPCD dump start address. */
5345 unsigned int offset;
5346 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5347 unsigned int end;
5348 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5349 size_t size;
5350 /* Only valid for eDP. */
5351 bool edp;
5352 };
5353
5354 static const struct dpcd_block i915_dpcd_debug[] = {
5355 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5356 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5357 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5358 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5359 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5360 { .offset = DP_SET_POWER },
5361 { .offset = DP_EDP_DPCD_REV },
5362 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5363 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5364 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5365 };
5366
5367 static int i915_dpcd_show(struct seq_file *m, void *data)
5368 {
5369 struct drm_connector *connector = m->private;
5370 struct intel_dp *intel_dp =
5371 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5372 uint8_t buf[16];
5373 ssize_t err;
5374 int i;
5375
5376 if (connector->status != connector_status_connected)
5377 return -ENODEV;
5378
5379 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5380 const struct dpcd_block *b = &i915_dpcd_debug[i];
5381 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5382
5383 if (b->edp &&
5384 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5385 continue;
5386
5387 /* low tech for now */
5388 if (WARN_ON(size > sizeof(buf)))
5389 continue;
5390
5391 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5392 if (err <= 0) {
5393 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5394 size, b->offset, err);
5395 continue;
5396 }
5397
5398 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5399 }
5400
5401 return 0;
5402 }
5403
5404 static int i915_dpcd_open(struct inode *inode, struct file *file)
5405 {
5406 return single_open(file, i915_dpcd_show, inode->i_private);
5407 }
5408
5409 static const struct file_operations i915_dpcd_fops = {
5410 .owner = THIS_MODULE,
5411 .open = i915_dpcd_open,
5412 .read = seq_read,
5413 .llseek = seq_lseek,
5414 .release = single_release,
5415 };
5416
5417 /**
5418 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5419 * @connector: pointer to a registered drm_connector
5420 *
5421 * Cleanup will be done by drm_connector_unregister() through a call to
5422 * drm_debugfs_connector_remove().
5423 *
5424 * Returns 0 on success, negative error codes on error.
5425 */
5426 int i915_debugfs_connector_add(struct drm_connector *connector)
5427 {
5428 struct dentry *root = connector->debugfs_entry;
5429
5430 /* The connector must have been registered beforehands. */
5431 if (!root)
5432 return -ENODEV;
5433
5434 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5435 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5436 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5437 &i915_dpcd_fops);
5438
5439 return 0;
5440 }
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