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drm/i915/kbl: Introduce Kabylake platform defition.
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51 static int
52 drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55 {
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73 }
74
75 static int i915_capabilities(struct seq_file *m, void *data)
76 {
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86 #undef PRINT_FLAG
87 #undef SEP_SEMICOLON
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->pin_display)
95 return "p";
96 else
97 return " ";
98 }
99
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
101 {
102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
108 }
109
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111 {
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
113 }
114
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116 {
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
124 }
125
126 return size;
127 }
128
129 static void
130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131 {
132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
134 struct i915_vma *vma;
135 int pin_count = 0;
136 int i;
137
138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
139 &obj->base,
140 obj->active ? "*" : " ",
141 get_pin_flag(obj),
142 get_tiling_flag(obj),
143 get_global_flag(obj),
144 obj->base.size / 1024,
145 obj->base.read_domains,
146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
148 seq_printf(m, "%x ",
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 if (obj->base.name)
157 seq_printf(m, " (name: %d)", obj->base.name);
158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
159 if (vma->pin_count > 0)
160 pin_count++;
161 }
162 seq_printf(m, " (pinned x %d)", pin_count);
163 if (obj->pin_display)
164 seq_printf(m, " (display)");
165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
173 else
174 seq_puts(m, ")");
175 }
176 if (obj->stolen)
177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
178 if (obj->pin_display || obj->fault_mappable) {
179 char s[3], *t = s;
180 if (obj->pin_display)
181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
187 if (obj->last_write_req != NULL)
188 seq_printf(m, " (%s)",
189 i915_gem_request_get_ring(obj->last_write_req)->name);
190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
192 }
193
194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
195 {
196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199 }
200
201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
202 {
203 struct drm_info_node *node = m->private;
204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
206 struct drm_device *dev = node->minor->dev;
207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
209 struct i915_vma *vma;
210 u64 total_obj_size, total_gtt_size;
211 int count, ret;
212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
216
217 /* FIXME: the user of this interface might want more than just GGTT */
218 switch (list) {
219 case ACTIVE_LIST:
220 seq_puts(m, "Active:\n");
221 head = &vm->active_list;
222 break;
223 case INACTIVE_LIST:
224 seq_puts(m, "Inactive:\n");
225 head = &vm->inactive_list;
226 break;
227 default:
228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
230 }
231
232 total_obj_size = total_gtt_size = count = 0;
233 list_for_each_entry(vma, head, mm_list) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
239 count++;
240 }
241 mutex_unlock(&dev->struct_mutex);
242
243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
244 count, total_obj_size, total_gtt_size);
245 return 0;
246 }
247
248 static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250 {
251 struct drm_i915_gem_object *a =
252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
253 struct drm_i915_gem_object *b =
254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
255
256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
261 }
262
263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264 {
265 struct drm_info_node *node = m->private;
266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
269 u64 total_obj_size, total_gtt_size;
270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
282 list_add(&obj->obj_exec_link, &stolen);
283
284 total_obj_size += obj->base.size;
285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
292 list_add(&obj->obj_exec_link, &stolen);
293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
304 list_del_init(&obj->obj_exec_link);
305 }
306 mutex_unlock(&dev->struct_mutex);
307
308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
309 count, total_obj_size, total_gtt_size);
310 return 0;
311 }
312
313 #define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
315 size += i915_gem_obj_total_ggtt_size(obj); \
316 ++count; \
317 if (obj->map_and_fenceable) { \
318 mappable_size += i915_gem_obj_ggtt_size(obj); \
319 ++mappable_count; \
320 } \
321 } \
322 } while (0)
323
324 struct file_stats {
325 struct drm_i915_file_private *file_priv;
326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
330 };
331
332 static int per_file_stats(int id, void *ptr, void *data)
333 {
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
336 struct i915_vma *vma;
337
338 stats->count++;
339 stats->total += obj->base.size;
340
341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, vma_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (i915_is_ggtt(vma->vm)) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
357 if (ppgtt->file_priv != stats->file_priv)
358 continue;
359
360 if (obj->active) /* XXX per-vma statistic */
361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
367 } else {
368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
370 if (obj->active)
371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
376 }
377
378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
381 return 0;
382 }
383
384 #define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395 } while (0)
396
397 static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399 {
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
402 struct intel_engine_cs *ring;
403 int i, j;
404
405 memset(&stats, 0, sizeof(stats));
406
407 for_each_ring(ring, dev_priv, i) {
408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &ring->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
414 }
415
416 print_file_stats(m, "[k]batch pool", stats);
417 }
418
419 #define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428 } while (0)
429
430 static int i915_gem_object_info(struct seq_file *m, void* data)
431 {
432 struct drm_info_node *node = m->private;
433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
435 u32 count, mappable_count, purgeable_count;
436 u64 size, mappable_size, purgeable_size;
437 struct drm_i915_gem_object *obj;
438 struct i915_address_space *vm = &dev_priv->gtt.base;
439 struct drm_file *file;
440 struct i915_vma *vma;
441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
452 count_objects(&dev_priv->mm.bound_list, global_list);
453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
457 count_vmas(&vm->active_list, mm_list);
458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
459 count, mappable_count, size, mappable_size);
460
461 size = count = mappable_size = mappable_count = 0;
462 count_vmas(&vm->inactive_list, mm_list);
463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
464 count, mappable_count, size, mappable_size);
465
466 size = count = purgeable_size = purgeable_count = 0;
467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
468 size += obj->base.size, ++count;
469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
473
474 size = count = mappable_size = mappable_count = 0;
475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
476 if (obj->fault_mappable) {
477 size += i915_gem_obj_ggtt_size(obj);
478 ++count;
479 }
480 if (obj->pin_display) {
481 mappable_size += i915_gem_obj_ggtt_size(obj);
482 ++mappable_count;
483 }
484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
488 }
489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
490 purgeable_count, purgeable_size);
491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
492 mappable_count, mappable_size);
493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
494 count, size);
495
496 seq_printf(m, "%llu [%llu] gtt total\n",
497 dev_priv->gtt.base.total,
498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
499
500 seq_putc(m, '\n');
501 print_batch_pool_stats(m, dev_priv);
502 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
503 struct file_stats stats;
504 struct task_struct *task;
505
506 memset(&stats, 0, sizeof(stats));
507 stats.file_priv = file->driver_priv;
508 spin_lock(&file->table_lock);
509 idr_for_each(&file->object_idr, per_file_stats, &stats);
510 spin_unlock(&file->table_lock);
511 /*
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
516 */
517 rcu_read_lock();
518 task = pid_task(file->pid, PIDTYPE_PID);
519 print_file_stats(m, task ? task->comm : "<unknown>", stats);
520 rcu_read_unlock();
521 }
522
523 mutex_unlock(&dev->struct_mutex);
524
525 return 0;
526 }
527
528 static int i915_gem_gtt_info(struct seq_file *m, void *data)
529 {
530 struct drm_info_node *node = m->private;
531 struct drm_device *dev = node->minor->dev;
532 uintptr_t list = (uintptr_t) node->info_ent->data;
533 struct drm_i915_private *dev_priv = dev->dev_private;
534 struct drm_i915_gem_object *obj;
535 u64 total_obj_size, total_gtt_size;
536 int count, ret;
537
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
539 if (ret)
540 return ret;
541
542 total_obj_size = total_gtt_size = count = 0;
543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
545 continue;
546
547 seq_puts(m, " ");
548 describe_obj(m, obj);
549 seq_putc(m, '\n');
550 total_obj_size += obj->base.size;
551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
552 count++;
553 }
554
555 mutex_unlock(&dev->struct_mutex);
556
557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
558 count, total_obj_size, total_gtt_size);
559
560 return 0;
561 }
562
563 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
564 {
565 struct drm_info_node *node = m->private;
566 struct drm_device *dev = node->minor->dev;
567 struct drm_i915_private *dev_priv = dev->dev_private;
568 struct intel_crtc *crtc;
569 int ret;
570
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
572 if (ret)
573 return ret;
574
575 for_each_intel_crtc(dev, crtc) {
576 const char pipe = pipe_name(crtc->pipe);
577 const char plane = plane_name(crtc->plane);
578 struct intel_unpin_work *work;
579
580 spin_lock_irq(&dev->event_lock);
581 work = crtc->unpin_work;
582 if (work == NULL) {
583 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
584 pipe, plane);
585 } else {
586 u32 addr;
587
588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
590 pipe, plane);
591 } else {
592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
593 pipe, plane);
594 }
595 if (work->flip_queued_req) {
596 struct intel_engine_cs *ring =
597 i915_gem_request_get_ring(work->flip_queued_req);
598
599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
600 ring->name,
601 i915_gem_request_get_seqno(work->flip_queued_req),
602 dev_priv->next_seqno,
603 ring->get_seqno(ring, true),
604 i915_gem_request_completed(work->flip_queued_req, true));
605 } else
606 seq_printf(m, "Flip not associated with any ring\n");
607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work->flip_queued_vblank,
609 work->flip_ready_vblank,
610 drm_crtc_vblank_count(&crtc->base));
611 if (work->enable_stall_check)
612 seq_puts(m, "Stall check enabled, ");
613 else
614 seq_puts(m, "Stall check waiting for page flip ioctl, ");
615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
616
617 if (INTEL_INFO(dev)->gen >= 4)
618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
619 else
620 addr = I915_READ(DSPADDR(crtc->plane));
621 seq_printf(m, "Current scanout address 0x%08x\n", addr);
622
623 if (work->pending_flip_obj) {
624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
626 }
627 }
628 spin_unlock_irq(&dev->event_lock);
629 }
630
631 mutex_unlock(&dev->struct_mutex);
632
633 return 0;
634 }
635
636 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
637 {
638 struct drm_info_node *node = m->private;
639 struct drm_device *dev = node->minor->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_i915_gem_object *obj;
642 struct intel_engine_cs *ring;
643 int total = 0;
644 int ret, i, j;
645
646 ret = mutex_lock_interruptible(&dev->struct_mutex);
647 if (ret)
648 return ret;
649
650 for_each_ring(ring, dev_priv, i) {
651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
652 int count;
653
654 count = 0;
655 list_for_each_entry(obj,
656 &ring->batch_pool.cache_list[j],
657 batch_pool_link)
658 count++;
659 seq_printf(m, "%s cache[%d]: %d objects\n",
660 ring->name, j, count);
661
662 list_for_each_entry(obj,
663 &ring->batch_pool.cache_list[j],
664 batch_pool_link) {
665 seq_puts(m, " ");
666 describe_obj(m, obj);
667 seq_putc(m, '\n');
668 }
669
670 total += count;
671 }
672 }
673
674 seq_printf(m, "total: %d\n", total);
675
676 mutex_unlock(&dev->struct_mutex);
677
678 return 0;
679 }
680
681 static int i915_gem_request_info(struct seq_file *m, void *data)
682 {
683 struct drm_info_node *node = m->private;
684 struct drm_device *dev = node->minor->dev;
685 struct drm_i915_private *dev_priv = dev->dev_private;
686 struct intel_engine_cs *ring;
687 struct drm_i915_gem_request *req;
688 int ret, any, i;
689
690 ret = mutex_lock_interruptible(&dev->struct_mutex);
691 if (ret)
692 return ret;
693
694 any = 0;
695 for_each_ring(ring, dev_priv, i) {
696 int count;
697
698 count = 0;
699 list_for_each_entry(req, &ring->request_list, list)
700 count++;
701 if (count == 0)
702 continue;
703
704 seq_printf(m, "%s requests: %d\n", ring->name, count);
705 list_for_each_entry(req, &ring->request_list, list) {
706 struct task_struct *task;
707
708 rcu_read_lock();
709 task = NULL;
710 if (req->pid)
711 task = pid_task(req->pid, PIDTYPE_PID);
712 seq_printf(m, " %x @ %d: %s [%d]\n",
713 req->seqno,
714 (int) (jiffies - req->emitted_jiffies),
715 task ? task->comm : "<unknown>",
716 task ? task->pid : -1);
717 rcu_read_unlock();
718 }
719
720 any++;
721 }
722 mutex_unlock(&dev->struct_mutex);
723
724 if (any == 0)
725 seq_puts(m, "No requests\n");
726
727 return 0;
728 }
729
730 static void i915_ring_seqno_info(struct seq_file *m,
731 struct intel_engine_cs *ring)
732 {
733 if (ring->get_seqno) {
734 seq_printf(m, "Current sequence (%s): %x\n",
735 ring->name, ring->get_seqno(ring, false));
736 }
737 }
738
739 static int i915_gem_seqno_info(struct seq_file *m, void *data)
740 {
741 struct drm_info_node *node = m->private;
742 struct drm_device *dev = node->minor->dev;
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 struct intel_engine_cs *ring;
745 int ret, i;
746
747 ret = mutex_lock_interruptible(&dev->struct_mutex);
748 if (ret)
749 return ret;
750 intel_runtime_pm_get(dev_priv);
751
752 for_each_ring(ring, dev_priv, i)
753 i915_ring_seqno_info(m, ring);
754
755 intel_runtime_pm_put(dev_priv);
756 mutex_unlock(&dev->struct_mutex);
757
758 return 0;
759 }
760
761
762 static int i915_interrupt_info(struct seq_file *m, void *data)
763 {
764 struct drm_info_node *node = m->private;
765 struct drm_device *dev = node->minor->dev;
766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct intel_engine_cs *ring;
768 int ret, i, pipe;
769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
773 intel_runtime_pm_get(dev_priv);
774
775 if (IS_CHERRYVIEW(dev)) {
776 seq_printf(m, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ));
778
779 seq_printf(m, "Display IER:\t%08x\n",
780 I915_READ(VLV_IER));
781 seq_printf(m, "Display IIR:\t%08x\n",
782 I915_READ(VLV_IIR));
783 seq_printf(m, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW));
785 seq_printf(m, "Display IMR:\t%08x\n",
786 I915_READ(VLV_IMR));
787 for_each_pipe(dev_priv, pipe)
788 seq_printf(m, "Pipe %c stat:\t%08x\n",
789 pipe_name(pipe),
790 I915_READ(PIPESTAT(pipe)));
791
792 seq_printf(m, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN));
794 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT));
796 seq_printf(m, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 seq_printf(m, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR));
810 seq_printf(m, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR));
812 seq_printf(m, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER));
814 } else if (INTEL_INFO(dev)->gen >= 8) {
815 seq_printf(m, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ));
817
818 for (i = 0; i < 4; i++) {
819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IMR(i)));
821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IIR(i)));
823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
824 i, I915_READ(GEN8_GT_IER(i)));
825 }
826
827 for_each_pipe(dev_priv, pipe) {
828 if (!intel_display_power_is_enabled(dev_priv,
829 POWER_DOMAIN_PIPE(pipe))) {
830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
840 seq_printf(m, "Pipe %c IER:\t%08x\n",
841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
843 }
844
845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR));
847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR));
849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER));
851
852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR));
854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR));
856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER));
858
859 seq_printf(m, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR));
861 seq_printf(m, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR));
863 seq_printf(m, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER));
865 } else if (IS_VALLEYVIEW(dev)) {
866 seq_printf(m, "Display IER:\t%08x\n",
867 I915_READ(VLV_IER));
868 seq_printf(m, "Display IIR:\t%08x\n",
869 I915_READ(VLV_IIR));
870 seq_printf(m, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW));
872 seq_printf(m, "Display IMR:\t%08x\n",
873 I915_READ(VLV_IMR));
874 for_each_pipe(dev_priv, pipe)
875 seq_printf(m, "Pipe %c stat:\t%08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
878
879 seq_printf(m, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER));
881
882 seq_printf(m, "Render IER:\t%08x\n",
883 I915_READ(GTIER));
884 seq_printf(m, "Render IIR:\t%08x\n",
885 I915_READ(GTIIR));
886 seq_printf(m, "Render IMR:\t%08x\n",
887 I915_READ(GTIMR));
888
889 seq_printf(m, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER));
891 seq_printf(m, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR));
893 seq_printf(m, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR));
895
896 seq_printf(m, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN));
898 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT));
900 seq_printf(m, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT));
902
903 } else if (!HAS_PCH_SPLIT(dev)) {
904 seq_printf(m, "Interrupt enable: %08x\n",
905 I915_READ(IER));
906 seq_printf(m, "Interrupt identity: %08x\n",
907 I915_READ(IIR));
908 seq_printf(m, "Interrupt mask: %08x\n",
909 I915_READ(IMR));
910 for_each_pipe(dev_priv, pipe)
911 seq_printf(m, "Pipe %c stat: %08x\n",
912 pipe_name(pipe),
913 I915_READ(PIPESTAT(pipe)));
914 } else {
915 seq_printf(m, "North Display Interrupt enable: %08x\n",
916 I915_READ(DEIER));
917 seq_printf(m, "North Display Interrupt identity: %08x\n",
918 I915_READ(DEIIR));
919 seq_printf(m, "North Display Interrupt mask: %08x\n",
920 I915_READ(DEIMR));
921 seq_printf(m, "South Display Interrupt enable: %08x\n",
922 I915_READ(SDEIER));
923 seq_printf(m, "South Display Interrupt identity: %08x\n",
924 I915_READ(SDEIIR));
925 seq_printf(m, "South Display Interrupt mask: %08x\n",
926 I915_READ(SDEIMR));
927 seq_printf(m, "Graphics Interrupt enable: %08x\n",
928 I915_READ(GTIER));
929 seq_printf(m, "Graphics Interrupt identity: %08x\n",
930 I915_READ(GTIIR));
931 seq_printf(m, "Graphics Interrupt mask: %08x\n",
932 I915_READ(GTIMR));
933 }
934 for_each_ring(ring, dev_priv, i) {
935 if (INTEL_INFO(dev)->gen >= 6) {
936 seq_printf(m,
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring->name, I915_READ_IMR(ring));
939 }
940 i915_ring_seqno_info(m, ring);
941 }
942 intel_runtime_pm_put(dev_priv);
943 mutex_unlock(&dev->struct_mutex);
944
945 return 0;
946 }
947
948 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
949 {
950 struct drm_info_node *node = m->private;
951 struct drm_device *dev = node->minor->dev;
952 struct drm_i915_private *dev_priv = dev->dev_private;
953 int i, ret;
954
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
956 if (ret)
957 return ret;
958
959 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
960 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
961 for (i = 0; i < dev_priv->num_fence_regs; i++) {
962 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
963
964 seq_printf(m, "Fence %d, pin count = %d, object = ",
965 i, dev_priv->fence_regs[i].pin_count);
966 if (obj == NULL)
967 seq_puts(m, "unused");
968 else
969 describe_obj(m, obj);
970 seq_putc(m, '\n');
971 }
972
973 mutex_unlock(&dev->struct_mutex);
974 return 0;
975 }
976
977 static int i915_hws_info(struct seq_file *m, void *data)
978 {
979 struct drm_info_node *node = m->private;
980 struct drm_device *dev = node->minor->dev;
981 struct drm_i915_private *dev_priv = dev->dev_private;
982 struct intel_engine_cs *ring;
983 const u32 *hws;
984 int i;
985
986 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
987 hws = ring->status_page.page_addr;
988 if (hws == NULL)
989 return 0;
990
991 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
992 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
993 i * 4,
994 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
995 }
996 return 0;
997 }
998
999 static ssize_t
1000 i915_error_state_write(struct file *filp,
1001 const char __user *ubuf,
1002 size_t cnt,
1003 loff_t *ppos)
1004 {
1005 struct i915_error_state_file_priv *error_priv = filp->private_data;
1006 struct drm_device *dev = error_priv->dev;
1007 int ret;
1008
1009 DRM_DEBUG_DRIVER("Resetting error state\n");
1010
1011 ret = mutex_lock_interruptible(&dev->struct_mutex);
1012 if (ret)
1013 return ret;
1014
1015 i915_destroy_error_state(dev);
1016 mutex_unlock(&dev->struct_mutex);
1017
1018 return cnt;
1019 }
1020
1021 static int i915_error_state_open(struct inode *inode, struct file *file)
1022 {
1023 struct drm_device *dev = inode->i_private;
1024 struct i915_error_state_file_priv *error_priv;
1025
1026 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1027 if (!error_priv)
1028 return -ENOMEM;
1029
1030 error_priv->dev = dev;
1031
1032 i915_error_state_get(dev, error_priv);
1033
1034 file->private_data = error_priv;
1035
1036 return 0;
1037 }
1038
1039 static int i915_error_state_release(struct inode *inode, struct file *file)
1040 {
1041 struct i915_error_state_file_priv *error_priv = file->private_data;
1042
1043 i915_error_state_put(error_priv);
1044 kfree(error_priv);
1045
1046 return 0;
1047 }
1048
1049 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1050 size_t count, loff_t *pos)
1051 {
1052 struct i915_error_state_file_priv *error_priv = file->private_data;
1053 struct drm_i915_error_state_buf error_str;
1054 loff_t tmp_pos = 0;
1055 ssize_t ret_count = 0;
1056 int ret;
1057
1058 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1059 if (ret)
1060 return ret;
1061
1062 ret = i915_error_state_to_str(&error_str, error_priv);
1063 if (ret)
1064 goto out;
1065
1066 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1067 error_str.buf,
1068 error_str.bytes);
1069
1070 if (ret_count < 0)
1071 ret = ret_count;
1072 else
1073 *pos = error_str.start + ret_count;
1074 out:
1075 i915_error_state_buf_release(&error_str);
1076 return ret ?: ret_count;
1077 }
1078
1079 static const struct file_operations i915_error_state_fops = {
1080 .owner = THIS_MODULE,
1081 .open = i915_error_state_open,
1082 .read = i915_error_state_read,
1083 .write = i915_error_state_write,
1084 .llseek = default_llseek,
1085 .release = i915_error_state_release,
1086 };
1087
1088 static int
1089 i915_next_seqno_get(void *data, u64 *val)
1090 {
1091 struct drm_device *dev = data;
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 int ret;
1094
1095 ret = mutex_lock_interruptible(&dev->struct_mutex);
1096 if (ret)
1097 return ret;
1098
1099 *val = dev_priv->next_seqno;
1100 mutex_unlock(&dev->struct_mutex);
1101
1102 return 0;
1103 }
1104
1105 static int
1106 i915_next_seqno_set(void *data, u64 val)
1107 {
1108 struct drm_device *dev = data;
1109 int ret;
1110
1111 ret = mutex_lock_interruptible(&dev->struct_mutex);
1112 if (ret)
1113 return ret;
1114
1115 ret = i915_gem_set_seqno(dev, val);
1116 mutex_unlock(&dev->struct_mutex);
1117
1118 return ret;
1119 }
1120
1121 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1122 i915_next_seqno_get, i915_next_seqno_set,
1123 "0x%llx\n");
1124
1125 static int i915_frequency_info(struct seq_file *m, void *unused)
1126 {
1127 struct drm_info_node *node = m->private;
1128 struct drm_device *dev = node->minor->dev;
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130 int ret = 0;
1131
1132 intel_runtime_pm_get(dev_priv);
1133
1134 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1135
1136 if (IS_GEN5(dev)) {
1137 u16 rgvswctl = I915_READ16(MEMSWCTL);
1138 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1139
1140 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1141 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1142 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1143 MEMSTAT_VID_SHIFT);
1144 seq_printf(m, "Current P-state: %d\n",
1145 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1146 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1147 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1148 u32 rp_state_limits;
1149 u32 gt_perf_status;
1150 u32 rp_state_cap;
1151 u32 rpmodectl, rpinclimit, rpdeclimit;
1152 u32 rpstat, cagf, reqf;
1153 u32 rpupei, rpcurup, rpprevup;
1154 u32 rpdownei, rpcurdown, rpprevdown;
1155 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1156 int max_freq;
1157
1158 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1159 if (IS_BROXTON(dev)) {
1160 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1161 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1162 } else {
1163 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1164 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1165 }
1166
1167 /* RPSTAT1 is in the GT power well */
1168 ret = mutex_lock_interruptible(&dev->struct_mutex);
1169 if (ret)
1170 goto out;
1171
1172 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1173
1174 reqf = I915_READ(GEN6_RPNSWREQ);
1175 if (IS_GEN9(dev))
1176 reqf >>= 23;
1177 else {
1178 reqf &= ~GEN6_TURBO_DISABLE;
1179 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1180 reqf >>= 24;
1181 else
1182 reqf >>= 25;
1183 }
1184 reqf = intel_gpu_freq(dev_priv, reqf);
1185
1186 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1187 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1188 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1189
1190 rpstat = I915_READ(GEN6_RPSTAT1);
1191 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1192 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1193 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1194 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1195 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1196 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1197 if (IS_GEN9(dev))
1198 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1199 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1200 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1201 else
1202 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1203 cagf = intel_gpu_freq(dev_priv, cagf);
1204
1205 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1206 mutex_unlock(&dev->struct_mutex);
1207
1208 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1209 pm_ier = I915_READ(GEN6_PMIER);
1210 pm_imr = I915_READ(GEN6_PMIMR);
1211 pm_isr = I915_READ(GEN6_PMISR);
1212 pm_iir = I915_READ(GEN6_PMIIR);
1213 pm_mask = I915_READ(GEN6_PMINTRMSK);
1214 } else {
1215 pm_ier = I915_READ(GEN8_GT_IER(2));
1216 pm_imr = I915_READ(GEN8_GT_IMR(2));
1217 pm_isr = I915_READ(GEN8_GT_ISR(2));
1218 pm_iir = I915_READ(GEN8_GT_IIR(2));
1219 pm_mask = I915_READ(GEN6_PMINTRMSK);
1220 }
1221 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1222 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1223 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1224 seq_printf(m, "Render p-state ratio: %d\n",
1225 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1226 seq_printf(m, "Render p-state VID: %d\n",
1227 gt_perf_status & 0xff);
1228 seq_printf(m, "Render p-state limit: %d\n",
1229 rp_state_limits & 0xff);
1230 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1231 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1232 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1233 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1234 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1235 seq_printf(m, "CAGF: %dMHz\n", cagf);
1236 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1237 GEN6_CURICONT_MASK);
1238 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1239 GEN6_CURBSYTAVG_MASK);
1240 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1241 GEN6_CURBSYTAVG_MASK);
1242 seq_printf(m, "Up threshold: %d%%\n",
1243 dev_priv->rps.up_threshold);
1244
1245 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1246 GEN6_CURIAVG_MASK);
1247 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1248 GEN6_CURBSYTAVG_MASK);
1249 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1250 GEN6_CURBSYTAVG_MASK);
1251 seq_printf(m, "Down threshold: %d%%\n",
1252 dev_priv->rps.down_threshold);
1253
1254 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1255 rp_state_cap >> 16) & 0xff;
1256 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1257 GEN9_FREQ_SCALER : 1);
1258 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1259 intel_gpu_freq(dev_priv, max_freq));
1260
1261 max_freq = (rp_state_cap & 0xff00) >> 8;
1262 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1263 GEN9_FREQ_SCALER : 1);
1264 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1265 intel_gpu_freq(dev_priv, max_freq));
1266
1267 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1268 rp_state_cap >> 0) & 0xff;
1269 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1270 GEN9_FREQ_SCALER : 1);
1271 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1272 intel_gpu_freq(dev_priv, max_freq));
1273 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1274 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1275
1276 seq_printf(m, "Current freq: %d MHz\n",
1277 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1278 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1279 seq_printf(m, "Idle freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1281 seq_printf(m, "Min freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1283 seq_printf(m, "Max freq: %d MHz\n",
1284 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1285 seq_printf(m,
1286 "efficient (RPe) frequency: %d MHz\n",
1287 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 u32 freq_sts;
1290
1291 mutex_lock(&dev_priv->rps.hw_lock);
1292 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1293 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1294 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1295
1296 seq_printf(m, "actual GPU freq: %d MHz\n",
1297 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1298
1299 seq_printf(m, "current GPU freq: %d MHz\n",
1300 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1301
1302 seq_printf(m, "max GPU freq: %d MHz\n",
1303 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1304
1305 seq_printf(m, "min GPU freq: %d MHz\n",
1306 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1307
1308 seq_printf(m, "idle GPU freq: %d MHz\n",
1309 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1310
1311 seq_printf(m,
1312 "efficient (RPe) frequency: %d MHz\n",
1313 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1314 mutex_unlock(&dev_priv->rps.hw_lock);
1315 } else {
1316 seq_puts(m, "no P-state info available\n");
1317 }
1318
1319 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1320 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1321 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1322
1323 out:
1324 intel_runtime_pm_put(dev_priv);
1325 return ret;
1326 }
1327
1328 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1329 {
1330 struct drm_info_node *node = m->private;
1331 struct drm_device *dev = node->minor->dev;
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 struct intel_engine_cs *ring;
1334 u64 acthd[I915_NUM_RINGS];
1335 u32 seqno[I915_NUM_RINGS];
1336 int i;
1337
1338 if (!i915.enable_hangcheck) {
1339 seq_printf(m, "Hangcheck disabled\n");
1340 return 0;
1341 }
1342
1343 intel_runtime_pm_get(dev_priv);
1344
1345 for_each_ring(ring, dev_priv, i) {
1346 seqno[i] = ring->get_seqno(ring, false);
1347 acthd[i] = intel_ring_get_active_head(ring);
1348 }
1349
1350 intel_runtime_pm_put(dev_priv);
1351
1352 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1353 seq_printf(m, "Hangcheck active, fires in %dms\n",
1354 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1355 jiffies));
1356 } else
1357 seq_printf(m, "Hangcheck inactive\n");
1358
1359 for_each_ring(ring, dev_priv, i) {
1360 seq_printf(m, "%s:\n", ring->name);
1361 seq_printf(m, "\tseqno = %x [current %x]\n",
1362 ring->hangcheck.seqno, seqno[i]);
1363 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1364 (long long)ring->hangcheck.acthd,
1365 (long long)acthd[i]);
1366 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1367 (long long)ring->hangcheck.max_acthd);
1368 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1369 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1370 }
1371
1372 return 0;
1373 }
1374
1375 static int ironlake_drpc_info(struct seq_file *m)
1376 {
1377 struct drm_info_node *node = m->private;
1378 struct drm_device *dev = node->minor->dev;
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380 u32 rgvmodectl, rstdbyctl;
1381 u16 crstandvid;
1382 int ret;
1383
1384 ret = mutex_lock_interruptible(&dev->struct_mutex);
1385 if (ret)
1386 return ret;
1387 intel_runtime_pm_get(dev_priv);
1388
1389 rgvmodectl = I915_READ(MEMMODECTL);
1390 rstdbyctl = I915_READ(RSTDBYCTL);
1391 crstandvid = I915_READ16(CRSTANDVID);
1392
1393 intel_runtime_pm_put(dev_priv);
1394 mutex_unlock(&dev->struct_mutex);
1395
1396 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1397 seq_printf(m, "Boost freq: %d\n",
1398 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1399 MEMMODE_BOOST_FREQ_SHIFT);
1400 seq_printf(m, "HW control enabled: %s\n",
1401 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1402 seq_printf(m, "SW control enabled: %s\n",
1403 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1404 seq_printf(m, "Gated voltage change: %s\n",
1405 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1406 seq_printf(m, "Starting frequency: P%d\n",
1407 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1408 seq_printf(m, "Max P-state: P%d\n",
1409 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1410 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1411 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1412 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1413 seq_printf(m, "Render standby enabled: %s\n",
1414 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1415 seq_puts(m, "Current RS state: ");
1416 switch (rstdbyctl & RSX_STATUS_MASK) {
1417 case RSX_STATUS_ON:
1418 seq_puts(m, "on\n");
1419 break;
1420 case RSX_STATUS_RC1:
1421 seq_puts(m, "RC1\n");
1422 break;
1423 case RSX_STATUS_RC1E:
1424 seq_puts(m, "RC1E\n");
1425 break;
1426 case RSX_STATUS_RS1:
1427 seq_puts(m, "RS1\n");
1428 break;
1429 case RSX_STATUS_RS2:
1430 seq_puts(m, "RS2 (RC6)\n");
1431 break;
1432 case RSX_STATUS_RS3:
1433 seq_puts(m, "RC3 (RC6+)\n");
1434 break;
1435 default:
1436 seq_puts(m, "unknown\n");
1437 break;
1438 }
1439
1440 return 0;
1441 }
1442
1443 static int i915_forcewake_domains(struct seq_file *m, void *data)
1444 {
1445 struct drm_info_node *node = m->private;
1446 struct drm_device *dev = node->minor->dev;
1447 struct drm_i915_private *dev_priv = dev->dev_private;
1448 struct intel_uncore_forcewake_domain *fw_domain;
1449 int i;
1450
1451 spin_lock_irq(&dev_priv->uncore.lock);
1452 for_each_fw_domain(fw_domain, dev_priv, i) {
1453 seq_printf(m, "%s.wake_count = %u\n",
1454 intel_uncore_forcewake_domain_to_str(i),
1455 fw_domain->wake_count);
1456 }
1457 spin_unlock_irq(&dev_priv->uncore.lock);
1458
1459 return 0;
1460 }
1461
1462 static int vlv_drpc_info(struct seq_file *m)
1463 {
1464 struct drm_info_node *node = m->private;
1465 struct drm_device *dev = node->minor->dev;
1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467 u32 rpmodectl1, rcctl1, pw_status;
1468
1469 intel_runtime_pm_get(dev_priv);
1470
1471 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1472 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1473 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1474
1475 intel_runtime_pm_put(dev_priv);
1476
1477 seq_printf(m, "Video Turbo Mode: %s\n",
1478 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1479 seq_printf(m, "Turbo enabled: %s\n",
1480 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1481 seq_printf(m, "HW control enabled: %s\n",
1482 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1483 seq_printf(m, "SW control enabled: %s\n",
1484 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1485 GEN6_RP_MEDIA_SW_MODE));
1486 seq_printf(m, "RC6 Enabled: %s\n",
1487 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1488 GEN6_RC_CTL_EI_MODE(1))));
1489 seq_printf(m, "Render Power Well: %s\n",
1490 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1491 seq_printf(m, "Media Power Well: %s\n",
1492 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1493
1494 seq_printf(m, "Render RC6 residency since boot: %u\n",
1495 I915_READ(VLV_GT_RENDER_RC6));
1496 seq_printf(m, "Media RC6 residency since boot: %u\n",
1497 I915_READ(VLV_GT_MEDIA_RC6));
1498
1499 return i915_forcewake_domains(m, NULL);
1500 }
1501
1502 static int gen6_drpc_info(struct seq_file *m)
1503 {
1504 struct drm_info_node *node = m->private;
1505 struct drm_device *dev = node->minor->dev;
1506 struct drm_i915_private *dev_priv = dev->dev_private;
1507 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1508 unsigned forcewake_count;
1509 int count = 0, ret;
1510
1511 ret = mutex_lock_interruptible(&dev->struct_mutex);
1512 if (ret)
1513 return ret;
1514 intel_runtime_pm_get(dev_priv);
1515
1516 spin_lock_irq(&dev_priv->uncore.lock);
1517 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1518 spin_unlock_irq(&dev_priv->uncore.lock);
1519
1520 if (forcewake_count) {
1521 seq_puts(m, "RC information inaccurate because somebody "
1522 "holds a forcewake reference \n");
1523 } else {
1524 /* NB: we cannot use forcewake, else we read the wrong values */
1525 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1526 udelay(10);
1527 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1528 }
1529
1530 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1531 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1532
1533 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1534 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1535 mutex_unlock(&dev->struct_mutex);
1536 mutex_lock(&dev_priv->rps.hw_lock);
1537 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1538 mutex_unlock(&dev_priv->rps.hw_lock);
1539
1540 intel_runtime_pm_put(dev_priv);
1541
1542 seq_printf(m, "Video Turbo Mode: %s\n",
1543 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1544 seq_printf(m, "HW control enabled: %s\n",
1545 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1546 seq_printf(m, "SW control enabled: %s\n",
1547 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1548 GEN6_RP_MEDIA_SW_MODE));
1549 seq_printf(m, "RC1e Enabled: %s\n",
1550 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1551 seq_printf(m, "RC6 Enabled: %s\n",
1552 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1553 seq_printf(m, "Deep RC6 Enabled: %s\n",
1554 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1555 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1556 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1557 seq_puts(m, "Current RC state: ");
1558 switch (gt_core_status & GEN6_RCn_MASK) {
1559 case GEN6_RC0:
1560 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1561 seq_puts(m, "Core Power Down\n");
1562 else
1563 seq_puts(m, "on\n");
1564 break;
1565 case GEN6_RC3:
1566 seq_puts(m, "RC3\n");
1567 break;
1568 case GEN6_RC6:
1569 seq_puts(m, "RC6\n");
1570 break;
1571 case GEN6_RC7:
1572 seq_puts(m, "RC7\n");
1573 break;
1574 default:
1575 seq_puts(m, "Unknown\n");
1576 break;
1577 }
1578
1579 seq_printf(m, "Core Power Down: %s\n",
1580 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1581
1582 /* Not exactly sure what this is */
1583 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1584 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1585 seq_printf(m, "RC6 residency since boot: %u\n",
1586 I915_READ(GEN6_GT_GFX_RC6));
1587 seq_printf(m, "RC6+ residency since boot: %u\n",
1588 I915_READ(GEN6_GT_GFX_RC6p));
1589 seq_printf(m, "RC6++ residency since boot: %u\n",
1590 I915_READ(GEN6_GT_GFX_RC6pp));
1591
1592 seq_printf(m, "RC6 voltage: %dmV\n",
1593 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1594 seq_printf(m, "RC6+ voltage: %dmV\n",
1595 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1596 seq_printf(m, "RC6++ voltage: %dmV\n",
1597 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1598 return 0;
1599 }
1600
1601 static int i915_drpc_info(struct seq_file *m, void *unused)
1602 {
1603 struct drm_info_node *node = m->private;
1604 struct drm_device *dev = node->minor->dev;
1605
1606 if (IS_VALLEYVIEW(dev))
1607 return vlv_drpc_info(m);
1608 else if (INTEL_INFO(dev)->gen >= 6)
1609 return gen6_drpc_info(m);
1610 else
1611 return ironlake_drpc_info(m);
1612 }
1613
1614 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1615 {
1616 struct drm_info_node *node = m->private;
1617 struct drm_device *dev = node->minor->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1621 dev_priv->fb_tracking.busy_bits);
1622
1623 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1624 dev_priv->fb_tracking.flip_bits);
1625
1626 return 0;
1627 }
1628
1629 static int i915_fbc_status(struct seq_file *m, void *unused)
1630 {
1631 struct drm_info_node *node = m->private;
1632 struct drm_device *dev = node->minor->dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634
1635 if (!HAS_FBC(dev)) {
1636 seq_puts(m, "FBC unsupported on this chipset\n");
1637 return 0;
1638 }
1639
1640 intel_runtime_pm_get(dev_priv);
1641 mutex_lock(&dev_priv->fbc.lock);
1642
1643 if (intel_fbc_enabled(dev_priv))
1644 seq_puts(m, "FBC enabled\n");
1645 else
1646 seq_printf(m, "FBC disabled: %s\n",
1647 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1648
1649 if (INTEL_INFO(dev_priv)->gen >= 7)
1650 seq_printf(m, "Compressing: %s\n",
1651 yesno(I915_READ(FBC_STATUS2) &
1652 FBC_COMPRESSION_MASK));
1653
1654 mutex_unlock(&dev_priv->fbc.lock);
1655 intel_runtime_pm_put(dev_priv);
1656
1657 return 0;
1658 }
1659
1660 static int i915_fbc_fc_get(void *data, u64 *val)
1661 {
1662 struct drm_device *dev = data;
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1666 return -ENODEV;
1667
1668 *val = dev_priv->fbc.false_color;
1669
1670 return 0;
1671 }
1672
1673 static int i915_fbc_fc_set(void *data, u64 val)
1674 {
1675 struct drm_device *dev = data;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 u32 reg;
1678
1679 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1680 return -ENODEV;
1681
1682 mutex_lock(&dev_priv->fbc.lock);
1683
1684 reg = I915_READ(ILK_DPFC_CONTROL);
1685 dev_priv->fbc.false_color = val;
1686
1687 I915_WRITE(ILK_DPFC_CONTROL, val ?
1688 (reg | FBC_CTL_FALSE_COLOR) :
1689 (reg & ~FBC_CTL_FALSE_COLOR));
1690
1691 mutex_unlock(&dev_priv->fbc.lock);
1692 return 0;
1693 }
1694
1695 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1696 i915_fbc_fc_get, i915_fbc_fc_set,
1697 "%llu\n");
1698
1699 static int i915_ips_status(struct seq_file *m, void *unused)
1700 {
1701 struct drm_info_node *node = m->private;
1702 struct drm_device *dev = node->minor->dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704
1705 if (!HAS_IPS(dev)) {
1706 seq_puts(m, "not supported\n");
1707 return 0;
1708 }
1709
1710 intel_runtime_pm_get(dev_priv);
1711
1712 seq_printf(m, "Enabled by kernel parameter: %s\n",
1713 yesno(i915.enable_ips));
1714
1715 if (INTEL_INFO(dev)->gen >= 8) {
1716 seq_puts(m, "Currently: unknown\n");
1717 } else {
1718 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1719 seq_puts(m, "Currently: enabled\n");
1720 else
1721 seq_puts(m, "Currently: disabled\n");
1722 }
1723
1724 intel_runtime_pm_put(dev_priv);
1725
1726 return 0;
1727 }
1728
1729 static int i915_sr_status(struct seq_file *m, void *unused)
1730 {
1731 struct drm_info_node *node = m->private;
1732 struct drm_device *dev = node->minor->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734 bool sr_enabled = false;
1735
1736 intel_runtime_pm_get(dev_priv);
1737
1738 if (HAS_PCH_SPLIT(dev))
1739 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1740 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1741 IS_I945G(dev) || IS_I945GM(dev))
1742 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1743 else if (IS_I915GM(dev))
1744 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1745 else if (IS_PINEVIEW(dev))
1746 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1747 else if (IS_VALLEYVIEW(dev))
1748 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1749
1750 intel_runtime_pm_put(dev_priv);
1751
1752 seq_printf(m, "self-refresh: %s\n",
1753 sr_enabled ? "enabled" : "disabled");
1754
1755 return 0;
1756 }
1757
1758 static int i915_emon_status(struct seq_file *m, void *unused)
1759 {
1760 struct drm_info_node *node = m->private;
1761 struct drm_device *dev = node->minor->dev;
1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 unsigned long temp, chipset, gfx;
1764 int ret;
1765
1766 if (!IS_GEN5(dev))
1767 return -ENODEV;
1768
1769 ret = mutex_lock_interruptible(&dev->struct_mutex);
1770 if (ret)
1771 return ret;
1772
1773 temp = i915_mch_val(dev_priv);
1774 chipset = i915_chipset_val(dev_priv);
1775 gfx = i915_gfx_val(dev_priv);
1776 mutex_unlock(&dev->struct_mutex);
1777
1778 seq_printf(m, "GMCH temp: %ld\n", temp);
1779 seq_printf(m, "Chipset power: %ld\n", chipset);
1780 seq_printf(m, "GFX power: %ld\n", gfx);
1781 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1782
1783 return 0;
1784 }
1785
1786 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1787 {
1788 struct drm_info_node *node = m->private;
1789 struct drm_device *dev = node->minor->dev;
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 int ret = 0;
1792 int gpu_freq, ia_freq;
1793 unsigned int max_gpu_freq, min_gpu_freq;
1794
1795 if (!HAS_CORE_RING_FREQ(dev)) {
1796 seq_puts(m, "unsupported on this chipset\n");
1797 return 0;
1798 }
1799
1800 intel_runtime_pm_get(dev_priv);
1801
1802 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1803
1804 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1805 if (ret)
1806 goto out;
1807
1808 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1809 /* Convert GT frequency to 50 HZ units */
1810 min_gpu_freq =
1811 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1812 max_gpu_freq =
1813 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1814 } else {
1815 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1816 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1817 }
1818
1819 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1820
1821 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1822 ia_freq = gpu_freq;
1823 sandybridge_pcode_read(dev_priv,
1824 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1825 &ia_freq);
1826 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1827 intel_gpu_freq(dev_priv, (gpu_freq *
1828 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1829 GEN9_FREQ_SCALER : 1))),
1830 ((ia_freq >> 0) & 0xff) * 100,
1831 ((ia_freq >> 8) & 0xff) * 100);
1832 }
1833
1834 mutex_unlock(&dev_priv->rps.hw_lock);
1835
1836 out:
1837 intel_runtime_pm_put(dev_priv);
1838 return ret;
1839 }
1840
1841 static int i915_opregion(struct seq_file *m, void *unused)
1842 {
1843 struct drm_info_node *node = m->private;
1844 struct drm_device *dev = node->minor->dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 struct intel_opregion *opregion = &dev_priv->opregion;
1847 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1848 int ret;
1849
1850 if (data == NULL)
1851 return -ENOMEM;
1852
1853 ret = mutex_lock_interruptible(&dev->struct_mutex);
1854 if (ret)
1855 goto out;
1856
1857 if (opregion->header) {
1858 memcpy(data, opregion->header, OPREGION_SIZE);
1859 seq_write(m, data, OPREGION_SIZE);
1860 }
1861
1862 mutex_unlock(&dev->struct_mutex);
1863
1864 out:
1865 kfree(data);
1866 return 0;
1867 }
1868
1869 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1870 {
1871 struct drm_info_node *node = m->private;
1872 struct drm_device *dev = node->minor->dev;
1873 struct intel_fbdev *ifbdev = NULL;
1874 struct intel_framebuffer *fb;
1875 struct drm_framebuffer *drm_fb;
1876
1877 #ifdef CONFIG_DRM_FBDEV_EMULATION
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879
1880 ifbdev = dev_priv->fbdev;
1881 fb = to_intel_framebuffer(ifbdev->helper.fb);
1882
1883 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1884 fb->base.width,
1885 fb->base.height,
1886 fb->base.depth,
1887 fb->base.bits_per_pixel,
1888 fb->base.modifier[0],
1889 atomic_read(&fb->base.refcount.refcount));
1890 describe_obj(m, fb->obj);
1891 seq_putc(m, '\n');
1892 #endif
1893
1894 mutex_lock(&dev->mode_config.fb_lock);
1895 drm_for_each_fb(drm_fb, dev) {
1896 fb = to_intel_framebuffer(drm_fb);
1897 if (ifbdev && &fb->base == ifbdev->helper.fb)
1898 continue;
1899
1900 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1901 fb->base.width,
1902 fb->base.height,
1903 fb->base.depth,
1904 fb->base.bits_per_pixel,
1905 fb->base.modifier[0],
1906 atomic_read(&fb->base.refcount.refcount));
1907 describe_obj(m, fb->obj);
1908 seq_putc(m, '\n');
1909 }
1910 mutex_unlock(&dev->mode_config.fb_lock);
1911
1912 return 0;
1913 }
1914
1915 static void describe_ctx_ringbuf(struct seq_file *m,
1916 struct intel_ringbuffer *ringbuf)
1917 {
1918 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1919 ringbuf->space, ringbuf->head, ringbuf->tail,
1920 ringbuf->last_retired_head);
1921 }
1922
1923 static int i915_context_status(struct seq_file *m, void *unused)
1924 {
1925 struct drm_info_node *node = m->private;
1926 struct drm_device *dev = node->minor->dev;
1927 struct drm_i915_private *dev_priv = dev->dev_private;
1928 struct intel_engine_cs *ring;
1929 struct intel_context *ctx;
1930 int ret, i;
1931
1932 ret = mutex_lock_interruptible(&dev->struct_mutex);
1933 if (ret)
1934 return ret;
1935
1936 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1937 if (!i915.enable_execlists &&
1938 ctx->legacy_hw_ctx.rcs_state == NULL)
1939 continue;
1940
1941 seq_puts(m, "HW context ");
1942 describe_ctx(m, ctx);
1943 for_each_ring(ring, dev_priv, i) {
1944 if (ring->default_context == ctx)
1945 seq_printf(m, "(default context %s) ",
1946 ring->name);
1947 }
1948
1949 if (i915.enable_execlists) {
1950 seq_putc(m, '\n');
1951 for_each_ring(ring, dev_priv, i) {
1952 struct drm_i915_gem_object *ctx_obj =
1953 ctx->engine[i].state;
1954 struct intel_ringbuffer *ringbuf =
1955 ctx->engine[i].ringbuf;
1956
1957 seq_printf(m, "%s: ", ring->name);
1958 if (ctx_obj)
1959 describe_obj(m, ctx_obj);
1960 if (ringbuf)
1961 describe_ctx_ringbuf(m, ringbuf);
1962 seq_putc(m, '\n');
1963 }
1964 } else {
1965 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1966 }
1967
1968 seq_putc(m, '\n');
1969 }
1970
1971 mutex_unlock(&dev->struct_mutex);
1972
1973 return 0;
1974 }
1975
1976 static void i915_dump_lrc_obj(struct seq_file *m,
1977 struct intel_engine_cs *ring,
1978 struct drm_i915_gem_object *ctx_obj)
1979 {
1980 struct page *page;
1981 uint32_t *reg_state;
1982 int j;
1983 unsigned long ggtt_offset = 0;
1984
1985 if (ctx_obj == NULL) {
1986 seq_printf(m, "Context on %s with no gem object\n",
1987 ring->name);
1988 return;
1989 }
1990
1991 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1992 intel_execlists_ctx_id(ctx_obj));
1993
1994 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1995 seq_puts(m, "\tNot bound in GGTT\n");
1996 else
1997 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1998
1999 if (i915_gem_object_get_pages(ctx_obj)) {
2000 seq_puts(m, "\tFailed to get pages for context object\n");
2001 return;
2002 }
2003
2004 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2005 if (!WARN_ON(page == NULL)) {
2006 reg_state = kmap_atomic(page);
2007
2008 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2009 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2010 ggtt_offset + 4096 + (j * 4),
2011 reg_state[j], reg_state[j + 1],
2012 reg_state[j + 2], reg_state[j + 3]);
2013 }
2014 kunmap_atomic(reg_state);
2015 }
2016
2017 seq_putc(m, '\n');
2018 }
2019
2020 static int i915_dump_lrc(struct seq_file *m, void *unused)
2021 {
2022 struct drm_info_node *node = (struct drm_info_node *) m->private;
2023 struct drm_device *dev = node->minor->dev;
2024 struct drm_i915_private *dev_priv = dev->dev_private;
2025 struct intel_engine_cs *ring;
2026 struct intel_context *ctx;
2027 int ret, i;
2028
2029 if (!i915.enable_execlists) {
2030 seq_printf(m, "Logical Ring Contexts are disabled\n");
2031 return 0;
2032 }
2033
2034 ret = mutex_lock_interruptible(&dev->struct_mutex);
2035 if (ret)
2036 return ret;
2037
2038 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2039 for_each_ring(ring, dev_priv, i) {
2040 if (ring->default_context != ctx)
2041 i915_dump_lrc_obj(m, ring,
2042 ctx->engine[i].state);
2043 }
2044 }
2045
2046 mutex_unlock(&dev->struct_mutex);
2047
2048 return 0;
2049 }
2050
2051 static int i915_execlists(struct seq_file *m, void *data)
2052 {
2053 struct drm_info_node *node = (struct drm_info_node *)m->private;
2054 struct drm_device *dev = node->minor->dev;
2055 struct drm_i915_private *dev_priv = dev->dev_private;
2056 struct intel_engine_cs *ring;
2057 u32 status_pointer;
2058 u8 read_pointer;
2059 u8 write_pointer;
2060 u32 status;
2061 u32 ctx_id;
2062 struct list_head *cursor;
2063 int ring_id, i;
2064 int ret;
2065
2066 if (!i915.enable_execlists) {
2067 seq_puts(m, "Logical Ring Contexts are disabled\n");
2068 return 0;
2069 }
2070
2071 ret = mutex_lock_interruptible(&dev->struct_mutex);
2072 if (ret)
2073 return ret;
2074
2075 intel_runtime_pm_get(dev_priv);
2076
2077 for_each_ring(ring, dev_priv, ring_id) {
2078 struct drm_i915_gem_request *head_req = NULL;
2079 int count = 0;
2080 unsigned long flags;
2081
2082 seq_printf(m, "%s\n", ring->name);
2083
2084 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2085 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2086 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2087 status, ctx_id);
2088
2089 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2090 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2091
2092 read_pointer = ring->next_context_status_buffer;
2093 write_pointer = status_pointer & 0x07;
2094 if (read_pointer > write_pointer)
2095 write_pointer += 6;
2096 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2097 read_pointer, write_pointer);
2098
2099 for (i = 0; i < 6; i++) {
2100 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2101 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2102
2103 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2104 i, status, ctx_id);
2105 }
2106
2107 spin_lock_irqsave(&ring->execlist_lock, flags);
2108 list_for_each(cursor, &ring->execlist_queue)
2109 count++;
2110 head_req = list_first_entry_or_null(&ring->execlist_queue,
2111 struct drm_i915_gem_request, execlist_link);
2112 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2113
2114 seq_printf(m, "\t%d requests in queue\n", count);
2115 if (head_req) {
2116 struct drm_i915_gem_object *ctx_obj;
2117
2118 ctx_obj = head_req->ctx->engine[ring_id].state;
2119 seq_printf(m, "\tHead request id: %u\n",
2120 intel_execlists_ctx_id(ctx_obj));
2121 seq_printf(m, "\tHead request tail: %u\n",
2122 head_req->tail);
2123 }
2124
2125 seq_putc(m, '\n');
2126 }
2127
2128 intel_runtime_pm_put(dev_priv);
2129 mutex_unlock(&dev->struct_mutex);
2130
2131 return 0;
2132 }
2133
2134 static const char *swizzle_string(unsigned swizzle)
2135 {
2136 switch (swizzle) {
2137 case I915_BIT_6_SWIZZLE_NONE:
2138 return "none";
2139 case I915_BIT_6_SWIZZLE_9:
2140 return "bit9";
2141 case I915_BIT_6_SWIZZLE_9_10:
2142 return "bit9/bit10";
2143 case I915_BIT_6_SWIZZLE_9_11:
2144 return "bit9/bit11";
2145 case I915_BIT_6_SWIZZLE_9_10_11:
2146 return "bit9/bit10/bit11";
2147 case I915_BIT_6_SWIZZLE_9_17:
2148 return "bit9/bit17";
2149 case I915_BIT_6_SWIZZLE_9_10_17:
2150 return "bit9/bit10/bit17";
2151 case I915_BIT_6_SWIZZLE_UNKNOWN:
2152 return "unknown";
2153 }
2154
2155 return "bug";
2156 }
2157
2158 static int i915_swizzle_info(struct seq_file *m, void *data)
2159 {
2160 struct drm_info_node *node = m->private;
2161 struct drm_device *dev = node->minor->dev;
2162 struct drm_i915_private *dev_priv = dev->dev_private;
2163 int ret;
2164
2165 ret = mutex_lock_interruptible(&dev->struct_mutex);
2166 if (ret)
2167 return ret;
2168 intel_runtime_pm_get(dev_priv);
2169
2170 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2171 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2172 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2173 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2174
2175 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2176 seq_printf(m, "DDC = 0x%08x\n",
2177 I915_READ(DCC));
2178 seq_printf(m, "DDC2 = 0x%08x\n",
2179 I915_READ(DCC2));
2180 seq_printf(m, "C0DRB3 = 0x%04x\n",
2181 I915_READ16(C0DRB3));
2182 seq_printf(m, "C1DRB3 = 0x%04x\n",
2183 I915_READ16(C1DRB3));
2184 } else if (INTEL_INFO(dev)->gen >= 6) {
2185 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2186 I915_READ(MAD_DIMM_C0));
2187 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2188 I915_READ(MAD_DIMM_C1));
2189 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2190 I915_READ(MAD_DIMM_C2));
2191 seq_printf(m, "TILECTL = 0x%08x\n",
2192 I915_READ(TILECTL));
2193 if (INTEL_INFO(dev)->gen >= 8)
2194 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2195 I915_READ(GAMTARBMODE));
2196 else
2197 seq_printf(m, "ARB_MODE = 0x%08x\n",
2198 I915_READ(ARB_MODE));
2199 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2200 I915_READ(DISP_ARB_CTL));
2201 }
2202
2203 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2204 seq_puts(m, "L-shaped memory detected\n");
2205
2206 intel_runtime_pm_put(dev_priv);
2207 mutex_unlock(&dev->struct_mutex);
2208
2209 return 0;
2210 }
2211
2212 static int per_file_ctx(int id, void *ptr, void *data)
2213 {
2214 struct intel_context *ctx = ptr;
2215 struct seq_file *m = data;
2216 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2217
2218 if (!ppgtt) {
2219 seq_printf(m, " no ppgtt for context %d\n",
2220 ctx->user_handle);
2221 return 0;
2222 }
2223
2224 if (i915_gem_context_is_default(ctx))
2225 seq_puts(m, " default context:\n");
2226 else
2227 seq_printf(m, " context %d:\n", ctx->user_handle);
2228 ppgtt->debug_dump(ppgtt, m);
2229
2230 return 0;
2231 }
2232
2233 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2234 {
2235 struct drm_i915_private *dev_priv = dev->dev_private;
2236 struct intel_engine_cs *ring;
2237 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2238 int unused, i;
2239
2240 if (!ppgtt)
2241 return;
2242
2243 for_each_ring(ring, dev_priv, unused) {
2244 seq_printf(m, "%s\n", ring->name);
2245 for (i = 0; i < 4; i++) {
2246 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2247 pdp <<= 32;
2248 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2249 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2250 }
2251 }
2252 }
2253
2254 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2255 {
2256 struct drm_i915_private *dev_priv = dev->dev_private;
2257 struct intel_engine_cs *ring;
2258 int i;
2259
2260 if (INTEL_INFO(dev)->gen == 6)
2261 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2262
2263 for_each_ring(ring, dev_priv, i) {
2264 seq_printf(m, "%s\n", ring->name);
2265 if (INTEL_INFO(dev)->gen == 7)
2266 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2267 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2268 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2269 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2270 }
2271 if (dev_priv->mm.aliasing_ppgtt) {
2272 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2273
2274 seq_puts(m, "aliasing PPGTT:\n");
2275 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2276
2277 ppgtt->debug_dump(ppgtt, m);
2278 }
2279
2280 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2281 }
2282
2283 static int i915_ppgtt_info(struct seq_file *m, void *data)
2284 {
2285 struct drm_info_node *node = m->private;
2286 struct drm_device *dev = node->minor->dev;
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288 struct drm_file *file;
2289
2290 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2291 if (ret)
2292 return ret;
2293 intel_runtime_pm_get(dev_priv);
2294
2295 if (INTEL_INFO(dev)->gen >= 8)
2296 gen8_ppgtt_info(m, dev);
2297 else if (INTEL_INFO(dev)->gen >= 6)
2298 gen6_ppgtt_info(m, dev);
2299
2300 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2301 struct drm_i915_file_private *file_priv = file->driver_priv;
2302 struct task_struct *task;
2303
2304 task = get_pid_task(file->pid, PIDTYPE_PID);
2305 if (!task) {
2306 ret = -ESRCH;
2307 goto out_put;
2308 }
2309 seq_printf(m, "\nproc: %s\n", task->comm);
2310 put_task_struct(task);
2311 idr_for_each(&file_priv->context_idr, per_file_ctx,
2312 (void *)(unsigned long)m);
2313 }
2314
2315 out_put:
2316 intel_runtime_pm_put(dev_priv);
2317 mutex_unlock(&dev->struct_mutex);
2318
2319 return ret;
2320 }
2321
2322 static int count_irq_waiters(struct drm_i915_private *i915)
2323 {
2324 struct intel_engine_cs *ring;
2325 int count = 0;
2326 int i;
2327
2328 for_each_ring(ring, i915, i)
2329 count += ring->irq_refcount;
2330
2331 return count;
2332 }
2333
2334 static int i915_rps_boost_info(struct seq_file *m, void *data)
2335 {
2336 struct drm_info_node *node = m->private;
2337 struct drm_device *dev = node->minor->dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct drm_file *file;
2340
2341 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2342 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2343 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2344 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2345 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2346 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2347 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2348 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2349 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2350 spin_lock(&dev_priv->rps.client_lock);
2351 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2352 struct drm_i915_file_private *file_priv = file->driver_priv;
2353 struct task_struct *task;
2354
2355 rcu_read_lock();
2356 task = pid_task(file->pid, PIDTYPE_PID);
2357 seq_printf(m, "%s [%d]: %d boosts%s\n",
2358 task ? task->comm : "<unknown>",
2359 task ? task->pid : -1,
2360 file_priv->rps.boosts,
2361 list_empty(&file_priv->rps.link) ? "" : ", active");
2362 rcu_read_unlock();
2363 }
2364 seq_printf(m, "Semaphore boosts: %d%s\n",
2365 dev_priv->rps.semaphores.boosts,
2366 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2367 seq_printf(m, "MMIO flip boosts: %d%s\n",
2368 dev_priv->rps.mmioflips.boosts,
2369 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2370 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2371 spin_unlock(&dev_priv->rps.client_lock);
2372
2373 return 0;
2374 }
2375
2376 static int i915_llc(struct seq_file *m, void *data)
2377 {
2378 struct drm_info_node *node = m->private;
2379 struct drm_device *dev = node->minor->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381
2382 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2383 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2384 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2385
2386 return 0;
2387 }
2388
2389 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2390 {
2391 struct drm_info_node *node = m->private;
2392 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2393 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2394 u32 tmp, i;
2395
2396 if (!HAS_GUC_UCODE(dev_priv->dev))
2397 return 0;
2398
2399 seq_printf(m, "GuC firmware status:\n");
2400 seq_printf(m, "\tpath: %s\n",
2401 guc_fw->guc_fw_path);
2402 seq_printf(m, "\tfetch: %s\n",
2403 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2404 seq_printf(m, "\tload: %s\n",
2405 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2406 seq_printf(m, "\tversion wanted: %d.%d\n",
2407 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2408 seq_printf(m, "\tversion found: %d.%d\n",
2409 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2410 seq_printf(m, "\theader: offset is %d; size = %d\n",
2411 guc_fw->header_offset, guc_fw->header_size);
2412 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2413 guc_fw->ucode_offset, guc_fw->ucode_size);
2414 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2415 guc_fw->rsa_offset, guc_fw->rsa_size);
2416
2417 tmp = I915_READ(GUC_STATUS);
2418
2419 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2420 seq_printf(m, "\tBootrom status = 0x%x\n",
2421 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2422 seq_printf(m, "\tuKernel status = 0x%x\n",
2423 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2424 seq_printf(m, "\tMIA Core status = 0x%x\n",
2425 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2426 seq_puts(m, "\nScratch registers:\n");
2427 for (i = 0; i < 16; i++)
2428 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2429
2430 return 0;
2431 }
2432
2433 static void i915_guc_client_info(struct seq_file *m,
2434 struct drm_i915_private *dev_priv,
2435 struct i915_guc_client *client)
2436 {
2437 struct intel_engine_cs *ring;
2438 uint64_t tot = 0;
2439 uint32_t i;
2440
2441 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2442 client->priority, client->ctx_index, client->proc_desc_offset);
2443 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2444 client->doorbell_id, client->doorbell_offset, client->cookie);
2445 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2446 client->wq_size, client->wq_offset, client->wq_tail);
2447
2448 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2449 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2450 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2451
2452 for_each_ring(ring, dev_priv, i) {
2453 seq_printf(m, "\tSubmissions: %llu %s\n",
2454 client->submissions[i],
2455 ring->name);
2456 tot += client->submissions[i];
2457 }
2458 seq_printf(m, "\tTotal: %llu\n", tot);
2459 }
2460
2461 static int i915_guc_info(struct seq_file *m, void *data)
2462 {
2463 struct drm_info_node *node = m->private;
2464 struct drm_device *dev = node->minor->dev;
2465 struct drm_i915_private *dev_priv = dev->dev_private;
2466 struct intel_guc guc;
2467 struct i915_guc_client client = {};
2468 struct intel_engine_cs *ring;
2469 enum intel_ring_id i;
2470 u64 total = 0;
2471
2472 if (!HAS_GUC_SCHED(dev_priv->dev))
2473 return 0;
2474
2475 /* Take a local copy of the GuC data, so we can dump it at leisure */
2476 spin_lock(&dev_priv->guc.host2guc_lock);
2477 guc = dev_priv->guc;
2478 if (guc.execbuf_client) {
2479 spin_lock(&guc.execbuf_client->wq_lock);
2480 client = *guc.execbuf_client;
2481 spin_unlock(&guc.execbuf_client->wq_lock);
2482 }
2483 spin_unlock(&dev_priv->guc.host2guc_lock);
2484
2485 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2486 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2487 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2488 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2489 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2490
2491 seq_printf(m, "\nGuC submissions:\n");
2492 for_each_ring(ring, dev_priv, i) {
2493 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2494 ring->name, guc.submissions[i],
2495 guc.last_seqno[i], guc.last_seqno[i]);
2496 total += guc.submissions[i];
2497 }
2498 seq_printf(m, "\t%s: %llu\n", "Total", total);
2499
2500 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2501 i915_guc_client_info(m, dev_priv, &client);
2502
2503 /* Add more as required ... */
2504
2505 return 0;
2506 }
2507
2508 static int i915_guc_log_dump(struct seq_file *m, void *data)
2509 {
2510 struct drm_info_node *node = m->private;
2511 struct drm_device *dev = node->minor->dev;
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2514 u32 *log;
2515 int i = 0, pg;
2516
2517 if (!log_obj)
2518 return 0;
2519
2520 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2521 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2522
2523 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2524 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2525 *(log + i), *(log + i + 1),
2526 *(log + i + 2), *(log + i + 3));
2527
2528 kunmap_atomic(log);
2529 }
2530
2531 seq_putc(m, '\n');
2532
2533 return 0;
2534 }
2535
2536 static int i915_edp_psr_status(struct seq_file *m, void *data)
2537 {
2538 struct drm_info_node *node = m->private;
2539 struct drm_device *dev = node->minor->dev;
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2541 u32 psrperf = 0;
2542 u32 stat[3];
2543 enum pipe pipe;
2544 bool enabled = false;
2545
2546 if (!HAS_PSR(dev)) {
2547 seq_puts(m, "PSR not supported\n");
2548 return 0;
2549 }
2550
2551 intel_runtime_pm_get(dev_priv);
2552
2553 mutex_lock(&dev_priv->psr.lock);
2554 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2555 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2556 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2557 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2558 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2559 dev_priv->psr.busy_frontbuffer_bits);
2560 seq_printf(m, "Re-enable work scheduled: %s\n",
2561 yesno(work_busy(&dev_priv->psr.work.work)));
2562
2563 if (HAS_DDI(dev))
2564 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2565 else {
2566 for_each_pipe(dev_priv, pipe) {
2567 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2568 VLV_EDP_PSR_CURR_STATE_MASK;
2569 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2570 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2571 enabled = true;
2572 }
2573 }
2574 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2575
2576 if (!HAS_DDI(dev))
2577 for_each_pipe(dev_priv, pipe) {
2578 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2579 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2580 seq_printf(m, " pipe %c", pipe_name(pipe));
2581 }
2582 seq_puts(m, "\n");
2583
2584 /* CHV PSR has no kind of performance counter */
2585 if (HAS_DDI(dev)) {
2586 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2587 EDP_PSR_PERF_CNT_MASK;
2588
2589 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2590 }
2591 mutex_unlock(&dev_priv->psr.lock);
2592
2593 intel_runtime_pm_put(dev_priv);
2594 return 0;
2595 }
2596
2597 static int i915_sink_crc(struct seq_file *m, void *data)
2598 {
2599 struct drm_info_node *node = m->private;
2600 struct drm_device *dev = node->minor->dev;
2601 struct intel_encoder *encoder;
2602 struct intel_connector *connector;
2603 struct intel_dp *intel_dp = NULL;
2604 int ret;
2605 u8 crc[6];
2606
2607 drm_modeset_lock_all(dev);
2608 for_each_intel_connector(dev, connector) {
2609
2610 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2611 continue;
2612
2613 if (!connector->base.encoder)
2614 continue;
2615
2616 encoder = to_intel_encoder(connector->base.encoder);
2617 if (encoder->type != INTEL_OUTPUT_EDP)
2618 continue;
2619
2620 intel_dp = enc_to_intel_dp(&encoder->base);
2621
2622 ret = intel_dp_sink_crc(intel_dp, crc);
2623 if (ret)
2624 goto out;
2625
2626 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2627 crc[0], crc[1], crc[2],
2628 crc[3], crc[4], crc[5]);
2629 goto out;
2630 }
2631 ret = -ENODEV;
2632 out:
2633 drm_modeset_unlock_all(dev);
2634 return ret;
2635 }
2636
2637 static int i915_energy_uJ(struct seq_file *m, void *data)
2638 {
2639 struct drm_info_node *node = m->private;
2640 struct drm_device *dev = node->minor->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 u64 power;
2643 u32 units;
2644
2645 if (INTEL_INFO(dev)->gen < 6)
2646 return -ENODEV;
2647
2648 intel_runtime_pm_get(dev_priv);
2649
2650 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2651 power = (power & 0x1f00) >> 8;
2652 units = 1000000 / (1 << power); /* convert to uJ */
2653 power = I915_READ(MCH_SECP_NRG_STTS);
2654 power *= units;
2655
2656 intel_runtime_pm_put(dev_priv);
2657
2658 seq_printf(m, "%llu", (long long unsigned)power);
2659
2660 return 0;
2661 }
2662
2663 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2664 {
2665 struct drm_info_node *node = m->private;
2666 struct drm_device *dev = node->minor->dev;
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2668
2669 if (!HAS_RUNTIME_PM(dev)) {
2670 seq_puts(m, "not supported\n");
2671 return 0;
2672 }
2673
2674 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2675 seq_printf(m, "IRQs disabled: %s\n",
2676 yesno(!intel_irqs_enabled(dev_priv)));
2677 #ifdef CONFIG_PM
2678 seq_printf(m, "Usage count: %d\n",
2679 atomic_read(&dev->dev->power.usage_count));
2680 #else
2681 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2682 #endif
2683
2684 return 0;
2685 }
2686
2687 static const char *power_domain_str(enum intel_display_power_domain domain)
2688 {
2689 switch (domain) {
2690 case POWER_DOMAIN_PIPE_A:
2691 return "PIPE_A";
2692 case POWER_DOMAIN_PIPE_B:
2693 return "PIPE_B";
2694 case POWER_DOMAIN_PIPE_C:
2695 return "PIPE_C";
2696 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2697 return "PIPE_A_PANEL_FITTER";
2698 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2699 return "PIPE_B_PANEL_FITTER";
2700 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2701 return "PIPE_C_PANEL_FITTER";
2702 case POWER_DOMAIN_TRANSCODER_A:
2703 return "TRANSCODER_A";
2704 case POWER_DOMAIN_TRANSCODER_B:
2705 return "TRANSCODER_B";
2706 case POWER_DOMAIN_TRANSCODER_C:
2707 return "TRANSCODER_C";
2708 case POWER_DOMAIN_TRANSCODER_EDP:
2709 return "TRANSCODER_EDP";
2710 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2711 return "PORT_DDI_A_2_LANES";
2712 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2713 return "PORT_DDI_A_4_LANES";
2714 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2715 return "PORT_DDI_B_2_LANES";
2716 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2717 return "PORT_DDI_B_4_LANES";
2718 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2719 return "PORT_DDI_C_2_LANES";
2720 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2721 return "PORT_DDI_C_4_LANES";
2722 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2723 return "PORT_DDI_D_2_LANES";
2724 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2725 return "PORT_DDI_D_4_LANES";
2726 case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2727 return "PORT_DDI_E_2_LANES";
2728 case POWER_DOMAIN_PORT_DSI:
2729 return "PORT_DSI";
2730 case POWER_DOMAIN_PORT_CRT:
2731 return "PORT_CRT";
2732 case POWER_DOMAIN_PORT_OTHER:
2733 return "PORT_OTHER";
2734 case POWER_DOMAIN_VGA:
2735 return "VGA";
2736 case POWER_DOMAIN_AUDIO:
2737 return "AUDIO";
2738 case POWER_DOMAIN_PLLS:
2739 return "PLLS";
2740 case POWER_DOMAIN_AUX_A:
2741 return "AUX_A";
2742 case POWER_DOMAIN_AUX_B:
2743 return "AUX_B";
2744 case POWER_DOMAIN_AUX_C:
2745 return "AUX_C";
2746 case POWER_DOMAIN_AUX_D:
2747 return "AUX_D";
2748 case POWER_DOMAIN_INIT:
2749 return "INIT";
2750 default:
2751 MISSING_CASE(domain);
2752 return "?";
2753 }
2754 }
2755
2756 static int i915_power_domain_info(struct seq_file *m, void *unused)
2757 {
2758 struct drm_info_node *node = m->private;
2759 struct drm_device *dev = node->minor->dev;
2760 struct drm_i915_private *dev_priv = dev->dev_private;
2761 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2762 int i;
2763
2764 mutex_lock(&power_domains->lock);
2765
2766 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2767 for (i = 0; i < power_domains->power_well_count; i++) {
2768 struct i915_power_well *power_well;
2769 enum intel_display_power_domain power_domain;
2770
2771 power_well = &power_domains->power_wells[i];
2772 seq_printf(m, "%-25s %d\n", power_well->name,
2773 power_well->count);
2774
2775 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2776 power_domain++) {
2777 if (!(BIT(power_domain) & power_well->domains))
2778 continue;
2779
2780 seq_printf(m, " %-23s %d\n",
2781 power_domain_str(power_domain),
2782 power_domains->domain_use_count[power_domain]);
2783 }
2784 }
2785
2786 mutex_unlock(&power_domains->lock);
2787
2788 return 0;
2789 }
2790
2791 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2792 struct drm_display_mode *mode)
2793 {
2794 int i;
2795
2796 for (i = 0; i < tabs; i++)
2797 seq_putc(m, '\t');
2798
2799 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2800 mode->base.id, mode->name,
2801 mode->vrefresh, mode->clock,
2802 mode->hdisplay, mode->hsync_start,
2803 mode->hsync_end, mode->htotal,
2804 mode->vdisplay, mode->vsync_start,
2805 mode->vsync_end, mode->vtotal,
2806 mode->type, mode->flags);
2807 }
2808
2809 static void intel_encoder_info(struct seq_file *m,
2810 struct intel_crtc *intel_crtc,
2811 struct intel_encoder *intel_encoder)
2812 {
2813 struct drm_info_node *node = m->private;
2814 struct drm_device *dev = node->minor->dev;
2815 struct drm_crtc *crtc = &intel_crtc->base;
2816 struct intel_connector *intel_connector;
2817 struct drm_encoder *encoder;
2818
2819 encoder = &intel_encoder->base;
2820 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2821 encoder->base.id, encoder->name);
2822 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2823 struct drm_connector *connector = &intel_connector->base;
2824 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2825 connector->base.id,
2826 connector->name,
2827 drm_get_connector_status_name(connector->status));
2828 if (connector->status == connector_status_connected) {
2829 struct drm_display_mode *mode = &crtc->mode;
2830 seq_printf(m, ", mode:\n");
2831 intel_seq_print_mode(m, 2, mode);
2832 } else {
2833 seq_putc(m, '\n');
2834 }
2835 }
2836 }
2837
2838 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2839 {
2840 struct drm_info_node *node = m->private;
2841 struct drm_device *dev = node->minor->dev;
2842 struct drm_crtc *crtc = &intel_crtc->base;
2843 struct intel_encoder *intel_encoder;
2844 struct drm_plane_state *plane_state = crtc->primary->state;
2845 struct drm_framebuffer *fb = plane_state->fb;
2846
2847 if (fb)
2848 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2849 fb->base.id, plane_state->src_x >> 16,
2850 plane_state->src_y >> 16, fb->width, fb->height);
2851 else
2852 seq_puts(m, "\tprimary plane disabled\n");
2853 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2854 intel_encoder_info(m, intel_crtc, intel_encoder);
2855 }
2856
2857 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2858 {
2859 struct drm_display_mode *mode = panel->fixed_mode;
2860
2861 seq_printf(m, "\tfixed mode:\n");
2862 intel_seq_print_mode(m, 2, mode);
2863 }
2864
2865 static void intel_dp_info(struct seq_file *m,
2866 struct intel_connector *intel_connector)
2867 {
2868 struct intel_encoder *intel_encoder = intel_connector->encoder;
2869 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2870
2871 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2872 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2873 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2874 intel_panel_info(m, &intel_connector->panel);
2875 }
2876
2877 static void intel_hdmi_info(struct seq_file *m,
2878 struct intel_connector *intel_connector)
2879 {
2880 struct intel_encoder *intel_encoder = intel_connector->encoder;
2881 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2882
2883 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2884 }
2885
2886 static void intel_lvds_info(struct seq_file *m,
2887 struct intel_connector *intel_connector)
2888 {
2889 intel_panel_info(m, &intel_connector->panel);
2890 }
2891
2892 static void intel_connector_info(struct seq_file *m,
2893 struct drm_connector *connector)
2894 {
2895 struct intel_connector *intel_connector = to_intel_connector(connector);
2896 struct intel_encoder *intel_encoder = intel_connector->encoder;
2897 struct drm_display_mode *mode;
2898
2899 seq_printf(m, "connector %d: type %s, status: %s\n",
2900 connector->base.id, connector->name,
2901 drm_get_connector_status_name(connector->status));
2902 if (connector->status == connector_status_connected) {
2903 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2904 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2905 connector->display_info.width_mm,
2906 connector->display_info.height_mm);
2907 seq_printf(m, "\tsubpixel order: %s\n",
2908 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2909 seq_printf(m, "\tCEA rev: %d\n",
2910 connector->display_info.cea_rev);
2911 }
2912 if (intel_encoder) {
2913 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2914 intel_encoder->type == INTEL_OUTPUT_EDP)
2915 intel_dp_info(m, intel_connector);
2916 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2917 intel_hdmi_info(m, intel_connector);
2918 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2919 intel_lvds_info(m, intel_connector);
2920 }
2921
2922 seq_printf(m, "\tmodes:\n");
2923 list_for_each_entry(mode, &connector->modes, head)
2924 intel_seq_print_mode(m, 2, mode);
2925 }
2926
2927 static bool cursor_active(struct drm_device *dev, int pipe)
2928 {
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 u32 state;
2931
2932 if (IS_845G(dev) || IS_I865G(dev))
2933 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2934 else
2935 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2936
2937 return state;
2938 }
2939
2940 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2941 {
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 u32 pos;
2944
2945 pos = I915_READ(CURPOS(pipe));
2946
2947 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2948 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2949 *x = -*x;
2950
2951 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2952 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2953 *y = -*y;
2954
2955 return cursor_active(dev, pipe);
2956 }
2957
2958 static int i915_display_info(struct seq_file *m, void *unused)
2959 {
2960 struct drm_info_node *node = m->private;
2961 struct drm_device *dev = node->minor->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 struct intel_crtc *crtc;
2964 struct drm_connector *connector;
2965
2966 intel_runtime_pm_get(dev_priv);
2967 drm_modeset_lock_all(dev);
2968 seq_printf(m, "CRTC info\n");
2969 seq_printf(m, "---------\n");
2970 for_each_intel_crtc(dev, crtc) {
2971 bool active;
2972 struct intel_crtc_state *pipe_config;
2973 int x, y;
2974
2975 pipe_config = to_intel_crtc_state(crtc->base.state);
2976
2977 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2978 crtc->base.base.id, pipe_name(crtc->pipe),
2979 yesno(pipe_config->base.active),
2980 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2981 if (pipe_config->base.active) {
2982 intel_crtc_info(m, crtc);
2983
2984 active = cursor_position(dev, crtc->pipe, &x, &y);
2985 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2986 yesno(crtc->cursor_base),
2987 x, y, crtc->base.cursor->state->crtc_w,
2988 crtc->base.cursor->state->crtc_h,
2989 crtc->cursor_addr, yesno(active));
2990 }
2991
2992 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2993 yesno(!crtc->cpu_fifo_underrun_disabled),
2994 yesno(!crtc->pch_fifo_underrun_disabled));
2995 }
2996
2997 seq_printf(m, "\n");
2998 seq_printf(m, "Connector info\n");
2999 seq_printf(m, "--------------\n");
3000 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3001 intel_connector_info(m, connector);
3002 }
3003 drm_modeset_unlock_all(dev);
3004 intel_runtime_pm_put(dev_priv);
3005
3006 return 0;
3007 }
3008
3009 static int i915_semaphore_status(struct seq_file *m, void *unused)
3010 {
3011 struct drm_info_node *node = (struct drm_info_node *) m->private;
3012 struct drm_device *dev = node->minor->dev;
3013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 struct intel_engine_cs *ring;
3015 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3016 int i, j, ret;
3017
3018 if (!i915_semaphore_is_enabled(dev)) {
3019 seq_puts(m, "Semaphores are disabled\n");
3020 return 0;
3021 }
3022
3023 ret = mutex_lock_interruptible(&dev->struct_mutex);
3024 if (ret)
3025 return ret;
3026 intel_runtime_pm_get(dev_priv);
3027
3028 if (IS_BROADWELL(dev)) {
3029 struct page *page;
3030 uint64_t *seqno;
3031
3032 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3033
3034 seqno = (uint64_t *)kmap_atomic(page);
3035 for_each_ring(ring, dev_priv, i) {
3036 uint64_t offset;
3037
3038 seq_printf(m, "%s\n", ring->name);
3039
3040 seq_puts(m, " Last signal:");
3041 for (j = 0; j < num_rings; j++) {
3042 offset = i * I915_NUM_RINGS + j;
3043 seq_printf(m, "0x%08llx (0x%02llx) ",
3044 seqno[offset], offset * 8);
3045 }
3046 seq_putc(m, '\n');
3047
3048 seq_puts(m, " Last wait: ");
3049 for (j = 0; j < num_rings; j++) {
3050 offset = i + (j * I915_NUM_RINGS);
3051 seq_printf(m, "0x%08llx (0x%02llx) ",
3052 seqno[offset], offset * 8);
3053 }
3054 seq_putc(m, '\n');
3055
3056 }
3057 kunmap_atomic(seqno);
3058 } else {
3059 seq_puts(m, " Last signal:");
3060 for_each_ring(ring, dev_priv, i)
3061 for (j = 0; j < num_rings; j++)
3062 seq_printf(m, "0x%08x\n",
3063 I915_READ(ring->semaphore.mbox.signal[j]));
3064 seq_putc(m, '\n');
3065 }
3066
3067 seq_puts(m, "\nSync seqno:\n");
3068 for_each_ring(ring, dev_priv, i) {
3069 for (j = 0; j < num_rings; j++) {
3070 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3071 }
3072 seq_putc(m, '\n');
3073 }
3074 seq_putc(m, '\n');
3075
3076 intel_runtime_pm_put(dev_priv);
3077 mutex_unlock(&dev->struct_mutex);
3078 return 0;
3079 }
3080
3081 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3082 {
3083 struct drm_info_node *node = (struct drm_info_node *) m->private;
3084 struct drm_device *dev = node->minor->dev;
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 int i;
3087
3088 drm_modeset_lock_all(dev);
3089 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3090 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3091
3092 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3093 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3094 pll->config.crtc_mask, pll->active, yesno(pll->on));
3095 seq_printf(m, " tracked hardware state:\n");
3096 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3097 seq_printf(m, " dpll_md: 0x%08x\n",
3098 pll->config.hw_state.dpll_md);
3099 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3100 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3101 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3102 }
3103 drm_modeset_unlock_all(dev);
3104
3105 return 0;
3106 }
3107
3108 static int i915_wa_registers(struct seq_file *m, void *unused)
3109 {
3110 int i;
3111 int ret;
3112 struct drm_info_node *node = (struct drm_info_node *) m->private;
3113 struct drm_device *dev = node->minor->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115
3116 ret = mutex_lock_interruptible(&dev->struct_mutex);
3117 if (ret)
3118 return ret;
3119
3120 intel_runtime_pm_get(dev_priv);
3121
3122 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3123 for (i = 0; i < dev_priv->workarounds.count; ++i) {
3124 u32 addr, mask, value, read;
3125 bool ok;
3126
3127 addr = dev_priv->workarounds.reg[i].addr;
3128 mask = dev_priv->workarounds.reg[i].mask;
3129 value = dev_priv->workarounds.reg[i].value;
3130 read = I915_READ(addr);
3131 ok = (value & mask) == (read & mask);
3132 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3133 addr, value, mask, read, ok ? "OK" : "FAIL");
3134 }
3135
3136 intel_runtime_pm_put(dev_priv);
3137 mutex_unlock(&dev->struct_mutex);
3138
3139 return 0;
3140 }
3141
3142 static int i915_ddb_info(struct seq_file *m, void *unused)
3143 {
3144 struct drm_info_node *node = m->private;
3145 struct drm_device *dev = node->minor->dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 struct skl_ddb_allocation *ddb;
3148 struct skl_ddb_entry *entry;
3149 enum pipe pipe;
3150 int plane;
3151
3152 if (INTEL_INFO(dev)->gen < 9)
3153 return 0;
3154
3155 drm_modeset_lock_all(dev);
3156
3157 ddb = &dev_priv->wm.skl_hw.ddb;
3158
3159 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3160
3161 for_each_pipe(dev_priv, pipe) {
3162 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3163
3164 for_each_plane(dev_priv, pipe, plane) {
3165 entry = &ddb->plane[pipe][plane];
3166 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3167 entry->start, entry->end,
3168 skl_ddb_entry_size(entry));
3169 }
3170
3171 entry = &ddb->plane[pipe][PLANE_CURSOR];
3172 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3173 entry->end, skl_ddb_entry_size(entry));
3174 }
3175
3176 drm_modeset_unlock_all(dev);
3177
3178 return 0;
3179 }
3180
3181 static void drrs_status_per_crtc(struct seq_file *m,
3182 struct drm_device *dev, struct intel_crtc *intel_crtc)
3183 {
3184 struct intel_encoder *intel_encoder;
3185 struct drm_i915_private *dev_priv = dev->dev_private;
3186 struct i915_drrs *drrs = &dev_priv->drrs;
3187 int vrefresh = 0;
3188
3189 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3190 /* Encoder connected on this CRTC */
3191 switch (intel_encoder->type) {
3192 case INTEL_OUTPUT_EDP:
3193 seq_puts(m, "eDP:\n");
3194 break;
3195 case INTEL_OUTPUT_DSI:
3196 seq_puts(m, "DSI:\n");
3197 break;
3198 case INTEL_OUTPUT_HDMI:
3199 seq_puts(m, "HDMI:\n");
3200 break;
3201 case INTEL_OUTPUT_DISPLAYPORT:
3202 seq_puts(m, "DP:\n");
3203 break;
3204 default:
3205 seq_printf(m, "Other encoder (id=%d).\n",
3206 intel_encoder->type);
3207 return;
3208 }
3209 }
3210
3211 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3212 seq_puts(m, "\tVBT: DRRS_type: Static");
3213 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3214 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3215 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3216 seq_puts(m, "\tVBT: DRRS_type: None");
3217 else
3218 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3219
3220 seq_puts(m, "\n\n");
3221
3222 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3223 struct intel_panel *panel;
3224
3225 mutex_lock(&drrs->mutex);
3226 /* DRRS Supported */
3227 seq_puts(m, "\tDRRS Supported: Yes\n");
3228
3229 /* disable_drrs() will make drrs->dp NULL */
3230 if (!drrs->dp) {
3231 seq_puts(m, "Idleness DRRS: Disabled");
3232 mutex_unlock(&drrs->mutex);
3233 return;
3234 }
3235
3236 panel = &drrs->dp->attached_connector->panel;
3237 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3238 drrs->busy_frontbuffer_bits);
3239
3240 seq_puts(m, "\n\t\t");
3241 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3242 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3243 vrefresh = panel->fixed_mode->vrefresh;
3244 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3245 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3246 vrefresh = panel->downclock_mode->vrefresh;
3247 } else {
3248 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3249 drrs->refresh_rate_type);
3250 mutex_unlock(&drrs->mutex);
3251 return;
3252 }
3253 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3254
3255 seq_puts(m, "\n\t\t");
3256 mutex_unlock(&drrs->mutex);
3257 } else {
3258 /* DRRS not supported. Print the VBT parameter*/
3259 seq_puts(m, "\tDRRS Supported : No");
3260 }
3261 seq_puts(m, "\n");
3262 }
3263
3264 static int i915_drrs_status(struct seq_file *m, void *unused)
3265 {
3266 struct drm_info_node *node = m->private;
3267 struct drm_device *dev = node->minor->dev;
3268 struct intel_crtc *intel_crtc;
3269 int active_crtc_cnt = 0;
3270
3271 for_each_intel_crtc(dev, intel_crtc) {
3272 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3273
3274 if (intel_crtc->base.state->active) {
3275 active_crtc_cnt++;
3276 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3277
3278 drrs_status_per_crtc(m, dev, intel_crtc);
3279 }
3280
3281 drm_modeset_unlock(&intel_crtc->base.mutex);
3282 }
3283
3284 if (!active_crtc_cnt)
3285 seq_puts(m, "No active crtc found\n");
3286
3287 return 0;
3288 }
3289
3290 struct pipe_crc_info {
3291 const char *name;
3292 struct drm_device *dev;
3293 enum pipe pipe;
3294 };
3295
3296 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3297 {
3298 struct drm_info_node *node = (struct drm_info_node *) m->private;
3299 struct drm_device *dev = node->minor->dev;
3300 struct drm_encoder *encoder;
3301 struct intel_encoder *intel_encoder;
3302 struct intel_digital_port *intel_dig_port;
3303 drm_modeset_lock_all(dev);
3304 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3305 intel_encoder = to_intel_encoder(encoder);
3306 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3307 continue;
3308 intel_dig_port = enc_to_dig_port(encoder);
3309 if (!intel_dig_port->dp.can_mst)
3310 continue;
3311
3312 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3313 }
3314 drm_modeset_unlock_all(dev);
3315 return 0;
3316 }
3317
3318 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3319 {
3320 struct pipe_crc_info *info = inode->i_private;
3321 struct drm_i915_private *dev_priv = info->dev->dev_private;
3322 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3323
3324 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3325 return -ENODEV;
3326
3327 spin_lock_irq(&pipe_crc->lock);
3328
3329 if (pipe_crc->opened) {
3330 spin_unlock_irq(&pipe_crc->lock);
3331 return -EBUSY; /* already open */
3332 }
3333
3334 pipe_crc->opened = true;
3335 filep->private_data = inode->i_private;
3336
3337 spin_unlock_irq(&pipe_crc->lock);
3338
3339 return 0;
3340 }
3341
3342 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3343 {
3344 struct pipe_crc_info *info = inode->i_private;
3345 struct drm_i915_private *dev_priv = info->dev->dev_private;
3346 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3347
3348 spin_lock_irq(&pipe_crc->lock);
3349 pipe_crc->opened = false;
3350 spin_unlock_irq(&pipe_crc->lock);
3351
3352 return 0;
3353 }
3354
3355 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3356 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3357 /* account for \'0' */
3358 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3359
3360 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3361 {
3362 assert_spin_locked(&pipe_crc->lock);
3363 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3364 INTEL_PIPE_CRC_ENTRIES_NR);
3365 }
3366
3367 static ssize_t
3368 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3369 loff_t *pos)
3370 {
3371 struct pipe_crc_info *info = filep->private_data;
3372 struct drm_device *dev = info->dev;
3373 struct drm_i915_private *dev_priv = dev->dev_private;
3374 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3375 char buf[PIPE_CRC_BUFFER_LEN];
3376 int n_entries;
3377 ssize_t bytes_read;
3378
3379 /*
3380 * Don't allow user space to provide buffers not big enough to hold
3381 * a line of data.
3382 */
3383 if (count < PIPE_CRC_LINE_LEN)
3384 return -EINVAL;
3385
3386 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3387 return 0;
3388
3389 /* nothing to read */
3390 spin_lock_irq(&pipe_crc->lock);
3391 while (pipe_crc_data_count(pipe_crc) == 0) {
3392 int ret;
3393
3394 if (filep->f_flags & O_NONBLOCK) {
3395 spin_unlock_irq(&pipe_crc->lock);
3396 return -EAGAIN;
3397 }
3398
3399 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3400 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3401 if (ret) {
3402 spin_unlock_irq(&pipe_crc->lock);
3403 return ret;
3404 }
3405 }
3406
3407 /* We now have one or more entries to read */
3408 n_entries = count / PIPE_CRC_LINE_LEN;
3409
3410 bytes_read = 0;
3411 while (n_entries > 0) {
3412 struct intel_pipe_crc_entry *entry =
3413 &pipe_crc->entries[pipe_crc->tail];
3414 int ret;
3415
3416 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3417 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3418 break;
3419
3420 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3421 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3422
3423 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3424 "%8u %8x %8x %8x %8x %8x\n",
3425 entry->frame, entry->crc[0],
3426 entry->crc[1], entry->crc[2],
3427 entry->crc[3], entry->crc[4]);
3428
3429 spin_unlock_irq(&pipe_crc->lock);
3430
3431 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3432 if (ret == PIPE_CRC_LINE_LEN)
3433 return -EFAULT;
3434
3435 user_buf += PIPE_CRC_LINE_LEN;
3436 n_entries--;
3437
3438 spin_lock_irq(&pipe_crc->lock);
3439 }
3440
3441 spin_unlock_irq(&pipe_crc->lock);
3442
3443 return bytes_read;
3444 }
3445
3446 static const struct file_operations i915_pipe_crc_fops = {
3447 .owner = THIS_MODULE,
3448 .open = i915_pipe_crc_open,
3449 .read = i915_pipe_crc_read,
3450 .release = i915_pipe_crc_release,
3451 };
3452
3453 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3454 {
3455 .name = "i915_pipe_A_crc",
3456 .pipe = PIPE_A,
3457 },
3458 {
3459 .name = "i915_pipe_B_crc",
3460 .pipe = PIPE_B,
3461 },
3462 {
3463 .name = "i915_pipe_C_crc",
3464 .pipe = PIPE_C,
3465 },
3466 };
3467
3468 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3469 enum pipe pipe)
3470 {
3471 struct drm_device *dev = minor->dev;
3472 struct dentry *ent;
3473 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3474
3475 info->dev = dev;
3476 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3477 &i915_pipe_crc_fops);
3478 if (!ent)
3479 return -ENOMEM;
3480
3481 return drm_add_fake_info_node(minor, ent, info);
3482 }
3483
3484 static const char * const pipe_crc_sources[] = {
3485 "none",
3486 "plane1",
3487 "plane2",
3488 "pf",
3489 "pipe",
3490 "TV",
3491 "DP-B",
3492 "DP-C",
3493 "DP-D",
3494 "auto",
3495 };
3496
3497 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3498 {
3499 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3500 return pipe_crc_sources[source];
3501 }
3502
3503 static int display_crc_ctl_show(struct seq_file *m, void *data)
3504 {
3505 struct drm_device *dev = m->private;
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 int i;
3508
3509 for (i = 0; i < I915_MAX_PIPES; i++)
3510 seq_printf(m, "%c %s\n", pipe_name(i),
3511 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3512
3513 return 0;
3514 }
3515
3516 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3517 {
3518 struct drm_device *dev = inode->i_private;
3519
3520 return single_open(file, display_crc_ctl_show, dev);
3521 }
3522
3523 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3524 uint32_t *val)
3525 {
3526 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3527 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3528
3529 switch (*source) {
3530 case INTEL_PIPE_CRC_SOURCE_PIPE:
3531 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3532 break;
3533 case INTEL_PIPE_CRC_SOURCE_NONE:
3534 *val = 0;
3535 break;
3536 default:
3537 return -EINVAL;
3538 }
3539
3540 return 0;
3541 }
3542
3543 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3544 enum intel_pipe_crc_source *source)
3545 {
3546 struct intel_encoder *encoder;
3547 struct intel_crtc *crtc;
3548 struct intel_digital_port *dig_port;
3549 int ret = 0;
3550
3551 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3552
3553 drm_modeset_lock_all(dev);
3554 for_each_intel_encoder(dev, encoder) {
3555 if (!encoder->base.crtc)
3556 continue;
3557
3558 crtc = to_intel_crtc(encoder->base.crtc);
3559
3560 if (crtc->pipe != pipe)
3561 continue;
3562
3563 switch (encoder->type) {
3564 case INTEL_OUTPUT_TVOUT:
3565 *source = INTEL_PIPE_CRC_SOURCE_TV;
3566 break;
3567 case INTEL_OUTPUT_DISPLAYPORT:
3568 case INTEL_OUTPUT_EDP:
3569 dig_port = enc_to_dig_port(&encoder->base);
3570 switch (dig_port->port) {
3571 case PORT_B:
3572 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3573 break;
3574 case PORT_C:
3575 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3576 break;
3577 case PORT_D:
3578 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3579 break;
3580 default:
3581 WARN(1, "nonexisting DP port %c\n",
3582 port_name(dig_port->port));
3583 break;
3584 }
3585 break;
3586 default:
3587 break;
3588 }
3589 }
3590 drm_modeset_unlock_all(dev);
3591
3592 return ret;
3593 }
3594
3595 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3596 enum pipe pipe,
3597 enum intel_pipe_crc_source *source,
3598 uint32_t *val)
3599 {
3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601 bool need_stable_symbols = false;
3602
3603 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3604 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3605 if (ret)
3606 return ret;
3607 }
3608
3609 switch (*source) {
3610 case INTEL_PIPE_CRC_SOURCE_PIPE:
3611 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3612 break;
3613 case INTEL_PIPE_CRC_SOURCE_DP_B:
3614 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3615 need_stable_symbols = true;
3616 break;
3617 case INTEL_PIPE_CRC_SOURCE_DP_C:
3618 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3619 need_stable_symbols = true;
3620 break;
3621 case INTEL_PIPE_CRC_SOURCE_DP_D:
3622 if (!IS_CHERRYVIEW(dev))
3623 return -EINVAL;
3624 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3625 need_stable_symbols = true;
3626 break;
3627 case INTEL_PIPE_CRC_SOURCE_NONE:
3628 *val = 0;
3629 break;
3630 default:
3631 return -EINVAL;
3632 }
3633
3634 /*
3635 * When the pipe CRC tap point is after the transcoders we need
3636 * to tweak symbol-level features to produce a deterministic series of
3637 * symbols for a given frame. We need to reset those features only once
3638 * a frame (instead of every nth symbol):
3639 * - DC-balance: used to ensure a better clock recovery from the data
3640 * link (SDVO)
3641 * - DisplayPort scrambling: used for EMI reduction
3642 */
3643 if (need_stable_symbols) {
3644 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3645
3646 tmp |= DC_BALANCE_RESET_VLV;
3647 switch (pipe) {
3648 case PIPE_A:
3649 tmp |= PIPE_A_SCRAMBLE_RESET;
3650 break;
3651 case PIPE_B:
3652 tmp |= PIPE_B_SCRAMBLE_RESET;
3653 break;
3654 case PIPE_C:
3655 tmp |= PIPE_C_SCRAMBLE_RESET;
3656 break;
3657 default:
3658 return -EINVAL;
3659 }
3660 I915_WRITE(PORT_DFT2_G4X, tmp);
3661 }
3662
3663 return 0;
3664 }
3665
3666 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3667 enum pipe pipe,
3668 enum intel_pipe_crc_source *source,
3669 uint32_t *val)
3670 {
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 bool need_stable_symbols = false;
3673
3674 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3675 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3676 if (ret)
3677 return ret;
3678 }
3679
3680 switch (*source) {
3681 case INTEL_PIPE_CRC_SOURCE_PIPE:
3682 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3683 break;
3684 case INTEL_PIPE_CRC_SOURCE_TV:
3685 if (!SUPPORTS_TV(dev))
3686 return -EINVAL;
3687 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3688 break;
3689 case INTEL_PIPE_CRC_SOURCE_DP_B:
3690 if (!IS_G4X(dev))
3691 return -EINVAL;
3692 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3693 need_stable_symbols = true;
3694 break;
3695 case INTEL_PIPE_CRC_SOURCE_DP_C:
3696 if (!IS_G4X(dev))
3697 return -EINVAL;
3698 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3699 need_stable_symbols = true;
3700 break;
3701 case INTEL_PIPE_CRC_SOURCE_DP_D:
3702 if (!IS_G4X(dev))
3703 return -EINVAL;
3704 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3705 need_stable_symbols = true;
3706 break;
3707 case INTEL_PIPE_CRC_SOURCE_NONE:
3708 *val = 0;
3709 break;
3710 default:
3711 return -EINVAL;
3712 }
3713
3714 /*
3715 * When the pipe CRC tap point is after the transcoders we need
3716 * to tweak symbol-level features to produce a deterministic series of
3717 * symbols for a given frame. We need to reset those features only once
3718 * a frame (instead of every nth symbol):
3719 * - DC-balance: used to ensure a better clock recovery from the data
3720 * link (SDVO)
3721 * - DisplayPort scrambling: used for EMI reduction
3722 */
3723 if (need_stable_symbols) {
3724 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3725
3726 WARN_ON(!IS_G4X(dev));
3727
3728 I915_WRITE(PORT_DFT_I9XX,
3729 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3730
3731 if (pipe == PIPE_A)
3732 tmp |= PIPE_A_SCRAMBLE_RESET;
3733 else
3734 tmp |= PIPE_B_SCRAMBLE_RESET;
3735
3736 I915_WRITE(PORT_DFT2_G4X, tmp);
3737 }
3738
3739 return 0;
3740 }
3741
3742 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3743 enum pipe pipe)
3744 {
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3747
3748 switch (pipe) {
3749 case PIPE_A:
3750 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3751 break;
3752 case PIPE_B:
3753 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3754 break;
3755 case PIPE_C:
3756 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3757 break;
3758 default:
3759 return;
3760 }
3761 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3762 tmp &= ~DC_BALANCE_RESET_VLV;
3763 I915_WRITE(PORT_DFT2_G4X, tmp);
3764
3765 }
3766
3767 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3768 enum pipe pipe)
3769 {
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3772
3773 if (pipe == PIPE_A)
3774 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3775 else
3776 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3777 I915_WRITE(PORT_DFT2_G4X, tmp);
3778
3779 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3780 I915_WRITE(PORT_DFT_I9XX,
3781 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3782 }
3783 }
3784
3785 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3786 uint32_t *val)
3787 {
3788 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3789 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3790
3791 switch (*source) {
3792 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3793 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3794 break;
3795 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3796 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3797 break;
3798 case INTEL_PIPE_CRC_SOURCE_PIPE:
3799 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3800 break;
3801 case INTEL_PIPE_CRC_SOURCE_NONE:
3802 *val = 0;
3803 break;
3804 default:
3805 return -EINVAL;
3806 }
3807
3808 return 0;
3809 }
3810
3811 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3812 {
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct intel_crtc *crtc =
3815 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3816 struct intel_crtc_state *pipe_config;
3817 struct drm_atomic_state *state;
3818 int ret = 0;
3819
3820 drm_modeset_lock_all(dev);
3821 state = drm_atomic_state_alloc(dev);
3822 if (!state) {
3823 ret = -ENOMEM;
3824 goto out;
3825 }
3826
3827 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3828 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3829 if (IS_ERR(pipe_config)) {
3830 ret = PTR_ERR(pipe_config);
3831 goto out;
3832 }
3833
3834 pipe_config->pch_pfit.force_thru = enable;
3835 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3836 pipe_config->pch_pfit.enabled != enable)
3837 pipe_config->base.connectors_changed = true;
3838
3839 ret = drm_atomic_commit(state);
3840 out:
3841 drm_modeset_unlock_all(dev);
3842 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3843 if (ret)
3844 drm_atomic_state_free(state);
3845 }
3846
3847 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3848 enum pipe pipe,
3849 enum intel_pipe_crc_source *source,
3850 uint32_t *val)
3851 {
3852 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3853 *source = INTEL_PIPE_CRC_SOURCE_PF;
3854
3855 switch (*source) {
3856 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3857 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3858 break;
3859 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3860 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3861 break;
3862 case INTEL_PIPE_CRC_SOURCE_PF:
3863 if (IS_HASWELL(dev) && pipe == PIPE_A)
3864 hsw_trans_edp_pipe_A_crc_wa(dev, true);
3865
3866 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3867 break;
3868 case INTEL_PIPE_CRC_SOURCE_NONE:
3869 *val = 0;
3870 break;
3871 default:
3872 return -EINVAL;
3873 }
3874
3875 return 0;
3876 }
3877
3878 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3879 enum intel_pipe_crc_source source)
3880 {
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3883 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3884 pipe));
3885 u32 val = 0; /* shut up gcc */
3886 int ret;
3887
3888 if (pipe_crc->source == source)
3889 return 0;
3890
3891 /* forbid changing the source without going back to 'none' */
3892 if (pipe_crc->source && source)
3893 return -EINVAL;
3894
3895 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3896 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3897 return -EIO;
3898 }
3899
3900 if (IS_GEN2(dev))
3901 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3902 else if (INTEL_INFO(dev)->gen < 5)
3903 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3904 else if (IS_VALLEYVIEW(dev))
3905 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3906 else if (IS_GEN5(dev) || IS_GEN6(dev))
3907 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3908 else
3909 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3910
3911 if (ret != 0)
3912 return ret;
3913
3914 /* none -> real source transition */
3915 if (source) {
3916 struct intel_pipe_crc_entry *entries;
3917
3918 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3919 pipe_name(pipe), pipe_crc_source_name(source));
3920
3921 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3922 sizeof(pipe_crc->entries[0]),
3923 GFP_KERNEL);
3924 if (!entries)
3925 return -ENOMEM;
3926
3927 /*
3928 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3929 * enabled and disabled dynamically based on package C states,
3930 * user space can't make reliable use of the CRCs, so let's just
3931 * completely disable it.
3932 */
3933 hsw_disable_ips(crtc);
3934
3935 spin_lock_irq(&pipe_crc->lock);
3936 kfree(pipe_crc->entries);
3937 pipe_crc->entries = entries;
3938 pipe_crc->head = 0;
3939 pipe_crc->tail = 0;
3940 spin_unlock_irq(&pipe_crc->lock);
3941 }
3942
3943 pipe_crc->source = source;
3944
3945 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3946 POSTING_READ(PIPE_CRC_CTL(pipe));
3947
3948 /* real source -> none transition */
3949 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3950 struct intel_pipe_crc_entry *entries;
3951 struct intel_crtc *crtc =
3952 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3953
3954 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3955 pipe_name(pipe));
3956
3957 drm_modeset_lock(&crtc->base.mutex, NULL);
3958 if (crtc->base.state->active)
3959 intel_wait_for_vblank(dev, pipe);
3960 drm_modeset_unlock(&crtc->base.mutex);
3961
3962 spin_lock_irq(&pipe_crc->lock);
3963 entries = pipe_crc->entries;
3964 pipe_crc->entries = NULL;
3965 pipe_crc->head = 0;
3966 pipe_crc->tail = 0;
3967 spin_unlock_irq(&pipe_crc->lock);
3968
3969 kfree(entries);
3970
3971 if (IS_G4X(dev))
3972 g4x_undo_pipe_scramble_reset(dev, pipe);
3973 else if (IS_VALLEYVIEW(dev))
3974 vlv_undo_pipe_scramble_reset(dev, pipe);
3975 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3976 hsw_trans_edp_pipe_A_crc_wa(dev, false);
3977
3978 hsw_enable_ips(crtc);
3979 }
3980
3981 return 0;
3982 }
3983
3984 /*
3985 * Parse pipe CRC command strings:
3986 * command: wsp* object wsp+ name wsp+ source wsp*
3987 * object: 'pipe'
3988 * name: (A | B | C)
3989 * source: (none | plane1 | plane2 | pf)
3990 * wsp: (#0x20 | #0x9 | #0xA)+
3991 *
3992 * eg.:
3993 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3994 * "pipe A none" -> Stop CRC
3995 */
3996 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3997 {
3998 int n_words = 0;
3999
4000 while (*buf) {
4001 char *end;
4002
4003 /* skip leading white space */
4004 buf = skip_spaces(buf);
4005 if (!*buf)
4006 break; /* end of buffer */
4007
4008 /* find end of word */
4009 for (end = buf; *end && !isspace(*end); end++)
4010 ;
4011
4012 if (n_words == max_words) {
4013 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4014 max_words);
4015 return -EINVAL; /* ran out of words[] before bytes */
4016 }
4017
4018 if (*end)
4019 *end++ = '\0';
4020 words[n_words++] = buf;
4021 buf = end;
4022 }
4023
4024 return n_words;
4025 }
4026
4027 enum intel_pipe_crc_object {
4028 PIPE_CRC_OBJECT_PIPE,
4029 };
4030
4031 static const char * const pipe_crc_objects[] = {
4032 "pipe",
4033 };
4034
4035 static int
4036 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4037 {
4038 int i;
4039
4040 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4041 if (!strcmp(buf, pipe_crc_objects[i])) {
4042 *o = i;
4043 return 0;
4044 }
4045
4046 return -EINVAL;
4047 }
4048
4049 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4050 {
4051 const char name = buf[0];
4052
4053 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4054 return -EINVAL;
4055
4056 *pipe = name - 'A';
4057
4058 return 0;
4059 }
4060
4061 static int
4062 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4063 {
4064 int i;
4065
4066 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4067 if (!strcmp(buf, pipe_crc_sources[i])) {
4068 *s = i;
4069 return 0;
4070 }
4071
4072 return -EINVAL;
4073 }
4074
4075 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4076 {
4077 #define N_WORDS 3
4078 int n_words;
4079 char *words[N_WORDS];
4080 enum pipe pipe;
4081 enum intel_pipe_crc_object object;
4082 enum intel_pipe_crc_source source;
4083
4084 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4085 if (n_words != N_WORDS) {
4086 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4087 N_WORDS);
4088 return -EINVAL;
4089 }
4090
4091 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4092 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4093 return -EINVAL;
4094 }
4095
4096 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4097 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4098 return -EINVAL;
4099 }
4100
4101 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4102 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4103 return -EINVAL;
4104 }
4105
4106 return pipe_crc_set_source(dev, pipe, source);
4107 }
4108
4109 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4110 size_t len, loff_t *offp)
4111 {
4112 struct seq_file *m = file->private_data;
4113 struct drm_device *dev = m->private;
4114 char *tmpbuf;
4115 int ret;
4116
4117 if (len == 0)
4118 return 0;
4119
4120 if (len > PAGE_SIZE - 1) {
4121 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4122 PAGE_SIZE);
4123 return -E2BIG;
4124 }
4125
4126 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4127 if (!tmpbuf)
4128 return -ENOMEM;
4129
4130 if (copy_from_user(tmpbuf, ubuf, len)) {
4131 ret = -EFAULT;
4132 goto out;
4133 }
4134 tmpbuf[len] = '\0';
4135
4136 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4137
4138 out:
4139 kfree(tmpbuf);
4140 if (ret < 0)
4141 return ret;
4142
4143 *offp += len;
4144 return len;
4145 }
4146
4147 static const struct file_operations i915_display_crc_ctl_fops = {
4148 .owner = THIS_MODULE,
4149 .open = display_crc_ctl_open,
4150 .read = seq_read,
4151 .llseek = seq_lseek,
4152 .release = single_release,
4153 .write = display_crc_ctl_write
4154 };
4155
4156 static ssize_t i915_displayport_test_active_write(struct file *file,
4157 const char __user *ubuf,
4158 size_t len, loff_t *offp)
4159 {
4160 char *input_buffer;
4161 int status = 0;
4162 struct drm_device *dev;
4163 struct drm_connector *connector;
4164 struct list_head *connector_list;
4165 struct intel_dp *intel_dp;
4166 int val = 0;
4167
4168 dev = ((struct seq_file *)file->private_data)->private;
4169
4170 connector_list = &dev->mode_config.connector_list;
4171
4172 if (len == 0)
4173 return 0;
4174
4175 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4176 if (!input_buffer)
4177 return -ENOMEM;
4178
4179 if (copy_from_user(input_buffer, ubuf, len)) {
4180 status = -EFAULT;
4181 goto out;
4182 }
4183
4184 input_buffer[len] = '\0';
4185 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4186
4187 list_for_each_entry(connector, connector_list, head) {
4188
4189 if (connector->connector_type !=
4190 DRM_MODE_CONNECTOR_DisplayPort)
4191 continue;
4192
4193 if (connector->status == connector_status_connected &&
4194 connector->encoder != NULL) {
4195 intel_dp = enc_to_intel_dp(connector->encoder);
4196 status = kstrtoint(input_buffer, 10, &val);
4197 if (status < 0)
4198 goto out;
4199 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4200 /* To prevent erroneous activation of the compliance
4201 * testing code, only accept an actual value of 1 here
4202 */
4203 if (val == 1)
4204 intel_dp->compliance_test_active = 1;
4205 else
4206 intel_dp->compliance_test_active = 0;
4207 }
4208 }
4209 out:
4210 kfree(input_buffer);
4211 if (status < 0)
4212 return status;
4213
4214 *offp += len;
4215 return len;
4216 }
4217
4218 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4219 {
4220 struct drm_device *dev = m->private;
4221 struct drm_connector *connector;
4222 struct list_head *connector_list = &dev->mode_config.connector_list;
4223 struct intel_dp *intel_dp;
4224
4225 list_for_each_entry(connector, connector_list, head) {
4226
4227 if (connector->connector_type !=
4228 DRM_MODE_CONNECTOR_DisplayPort)
4229 continue;
4230
4231 if (connector->status == connector_status_connected &&
4232 connector->encoder != NULL) {
4233 intel_dp = enc_to_intel_dp(connector->encoder);
4234 if (intel_dp->compliance_test_active)
4235 seq_puts(m, "1");
4236 else
4237 seq_puts(m, "0");
4238 } else
4239 seq_puts(m, "0");
4240 }
4241
4242 return 0;
4243 }
4244
4245 static int i915_displayport_test_active_open(struct inode *inode,
4246 struct file *file)
4247 {
4248 struct drm_device *dev = inode->i_private;
4249
4250 return single_open(file, i915_displayport_test_active_show, dev);
4251 }
4252
4253 static const struct file_operations i915_displayport_test_active_fops = {
4254 .owner = THIS_MODULE,
4255 .open = i915_displayport_test_active_open,
4256 .read = seq_read,
4257 .llseek = seq_lseek,
4258 .release = single_release,
4259 .write = i915_displayport_test_active_write
4260 };
4261
4262 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4263 {
4264 struct drm_device *dev = m->private;
4265 struct drm_connector *connector;
4266 struct list_head *connector_list = &dev->mode_config.connector_list;
4267 struct intel_dp *intel_dp;
4268
4269 list_for_each_entry(connector, connector_list, head) {
4270
4271 if (connector->connector_type !=
4272 DRM_MODE_CONNECTOR_DisplayPort)
4273 continue;
4274
4275 if (connector->status == connector_status_connected &&
4276 connector->encoder != NULL) {
4277 intel_dp = enc_to_intel_dp(connector->encoder);
4278 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4279 } else
4280 seq_puts(m, "0");
4281 }
4282
4283 return 0;
4284 }
4285 static int i915_displayport_test_data_open(struct inode *inode,
4286 struct file *file)
4287 {
4288 struct drm_device *dev = inode->i_private;
4289
4290 return single_open(file, i915_displayport_test_data_show, dev);
4291 }
4292
4293 static const struct file_operations i915_displayport_test_data_fops = {
4294 .owner = THIS_MODULE,
4295 .open = i915_displayport_test_data_open,
4296 .read = seq_read,
4297 .llseek = seq_lseek,
4298 .release = single_release
4299 };
4300
4301 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4302 {
4303 struct drm_device *dev = m->private;
4304 struct drm_connector *connector;
4305 struct list_head *connector_list = &dev->mode_config.connector_list;
4306 struct intel_dp *intel_dp;
4307
4308 list_for_each_entry(connector, connector_list, head) {
4309
4310 if (connector->connector_type !=
4311 DRM_MODE_CONNECTOR_DisplayPort)
4312 continue;
4313
4314 if (connector->status == connector_status_connected &&
4315 connector->encoder != NULL) {
4316 intel_dp = enc_to_intel_dp(connector->encoder);
4317 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4318 } else
4319 seq_puts(m, "0");
4320 }
4321
4322 return 0;
4323 }
4324
4325 static int i915_displayport_test_type_open(struct inode *inode,
4326 struct file *file)
4327 {
4328 struct drm_device *dev = inode->i_private;
4329
4330 return single_open(file, i915_displayport_test_type_show, dev);
4331 }
4332
4333 static const struct file_operations i915_displayport_test_type_fops = {
4334 .owner = THIS_MODULE,
4335 .open = i915_displayport_test_type_open,
4336 .read = seq_read,
4337 .llseek = seq_lseek,
4338 .release = single_release
4339 };
4340
4341 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4342 {
4343 struct drm_device *dev = m->private;
4344 int level;
4345 int num_levels;
4346
4347 if (IS_CHERRYVIEW(dev))
4348 num_levels = 3;
4349 else if (IS_VALLEYVIEW(dev))
4350 num_levels = 1;
4351 else
4352 num_levels = ilk_wm_max_level(dev) + 1;
4353
4354 drm_modeset_lock_all(dev);
4355
4356 for (level = 0; level < num_levels; level++) {
4357 unsigned int latency = wm[level];
4358
4359 /*
4360 * - WM1+ latency values in 0.5us units
4361 * - latencies are in us on gen9/vlv/chv
4362 */
4363 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4364 latency *= 10;
4365 else if (level > 0)
4366 latency *= 5;
4367
4368 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4369 level, wm[level], latency / 10, latency % 10);
4370 }
4371
4372 drm_modeset_unlock_all(dev);
4373 }
4374
4375 static int pri_wm_latency_show(struct seq_file *m, void *data)
4376 {
4377 struct drm_device *dev = m->private;
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379 const uint16_t *latencies;
4380
4381 if (INTEL_INFO(dev)->gen >= 9)
4382 latencies = dev_priv->wm.skl_latency;
4383 else
4384 latencies = to_i915(dev)->wm.pri_latency;
4385
4386 wm_latency_show(m, latencies);
4387
4388 return 0;
4389 }
4390
4391 static int spr_wm_latency_show(struct seq_file *m, void *data)
4392 {
4393 struct drm_device *dev = m->private;
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395 const uint16_t *latencies;
4396
4397 if (INTEL_INFO(dev)->gen >= 9)
4398 latencies = dev_priv->wm.skl_latency;
4399 else
4400 latencies = to_i915(dev)->wm.spr_latency;
4401
4402 wm_latency_show(m, latencies);
4403
4404 return 0;
4405 }
4406
4407 static int cur_wm_latency_show(struct seq_file *m, void *data)
4408 {
4409 struct drm_device *dev = m->private;
4410 struct drm_i915_private *dev_priv = dev->dev_private;
4411 const uint16_t *latencies;
4412
4413 if (INTEL_INFO(dev)->gen >= 9)
4414 latencies = dev_priv->wm.skl_latency;
4415 else
4416 latencies = to_i915(dev)->wm.cur_latency;
4417
4418 wm_latency_show(m, latencies);
4419
4420 return 0;
4421 }
4422
4423 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4424 {
4425 struct drm_device *dev = inode->i_private;
4426
4427 if (INTEL_INFO(dev)->gen < 5)
4428 return -ENODEV;
4429
4430 return single_open(file, pri_wm_latency_show, dev);
4431 }
4432
4433 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4434 {
4435 struct drm_device *dev = inode->i_private;
4436
4437 if (HAS_GMCH_DISPLAY(dev))
4438 return -ENODEV;
4439
4440 return single_open(file, spr_wm_latency_show, dev);
4441 }
4442
4443 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4444 {
4445 struct drm_device *dev = inode->i_private;
4446
4447 if (HAS_GMCH_DISPLAY(dev))
4448 return -ENODEV;
4449
4450 return single_open(file, cur_wm_latency_show, dev);
4451 }
4452
4453 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4454 size_t len, loff_t *offp, uint16_t wm[8])
4455 {
4456 struct seq_file *m = file->private_data;
4457 struct drm_device *dev = m->private;
4458 uint16_t new[8] = { 0 };
4459 int num_levels;
4460 int level;
4461 int ret;
4462 char tmp[32];
4463
4464 if (IS_CHERRYVIEW(dev))
4465 num_levels = 3;
4466 else if (IS_VALLEYVIEW(dev))
4467 num_levels = 1;
4468 else
4469 num_levels = ilk_wm_max_level(dev) + 1;
4470
4471 if (len >= sizeof(tmp))
4472 return -EINVAL;
4473
4474 if (copy_from_user(tmp, ubuf, len))
4475 return -EFAULT;
4476
4477 tmp[len] = '\0';
4478
4479 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4480 &new[0], &new[1], &new[2], &new[3],
4481 &new[4], &new[5], &new[6], &new[7]);
4482 if (ret != num_levels)
4483 return -EINVAL;
4484
4485 drm_modeset_lock_all(dev);
4486
4487 for (level = 0; level < num_levels; level++)
4488 wm[level] = new[level];
4489
4490 drm_modeset_unlock_all(dev);
4491
4492 return len;
4493 }
4494
4495
4496 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4497 size_t len, loff_t *offp)
4498 {
4499 struct seq_file *m = file->private_data;
4500 struct drm_device *dev = m->private;
4501 struct drm_i915_private *dev_priv = dev->dev_private;
4502 uint16_t *latencies;
4503
4504 if (INTEL_INFO(dev)->gen >= 9)
4505 latencies = dev_priv->wm.skl_latency;
4506 else
4507 latencies = to_i915(dev)->wm.pri_latency;
4508
4509 return wm_latency_write(file, ubuf, len, offp, latencies);
4510 }
4511
4512 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4513 size_t len, loff_t *offp)
4514 {
4515 struct seq_file *m = file->private_data;
4516 struct drm_device *dev = m->private;
4517 struct drm_i915_private *dev_priv = dev->dev_private;
4518 uint16_t *latencies;
4519
4520 if (INTEL_INFO(dev)->gen >= 9)
4521 latencies = dev_priv->wm.skl_latency;
4522 else
4523 latencies = to_i915(dev)->wm.spr_latency;
4524
4525 return wm_latency_write(file, ubuf, len, offp, latencies);
4526 }
4527
4528 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4529 size_t len, loff_t *offp)
4530 {
4531 struct seq_file *m = file->private_data;
4532 struct drm_device *dev = m->private;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 uint16_t *latencies;
4535
4536 if (INTEL_INFO(dev)->gen >= 9)
4537 latencies = dev_priv->wm.skl_latency;
4538 else
4539 latencies = to_i915(dev)->wm.cur_latency;
4540
4541 return wm_latency_write(file, ubuf, len, offp, latencies);
4542 }
4543
4544 static const struct file_operations i915_pri_wm_latency_fops = {
4545 .owner = THIS_MODULE,
4546 .open = pri_wm_latency_open,
4547 .read = seq_read,
4548 .llseek = seq_lseek,
4549 .release = single_release,
4550 .write = pri_wm_latency_write
4551 };
4552
4553 static const struct file_operations i915_spr_wm_latency_fops = {
4554 .owner = THIS_MODULE,
4555 .open = spr_wm_latency_open,
4556 .read = seq_read,
4557 .llseek = seq_lseek,
4558 .release = single_release,
4559 .write = spr_wm_latency_write
4560 };
4561
4562 static const struct file_operations i915_cur_wm_latency_fops = {
4563 .owner = THIS_MODULE,
4564 .open = cur_wm_latency_open,
4565 .read = seq_read,
4566 .llseek = seq_lseek,
4567 .release = single_release,
4568 .write = cur_wm_latency_write
4569 };
4570
4571 static int
4572 i915_wedged_get(void *data, u64 *val)
4573 {
4574 struct drm_device *dev = data;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576
4577 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4578
4579 return 0;
4580 }
4581
4582 static int
4583 i915_wedged_set(void *data, u64 val)
4584 {
4585 struct drm_device *dev = data;
4586 struct drm_i915_private *dev_priv = dev->dev_private;
4587
4588 /*
4589 * There is no safeguard against this debugfs entry colliding
4590 * with the hangcheck calling same i915_handle_error() in
4591 * parallel, causing an explosion. For now we assume that the
4592 * test harness is responsible enough not to inject gpu hangs
4593 * while it is writing to 'i915_wedged'
4594 */
4595
4596 if (i915_reset_in_progress(&dev_priv->gpu_error))
4597 return -EAGAIN;
4598
4599 intel_runtime_pm_get(dev_priv);
4600
4601 i915_handle_error(dev, val,
4602 "Manually setting wedged to %llu", val);
4603
4604 intel_runtime_pm_put(dev_priv);
4605
4606 return 0;
4607 }
4608
4609 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4610 i915_wedged_get, i915_wedged_set,
4611 "%llu\n");
4612
4613 static int
4614 i915_ring_stop_get(void *data, u64 *val)
4615 {
4616 struct drm_device *dev = data;
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618
4619 *val = dev_priv->gpu_error.stop_rings;
4620
4621 return 0;
4622 }
4623
4624 static int
4625 i915_ring_stop_set(void *data, u64 val)
4626 {
4627 struct drm_device *dev = data;
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629 int ret;
4630
4631 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4632
4633 ret = mutex_lock_interruptible(&dev->struct_mutex);
4634 if (ret)
4635 return ret;
4636
4637 dev_priv->gpu_error.stop_rings = val;
4638 mutex_unlock(&dev->struct_mutex);
4639
4640 return 0;
4641 }
4642
4643 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4644 i915_ring_stop_get, i915_ring_stop_set,
4645 "0x%08llx\n");
4646
4647 static int
4648 i915_ring_missed_irq_get(void *data, u64 *val)
4649 {
4650 struct drm_device *dev = data;
4651 struct drm_i915_private *dev_priv = dev->dev_private;
4652
4653 *val = dev_priv->gpu_error.missed_irq_rings;
4654 return 0;
4655 }
4656
4657 static int
4658 i915_ring_missed_irq_set(void *data, u64 val)
4659 {
4660 struct drm_device *dev = data;
4661 struct drm_i915_private *dev_priv = dev->dev_private;
4662 int ret;
4663
4664 /* Lock against concurrent debugfs callers */
4665 ret = mutex_lock_interruptible(&dev->struct_mutex);
4666 if (ret)
4667 return ret;
4668 dev_priv->gpu_error.missed_irq_rings = val;
4669 mutex_unlock(&dev->struct_mutex);
4670
4671 return 0;
4672 }
4673
4674 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4675 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4676 "0x%08llx\n");
4677
4678 static int
4679 i915_ring_test_irq_get(void *data, u64 *val)
4680 {
4681 struct drm_device *dev = data;
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4683
4684 *val = dev_priv->gpu_error.test_irq_rings;
4685
4686 return 0;
4687 }
4688
4689 static int
4690 i915_ring_test_irq_set(void *data, u64 val)
4691 {
4692 struct drm_device *dev = data;
4693 struct drm_i915_private *dev_priv = dev->dev_private;
4694 int ret;
4695
4696 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4697
4698 /* Lock against concurrent debugfs callers */
4699 ret = mutex_lock_interruptible(&dev->struct_mutex);
4700 if (ret)
4701 return ret;
4702
4703 dev_priv->gpu_error.test_irq_rings = val;
4704 mutex_unlock(&dev->struct_mutex);
4705
4706 return 0;
4707 }
4708
4709 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4710 i915_ring_test_irq_get, i915_ring_test_irq_set,
4711 "0x%08llx\n");
4712
4713 #define DROP_UNBOUND 0x1
4714 #define DROP_BOUND 0x2
4715 #define DROP_RETIRE 0x4
4716 #define DROP_ACTIVE 0x8
4717 #define DROP_ALL (DROP_UNBOUND | \
4718 DROP_BOUND | \
4719 DROP_RETIRE | \
4720 DROP_ACTIVE)
4721 static int
4722 i915_drop_caches_get(void *data, u64 *val)
4723 {
4724 *val = DROP_ALL;
4725
4726 return 0;
4727 }
4728
4729 static int
4730 i915_drop_caches_set(void *data, u64 val)
4731 {
4732 struct drm_device *dev = data;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 int ret;
4735
4736 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4737
4738 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4739 * on ioctls on -EAGAIN. */
4740 ret = mutex_lock_interruptible(&dev->struct_mutex);
4741 if (ret)
4742 return ret;
4743
4744 if (val & DROP_ACTIVE) {
4745 ret = i915_gpu_idle(dev);
4746 if (ret)
4747 goto unlock;
4748 }
4749
4750 if (val & (DROP_RETIRE | DROP_ACTIVE))
4751 i915_gem_retire_requests(dev);
4752
4753 if (val & DROP_BOUND)
4754 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4755
4756 if (val & DROP_UNBOUND)
4757 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4758
4759 unlock:
4760 mutex_unlock(&dev->struct_mutex);
4761
4762 return ret;
4763 }
4764
4765 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4766 i915_drop_caches_get, i915_drop_caches_set,
4767 "0x%08llx\n");
4768
4769 static int
4770 i915_max_freq_get(void *data, u64 *val)
4771 {
4772 struct drm_device *dev = data;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 int ret;
4775
4776 if (INTEL_INFO(dev)->gen < 6)
4777 return -ENODEV;
4778
4779 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4780
4781 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4782 if (ret)
4783 return ret;
4784
4785 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4786 mutex_unlock(&dev_priv->rps.hw_lock);
4787
4788 return 0;
4789 }
4790
4791 static int
4792 i915_max_freq_set(void *data, u64 val)
4793 {
4794 struct drm_device *dev = data;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 u32 hw_max, hw_min;
4797 int ret;
4798
4799 if (INTEL_INFO(dev)->gen < 6)
4800 return -ENODEV;
4801
4802 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4803
4804 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4805
4806 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4807 if (ret)
4808 return ret;
4809
4810 /*
4811 * Turbo will still be enabled, but won't go above the set value.
4812 */
4813 val = intel_freq_opcode(dev_priv, val);
4814
4815 hw_max = dev_priv->rps.max_freq;
4816 hw_min = dev_priv->rps.min_freq;
4817
4818 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4819 mutex_unlock(&dev_priv->rps.hw_lock);
4820 return -EINVAL;
4821 }
4822
4823 dev_priv->rps.max_freq_softlimit = val;
4824
4825 intel_set_rps(dev, val);
4826
4827 mutex_unlock(&dev_priv->rps.hw_lock);
4828
4829 return 0;
4830 }
4831
4832 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4833 i915_max_freq_get, i915_max_freq_set,
4834 "%llu\n");
4835
4836 static int
4837 i915_min_freq_get(void *data, u64 *val)
4838 {
4839 struct drm_device *dev = data;
4840 struct drm_i915_private *dev_priv = dev->dev_private;
4841 int ret;
4842
4843 if (INTEL_INFO(dev)->gen < 6)
4844 return -ENODEV;
4845
4846 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4847
4848 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4849 if (ret)
4850 return ret;
4851
4852 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4853 mutex_unlock(&dev_priv->rps.hw_lock);
4854
4855 return 0;
4856 }
4857
4858 static int
4859 i915_min_freq_set(void *data, u64 val)
4860 {
4861 struct drm_device *dev = data;
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4863 u32 hw_max, hw_min;
4864 int ret;
4865
4866 if (INTEL_INFO(dev)->gen < 6)
4867 return -ENODEV;
4868
4869 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4870
4871 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4872
4873 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4874 if (ret)
4875 return ret;
4876
4877 /*
4878 * Turbo will still be enabled, but won't go below the set value.
4879 */
4880 val = intel_freq_opcode(dev_priv, val);
4881
4882 hw_max = dev_priv->rps.max_freq;
4883 hw_min = dev_priv->rps.min_freq;
4884
4885 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4886 mutex_unlock(&dev_priv->rps.hw_lock);
4887 return -EINVAL;
4888 }
4889
4890 dev_priv->rps.min_freq_softlimit = val;
4891
4892 intel_set_rps(dev, val);
4893
4894 mutex_unlock(&dev_priv->rps.hw_lock);
4895
4896 return 0;
4897 }
4898
4899 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4900 i915_min_freq_get, i915_min_freq_set,
4901 "%llu\n");
4902
4903 static int
4904 i915_cache_sharing_get(void *data, u64 *val)
4905 {
4906 struct drm_device *dev = data;
4907 struct drm_i915_private *dev_priv = dev->dev_private;
4908 u32 snpcr;
4909 int ret;
4910
4911 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4912 return -ENODEV;
4913
4914 ret = mutex_lock_interruptible(&dev->struct_mutex);
4915 if (ret)
4916 return ret;
4917 intel_runtime_pm_get(dev_priv);
4918
4919 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4920
4921 intel_runtime_pm_put(dev_priv);
4922 mutex_unlock(&dev_priv->dev->struct_mutex);
4923
4924 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4925
4926 return 0;
4927 }
4928
4929 static int
4930 i915_cache_sharing_set(void *data, u64 val)
4931 {
4932 struct drm_device *dev = data;
4933 struct drm_i915_private *dev_priv = dev->dev_private;
4934 u32 snpcr;
4935
4936 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4937 return -ENODEV;
4938
4939 if (val > 3)
4940 return -EINVAL;
4941
4942 intel_runtime_pm_get(dev_priv);
4943 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4944
4945 /* Update the cache sharing policy here as well */
4946 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4947 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4948 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4949 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4950
4951 intel_runtime_pm_put(dev_priv);
4952 return 0;
4953 }
4954
4955 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4956 i915_cache_sharing_get, i915_cache_sharing_set,
4957 "%llu\n");
4958
4959 struct sseu_dev_status {
4960 unsigned int slice_total;
4961 unsigned int subslice_total;
4962 unsigned int subslice_per_slice;
4963 unsigned int eu_total;
4964 unsigned int eu_per_subslice;
4965 };
4966
4967 static void cherryview_sseu_device_status(struct drm_device *dev,
4968 struct sseu_dev_status *stat)
4969 {
4970 struct drm_i915_private *dev_priv = dev->dev_private;
4971 int ss_max = 2;
4972 int ss;
4973 u32 sig1[ss_max], sig2[ss_max];
4974
4975 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4976 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4977 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4978 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4979
4980 for (ss = 0; ss < ss_max; ss++) {
4981 unsigned int eu_cnt;
4982
4983 if (sig1[ss] & CHV_SS_PG_ENABLE)
4984 /* skip disabled subslice */
4985 continue;
4986
4987 stat->slice_total = 1;
4988 stat->subslice_per_slice++;
4989 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4990 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4991 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4992 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4993 stat->eu_total += eu_cnt;
4994 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4995 }
4996 stat->subslice_total = stat->subslice_per_slice;
4997 }
4998
4999 static void gen9_sseu_device_status(struct drm_device *dev,
5000 struct sseu_dev_status *stat)
5001 {
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 int s_max = 3, ss_max = 4;
5004 int s, ss;
5005 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5006
5007 /* BXT has a single slice and at most 3 subslices. */
5008 if (IS_BROXTON(dev)) {
5009 s_max = 1;
5010 ss_max = 3;
5011 }
5012
5013 for (s = 0; s < s_max; s++) {
5014 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5015 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5016 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5017 }
5018
5019 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5020 GEN9_PGCTL_SSA_EU19_ACK |
5021 GEN9_PGCTL_SSA_EU210_ACK |
5022 GEN9_PGCTL_SSA_EU311_ACK;
5023 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5024 GEN9_PGCTL_SSB_EU19_ACK |
5025 GEN9_PGCTL_SSB_EU210_ACK |
5026 GEN9_PGCTL_SSB_EU311_ACK;
5027
5028 for (s = 0; s < s_max; s++) {
5029 unsigned int ss_cnt = 0;
5030
5031 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5032 /* skip disabled slice */
5033 continue;
5034
5035 stat->slice_total++;
5036
5037 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5038 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5039
5040 for (ss = 0; ss < ss_max; ss++) {
5041 unsigned int eu_cnt;
5042
5043 if (IS_BROXTON(dev) &&
5044 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5045 /* skip disabled subslice */
5046 continue;
5047
5048 if (IS_BROXTON(dev))
5049 ss_cnt++;
5050
5051 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5052 eu_mask[ss%2]);
5053 stat->eu_total += eu_cnt;
5054 stat->eu_per_subslice = max(stat->eu_per_subslice,
5055 eu_cnt);
5056 }
5057
5058 stat->subslice_total += ss_cnt;
5059 stat->subslice_per_slice = max(stat->subslice_per_slice,
5060 ss_cnt);
5061 }
5062 }
5063
5064 static void broadwell_sseu_device_status(struct drm_device *dev,
5065 struct sseu_dev_status *stat)
5066 {
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068 int s;
5069 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5070
5071 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5072
5073 if (stat->slice_total) {
5074 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5075 stat->subslice_total = stat->slice_total *
5076 stat->subslice_per_slice;
5077 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5078 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5079
5080 /* subtract fused off EU(s) from enabled slice(s) */
5081 for (s = 0; s < stat->slice_total; s++) {
5082 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5083
5084 stat->eu_total -= hweight8(subslice_7eu);
5085 }
5086 }
5087 }
5088
5089 static int i915_sseu_status(struct seq_file *m, void *unused)
5090 {
5091 struct drm_info_node *node = (struct drm_info_node *) m->private;
5092 struct drm_device *dev = node->minor->dev;
5093 struct sseu_dev_status stat;
5094
5095 if (INTEL_INFO(dev)->gen < 8)
5096 return -ENODEV;
5097
5098 seq_puts(m, "SSEU Device Info\n");
5099 seq_printf(m, " Available Slice Total: %u\n",
5100 INTEL_INFO(dev)->slice_total);
5101 seq_printf(m, " Available Subslice Total: %u\n",
5102 INTEL_INFO(dev)->subslice_total);
5103 seq_printf(m, " Available Subslice Per Slice: %u\n",
5104 INTEL_INFO(dev)->subslice_per_slice);
5105 seq_printf(m, " Available EU Total: %u\n",
5106 INTEL_INFO(dev)->eu_total);
5107 seq_printf(m, " Available EU Per Subslice: %u\n",
5108 INTEL_INFO(dev)->eu_per_subslice);
5109 seq_printf(m, " Has Slice Power Gating: %s\n",
5110 yesno(INTEL_INFO(dev)->has_slice_pg));
5111 seq_printf(m, " Has Subslice Power Gating: %s\n",
5112 yesno(INTEL_INFO(dev)->has_subslice_pg));
5113 seq_printf(m, " Has EU Power Gating: %s\n",
5114 yesno(INTEL_INFO(dev)->has_eu_pg));
5115
5116 seq_puts(m, "SSEU Device Status\n");
5117 memset(&stat, 0, sizeof(stat));
5118 if (IS_CHERRYVIEW(dev)) {
5119 cherryview_sseu_device_status(dev, &stat);
5120 } else if (IS_BROADWELL(dev)) {
5121 broadwell_sseu_device_status(dev, &stat);
5122 } else if (INTEL_INFO(dev)->gen >= 9) {
5123 gen9_sseu_device_status(dev, &stat);
5124 }
5125 seq_printf(m, " Enabled Slice Total: %u\n",
5126 stat.slice_total);
5127 seq_printf(m, " Enabled Subslice Total: %u\n",
5128 stat.subslice_total);
5129 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5130 stat.subslice_per_slice);
5131 seq_printf(m, " Enabled EU Total: %u\n",
5132 stat.eu_total);
5133 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5134 stat.eu_per_subslice);
5135
5136 return 0;
5137 }
5138
5139 static int i915_forcewake_open(struct inode *inode, struct file *file)
5140 {
5141 struct drm_device *dev = inode->i_private;
5142 struct drm_i915_private *dev_priv = dev->dev_private;
5143
5144 if (INTEL_INFO(dev)->gen < 6)
5145 return 0;
5146
5147 intel_runtime_pm_get(dev_priv);
5148 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5149
5150 return 0;
5151 }
5152
5153 static int i915_forcewake_release(struct inode *inode, struct file *file)
5154 {
5155 struct drm_device *dev = inode->i_private;
5156 struct drm_i915_private *dev_priv = dev->dev_private;
5157
5158 if (INTEL_INFO(dev)->gen < 6)
5159 return 0;
5160
5161 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5162 intel_runtime_pm_put(dev_priv);
5163
5164 return 0;
5165 }
5166
5167 static const struct file_operations i915_forcewake_fops = {
5168 .owner = THIS_MODULE,
5169 .open = i915_forcewake_open,
5170 .release = i915_forcewake_release,
5171 };
5172
5173 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5174 {
5175 struct drm_device *dev = minor->dev;
5176 struct dentry *ent;
5177
5178 ent = debugfs_create_file("i915_forcewake_user",
5179 S_IRUSR,
5180 root, dev,
5181 &i915_forcewake_fops);
5182 if (!ent)
5183 return -ENOMEM;
5184
5185 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5186 }
5187
5188 static int i915_debugfs_create(struct dentry *root,
5189 struct drm_minor *minor,
5190 const char *name,
5191 const struct file_operations *fops)
5192 {
5193 struct drm_device *dev = minor->dev;
5194 struct dentry *ent;
5195
5196 ent = debugfs_create_file(name,
5197 S_IRUGO | S_IWUSR,
5198 root, dev,
5199 fops);
5200 if (!ent)
5201 return -ENOMEM;
5202
5203 return drm_add_fake_info_node(minor, ent, fops);
5204 }
5205
5206 static const struct drm_info_list i915_debugfs_list[] = {
5207 {"i915_capabilities", i915_capabilities, 0},
5208 {"i915_gem_objects", i915_gem_object_info, 0},
5209 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5210 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5211 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5212 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5213 {"i915_gem_stolen", i915_gem_stolen_list_info },
5214 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5215 {"i915_gem_request", i915_gem_request_info, 0},
5216 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5217 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5218 {"i915_gem_interrupt", i915_interrupt_info, 0},
5219 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5220 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5221 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5222 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5223 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5224 {"i915_guc_info", i915_guc_info, 0},
5225 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5226 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5227 {"i915_frequency_info", i915_frequency_info, 0},
5228 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5229 {"i915_drpc_info", i915_drpc_info, 0},
5230 {"i915_emon_status", i915_emon_status, 0},
5231 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5232 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5233 {"i915_fbc_status", i915_fbc_status, 0},
5234 {"i915_ips_status", i915_ips_status, 0},
5235 {"i915_sr_status", i915_sr_status, 0},
5236 {"i915_opregion", i915_opregion, 0},
5237 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5238 {"i915_context_status", i915_context_status, 0},
5239 {"i915_dump_lrc", i915_dump_lrc, 0},
5240 {"i915_execlists", i915_execlists, 0},
5241 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5242 {"i915_swizzle_info", i915_swizzle_info, 0},
5243 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5244 {"i915_llc", i915_llc, 0},
5245 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5246 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5247 {"i915_energy_uJ", i915_energy_uJ, 0},
5248 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5249 {"i915_power_domain_info", i915_power_domain_info, 0},
5250 {"i915_display_info", i915_display_info, 0},
5251 {"i915_semaphore_status", i915_semaphore_status, 0},
5252 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5253 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5254 {"i915_wa_registers", i915_wa_registers, 0},
5255 {"i915_ddb_info", i915_ddb_info, 0},
5256 {"i915_sseu_status", i915_sseu_status, 0},
5257 {"i915_drrs_status", i915_drrs_status, 0},
5258 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5259 };
5260 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5261
5262 static const struct i915_debugfs_files {
5263 const char *name;
5264 const struct file_operations *fops;
5265 } i915_debugfs_files[] = {
5266 {"i915_wedged", &i915_wedged_fops},
5267 {"i915_max_freq", &i915_max_freq_fops},
5268 {"i915_min_freq", &i915_min_freq_fops},
5269 {"i915_cache_sharing", &i915_cache_sharing_fops},
5270 {"i915_ring_stop", &i915_ring_stop_fops},
5271 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5272 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5273 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5274 {"i915_error_state", &i915_error_state_fops},
5275 {"i915_next_seqno", &i915_next_seqno_fops},
5276 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5277 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5278 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5279 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5280 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5281 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5282 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5283 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5284 };
5285
5286 void intel_display_crc_init(struct drm_device *dev)
5287 {
5288 struct drm_i915_private *dev_priv = dev->dev_private;
5289 enum pipe pipe;
5290
5291 for_each_pipe(dev_priv, pipe) {
5292 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5293
5294 pipe_crc->opened = false;
5295 spin_lock_init(&pipe_crc->lock);
5296 init_waitqueue_head(&pipe_crc->wq);
5297 }
5298 }
5299
5300 int i915_debugfs_init(struct drm_minor *minor)
5301 {
5302 int ret, i;
5303
5304 ret = i915_forcewake_create(minor->debugfs_root, minor);
5305 if (ret)
5306 return ret;
5307
5308 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5309 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5310 if (ret)
5311 return ret;
5312 }
5313
5314 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5315 ret = i915_debugfs_create(minor->debugfs_root, minor,
5316 i915_debugfs_files[i].name,
5317 i915_debugfs_files[i].fops);
5318 if (ret)
5319 return ret;
5320 }
5321
5322 return drm_debugfs_create_files(i915_debugfs_list,
5323 I915_DEBUGFS_ENTRIES,
5324 minor->debugfs_root, minor);
5325 }
5326
5327 void i915_debugfs_cleanup(struct drm_minor *minor)
5328 {
5329 int i;
5330
5331 drm_debugfs_remove_files(i915_debugfs_list,
5332 I915_DEBUGFS_ENTRIES, minor);
5333
5334 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5335 1, minor);
5336
5337 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5338 struct drm_info_list *info_list =
5339 (struct drm_info_list *)&i915_pipe_crc_data[i];
5340
5341 drm_debugfs_remove_files(info_list, 1, minor);
5342 }
5343
5344 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5345 struct drm_info_list *info_list =
5346 (struct drm_info_list *) i915_debugfs_files[i].fops;
5347
5348 drm_debugfs_remove_files(info_list, 1, minor);
5349 }
5350 }
5351
5352 struct dpcd_block {
5353 /* DPCD dump start address. */
5354 unsigned int offset;
5355 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5356 unsigned int end;
5357 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5358 size_t size;
5359 /* Only valid for eDP. */
5360 bool edp;
5361 };
5362
5363 static const struct dpcd_block i915_dpcd_debug[] = {
5364 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5365 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5366 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5367 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5368 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5369 { .offset = DP_SET_POWER },
5370 { .offset = DP_EDP_DPCD_REV },
5371 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5372 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5373 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5374 };
5375
5376 static int i915_dpcd_show(struct seq_file *m, void *data)
5377 {
5378 struct drm_connector *connector = m->private;
5379 struct intel_dp *intel_dp =
5380 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5381 uint8_t buf[16];
5382 ssize_t err;
5383 int i;
5384
5385 if (connector->status != connector_status_connected)
5386 return -ENODEV;
5387
5388 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5389 const struct dpcd_block *b = &i915_dpcd_debug[i];
5390 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5391
5392 if (b->edp &&
5393 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5394 continue;
5395
5396 /* low tech for now */
5397 if (WARN_ON(size > sizeof(buf)))
5398 continue;
5399
5400 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5401 if (err <= 0) {
5402 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5403 size, b->offset, err);
5404 continue;
5405 }
5406
5407 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5408 }
5409
5410 return 0;
5411 }
5412
5413 static int i915_dpcd_open(struct inode *inode, struct file *file)
5414 {
5415 return single_open(file, i915_dpcd_show, inode->i_private);
5416 }
5417
5418 static const struct file_operations i915_dpcd_fops = {
5419 .owner = THIS_MODULE,
5420 .open = i915_dpcd_open,
5421 .read = seq_read,
5422 .llseek = seq_lseek,
5423 .release = single_release,
5424 };
5425
5426 /**
5427 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5428 * @connector: pointer to a registered drm_connector
5429 *
5430 * Cleanup will be done by drm_connector_unregister() through a call to
5431 * drm_debugfs_connector_remove().
5432 *
5433 * Returns 0 on success, negative error codes on error.
5434 */
5435 int i915_debugfs_connector_add(struct drm_connector *connector)
5436 {
5437 struct dentry *root = connector->debugfs_entry;
5438
5439 /* The connector must have been registered beforehands. */
5440 if (!root)
5441 return -ENODEV;
5442
5443 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5444 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5445 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5446 &i915_dpcd_fops);
5447
5448 return 0;
5449 }
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