2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (obj
->user_pin_count
> 0)
101 else if (i915_gem_obj_is_pinned(obj
))
107 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
109 switch (obj
->tiling_mode
) {
111 case I915_TILING_NONE
: return " ";
112 case I915_TILING_X
: return "X";
113 case I915_TILING_Y
: return "Y";
117 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
119 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
123 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
128 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj
),
132 get_global_flag(obj
),
133 obj
->base
.size
/ 1024,
134 obj
->base
.read_domains
,
135 obj
->base
.write_domain
,
136 obj
->last_read_seqno
,
137 obj
->last_write_seqno
,
138 obj
->last_fenced_seqno
,
139 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
140 obj
->dirty
? " dirty" : "",
141 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
143 seq_printf(m
, " (name: %d)", obj
->base
.name
);
144 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
145 if (vma
->pin_count
> 0)
147 seq_printf(m
, " (pinned x %d)", pin_count
);
148 if (obj
->pin_display
)
149 seq_printf(m
, " (display)");
150 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
151 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
152 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
153 if (!i915_is_ggtt(vma
->vm
))
157 seq_printf(m
, "gtt offset: %08lx, size: %08lx)",
158 vma
->node
.start
, vma
->node
.size
);
161 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
162 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
164 if (obj
->pin_mappable
)
166 if (obj
->fault_mappable
)
169 seq_printf(m
, " (%s mappable)", s
);
171 if (obj
->ring
!= NULL
)
172 seq_printf(m
, " (%s)", obj
->ring
->name
);
173 if (obj
->frontbuffer_bits
)
174 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
177 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
179 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
180 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
184 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
186 struct drm_info_node
*node
= m
->private;
187 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
188 struct list_head
*head
;
189 struct drm_device
*dev
= node
->minor
->dev
;
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
191 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
192 struct i915_vma
*vma
;
193 size_t total_obj_size
, total_gtt_size
;
196 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
200 /* FIXME: the user of this interface might want more than just GGTT */
203 seq_puts(m
, "Active:\n");
204 head
= &vm
->active_list
;
207 seq_puts(m
, "Inactive:\n");
208 head
= &vm
->inactive_list
;
211 mutex_unlock(&dev
->struct_mutex
);
215 total_obj_size
= total_gtt_size
= count
= 0;
216 list_for_each_entry(vma
, head
, mm_list
) {
218 describe_obj(m
, vma
->obj
);
220 total_obj_size
+= vma
->obj
->base
.size
;
221 total_gtt_size
+= vma
->node
.size
;
224 mutex_unlock(&dev
->struct_mutex
);
226 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count
, total_obj_size
, total_gtt_size
);
231 static int obj_rank_by_stolen(void *priv
,
232 struct list_head
*A
, struct list_head
*B
)
234 struct drm_i915_gem_object
*a
=
235 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
236 struct drm_i915_gem_object
*b
=
237 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
239 return a
->stolen
->start
- b
->stolen
->start
;
242 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
244 struct drm_info_node
*node
= m
->private;
245 struct drm_device
*dev
= node
->minor
->dev
;
246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
247 struct drm_i915_gem_object
*obj
;
248 size_t total_obj_size
, total_gtt_size
;
252 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
256 total_obj_size
= total_gtt_size
= count
= 0;
257 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
258 if (obj
->stolen
== NULL
)
261 list_add(&obj
->obj_exec_link
, &stolen
);
263 total_obj_size
+= obj
->base
.size
;
264 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
267 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
268 if (obj
->stolen
== NULL
)
271 list_add(&obj
->obj_exec_link
, &stolen
);
273 total_obj_size
+= obj
->base
.size
;
276 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
277 seq_puts(m
, "Stolen:\n");
278 while (!list_empty(&stolen
)) {
279 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
281 describe_obj(m
, obj
);
283 list_del_init(&obj
->obj_exec_link
);
285 mutex_unlock(&dev
->struct_mutex
);
287 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count
, total_obj_size
, total_gtt_size
);
292 #define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
294 size += i915_gem_obj_ggtt_size(obj); \
296 if (obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(obj); \
304 struct drm_i915_file_private
*file_priv
;
306 size_t total
, unbound
;
307 size_t global
, shared
;
308 size_t active
, inactive
;
311 static int per_file_stats(int id
, void *ptr
, void *data
)
313 struct drm_i915_gem_object
*obj
= ptr
;
314 struct file_stats
*stats
= data
;
315 struct i915_vma
*vma
;
318 stats
->total
+= obj
->base
.size
;
320 if (obj
->base
.name
|| obj
->base
.dma_buf
)
321 stats
->shared
+= obj
->base
.size
;
323 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
324 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
325 struct i915_hw_ppgtt
*ppgtt
;
327 if (!drm_mm_node_allocated(&vma
->node
))
330 if (i915_is_ggtt(vma
->vm
)) {
331 stats
->global
+= obj
->base
.size
;
335 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
336 if (ppgtt
->file_priv
!= stats
->file_priv
)
339 if (obj
->ring
) /* XXX per-vma statistic */
340 stats
->active
+= obj
->base
.size
;
342 stats
->inactive
+= obj
->base
.size
;
347 if (i915_gem_obj_ggtt_bound(obj
)) {
348 stats
->global
+= obj
->base
.size
;
350 stats
->active
+= obj
->base
.size
;
352 stats
->inactive
+= obj
->base
.size
;
357 if (!list_empty(&obj
->global_list
))
358 stats
->unbound
+= obj
->base
.size
;
363 #define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
374 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
376 struct drm_info_node
*node
= m
->private;
377 struct drm_device
*dev
= node
->minor
->dev
;
378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
379 u32 count
, mappable_count
, purgeable_count
;
380 size_t size
, mappable_size
, purgeable_size
;
381 struct drm_i915_gem_object
*obj
;
382 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
383 struct drm_file
*file
;
384 struct i915_vma
*vma
;
387 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
391 seq_printf(m
, "%u objects, %zu bytes\n",
392 dev_priv
->mm
.object_count
,
393 dev_priv
->mm
.object_memory
);
395 size
= count
= mappable_size
= mappable_count
= 0;
396 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
397 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count
, mappable_count
, size
, mappable_size
);
400 size
= count
= mappable_size
= mappable_count
= 0;
401 count_vmas(&vm
->active_list
, mm_list
);
402 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count
, mappable_count
, size
, mappable_size
);
405 size
= count
= mappable_size
= mappable_count
= 0;
406 count_vmas(&vm
->inactive_list
, mm_list
);
407 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count
, mappable_count
, size
, mappable_size
);
410 size
= count
= purgeable_size
= purgeable_count
= 0;
411 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
412 size
+= obj
->base
.size
, ++count
;
413 if (obj
->madv
== I915_MADV_DONTNEED
)
414 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
416 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
418 size
= count
= mappable_size
= mappable_count
= 0;
419 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
420 if (obj
->fault_mappable
) {
421 size
+= i915_gem_obj_ggtt_size(obj
);
424 if (obj
->pin_mappable
) {
425 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
428 if (obj
->madv
== I915_MADV_DONTNEED
) {
429 purgeable_size
+= obj
->base
.size
;
433 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
434 purgeable_count
, purgeable_size
);
435 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count
, mappable_size
);
437 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
440 seq_printf(m
, "%zu [%lu] gtt total\n",
441 dev_priv
->gtt
.base
.total
,
442 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
445 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
446 struct file_stats stats
;
447 struct task_struct
*task
;
449 memset(&stats
, 0, sizeof(stats
));
450 stats
.file_priv
= file
->driver_priv
;
451 spin_lock(&file
->table_lock
);
452 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
453 spin_unlock(&file
->table_lock
);
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
461 task
= pid_task(file
->pid
, PIDTYPE_PID
);
462 seq_printf(m
, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
463 task
? task
->comm
: "<unknown>",
474 mutex_unlock(&dev
->struct_mutex
);
479 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
481 struct drm_info_node
*node
= m
->private;
482 struct drm_device
*dev
= node
->minor
->dev
;
483 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
485 struct drm_i915_gem_object
*obj
;
486 size_t total_obj_size
, total_gtt_size
;
489 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
493 total_obj_size
= total_gtt_size
= count
= 0;
494 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
495 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
499 describe_obj(m
, obj
);
501 total_obj_size
+= obj
->base
.size
;
502 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
506 mutex_unlock(&dev
->struct_mutex
);
508 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count
, total_obj_size
, total_gtt_size
);
514 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
516 struct drm_info_node
*node
= m
->private;
517 struct drm_device
*dev
= node
->minor
->dev
;
518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
519 struct intel_crtc
*crtc
;
522 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
526 for_each_intel_crtc(dev
, crtc
) {
527 const char pipe
= pipe_name(crtc
->pipe
);
528 const char plane
= plane_name(crtc
->plane
);
529 struct intel_unpin_work
*work
;
531 spin_lock_irq(&dev
->event_lock
);
532 work
= crtc
->unpin_work
;
534 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
539 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
540 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
543 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
546 if (work
->flip_queued_ring
) {
547 seq_printf(m
, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
548 work
->flip_queued_ring
->name
,
549 work
->flip_queued_seqno
,
550 dev_priv
->next_seqno
,
551 work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
552 i915_seqno_passed(work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
553 work
->flip_queued_seqno
));
555 seq_printf(m
, "Flip not associated with any ring\n");
556 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
557 work
->flip_queued_vblank
,
558 work
->flip_ready_vblank
,
559 drm_vblank_count(dev
, crtc
->pipe
));
560 if (work
->enable_stall_check
)
561 seq_puts(m
, "Stall check enabled, ");
563 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
564 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
566 if (INTEL_INFO(dev
)->gen
>= 4)
567 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
569 addr
= I915_READ(DSPADDR(crtc
->plane
));
570 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
572 if (work
->pending_flip_obj
) {
573 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
574 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
577 spin_unlock_irq(&dev
->event_lock
);
580 mutex_unlock(&dev
->struct_mutex
);
585 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
587 struct drm_info_node
*node
= m
->private;
588 struct drm_device
*dev
= node
->minor
->dev
;
589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
590 struct intel_engine_cs
*ring
;
591 struct drm_i915_gem_request
*gem_request
;
594 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
599 for_each_ring(ring
, dev_priv
, i
) {
600 if (list_empty(&ring
->request_list
))
603 seq_printf(m
, "%s requests:\n", ring
->name
);
604 list_for_each_entry(gem_request
,
607 seq_printf(m
, " %d @ %d\n",
609 (int) (jiffies
- gem_request
->emitted_jiffies
));
613 mutex_unlock(&dev
->struct_mutex
);
616 seq_puts(m
, "No requests\n");
621 static void i915_ring_seqno_info(struct seq_file
*m
,
622 struct intel_engine_cs
*ring
)
624 if (ring
->get_seqno
) {
625 seq_printf(m
, "Current sequence (%s): %u\n",
626 ring
->name
, ring
->get_seqno(ring
, false));
630 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
632 struct drm_info_node
*node
= m
->private;
633 struct drm_device
*dev
= node
->minor
->dev
;
634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
635 struct intel_engine_cs
*ring
;
638 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
641 intel_runtime_pm_get(dev_priv
);
643 for_each_ring(ring
, dev_priv
, i
)
644 i915_ring_seqno_info(m
, ring
);
646 intel_runtime_pm_put(dev_priv
);
647 mutex_unlock(&dev
->struct_mutex
);
653 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
655 struct drm_info_node
*node
= m
->private;
656 struct drm_device
*dev
= node
->minor
->dev
;
657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
658 struct intel_engine_cs
*ring
;
661 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
664 intel_runtime_pm_get(dev_priv
);
666 if (IS_CHERRYVIEW(dev
)) {
667 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
668 I915_READ(GEN8_MASTER_IRQ
));
670 seq_printf(m
, "Display IER:\t%08x\n",
672 seq_printf(m
, "Display IIR:\t%08x\n",
674 seq_printf(m
, "Display IIR_RW:\t%08x\n",
675 I915_READ(VLV_IIR_RW
));
676 seq_printf(m
, "Display IMR:\t%08x\n",
678 for_each_pipe(dev_priv
, pipe
)
679 seq_printf(m
, "Pipe %c stat:\t%08x\n",
681 I915_READ(PIPESTAT(pipe
)));
683 seq_printf(m
, "Port hotplug:\t%08x\n",
684 I915_READ(PORT_HOTPLUG_EN
));
685 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
686 I915_READ(VLV_DPFLIPSTAT
));
687 seq_printf(m
, "DPINVGTT:\t%08x\n",
688 I915_READ(DPINVGTT
));
690 for (i
= 0; i
< 4; i
++) {
691 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
692 i
, I915_READ(GEN8_GT_IMR(i
)));
693 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
694 i
, I915_READ(GEN8_GT_IIR(i
)));
695 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
696 i
, I915_READ(GEN8_GT_IER(i
)));
699 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
700 I915_READ(GEN8_PCU_IMR
));
701 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
702 I915_READ(GEN8_PCU_IIR
));
703 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
704 I915_READ(GEN8_PCU_IER
));
705 } else if (INTEL_INFO(dev
)->gen
>= 8) {
706 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
707 I915_READ(GEN8_MASTER_IRQ
));
709 for (i
= 0; i
< 4; i
++) {
710 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
711 i
, I915_READ(GEN8_GT_IMR(i
)));
712 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
713 i
, I915_READ(GEN8_GT_IIR(i
)));
714 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
715 i
, I915_READ(GEN8_GT_IER(i
)));
718 for_each_pipe(dev_priv
, pipe
) {
719 if (!intel_display_power_is_enabled(dev_priv
,
720 POWER_DOMAIN_PIPE(pipe
))) {
721 seq_printf(m
, "Pipe %c power disabled\n",
725 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
727 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
728 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
730 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
731 seq_printf(m
, "Pipe %c IER:\t%08x\n",
733 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
736 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
737 I915_READ(GEN8_DE_PORT_IMR
));
738 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
739 I915_READ(GEN8_DE_PORT_IIR
));
740 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
741 I915_READ(GEN8_DE_PORT_IER
));
743 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
744 I915_READ(GEN8_DE_MISC_IMR
));
745 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
746 I915_READ(GEN8_DE_MISC_IIR
));
747 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
748 I915_READ(GEN8_DE_MISC_IER
));
750 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
751 I915_READ(GEN8_PCU_IMR
));
752 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
753 I915_READ(GEN8_PCU_IIR
));
754 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
755 I915_READ(GEN8_PCU_IER
));
756 } else if (IS_VALLEYVIEW(dev
)) {
757 seq_printf(m
, "Display IER:\t%08x\n",
759 seq_printf(m
, "Display IIR:\t%08x\n",
761 seq_printf(m
, "Display IIR_RW:\t%08x\n",
762 I915_READ(VLV_IIR_RW
));
763 seq_printf(m
, "Display IMR:\t%08x\n",
765 for_each_pipe(dev_priv
, pipe
)
766 seq_printf(m
, "Pipe %c stat:\t%08x\n",
768 I915_READ(PIPESTAT(pipe
)));
770 seq_printf(m
, "Master IER:\t%08x\n",
771 I915_READ(VLV_MASTER_IER
));
773 seq_printf(m
, "Render IER:\t%08x\n",
775 seq_printf(m
, "Render IIR:\t%08x\n",
777 seq_printf(m
, "Render IMR:\t%08x\n",
780 seq_printf(m
, "PM IER:\t\t%08x\n",
781 I915_READ(GEN6_PMIER
));
782 seq_printf(m
, "PM IIR:\t\t%08x\n",
783 I915_READ(GEN6_PMIIR
));
784 seq_printf(m
, "PM IMR:\t\t%08x\n",
785 I915_READ(GEN6_PMIMR
));
787 seq_printf(m
, "Port hotplug:\t%08x\n",
788 I915_READ(PORT_HOTPLUG_EN
));
789 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
790 I915_READ(VLV_DPFLIPSTAT
));
791 seq_printf(m
, "DPINVGTT:\t%08x\n",
792 I915_READ(DPINVGTT
));
794 } else if (!HAS_PCH_SPLIT(dev
)) {
795 seq_printf(m
, "Interrupt enable: %08x\n",
797 seq_printf(m
, "Interrupt identity: %08x\n",
799 seq_printf(m
, "Interrupt mask: %08x\n",
801 for_each_pipe(dev_priv
, pipe
)
802 seq_printf(m
, "Pipe %c stat: %08x\n",
804 I915_READ(PIPESTAT(pipe
)));
806 seq_printf(m
, "North Display Interrupt enable: %08x\n",
808 seq_printf(m
, "North Display Interrupt identity: %08x\n",
810 seq_printf(m
, "North Display Interrupt mask: %08x\n",
812 seq_printf(m
, "South Display Interrupt enable: %08x\n",
814 seq_printf(m
, "South Display Interrupt identity: %08x\n",
816 seq_printf(m
, "South Display Interrupt mask: %08x\n",
818 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
820 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
822 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
825 for_each_ring(ring
, dev_priv
, i
) {
826 if (INTEL_INFO(dev
)->gen
>= 6) {
828 "Graphics Interrupt mask (%s): %08x\n",
829 ring
->name
, I915_READ_IMR(ring
));
831 i915_ring_seqno_info(m
, ring
);
833 intel_runtime_pm_put(dev_priv
);
834 mutex_unlock(&dev
->struct_mutex
);
839 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
841 struct drm_info_node
*node
= m
->private;
842 struct drm_device
*dev
= node
->minor
->dev
;
843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
846 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
850 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
851 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
852 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
853 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
855 seq_printf(m
, "Fence %d, pin count = %d, object = ",
856 i
, dev_priv
->fence_regs
[i
].pin_count
);
858 seq_puts(m
, "unused");
860 describe_obj(m
, obj
);
864 mutex_unlock(&dev
->struct_mutex
);
868 static int i915_hws_info(struct seq_file
*m
, void *data
)
870 struct drm_info_node
*node
= m
->private;
871 struct drm_device
*dev
= node
->minor
->dev
;
872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
873 struct intel_engine_cs
*ring
;
877 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
878 hws
= ring
->status_page
.page_addr
;
882 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
883 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
885 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
891 i915_error_state_write(struct file
*filp
,
892 const char __user
*ubuf
,
896 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
897 struct drm_device
*dev
= error_priv
->dev
;
900 DRM_DEBUG_DRIVER("Resetting error state\n");
902 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
906 i915_destroy_error_state(dev
);
907 mutex_unlock(&dev
->struct_mutex
);
912 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
914 struct drm_device
*dev
= inode
->i_private
;
915 struct i915_error_state_file_priv
*error_priv
;
917 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
921 error_priv
->dev
= dev
;
923 i915_error_state_get(dev
, error_priv
);
925 file
->private_data
= error_priv
;
930 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
932 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
934 i915_error_state_put(error_priv
);
940 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
941 size_t count
, loff_t
*pos
)
943 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
944 struct drm_i915_error_state_buf error_str
;
946 ssize_t ret_count
= 0;
949 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
953 ret
= i915_error_state_to_str(&error_str
, error_priv
);
957 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
964 *pos
= error_str
.start
+ ret_count
;
966 i915_error_state_buf_release(&error_str
);
967 return ret
?: ret_count
;
970 static const struct file_operations i915_error_state_fops
= {
971 .owner
= THIS_MODULE
,
972 .open
= i915_error_state_open
,
973 .read
= i915_error_state_read
,
974 .write
= i915_error_state_write
,
975 .llseek
= default_llseek
,
976 .release
= i915_error_state_release
,
980 i915_next_seqno_get(void *data
, u64
*val
)
982 struct drm_device
*dev
= data
;
983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
986 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
990 *val
= dev_priv
->next_seqno
;
991 mutex_unlock(&dev
->struct_mutex
);
997 i915_next_seqno_set(void *data
, u64 val
)
999 struct drm_device
*dev
= data
;
1002 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1006 ret
= i915_gem_set_seqno(dev
, val
);
1007 mutex_unlock(&dev
->struct_mutex
);
1012 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1013 i915_next_seqno_get
, i915_next_seqno_set
,
1016 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1018 struct drm_info_node
*node
= m
->private;
1019 struct drm_device
*dev
= node
->minor
->dev
;
1020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1023 intel_runtime_pm_get(dev_priv
);
1025 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1028 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1029 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1031 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1032 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1033 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1035 seq_printf(m
, "Current P-state: %d\n",
1036 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1037 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1038 IS_BROADWELL(dev
)) {
1039 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1040 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1041 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1042 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1043 u32 rpstat
, cagf
, reqf
;
1044 u32 rpupei
, rpcurup
, rpprevup
;
1045 u32 rpdownei
, rpcurdown
, rpprevdown
;
1046 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1049 /* RPSTAT1 is in the GT power well */
1050 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1054 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
1056 reqf
= I915_READ(GEN6_RPNSWREQ
);
1057 reqf
&= ~GEN6_TURBO_DISABLE
;
1058 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1062 reqf
*= GT_FREQUENCY_MULTIPLIER
;
1064 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1065 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1066 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1068 rpstat
= I915_READ(GEN6_RPSTAT1
);
1069 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1070 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1071 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1072 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1073 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1074 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1075 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1076 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1078 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1079 cagf
*= GT_FREQUENCY_MULTIPLIER
;
1081 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
1082 mutex_unlock(&dev
->struct_mutex
);
1084 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1085 pm_ier
= I915_READ(GEN6_PMIER
);
1086 pm_imr
= I915_READ(GEN6_PMIMR
);
1087 pm_isr
= I915_READ(GEN6_PMISR
);
1088 pm_iir
= I915_READ(GEN6_PMIIR
);
1089 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1091 pm_ier
= I915_READ(GEN8_GT_IER(2));
1092 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1093 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1094 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1095 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1097 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1098 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1099 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1100 seq_printf(m
, "Render p-state ratio: %d\n",
1101 (gt_perf_status
& 0xff00) >> 8);
1102 seq_printf(m
, "Render p-state VID: %d\n",
1103 gt_perf_status
& 0xff);
1104 seq_printf(m
, "Render p-state limit: %d\n",
1105 rp_state_limits
& 0xff);
1106 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1107 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1108 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1109 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1110 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1111 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1112 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1113 GEN6_CURICONT_MASK
);
1114 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1115 GEN6_CURBSYTAVG_MASK
);
1116 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1117 GEN6_CURBSYTAVG_MASK
);
1118 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1120 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1121 GEN6_CURBSYTAVG_MASK
);
1122 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1123 GEN6_CURBSYTAVG_MASK
);
1125 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1126 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1127 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1129 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1130 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1131 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1133 max_freq
= rp_state_cap
& 0xff;
1134 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1135 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1137 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1138 dev_priv
->rps
.max_freq
* GT_FREQUENCY_MULTIPLIER
);
1139 } else if (IS_VALLEYVIEW(dev
)) {
1142 mutex_lock(&dev_priv
->rps
.hw_lock
);
1143 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1144 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1145 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1147 seq_printf(m
, "max GPU freq: %d MHz\n",
1148 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1150 seq_printf(m
, "min GPU freq: %d MHz\n",
1151 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1153 seq_printf(m
, "efficient (RPe) frequency: %d MHz\n",
1154 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1156 seq_printf(m
, "current GPU freq: %d MHz\n",
1157 vlv_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1158 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1160 seq_puts(m
, "no P-state info available\n");
1164 intel_runtime_pm_put(dev_priv
);
1168 static int ironlake_drpc_info(struct seq_file
*m
)
1170 struct drm_info_node
*node
= m
->private;
1171 struct drm_device
*dev
= node
->minor
->dev
;
1172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1173 u32 rgvmodectl
, rstdbyctl
;
1177 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1180 intel_runtime_pm_get(dev_priv
);
1182 rgvmodectl
= I915_READ(MEMMODECTL
);
1183 rstdbyctl
= I915_READ(RSTDBYCTL
);
1184 crstandvid
= I915_READ16(CRSTANDVID
);
1186 intel_runtime_pm_put(dev_priv
);
1187 mutex_unlock(&dev
->struct_mutex
);
1189 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1191 seq_printf(m
, "Boost freq: %d\n",
1192 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1193 MEMMODE_BOOST_FREQ_SHIFT
);
1194 seq_printf(m
, "HW control enabled: %s\n",
1195 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1196 seq_printf(m
, "SW control enabled: %s\n",
1197 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1198 seq_printf(m
, "Gated voltage change: %s\n",
1199 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1200 seq_printf(m
, "Starting frequency: P%d\n",
1201 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1202 seq_printf(m
, "Max P-state: P%d\n",
1203 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1204 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1205 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1206 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1207 seq_printf(m
, "Render standby enabled: %s\n",
1208 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1209 seq_puts(m
, "Current RS state: ");
1210 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1212 seq_puts(m
, "on\n");
1214 case RSX_STATUS_RC1
:
1215 seq_puts(m
, "RC1\n");
1217 case RSX_STATUS_RC1E
:
1218 seq_puts(m
, "RC1E\n");
1220 case RSX_STATUS_RS1
:
1221 seq_puts(m
, "RS1\n");
1223 case RSX_STATUS_RS2
:
1224 seq_puts(m
, "RS2 (RC6)\n");
1226 case RSX_STATUS_RS3
:
1227 seq_puts(m
, "RC3 (RC6+)\n");
1230 seq_puts(m
, "unknown\n");
1237 static int vlv_drpc_info(struct seq_file
*m
)
1240 struct drm_info_node
*node
= m
->private;
1241 struct drm_device
*dev
= node
->minor
->dev
;
1242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1243 u32 rpmodectl1
, rcctl1
;
1244 unsigned fw_rendercount
= 0, fw_mediacount
= 0;
1246 intel_runtime_pm_get(dev_priv
);
1248 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1249 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1251 intel_runtime_pm_put(dev_priv
);
1253 seq_printf(m
, "Video Turbo Mode: %s\n",
1254 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1255 seq_printf(m
, "Turbo enabled: %s\n",
1256 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1257 seq_printf(m
, "HW control enabled: %s\n",
1258 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1259 seq_printf(m
, "SW control enabled: %s\n",
1260 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1261 GEN6_RP_MEDIA_SW_MODE
));
1262 seq_printf(m
, "RC6 Enabled: %s\n",
1263 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1264 GEN6_RC_CTL_EI_MODE(1))));
1265 seq_printf(m
, "Render Power Well: %s\n",
1266 (I915_READ(VLV_GTLC_PW_STATUS
) &
1267 VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1268 seq_printf(m
, "Media Power Well: %s\n",
1269 (I915_READ(VLV_GTLC_PW_STATUS
) &
1270 VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1272 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1273 I915_READ(VLV_GT_RENDER_RC6
));
1274 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1275 I915_READ(VLV_GT_MEDIA_RC6
));
1277 spin_lock_irq(&dev_priv
->uncore
.lock
);
1278 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1279 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1280 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1282 seq_printf(m
, "Forcewake Render Count = %u\n", fw_rendercount
);
1283 seq_printf(m
, "Forcewake Media Count = %u\n", fw_mediacount
);
1290 static int gen6_drpc_info(struct seq_file
*m
)
1293 struct drm_info_node
*node
= m
->private;
1294 struct drm_device
*dev
= node
->minor
->dev
;
1295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1296 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1297 unsigned forcewake_count
;
1300 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1303 intel_runtime_pm_get(dev_priv
);
1305 spin_lock_irq(&dev_priv
->uncore
.lock
);
1306 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1307 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1309 if (forcewake_count
) {
1310 seq_puts(m
, "RC information inaccurate because somebody "
1311 "holds a forcewake reference \n");
1313 /* NB: we cannot use forcewake, else we read the wrong values */
1314 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1316 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1319 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1320 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1322 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1323 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1324 mutex_unlock(&dev
->struct_mutex
);
1325 mutex_lock(&dev_priv
->rps
.hw_lock
);
1326 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1327 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1329 intel_runtime_pm_put(dev_priv
);
1331 seq_printf(m
, "Video Turbo Mode: %s\n",
1332 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1333 seq_printf(m
, "HW control enabled: %s\n",
1334 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1335 seq_printf(m
, "SW control enabled: %s\n",
1336 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1337 GEN6_RP_MEDIA_SW_MODE
));
1338 seq_printf(m
, "RC1e Enabled: %s\n",
1339 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1340 seq_printf(m
, "RC6 Enabled: %s\n",
1341 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1342 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1343 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1344 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1345 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1346 seq_puts(m
, "Current RC state: ");
1347 switch (gt_core_status
& GEN6_RCn_MASK
) {
1349 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1350 seq_puts(m
, "Core Power Down\n");
1352 seq_puts(m
, "on\n");
1355 seq_puts(m
, "RC3\n");
1358 seq_puts(m
, "RC6\n");
1361 seq_puts(m
, "RC7\n");
1364 seq_puts(m
, "Unknown\n");
1368 seq_printf(m
, "Core Power Down: %s\n",
1369 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1371 /* Not exactly sure what this is */
1372 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1373 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1374 seq_printf(m
, "RC6 residency since boot: %u\n",
1375 I915_READ(GEN6_GT_GFX_RC6
));
1376 seq_printf(m
, "RC6+ residency since boot: %u\n",
1377 I915_READ(GEN6_GT_GFX_RC6p
));
1378 seq_printf(m
, "RC6++ residency since boot: %u\n",
1379 I915_READ(GEN6_GT_GFX_RC6pp
));
1381 seq_printf(m
, "RC6 voltage: %dmV\n",
1382 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1383 seq_printf(m
, "RC6+ voltage: %dmV\n",
1384 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1385 seq_printf(m
, "RC6++ voltage: %dmV\n",
1386 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1390 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1392 struct drm_info_node
*node
= m
->private;
1393 struct drm_device
*dev
= node
->minor
->dev
;
1395 if (IS_VALLEYVIEW(dev
))
1396 return vlv_drpc_info(m
);
1397 else if (INTEL_INFO(dev
)->gen
>= 6)
1398 return gen6_drpc_info(m
);
1400 return ironlake_drpc_info(m
);
1403 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1405 struct drm_info_node
*node
= m
->private;
1406 struct drm_device
*dev
= node
->minor
->dev
;
1407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1409 if (!HAS_FBC(dev
)) {
1410 seq_puts(m
, "FBC unsupported on this chipset\n");
1414 intel_runtime_pm_get(dev_priv
);
1416 if (intel_fbc_enabled(dev
)) {
1417 seq_puts(m
, "FBC enabled\n");
1419 seq_puts(m
, "FBC disabled: ");
1420 switch (dev_priv
->fbc
.no_fbc_reason
) {
1422 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1424 case FBC_UNSUPPORTED
:
1425 seq_puts(m
, "unsupported by this chipset");
1428 seq_puts(m
, "no outputs");
1430 case FBC_STOLEN_TOO_SMALL
:
1431 seq_puts(m
, "not enough stolen memory");
1433 case FBC_UNSUPPORTED_MODE
:
1434 seq_puts(m
, "mode not supported");
1436 case FBC_MODE_TOO_LARGE
:
1437 seq_puts(m
, "mode too large");
1440 seq_puts(m
, "FBC unsupported on plane");
1443 seq_puts(m
, "scanout buffer not tiled");
1445 case FBC_MULTIPLE_PIPES
:
1446 seq_puts(m
, "multiple pipes are enabled");
1448 case FBC_MODULE_PARAM
:
1449 seq_puts(m
, "disabled per module param (default off)");
1451 case FBC_CHIP_DEFAULT
:
1452 seq_puts(m
, "disabled per chip default");
1455 seq_puts(m
, "unknown reason");
1460 intel_runtime_pm_put(dev_priv
);
1465 static int i915_fbc_fc_get(void *data
, u64
*val
)
1467 struct drm_device
*dev
= data
;
1468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1470 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1473 drm_modeset_lock_all(dev
);
1474 *val
= dev_priv
->fbc
.false_color
;
1475 drm_modeset_unlock_all(dev
);
1480 static int i915_fbc_fc_set(void *data
, u64 val
)
1482 struct drm_device
*dev
= data
;
1483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1489 drm_modeset_lock_all(dev
);
1491 reg
= I915_READ(ILK_DPFC_CONTROL
);
1492 dev_priv
->fbc
.false_color
= val
;
1494 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1495 (reg
| FBC_CTL_FALSE_COLOR
) :
1496 (reg
& ~FBC_CTL_FALSE_COLOR
));
1498 drm_modeset_unlock_all(dev
);
1502 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1503 i915_fbc_fc_get
, i915_fbc_fc_set
,
1506 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1508 struct drm_info_node
*node
= m
->private;
1509 struct drm_device
*dev
= node
->minor
->dev
;
1510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 if (!HAS_IPS(dev
)) {
1513 seq_puts(m
, "not supported\n");
1517 intel_runtime_pm_get(dev_priv
);
1519 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1520 yesno(i915
.enable_ips
));
1522 if (INTEL_INFO(dev
)->gen
>= 8) {
1523 seq_puts(m
, "Currently: unknown\n");
1525 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1526 seq_puts(m
, "Currently: enabled\n");
1528 seq_puts(m
, "Currently: disabled\n");
1531 intel_runtime_pm_put(dev_priv
);
1536 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1538 struct drm_info_node
*node
= m
->private;
1539 struct drm_device
*dev
= node
->minor
->dev
;
1540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1541 bool sr_enabled
= false;
1543 intel_runtime_pm_get(dev_priv
);
1545 if (HAS_PCH_SPLIT(dev
))
1546 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1547 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1548 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1549 else if (IS_I915GM(dev
))
1550 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1551 else if (IS_PINEVIEW(dev
))
1552 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1554 intel_runtime_pm_put(dev_priv
);
1556 seq_printf(m
, "self-refresh: %s\n",
1557 sr_enabled
? "enabled" : "disabled");
1562 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1564 struct drm_info_node
*node
= m
->private;
1565 struct drm_device
*dev
= node
->minor
->dev
;
1566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1567 unsigned long temp
, chipset
, gfx
;
1573 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1577 temp
= i915_mch_val(dev_priv
);
1578 chipset
= i915_chipset_val(dev_priv
);
1579 gfx
= i915_gfx_val(dev_priv
);
1580 mutex_unlock(&dev
->struct_mutex
);
1582 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1583 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1584 seq_printf(m
, "GFX power: %ld\n", gfx
);
1585 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1590 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1592 struct drm_info_node
*node
= m
->private;
1593 struct drm_device
*dev
= node
->minor
->dev
;
1594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1596 int gpu_freq
, ia_freq
;
1598 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1599 seq_puts(m
, "unsupported on this chipset\n");
1603 intel_runtime_pm_get(dev_priv
);
1605 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1607 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1611 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1613 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1614 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1617 sandybridge_pcode_read(dev_priv
,
1618 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1620 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1621 gpu_freq
* GT_FREQUENCY_MULTIPLIER
,
1622 ((ia_freq
>> 0) & 0xff) * 100,
1623 ((ia_freq
>> 8) & 0xff) * 100);
1626 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1629 intel_runtime_pm_put(dev_priv
);
1633 static int i915_opregion(struct seq_file
*m
, void *unused
)
1635 struct drm_info_node
*node
= m
->private;
1636 struct drm_device
*dev
= node
->minor
->dev
;
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1638 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1639 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1645 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1649 if (opregion
->header
) {
1650 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1651 seq_write(m
, data
, OPREGION_SIZE
);
1654 mutex_unlock(&dev
->struct_mutex
);
1661 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1663 struct drm_info_node
*node
= m
->private;
1664 struct drm_device
*dev
= node
->minor
->dev
;
1665 struct intel_fbdev
*ifbdev
= NULL
;
1666 struct intel_framebuffer
*fb
;
1668 #ifdef CONFIG_DRM_I915_FBDEV
1669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1671 ifbdev
= dev_priv
->fbdev
;
1672 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1674 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1678 fb
->base
.bits_per_pixel
,
1679 atomic_read(&fb
->base
.refcount
.refcount
));
1680 describe_obj(m
, fb
->obj
);
1684 mutex_lock(&dev
->mode_config
.fb_lock
);
1685 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1686 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1689 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1693 fb
->base
.bits_per_pixel
,
1694 atomic_read(&fb
->base
.refcount
.refcount
));
1695 describe_obj(m
, fb
->obj
);
1698 mutex_unlock(&dev
->mode_config
.fb_lock
);
1703 static void describe_ctx_ringbuf(struct seq_file
*m
,
1704 struct intel_ringbuffer
*ringbuf
)
1706 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1707 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1708 ringbuf
->last_retired_head
);
1711 static int i915_context_status(struct seq_file
*m
, void *unused
)
1713 struct drm_info_node
*node
= m
->private;
1714 struct drm_device
*dev
= node
->minor
->dev
;
1715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1716 struct intel_engine_cs
*ring
;
1717 struct intel_context
*ctx
;
1720 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1724 if (dev_priv
->ips
.pwrctx
) {
1725 seq_puts(m
, "power context ");
1726 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1730 if (dev_priv
->ips
.renderctx
) {
1731 seq_puts(m
, "render context ");
1732 describe_obj(m
, dev_priv
->ips
.renderctx
);
1736 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1737 if (!i915
.enable_execlists
&&
1738 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1741 seq_puts(m
, "HW context ");
1742 describe_ctx(m
, ctx
);
1743 for_each_ring(ring
, dev_priv
, i
) {
1744 if (ring
->default_context
== ctx
)
1745 seq_printf(m
, "(default context %s) ",
1749 if (i915
.enable_execlists
) {
1751 for_each_ring(ring
, dev_priv
, i
) {
1752 struct drm_i915_gem_object
*ctx_obj
=
1753 ctx
->engine
[i
].state
;
1754 struct intel_ringbuffer
*ringbuf
=
1755 ctx
->engine
[i
].ringbuf
;
1757 seq_printf(m
, "%s: ", ring
->name
);
1759 describe_obj(m
, ctx_obj
);
1761 describe_ctx_ringbuf(m
, ringbuf
);
1765 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1771 mutex_unlock(&dev
->struct_mutex
);
1776 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1778 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1779 struct drm_device
*dev
= node
->minor
->dev
;
1780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1781 struct intel_engine_cs
*ring
;
1782 struct intel_context
*ctx
;
1785 if (!i915
.enable_execlists
) {
1786 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1790 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1794 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1795 for_each_ring(ring
, dev_priv
, i
) {
1796 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
1798 if (ring
->default_context
== ctx
)
1802 struct page
*page
= i915_gem_object_get_page(ctx_obj
, 1);
1803 uint32_t *reg_state
= kmap_atomic(page
);
1806 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1807 intel_execlists_ctx_id(ctx_obj
));
1809 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1810 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1811 i915_gem_obj_ggtt_offset(ctx_obj
) + 4096 + (j
* 4),
1812 reg_state
[j
], reg_state
[j
+ 1],
1813 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1815 kunmap_atomic(reg_state
);
1822 mutex_unlock(&dev
->struct_mutex
);
1827 static int i915_execlists(struct seq_file
*m
, void *data
)
1829 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1830 struct drm_device
*dev
= node
->minor
->dev
;
1831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1832 struct intel_engine_cs
*ring
;
1838 struct list_head
*cursor
;
1842 if (!i915
.enable_execlists
) {
1843 seq_puts(m
, "Logical Ring Contexts are disabled\n");
1847 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1851 intel_runtime_pm_get(dev_priv
);
1853 for_each_ring(ring
, dev_priv
, ring_id
) {
1854 struct intel_ctx_submit_request
*head_req
= NULL
;
1856 unsigned long flags
;
1858 seq_printf(m
, "%s\n", ring
->name
);
1860 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
1861 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
1862 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
1865 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
1866 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
1868 read_pointer
= ring
->next_context_status_buffer
;
1869 write_pointer
= status_pointer
& 0x07;
1870 if (read_pointer
> write_pointer
)
1872 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1873 read_pointer
, write_pointer
);
1875 for (i
= 0; i
< 6; i
++) {
1876 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
1877 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
1879 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
1883 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
1884 list_for_each(cursor
, &ring
->execlist_queue
)
1886 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
1887 struct intel_ctx_submit_request
, execlist_link
);
1888 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
1890 seq_printf(m
, "\t%d requests in queue\n", count
);
1892 struct drm_i915_gem_object
*ctx_obj
;
1894 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
1895 seq_printf(m
, "\tHead request id: %u\n",
1896 intel_execlists_ctx_id(ctx_obj
));
1897 seq_printf(m
, "\tHead request tail: %u\n",
1904 intel_runtime_pm_put(dev_priv
);
1905 mutex_unlock(&dev
->struct_mutex
);
1910 static int i915_gen6_forcewake_count_info(struct seq_file
*m
, void *data
)
1912 struct drm_info_node
*node
= m
->private;
1913 struct drm_device
*dev
= node
->minor
->dev
;
1914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1915 unsigned forcewake_count
= 0, fw_rendercount
= 0, fw_mediacount
= 0;
1917 spin_lock_irq(&dev_priv
->uncore
.lock
);
1918 if (IS_VALLEYVIEW(dev
)) {
1919 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1920 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1922 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1923 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1925 if (IS_VALLEYVIEW(dev
)) {
1926 seq_printf(m
, "fw_rendercount = %u\n", fw_rendercount
);
1927 seq_printf(m
, "fw_mediacount = %u\n", fw_mediacount
);
1929 seq_printf(m
, "forcewake count = %u\n", forcewake_count
);
1934 static const char *swizzle_string(unsigned swizzle
)
1937 case I915_BIT_6_SWIZZLE_NONE
:
1939 case I915_BIT_6_SWIZZLE_9
:
1941 case I915_BIT_6_SWIZZLE_9_10
:
1942 return "bit9/bit10";
1943 case I915_BIT_6_SWIZZLE_9_11
:
1944 return "bit9/bit11";
1945 case I915_BIT_6_SWIZZLE_9_10_11
:
1946 return "bit9/bit10/bit11";
1947 case I915_BIT_6_SWIZZLE_9_17
:
1948 return "bit9/bit17";
1949 case I915_BIT_6_SWIZZLE_9_10_17
:
1950 return "bit9/bit10/bit17";
1951 case I915_BIT_6_SWIZZLE_UNKNOWN
:
1958 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
1960 struct drm_info_node
*node
= m
->private;
1961 struct drm_device
*dev
= node
->minor
->dev
;
1962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1965 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1968 intel_runtime_pm_get(dev_priv
);
1970 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
1971 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
1972 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
1973 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
1975 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
1976 seq_printf(m
, "DDC = 0x%08x\n",
1978 seq_printf(m
, "C0DRB3 = 0x%04x\n",
1979 I915_READ16(C0DRB3
));
1980 seq_printf(m
, "C1DRB3 = 0x%04x\n",
1981 I915_READ16(C1DRB3
));
1982 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1983 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
1984 I915_READ(MAD_DIMM_C0
));
1985 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
1986 I915_READ(MAD_DIMM_C1
));
1987 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
1988 I915_READ(MAD_DIMM_C2
));
1989 seq_printf(m
, "TILECTL = 0x%08x\n",
1990 I915_READ(TILECTL
));
1991 if (INTEL_INFO(dev
)->gen
>= 8)
1992 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
1993 I915_READ(GAMTARBMODE
));
1995 seq_printf(m
, "ARB_MODE = 0x%08x\n",
1996 I915_READ(ARB_MODE
));
1997 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
1998 I915_READ(DISP_ARB_CTL
));
2000 intel_runtime_pm_put(dev_priv
);
2001 mutex_unlock(&dev
->struct_mutex
);
2006 static int per_file_ctx(int id
, void *ptr
, void *data
)
2008 struct intel_context
*ctx
= ptr
;
2009 struct seq_file
*m
= data
;
2010 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2013 seq_printf(m
, " no ppgtt for context %d\n",
2018 if (i915_gem_context_is_default(ctx
))
2019 seq_puts(m
, " default context:\n");
2021 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2022 ppgtt
->debug_dump(ppgtt
, m
);
2027 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2030 struct intel_engine_cs
*ring
;
2031 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2037 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
2038 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
2039 for_each_ring(ring
, dev_priv
, unused
) {
2040 seq_printf(m
, "%s\n", ring
->name
);
2041 for (i
= 0; i
< 4; i
++) {
2042 u32 offset
= 0x270 + i
* 8;
2043 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2045 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2046 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2051 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2054 struct intel_engine_cs
*ring
;
2055 struct drm_file
*file
;
2058 if (INTEL_INFO(dev
)->gen
== 6)
2059 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2061 for_each_ring(ring
, dev_priv
, i
) {
2062 seq_printf(m
, "%s\n", ring
->name
);
2063 if (INTEL_INFO(dev
)->gen
== 7)
2064 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2065 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2066 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2067 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2069 if (dev_priv
->mm
.aliasing_ppgtt
) {
2070 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2072 seq_puts(m
, "aliasing PPGTT:\n");
2073 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
2075 ppgtt
->debug_dump(ppgtt
, m
);
2078 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2079 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2081 seq_printf(m
, "proc: %s\n",
2082 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2083 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2085 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2088 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2090 struct drm_info_node
*node
= m
->private;
2091 struct drm_device
*dev
= node
->minor
->dev
;
2092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2094 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2097 intel_runtime_pm_get(dev_priv
);
2099 if (INTEL_INFO(dev
)->gen
>= 8)
2100 gen8_ppgtt_info(m
, dev
);
2101 else if (INTEL_INFO(dev
)->gen
>= 6)
2102 gen6_ppgtt_info(m
, dev
);
2104 intel_runtime_pm_put(dev_priv
);
2105 mutex_unlock(&dev
->struct_mutex
);
2110 static int i915_llc(struct seq_file
*m
, void *data
)
2112 struct drm_info_node
*node
= m
->private;
2113 struct drm_device
*dev
= node
->minor
->dev
;
2114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2116 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2117 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2118 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2123 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2125 struct drm_info_node
*node
= m
->private;
2126 struct drm_device
*dev
= node
->minor
->dev
;
2127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2129 bool enabled
= false;
2131 intel_runtime_pm_get(dev_priv
);
2133 mutex_lock(&dev_priv
->psr
.lock
);
2134 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2135 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2136 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2137 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2138 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2139 dev_priv
->psr
.busy_frontbuffer_bits
);
2140 seq_printf(m
, "Re-enable work scheduled: %s\n",
2141 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2143 enabled
= HAS_PSR(dev
) &&
2144 I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2145 seq_printf(m
, "HW Enabled & Active bit: %s\n", yesno(enabled
));
2148 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2149 EDP_PSR_PERF_CNT_MASK
;
2150 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2151 mutex_unlock(&dev_priv
->psr
.lock
);
2153 intel_runtime_pm_put(dev_priv
);
2157 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2159 struct drm_info_node
*node
= m
->private;
2160 struct drm_device
*dev
= node
->minor
->dev
;
2161 struct intel_encoder
*encoder
;
2162 struct intel_connector
*connector
;
2163 struct intel_dp
*intel_dp
= NULL
;
2167 drm_modeset_lock_all(dev
);
2168 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
2171 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2174 if (!connector
->base
.encoder
)
2177 encoder
= to_intel_encoder(connector
->base
.encoder
);
2178 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2181 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2183 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2187 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2188 crc
[0], crc
[1], crc
[2],
2189 crc
[3], crc
[4], crc
[5]);
2194 drm_modeset_unlock_all(dev
);
2198 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2200 struct drm_info_node
*node
= m
->private;
2201 struct drm_device
*dev
= node
->minor
->dev
;
2202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2206 if (INTEL_INFO(dev
)->gen
< 6)
2209 intel_runtime_pm_get(dev_priv
);
2211 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2212 power
= (power
& 0x1f00) >> 8;
2213 units
= 1000000 / (1 << power
); /* convert to uJ */
2214 power
= I915_READ(MCH_SECP_NRG_STTS
);
2217 intel_runtime_pm_put(dev_priv
);
2219 seq_printf(m
, "%llu", (long long unsigned)power
);
2224 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2226 struct drm_info_node
*node
= m
->private;
2227 struct drm_device
*dev
= node
->minor
->dev
;
2228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2230 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2231 seq_puts(m
, "not supported\n");
2235 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2236 seq_printf(m
, "IRQs disabled: %s\n",
2237 yesno(!intel_irqs_enabled(dev_priv
)));
2242 static const char *power_domain_str(enum intel_display_power_domain domain
)
2245 case POWER_DOMAIN_PIPE_A
:
2247 case POWER_DOMAIN_PIPE_B
:
2249 case POWER_DOMAIN_PIPE_C
:
2251 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2252 return "PIPE_A_PANEL_FITTER";
2253 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2254 return "PIPE_B_PANEL_FITTER";
2255 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2256 return "PIPE_C_PANEL_FITTER";
2257 case POWER_DOMAIN_TRANSCODER_A
:
2258 return "TRANSCODER_A";
2259 case POWER_DOMAIN_TRANSCODER_B
:
2260 return "TRANSCODER_B";
2261 case POWER_DOMAIN_TRANSCODER_C
:
2262 return "TRANSCODER_C";
2263 case POWER_DOMAIN_TRANSCODER_EDP
:
2264 return "TRANSCODER_EDP";
2265 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2266 return "PORT_DDI_A_2_LANES";
2267 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2268 return "PORT_DDI_A_4_LANES";
2269 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2270 return "PORT_DDI_B_2_LANES";
2271 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2272 return "PORT_DDI_B_4_LANES";
2273 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2274 return "PORT_DDI_C_2_LANES";
2275 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2276 return "PORT_DDI_C_4_LANES";
2277 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2278 return "PORT_DDI_D_2_LANES";
2279 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2280 return "PORT_DDI_D_4_LANES";
2281 case POWER_DOMAIN_PORT_DSI
:
2283 case POWER_DOMAIN_PORT_CRT
:
2285 case POWER_DOMAIN_PORT_OTHER
:
2286 return "PORT_OTHER";
2287 case POWER_DOMAIN_VGA
:
2289 case POWER_DOMAIN_AUDIO
:
2291 case POWER_DOMAIN_PLLS
:
2293 case POWER_DOMAIN_INIT
:
2301 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2303 struct drm_info_node
*node
= m
->private;
2304 struct drm_device
*dev
= node
->minor
->dev
;
2305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2306 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2309 mutex_lock(&power_domains
->lock
);
2311 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2312 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2313 struct i915_power_well
*power_well
;
2314 enum intel_display_power_domain power_domain
;
2316 power_well
= &power_domains
->power_wells
[i
];
2317 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2320 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2322 if (!(BIT(power_domain
) & power_well
->domains
))
2325 seq_printf(m
, " %-23s %d\n",
2326 power_domain_str(power_domain
),
2327 power_domains
->domain_use_count
[power_domain
]);
2331 mutex_unlock(&power_domains
->lock
);
2336 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2337 struct drm_display_mode
*mode
)
2341 for (i
= 0; i
< tabs
; i
++)
2344 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2345 mode
->base
.id
, mode
->name
,
2346 mode
->vrefresh
, mode
->clock
,
2347 mode
->hdisplay
, mode
->hsync_start
,
2348 mode
->hsync_end
, mode
->htotal
,
2349 mode
->vdisplay
, mode
->vsync_start
,
2350 mode
->vsync_end
, mode
->vtotal
,
2351 mode
->type
, mode
->flags
);
2354 static void intel_encoder_info(struct seq_file
*m
,
2355 struct intel_crtc
*intel_crtc
,
2356 struct intel_encoder
*intel_encoder
)
2358 struct drm_info_node
*node
= m
->private;
2359 struct drm_device
*dev
= node
->minor
->dev
;
2360 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2361 struct intel_connector
*intel_connector
;
2362 struct drm_encoder
*encoder
;
2364 encoder
= &intel_encoder
->base
;
2365 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2366 encoder
->base
.id
, encoder
->name
);
2367 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2368 struct drm_connector
*connector
= &intel_connector
->base
;
2369 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2372 drm_get_connector_status_name(connector
->status
));
2373 if (connector
->status
== connector_status_connected
) {
2374 struct drm_display_mode
*mode
= &crtc
->mode
;
2375 seq_printf(m
, ", mode:\n");
2376 intel_seq_print_mode(m
, 2, mode
);
2383 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2385 struct drm_info_node
*node
= m
->private;
2386 struct drm_device
*dev
= node
->minor
->dev
;
2387 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2388 struct intel_encoder
*intel_encoder
;
2390 if (crtc
->primary
->fb
)
2391 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2392 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2393 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2395 seq_puts(m
, "\tprimary plane disabled\n");
2396 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2397 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2400 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2402 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2404 seq_printf(m
, "\tfixed mode:\n");
2405 intel_seq_print_mode(m
, 2, mode
);
2408 static void intel_dp_info(struct seq_file
*m
,
2409 struct intel_connector
*intel_connector
)
2411 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2412 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2414 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2415 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2417 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2418 intel_panel_info(m
, &intel_connector
->panel
);
2421 static void intel_hdmi_info(struct seq_file
*m
,
2422 struct intel_connector
*intel_connector
)
2424 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2425 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2427 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2431 static void intel_lvds_info(struct seq_file
*m
,
2432 struct intel_connector
*intel_connector
)
2434 intel_panel_info(m
, &intel_connector
->panel
);
2437 static void intel_connector_info(struct seq_file
*m
,
2438 struct drm_connector
*connector
)
2440 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2441 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2442 struct drm_display_mode
*mode
;
2444 seq_printf(m
, "connector %d: type %s, status: %s\n",
2445 connector
->base
.id
, connector
->name
,
2446 drm_get_connector_status_name(connector
->status
));
2447 if (connector
->status
== connector_status_connected
) {
2448 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2449 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2450 connector
->display_info
.width_mm
,
2451 connector
->display_info
.height_mm
);
2452 seq_printf(m
, "\tsubpixel order: %s\n",
2453 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2454 seq_printf(m
, "\tCEA rev: %d\n",
2455 connector
->display_info
.cea_rev
);
2457 if (intel_encoder
) {
2458 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2459 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2460 intel_dp_info(m
, intel_connector
);
2461 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2462 intel_hdmi_info(m
, intel_connector
);
2463 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2464 intel_lvds_info(m
, intel_connector
);
2467 seq_printf(m
, "\tmodes:\n");
2468 list_for_each_entry(mode
, &connector
->modes
, head
)
2469 intel_seq_print_mode(m
, 2, mode
);
2472 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2477 if (IS_845G(dev
) || IS_I865G(dev
))
2478 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2480 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2485 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2490 pos
= I915_READ(CURPOS(pipe
));
2492 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2493 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2496 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2497 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2500 return cursor_active(dev
, pipe
);
2503 static int i915_display_info(struct seq_file
*m
, void *unused
)
2505 struct drm_info_node
*node
= m
->private;
2506 struct drm_device
*dev
= node
->minor
->dev
;
2507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2508 struct intel_crtc
*crtc
;
2509 struct drm_connector
*connector
;
2511 intel_runtime_pm_get(dev_priv
);
2512 drm_modeset_lock_all(dev
);
2513 seq_printf(m
, "CRTC info\n");
2514 seq_printf(m
, "---------\n");
2515 for_each_intel_crtc(dev
, crtc
) {
2519 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2520 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2521 yesno(crtc
->active
), crtc
->config
.pipe_src_w
, crtc
->config
.pipe_src_h
);
2523 intel_crtc_info(m
, crtc
);
2525 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2526 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2527 yesno(crtc
->cursor_base
),
2528 x
, y
, crtc
->cursor_width
, crtc
->cursor_height
,
2529 crtc
->cursor_addr
, yesno(active
));
2532 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2533 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2534 yesno(!crtc
->pch_fifo_underrun_disabled
));
2537 seq_printf(m
, "\n");
2538 seq_printf(m
, "Connector info\n");
2539 seq_printf(m
, "--------------\n");
2540 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2541 intel_connector_info(m
, connector
);
2543 drm_modeset_unlock_all(dev
);
2544 intel_runtime_pm_put(dev_priv
);
2549 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2551 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2552 struct drm_device
*dev
= node
->minor
->dev
;
2553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2554 struct intel_engine_cs
*ring
;
2555 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2558 if (!i915_semaphore_is_enabled(dev
)) {
2559 seq_puts(m
, "Semaphores are disabled\n");
2563 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2566 intel_runtime_pm_get(dev_priv
);
2568 if (IS_BROADWELL(dev
)) {
2572 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2574 seqno
= (uint64_t *)kmap_atomic(page
);
2575 for_each_ring(ring
, dev_priv
, i
) {
2578 seq_printf(m
, "%s\n", ring
->name
);
2580 seq_puts(m
, " Last signal:");
2581 for (j
= 0; j
< num_rings
; j
++) {
2582 offset
= i
* I915_NUM_RINGS
+ j
;
2583 seq_printf(m
, "0x%08llx (0x%02llx) ",
2584 seqno
[offset
], offset
* 8);
2588 seq_puts(m
, " Last wait: ");
2589 for (j
= 0; j
< num_rings
; j
++) {
2590 offset
= i
+ (j
* I915_NUM_RINGS
);
2591 seq_printf(m
, "0x%08llx (0x%02llx) ",
2592 seqno
[offset
], offset
* 8);
2597 kunmap_atomic(seqno
);
2599 seq_puts(m
, " Last signal:");
2600 for_each_ring(ring
, dev_priv
, i
)
2601 for (j
= 0; j
< num_rings
; j
++)
2602 seq_printf(m
, "0x%08x\n",
2603 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2607 seq_puts(m
, "\nSync seqno:\n");
2608 for_each_ring(ring
, dev_priv
, i
) {
2609 for (j
= 0; j
< num_rings
; j
++) {
2610 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2616 intel_runtime_pm_put(dev_priv
);
2617 mutex_unlock(&dev
->struct_mutex
);
2621 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2623 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2624 struct drm_device
*dev
= node
->minor
->dev
;
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2628 drm_modeset_lock_all(dev
);
2629 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2630 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2632 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2633 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2634 pll
->crtc_mask
, pll
->active
, yesno(pll
->on
));
2635 seq_printf(m
, " tracked hardware state:\n");
2636 seq_printf(m
, " dpll: 0x%08x\n", pll
->hw_state
.dpll
);
2637 seq_printf(m
, " dpll_md: 0x%08x\n", pll
->hw_state
.dpll_md
);
2638 seq_printf(m
, " fp0: 0x%08x\n", pll
->hw_state
.fp0
);
2639 seq_printf(m
, " fp1: 0x%08x\n", pll
->hw_state
.fp1
);
2640 seq_printf(m
, " wrpll: 0x%08x\n", pll
->hw_state
.wrpll
);
2642 drm_modeset_unlock_all(dev
);
2647 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
2651 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2652 struct drm_device
*dev
= node
->minor
->dev
;
2653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2655 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2659 intel_runtime_pm_get(dev_priv
);
2661 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
2662 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
2663 u32 addr
, mask
, value
, read
;
2666 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
2667 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
2668 value
= dev_priv
->workarounds
.reg
[i
].value
;
2669 read
= I915_READ(addr
);
2670 ok
= (value
& mask
) == (read
& mask
);
2671 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2672 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
2675 intel_runtime_pm_put(dev_priv
);
2676 mutex_unlock(&dev
->struct_mutex
);
2681 struct pipe_crc_info
{
2683 struct drm_device
*dev
;
2687 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
2689 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2690 struct drm_device
*dev
= node
->minor
->dev
;
2691 struct drm_encoder
*encoder
;
2692 struct intel_encoder
*intel_encoder
;
2693 struct intel_digital_port
*intel_dig_port
;
2694 drm_modeset_lock_all(dev
);
2695 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2696 intel_encoder
= to_intel_encoder(encoder
);
2697 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
2699 intel_dig_port
= enc_to_dig_port(encoder
);
2700 if (!intel_dig_port
->dp
.can_mst
)
2703 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
2705 drm_modeset_unlock_all(dev
);
2709 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2711 struct pipe_crc_info
*info
= inode
->i_private
;
2712 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2713 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2715 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2718 spin_lock_irq(&pipe_crc
->lock
);
2720 if (pipe_crc
->opened
) {
2721 spin_unlock_irq(&pipe_crc
->lock
);
2722 return -EBUSY
; /* already open */
2725 pipe_crc
->opened
= true;
2726 filep
->private_data
= inode
->i_private
;
2728 spin_unlock_irq(&pipe_crc
->lock
);
2733 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2735 struct pipe_crc_info
*info
= inode
->i_private
;
2736 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2737 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2739 spin_lock_irq(&pipe_crc
->lock
);
2740 pipe_crc
->opened
= false;
2741 spin_unlock_irq(&pipe_crc
->lock
);
2746 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2747 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2748 /* account for \'0' */
2749 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2751 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2753 assert_spin_locked(&pipe_crc
->lock
);
2754 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2755 INTEL_PIPE_CRC_ENTRIES_NR
);
2759 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2762 struct pipe_crc_info
*info
= filep
->private_data
;
2763 struct drm_device
*dev
= info
->dev
;
2764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2765 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2766 char buf
[PIPE_CRC_BUFFER_LEN
];
2767 int head
, tail
, n_entries
, n
;
2771 * Don't allow user space to provide buffers not big enough to hold
2774 if (count
< PIPE_CRC_LINE_LEN
)
2777 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2780 /* nothing to read */
2781 spin_lock_irq(&pipe_crc
->lock
);
2782 while (pipe_crc_data_count(pipe_crc
) == 0) {
2785 if (filep
->f_flags
& O_NONBLOCK
) {
2786 spin_unlock_irq(&pipe_crc
->lock
);
2790 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2791 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2793 spin_unlock_irq(&pipe_crc
->lock
);
2798 /* We now have one or more entries to read */
2799 head
= pipe_crc
->head
;
2800 tail
= pipe_crc
->tail
;
2801 n_entries
= min((size_t)CIRC_CNT(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
),
2802 count
/ PIPE_CRC_LINE_LEN
);
2803 spin_unlock_irq(&pipe_crc
->lock
);
2808 struct intel_pipe_crc_entry
*entry
= &pipe_crc
->entries
[tail
];
2811 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
2812 "%8u %8x %8x %8x %8x %8x\n",
2813 entry
->frame
, entry
->crc
[0],
2814 entry
->crc
[1], entry
->crc
[2],
2815 entry
->crc
[3], entry
->crc
[4]);
2817 ret
= copy_to_user(user_buf
+ n
* PIPE_CRC_LINE_LEN
,
2818 buf
, PIPE_CRC_LINE_LEN
);
2819 if (ret
== PIPE_CRC_LINE_LEN
)
2822 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
2823 tail
= (tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
2825 } while (--n_entries
);
2827 spin_lock_irq(&pipe_crc
->lock
);
2828 pipe_crc
->tail
= tail
;
2829 spin_unlock_irq(&pipe_crc
->lock
);
2834 static const struct file_operations i915_pipe_crc_fops
= {
2835 .owner
= THIS_MODULE
,
2836 .open
= i915_pipe_crc_open
,
2837 .read
= i915_pipe_crc_read
,
2838 .release
= i915_pipe_crc_release
,
2841 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
2843 .name
= "i915_pipe_A_crc",
2847 .name
= "i915_pipe_B_crc",
2851 .name
= "i915_pipe_C_crc",
2856 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
2859 struct drm_device
*dev
= minor
->dev
;
2861 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
2864 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
2865 &i915_pipe_crc_fops
);
2869 return drm_add_fake_info_node(minor
, ent
, info
);
2872 static const char * const pipe_crc_sources
[] = {
2885 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
2887 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
2888 return pipe_crc_sources
[source
];
2891 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
2893 struct drm_device
*dev
= m
->private;
2894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2897 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
2898 seq_printf(m
, "%c %s\n", pipe_name(i
),
2899 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
2904 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
2906 struct drm_device
*dev
= inode
->i_private
;
2908 return single_open(file
, display_crc_ctl_show
, dev
);
2911 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2914 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2915 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2918 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2919 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
2921 case INTEL_PIPE_CRC_SOURCE_NONE
:
2931 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
2932 enum intel_pipe_crc_source
*source
)
2934 struct intel_encoder
*encoder
;
2935 struct intel_crtc
*crtc
;
2936 struct intel_digital_port
*dig_port
;
2939 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2941 drm_modeset_lock_all(dev
);
2942 for_each_intel_encoder(dev
, encoder
) {
2943 if (!encoder
->base
.crtc
)
2946 crtc
= to_intel_crtc(encoder
->base
.crtc
);
2948 if (crtc
->pipe
!= pipe
)
2951 switch (encoder
->type
) {
2952 case INTEL_OUTPUT_TVOUT
:
2953 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
2955 case INTEL_OUTPUT_DISPLAYPORT
:
2956 case INTEL_OUTPUT_EDP
:
2957 dig_port
= enc_to_dig_port(&encoder
->base
);
2958 switch (dig_port
->port
) {
2960 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
2963 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
2966 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
2969 WARN(1, "nonexisting DP port %c\n",
2970 port_name(dig_port
->port
));
2978 drm_modeset_unlock_all(dev
);
2983 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
2985 enum intel_pipe_crc_source
*source
,
2988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2989 bool need_stable_symbols
= false;
2991 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
2992 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
2998 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2999 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3001 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3002 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3003 need_stable_symbols
= true;
3005 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3006 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3007 need_stable_symbols
= true;
3009 case INTEL_PIPE_CRC_SOURCE_NONE
:
3017 * When the pipe CRC tap point is after the transcoders we need
3018 * to tweak symbol-level features to produce a deterministic series of
3019 * symbols for a given frame. We need to reset those features only once
3020 * a frame (instead of every nth symbol):
3021 * - DC-balance: used to ensure a better clock recovery from the data
3023 * - DisplayPort scrambling: used for EMI reduction
3025 if (need_stable_symbols
) {
3026 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3028 tmp
|= DC_BALANCE_RESET_VLV
;
3030 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3032 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3034 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3040 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3042 enum intel_pipe_crc_source
*source
,
3045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3046 bool need_stable_symbols
= false;
3048 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3049 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3055 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3056 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3058 case INTEL_PIPE_CRC_SOURCE_TV
:
3059 if (!SUPPORTS_TV(dev
))
3061 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3063 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3066 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3067 need_stable_symbols
= true;
3069 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3072 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3073 need_stable_symbols
= true;
3075 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3078 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3079 need_stable_symbols
= true;
3081 case INTEL_PIPE_CRC_SOURCE_NONE
:
3089 * When the pipe CRC tap point is after the transcoders we need
3090 * to tweak symbol-level features to produce a deterministic series of
3091 * symbols for a given frame. We need to reset those features only once
3092 * a frame (instead of every nth symbol):
3093 * - DC-balance: used to ensure a better clock recovery from the data
3095 * - DisplayPort scrambling: used for EMI reduction
3097 if (need_stable_symbols
) {
3098 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3100 WARN_ON(!IS_G4X(dev
));
3102 I915_WRITE(PORT_DFT_I9XX
,
3103 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3106 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3108 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3110 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3116 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3120 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3123 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3125 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3126 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3127 tmp
&= ~DC_BALANCE_RESET_VLV
;
3128 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3132 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3136 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3139 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3141 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3142 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3144 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3145 I915_WRITE(PORT_DFT_I9XX
,
3146 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3150 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3153 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3154 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3157 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3158 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3160 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3161 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3163 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3164 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3166 case INTEL_PIPE_CRC_SOURCE_NONE
:
3176 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3179 struct intel_crtc
*crtc
=
3180 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3182 drm_modeset_lock_all(dev
);
3184 * If we use the eDP transcoder we need to make sure that we don't
3185 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3186 * relevant on hsw with pipe A when using the always-on power well
3189 if (crtc
->config
.cpu_transcoder
== TRANSCODER_EDP
&&
3190 !crtc
->config
.pch_pfit
.enabled
) {
3191 crtc
->config
.pch_pfit
.force_thru
= true;
3193 intel_display_power_get(dev_priv
,
3194 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3196 dev_priv
->display
.crtc_disable(&crtc
->base
);
3197 dev_priv
->display
.crtc_enable(&crtc
->base
);
3199 drm_modeset_unlock_all(dev
);
3202 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3205 struct intel_crtc
*crtc
=
3206 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3208 drm_modeset_lock_all(dev
);
3210 * If we use the eDP transcoder we need to make sure that we don't
3211 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3212 * relevant on hsw with pipe A when using the always-on power well
3215 if (crtc
->config
.pch_pfit
.force_thru
) {
3216 crtc
->config
.pch_pfit
.force_thru
= false;
3218 dev_priv
->display
.crtc_disable(&crtc
->base
);
3219 dev_priv
->display
.crtc_enable(&crtc
->base
);
3221 intel_display_power_put(dev_priv
,
3222 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3224 drm_modeset_unlock_all(dev
);
3227 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3229 enum intel_pipe_crc_source
*source
,
3232 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3233 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3236 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3237 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3239 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3240 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3242 case INTEL_PIPE_CRC_SOURCE_PF
:
3243 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3244 hsw_trans_edp_pipe_A_crc_wa(dev
);
3246 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3248 case INTEL_PIPE_CRC_SOURCE_NONE
:
3258 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3259 enum intel_pipe_crc_source source
)
3261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3262 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3263 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3265 u32 val
= 0; /* shut up gcc */
3268 if (pipe_crc
->source
== source
)
3271 /* forbid changing the source without going back to 'none' */
3272 if (pipe_crc
->source
&& source
)
3276 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3277 else if (INTEL_INFO(dev
)->gen
< 5)
3278 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3279 else if (IS_VALLEYVIEW(dev
))
3280 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3281 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3282 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3284 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3289 /* none -> real source transition */
3291 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3292 pipe_name(pipe
), pipe_crc_source_name(source
));
3294 pipe_crc
->entries
= kzalloc(sizeof(*pipe_crc
->entries
) *
3295 INTEL_PIPE_CRC_ENTRIES_NR
,
3297 if (!pipe_crc
->entries
)
3301 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3302 * enabled and disabled dynamically based on package C states,
3303 * user space can't make reliable use of the CRCs, so let's just
3304 * completely disable it.
3306 hsw_disable_ips(crtc
);
3308 spin_lock_irq(&pipe_crc
->lock
);
3311 spin_unlock_irq(&pipe_crc
->lock
);
3314 pipe_crc
->source
= source
;
3316 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3317 POSTING_READ(PIPE_CRC_CTL(pipe
));
3319 /* real source -> none transition */
3320 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3321 struct intel_pipe_crc_entry
*entries
;
3322 struct intel_crtc
*crtc
=
3323 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3325 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3328 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3330 intel_wait_for_vblank(dev
, pipe
);
3331 drm_modeset_unlock(&crtc
->base
.mutex
);
3333 spin_lock_irq(&pipe_crc
->lock
);
3334 entries
= pipe_crc
->entries
;
3335 pipe_crc
->entries
= NULL
;
3336 spin_unlock_irq(&pipe_crc
->lock
);
3341 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3342 else if (IS_VALLEYVIEW(dev
))
3343 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3344 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3345 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3347 hsw_enable_ips(crtc
);
3354 * Parse pipe CRC command strings:
3355 * command: wsp* object wsp+ name wsp+ source wsp*
3358 * source: (none | plane1 | plane2 | pf)
3359 * wsp: (#0x20 | #0x9 | #0xA)+
3362 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3363 * "pipe A none" -> Stop CRC
3365 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3372 /* skip leading white space */
3373 buf
= skip_spaces(buf
);
3375 break; /* end of buffer */
3377 /* find end of word */
3378 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3381 if (n_words
== max_words
) {
3382 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3384 return -EINVAL
; /* ran out of words[] before bytes */
3389 words
[n_words
++] = buf
;
3396 enum intel_pipe_crc_object
{
3397 PIPE_CRC_OBJECT_PIPE
,
3400 static const char * const pipe_crc_objects
[] = {
3405 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3409 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3410 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3418 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3420 const char name
= buf
[0];
3422 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3431 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3435 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3436 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3444 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3448 char *words
[N_WORDS
];
3450 enum intel_pipe_crc_object object
;
3451 enum intel_pipe_crc_source source
;
3453 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3454 if (n_words
!= N_WORDS
) {
3455 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3460 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3461 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3465 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3466 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3470 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3471 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3475 return pipe_crc_set_source(dev
, pipe
, source
);
3478 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3479 size_t len
, loff_t
*offp
)
3481 struct seq_file
*m
= file
->private_data
;
3482 struct drm_device
*dev
= m
->private;
3489 if (len
> PAGE_SIZE
- 1) {
3490 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3495 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3499 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3505 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3516 static const struct file_operations i915_display_crc_ctl_fops
= {
3517 .owner
= THIS_MODULE
,
3518 .open
= display_crc_ctl_open
,
3520 .llseek
= seq_lseek
,
3521 .release
= single_release
,
3522 .write
= display_crc_ctl_write
3525 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[5])
3527 struct drm_device
*dev
= m
->private;
3528 int num_levels
= ilk_wm_max_level(dev
) + 1;
3531 drm_modeset_lock_all(dev
);
3533 for (level
= 0; level
< num_levels
; level
++) {
3534 unsigned int latency
= wm
[level
];
3536 /* WM1+ latency values in 0.5us units */
3540 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3542 latency
/ 10, latency
% 10);
3545 drm_modeset_unlock_all(dev
);
3548 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3550 struct drm_device
*dev
= m
->private;
3552 wm_latency_show(m
, to_i915(dev
)->wm
.pri_latency
);
3557 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3559 struct drm_device
*dev
= m
->private;
3561 wm_latency_show(m
, to_i915(dev
)->wm
.spr_latency
);
3566 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3568 struct drm_device
*dev
= m
->private;
3570 wm_latency_show(m
, to_i915(dev
)->wm
.cur_latency
);
3575 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3577 struct drm_device
*dev
= inode
->i_private
;
3579 if (HAS_GMCH_DISPLAY(dev
))
3582 return single_open(file
, pri_wm_latency_show
, dev
);
3585 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3587 struct drm_device
*dev
= inode
->i_private
;
3589 if (HAS_GMCH_DISPLAY(dev
))
3592 return single_open(file
, spr_wm_latency_show
, dev
);
3595 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3597 struct drm_device
*dev
= inode
->i_private
;
3599 if (HAS_GMCH_DISPLAY(dev
))
3602 return single_open(file
, cur_wm_latency_show
, dev
);
3605 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3606 size_t len
, loff_t
*offp
, uint16_t wm
[5])
3608 struct seq_file
*m
= file
->private_data
;
3609 struct drm_device
*dev
= m
->private;
3610 uint16_t new[5] = { 0 };
3611 int num_levels
= ilk_wm_max_level(dev
) + 1;
3616 if (len
>= sizeof(tmp
))
3619 if (copy_from_user(tmp
, ubuf
, len
))
3624 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3625 if (ret
!= num_levels
)
3628 drm_modeset_lock_all(dev
);
3630 for (level
= 0; level
< num_levels
; level
++)
3631 wm
[level
] = new[level
];
3633 drm_modeset_unlock_all(dev
);
3639 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3640 size_t len
, loff_t
*offp
)
3642 struct seq_file
*m
= file
->private_data
;
3643 struct drm_device
*dev
= m
->private;
3645 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.pri_latency
);
3648 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3649 size_t len
, loff_t
*offp
)
3651 struct seq_file
*m
= file
->private_data
;
3652 struct drm_device
*dev
= m
->private;
3654 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.spr_latency
);
3657 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3658 size_t len
, loff_t
*offp
)
3660 struct seq_file
*m
= file
->private_data
;
3661 struct drm_device
*dev
= m
->private;
3663 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.cur_latency
);
3666 static const struct file_operations i915_pri_wm_latency_fops
= {
3667 .owner
= THIS_MODULE
,
3668 .open
= pri_wm_latency_open
,
3670 .llseek
= seq_lseek
,
3671 .release
= single_release
,
3672 .write
= pri_wm_latency_write
3675 static const struct file_operations i915_spr_wm_latency_fops
= {
3676 .owner
= THIS_MODULE
,
3677 .open
= spr_wm_latency_open
,
3679 .llseek
= seq_lseek
,
3680 .release
= single_release
,
3681 .write
= spr_wm_latency_write
3684 static const struct file_operations i915_cur_wm_latency_fops
= {
3685 .owner
= THIS_MODULE
,
3686 .open
= cur_wm_latency_open
,
3688 .llseek
= seq_lseek
,
3689 .release
= single_release
,
3690 .write
= cur_wm_latency_write
3694 i915_wedged_get(void *data
, u64
*val
)
3696 struct drm_device
*dev
= data
;
3697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3699 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3705 i915_wedged_set(void *data
, u64 val
)
3707 struct drm_device
*dev
= data
;
3708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3710 intel_runtime_pm_get(dev_priv
);
3712 i915_handle_error(dev
, val
,
3713 "Manually setting wedged to %llu", val
);
3715 intel_runtime_pm_put(dev_priv
);
3720 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
3721 i915_wedged_get
, i915_wedged_set
,
3725 i915_ring_stop_get(void *data
, u64
*val
)
3727 struct drm_device
*dev
= data
;
3728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3730 *val
= dev_priv
->gpu_error
.stop_rings
;
3736 i915_ring_stop_set(void *data
, u64 val
)
3738 struct drm_device
*dev
= data
;
3739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3742 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
3744 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3748 dev_priv
->gpu_error
.stop_rings
= val
;
3749 mutex_unlock(&dev
->struct_mutex
);
3754 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
3755 i915_ring_stop_get
, i915_ring_stop_set
,
3759 i915_ring_missed_irq_get(void *data
, u64
*val
)
3761 struct drm_device
*dev
= data
;
3762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3764 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
3769 i915_ring_missed_irq_set(void *data
, u64 val
)
3771 struct drm_device
*dev
= data
;
3772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3775 /* Lock against concurrent debugfs callers */
3776 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3779 dev_priv
->gpu_error
.missed_irq_rings
= val
;
3780 mutex_unlock(&dev
->struct_mutex
);
3785 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
3786 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
3790 i915_ring_test_irq_get(void *data
, u64
*val
)
3792 struct drm_device
*dev
= data
;
3793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3795 *val
= dev_priv
->gpu_error
.test_irq_rings
;
3801 i915_ring_test_irq_set(void *data
, u64 val
)
3803 struct drm_device
*dev
= data
;
3804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3807 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
3809 /* Lock against concurrent debugfs callers */
3810 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3814 dev_priv
->gpu_error
.test_irq_rings
= val
;
3815 mutex_unlock(&dev
->struct_mutex
);
3820 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
3821 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
3824 #define DROP_UNBOUND 0x1
3825 #define DROP_BOUND 0x2
3826 #define DROP_RETIRE 0x4
3827 #define DROP_ACTIVE 0x8
3828 #define DROP_ALL (DROP_UNBOUND | \
3833 i915_drop_caches_get(void *data
, u64
*val
)
3841 i915_drop_caches_set(void *data
, u64 val
)
3843 struct drm_device
*dev
= data
;
3844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3847 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
3849 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3850 * on ioctls on -EAGAIN. */
3851 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3855 if (val
& DROP_ACTIVE
) {
3856 ret
= i915_gpu_idle(dev
);
3861 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
3862 i915_gem_retire_requests(dev
);
3864 if (val
& DROP_BOUND
)
3865 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
3867 if (val
& DROP_UNBOUND
)
3868 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
3871 mutex_unlock(&dev
->struct_mutex
);
3876 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
3877 i915_drop_caches_get
, i915_drop_caches_set
,
3881 i915_max_freq_get(void *data
, u64
*val
)
3883 struct drm_device
*dev
= data
;
3884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3887 if (INTEL_INFO(dev
)->gen
< 6)
3890 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3892 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3896 if (IS_VALLEYVIEW(dev
))
3897 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
3899 *val
= dev_priv
->rps
.max_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
3900 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3906 i915_max_freq_set(void *data
, u64 val
)
3908 struct drm_device
*dev
= data
;
3909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3910 u32 rp_state_cap
, hw_max
, hw_min
;
3913 if (INTEL_INFO(dev
)->gen
< 6)
3916 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3918 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
3920 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3925 * Turbo will still be enabled, but won't go above the set value.
3927 if (IS_VALLEYVIEW(dev
)) {
3928 val
= vlv_freq_opcode(dev_priv
, val
);
3930 hw_max
= dev_priv
->rps
.max_freq
;
3931 hw_min
= dev_priv
->rps
.min_freq
;
3933 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
3935 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3936 hw_max
= dev_priv
->rps
.max_freq
;
3937 hw_min
= (rp_state_cap
>> 16) & 0xff;
3940 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
3941 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3945 dev_priv
->rps
.max_freq_softlimit
= val
;
3947 if (IS_VALLEYVIEW(dev
))
3948 valleyview_set_rps(dev
, val
);
3950 gen6_set_rps(dev
, val
);
3952 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3957 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
3958 i915_max_freq_get
, i915_max_freq_set
,
3962 i915_min_freq_get(void *data
, u64
*val
)
3964 struct drm_device
*dev
= data
;
3965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3968 if (INTEL_INFO(dev
)->gen
< 6)
3971 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3973 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3977 if (IS_VALLEYVIEW(dev
))
3978 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
3980 *val
= dev_priv
->rps
.min_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
3981 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3987 i915_min_freq_set(void *data
, u64 val
)
3989 struct drm_device
*dev
= data
;
3990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3991 u32 rp_state_cap
, hw_max
, hw_min
;
3994 if (INTEL_INFO(dev
)->gen
< 6)
3997 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3999 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4001 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4006 * Turbo will still be enabled, but won't go below the set value.
4008 if (IS_VALLEYVIEW(dev
)) {
4009 val
= vlv_freq_opcode(dev_priv
, val
);
4011 hw_max
= dev_priv
->rps
.max_freq
;
4012 hw_min
= dev_priv
->rps
.min_freq
;
4014 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
4016 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4017 hw_max
= dev_priv
->rps
.max_freq
;
4018 hw_min
= (rp_state_cap
>> 16) & 0xff;
4021 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4022 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4026 dev_priv
->rps
.min_freq_softlimit
= val
;
4028 if (IS_VALLEYVIEW(dev
))
4029 valleyview_set_rps(dev
, val
);
4031 gen6_set_rps(dev
, val
);
4033 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4038 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4039 i915_min_freq_get
, i915_min_freq_set
,
4043 i915_cache_sharing_get(void *data
, u64
*val
)
4045 struct drm_device
*dev
= data
;
4046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4050 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4053 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4056 intel_runtime_pm_get(dev_priv
);
4058 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4060 intel_runtime_pm_put(dev_priv
);
4061 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4063 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4069 i915_cache_sharing_set(void *data
, u64 val
)
4071 struct drm_device
*dev
= data
;
4072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4075 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4081 intel_runtime_pm_get(dev_priv
);
4082 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4084 /* Update the cache sharing policy here as well */
4085 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4086 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4087 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4088 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4090 intel_runtime_pm_put(dev_priv
);
4094 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4095 i915_cache_sharing_get
, i915_cache_sharing_set
,
4098 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4100 struct drm_device
*dev
= inode
->i_private
;
4101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4103 if (INTEL_INFO(dev
)->gen
< 6)
4106 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4111 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4113 struct drm_device
*dev
= inode
->i_private
;
4114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4116 if (INTEL_INFO(dev
)->gen
< 6)
4119 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4124 static const struct file_operations i915_forcewake_fops
= {
4125 .owner
= THIS_MODULE
,
4126 .open
= i915_forcewake_open
,
4127 .release
= i915_forcewake_release
,
4130 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4132 struct drm_device
*dev
= minor
->dev
;
4135 ent
= debugfs_create_file("i915_forcewake_user",
4138 &i915_forcewake_fops
);
4142 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4145 static int i915_debugfs_create(struct dentry
*root
,
4146 struct drm_minor
*minor
,
4148 const struct file_operations
*fops
)
4150 struct drm_device
*dev
= minor
->dev
;
4153 ent
= debugfs_create_file(name
,
4160 return drm_add_fake_info_node(minor
, ent
, fops
);
4163 static const struct drm_info_list i915_debugfs_list
[] = {
4164 {"i915_capabilities", i915_capabilities
, 0},
4165 {"i915_gem_objects", i915_gem_object_info
, 0},
4166 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4167 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4168 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4169 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4170 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4171 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4172 {"i915_gem_request", i915_gem_request_info
, 0},
4173 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4174 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4175 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4176 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4177 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4178 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4179 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4180 {"i915_frequency_info", i915_frequency_info
, 0},
4181 {"i915_drpc_info", i915_drpc_info
, 0},
4182 {"i915_emon_status", i915_emon_status
, 0},
4183 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
4184 {"i915_fbc_status", i915_fbc_status
, 0},
4185 {"i915_ips_status", i915_ips_status
, 0},
4186 {"i915_sr_status", i915_sr_status
, 0},
4187 {"i915_opregion", i915_opregion
, 0},
4188 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
4189 {"i915_context_status", i915_context_status
, 0},
4190 {"i915_dump_lrc", i915_dump_lrc
, 0},
4191 {"i915_execlists", i915_execlists
, 0},
4192 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info
, 0},
4193 {"i915_swizzle_info", i915_swizzle_info
, 0},
4194 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
4195 {"i915_llc", i915_llc
, 0},
4196 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
4197 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
4198 {"i915_energy_uJ", i915_energy_uJ
, 0},
4199 {"i915_pc8_status", i915_pc8_status
, 0},
4200 {"i915_power_domain_info", i915_power_domain_info
, 0},
4201 {"i915_display_info", i915_display_info
, 0},
4202 {"i915_semaphore_status", i915_semaphore_status
, 0},
4203 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
4204 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
4205 {"i915_wa_registers", i915_wa_registers
, 0},
4207 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4209 static const struct i915_debugfs_files
{
4211 const struct file_operations
*fops
;
4212 } i915_debugfs_files
[] = {
4213 {"i915_wedged", &i915_wedged_fops
},
4214 {"i915_max_freq", &i915_max_freq_fops
},
4215 {"i915_min_freq", &i915_min_freq_fops
},
4216 {"i915_cache_sharing", &i915_cache_sharing_fops
},
4217 {"i915_ring_stop", &i915_ring_stop_fops
},
4218 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
4219 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
4220 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
4221 {"i915_error_state", &i915_error_state_fops
},
4222 {"i915_next_seqno", &i915_next_seqno_fops
},
4223 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
4224 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
4225 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
4226 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
4227 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
4230 void intel_display_crc_init(struct drm_device
*dev
)
4232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4235 for_each_pipe(dev_priv
, pipe
) {
4236 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4238 pipe_crc
->opened
= false;
4239 spin_lock_init(&pipe_crc
->lock
);
4240 init_waitqueue_head(&pipe_crc
->wq
);
4244 int i915_debugfs_init(struct drm_minor
*minor
)
4248 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
4252 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4253 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
4258 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4259 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
4260 i915_debugfs_files
[i
].name
,
4261 i915_debugfs_files
[i
].fops
);
4266 return drm_debugfs_create_files(i915_debugfs_list
,
4267 I915_DEBUGFS_ENTRIES
,
4268 minor
->debugfs_root
, minor
);
4271 void i915_debugfs_cleanup(struct drm_minor
*minor
)
4275 drm_debugfs_remove_files(i915_debugfs_list
,
4276 I915_DEBUGFS_ENTRIES
, minor
);
4278 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
4281 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4282 struct drm_info_list
*info_list
=
4283 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
4285 drm_debugfs_remove_files(info_list
, 1, minor
);
4288 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4289 struct drm_info_list
*info_list
=
4290 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
4292 drm_debugfs_remove_files(info_list
, 1, minor
);