2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static char get_active_flag(struct drm_i915_gem_object
*obj
)
94 return i915_gem_object_is_active(obj
) ? '*' : ' ';
97 static char get_pin_flag(struct drm_i915_gem_object
*obj
)
99 return obj
->pin_display
? 'p' : ' ';
102 static char get_tiling_flag(struct drm_i915_gem_object
*obj
)
104 switch (i915_gem_object_get_tiling(obj
)) {
106 case I915_TILING_NONE
: return ' ';
107 case I915_TILING_X
: return 'X';
108 case I915_TILING_Y
: return 'Y';
112 static char get_global_flag(struct drm_i915_gem_object
*obj
)
114 return i915_gem_obj_to_ggtt(obj
) ? 'g' : ' ';
117 static char get_pin_mapped_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->mapping
? 'M' : ' ';
122 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
127 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
128 if (i915_vma_is_ggtt(vma
) && drm_mm_node_allocated(&vma
->node
))
129 size
+= vma
->node
.size
;
136 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
138 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
139 struct intel_engine_cs
*engine
;
140 struct i915_vma
*vma
;
141 unsigned int frontbuffer_bits
;
143 enum intel_engine_id id
;
145 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
147 seq_printf(m
, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
149 get_active_flag(obj
),
151 get_tiling_flag(obj
),
152 get_global_flag(obj
),
153 get_pin_mapped_flag(obj
),
154 obj
->base
.size
/ 1024,
155 obj
->base
.read_domains
,
156 obj
->base
.write_domain
);
157 for_each_engine_id(engine
, dev_priv
, id
)
159 i915_gem_active_get_seqno(&obj
->last_read
[id
],
160 &obj
->base
.dev
->struct_mutex
));
161 seq_printf(m
, "] %x %x%s%s%s",
162 i915_gem_active_get_seqno(&obj
->last_write
,
163 &obj
->base
.dev
->struct_mutex
),
164 i915_gem_active_get_seqno(&obj
->last_fence
,
165 &obj
->base
.dev
->struct_mutex
),
166 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
167 obj
->dirty
? " dirty" : "",
168 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
170 seq_printf(m
, " (name: %d)", obj
->base
.name
);
171 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
172 if (i915_vma_is_pinned(vma
))
175 seq_printf(m
, " (pinned x %d)", pin_count
);
176 if (obj
->pin_display
)
177 seq_printf(m
, " (display)");
178 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
179 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
180 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
181 if (!drm_mm_node_allocated(&vma
->node
))
184 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
185 i915_vma_is_ggtt(vma
) ? "g" : "pp",
186 vma
->node
.start
, vma
->node
.size
);
187 if (i915_vma_is_ggtt(vma
))
188 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
192 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
193 if (obj
->pin_display
|| obj
->fault_mappable
) {
195 if (obj
->pin_display
)
197 if (obj
->fault_mappable
)
200 seq_printf(m
, " (%s mappable)", s
);
203 engine
= i915_gem_active_get_engine(&obj
->last_write
,
204 &obj
->base
.dev
->struct_mutex
);
206 seq_printf(m
, " (%s)", engine
->name
);
208 frontbuffer_bits
= atomic_read(&obj
->frontbuffer_bits
);
209 if (frontbuffer_bits
)
210 seq_printf(m
, " (frontbuffer: 0x%03x)", frontbuffer_bits
);
213 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
215 struct drm_info_node
*node
= m
->private;
216 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
217 struct list_head
*head
;
218 struct drm_device
*dev
= node
->minor
->dev
;
219 struct drm_i915_private
*dev_priv
= to_i915(dev
);
220 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
221 struct i915_vma
*vma
;
222 u64 total_obj_size
, total_gtt_size
;
225 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
229 /* FIXME: the user of this interface might want more than just GGTT */
232 seq_puts(m
, "Active:\n");
233 head
= &ggtt
->base
.active_list
;
236 seq_puts(m
, "Inactive:\n");
237 head
= &ggtt
->base
.inactive_list
;
240 mutex_unlock(&dev
->struct_mutex
);
244 total_obj_size
= total_gtt_size
= count
= 0;
245 list_for_each_entry(vma
, head
, vm_link
) {
247 describe_obj(m
, vma
->obj
);
249 total_obj_size
+= vma
->obj
->base
.size
;
250 total_gtt_size
+= vma
->node
.size
;
253 mutex_unlock(&dev
->struct_mutex
);
255 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
256 count
, total_obj_size
, total_gtt_size
);
260 static int obj_rank_by_stolen(void *priv
,
261 struct list_head
*A
, struct list_head
*B
)
263 struct drm_i915_gem_object
*a
=
264 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
265 struct drm_i915_gem_object
*b
=
266 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
268 if (a
->stolen
->start
< b
->stolen
->start
)
270 if (a
->stolen
->start
> b
->stolen
->start
)
275 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
277 struct drm_info_node
*node
= m
->private;
278 struct drm_device
*dev
= node
->minor
->dev
;
279 struct drm_i915_private
*dev_priv
= to_i915(dev
);
280 struct drm_i915_gem_object
*obj
;
281 u64 total_obj_size
, total_gtt_size
;
285 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
289 total_obj_size
= total_gtt_size
= count
= 0;
290 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
291 if (obj
->stolen
== NULL
)
294 list_add(&obj
->obj_exec_link
, &stolen
);
296 total_obj_size
+= obj
->base
.size
;
297 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
300 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
301 if (obj
->stolen
== NULL
)
304 list_add(&obj
->obj_exec_link
, &stolen
);
306 total_obj_size
+= obj
->base
.size
;
309 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
310 seq_puts(m
, "Stolen:\n");
311 while (!list_empty(&stolen
)) {
312 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
314 describe_obj(m
, obj
);
316 list_del_init(&obj
->obj_exec_link
);
318 mutex_unlock(&dev
->struct_mutex
);
320 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
321 count
, total_obj_size
, total_gtt_size
);
325 #define count_objects(list, member) do { \
326 list_for_each_entry(obj, list, member) { \
327 size += i915_gem_obj_total_ggtt_size(obj); \
329 if (obj->map_and_fenceable) { \
330 mappable_size += i915_gem_obj_ggtt_size(obj); \
337 struct drm_i915_file_private
*file_priv
;
341 u64 active
, inactive
;
344 static int per_file_stats(int id
, void *ptr
, void *data
)
346 struct drm_i915_gem_object
*obj
= ptr
;
347 struct file_stats
*stats
= data
;
348 struct i915_vma
*vma
;
351 stats
->total
+= obj
->base
.size
;
352 if (!obj
->bind_count
)
353 stats
->unbound
+= obj
->base
.size
;
354 if (obj
->base
.name
|| obj
->base
.dma_buf
)
355 stats
->shared
+= obj
->base
.size
;
357 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
358 if (!drm_mm_node_allocated(&vma
->node
))
361 if (i915_vma_is_ggtt(vma
)) {
362 stats
->global
+= vma
->node
.size
;
364 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vma
->vm
);
366 if (ppgtt
->base
.file
!= stats
->file_priv
)
370 if (i915_vma_is_active(vma
))
371 stats
->active
+= vma
->node
.size
;
373 stats
->inactive
+= vma
->node
.size
;
379 #define print_file_stats(m, name, stats) do { \
381 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
392 static void print_batch_pool_stats(struct seq_file
*m
,
393 struct drm_i915_private
*dev_priv
)
395 struct drm_i915_gem_object
*obj
;
396 struct file_stats stats
;
397 struct intel_engine_cs
*engine
;
400 memset(&stats
, 0, sizeof(stats
));
402 for_each_engine(engine
, dev_priv
) {
403 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
404 list_for_each_entry(obj
,
405 &engine
->batch_pool
.cache_list
[j
],
407 per_file_stats(0, obj
, &stats
);
411 print_file_stats(m
, "[k]batch pool", stats
);
414 static int per_file_ctx_stats(int id
, void *ptr
, void *data
)
416 struct i915_gem_context
*ctx
= ptr
;
419 for (n
= 0; n
< ARRAY_SIZE(ctx
->engine
); n
++) {
420 if (ctx
->engine
[n
].state
)
421 per_file_stats(0, ctx
->engine
[n
].state
, data
);
422 if (ctx
->engine
[n
].ring
)
423 per_file_stats(0, ctx
->engine
[n
].ring
->obj
, data
);
429 static void print_context_stats(struct seq_file
*m
,
430 struct drm_i915_private
*dev_priv
)
432 struct file_stats stats
;
433 struct drm_file
*file
;
435 memset(&stats
, 0, sizeof(stats
));
437 mutex_lock(&dev_priv
->drm
.struct_mutex
);
438 if (dev_priv
->kernel_context
)
439 per_file_ctx_stats(0, dev_priv
->kernel_context
, &stats
);
441 list_for_each_entry(file
, &dev_priv
->drm
.filelist
, lhead
) {
442 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
443 idr_for_each(&fpriv
->context_idr
, per_file_ctx_stats
, &stats
);
445 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
447 print_file_stats(m
, "[k]contexts", stats
);
450 #define count_vmas(list, member) do { \
451 list_for_each_entry(vma, list, member) { \
452 size += i915_gem_obj_total_ggtt_size(vma->obj); \
454 if (vma->obj->map_and_fenceable) { \
455 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
461 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
463 struct drm_info_node
*node
= m
->private;
464 struct drm_device
*dev
= node
->minor
->dev
;
465 struct drm_i915_private
*dev_priv
= to_i915(dev
);
466 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
467 u32 count
, mappable_count
, purgeable_count
;
468 u64 size
, mappable_size
, purgeable_size
;
469 unsigned long pin_mapped_count
= 0, pin_mapped_purgeable_count
= 0;
470 u64 pin_mapped_size
= 0, pin_mapped_purgeable_size
= 0;
471 struct drm_i915_gem_object
*obj
;
472 struct drm_file
*file
;
473 struct i915_vma
*vma
;
476 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
480 seq_printf(m
, "%u objects, %zu bytes\n",
481 dev_priv
->mm
.object_count
,
482 dev_priv
->mm
.object_memory
);
484 size
= count
= mappable_size
= mappable_count
= 0;
485 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
486 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
487 count
, mappable_count
, size
, mappable_size
);
489 size
= count
= mappable_size
= mappable_count
= 0;
490 count_vmas(&ggtt
->base
.active_list
, vm_link
);
491 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
492 count
, mappable_count
, size
, mappable_size
);
494 size
= count
= mappable_size
= mappable_count
= 0;
495 count_vmas(&ggtt
->base
.inactive_list
, vm_link
);
496 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
497 count
, mappable_count
, size
, mappable_size
);
499 size
= count
= purgeable_size
= purgeable_count
= 0;
500 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
501 size
+= obj
->base
.size
, ++count
;
502 if (obj
->madv
== I915_MADV_DONTNEED
)
503 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
506 pin_mapped_size
+= obj
->base
.size
;
507 if (obj
->pages_pin_count
== 0) {
508 pin_mapped_purgeable_count
++;
509 pin_mapped_purgeable_size
+= obj
->base
.size
;
513 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
515 size
= count
= mappable_size
= mappable_count
= 0;
516 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
517 if (obj
->fault_mappable
) {
518 size
+= i915_gem_obj_ggtt_size(obj
);
521 if (obj
->pin_display
) {
522 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
525 if (obj
->madv
== I915_MADV_DONTNEED
) {
526 purgeable_size
+= obj
->base
.size
;
531 pin_mapped_size
+= obj
->base
.size
;
532 if (obj
->pages_pin_count
== 0) {
533 pin_mapped_purgeable_count
++;
534 pin_mapped_purgeable_size
+= obj
->base
.size
;
538 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
539 purgeable_count
, purgeable_size
);
540 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
541 mappable_count
, mappable_size
);
542 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
545 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
546 pin_mapped_count
, pin_mapped_purgeable_count
,
547 pin_mapped_size
, pin_mapped_purgeable_size
);
549 seq_printf(m
, "%llu [%llu] gtt total\n",
550 ggtt
->base
.total
, ggtt
->mappable_end
- ggtt
->base
.start
);
553 print_batch_pool_stats(m
, dev_priv
);
554 mutex_unlock(&dev
->struct_mutex
);
556 mutex_lock(&dev
->filelist_mutex
);
557 print_context_stats(m
, dev_priv
);
558 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
559 struct file_stats stats
;
560 struct task_struct
*task
;
562 memset(&stats
, 0, sizeof(stats
));
563 stats
.file_priv
= file
->driver_priv
;
564 spin_lock(&file
->table_lock
);
565 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
566 spin_unlock(&file
->table_lock
);
568 * Although we have a valid reference on file->pid, that does
569 * not guarantee that the task_struct who called get_pid() is
570 * still alive (e.g. get_pid(current) => fork() => exit()).
571 * Therefore, we need to protect this ->comm access using RCU.
574 task
= pid_task(file
->pid
, PIDTYPE_PID
);
575 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
578 mutex_unlock(&dev
->filelist_mutex
);
583 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
585 struct drm_info_node
*node
= m
->private;
586 struct drm_device
*dev
= node
->minor
->dev
;
587 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
588 struct drm_i915_private
*dev_priv
= to_i915(dev
);
589 struct drm_i915_gem_object
*obj
;
590 u64 total_obj_size
, total_gtt_size
;
593 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
597 total_obj_size
= total_gtt_size
= count
= 0;
598 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
599 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
603 describe_obj(m
, obj
);
605 total_obj_size
+= obj
->base
.size
;
606 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
610 mutex_unlock(&dev
->struct_mutex
);
612 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
613 count
, total_obj_size
, total_gtt_size
);
618 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
620 struct drm_info_node
*node
= m
->private;
621 struct drm_device
*dev
= node
->minor
->dev
;
622 struct drm_i915_private
*dev_priv
= to_i915(dev
);
623 struct intel_crtc
*crtc
;
626 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
630 for_each_intel_crtc(dev
, crtc
) {
631 const char pipe
= pipe_name(crtc
->pipe
);
632 const char plane
= plane_name(crtc
->plane
);
633 struct intel_flip_work
*work
;
635 spin_lock_irq(&dev
->event_lock
);
636 work
= crtc
->flip_work
;
638 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
644 pending
= atomic_read(&work
->pending
);
646 seq_printf(m
, "Flip ioctl preparing on pipe %c (plane %c)\n",
649 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
652 if (work
->flip_queued_req
) {
653 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(work
->flip_queued_req
);
655 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
657 i915_gem_request_get_seqno(work
->flip_queued_req
),
658 dev_priv
->next_seqno
,
659 intel_engine_get_seqno(engine
),
660 i915_gem_request_completed(work
->flip_queued_req
));
662 seq_printf(m
, "Flip not associated with any ring\n");
663 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
664 work
->flip_queued_vblank
,
665 work
->flip_ready_vblank
,
666 intel_crtc_get_vblank_counter(crtc
));
667 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
669 if (INTEL_INFO(dev
)->gen
>= 4)
670 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
672 addr
= I915_READ(DSPADDR(crtc
->plane
));
673 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
675 if (work
->pending_flip_obj
) {
676 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
677 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
680 spin_unlock_irq(&dev
->event_lock
);
683 mutex_unlock(&dev
->struct_mutex
);
688 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
690 struct drm_info_node
*node
= m
->private;
691 struct drm_device
*dev
= node
->minor
->dev
;
692 struct drm_i915_private
*dev_priv
= to_i915(dev
);
693 struct drm_i915_gem_object
*obj
;
694 struct intel_engine_cs
*engine
;
698 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
702 for_each_engine(engine
, dev_priv
) {
703 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
707 list_for_each_entry(obj
,
708 &engine
->batch_pool
.cache_list
[j
],
711 seq_printf(m
, "%s cache[%d]: %d objects\n",
712 engine
->name
, j
, count
);
714 list_for_each_entry(obj
,
715 &engine
->batch_pool
.cache_list
[j
],
718 describe_obj(m
, obj
);
726 seq_printf(m
, "total: %d\n", total
);
728 mutex_unlock(&dev
->struct_mutex
);
733 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
735 struct drm_info_node
*node
= m
->private;
736 struct drm_device
*dev
= node
->minor
->dev
;
737 struct drm_i915_private
*dev_priv
= to_i915(dev
);
738 struct intel_engine_cs
*engine
;
739 struct drm_i915_gem_request
*req
;
742 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
747 for_each_engine(engine
, dev_priv
) {
751 list_for_each_entry(req
, &engine
->request_list
, link
)
756 seq_printf(m
, "%s requests: %d\n", engine
->name
, count
);
757 list_for_each_entry(req
, &engine
->request_list
, link
) {
758 struct task_struct
*task
;
763 task
= pid_task(req
->pid
, PIDTYPE_PID
);
764 seq_printf(m
, " %x @ %d: %s [%d]\n",
766 (int) (jiffies
- req
->emitted_jiffies
),
767 task
? task
->comm
: "<unknown>",
768 task
? task
->pid
: -1);
774 mutex_unlock(&dev
->struct_mutex
);
777 seq_puts(m
, "No requests\n");
782 static void i915_ring_seqno_info(struct seq_file
*m
,
783 struct intel_engine_cs
*engine
)
785 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
788 seq_printf(m
, "Current sequence (%s): %x\n",
789 engine
->name
, intel_engine_get_seqno(engine
));
790 seq_printf(m
, "Current user interrupts (%s): %lx\n",
791 engine
->name
, READ_ONCE(engine
->breadcrumbs
.irq_wakeups
));
794 for (rb
= rb_first(&b
->waiters
); rb
; rb
= rb_next(rb
)) {
795 struct intel_wait
*w
= container_of(rb
, typeof(*w
), node
);
797 seq_printf(m
, "Waiting (%s): %s [%d] on %x\n",
798 engine
->name
, w
->tsk
->comm
, w
->tsk
->pid
, w
->seqno
);
800 spin_unlock(&b
->lock
);
803 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
805 struct drm_info_node
*node
= m
->private;
806 struct drm_device
*dev
= node
->minor
->dev
;
807 struct drm_i915_private
*dev_priv
= to_i915(dev
);
808 struct intel_engine_cs
*engine
;
811 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
814 intel_runtime_pm_get(dev_priv
);
816 for_each_engine(engine
, dev_priv
)
817 i915_ring_seqno_info(m
, engine
);
819 intel_runtime_pm_put(dev_priv
);
820 mutex_unlock(&dev
->struct_mutex
);
826 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
828 struct drm_info_node
*node
= m
->private;
829 struct drm_device
*dev
= node
->minor
->dev
;
830 struct drm_i915_private
*dev_priv
= to_i915(dev
);
831 struct intel_engine_cs
*engine
;
834 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
837 intel_runtime_pm_get(dev_priv
);
839 if (IS_CHERRYVIEW(dev
)) {
840 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
841 I915_READ(GEN8_MASTER_IRQ
));
843 seq_printf(m
, "Display IER:\t%08x\n",
845 seq_printf(m
, "Display IIR:\t%08x\n",
847 seq_printf(m
, "Display IIR_RW:\t%08x\n",
848 I915_READ(VLV_IIR_RW
));
849 seq_printf(m
, "Display IMR:\t%08x\n",
851 for_each_pipe(dev_priv
, pipe
)
852 seq_printf(m
, "Pipe %c stat:\t%08x\n",
854 I915_READ(PIPESTAT(pipe
)));
856 seq_printf(m
, "Port hotplug:\t%08x\n",
857 I915_READ(PORT_HOTPLUG_EN
));
858 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
859 I915_READ(VLV_DPFLIPSTAT
));
860 seq_printf(m
, "DPINVGTT:\t%08x\n",
861 I915_READ(DPINVGTT
));
863 for (i
= 0; i
< 4; i
++) {
864 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
865 i
, I915_READ(GEN8_GT_IMR(i
)));
866 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
867 i
, I915_READ(GEN8_GT_IIR(i
)));
868 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
869 i
, I915_READ(GEN8_GT_IER(i
)));
872 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
873 I915_READ(GEN8_PCU_IMR
));
874 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
875 I915_READ(GEN8_PCU_IIR
));
876 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
877 I915_READ(GEN8_PCU_IER
));
878 } else if (INTEL_INFO(dev
)->gen
>= 8) {
879 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
880 I915_READ(GEN8_MASTER_IRQ
));
882 for (i
= 0; i
< 4; i
++) {
883 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
884 i
, I915_READ(GEN8_GT_IMR(i
)));
885 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
886 i
, I915_READ(GEN8_GT_IIR(i
)));
887 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
888 i
, I915_READ(GEN8_GT_IER(i
)));
891 for_each_pipe(dev_priv
, pipe
) {
892 enum intel_display_power_domain power_domain
;
894 power_domain
= POWER_DOMAIN_PIPE(pipe
);
895 if (!intel_display_power_get_if_enabled(dev_priv
,
897 seq_printf(m
, "Pipe %c power disabled\n",
901 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
903 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
904 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
906 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
907 seq_printf(m
, "Pipe %c IER:\t%08x\n",
909 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
911 intel_display_power_put(dev_priv
, power_domain
);
914 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
915 I915_READ(GEN8_DE_PORT_IMR
));
916 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
917 I915_READ(GEN8_DE_PORT_IIR
));
918 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
919 I915_READ(GEN8_DE_PORT_IER
));
921 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
922 I915_READ(GEN8_DE_MISC_IMR
));
923 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
924 I915_READ(GEN8_DE_MISC_IIR
));
925 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
926 I915_READ(GEN8_DE_MISC_IER
));
928 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
929 I915_READ(GEN8_PCU_IMR
));
930 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
931 I915_READ(GEN8_PCU_IIR
));
932 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
933 I915_READ(GEN8_PCU_IER
));
934 } else if (IS_VALLEYVIEW(dev
)) {
935 seq_printf(m
, "Display IER:\t%08x\n",
937 seq_printf(m
, "Display IIR:\t%08x\n",
939 seq_printf(m
, "Display IIR_RW:\t%08x\n",
940 I915_READ(VLV_IIR_RW
));
941 seq_printf(m
, "Display IMR:\t%08x\n",
943 for_each_pipe(dev_priv
, pipe
)
944 seq_printf(m
, "Pipe %c stat:\t%08x\n",
946 I915_READ(PIPESTAT(pipe
)));
948 seq_printf(m
, "Master IER:\t%08x\n",
949 I915_READ(VLV_MASTER_IER
));
951 seq_printf(m
, "Render IER:\t%08x\n",
953 seq_printf(m
, "Render IIR:\t%08x\n",
955 seq_printf(m
, "Render IMR:\t%08x\n",
958 seq_printf(m
, "PM IER:\t\t%08x\n",
959 I915_READ(GEN6_PMIER
));
960 seq_printf(m
, "PM IIR:\t\t%08x\n",
961 I915_READ(GEN6_PMIIR
));
962 seq_printf(m
, "PM IMR:\t\t%08x\n",
963 I915_READ(GEN6_PMIMR
));
965 seq_printf(m
, "Port hotplug:\t%08x\n",
966 I915_READ(PORT_HOTPLUG_EN
));
967 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
968 I915_READ(VLV_DPFLIPSTAT
));
969 seq_printf(m
, "DPINVGTT:\t%08x\n",
970 I915_READ(DPINVGTT
));
972 } else if (!HAS_PCH_SPLIT(dev
)) {
973 seq_printf(m
, "Interrupt enable: %08x\n",
975 seq_printf(m
, "Interrupt identity: %08x\n",
977 seq_printf(m
, "Interrupt mask: %08x\n",
979 for_each_pipe(dev_priv
, pipe
)
980 seq_printf(m
, "Pipe %c stat: %08x\n",
982 I915_READ(PIPESTAT(pipe
)));
984 seq_printf(m
, "North Display Interrupt enable: %08x\n",
986 seq_printf(m
, "North Display Interrupt identity: %08x\n",
988 seq_printf(m
, "North Display Interrupt mask: %08x\n",
990 seq_printf(m
, "South Display Interrupt enable: %08x\n",
992 seq_printf(m
, "South Display Interrupt identity: %08x\n",
994 seq_printf(m
, "South Display Interrupt mask: %08x\n",
996 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
998 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
1000 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
1003 for_each_engine(engine
, dev_priv
) {
1004 if (INTEL_INFO(dev
)->gen
>= 6) {
1006 "Graphics Interrupt mask (%s): %08x\n",
1007 engine
->name
, I915_READ_IMR(engine
));
1009 i915_ring_seqno_info(m
, engine
);
1011 intel_runtime_pm_put(dev_priv
);
1012 mutex_unlock(&dev
->struct_mutex
);
1017 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
1019 struct drm_info_node
*node
= m
->private;
1020 struct drm_device
*dev
= node
->minor
->dev
;
1021 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1024 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1028 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
1029 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1030 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
1032 seq_printf(m
, "Fence %d, pin count = %d, object = ",
1033 i
, dev_priv
->fence_regs
[i
].pin_count
);
1035 seq_puts(m
, "unused");
1037 describe_obj(m
, obj
);
1041 mutex_unlock(&dev
->struct_mutex
);
1045 static int i915_hws_info(struct seq_file
*m
, void *data
)
1047 struct drm_info_node
*node
= m
->private;
1048 struct drm_device
*dev
= node
->minor
->dev
;
1049 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1050 struct intel_engine_cs
*engine
;
1054 engine
= &dev_priv
->engine
[(uintptr_t)node
->info_ent
->data
];
1055 hws
= engine
->status_page
.page_addr
;
1059 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
1060 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1062 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1068 i915_error_state_write(struct file
*filp
,
1069 const char __user
*ubuf
,
1073 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1074 struct drm_device
*dev
= error_priv
->dev
;
1077 DRM_DEBUG_DRIVER("Resetting error state\n");
1079 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1083 i915_destroy_error_state(dev
);
1084 mutex_unlock(&dev
->struct_mutex
);
1089 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1091 struct drm_device
*dev
= inode
->i_private
;
1092 struct i915_error_state_file_priv
*error_priv
;
1094 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1098 error_priv
->dev
= dev
;
1100 i915_error_state_get(dev
, error_priv
);
1102 file
->private_data
= error_priv
;
1107 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1109 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1111 i915_error_state_put(error_priv
);
1117 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1118 size_t count
, loff_t
*pos
)
1120 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1121 struct drm_i915_error_state_buf error_str
;
1123 ssize_t ret_count
= 0;
1126 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1130 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1134 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1141 *pos
= error_str
.start
+ ret_count
;
1143 i915_error_state_buf_release(&error_str
);
1144 return ret
?: ret_count
;
1147 static const struct file_operations i915_error_state_fops
= {
1148 .owner
= THIS_MODULE
,
1149 .open
= i915_error_state_open
,
1150 .read
= i915_error_state_read
,
1151 .write
= i915_error_state_write
,
1152 .llseek
= default_llseek
,
1153 .release
= i915_error_state_release
,
1157 i915_next_seqno_get(void *data
, u64
*val
)
1159 struct drm_device
*dev
= data
;
1160 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1163 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1167 *val
= dev_priv
->next_seqno
;
1168 mutex_unlock(&dev
->struct_mutex
);
1174 i915_next_seqno_set(void *data
, u64 val
)
1176 struct drm_device
*dev
= data
;
1179 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1183 ret
= i915_gem_set_seqno(dev
, val
);
1184 mutex_unlock(&dev
->struct_mutex
);
1189 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1190 i915_next_seqno_get
, i915_next_seqno_set
,
1193 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1195 struct drm_info_node
*node
= m
->private;
1196 struct drm_device
*dev
= node
->minor
->dev
;
1197 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1200 intel_runtime_pm_get(dev_priv
);
1203 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1204 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1206 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1207 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1208 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1210 seq_printf(m
, "Current P-state: %d\n",
1211 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1212 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1215 mutex_lock(&dev_priv
->rps
.hw_lock
);
1216 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1217 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1218 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1220 seq_printf(m
, "actual GPU freq: %d MHz\n",
1221 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1223 seq_printf(m
, "current GPU freq: %d MHz\n",
1224 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1226 seq_printf(m
, "max GPU freq: %d MHz\n",
1227 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1229 seq_printf(m
, "min GPU freq: %d MHz\n",
1230 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1232 seq_printf(m
, "idle GPU freq: %d MHz\n",
1233 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1236 "efficient (RPe) frequency: %d MHz\n",
1237 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1238 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1239 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1240 u32 rp_state_limits
;
1243 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1244 u32 rpstat
, cagf
, reqf
;
1245 u32 rpupei
, rpcurup
, rpprevup
;
1246 u32 rpdownei
, rpcurdown
, rpprevdown
;
1247 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1250 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1251 if (IS_BROXTON(dev
)) {
1252 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1253 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1255 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1256 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1259 /* RPSTAT1 is in the GT power well */
1260 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1264 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1266 reqf
= I915_READ(GEN6_RPNSWREQ
);
1270 reqf
&= ~GEN6_TURBO_DISABLE
;
1271 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1276 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1278 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1279 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1280 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1282 rpstat
= I915_READ(GEN6_RPSTAT1
);
1283 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
) & GEN6_CURICONT_MASK
;
1284 rpcurup
= I915_READ(GEN6_RP_CUR_UP
) & GEN6_CURBSYTAVG_MASK
;
1285 rpprevup
= I915_READ(GEN6_RP_PREV_UP
) & GEN6_CURBSYTAVG_MASK
;
1286 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
) & GEN6_CURIAVG_MASK
;
1287 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1288 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1290 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1291 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1292 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1294 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1295 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1297 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1298 mutex_unlock(&dev
->struct_mutex
);
1300 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1301 pm_ier
= I915_READ(GEN6_PMIER
);
1302 pm_imr
= I915_READ(GEN6_PMIMR
);
1303 pm_isr
= I915_READ(GEN6_PMISR
);
1304 pm_iir
= I915_READ(GEN6_PMIIR
);
1305 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1307 pm_ier
= I915_READ(GEN8_GT_IER(2));
1308 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1309 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1310 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1311 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1313 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1314 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1315 seq_printf(m
, "pm_intr_keep: 0x%08x\n", dev_priv
->rps
.pm_intr_keep
);
1316 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1317 seq_printf(m
, "Render p-state ratio: %d\n",
1318 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1319 seq_printf(m
, "Render p-state VID: %d\n",
1320 gt_perf_status
& 0xff);
1321 seq_printf(m
, "Render p-state limit: %d\n",
1322 rp_state_limits
& 0xff);
1323 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1324 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1325 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1326 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1327 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1328 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1329 seq_printf(m
, "RP CUR UP EI: %d (%dus)\n",
1330 rpupei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpupei
));
1331 seq_printf(m
, "RP CUR UP: %d (%dus)\n",
1332 rpcurup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurup
));
1333 seq_printf(m
, "RP PREV UP: %d (%dus)\n",
1334 rpprevup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevup
));
1335 seq_printf(m
, "Up threshold: %d%%\n",
1336 dev_priv
->rps
.up_threshold
);
1338 seq_printf(m
, "RP CUR DOWN EI: %d (%dus)\n",
1339 rpdownei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpdownei
));
1340 seq_printf(m
, "RP CUR DOWN: %d (%dus)\n",
1341 rpcurdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurdown
));
1342 seq_printf(m
, "RP PREV DOWN: %d (%dus)\n",
1343 rpprevdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevdown
));
1344 seq_printf(m
, "Down threshold: %d%%\n",
1345 dev_priv
->rps
.down_threshold
);
1347 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1348 rp_state_cap
>> 16) & 0xff;
1349 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1350 GEN9_FREQ_SCALER
: 1);
1351 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1352 intel_gpu_freq(dev_priv
, max_freq
));
1354 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1355 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1356 GEN9_FREQ_SCALER
: 1);
1357 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1358 intel_gpu_freq(dev_priv
, max_freq
));
1360 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1361 rp_state_cap
>> 0) & 0xff;
1362 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1363 GEN9_FREQ_SCALER
: 1);
1364 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1365 intel_gpu_freq(dev_priv
, max_freq
));
1366 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1367 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1369 seq_printf(m
, "Current freq: %d MHz\n",
1370 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1371 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1372 seq_printf(m
, "Idle freq: %d MHz\n",
1373 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1374 seq_printf(m
, "Min freq: %d MHz\n",
1375 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1376 seq_printf(m
, "Boost freq: %d MHz\n",
1377 intel_gpu_freq(dev_priv
, dev_priv
->rps
.boost_freq
));
1378 seq_printf(m
, "Max freq: %d MHz\n",
1379 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1381 "efficient (RPe) frequency: %d MHz\n",
1382 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1384 seq_puts(m
, "no P-state info available\n");
1387 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1388 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1389 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1392 intel_runtime_pm_put(dev_priv
);
1396 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1398 struct drm_info_node
*node
= m
->private;
1399 struct drm_device
*dev
= node
->minor
->dev
;
1400 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1401 struct intel_engine_cs
*engine
;
1402 u64 acthd
[I915_NUM_ENGINES
];
1403 u32 seqno
[I915_NUM_ENGINES
];
1404 u32 instdone
[I915_NUM_INSTDONE_REG
];
1405 enum intel_engine_id id
;
1408 if (!i915
.enable_hangcheck
) {
1409 seq_printf(m
, "Hangcheck disabled\n");
1413 intel_runtime_pm_get(dev_priv
);
1415 for_each_engine_id(engine
, dev_priv
, id
) {
1416 acthd
[id
] = intel_engine_get_active_head(engine
);
1417 seqno
[id
] = intel_engine_get_seqno(engine
);
1420 i915_get_extra_instdone(dev_priv
, instdone
);
1422 intel_runtime_pm_put(dev_priv
);
1424 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1425 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1426 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1429 seq_printf(m
, "Hangcheck inactive\n");
1431 for_each_engine_id(engine
, dev_priv
, id
) {
1432 seq_printf(m
, "%s:\n", engine
->name
);
1433 seq_printf(m
, "\tseqno = %x [current %x, last %x]\n",
1434 engine
->hangcheck
.seqno
,
1436 engine
->last_submitted_seqno
);
1437 seq_printf(m
, "\twaiters? %d\n",
1438 intel_engine_has_waiter(engine
));
1439 seq_printf(m
, "\tuser interrupts = %lx [current %lx]\n",
1440 engine
->hangcheck
.user_interrupts
,
1441 READ_ONCE(engine
->breadcrumbs
.irq_wakeups
));
1442 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1443 (long long)engine
->hangcheck
.acthd
,
1444 (long long)acthd
[id
]);
1445 seq_printf(m
, "\tscore = %d\n", engine
->hangcheck
.score
);
1446 seq_printf(m
, "\taction = %d\n", engine
->hangcheck
.action
);
1448 if (engine
->id
== RCS
) {
1449 seq_puts(m
, "\tinstdone read =");
1451 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1452 seq_printf(m
, " 0x%08x", instdone
[j
]);
1454 seq_puts(m
, "\n\tinstdone accu =");
1456 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1457 seq_printf(m
, " 0x%08x",
1458 engine
->hangcheck
.instdone
[j
]);
1467 static int ironlake_drpc_info(struct seq_file
*m
)
1469 struct drm_info_node
*node
= m
->private;
1470 struct drm_device
*dev
= node
->minor
->dev
;
1471 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1472 u32 rgvmodectl
, rstdbyctl
;
1476 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1479 intel_runtime_pm_get(dev_priv
);
1481 rgvmodectl
= I915_READ(MEMMODECTL
);
1482 rstdbyctl
= I915_READ(RSTDBYCTL
);
1483 crstandvid
= I915_READ16(CRSTANDVID
);
1485 intel_runtime_pm_put(dev_priv
);
1486 mutex_unlock(&dev
->struct_mutex
);
1488 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1489 seq_printf(m
, "Boost freq: %d\n",
1490 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1491 MEMMODE_BOOST_FREQ_SHIFT
);
1492 seq_printf(m
, "HW control enabled: %s\n",
1493 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1494 seq_printf(m
, "SW control enabled: %s\n",
1495 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1496 seq_printf(m
, "Gated voltage change: %s\n",
1497 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1498 seq_printf(m
, "Starting frequency: P%d\n",
1499 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1500 seq_printf(m
, "Max P-state: P%d\n",
1501 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1502 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1503 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1504 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1505 seq_printf(m
, "Render standby enabled: %s\n",
1506 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1507 seq_puts(m
, "Current RS state: ");
1508 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1510 seq_puts(m
, "on\n");
1512 case RSX_STATUS_RC1
:
1513 seq_puts(m
, "RC1\n");
1515 case RSX_STATUS_RC1E
:
1516 seq_puts(m
, "RC1E\n");
1518 case RSX_STATUS_RS1
:
1519 seq_puts(m
, "RS1\n");
1521 case RSX_STATUS_RS2
:
1522 seq_puts(m
, "RS2 (RC6)\n");
1524 case RSX_STATUS_RS3
:
1525 seq_puts(m
, "RC3 (RC6+)\n");
1528 seq_puts(m
, "unknown\n");
1535 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1537 struct drm_info_node
*node
= m
->private;
1538 struct drm_device
*dev
= node
->minor
->dev
;
1539 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1540 struct intel_uncore_forcewake_domain
*fw_domain
;
1542 spin_lock_irq(&dev_priv
->uncore
.lock
);
1543 for_each_fw_domain(fw_domain
, dev_priv
) {
1544 seq_printf(m
, "%s.wake_count = %u\n",
1545 intel_uncore_forcewake_domain_to_str(fw_domain
->id
),
1546 fw_domain
->wake_count
);
1548 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1553 static int vlv_drpc_info(struct seq_file
*m
)
1555 struct drm_info_node
*node
= m
->private;
1556 struct drm_device
*dev
= node
->minor
->dev
;
1557 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1558 u32 rpmodectl1
, rcctl1
, pw_status
;
1560 intel_runtime_pm_get(dev_priv
);
1562 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1563 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1564 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1566 intel_runtime_pm_put(dev_priv
);
1568 seq_printf(m
, "Video Turbo Mode: %s\n",
1569 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1570 seq_printf(m
, "Turbo enabled: %s\n",
1571 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1572 seq_printf(m
, "HW control enabled: %s\n",
1573 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1574 seq_printf(m
, "SW control enabled: %s\n",
1575 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1576 GEN6_RP_MEDIA_SW_MODE
));
1577 seq_printf(m
, "RC6 Enabled: %s\n",
1578 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1579 GEN6_RC_CTL_EI_MODE(1))));
1580 seq_printf(m
, "Render Power Well: %s\n",
1581 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1582 seq_printf(m
, "Media Power Well: %s\n",
1583 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1585 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1586 I915_READ(VLV_GT_RENDER_RC6
));
1587 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1588 I915_READ(VLV_GT_MEDIA_RC6
));
1590 return i915_forcewake_domains(m
, NULL
);
1593 static int gen6_drpc_info(struct seq_file
*m
)
1595 struct drm_info_node
*node
= m
->private;
1596 struct drm_device
*dev
= node
->minor
->dev
;
1597 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1598 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1599 u32 gen9_powergate_enable
= 0, gen9_powergate_status
= 0;
1600 unsigned forcewake_count
;
1603 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1606 intel_runtime_pm_get(dev_priv
);
1608 spin_lock_irq(&dev_priv
->uncore
.lock
);
1609 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1610 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1612 if (forcewake_count
) {
1613 seq_puts(m
, "RC information inaccurate because somebody "
1614 "holds a forcewake reference \n");
1616 /* NB: we cannot use forcewake, else we read the wrong values */
1617 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1619 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1622 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1623 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1625 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1626 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1627 if (INTEL_INFO(dev
)->gen
>= 9) {
1628 gen9_powergate_enable
= I915_READ(GEN9_PG_ENABLE
);
1629 gen9_powergate_status
= I915_READ(GEN9_PWRGT_DOMAIN_STATUS
);
1631 mutex_unlock(&dev
->struct_mutex
);
1632 mutex_lock(&dev_priv
->rps
.hw_lock
);
1633 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1634 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1636 intel_runtime_pm_put(dev_priv
);
1638 seq_printf(m
, "Video Turbo Mode: %s\n",
1639 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1640 seq_printf(m
, "HW control enabled: %s\n",
1641 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1642 seq_printf(m
, "SW control enabled: %s\n",
1643 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1644 GEN6_RP_MEDIA_SW_MODE
));
1645 seq_printf(m
, "RC1e Enabled: %s\n",
1646 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1647 seq_printf(m
, "RC6 Enabled: %s\n",
1648 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1649 if (INTEL_INFO(dev
)->gen
>= 9) {
1650 seq_printf(m
, "Render Well Gating Enabled: %s\n",
1651 yesno(gen9_powergate_enable
& GEN9_RENDER_PG_ENABLE
));
1652 seq_printf(m
, "Media Well Gating Enabled: %s\n",
1653 yesno(gen9_powergate_enable
& GEN9_MEDIA_PG_ENABLE
));
1655 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1656 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1657 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1658 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1659 seq_puts(m
, "Current RC state: ");
1660 switch (gt_core_status
& GEN6_RCn_MASK
) {
1662 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1663 seq_puts(m
, "Core Power Down\n");
1665 seq_puts(m
, "on\n");
1668 seq_puts(m
, "RC3\n");
1671 seq_puts(m
, "RC6\n");
1674 seq_puts(m
, "RC7\n");
1677 seq_puts(m
, "Unknown\n");
1681 seq_printf(m
, "Core Power Down: %s\n",
1682 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1683 if (INTEL_INFO(dev
)->gen
>= 9) {
1684 seq_printf(m
, "Render Power Well: %s\n",
1685 (gen9_powergate_status
&
1686 GEN9_PWRGT_RENDER_STATUS_MASK
) ? "Up" : "Down");
1687 seq_printf(m
, "Media Power Well: %s\n",
1688 (gen9_powergate_status
&
1689 GEN9_PWRGT_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1692 /* Not exactly sure what this is */
1693 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1694 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1695 seq_printf(m
, "RC6 residency since boot: %u\n",
1696 I915_READ(GEN6_GT_GFX_RC6
));
1697 seq_printf(m
, "RC6+ residency since boot: %u\n",
1698 I915_READ(GEN6_GT_GFX_RC6p
));
1699 seq_printf(m
, "RC6++ residency since boot: %u\n",
1700 I915_READ(GEN6_GT_GFX_RC6pp
));
1702 seq_printf(m
, "RC6 voltage: %dmV\n",
1703 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1704 seq_printf(m
, "RC6+ voltage: %dmV\n",
1705 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1706 seq_printf(m
, "RC6++ voltage: %dmV\n",
1707 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1708 return i915_forcewake_domains(m
, NULL
);
1711 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1713 struct drm_info_node
*node
= m
->private;
1714 struct drm_device
*dev
= node
->minor
->dev
;
1716 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1717 return vlv_drpc_info(m
);
1718 else if (INTEL_INFO(dev
)->gen
>= 6)
1719 return gen6_drpc_info(m
);
1721 return ironlake_drpc_info(m
);
1724 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1726 struct drm_info_node
*node
= m
->private;
1727 struct drm_device
*dev
= node
->minor
->dev
;
1728 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1730 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1731 dev_priv
->fb_tracking
.busy_bits
);
1733 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1734 dev_priv
->fb_tracking
.flip_bits
);
1739 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1741 struct drm_info_node
*node
= m
->private;
1742 struct drm_device
*dev
= node
->minor
->dev
;
1743 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1745 if (!HAS_FBC(dev
)) {
1746 seq_puts(m
, "FBC unsupported on this chipset\n");
1750 intel_runtime_pm_get(dev_priv
);
1751 mutex_lock(&dev_priv
->fbc
.lock
);
1753 if (intel_fbc_is_active(dev_priv
))
1754 seq_puts(m
, "FBC enabled\n");
1756 seq_printf(m
, "FBC disabled: %s\n",
1757 dev_priv
->fbc
.no_fbc_reason
);
1759 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1760 seq_printf(m
, "Compressing: %s\n",
1761 yesno(I915_READ(FBC_STATUS2
) &
1762 FBC_COMPRESSION_MASK
));
1764 mutex_unlock(&dev_priv
->fbc
.lock
);
1765 intel_runtime_pm_put(dev_priv
);
1770 static int i915_fbc_fc_get(void *data
, u64
*val
)
1772 struct drm_device
*dev
= data
;
1773 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1775 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1778 *val
= dev_priv
->fbc
.false_color
;
1783 static int i915_fbc_fc_set(void *data
, u64 val
)
1785 struct drm_device
*dev
= data
;
1786 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1789 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1792 mutex_lock(&dev_priv
->fbc
.lock
);
1794 reg
= I915_READ(ILK_DPFC_CONTROL
);
1795 dev_priv
->fbc
.false_color
= val
;
1797 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1798 (reg
| FBC_CTL_FALSE_COLOR
) :
1799 (reg
& ~FBC_CTL_FALSE_COLOR
));
1801 mutex_unlock(&dev_priv
->fbc
.lock
);
1805 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1806 i915_fbc_fc_get
, i915_fbc_fc_set
,
1809 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1811 struct drm_info_node
*node
= m
->private;
1812 struct drm_device
*dev
= node
->minor
->dev
;
1813 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1815 if (!HAS_IPS(dev
)) {
1816 seq_puts(m
, "not supported\n");
1820 intel_runtime_pm_get(dev_priv
);
1822 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1823 yesno(i915
.enable_ips
));
1825 if (INTEL_INFO(dev
)->gen
>= 8) {
1826 seq_puts(m
, "Currently: unknown\n");
1828 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1829 seq_puts(m
, "Currently: enabled\n");
1831 seq_puts(m
, "Currently: disabled\n");
1834 intel_runtime_pm_put(dev_priv
);
1839 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1841 struct drm_info_node
*node
= m
->private;
1842 struct drm_device
*dev
= node
->minor
->dev
;
1843 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1844 bool sr_enabled
= false;
1846 intel_runtime_pm_get(dev_priv
);
1848 if (HAS_PCH_SPLIT(dev
))
1849 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1850 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1851 IS_I945G(dev
) || IS_I945GM(dev
))
1852 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1853 else if (IS_I915GM(dev
))
1854 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1855 else if (IS_PINEVIEW(dev
))
1856 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1857 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1858 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1860 intel_runtime_pm_put(dev_priv
);
1862 seq_printf(m
, "self-refresh: %s\n",
1863 sr_enabled
? "enabled" : "disabled");
1868 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1870 struct drm_info_node
*node
= m
->private;
1871 struct drm_device
*dev
= node
->minor
->dev
;
1872 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1873 unsigned long temp
, chipset
, gfx
;
1879 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1883 temp
= i915_mch_val(dev_priv
);
1884 chipset
= i915_chipset_val(dev_priv
);
1885 gfx
= i915_gfx_val(dev_priv
);
1886 mutex_unlock(&dev
->struct_mutex
);
1888 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1889 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1890 seq_printf(m
, "GFX power: %ld\n", gfx
);
1891 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1896 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1898 struct drm_info_node
*node
= m
->private;
1899 struct drm_device
*dev
= node
->minor
->dev
;
1900 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1902 int gpu_freq
, ia_freq
;
1903 unsigned int max_gpu_freq
, min_gpu_freq
;
1905 if (!HAS_CORE_RING_FREQ(dev
)) {
1906 seq_puts(m
, "unsupported on this chipset\n");
1910 intel_runtime_pm_get(dev_priv
);
1912 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1916 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1917 /* Convert GT frequency to 50 HZ units */
1919 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1921 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1923 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1924 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1927 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1929 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1931 sandybridge_pcode_read(dev_priv
,
1932 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1934 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1935 intel_gpu_freq(dev_priv
, (gpu_freq
*
1936 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1937 GEN9_FREQ_SCALER
: 1))),
1938 ((ia_freq
>> 0) & 0xff) * 100,
1939 ((ia_freq
>> 8) & 0xff) * 100);
1942 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1945 intel_runtime_pm_put(dev_priv
);
1949 static int i915_opregion(struct seq_file
*m
, void *unused
)
1951 struct drm_info_node
*node
= m
->private;
1952 struct drm_device
*dev
= node
->minor
->dev
;
1953 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1954 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1957 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1961 if (opregion
->header
)
1962 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1964 mutex_unlock(&dev
->struct_mutex
);
1970 static int i915_vbt(struct seq_file
*m
, void *unused
)
1972 struct drm_info_node
*node
= m
->private;
1973 struct drm_device
*dev
= node
->minor
->dev
;
1974 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1975 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1978 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1983 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1985 struct drm_info_node
*node
= m
->private;
1986 struct drm_device
*dev
= node
->minor
->dev
;
1987 struct intel_framebuffer
*fbdev_fb
= NULL
;
1988 struct drm_framebuffer
*drm_fb
;
1991 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1995 #ifdef CONFIG_DRM_FBDEV_EMULATION
1996 if (to_i915(dev
)->fbdev
) {
1997 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1999 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2000 fbdev_fb
->base
.width
,
2001 fbdev_fb
->base
.height
,
2002 fbdev_fb
->base
.depth
,
2003 fbdev_fb
->base
.bits_per_pixel
,
2004 fbdev_fb
->base
.modifier
[0],
2005 drm_framebuffer_read_refcount(&fbdev_fb
->base
));
2006 describe_obj(m
, fbdev_fb
->obj
);
2011 mutex_lock(&dev
->mode_config
.fb_lock
);
2012 drm_for_each_fb(drm_fb
, dev
) {
2013 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
2017 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2021 fb
->base
.bits_per_pixel
,
2022 fb
->base
.modifier
[0],
2023 drm_framebuffer_read_refcount(&fb
->base
));
2024 describe_obj(m
, fb
->obj
);
2027 mutex_unlock(&dev
->mode_config
.fb_lock
);
2028 mutex_unlock(&dev
->struct_mutex
);
2033 static void describe_ctx_ring(struct seq_file
*m
, struct intel_ring
*ring
)
2035 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2036 ring
->space
, ring
->head
, ring
->tail
,
2037 ring
->last_retired_head
);
2040 static int i915_context_status(struct seq_file
*m
, void *unused
)
2042 struct drm_info_node
*node
= m
->private;
2043 struct drm_device
*dev
= node
->minor
->dev
;
2044 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2045 struct intel_engine_cs
*engine
;
2046 struct i915_gem_context
*ctx
;
2049 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2053 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2054 seq_printf(m
, "HW context %u ", ctx
->hw_id
);
2055 if (IS_ERR(ctx
->file_priv
)) {
2056 seq_puts(m
, "(deleted) ");
2057 } else if (ctx
->file_priv
) {
2058 struct pid
*pid
= ctx
->file_priv
->file
->pid
;
2059 struct task_struct
*task
;
2061 task
= get_pid_task(pid
, PIDTYPE_PID
);
2063 seq_printf(m
, "(%s [%d]) ",
2064 task
->comm
, task
->pid
);
2065 put_task_struct(task
);
2068 seq_puts(m
, "(kernel) ");
2071 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
2074 for_each_engine(engine
, dev_priv
) {
2075 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2077 seq_printf(m
, "%s: ", engine
->name
);
2078 seq_putc(m
, ce
->initialised
? 'I' : 'i');
2080 describe_obj(m
, ce
->state
);
2082 describe_ctx_ring(m
, ce
->ring
);
2089 mutex_unlock(&dev
->struct_mutex
);
2094 static void i915_dump_lrc_obj(struct seq_file
*m
,
2095 struct i915_gem_context
*ctx
,
2096 struct intel_engine_cs
*engine
)
2098 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
2100 uint32_t *reg_state
;
2102 unsigned long ggtt_offset
= 0;
2104 seq_printf(m
, "CONTEXT: %s %u\n", engine
->name
, ctx
->hw_id
);
2106 if (ctx_obj
== NULL
) {
2107 seq_puts(m
, "\tNot allocated\n");
2111 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
2112 seq_puts(m
, "\tNot bound in GGTT\n");
2114 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2116 if (i915_gem_object_get_pages(ctx_obj
)) {
2117 seq_puts(m
, "\tFailed to get pages for context object\n");
2121 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2122 if (!WARN_ON(page
== NULL
)) {
2123 reg_state
= kmap_atomic(page
);
2125 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2126 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2127 ggtt_offset
+ 4096 + (j
* 4),
2128 reg_state
[j
], reg_state
[j
+ 1],
2129 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2131 kunmap_atomic(reg_state
);
2137 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2139 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2140 struct drm_device
*dev
= node
->minor
->dev
;
2141 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2142 struct intel_engine_cs
*engine
;
2143 struct i915_gem_context
*ctx
;
2146 if (!i915
.enable_execlists
) {
2147 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2151 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2155 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2156 for_each_engine(engine
, dev_priv
)
2157 i915_dump_lrc_obj(m
, ctx
, engine
);
2159 mutex_unlock(&dev
->struct_mutex
);
2164 static int i915_execlists(struct seq_file
*m
, void *data
)
2166 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2167 struct drm_device
*dev
= node
->minor
->dev
;
2168 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2169 struct intel_engine_cs
*engine
;
2175 struct list_head
*cursor
;
2178 if (!i915
.enable_execlists
) {
2179 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2183 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2187 intel_runtime_pm_get(dev_priv
);
2189 for_each_engine(engine
, dev_priv
) {
2190 struct drm_i915_gem_request
*head_req
= NULL
;
2193 seq_printf(m
, "%s\n", engine
->name
);
2195 status
= I915_READ(RING_EXECLIST_STATUS_LO(engine
));
2196 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(engine
));
2197 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2200 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(engine
));
2201 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2203 read_pointer
= engine
->next_context_status_buffer
;
2204 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
2205 if (read_pointer
> write_pointer
)
2206 write_pointer
+= GEN8_CSB_ENTRIES
;
2207 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2208 read_pointer
, write_pointer
);
2210 for (i
= 0; i
< GEN8_CSB_ENTRIES
; i
++) {
2211 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine
, i
));
2212 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine
, i
));
2214 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2218 spin_lock_bh(&engine
->execlist_lock
);
2219 list_for_each(cursor
, &engine
->execlist_queue
)
2221 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
2222 struct drm_i915_gem_request
,
2224 spin_unlock_bh(&engine
->execlist_lock
);
2226 seq_printf(m
, "\t%d requests in queue\n", count
);
2228 seq_printf(m
, "\tHead request context: %u\n",
2229 head_req
->ctx
->hw_id
);
2230 seq_printf(m
, "\tHead request tail: %u\n",
2237 intel_runtime_pm_put(dev_priv
);
2238 mutex_unlock(&dev
->struct_mutex
);
2243 static const char *swizzle_string(unsigned swizzle
)
2246 case I915_BIT_6_SWIZZLE_NONE
:
2248 case I915_BIT_6_SWIZZLE_9
:
2250 case I915_BIT_6_SWIZZLE_9_10
:
2251 return "bit9/bit10";
2252 case I915_BIT_6_SWIZZLE_9_11
:
2253 return "bit9/bit11";
2254 case I915_BIT_6_SWIZZLE_9_10_11
:
2255 return "bit9/bit10/bit11";
2256 case I915_BIT_6_SWIZZLE_9_17
:
2257 return "bit9/bit17";
2258 case I915_BIT_6_SWIZZLE_9_10_17
:
2259 return "bit9/bit10/bit17";
2260 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2267 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2269 struct drm_info_node
*node
= m
->private;
2270 struct drm_device
*dev
= node
->minor
->dev
;
2271 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2274 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2277 intel_runtime_pm_get(dev_priv
);
2279 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2280 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2281 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2282 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2284 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2285 seq_printf(m
, "DDC = 0x%08x\n",
2287 seq_printf(m
, "DDC2 = 0x%08x\n",
2289 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2290 I915_READ16(C0DRB3
));
2291 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2292 I915_READ16(C1DRB3
));
2293 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2294 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2295 I915_READ(MAD_DIMM_C0
));
2296 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2297 I915_READ(MAD_DIMM_C1
));
2298 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2299 I915_READ(MAD_DIMM_C2
));
2300 seq_printf(m
, "TILECTL = 0x%08x\n",
2301 I915_READ(TILECTL
));
2302 if (INTEL_INFO(dev
)->gen
>= 8)
2303 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2304 I915_READ(GAMTARBMODE
));
2306 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2307 I915_READ(ARB_MODE
));
2308 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2309 I915_READ(DISP_ARB_CTL
));
2312 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2313 seq_puts(m
, "L-shaped memory detected\n");
2315 intel_runtime_pm_put(dev_priv
);
2316 mutex_unlock(&dev
->struct_mutex
);
2321 static int per_file_ctx(int id
, void *ptr
, void *data
)
2323 struct i915_gem_context
*ctx
= ptr
;
2324 struct seq_file
*m
= data
;
2325 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2328 seq_printf(m
, " no ppgtt for context %d\n",
2333 if (i915_gem_context_is_default(ctx
))
2334 seq_puts(m
, " default context:\n");
2336 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2337 ppgtt
->debug_dump(ppgtt
, m
);
2342 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2344 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2345 struct intel_engine_cs
*engine
;
2346 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2352 for_each_engine(engine
, dev_priv
) {
2353 seq_printf(m
, "%s\n", engine
->name
);
2354 for (i
= 0; i
< 4; i
++) {
2355 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(engine
, i
));
2357 pdp
|= I915_READ(GEN8_RING_PDP_LDW(engine
, i
));
2358 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2363 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2365 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2366 struct intel_engine_cs
*engine
;
2368 if (IS_GEN6(dev_priv
))
2369 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2371 for_each_engine(engine
, dev_priv
) {
2372 seq_printf(m
, "%s\n", engine
->name
);
2373 if (IS_GEN7(dev_priv
))
2374 seq_printf(m
, "GFX_MODE: 0x%08x\n",
2375 I915_READ(RING_MODE_GEN7(engine
)));
2376 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n",
2377 I915_READ(RING_PP_DIR_BASE(engine
)));
2378 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n",
2379 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
2380 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n",
2381 I915_READ(RING_PP_DIR_DCLV(engine
)));
2383 if (dev_priv
->mm
.aliasing_ppgtt
) {
2384 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2386 seq_puts(m
, "aliasing PPGTT:\n");
2387 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2389 ppgtt
->debug_dump(ppgtt
, m
);
2392 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2395 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2397 struct drm_info_node
*node
= m
->private;
2398 struct drm_device
*dev
= node
->minor
->dev
;
2399 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2400 struct drm_file
*file
;
2402 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2405 intel_runtime_pm_get(dev_priv
);
2407 if (INTEL_INFO(dev
)->gen
>= 8)
2408 gen8_ppgtt_info(m
, dev
);
2409 else if (INTEL_INFO(dev
)->gen
>= 6)
2410 gen6_ppgtt_info(m
, dev
);
2412 mutex_lock(&dev
->filelist_mutex
);
2413 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2414 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2415 struct task_struct
*task
;
2417 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2422 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2423 put_task_struct(task
);
2424 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2425 (void *)(unsigned long)m
);
2428 mutex_unlock(&dev
->filelist_mutex
);
2430 intel_runtime_pm_put(dev_priv
);
2431 mutex_unlock(&dev
->struct_mutex
);
2436 static int count_irq_waiters(struct drm_i915_private
*i915
)
2438 struct intel_engine_cs
*engine
;
2441 for_each_engine(engine
, i915
)
2442 count
+= intel_engine_has_waiter(engine
);
2447 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2449 struct drm_info_node
*node
= m
->private;
2450 struct drm_device
*dev
= node
->minor
->dev
;
2451 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2452 struct drm_file
*file
;
2454 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2455 seq_printf(m
, "GPU busy? %s [%x]\n",
2456 yesno(dev_priv
->gt
.awake
), dev_priv
->gt
.active_engines
);
2457 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2458 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2459 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2460 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2461 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2462 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2463 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2465 mutex_lock(&dev
->filelist_mutex
);
2466 spin_lock(&dev_priv
->rps
.client_lock
);
2467 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2468 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2469 struct task_struct
*task
;
2472 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2473 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2474 task
? task
->comm
: "<unknown>",
2475 task
? task
->pid
: -1,
2476 file_priv
->rps
.boosts
,
2477 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2480 seq_printf(m
, "Kernel (anonymous) boosts: %d\n", dev_priv
->rps
.boosts
);
2481 spin_unlock(&dev_priv
->rps
.client_lock
);
2482 mutex_unlock(&dev
->filelist_mutex
);
2487 static int i915_llc(struct seq_file
*m
, void *data
)
2489 struct drm_info_node
*node
= m
->private;
2490 struct drm_device
*dev
= node
->minor
->dev
;
2491 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2492 const bool edram
= INTEL_GEN(dev_priv
) > 8;
2494 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2495 seq_printf(m
, "%s: %lluMB\n", edram
? "eDRAM" : "eLLC",
2496 intel_uncore_edram_size(dev_priv
)/1024/1024);
2501 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2503 struct drm_info_node
*node
= m
->private;
2504 struct drm_i915_private
*dev_priv
= to_i915(node
->minor
->dev
);
2505 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2508 if (!HAS_GUC_UCODE(dev_priv
))
2511 seq_printf(m
, "GuC firmware status:\n");
2512 seq_printf(m
, "\tpath: %s\n",
2513 guc_fw
->guc_fw_path
);
2514 seq_printf(m
, "\tfetch: %s\n",
2515 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2516 seq_printf(m
, "\tload: %s\n",
2517 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2518 seq_printf(m
, "\tversion wanted: %d.%d\n",
2519 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2520 seq_printf(m
, "\tversion found: %d.%d\n",
2521 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2522 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2523 guc_fw
->header_offset
, guc_fw
->header_size
);
2524 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2525 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2526 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2527 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2529 tmp
= I915_READ(GUC_STATUS
);
2531 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2532 seq_printf(m
, "\tBootrom status = 0x%x\n",
2533 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2534 seq_printf(m
, "\tuKernel status = 0x%x\n",
2535 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2536 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2537 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2538 seq_puts(m
, "\nScratch registers:\n");
2539 for (i
= 0; i
< 16; i
++)
2540 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2545 static void i915_guc_client_info(struct seq_file
*m
,
2546 struct drm_i915_private
*dev_priv
,
2547 struct i915_guc_client
*client
)
2549 struct intel_engine_cs
*engine
;
2552 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2553 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2554 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2555 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2556 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2557 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2559 seq_printf(m
, "\tWork queue full: %u\n", client
->no_wq_space
);
2560 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2561 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2562 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2564 for_each_engine(engine
, dev_priv
) {
2565 seq_printf(m
, "\tSubmissions: %llu %s\n",
2566 client
->submissions
[engine
->id
],
2568 tot
+= client
->submissions
[engine
->id
];
2570 seq_printf(m
, "\tTotal: %llu\n", tot
);
2573 static int i915_guc_info(struct seq_file
*m
, void *data
)
2575 struct drm_info_node
*node
= m
->private;
2576 struct drm_device
*dev
= node
->minor
->dev
;
2577 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2578 struct intel_guc guc
;
2579 struct i915_guc_client client
= {};
2580 struct intel_engine_cs
*engine
;
2583 if (!HAS_GUC_SCHED(dev_priv
))
2586 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2589 /* Take a local copy of the GuC data, so we can dump it at leisure */
2590 guc
= dev_priv
->guc
;
2591 if (guc
.execbuf_client
)
2592 client
= *guc
.execbuf_client
;
2594 mutex_unlock(&dev
->struct_mutex
);
2596 seq_printf(m
, "Doorbell map:\n");
2597 seq_printf(m
, "\t%*pb\n", GUC_MAX_DOORBELLS
, guc
.doorbell_bitmap
);
2598 seq_printf(m
, "Doorbell next cacheline: 0x%x\n\n", guc
.db_cacheline
);
2600 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2601 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2602 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2603 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2604 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2606 seq_printf(m
, "\nGuC submissions:\n");
2607 for_each_engine(engine
, dev_priv
) {
2608 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2609 engine
->name
, guc
.submissions
[engine
->id
],
2610 guc
.last_seqno
[engine
->id
]);
2611 total
+= guc
.submissions
[engine
->id
];
2613 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2615 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2616 i915_guc_client_info(m
, dev_priv
, &client
);
2618 /* Add more as required ... */
2623 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2625 struct drm_info_node
*node
= m
->private;
2626 struct drm_device
*dev
= node
->minor
->dev
;
2627 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2628 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2635 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2636 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2638 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2639 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2640 *(log
+ i
), *(log
+ i
+ 1),
2641 *(log
+ i
+ 2), *(log
+ i
+ 3));
2651 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2653 struct drm_info_node
*node
= m
->private;
2654 struct drm_device
*dev
= node
->minor
->dev
;
2655 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2659 bool enabled
= false;
2661 if (!HAS_PSR(dev
)) {
2662 seq_puts(m
, "PSR not supported\n");
2666 intel_runtime_pm_get(dev_priv
);
2668 mutex_lock(&dev_priv
->psr
.lock
);
2669 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2670 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2671 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2672 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2673 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2674 dev_priv
->psr
.busy_frontbuffer_bits
);
2675 seq_printf(m
, "Re-enable work scheduled: %s\n",
2676 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2679 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2681 for_each_pipe(dev_priv
, pipe
) {
2682 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2683 VLV_EDP_PSR_CURR_STATE_MASK
;
2684 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2685 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2690 seq_printf(m
, "Main link in standby mode: %s\n",
2691 yesno(dev_priv
->psr
.link_standby
));
2693 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2696 for_each_pipe(dev_priv
, pipe
) {
2697 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2698 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2699 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2704 * VLV/CHV PSR has no kind of performance counter
2705 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2707 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2708 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2709 EDP_PSR_PERF_CNT_MASK
;
2711 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2713 mutex_unlock(&dev_priv
->psr
.lock
);
2715 intel_runtime_pm_put(dev_priv
);
2719 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2721 struct drm_info_node
*node
= m
->private;
2722 struct drm_device
*dev
= node
->minor
->dev
;
2723 struct intel_connector
*connector
;
2724 struct intel_dp
*intel_dp
= NULL
;
2728 drm_modeset_lock_all(dev
);
2729 for_each_intel_connector(dev
, connector
) {
2730 struct drm_crtc
*crtc
;
2732 if (!connector
->base
.state
->best_encoder
)
2735 crtc
= connector
->base
.state
->crtc
;
2736 if (!crtc
->state
->active
)
2739 if (connector
->base
.connector_type
!= DRM_MODE_CONNECTOR_eDP
)
2742 intel_dp
= enc_to_intel_dp(connector
->base
.state
->best_encoder
);
2744 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2748 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2749 crc
[0], crc
[1], crc
[2],
2750 crc
[3], crc
[4], crc
[5]);
2755 drm_modeset_unlock_all(dev
);
2759 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2761 struct drm_info_node
*node
= m
->private;
2762 struct drm_device
*dev
= node
->minor
->dev
;
2763 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2767 if (INTEL_INFO(dev
)->gen
< 6)
2770 intel_runtime_pm_get(dev_priv
);
2772 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2773 power
= (power
& 0x1f00) >> 8;
2774 units
= 1000000 / (1 << power
); /* convert to uJ */
2775 power
= I915_READ(MCH_SECP_NRG_STTS
);
2778 intel_runtime_pm_put(dev_priv
);
2780 seq_printf(m
, "%llu", (long long unsigned)power
);
2785 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2787 struct drm_info_node
*node
= m
->private;
2788 struct drm_device
*dev
= node
->minor
->dev
;
2789 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2791 if (!HAS_RUNTIME_PM(dev_priv
))
2792 seq_puts(m
, "Runtime power management not supported\n");
2794 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->gt
.awake
));
2795 seq_printf(m
, "IRQs disabled: %s\n",
2796 yesno(!intel_irqs_enabled(dev_priv
)));
2798 seq_printf(m
, "Usage count: %d\n",
2799 atomic_read(&dev
->dev
->power
.usage_count
));
2801 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2803 seq_printf(m
, "PCI device power state: %s [%d]\n",
2804 pci_power_name(dev_priv
->drm
.pdev
->current_state
),
2805 dev_priv
->drm
.pdev
->current_state
);
2810 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2812 struct drm_info_node
*node
= m
->private;
2813 struct drm_device
*dev
= node
->minor
->dev
;
2814 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2815 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2818 mutex_lock(&power_domains
->lock
);
2820 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2821 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2822 struct i915_power_well
*power_well
;
2823 enum intel_display_power_domain power_domain
;
2825 power_well
= &power_domains
->power_wells
[i
];
2826 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2829 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2831 if (!(BIT(power_domain
) & power_well
->domains
))
2834 seq_printf(m
, " %-23s %d\n",
2835 intel_display_power_domain_str(power_domain
),
2836 power_domains
->domain_use_count
[power_domain
]);
2840 mutex_unlock(&power_domains
->lock
);
2845 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2847 struct drm_info_node
*node
= m
->private;
2848 struct drm_device
*dev
= node
->minor
->dev
;
2849 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2850 struct intel_csr
*csr
;
2852 if (!HAS_CSR(dev
)) {
2853 seq_puts(m
, "not supported\n");
2857 csr
= &dev_priv
->csr
;
2859 intel_runtime_pm_get(dev_priv
);
2861 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2862 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2864 if (!csr
->dmc_payload
)
2867 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2868 CSR_VERSION_MINOR(csr
->version
));
2870 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2871 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2872 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2873 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2874 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2875 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2876 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2877 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2881 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2882 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2883 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2885 intel_runtime_pm_put(dev_priv
);
2890 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2891 struct drm_display_mode
*mode
)
2895 for (i
= 0; i
< tabs
; i
++)
2898 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2899 mode
->base
.id
, mode
->name
,
2900 mode
->vrefresh
, mode
->clock
,
2901 mode
->hdisplay
, mode
->hsync_start
,
2902 mode
->hsync_end
, mode
->htotal
,
2903 mode
->vdisplay
, mode
->vsync_start
,
2904 mode
->vsync_end
, mode
->vtotal
,
2905 mode
->type
, mode
->flags
);
2908 static void intel_encoder_info(struct seq_file
*m
,
2909 struct intel_crtc
*intel_crtc
,
2910 struct intel_encoder
*intel_encoder
)
2912 struct drm_info_node
*node
= m
->private;
2913 struct drm_device
*dev
= node
->minor
->dev
;
2914 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2915 struct intel_connector
*intel_connector
;
2916 struct drm_encoder
*encoder
;
2918 encoder
= &intel_encoder
->base
;
2919 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2920 encoder
->base
.id
, encoder
->name
);
2921 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2922 struct drm_connector
*connector
= &intel_connector
->base
;
2923 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2926 drm_get_connector_status_name(connector
->status
));
2927 if (connector
->status
== connector_status_connected
) {
2928 struct drm_display_mode
*mode
= &crtc
->mode
;
2929 seq_printf(m
, ", mode:\n");
2930 intel_seq_print_mode(m
, 2, mode
);
2937 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2939 struct drm_info_node
*node
= m
->private;
2940 struct drm_device
*dev
= node
->minor
->dev
;
2941 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2942 struct intel_encoder
*intel_encoder
;
2943 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2944 struct drm_framebuffer
*fb
= plane_state
->fb
;
2947 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2948 fb
->base
.id
, plane_state
->src_x
>> 16,
2949 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2951 seq_puts(m
, "\tprimary plane disabled\n");
2952 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2953 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2956 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2958 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2960 seq_printf(m
, "\tfixed mode:\n");
2961 intel_seq_print_mode(m
, 2, mode
);
2964 static void intel_dp_info(struct seq_file
*m
,
2965 struct intel_connector
*intel_connector
)
2967 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2968 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2970 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2971 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2972 if (intel_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)
2973 intel_panel_info(m
, &intel_connector
->panel
);
2976 static void intel_hdmi_info(struct seq_file
*m
,
2977 struct intel_connector
*intel_connector
)
2979 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2980 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2982 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2985 static void intel_lvds_info(struct seq_file
*m
,
2986 struct intel_connector
*intel_connector
)
2988 intel_panel_info(m
, &intel_connector
->panel
);
2991 static void intel_connector_info(struct seq_file
*m
,
2992 struct drm_connector
*connector
)
2994 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2995 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2996 struct drm_display_mode
*mode
;
2998 seq_printf(m
, "connector %d: type %s, status: %s\n",
2999 connector
->base
.id
, connector
->name
,
3000 drm_get_connector_status_name(connector
->status
));
3001 if (connector
->status
== connector_status_connected
) {
3002 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
3003 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
3004 connector
->display_info
.width_mm
,
3005 connector
->display_info
.height_mm
);
3006 seq_printf(m
, "\tsubpixel order: %s\n",
3007 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
3008 seq_printf(m
, "\tCEA rev: %d\n",
3009 connector
->display_info
.cea_rev
);
3012 if (!intel_encoder
|| intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
3015 switch (connector
->connector_type
) {
3016 case DRM_MODE_CONNECTOR_DisplayPort
:
3017 case DRM_MODE_CONNECTOR_eDP
:
3018 intel_dp_info(m
, intel_connector
);
3020 case DRM_MODE_CONNECTOR_LVDS
:
3021 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
3022 intel_lvds_info(m
, intel_connector
);
3024 case DRM_MODE_CONNECTOR_HDMIA
:
3025 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
||
3026 intel_encoder
->type
== INTEL_OUTPUT_UNKNOWN
)
3027 intel_hdmi_info(m
, intel_connector
);
3033 seq_printf(m
, "\tmodes:\n");
3034 list_for_each_entry(mode
, &connector
->modes
, head
)
3035 intel_seq_print_mode(m
, 2, mode
);
3038 static bool cursor_active(struct drm_device
*dev
, int pipe
)
3040 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3043 if (IS_845G(dev
) || IS_I865G(dev
))
3044 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
3046 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
3051 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
3053 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3056 pos
= I915_READ(CURPOS(pipe
));
3058 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
3059 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
3062 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
3063 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
3066 return cursor_active(dev
, pipe
);
3069 static const char *plane_type(enum drm_plane_type type
)
3072 case DRM_PLANE_TYPE_OVERLAY
:
3074 case DRM_PLANE_TYPE_PRIMARY
:
3076 case DRM_PLANE_TYPE_CURSOR
:
3079 * Deliberately omitting default: to generate compiler warnings
3080 * when a new drm_plane_type gets added.
3087 static const char *plane_rotation(unsigned int rotation
)
3089 static char buf
[48];
3091 * According to doc only one DRM_ROTATE_ is allowed but this
3092 * will print them all to visualize if the values are misused
3094 snprintf(buf
, sizeof(buf
),
3095 "%s%s%s%s%s%s(0x%08x)",
3096 (rotation
& DRM_ROTATE_0
) ? "0 " : "",
3097 (rotation
& DRM_ROTATE_90
) ? "90 " : "",
3098 (rotation
& DRM_ROTATE_180
) ? "180 " : "",
3099 (rotation
& DRM_ROTATE_270
) ? "270 " : "",
3100 (rotation
& DRM_REFLECT_X
) ? "FLIPX " : "",
3101 (rotation
& DRM_REFLECT_Y
) ? "FLIPY " : "",
3107 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3109 struct drm_info_node
*node
= m
->private;
3110 struct drm_device
*dev
= node
->minor
->dev
;
3111 struct intel_plane
*intel_plane
;
3113 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3114 struct drm_plane_state
*state
;
3115 struct drm_plane
*plane
= &intel_plane
->base
;
3117 if (!plane
->state
) {
3118 seq_puts(m
, "plane->state is NULL!\n");
3122 state
= plane
->state
;
3124 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3126 plane_type(intel_plane
->base
.type
),
3127 state
->crtc_x
, state
->crtc_y
,
3128 state
->crtc_w
, state
->crtc_h
,
3129 (state
->src_x
>> 16),
3130 ((state
->src_x
& 0xffff) * 15625) >> 10,
3131 (state
->src_y
>> 16),
3132 ((state
->src_y
& 0xffff) * 15625) >> 10,
3133 (state
->src_w
>> 16),
3134 ((state
->src_w
& 0xffff) * 15625) >> 10,
3135 (state
->src_h
>> 16),
3136 ((state
->src_h
& 0xffff) * 15625) >> 10,
3137 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3138 plane_rotation(state
->rotation
));
3142 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3144 struct intel_crtc_state
*pipe_config
;
3145 int num_scalers
= intel_crtc
->num_scalers
;
3148 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3150 /* Not all platformas have a scaler */
3152 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3154 pipe_config
->scaler_state
.scaler_users
,
3155 pipe_config
->scaler_state
.scaler_id
);
3157 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3158 struct intel_scaler
*sc
=
3159 &pipe_config
->scaler_state
.scalers
[i
];
3161 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3162 i
, yesno(sc
->in_use
), sc
->mode
);
3166 seq_puts(m
, "\tNo scalers available on this platform\n");
3170 static int i915_display_info(struct seq_file
*m
, void *unused
)
3172 struct drm_info_node
*node
= m
->private;
3173 struct drm_device
*dev
= node
->minor
->dev
;
3174 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3175 struct intel_crtc
*crtc
;
3176 struct drm_connector
*connector
;
3178 intel_runtime_pm_get(dev_priv
);
3179 drm_modeset_lock_all(dev
);
3180 seq_printf(m
, "CRTC info\n");
3181 seq_printf(m
, "---------\n");
3182 for_each_intel_crtc(dev
, crtc
) {
3184 struct intel_crtc_state
*pipe_config
;
3187 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3189 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3190 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3191 yesno(pipe_config
->base
.active
),
3192 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3193 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3195 if (pipe_config
->base
.active
) {
3196 intel_crtc_info(m
, crtc
);
3198 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3199 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3200 yesno(crtc
->cursor_base
),
3201 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3202 crtc
->base
.cursor
->state
->crtc_h
,
3203 crtc
->cursor_addr
, yesno(active
));
3204 intel_scaler_info(m
, crtc
);
3205 intel_plane_info(m
, crtc
);
3208 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3209 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3210 yesno(!crtc
->pch_fifo_underrun_disabled
));
3213 seq_printf(m
, "\n");
3214 seq_printf(m
, "Connector info\n");
3215 seq_printf(m
, "--------------\n");
3216 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3217 intel_connector_info(m
, connector
);
3219 drm_modeset_unlock_all(dev
);
3220 intel_runtime_pm_put(dev_priv
);
3225 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3227 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3228 struct drm_device
*dev
= node
->minor
->dev
;
3229 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3230 struct intel_engine_cs
*engine
;
3231 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3232 enum intel_engine_id id
;
3235 if (!i915
.semaphores
) {
3236 seq_puts(m
, "Semaphores are disabled\n");
3240 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3243 intel_runtime_pm_get(dev_priv
);
3245 if (IS_BROADWELL(dev
)) {
3249 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3251 seqno
= (uint64_t *)kmap_atomic(page
);
3252 for_each_engine_id(engine
, dev_priv
, id
) {
3255 seq_printf(m
, "%s\n", engine
->name
);
3257 seq_puts(m
, " Last signal:");
3258 for (j
= 0; j
< num_rings
; j
++) {
3259 offset
= id
* I915_NUM_ENGINES
+ j
;
3260 seq_printf(m
, "0x%08llx (0x%02llx) ",
3261 seqno
[offset
], offset
* 8);
3265 seq_puts(m
, " Last wait: ");
3266 for (j
= 0; j
< num_rings
; j
++) {
3267 offset
= id
+ (j
* I915_NUM_ENGINES
);
3268 seq_printf(m
, "0x%08llx (0x%02llx) ",
3269 seqno
[offset
], offset
* 8);
3274 kunmap_atomic(seqno
);
3276 seq_puts(m
, " Last signal:");
3277 for_each_engine(engine
, dev_priv
)
3278 for (j
= 0; j
< num_rings
; j
++)
3279 seq_printf(m
, "0x%08x\n",
3280 I915_READ(engine
->semaphore
.mbox
.signal
[j
]));
3284 seq_puts(m
, "\nSync seqno:\n");
3285 for_each_engine(engine
, dev_priv
) {
3286 for (j
= 0; j
< num_rings
; j
++)
3287 seq_printf(m
, " 0x%08x ",
3288 engine
->semaphore
.sync_seqno
[j
]);
3293 intel_runtime_pm_put(dev_priv
);
3294 mutex_unlock(&dev
->struct_mutex
);
3298 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3300 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3301 struct drm_device
*dev
= node
->minor
->dev
;
3302 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3305 drm_modeset_lock_all(dev
);
3306 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3307 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3309 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3310 seq_printf(m
, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3311 pll
->config
.crtc_mask
, pll
->active_mask
, yesno(pll
->on
));
3312 seq_printf(m
, " tracked hardware state:\n");
3313 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3314 seq_printf(m
, " dpll_md: 0x%08x\n",
3315 pll
->config
.hw_state
.dpll_md
);
3316 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3317 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3318 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3320 drm_modeset_unlock_all(dev
);
3325 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3329 struct intel_engine_cs
*engine
;
3330 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3331 struct drm_device
*dev
= node
->minor
->dev
;
3332 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3333 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3334 enum intel_engine_id id
;
3336 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3340 intel_runtime_pm_get(dev_priv
);
3342 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3343 for_each_engine_id(engine
, dev_priv
, id
)
3344 seq_printf(m
, "HW whitelist count for %s: %d\n",
3345 engine
->name
, workarounds
->hw_whitelist_count
[id
]);
3346 for (i
= 0; i
< workarounds
->count
; ++i
) {
3348 u32 mask
, value
, read
;
3351 addr
= workarounds
->reg
[i
].addr
;
3352 mask
= workarounds
->reg
[i
].mask
;
3353 value
= workarounds
->reg
[i
].value
;
3354 read
= I915_READ(addr
);
3355 ok
= (value
& mask
) == (read
& mask
);
3356 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3357 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3360 intel_runtime_pm_put(dev_priv
);
3361 mutex_unlock(&dev
->struct_mutex
);
3366 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3368 struct drm_info_node
*node
= m
->private;
3369 struct drm_device
*dev
= node
->minor
->dev
;
3370 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3371 struct skl_ddb_allocation
*ddb
;
3372 struct skl_ddb_entry
*entry
;
3376 if (INTEL_INFO(dev
)->gen
< 9)
3379 drm_modeset_lock_all(dev
);
3381 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3383 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3385 for_each_pipe(dev_priv
, pipe
) {
3386 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3388 for_each_plane(dev_priv
, pipe
, plane
) {
3389 entry
= &ddb
->plane
[pipe
][plane
];
3390 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3391 entry
->start
, entry
->end
,
3392 skl_ddb_entry_size(entry
));
3395 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3396 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3397 entry
->end
, skl_ddb_entry_size(entry
));
3400 drm_modeset_unlock_all(dev
);
3405 static void drrs_status_per_crtc(struct seq_file
*m
,
3406 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3408 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3409 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3411 struct drm_connector
*connector
;
3413 drm_for_each_connector(connector
, dev
) {
3414 if (connector
->state
->crtc
!= &intel_crtc
->base
)
3417 seq_printf(m
, "%s:\n", connector
->name
);
3420 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3421 seq_puts(m
, "\tVBT: DRRS_type: Static");
3422 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3423 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3424 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3425 seq_puts(m
, "\tVBT: DRRS_type: None");
3427 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3429 seq_puts(m
, "\n\n");
3431 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3432 struct intel_panel
*panel
;
3434 mutex_lock(&drrs
->mutex
);
3435 /* DRRS Supported */
3436 seq_puts(m
, "\tDRRS Supported: Yes\n");
3438 /* disable_drrs() will make drrs->dp NULL */
3440 seq_puts(m
, "Idleness DRRS: Disabled");
3441 mutex_unlock(&drrs
->mutex
);
3445 panel
= &drrs
->dp
->attached_connector
->panel
;
3446 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3447 drrs
->busy_frontbuffer_bits
);
3449 seq_puts(m
, "\n\t\t");
3450 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3451 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3452 vrefresh
= panel
->fixed_mode
->vrefresh
;
3453 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3454 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3455 vrefresh
= panel
->downclock_mode
->vrefresh
;
3457 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3458 drrs
->refresh_rate_type
);
3459 mutex_unlock(&drrs
->mutex
);
3462 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3464 seq_puts(m
, "\n\t\t");
3465 mutex_unlock(&drrs
->mutex
);
3467 /* DRRS not supported. Print the VBT parameter*/
3468 seq_puts(m
, "\tDRRS Supported : No");
3473 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3475 struct drm_info_node
*node
= m
->private;
3476 struct drm_device
*dev
= node
->minor
->dev
;
3477 struct intel_crtc
*intel_crtc
;
3478 int active_crtc_cnt
= 0;
3480 drm_modeset_lock_all(dev
);
3481 for_each_intel_crtc(dev
, intel_crtc
) {
3482 if (intel_crtc
->base
.state
->active
) {
3484 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3486 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3489 drm_modeset_unlock_all(dev
);
3491 if (!active_crtc_cnt
)
3492 seq_puts(m
, "No active crtc found\n");
3497 struct pipe_crc_info
{
3499 struct drm_device
*dev
;
3503 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3505 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3506 struct drm_device
*dev
= node
->minor
->dev
;
3507 struct intel_encoder
*intel_encoder
;
3508 struct intel_digital_port
*intel_dig_port
;
3509 struct drm_connector
*connector
;
3511 drm_modeset_lock_all(dev
);
3512 drm_for_each_connector(connector
, dev
) {
3513 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_DisplayPort
)
3516 intel_encoder
= intel_attached_encoder(connector
);
3517 if (!intel_encoder
|| intel_encoder
->type
== INTEL_OUTPUT_DP_MST
)
3520 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
3521 if (!intel_dig_port
->dp
.can_mst
)
3524 seq_printf(m
, "MST Source Port %c\n",
3525 port_name(intel_dig_port
->port
));
3526 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3528 drm_modeset_unlock_all(dev
);
3532 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3534 struct pipe_crc_info
*info
= inode
->i_private
;
3535 struct drm_i915_private
*dev_priv
= to_i915(info
->dev
);
3536 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3538 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3541 spin_lock_irq(&pipe_crc
->lock
);
3543 if (pipe_crc
->opened
) {
3544 spin_unlock_irq(&pipe_crc
->lock
);
3545 return -EBUSY
; /* already open */
3548 pipe_crc
->opened
= true;
3549 filep
->private_data
= inode
->i_private
;
3551 spin_unlock_irq(&pipe_crc
->lock
);
3556 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3558 struct pipe_crc_info
*info
= inode
->i_private
;
3559 struct drm_i915_private
*dev_priv
= to_i915(info
->dev
);
3560 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3562 spin_lock_irq(&pipe_crc
->lock
);
3563 pipe_crc
->opened
= false;
3564 spin_unlock_irq(&pipe_crc
->lock
);
3569 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3570 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3571 /* account for \'0' */
3572 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3574 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3576 assert_spin_locked(&pipe_crc
->lock
);
3577 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3578 INTEL_PIPE_CRC_ENTRIES_NR
);
3582 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3585 struct pipe_crc_info
*info
= filep
->private_data
;
3586 struct drm_device
*dev
= info
->dev
;
3587 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3588 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3589 char buf
[PIPE_CRC_BUFFER_LEN
];
3594 * Don't allow user space to provide buffers not big enough to hold
3597 if (count
< PIPE_CRC_LINE_LEN
)
3600 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3603 /* nothing to read */
3604 spin_lock_irq(&pipe_crc
->lock
);
3605 while (pipe_crc_data_count(pipe_crc
) == 0) {
3608 if (filep
->f_flags
& O_NONBLOCK
) {
3609 spin_unlock_irq(&pipe_crc
->lock
);
3613 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3614 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3616 spin_unlock_irq(&pipe_crc
->lock
);
3621 /* We now have one or more entries to read */
3622 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3625 while (n_entries
> 0) {
3626 struct intel_pipe_crc_entry
*entry
=
3627 &pipe_crc
->entries
[pipe_crc
->tail
];
3629 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3630 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3633 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3634 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3636 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3637 "%8u %8x %8x %8x %8x %8x\n",
3638 entry
->frame
, entry
->crc
[0],
3639 entry
->crc
[1], entry
->crc
[2],
3640 entry
->crc
[3], entry
->crc
[4]);
3642 spin_unlock_irq(&pipe_crc
->lock
);
3644 if (copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
))
3647 user_buf
+= PIPE_CRC_LINE_LEN
;
3650 spin_lock_irq(&pipe_crc
->lock
);
3653 spin_unlock_irq(&pipe_crc
->lock
);
3658 static const struct file_operations i915_pipe_crc_fops
= {
3659 .owner
= THIS_MODULE
,
3660 .open
= i915_pipe_crc_open
,
3661 .read
= i915_pipe_crc_read
,
3662 .release
= i915_pipe_crc_release
,
3665 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3667 .name
= "i915_pipe_A_crc",
3671 .name
= "i915_pipe_B_crc",
3675 .name
= "i915_pipe_C_crc",
3680 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3683 struct drm_device
*dev
= minor
->dev
;
3685 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3688 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3689 &i915_pipe_crc_fops
);
3693 return drm_add_fake_info_node(minor
, ent
, info
);
3696 static const char * const pipe_crc_sources
[] = {
3709 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3711 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3712 return pipe_crc_sources
[source
];
3715 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3717 struct drm_device
*dev
= m
->private;
3718 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3721 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3722 seq_printf(m
, "%c %s\n", pipe_name(i
),
3723 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3728 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3730 struct drm_device
*dev
= inode
->i_private
;
3732 return single_open(file
, display_crc_ctl_show
, dev
);
3735 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3738 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3739 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3742 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3743 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3745 case INTEL_PIPE_CRC_SOURCE_NONE
:
3755 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3756 enum intel_pipe_crc_source
*source
)
3758 struct intel_encoder
*encoder
;
3759 struct intel_crtc
*crtc
;
3760 struct intel_digital_port
*dig_port
;
3763 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3765 drm_modeset_lock_all(dev
);
3766 for_each_intel_encoder(dev
, encoder
) {
3767 if (!encoder
->base
.crtc
)
3770 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3772 if (crtc
->pipe
!= pipe
)
3775 switch (encoder
->type
) {
3776 case INTEL_OUTPUT_TVOUT
:
3777 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3779 case INTEL_OUTPUT_DP
:
3780 case INTEL_OUTPUT_EDP
:
3781 dig_port
= enc_to_dig_port(&encoder
->base
);
3782 switch (dig_port
->port
) {
3784 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3787 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3790 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3793 WARN(1, "nonexisting DP port %c\n",
3794 port_name(dig_port
->port
));
3802 drm_modeset_unlock_all(dev
);
3807 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3809 enum intel_pipe_crc_source
*source
,
3812 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3813 bool need_stable_symbols
= false;
3815 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3816 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3822 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3823 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3825 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3826 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3827 need_stable_symbols
= true;
3829 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3830 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3831 need_stable_symbols
= true;
3833 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3834 if (!IS_CHERRYVIEW(dev
))
3836 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3837 need_stable_symbols
= true;
3839 case INTEL_PIPE_CRC_SOURCE_NONE
:
3847 * When the pipe CRC tap point is after the transcoders we need
3848 * to tweak symbol-level features to produce a deterministic series of
3849 * symbols for a given frame. We need to reset those features only once
3850 * a frame (instead of every nth symbol):
3851 * - DC-balance: used to ensure a better clock recovery from the data
3853 * - DisplayPort scrambling: used for EMI reduction
3855 if (need_stable_symbols
) {
3856 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3858 tmp
|= DC_BALANCE_RESET_VLV
;
3861 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3864 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3867 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3872 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3878 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3880 enum intel_pipe_crc_source
*source
,
3883 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3884 bool need_stable_symbols
= false;
3886 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3887 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3893 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3894 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3896 case INTEL_PIPE_CRC_SOURCE_TV
:
3897 if (!SUPPORTS_TV(dev
))
3899 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3901 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3904 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3905 need_stable_symbols
= true;
3907 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3910 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3911 need_stable_symbols
= true;
3913 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3916 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3917 need_stable_symbols
= true;
3919 case INTEL_PIPE_CRC_SOURCE_NONE
:
3927 * When the pipe CRC tap point is after the transcoders we need
3928 * to tweak symbol-level features to produce a deterministic series of
3929 * symbols for a given frame. We need to reset those features only once
3930 * a frame (instead of every nth symbol):
3931 * - DC-balance: used to ensure a better clock recovery from the data
3933 * - DisplayPort scrambling: used for EMI reduction
3935 if (need_stable_symbols
) {
3936 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3938 WARN_ON(!IS_G4X(dev
));
3940 I915_WRITE(PORT_DFT_I9XX
,
3941 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3944 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3946 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3948 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3954 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3957 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3958 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3962 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3965 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3968 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3973 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3974 tmp
&= ~DC_BALANCE_RESET_VLV
;
3975 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3979 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3982 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3983 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3986 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3988 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3989 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3991 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3992 I915_WRITE(PORT_DFT_I9XX
,
3993 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3997 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
4000 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
4001 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
4004 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
4005 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
4007 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
4008 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
4010 case INTEL_PIPE_CRC_SOURCE_PIPE
:
4011 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
4013 case INTEL_PIPE_CRC_SOURCE_NONE
:
4023 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
4025 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4026 struct intel_crtc
*crtc
=
4027 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
4028 struct intel_crtc_state
*pipe_config
;
4029 struct drm_atomic_state
*state
;
4032 drm_modeset_lock_all(dev
);
4033 state
= drm_atomic_state_alloc(dev
);
4039 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
4040 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
4041 if (IS_ERR(pipe_config
)) {
4042 ret
= PTR_ERR(pipe_config
);
4046 pipe_config
->pch_pfit
.force_thru
= enable
;
4047 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
4048 pipe_config
->pch_pfit
.enabled
!= enable
)
4049 pipe_config
->base
.connectors_changed
= true;
4051 ret
= drm_atomic_commit(state
);
4053 drm_modeset_unlock_all(dev
);
4054 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
4056 drm_atomic_state_free(state
);
4059 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
4061 enum intel_pipe_crc_source
*source
,
4064 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
4065 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
4068 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
4069 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
4071 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
4072 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
4074 case INTEL_PIPE_CRC_SOURCE_PF
:
4075 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4076 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
4078 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
4080 case INTEL_PIPE_CRC_SOURCE_NONE
:
4090 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
4091 enum intel_pipe_crc_source source
)
4093 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4094 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4095 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
4097 enum intel_display_power_domain power_domain
;
4098 u32 val
= 0; /* shut up gcc */
4101 if (pipe_crc
->source
== source
)
4104 /* forbid changing the source without going back to 'none' */
4105 if (pipe_crc
->source
&& source
)
4108 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4109 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4110 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4115 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4116 else if (INTEL_INFO(dev
)->gen
< 5)
4117 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4118 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4119 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4120 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4121 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4123 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4128 /* none -> real source transition */
4130 struct intel_pipe_crc_entry
*entries
;
4132 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4133 pipe_name(pipe
), pipe_crc_source_name(source
));
4135 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4136 sizeof(pipe_crc
->entries
[0]),
4144 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4145 * enabled and disabled dynamically based on package C states,
4146 * user space can't make reliable use of the CRCs, so let's just
4147 * completely disable it.
4149 hsw_disable_ips(crtc
);
4151 spin_lock_irq(&pipe_crc
->lock
);
4152 kfree(pipe_crc
->entries
);
4153 pipe_crc
->entries
= entries
;
4156 spin_unlock_irq(&pipe_crc
->lock
);
4159 pipe_crc
->source
= source
;
4161 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4162 POSTING_READ(PIPE_CRC_CTL(pipe
));
4164 /* real source -> none transition */
4165 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4166 struct intel_pipe_crc_entry
*entries
;
4167 struct intel_crtc
*crtc
=
4168 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4170 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4173 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4174 if (crtc
->base
.state
->active
)
4175 intel_wait_for_vblank(dev
, pipe
);
4176 drm_modeset_unlock(&crtc
->base
.mutex
);
4178 spin_lock_irq(&pipe_crc
->lock
);
4179 entries
= pipe_crc
->entries
;
4180 pipe_crc
->entries
= NULL
;
4183 spin_unlock_irq(&pipe_crc
->lock
);
4188 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4189 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4190 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4191 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4192 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4194 hsw_enable_ips(crtc
);
4200 intel_display_power_put(dev_priv
, power_domain
);
4206 * Parse pipe CRC command strings:
4207 * command: wsp* object wsp+ name wsp+ source wsp*
4210 * source: (none | plane1 | plane2 | pf)
4211 * wsp: (#0x20 | #0x9 | #0xA)+
4214 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4215 * "pipe A none" -> Stop CRC
4217 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4224 /* skip leading white space */
4225 buf
= skip_spaces(buf
);
4227 break; /* end of buffer */
4229 /* find end of word */
4230 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4233 if (n_words
== max_words
) {
4234 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4236 return -EINVAL
; /* ran out of words[] before bytes */
4241 words
[n_words
++] = buf
;
4248 enum intel_pipe_crc_object
{
4249 PIPE_CRC_OBJECT_PIPE
,
4252 static const char * const pipe_crc_objects
[] = {
4257 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4261 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4262 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4270 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4272 const char name
= buf
[0];
4274 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4283 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4287 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4288 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4296 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4300 char *words
[N_WORDS
];
4302 enum intel_pipe_crc_object object
;
4303 enum intel_pipe_crc_source source
;
4305 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4306 if (n_words
!= N_WORDS
) {
4307 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4312 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4313 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4317 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4318 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4322 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4323 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4327 return pipe_crc_set_source(dev
, pipe
, source
);
4330 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4331 size_t len
, loff_t
*offp
)
4333 struct seq_file
*m
= file
->private_data
;
4334 struct drm_device
*dev
= m
->private;
4341 if (len
> PAGE_SIZE
- 1) {
4342 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4347 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4351 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4357 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4368 static const struct file_operations i915_display_crc_ctl_fops
= {
4369 .owner
= THIS_MODULE
,
4370 .open
= display_crc_ctl_open
,
4372 .llseek
= seq_lseek
,
4373 .release
= single_release
,
4374 .write
= display_crc_ctl_write
4377 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4378 const char __user
*ubuf
,
4379 size_t len
, loff_t
*offp
)
4383 struct drm_device
*dev
;
4384 struct drm_connector
*connector
;
4385 struct list_head
*connector_list
;
4386 struct intel_dp
*intel_dp
;
4389 dev
= ((struct seq_file
*)file
->private_data
)->private;
4391 connector_list
= &dev
->mode_config
.connector_list
;
4396 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4400 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4405 input_buffer
[len
] = '\0';
4406 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4408 list_for_each_entry(connector
, connector_list
, head
) {
4410 if (connector
->connector_type
!=
4411 DRM_MODE_CONNECTOR_DisplayPort
)
4414 if (connector
->status
== connector_status_connected
&&
4415 connector
->encoder
!= NULL
) {
4416 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4417 status
= kstrtoint(input_buffer
, 10, &val
);
4420 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4421 /* To prevent erroneous activation of the compliance
4422 * testing code, only accept an actual value of 1 here
4425 intel_dp
->compliance_test_active
= 1;
4427 intel_dp
->compliance_test_active
= 0;
4431 kfree(input_buffer
);
4439 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4441 struct drm_device
*dev
= m
->private;
4442 struct drm_connector
*connector
;
4443 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4444 struct intel_dp
*intel_dp
;
4446 list_for_each_entry(connector
, connector_list
, head
) {
4448 if (connector
->connector_type
!=
4449 DRM_MODE_CONNECTOR_DisplayPort
)
4452 if (connector
->status
== connector_status_connected
&&
4453 connector
->encoder
!= NULL
) {
4454 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4455 if (intel_dp
->compliance_test_active
)
4466 static int i915_displayport_test_active_open(struct inode
*inode
,
4469 struct drm_device
*dev
= inode
->i_private
;
4471 return single_open(file
, i915_displayport_test_active_show
, dev
);
4474 static const struct file_operations i915_displayport_test_active_fops
= {
4475 .owner
= THIS_MODULE
,
4476 .open
= i915_displayport_test_active_open
,
4478 .llseek
= seq_lseek
,
4479 .release
= single_release
,
4480 .write
= i915_displayport_test_active_write
4483 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4485 struct drm_device
*dev
= m
->private;
4486 struct drm_connector
*connector
;
4487 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4488 struct intel_dp
*intel_dp
;
4490 list_for_each_entry(connector
, connector_list
, head
) {
4492 if (connector
->connector_type
!=
4493 DRM_MODE_CONNECTOR_DisplayPort
)
4496 if (connector
->status
== connector_status_connected
&&
4497 connector
->encoder
!= NULL
) {
4498 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4499 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4506 static int i915_displayport_test_data_open(struct inode
*inode
,
4509 struct drm_device
*dev
= inode
->i_private
;
4511 return single_open(file
, i915_displayport_test_data_show
, dev
);
4514 static const struct file_operations i915_displayport_test_data_fops
= {
4515 .owner
= THIS_MODULE
,
4516 .open
= i915_displayport_test_data_open
,
4518 .llseek
= seq_lseek
,
4519 .release
= single_release
4522 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4524 struct drm_device
*dev
= m
->private;
4525 struct drm_connector
*connector
;
4526 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4527 struct intel_dp
*intel_dp
;
4529 list_for_each_entry(connector
, connector_list
, head
) {
4531 if (connector
->connector_type
!=
4532 DRM_MODE_CONNECTOR_DisplayPort
)
4535 if (connector
->status
== connector_status_connected
&&
4536 connector
->encoder
!= NULL
) {
4537 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4538 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4546 static int i915_displayport_test_type_open(struct inode
*inode
,
4549 struct drm_device
*dev
= inode
->i_private
;
4551 return single_open(file
, i915_displayport_test_type_show
, dev
);
4554 static const struct file_operations i915_displayport_test_type_fops
= {
4555 .owner
= THIS_MODULE
,
4556 .open
= i915_displayport_test_type_open
,
4558 .llseek
= seq_lseek
,
4559 .release
= single_release
4562 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4564 struct drm_device
*dev
= m
->private;
4568 if (IS_CHERRYVIEW(dev
))
4570 else if (IS_VALLEYVIEW(dev
))
4573 num_levels
= ilk_wm_max_level(dev
) + 1;
4575 drm_modeset_lock_all(dev
);
4577 for (level
= 0; level
< num_levels
; level
++) {
4578 unsigned int latency
= wm
[level
];
4581 * - WM1+ latency values in 0.5us units
4582 * - latencies are in us on gen9/vlv/chv
4584 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4590 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4591 level
, wm
[level
], latency
/ 10, latency
% 10);
4594 drm_modeset_unlock_all(dev
);
4597 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4599 struct drm_device
*dev
= m
->private;
4600 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4601 const uint16_t *latencies
;
4603 if (INTEL_INFO(dev
)->gen
>= 9)
4604 latencies
= dev_priv
->wm
.skl_latency
;
4606 latencies
= to_i915(dev
)->wm
.pri_latency
;
4608 wm_latency_show(m
, latencies
);
4613 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4615 struct drm_device
*dev
= m
->private;
4616 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4617 const uint16_t *latencies
;
4619 if (INTEL_INFO(dev
)->gen
>= 9)
4620 latencies
= dev_priv
->wm
.skl_latency
;
4622 latencies
= to_i915(dev
)->wm
.spr_latency
;
4624 wm_latency_show(m
, latencies
);
4629 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4631 struct drm_device
*dev
= m
->private;
4632 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4633 const uint16_t *latencies
;
4635 if (INTEL_INFO(dev
)->gen
>= 9)
4636 latencies
= dev_priv
->wm
.skl_latency
;
4638 latencies
= to_i915(dev
)->wm
.cur_latency
;
4640 wm_latency_show(m
, latencies
);
4645 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4647 struct drm_device
*dev
= inode
->i_private
;
4649 if (INTEL_INFO(dev
)->gen
< 5)
4652 return single_open(file
, pri_wm_latency_show
, dev
);
4655 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4657 struct drm_device
*dev
= inode
->i_private
;
4659 if (HAS_GMCH_DISPLAY(dev
))
4662 return single_open(file
, spr_wm_latency_show
, dev
);
4665 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4667 struct drm_device
*dev
= inode
->i_private
;
4669 if (HAS_GMCH_DISPLAY(dev
))
4672 return single_open(file
, cur_wm_latency_show
, dev
);
4675 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4676 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4678 struct seq_file
*m
= file
->private_data
;
4679 struct drm_device
*dev
= m
->private;
4680 uint16_t new[8] = { 0 };
4686 if (IS_CHERRYVIEW(dev
))
4688 else if (IS_VALLEYVIEW(dev
))
4691 num_levels
= ilk_wm_max_level(dev
) + 1;
4693 if (len
>= sizeof(tmp
))
4696 if (copy_from_user(tmp
, ubuf
, len
))
4701 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4702 &new[0], &new[1], &new[2], &new[3],
4703 &new[4], &new[5], &new[6], &new[7]);
4704 if (ret
!= num_levels
)
4707 drm_modeset_lock_all(dev
);
4709 for (level
= 0; level
< num_levels
; level
++)
4710 wm
[level
] = new[level
];
4712 drm_modeset_unlock_all(dev
);
4718 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4719 size_t len
, loff_t
*offp
)
4721 struct seq_file
*m
= file
->private_data
;
4722 struct drm_device
*dev
= m
->private;
4723 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4724 uint16_t *latencies
;
4726 if (INTEL_INFO(dev
)->gen
>= 9)
4727 latencies
= dev_priv
->wm
.skl_latency
;
4729 latencies
= to_i915(dev
)->wm
.pri_latency
;
4731 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4734 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4735 size_t len
, loff_t
*offp
)
4737 struct seq_file
*m
= file
->private_data
;
4738 struct drm_device
*dev
= m
->private;
4739 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4740 uint16_t *latencies
;
4742 if (INTEL_INFO(dev
)->gen
>= 9)
4743 latencies
= dev_priv
->wm
.skl_latency
;
4745 latencies
= to_i915(dev
)->wm
.spr_latency
;
4747 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4750 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4751 size_t len
, loff_t
*offp
)
4753 struct seq_file
*m
= file
->private_data
;
4754 struct drm_device
*dev
= m
->private;
4755 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4756 uint16_t *latencies
;
4758 if (INTEL_INFO(dev
)->gen
>= 9)
4759 latencies
= dev_priv
->wm
.skl_latency
;
4761 latencies
= to_i915(dev
)->wm
.cur_latency
;
4763 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4766 static const struct file_operations i915_pri_wm_latency_fops
= {
4767 .owner
= THIS_MODULE
,
4768 .open
= pri_wm_latency_open
,
4770 .llseek
= seq_lseek
,
4771 .release
= single_release
,
4772 .write
= pri_wm_latency_write
4775 static const struct file_operations i915_spr_wm_latency_fops
= {
4776 .owner
= THIS_MODULE
,
4777 .open
= spr_wm_latency_open
,
4779 .llseek
= seq_lseek
,
4780 .release
= single_release
,
4781 .write
= spr_wm_latency_write
4784 static const struct file_operations i915_cur_wm_latency_fops
= {
4785 .owner
= THIS_MODULE
,
4786 .open
= cur_wm_latency_open
,
4788 .llseek
= seq_lseek
,
4789 .release
= single_release
,
4790 .write
= cur_wm_latency_write
4794 i915_wedged_get(void *data
, u64
*val
)
4796 struct drm_device
*dev
= data
;
4797 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4799 *val
= i915_terminally_wedged(&dev_priv
->gpu_error
);
4805 i915_wedged_set(void *data
, u64 val
)
4807 struct drm_device
*dev
= data
;
4808 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4811 * There is no safeguard against this debugfs entry colliding
4812 * with the hangcheck calling same i915_handle_error() in
4813 * parallel, causing an explosion. For now we assume that the
4814 * test harness is responsible enough not to inject gpu hangs
4815 * while it is writing to 'i915_wedged'
4818 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4821 intel_runtime_pm_get(dev_priv
);
4823 i915_handle_error(dev_priv
, val
,
4824 "Manually setting wedged to %llu", val
);
4826 intel_runtime_pm_put(dev_priv
);
4831 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4832 i915_wedged_get
, i915_wedged_set
,
4836 i915_ring_missed_irq_get(void *data
, u64
*val
)
4838 struct drm_device
*dev
= data
;
4839 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4841 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4846 i915_ring_missed_irq_set(void *data
, u64 val
)
4848 struct drm_device
*dev
= data
;
4849 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4852 /* Lock against concurrent debugfs callers */
4853 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4856 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4857 mutex_unlock(&dev
->struct_mutex
);
4862 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4863 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4867 i915_ring_test_irq_get(void *data
, u64
*val
)
4869 struct drm_device
*dev
= data
;
4870 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4872 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4878 i915_ring_test_irq_set(void *data
, u64 val
)
4880 struct drm_device
*dev
= data
;
4881 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4883 val
&= INTEL_INFO(dev_priv
)->ring_mask
;
4884 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4885 dev_priv
->gpu_error
.test_irq_rings
= val
;
4890 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4891 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4894 #define DROP_UNBOUND 0x1
4895 #define DROP_BOUND 0x2
4896 #define DROP_RETIRE 0x4
4897 #define DROP_ACTIVE 0x8
4898 #define DROP_ALL (DROP_UNBOUND | \
4903 i915_drop_caches_get(void *data
, u64
*val
)
4911 i915_drop_caches_set(void *data
, u64 val
)
4913 struct drm_device
*dev
= data
;
4914 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4917 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4919 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4920 * on ioctls on -EAGAIN. */
4921 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4925 if (val
& DROP_ACTIVE
) {
4926 ret
= i915_gem_wait_for_idle(dev_priv
, true);
4931 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4932 i915_gem_retire_requests(dev_priv
);
4934 if (val
& DROP_BOUND
)
4935 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4937 if (val
& DROP_UNBOUND
)
4938 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4941 mutex_unlock(&dev
->struct_mutex
);
4946 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4947 i915_drop_caches_get
, i915_drop_caches_set
,
4951 i915_max_freq_get(void *data
, u64
*val
)
4953 struct drm_device
*dev
= data
;
4954 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4956 if (INTEL_INFO(dev
)->gen
< 6)
4959 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4964 i915_max_freq_set(void *data
, u64 val
)
4966 struct drm_device
*dev
= data
;
4967 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4971 if (INTEL_INFO(dev
)->gen
< 6)
4974 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4976 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4981 * Turbo will still be enabled, but won't go above the set value.
4983 val
= intel_freq_opcode(dev_priv
, val
);
4985 hw_max
= dev_priv
->rps
.max_freq
;
4986 hw_min
= dev_priv
->rps
.min_freq
;
4988 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4989 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4993 dev_priv
->rps
.max_freq_softlimit
= val
;
4995 intel_set_rps(dev_priv
, val
);
4997 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5002 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
5003 i915_max_freq_get
, i915_max_freq_set
,
5007 i915_min_freq_get(void *data
, u64
*val
)
5009 struct drm_device
*dev
= data
;
5010 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5012 if (INTEL_GEN(dev_priv
) < 6)
5015 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
5020 i915_min_freq_set(void *data
, u64 val
)
5022 struct drm_device
*dev
= data
;
5023 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5027 if (INTEL_GEN(dev_priv
) < 6)
5030 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
5032 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5037 * Turbo will still be enabled, but won't go below the set value.
5039 val
= intel_freq_opcode(dev_priv
, val
);
5041 hw_max
= dev_priv
->rps
.max_freq
;
5042 hw_min
= dev_priv
->rps
.min_freq
;
5044 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5045 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5049 dev_priv
->rps
.min_freq_softlimit
= val
;
5051 intel_set_rps(dev_priv
, val
);
5053 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5058 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5059 i915_min_freq_get
, i915_min_freq_set
,
5063 i915_cache_sharing_get(void *data
, u64
*val
)
5065 struct drm_device
*dev
= data
;
5066 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5070 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5073 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5076 intel_runtime_pm_get(dev_priv
);
5078 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5080 intel_runtime_pm_put(dev_priv
);
5081 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
5083 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5089 i915_cache_sharing_set(void *data
, u64 val
)
5091 struct drm_device
*dev
= data
;
5092 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5095 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5101 intel_runtime_pm_get(dev_priv
);
5102 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5104 /* Update the cache sharing policy here as well */
5105 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5106 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5107 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5108 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5110 intel_runtime_pm_put(dev_priv
);
5114 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5115 i915_cache_sharing_get
, i915_cache_sharing_set
,
5118 struct sseu_dev_status
{
5119 unsigned int slice_total
;
5120 unsigned int subslice_total
;
5121 unsigned int subslice_per_slice
;
5122 unsigned int eu_total
;
5123 unsigned int eu_per_subslice
;
5126 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5127 struct sseu_dev_status
*stat
)
5129 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5132 u32 sig1
[ss_max
], sig2
[ss_max
];
5134 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5135 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5136 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5137 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5139 for (ss
= 0; ss
< ss_max
; ss
++) {
5140 unsigned int eu_cnt
;
5142 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5143 /* skip disabled subslice */
5146 stat
->slice_total
= 1;
5147 stat
->subslice_per_slice
++;
5148 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5149 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5150 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5151 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5152 stat
->eu_total
+= eu_cnt
;
5153 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5155 stat
->subslice_total
= stat
->subslice_per_slice
;
5158 static void gen9_sseu_device_status(struct drm_device
*dev
,
5159 struct sseu_dev_status
*stat
)
5161 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5162 int s_max
= 3, ss_max
= 4;
5164 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5166 /* BXT has a single slice and at most 3 subslices. */
5167 if (IS_BROXTON(dev
)) {
5172 for (s
= 0; s
< s_max
; s
++) {
5173 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5174 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5175 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5178 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5179 GEN9_PGCTL_SSA_EU19_ACK
|
5180 GEN9_PGCTL_SSA_EU210_ACK
|
5181 GEN9_PGCTL_SSA_EU311_ACK
;
5182 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5183 GEN9_PGCTL_SSB_EU19_ACK
|
5184 GEN9_PGCTL_SSB_EU210_ACK
|
5185 GEN9_PGCTL_SSB_EU311_ACK
;
5187 for (s
= 0; s
< s_max
; s
++) {
5188 unsigned int ss_cnt
= 0;
5190 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5191 /* skip disabled slice */
5194 stat
->slice_total
++;
5196 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5197 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5199 for (ss
= 0; ss
< ss_max
; ss
++) {
5200 unsigned int eu_cnt
;
5202 if (IS_BROXTON(dev
) &&
5203 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5204 /* skip disabled subslice */
5207 if (IS_BROXTON(dev
))
5210 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5212 stat
->eu_total
+= eu_cnt
;
5213 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5217 stat
->subslice_total
+= ss_cnt
;
5218 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5223 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5224 struct sseu_dev_status
*stat
)
5226 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5228 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5230 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5232 if (stat
->slice_total
) {
5233 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5234 stat
->subslice_total
= stat
->slice_total
*
5235 stat
->subslice_per_slice
;
5236 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5237 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5239 /* subtract fused off EU(s) from enabled slice(s) */
5240 for (s
= 0; s
< stat
->slice_total
; s
++) {
5241 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5243 stat
->eu_total
-= hweight8(subslice_7eu
);
5248 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5250 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5251 struct drm_i915_private
*dev_priv
= to_i915(node
->minor
->dev
);
5252 struct drm_device
*dev
= &dev_priv
->drm
;
5253 struct sseu_dev_status stat
;
5255 if (INTEL_INFO(dev
)->gen
< 8)
5258 seq_puts(m
, "SSEU Device Info\n");
5259 seq_printf(m
, " Available Slice Total: %u\n",
5260 INTEL_INFO(dev
)->slice_total
);
5261 seq_printf(m
, " Available Subslice Total: %u\n",
5262 INTEL_INFO(dev
)->subslice_total
);
5263 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5264 INTEL_INFO(dev
)->subslice_per_slice
);
5265 seq_printf(m
, " Available EU Total: %u\n",
5266 INTEL_INFO(dev
)->eu_total
);
5267 seq_printf(m
, " Available EU Per Subslice: %u\n",
5268 INTEL_INFO(dev
)->eu_per_subslice
);
5269 seq_printf(m
, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev
)));
5270 if (HAS_POOLED_EU(dev
))
5271 seq_printf(m
, " Min EU in pool: %u\n",
5272 INTEL_INFO(dev
)->min_eu_in_pool
);
5273 seq_printf(m
, " Has Slice Power Gating: %s\n",
5274 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5275 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5276 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5277 seq_printf(m
, " Has EU Power Gating: %s\n",
5278 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5280 seq_puts(m
, "SSEU Device Status\n");
5281 memset(&stat
, 0, sizeof(stat
));
5283 intel_runtime_pm_get(dev_priv
);
5285 if (IS_CHERRYVIEW(dev
)) {
5286 cherryview_sseu_device_status(dev
, &stat
);
5287 } else if (IS_BROADWELL(dev
)) {
5288 broadwell_sseu_device_status(dev
, &stat
);
5289 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5290 gen9_sseu_device_status(dev
, &stat
);
5293 intel_runtime_pm_put(dev_priv
);
5295 seq_printf(m
, " Enabled Slice Total: %u\n",
5297 seq_printf(m
, " Enabled Subslice Total: %u\n",
5298 stat
.subslice_total
);
5299 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5300 stat
.subslice_per_slice
);
5301 seq_printf(m
, " Enabled EU Total: %u\n",
5303 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5304 stat
.eu_per_subslice
);
5309 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5311 struct drm_device
*dev
= inode
->i_private
;
5312 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5314 if (INTEL_INFO(dev
)->gen
< 6)
5317 intel_runtime_pm_get(dev_priv
);
5318 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5323 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5325 struct drm_device
*dev
= inode
->i_private
;
5326 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5328 if (INTEL_INFO(dev
)->gen
< 6)
5331 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5332 intel_runtime_pm_put(dev_priv
);
5337 static const struct file_operations i915_forcewake_fops
= {
5338 .owner
= THIS_MODULE
,
5339 .open
= i915_forcewake_open
,
5340 .release
= i915_forcewake_release
,
5343 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5345 struct drm_device
*dev
= minor
->dev
;
5348 ent
= debugfs_create_file("i915_forcewake_user",
5351 &i915_forcewake_fops
);
5355 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5358 static int i915_debugfs_create(struct dentry
*root
,
5359 struct drm_minor
*minor
,
5361 const struct file_operations
*fops
)
5363 struct drm_device
*dev
= minor
->dev
;
5366 ent
= debugfs_create_file(name
,
5373 return drm_add_fake_info_node(minor
, ent
, fops
);
5376 static const struct drm_info_list i915_debugfs_list
[] = {
5377 {"i915_capabilities", i915_capabilities
, 0},
5378 {"i915_gem_objects", i915_gem_object_info
, 0},
5379 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5380 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5381 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5382 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5383 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5384 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5385 {"i915_gem_request", i915_gem_request_info
, 0},
5386 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5387 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5388 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5389 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5390 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5391 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5392 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5393 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5394 {"i915_guc_info", i915_guc_info
, 0},
5395 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5396 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5397 {"i915_frequency_info", i915_frequency_info
, 0},
5398 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5399 {"i915_drpc_info", i915_drpc_info
, 0},
5400 {"i915_emon_status", i915_emon_status
, 0},
5401 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5402 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5403 {"i915_fbc_status", i915_fbc_status
, 0},
5404 {"i915_ips_status", i915_ips_status
, 0},
5405 {"i915_sr_status", i915_sr_status
, 0},
5406 {"i915_opregion", i915_opregion
, 0},
5407 {"i915_vbt", i915_vbt
, 0},
5408 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5409 {"i915_context_status", i915_context_status
, 0},
5410 {"i915_dump_lrc", i915_dump_lrc
, 0},
5411 {"i915_execlists", i915_execlists
, 0},
5412 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5413 {"i915_swizzle_info", i915_swizzle_info
, 0},
5414 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5415 {"i915_llc", i915_llc
, 0},
5416 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5417 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5418 {"i915_energy_uJ", i915_energy_uJ
, 0},
5419 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5420 {"i915_power_domain_info", i915_power_domain_info
, 0},
5421 {"i915_dmc_info", i915_dmc_info
, 0},
5422 {"i915_display_info", i915_display_info
, 0},
5423 {"i915_semaphore_status", i915_semaphore_status
, 0},
5424 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5425 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5426 {"i915_wa_registers", i915_wa_registers
, 0},
5427 {"i915_ddb_info", i915_ddb_info
, 0},
5428 {"i915_sseu_status", i915_sseu_status
, 0},
5429 {"i915_drrs_status", i915_drrs_status
, 0},
5430 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5432 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5434 static const struct i915_debugfs_files
{
5436 const struct file_operations
*fops
;
5437 } i915_debugfs_files
[] = {
5438 {"i915_wedged", &i915_wedged_fops
},
5439 {"i915_max_freq", &i915_max_freq_fops
},
5440 {"i915_min_freq", &i915_min_freq_fops
},
5441 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5442 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5443 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5444 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5445 {"i915_error_state", &i915_error_state_fops
},
5446 {"i915_next_seqno", &i915_next_seqno_fops
},
5447 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5448 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5449 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5450 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5451 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5452 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5453 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5454 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5457 void intel_display_crc_init(struct drm_device
*dev
)
5459 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5462 for_each_pipe(dev_priv
, pipe
) {
5463 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5465 pipe_crc
->opened
= false;
5466 spin_lock_init(&pipe_crc
->lock
);
5467 init_waitqueue_head(&pipe_crc
->wq
);
5471 int i915_debugfs_register(struct drm_i915_private
*dev_priv
)
5473 struct drm_minor
*minor
= dev_priv
->drm
.primary
;
5476 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5480 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5481 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5486 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5487 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5488 i915_debugfs_files
[i
].name
,
5489 i915_debugfs_files
[i
].fops
);
5494 return drm_debugfs_create_files(i915_debugfs_list
,
5495 I915_DEBUGFS_ENTRIES
,
5496 minor
->debugfs_root
, minor
);
5499 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
)
5501 struct drm_minor
*minor
= dev_priv
->drm
.primary
;
5504 drm_debugfs_remove_files(i915_debugfs_list
,
5505 I915_DEBUGFS_ENTRIES
, minor
);
5507 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5510 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5511 struct drm_info_list
*info_list
=
5512 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5514 drm_debugfs_remove_files(info_list
, 1, minor
);
5517 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5518 struct drm_info_list
*info_list
=
5519 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5521 drm_debugfs_remove_files(info_list
, 1, minor
);
5526 /* DPCD dump start address. */
5527 unsigned int offset
;
5528 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5530 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5532 /* Only valid for eDP. */
5536 static const struct dpcd_block i915_dpcd_debug
[] = {
5537 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5538 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5539 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5540 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5541 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5542 { .offset
= DP_SET_POWER
},
5543 { .offset
= DP_EDP_DPCD_REV
},
5544 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5545 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5546 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5549 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5551 struct drm_connector
*connector
= m
->private;
5552 struct intel_dp
*intel_dp
=
5553 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5558 if (connector
->status
!= connector_status_connected
)
5561 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5562 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5563 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5566 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5569 /* low tech for now */
5570 if (WARN_ON(size
> sizeof(buf
)))
5573 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5575 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5576 size
, b
->offset
, err
);
5580 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5586 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5588 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5591 static const struct file_operations i915_dpcd_fops
= {
5592 .owner
= THIS_MODULE
,
5593 .open
= i915_dpcd_open
,
5595 .llseek
= seq_lseek
,
5596 .release
= single_release
,
5600 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5601 * @connector: pointer to a registered drm_connector
5603 * Cleanup will be done by drm_connector_unregister() through a call to
5604 * drm_debugfs_connector_remove().
5606 * Returns 0 on success, negative error codes on error.
5608 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5610 struct dentry
*root
= connector
->debugfs_entry
;
5612 /* The connector must have been registered beforehands. */
5616 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5617 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5618 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,