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drm/i915: Add some missing steps to i915_driver_load error path
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/debugfs.h>
31 #include <linux/slab.h>
32 #include <linux/export.h>
33 #include <linux/list_sort.h>
34 #include <asm/msr-index.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include "intel_ringbuffer.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 #define DRM_I915_RING_DEBUG 1
42
43
44 #if defined(CONFIG_DEBUG_FS)
45
46 enum {
47 ACTIVE_LIST,
48 INACTIVE_LIST,
49 PINNED_LIST,
50 };
51
52 static const char *yesno(int v)
53 {
54 return v ? "yes" : "no";
55 }
56
57 static int i915_capabilities(struct seq_file *m, void *data)
58 {
59 struct drm_info_node *node = (struct drm_info_node *) m->private;
60 struct drm_device *dev = node->minor->dev;
61 const struct intel_device_info *info = INTEL_INFO(dev);
62
63 seq_printf(m, "gen: %d\n", info->gen);
64 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
65 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
66 #define SEP_SEMICOLON ;
67 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
68 #undef PRINT_FLAG
69 #undef SEP_SEMICOLON
70
71 return 0;
72 }
73
74 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
75 {
76 if (obj->user_pin_count > 0)
77 return "P";
78 else if (obj->pin_count > 0)
79 return "p";
80 else
81 return " ";
82 }
83
84 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
85 {
86 switch (obj->tiling_mode) {
87 default:
88 case I915_TILING_NONE: return " ";
89 case I915_TILING_X: return "X";
90 case I915_TILING_Y: return "Y";
91 }
92 }
93
94 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
95 {
96 return obj->has_global_gtt_mapping ? "g" : " ";
97 }
98
99 static void
100 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
101 {
102 struct i915_vma *vma;
103 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
104 &obj->base,
105 get_pin_flag(obj),
106 get_tiling_flag(obj),
107 get_global_flag(obj),
108 obj->base.size / 1024,
109 obj->base.read_domains,
110 obj->base.write_domain,
111 obj->last_read_seqno,
112 obj->last_write_seqno,
113 obj->last_fenced_seqno,
114 i915_cache_level_str(obj->cache_level),
115 obj->dirty ? " dirty" : "",
116 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
117 if (obj->base.name)
118 seq_printf(m, " (name: %d)", obj->base.name);
119 if (obj->pin_count)
120 seq_printf(m, " (pinned x %d)", obj->pin_count);
121 if (obj->pin_display)
122 seq_printf(m, " (display)");
123 if (obj->fence_reg != I915_FENCE_REG_NONE)
124 seq_printf(m, " (fence: %d)", obj->fence_reg);
125 list_for_each_entry(vma, &obj->vma_list, vma_link) {
126 if (!i915_is_ggtt(vma->vm))
127 seq_puts(m, " (pp");
128 else
129 seq_puts(m, " (g");
130 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
131 vma->node.start, vma->node.size);
132 }
133 if (obj->stolen)
134 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
135 if (obj->pin_mappable || obj->fault_mappable) {
136 char s[3], *t = s;
137 if (obj->pin_mappable)
138 *t++ = 'p';
139 if (obj->fault_mappable)
140 *t++ = 'f';
141 *t = '\0';
142 seq_printf(m, " (%s mappable)", s);
143 }
144 if (obj->ring != NULL)
145 seq_printf(m, " (%s)", obj->ring->name);
146 }
147
148 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
149 {
150 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
151 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
152 seq_putc(m, ' ');
153 }
154
155 static int i915_gem_object_list_info(struct seq_file *m, void *data)
156 {
157 struct drm_info_node *node = (struct drm_info_node *) m->private;
158 uintptr_t list = (uintptr_t) node->info_ent->data;
159 struct list_head *head;
160 struct drm_device *dev = node->minor->dev;
161 struct drm_i915_private *dev_priv = dev->dev_private;
162 struct i915_address_space *vm = &dev_priv->gtt.base;
163 struct i915_vma *vma;
164 size_t total_obj_size, total_gtt_size;
165 int count, ret;
166
167 ret = mutex_lock_interruptible(&dev->struct_mutex);
168 if (ret)
169 return ret;
170
171 /* FIXME: the user of this interface might want more than just GGTT */
172 switch (list) {
173 case ACTIVE_LIST:
174 seq_puts(m, "Active:\n");
175 head = &vm->active_list;
176 break;
177 case INACTIVE_LIST:
178 seq_puts(m, "Inactive:\n");
179 head = &vm->inactive_list;
180 break;
181 default:
182 mutex_unlock(&dev->struct_mutex);
183 return -EINVAL;
184 }
185
186 total_obj_size = total_gtt_size = count = 0;
187 list_for_each_entry(vma, head, mm_list) {
188 seq_printf(m, " ");
189 describe_obj(m, vma->obj);
190 seq_printf(m, "\n");
191 total_obj_size += vma->obj->base.size;
192 total_gtt_size += vma->node.size;
193 count++;
194 }
195 mutex_unlock(&dev->struct_mutex);
196
197 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
198 count, total_obj_size, total_gtt_size);
199 return 0;
200 }
201
202 static int obj_rank_by_stolen(void *priv,
203 struct list_head *A, struct list_head *B)
204 {
205 struct drm_i915_gem_object *a =
206 container_of(A, struct drm_i915_gem_object, obj_exec_link);
207 struct drm_i915_gem_object *b =
208 container_of(B, struct drm_i915_gem_object, obj_exec_link);
209
210 return a->stolen->start - b->stolen->start;
211 }
212
213 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
214 {
215 struct drm_info_node *node = (struct drm_info_node *) m->private;
216 struct drm_device *dev = node->minor->dev;
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 struct drm_i915_gem_object *obj;
219 size_t total_obj_size, total_gtt_size;
220 LIST_HEAD(stolen);
221 int count, ret;
222
223 ret = mutex_lock_interruptible(&dev->struct_mutex);
224 if (ret)
225 return ret;
226
227 total_obj_size = total_gtt_size = count = 0;
228 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
229 if (obj->stolen == NULL)
230 continue;
231
232 list_add(&obj->obj_exec_link, &stolen);
233
234 total_obj_size += obj->base.size;
235 total_gtt_size += i915_gem_obj_ggtt_size(obj);
236 count++;
237 }
238 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
239 if (obj->stolen == NULL)
240 continue;
241
242 list_add(&obj->obj_exec_link, &stolen);
243
244 total_obj_size += obj->base.size;
245 count++;
246 }
247 list_sort(NULL, &stolen, obj_rank_by_stolen);
248 seq_puts(m, "Stolen:\n");
249 while (!list_empty(&stolen)) {
250 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
251 seq_puts(m, " ");
252 describe_obj(m, obj);
253 seq_putc(m, '\n');
254 list_del_init(&obj->obj_exec_link);
255 }
256 mutex_unlock(&dev->struct_mutex);
257
258 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
259 count, total_obj_size, total_gtt_size);
260 return 0;
261 }
262
263 #define count_objects(list, member) do { \
264 list_for_each_entry(obj, list, member) { \
265 size += i915_gem_obj_ggtt_size(obj); \
266 ++count; \
267 if (obj->map_and_fenceable) { \
268 mappable_size += i915_gem_obj_ggtt_size(obj); \
269 ++mappable_count; \
270 } \
271 } \
272 } while (0)
273
274 struct file_stats {
275 int count;
276 size_t total, active, inactive, unbound;
277 };
278
279 static int per_file_stats(int id, void *ptr, void *data)
280 {
281 struct drm_i915_gem_object *obj = ptr;
282 struct file_stats *stats = data;
283
284 stats->count++;
285 stats->total += obj->base.size;
286
287 if (i915_gem_obj_ggtt_bound(obj)) {
288 if (!list_empty(&obj->ring_list))
289 stats->active += obj->base.size;
290 else
291 stats->inactive += obj->base.size;
292 } else {
293 if (!list_empty(&obj->global_list))
294 stats->unbound += obj->base.size;
295 }
296
297 return 0;
298 }
299
300 #define count_vmas(list, member) do { \
301 list_for_each_entry(vma, list, member) { \
302 size += i915_gem_obj_ggtt_size(vma->obj); \
303 ++count; \
304 if (vma->obj->map_and_fenceable) { \
305 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
306 ++mappable_count; \
307 } \
308 } \
309 } while (0)
310
311 static int i915_gem_object_info(struct seq_file *m, void* data)
312 {
313 struct drm_info_node *node = (struct drm_info_node *) m->private;
314 struct drm_device *dev = node->minor->dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 u32 count, mappable_count, purgeable_count;
317 size_t size, mappable_size, purgeable_size;
318 struct drm_i915_gem_object *obj;
319 struct i915_address_space *vm = &dev_priv->gtt.base;
320 struct drm_file *file;
321 struct i915_vma *vma;
322 int ret;
323
324 ret = mutex_lock_interruptible(&dev->struct_mutex);
325 if (ret)
326 return ret;
327
328 seq_printf(m, "%u objects, %zu bytes\n",
329 dev_priv->mm.object_count,
330 dev_priv->mm.object_memory);
331
332 size = count = mappable_size = mappable_count = 0;
333 count_objects(&dev_priv->mm.bound_list, global_list);
334 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
335 count, mappable_count, size, mappable_size);
336
337 size = count = mappable_size = mappable_count = 0;
338 count_vmas(&vm->active_list, mm_list);
339 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
340 count, mappable_count, size, mappable_size);
341
342 size = count = mappable_size = mappable_count = 0;
343 count_vmas(&vm->inactive_list, mm_list);
344 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
345 count, mappable_count, size, mappable_size);
346
347 size = count = purgeable_size = purgeable_count = 0;
348 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
349 size += obj->base.size, ++count;
350 if (obj->madv == I915_MADV_DONTNEED)
351 purgeable_size += obj->base.size, ++purgeable_count;
352 }
353 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
354
355 size = count = mappable_size = mappable_count = 0;
356 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
357 if (obj->fault_mappable) {
358 size += i915_gem_obj_ggtt_size(obj);
359 ++count;
360 }
361 if (obj->pin_mappable) {
362 mappable_size += i915_gem_obj_ggtt_size(obj);
363 ++mappable_count;
364 }
365 if (obj->madv == I915_MADV_DONTNEED) {
366 purgeable_size += obj->base.size;
367 ++purgeable_count;
368 }
369 }
370 seq_printf(m, "%u purgeable objects, %zu bytes\n",
371 purgeable_count, purgeable_size);
372 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
373 mappable_count, mappable_size);
374 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
375 count, size);
376
377 seq_printf(m, "%zu [%lu] gtt total\n",
378 dev_priv->gtt.base.total,
379 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
380
381 seq_putc(m, '\n');
382 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
383 struct file_stats stats;
384
385 memset(&stats, 0, sizeof(stats));
386 idr_for_each(&file->object_idr, per_file_stats, &stats);
387 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
388 get_pid_task(file->pid, PIDTYPE_PID)->comm,
389 stats.count,
390 stats.total,
391 stats.active,
392 stats.inactive,
393 stats.unbound);
394 }
395
396 mutex_unlock(&dev->struct_mutex);
397
398 return 0;
399 }
400
401 static int i915_gem_gtt_info(struct seq_file *m, void *data)
402 {
403 struct drm_info_node *node = (struct drm_info_node *) m->private;
404 struct drm_device *dev = node->minor->dev;
405 uintptr_t list = (uintptr_t) node->info_ent->data;
406 struct drm_i915_private *dev_priv = dev->dev_private;
407 struct drm_i915_gem_object *obj;
408 size_t total_obj_size, total_gtt_size;
409 int count, ret;
410
411 ret = mutex_lock_interruptible(&dev->struct_mutex);
412 if (ret)
413 return ret;
414
415 total_obj_size = total_gtt_size = count = 0;
416 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
417 if (list == PINNED_LIST && obj->pin_count == 0)
418 continue;
419
420 seq_puts(m, " ");
421 describe_obj(m, obj);
422 seq_putc(m, '\n');
423 total_obj_size += obj->base.size;
424 total_gtt_size += i915_gem_obj_ggtt_size(obj);
425 count++;
426 }
427
428 mutex_unlock(&dev->struct_mutex);
429
430 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
431 count, total_obj_size, total_gtt_size);
432
433 return 0;
434 }
435
436 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
437 {
438 struct drm_info_node *node = (struct drm_info_node *) m->private;
439 struct drm_device *dev = node->minor->dev;
440 unsigned long flags;
441 struct intel_crtc *crtc;
442
443 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
444 const char pipe = pipe_name(crtc->pipe);
445 const char plane = plane_name(crtc->plane);
446 struct intel_unpin_work *work;
447
448 spin_lock_irqsave(&dev->event_lock, flags);
449 work = crtc->unpin_work;
450 if (work == NULL) {
451 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
452 pipe, plane);
453 } else {
454 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
455 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
456 pipe, plane);
457 } else {
458 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
459 pipe, plane);
460 }
461 if (work->enable_stall_check)
462 seq_puts(m, "Stall check enabled, ");
463 else
464 seq_puts(m, "Stall check waiting for page flip ioctl, ");
465 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
466
467 if (work->old_fb_obj) {
468 struct drm_i915_gem_object *obj = work->old_fb_obj;
469 if (obj)
470 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
471 i915_gem_obj_ggtt_offset(obj));
472 }
473 if (work->pending_flip_obj) {
474 struct drm_i915_gem_object *obj = work->pending_flip_obj;
475 if (obj)
476 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
477 i915_gem_obj_ggtt_offset(obj));
478 }
479 }
480 spin_unlock_irqrestore(&dev->event_lock, flags);
481 }
482
483 return 0;
484 }
485
486 static int i915_gem_request_info(struct seq_file *m, void *data)
487 {
488 struct drm_info_node *node = (struct drm_info_node *) m->private;
489 struct drm_device *dev = node->minor->dev;
490 drm_i915_private_t *dev_priv = dev->dev_private;
491 struct intel_ring_buffer *ring;
492 struct drm_i915_gem_request *gem_request;
493 int ret, count, i;
494
495 ret = mutex_lock_interruptible(&dev->struct_mutex);
496 if (ret)
497 return ret;
498
499 count = 0;
500 for_each_ring(ring, dev_priv, i) {
501 if (list_empty(&ring->request_list))
502 continue;
503
504 seq_printf(m, "%s requests:\n", ring->name);
505 list_for_each_entry(gem_request,
506 &ring->request_list,
507 list) {
508 seq_printf(m, " %d @ %d\n",
509 gem_request->seqno,
510 (int) (jiffies - gem_request->emitted_jiffies));
511 }
512 count++;
513 }
514 mutex_unlock(&dev->struct_mutex);
515
516 if (count == 0)
517 seq_puts(m, "No requests\n");
518
519 return 0;
520 }
521
522 static void i915_ring_seqno_info(struct seq_file *m,
523 struct intel_ring_buffer *ring)
524 {
525 if (ring->get_seqno) {
526 seq_printf(m, "Current sequence (%s): %u\n",
527 ring->name, ring->get_seqno(ring, false));
528 }
529 }
530
531 static int i915_gem_seqno_info(struct seq_file *m, void *data)
532 {
533 struct drm_info_node *node = (struct drm_info_node *) m->private;
534 struct drm_device *dev = node->minor->dev;
535 drm_i915_private_t *dev_priv = dev->dev_private;
536 struct intel_ring_buffer *ring;
537 int ret, i;
538
539 ret = mutex_lock_interruptible(&dev->struct_mutex);
540 if (ret)
541 return ret;
542
543 for_each_ring(ring, dev_priv, i)
544 i915_ring_seqno_info(m, ring);
545
546 mutex_unlock(&dev->struct_mutex);
547
548 return 0;
549 }
550
551
552 static int i915_interrupt_info(struct seq_file *m, void *data)
553 {
554 struct drm_info_node *node = (struct drm_info_node *) m->private;
555 struct drm_device *dev = node->minor->dev;
556 drm_i915_private_t *dev_priv = dev->dev_private;
557 struct intel_ring_buffer *ring;
558 int ret, i, pipe;
559
560 ret = mutex_lock_interruptible(&dev->struct_mutex);
561 if (ret)
562 return ret;
563
564 if (IS_VALLEYVIEW(dev)) {
565 seq_printf(m, "Display IER:\t%08x\n",
566 I915_READ(VLV_IER));
567 seq_printf(m, "Display IIR:\t%08x\n",
568 I915_READ(VLV_IIR));
569 seq_printf(m, "Display IIR_RW:\t%08x\n",
570 I915_READ(VLV_IIR_RW));
571 seq_printf(m, "Display IMR:\t%08x\n",
572 I915_READ(VLV_IMR));
573 for_each_pipe(pipe)
574 seq_printf(m, "Pipe %c stat:\t%08x\n",
575 pipe_name(pipe),
576 I915_READ(PIPESTAT(pipe)));
577
578 seq_printf(m, "Master IER:\t%08x\n",
579 I915_READ(VLV_MASTER_IER));
580
581 seq_printf(m, "Render IER:\t%08x\n",
582 I915_READ(GTIER));
583 seq_printf(m, "Render IIR:\t%08x\n",
584 I915_READ(GTIIR));
585 seq_printf(m, "Render IMR:\t%08x\n",
586 I915_READ(GTIMR));
587
588 seq_printf(m, "PM IER:\t\t%08x\n",
589 I915_READ(GEN6_PMIER));
590 seq_printf(m, "PM IIR:\t\t%08x\n",
591 I915_READ(GEN6_PMIIR));
592 seq_printf(m, "PM IMR:\t\t%08x\n",
593 I915_READ(GEN6_PMIMR));
594
595 seq_printf(m, "Port hotplug:\t%08x\n",
596 I915_READ(PORT_HOTPLUG_EN));
597 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
598 I915_READ(VLV_DPFLIPSTAT));
599 seq_printf(m, "DPINVGTT:\t%08x\n",
600 I915_READ(DPINVGTT));
601
602 } else if (!HAS_PCH_SPLIT(dev)) {
603 seq_printf(m, "Interrupt enable: %08x\n",
604 I915_READ(IER));
605 seq_printf(m, "Interrupt identity: %08x\n",
606 I915_READ(IIR));
607 seq_printf(m, "Interrupt mask: %08x\n",
608 I915_READ(IMR));
609 for_each_pipe(pipe)
610 seq_printf(m, "Pipe %c stat: %08x\n",
611 pipe_name(pipe),
612 I915_READ(PIPESTAT(pipe)));
613 } else {
614 seq_printf(m, "North Display Interrupt enable: %08x\n",
615 I915_READ(DEIER));
616 seq_printf(m, "North Display Interrupt identity: %08x\n",
617 I915_READ(DEIIR));
618 seq_printf(m, "North Display Interrupt mask: %08x\n",
619 I915_READ(DEIMR));
620 seq_printf(m, "South Display Interrupt enable: %08x\n",
621 I915_READ(SDEIER));
622 seq_printf(m, "South Display Interrupt identity: %08x\n",
623 I915_READ(SDEIIR));
624 seq_printf(m, "South Display Interrupt mask: %08x\n",
625 I915_READ(SDEIMR));
626 seq_printf(m, "Graphics Interrupt enable: %08x\n",
627 I915_READ(GTIER));
628 seq_printf(m, "Graphics Interrupt identity: %08x\n",
629 I915_READ(GTIIR));
630 seq_printf(m, "Graphics Interrupt mask: %08x\n",
631 I915_READ(GTIMR));
632 }
633 seq_printf(m, "Interrupts received: %d\n",
634 atomic_read(&dev_priv->irq_received));
635 for_each_ring(ring, dev_priv, i) {
636 if (IS_GEN6(dev) || IS_GEN7(dev)) {
637 seq_printf(m,
638 "Graphics Interrupt mask (%s): %08x\n",
639 ring->name, I915_READ_IMR(ring));
640 }
641 i915_ring_seqno_info(m, ring);
642 }
643 mutex_unlock(&dev->struct_mutex);
644
645 return 0;
646 }
647
648 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
649 {
650 struct drm_info_node *node = (struct drm_info_node *) m->private;
651 struct drm_device *dev = node->minor->dev;
652 drm_i915_private_t *dev_priv = dev->dev_private;
653 int i, ret;
654
655 ret = mutex_lock_interruptible(&dev->struct_mutex);
656 if (ret)
657 return ret;
658
659 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
660 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
661 for (i = 0; i < dev_priv->num_fence_regs; i++) {
662 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
663
664 seq_printf(m, "Fence %d, pin count = %d, object = ",
665 i, dev_priv->fence_regs[i].pin_count);
666 if (obj == NULL)
667 seq_puts(m, "unused");
668 else
669 describe_obj(m, obj);
670 seq_putc(m, '\n');
671 }
672
673 mutex_unlock(&dev->struct_mutex);
674 return 0;
675 }
676
677 static int i915_hws_info(struct seq_file *m, void *data)
678 {
679 struct drm_info_node *node = (struct drm_info_node *) m->private;
680 struct drm_device *dev = node->minor->dev;
681 drm_i915_private_t *dev_priv = dev->dev_private;
682 struct intel_ring_buffer *ring;
683 const u32 *hws;
684 int i;
685
686 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
687 hws = ring->status_page.page_addr;
688 if (hws == NULL)
689 return 0;
690
691 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
692 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
693 i * 4,
694 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
695 }
696 return 0;
697 }
698
699 static ssize_t
700 i915_error_state_write(struct file *filp,
701 const char __user *ubuf,
702 size_t cnt,
703 loff_t *ppos)
704 {
705 struct i915_error_state_file_priv *error_priv = filp->private_data;
706 struct drm_device *dev = error_priv->dev;
707 int ret;
708
709 DRM_DEBUG_DRIVER("Resetting error state\n");
710
711 ret = mutex_lock_interruptible(&dev->struct_mutex);
712 if (ret)
713 return ret;
714
715 i915_destroy_error_state(dev);
716 mutex_unlock(&dev->struct_mutex);
717
718 return cnt;
719 }
720
721 static int i915_error_state_open(struct inode *inode, struct file *file)
722 {
723 struct drm_device *dev = inode->i_private;
724 struct i915_error_state_file_priv *error_priv;
725
726 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
727 if (!error_priv)
728 return -ENOMEM;
729
730 error_priv->dev = dev;
731
732 i915_error_state_get(dev, error_priv);
733
734 file->private_data = error_priv;
735
736 return 0;
737 }
738
739 static int i915_error_state_release(struct inode *inode, struct file *file)
740 {
741 struct i915_error_state_file_priv *error_priv = file->private_data;
742
743 i915_error_state_put(error_priv);
744 kfree(error_priv);
745
746 return 0;
747 }
748
749 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
750 size_t count, loff_t *pos)
751 {
752 struct i915_error_state_file_priv *error_priv = file->private_data;
753 struct drm_i915_error_state_buf error_str;
754 loff_t tmp_pos = 0;
755 ssize_t ret_count = 0;
756 int ret;
757
758 ret = i915_error_state_buf_init(&error_str, count, *pos);
759 if (ret)
760 return ret;
761
762 ret = i915_error_state_to_str(&error_str, error_priv);
763 if (ret)
764 goto out;
765
766 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
767 error_str.buf,
768 error_str.bytes);
769
770 if (ret_count < 0)
771 ret = ret_count;
772 else
773 *pos = error_str.start + ret_count;
774 out:
775 i915_error_state_buf_release(&error_str);
776 return ret ?: ret_count;
777 }
778
779 static const struct file_operations i915_error_state_fops = {
780 .owner = THIS_MODULE,
781 .open = i915_error_state_open,
782 .read = i915_error_state_read,
783 .write = i915_error_state_write,
784 .llseek = default_llseek,
785 .release = i915_error_state_release,
786 };
787
788 static int
789 i915_next_seqno_get(void *data, u64 *val)
790 {
791 struct drm_device *dev = data;
792 drm_i915_private_t *dev_priv = dev->dev_private;
793 int ret;
794
795 ret = mutex_lock_interruptible(&dev->struct_mutex);
796 if (ret)
797 return ret;
798
799 *val = dev_priv->next_seqno;
800 mutex_unlock(&dev->struct_mutex);
801
802 return 0;
803 }
804
805 static int
806 i915_next_seqno_set(void *data, u64 val)
807 {
808 struct drm_device *dev = data;
809 int ret;
810
811 ret = mutex_lock_interruptible(&dev->struct_mutex);
812 if (ret)
813 return ret;
814
815 ret = i915_gem_set_seqno(dev, val);
816 mutex_unlock(&dev->struct_mutex);
817
818 return ret;
819 }
820
821 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
822 i915_next_seqno_get, i915_next_seqno_set,
823 "0x%llx\n");
824
825 static int i915_rstdby_delays(struct seq_file *m, void *unused)
826 {
827 struct drm_info_node *node = (struct drm_info_node *) m->private;
828 struct drm_device *dev = node->minor->dev;
829 drm_i915_private_t *dev_priv = dev->dev_private;
830 u16 crstanddelay;
831 int ret;
832
833 ret = mutex_lock_interruptible(&dev->struct_mutex);
834 if (ret)
835 return ret;
836
837 crstanddelay = I915_READ16(CRSTANDVID);
838
839 mutex_unlock(&dev->struct_mutex);
840
841 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
842
843 return 0;
844 }
845
846 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
847 {
848 struct drm_info_node *node = (struct drm_info_node *) m->private;
849 struct drm_device *dev = node->minor->dev;
850 drm_i915_private_t *dev_priv = dev->dev_private;
851 int ret;
852
853 if (IS_GEN5(dev)) {
854 u16 rgvswctl = I915_READ16(MEMSWCTL);
855 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
856
857 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
858 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
859 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
860 MEMSTAT_VID_SHIFT);
861 seq_printf(m, "Current P-state: %d\n",
862 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
863 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
864 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
865 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
866 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
867 u32 rpstat, cagf, reqf;
868 u32 rpupei, rpcurup, rpprevup;
869 u32 rpdownei, rpcurdown, rpprevdown;
870 int max_freq;
871
872 /* RPSTAT1 is in the GT power well */
873 ret = mutex_lock_interruptible(&dev->struct_mutex);
874 if (ret)
875 return ret;
876
877 gen6_gt_force_wake_get(dev_priv);
878
879 reqf = I915_READ(GEN6_RPNSWREQ);
880 reqf &= ~GEN6_TURBO_DISABLE;
881 if (IS_HASWELL(dev))
882 reqf >>= 24;
883 else
884 reqf >>= 25;
885 reqf *= GT_FREQUENCY_MULTIPLIER;
886
887 rpstat = I915_READ(GEN6_RPSTAT1);
888 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
889 rpcurup = I915_READ(GEN6_RP_CUR_UP);
890 rpprevup = I915_READ(GEN6_RP_PREV_UP);
891 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
892 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
893 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
894 if (IS_HASWELL(dev))
895 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
896 else
897 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
898 cagf *= GT_FREQUENCY_MULTIPLIER;
899
900 gen6_gt_force_wake_put(dev_priv);
901 mutex_unlock(&dev->struct_mutex);
902
903 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
904 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
905 seq_printf(m, "Render p-state ratio: %d\n",
906 (gt_perf_status & 0xff00) >> 8);
907 seq_printf(m, "Render p-state VID: %d\n",
908 gt_perf_status & 0xff);
909 seq_printf(m, "Render p-state limit: %d\n",
910 rp_state_limits & 0xff);
911 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
912 seq_printf(m, "CAGF: %dMHz\n", cagf);
913 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
914 GEN6_CURICONT_MASK);
915 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
916 GEN6_CURBSYTAVG_MASK);
917 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
918 GEN6_CURBSYTAVG_MASK);
919 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
920 GEN6_CURIAVG_MASK);
921 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
922 GEN6_CURBSYTAVG_MASK);
923 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
924 GEN6_CURBSYTAVG_MASK);
925
926 max_freq = (rp_state_cap & 0xff0000) >> 16;
927 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
928 max_freq * GT_FREQUENCY_MULTIPLIER);
929
930 max_freq = (rp_state_cap & 0xff00) >> 8;
931 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
932 max_freq * GT_FREQUENCY_MULTIPLIER);
933
934 max_freq = rp_state_cap & 0xff;
935 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
936 max_freq * GT_FREQUENCY_MULTIPLIER);
937
938 seq_printf(m, "Max overclocked frequency: %dMHz\n",
939 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
940 } else if (IS_VALLEYVIEW(dev)) {
941 u32 freq_sts, val;
942
943 mutex_lock(&dev_priv->rps.hw_lock);
944 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
945 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
946 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
947
948 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
949 seq_printf(m, "max GPU freq: %d MHz\n",
950 vlv_gpu_freq(dev_priv->mem_freq, val));
951
952 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
953 seq_printf(m, "min GPU freq: %d MHz\n",
954 vlv_gpu_freq(dev_priv->mem_freq, val));
955
956 seq_printf(m, "current GPU freq: %d MHz\n",
957 vlv_gpu_freq(dev_priv->mem_freq,
958 (freq_sts >> 8) & 0xff));
959 mutex_unlock(&dev_priv->rps.hw_lock);
960 } else {
961 seq_puts(m, "no P-state info available\n");
962 }
963
964 return 0;
965 }
966
967 static int i915_delayfreq_table(struct seq_file *m, void *unused)
968 {
969 struct drm_info_node *node = (struct drm_info_node *) m->private;
970 struct drm_device *dev = node->minor->dev;
971 drm_i915_private_t *dev_priv = dev->dev_private;
972 u32 delayfreq;
973 int ret, i;
974
975 ret = mutex_lock_interruptible(&dev->struct_mutex);
976 if (ret)
977 return ret;
978
979 for (i = 0; i < 16; i++) {
980 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
981 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
982 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
983 }
984
985 mutex_unlock(&dev->struct_mutex);
986
987 return 0;
988 }
989
990 static inline int MAP_TO_MV(int map)
991 {
992 return 1250 - (map * 25);
993 }
994
995 static int i915_inttoext_table(struct seq_file *m, void *unused)
996 {
997 struct drm_info_node *node = (struct drm_info_node *) m->private;
998 struct drm_device *dev = node->minor->dev;
999 drm_i915_private_t *dev_priv = dev->dev_private;
1000 u32 inttoext;
1001 int ret, i;
1002
1003 ret = mutex_lock_interruptible(&dev->struct_mutex);
1004 if (ret)
1005 return ret;
1006
1007 for (i = 1; i <= 32; i++) {
1008 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1009 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1010 }
1011
1012 mutex_unlock(&dev->struct_mutex);
1013
1014 return 0;
1015 }
1016
1017 static int ironlake_drpc_info(struct seq_file *m)
1018 {
1019 struct drm_info_node *node = (struct drm_info_node *) m->private;
1020 struct drm_device *dev = node->minor->dev;
1021 drm_i915_private_t *dev_priv = dev->dev_private;
1022 u32 rgvmodectl, rstdbyctl;
1023 u16 crstandvid;
1024 int ret;
1025
1026 ret = mutex_lock_interruptible(&dev->struct_mutex);
1027 if (ret)
1028 return ret;
1029
1030 rgvmodectl = I915_READ(MEMMODECTL);
1031 rstdbyctl = I915_READ(RSTDBYCTL);
1032 crstandvid = I915_READ16(CRSTANDVID);
1033
1034 mutex_unlock(&dev->struct_mutex);
1035
1036 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1037 "yes" : "no");
1038 seq_printf(m, "Boost freq: %d\n",
1039 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1040 MEMMODE_BOOST_FREQ_SHIFT);
1041 seq_printf(m, "HW control enabled: %s\n",
1042 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1043 seq_printf(m, "SW control enabled: %s\n",
1044 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1045 seq_printf(m, "Gated voltage change: %s\n",
1046 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1047 seq_printf(m, "Starting frequency: P%d\n",
1048 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1049 seq_printf(m, "Max P-state: P%d\n",
1050 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1051 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1052 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1053 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1054 seq_printf(m, "Render standby enabled: %s\n",
1055 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1056 seq_puts(m, "Current RS state: ");
1057 switch (rstdbyctl & RSX_STATUS_MASK) {
1058 case RSX_STATUS_ON:
1059 seq_puts(m, "on\n");
1060 break;
1061 case RSX_STATUS_RC1:
1062 seq_puts(m, "RC1\n");
1063 break;
1064 case RSX_STATUS_RC1E:
1065 seq_puts(m, "RC1E\n");
1066 break;
1067 case RSX_STATUS_RS1:
1068 seq_puts(m, "RS1\n");
1069 break;
1070 case RSX_STATUS_RS2:
1071 seq_puts(m, "RS2 (RC6)\n");
1072 break;
1073 case RSX_STATUS_RS3:
1074 seq_puts(m, "RC3 (RC6+)\n");
1075 break;
1076 default:
1077 seq_puts(m, "unknown\n");
1078 break;
1079 }
1080
1081 return 0;
1082 }
1083
1084 static int gen6_drpc_info(struct seq_file *m)
1085 {
1086
1087 struct drm_info_node *node = (struct drm_info_node *) m->private;
1088 struct drm_device *dev = node->minor->dev;
1089 struct drm_i915_private *dev_priv = dev->dev_private;
1090 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1091 unsigned forcewake_count;
1092 int count = 0, ret;
1093
1094 ret = mutex_lock_interruptible(&dev->struct_mutex);
1095 if (ret)
1096 return ret;
1097
1098 spin_lock_irq(&dev_priv->uncore.lock);
1099 forcewake_count = dev_priv->uncore.forcewake_count;
1100 spin_unlock_irq(&dev_priv->uncore.lock);
1101
1102 if (forcewake_count) {
1103 seq_puts(m, "RC information inaccurate because somebody "
1104 "holds a forcewake reference \n");
1105 } else {
1106 /* NB: we cannot use forcewake, else we read the wrong values */
1107 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1108 udelay(10);
1109 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1110 }
1111
1112 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1113 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1114
1115 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1116 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1117 mutex_unlock(&dev->struct_mutex);
1118 mutex_lock(&dev_priv->rps.hw_lock);
1119 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1120 mutex_unlock(&dev_priv->rps.hw_lock);
1121
1122 seq_printf(m, "Video Turbo Mode: %s\n",
1123 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1124 seq_printf(m, "HW control enabled: %s\n",
1125 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1126 seq_printf(m, "SW control enabled: %s\n",
1127 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1128 GEN6_RP_MEDIA_SW_MODE));
1129 seq_printf(m, "RC1e Enabled: %s\n",
1130 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1131 seq_printf(m, "RC6 Enabled: %s\n",
1132 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1133 seq_printf(m, "Deep RC6 Enabled: %s\n",
1134 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1135 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1136 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1137 seq_puts(m, "Current RC state: ");
1138 switch (gt_core_status & GEN6_RCn_MASK) {
1139 case GEN6_RC0:
1140 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1141 seq_puts(m, "Core Power Down\n");
1142 else
1143 seq_puts(m, "on\n");
1144 break;
1145 case GEN6_RC3:
1146 seq_puts(m, "RC3\n");
1147 break;
1148 case GEN6_RC6:
1149 seq_puts(m, "RC6\n");
1150 break;
1151 case GEN6_RC7:
1152 seq_puts(m, "RC7\n");
1153 break;
1154 default:
1155 seq_puts(m, "Unknown\n");
1156 break;
1157 }
1158
1159 seq_printf(m, "Core Power Down: %s\n",
1160 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1161
1162 /* Not exactly sure what this is */
1163 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1164 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1165 seq_printf(m, "RC6 residency since boot: %u\n",
1166 I915_READ(GEN6_GT_GFX_RC6));
1167 seq_printf(m, "RC6+ residency since boot: %u\n",
1168 I915_READ(GEN6_GT_GFX_RC6p));
1169 seq_printf(m, "RC6++ residency since boot: %u\n",
1170 I915_READ(GEN6_GT_GFX_RC6pp));
1171
1172 seq_printf(m, "RC6 voltage: %dmV\n",
1173 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1174 seq_printf(m, "RC6+ voltage: %dmV\n",
1175 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1176 seq_printf(m, "RC6++ voltage: %dmV\n",
1177 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1178 return 0;
1179 }
1180
1181 static int i915_drpc_info(struct seq_file *m, void *unused)
1182 {
1183 struct drm_info_node *node = (struct drm_info_node *) m->private;
1184 struct drm_device *dev = node->minor->dev;
1185
1186 if (IS_GEN6(dev) || IS_GEN7(dev))
1187 return gen6_drpc_info(m);
1188 else
1189 return ironlake_drpc_info(m);
1190 }
1191
1192 static int i915_fbc_status(struct seq_file *m, void *unused)
1193 {
1194 struct drm_info_node *node = (struct drm_info_node *) m->private;
1195 struct drm_device *dev = node->minor->dev;
1196 drm_i915_private_t *dev_priv = dev->dev_private;
1197
1198 if (!I915_HAS_FBC(dev)) {
1199 seq_puts(m, "FBC unsupported on this chipset\n");
1200 return 0;
1201 }
1202
1203 if (intel_fbc_enabled(dev)) {
1204 seq_puts(m, "FBC enabled\n");
1205 } else {
1206 seq_puts(m, "FBC disabled: ");
1207 switch (dev_priv->fbc.no_fbc_reason) {
1208 case FBC_OK:
1209 seq_puts(m, "FBC actived, but currently disabled in hardware");
1210 break;
1211 case FBC_UNSUPPORTED:
1212 seq_puts(m, "unsupported by this chipset");
1213 break;
1214 case FBC_NO_OUTPUT:
1215 seq_puts(m, "no outputs");
1216 break;
1217 case FBC_STOLEN_TOO_SMALL:
1218 seq_puts(m, "not enough stolen memory");
1219 break;
1220 case FBC_UNSUPPORTED_MODE:
1221 seq_puts(m, "mode not supported");
1222 break;
1223 case FBC_MODE_TOO_LARGE:
1224 seq_puts(m, "mode too large");
1225 break;
1226 case FBC_BAD_PLANE:
1227 seq_puts(m, "FBC unsupported on plane");
1228 break;
1229 case FBC_NOT_TILED:
1230 seq_puts(m, "scanout buffer not tiled");
1231 break;
1232 case FBC_MULTIPLE_PIPES:
1233 seq_puts(m, "multiple pipes are enabled");
1234 break;
1235 case FBC_MODULE_PARAM:
1236 seq_puts(m, "disabled per module param (default off)");
1237 break;
1238 case FBC_CHIP_DEFAULT:
1239 seq_puts(m, "disabled per chip default");
1240 break;
1241 default:
1242 seq_puts(m, "unknown reason");
1243 }
1244 seq_putc(m, '\n');
1245 }
1246 return 0;
1247 }
1248
1249 static int i915_ips_status(struct seq_file *m, void *unused)
1250 {
1251 struct drm_info_node *node = (struct drm_info_node *) m->private;
1252 struct drm_device *dev = node->minor->dev;
1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254
1255 if (!HAS_IPS(dev)) {
1256 seq_puts(m, "not supported\n");
1257 return 0;
1258 }
1259
1260 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1261 seq_puts(m, "enabled\n");
1262 else
1263 seq_puts(m, "disabled\n");
1264
1265 return 0;
1266 }
1267
1268 static int i915_sr_status(struct seq_file *m, void *unused)
1269 {
1270 struct drm_info_node *node = (struct drm_info_node *) m->private;
1271 struct drm_device *dev = node->minor->dev;
1272 drm_i915_private_t *dev_priv = dev->dev_private;
1273 bool sr_enabled = false;
1274
1275 if (HAS_PCH_SPLIT(dev))
1276 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1277 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1278 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1279 else if (IS_I915GM(dev))
1280 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1281 else if (IS_PINEVIEW(dev))
1282 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1283
1284 seq_printf(m, "self-refresh: %s\n",
1285 sr_enabled ? "enabled" : "disabled");
1286
1287 return 0;
1288 }
1289
1290 static int i915_emon_status(struct seq_file *m, void *unused)
1291 {
1292 struct drm_info_node *node = (struct drm_info_node *) m->private;
1293 struct drm_device *dev = node->minor->dev;
1294 drm_i915_private_t *dev_priv = dev->dev_private;
1295 unsigned long temp, chipset, gfx;
1296 int ret;
1297
1298 if (!IS_GEN5(dev))
1299 return -ENODEV;
1300
1301 ret = mutex_lock_interruptible(&dev->struct_mutex);
1302 if (ret)
1303 return ret;
1304
1305 temp = i915_mch_val(dev_priv);
1306 chipset = i915_chipset_val(dev_priv);
1307 gfx = i915_gfx_val(dev_priv);
1308 mutex_unlock(&dev->struct_mutex);
1309
1310 seq_printf(m, "GMCH temp: %ld\n", temp);
1311 seq_printf(m, "Chipset power: %ld\n", chipset);
1312 seq_printf(m, "GFX power: %ld\n", gfx);
1313 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1314
1315 return 0;
1316 }
1317
1318 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1319 {
1320 struct drm_info_node *node = (struct drm_info_node *) m->private;
1321 struct drm_device *dev = node->minor->dev;
1322 drm_i915_private_t *dev_priv = dev->dev_private;
1323 int ret;
1324 int gpu_freq, ia_freq;
1325
1326 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1327 seq_puts(m, "unsupported on this chipset\n");
1328 return 0;
1329 }
1330
1331 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1332 if (ret)
1333 return ret;
1334
1335 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1336
1337 for (gpu_freq = dev_priv->rps.min_delay;
1338 gpu_freq <= dev_priv->rps.max_delay;
1339 gpu_freq++) {
1340 ia_freq = gpu_freq;
1341 sandybridge_pcode_read(dev_priv,
1342 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1343 &ia_freq);
1344 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1345 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1346 ((ia_freq >> 0) & 0xff) * 100,
1347 ((ia_freq >> 8) & 0xff) * 100);
1348 }
1349
1350 mutex_unlock(&dev_priv->rps.hw_lock);
1351
1352 return 0;
1353 }
1354
1355 static int i915_gfxec(struct seq_file *m, void *unused)
1356 {
1357 struct drm_info_node *node = (struct drm_info_node *) m->private;
1358 struct drm_device *dev = node->minor->dev;
1359 drm_i915_private_t *dev_priv = dev->dev_private;
1360 int ret;
1361
1362 ret = mutex_lock_interruptible(&dev->struct_mutex);
1363 if (ret)
1364 return ret;
1365
1366 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1367
1368 mutex_unlock(&dev->struct_mutex);
1369
1370 return 0;
1371 }
1372
1373 static int i915_opregion(struct seq_file *m, void *unused)
1374 {
1375 struct drm_info_node *node = (struct drm_info_node *) m->private;
1376 struct drm_device *dev = node->minor->dev;
1377 drm_i915_private_t *dev_priv = dev->dev_private;
1378 struct intel_opregion *opregion = &dev_priv->opregion;
1379 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1380 int ret;
1381
1382 if (data == NULL)
1383 return -ENOMEM;
1384
1385 ret = mutex_lock_interruptible(&dev->struct_mutex);
1386 if (ret)
1387 goto out;
1388
1389 if (opregion->header) {
1390 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1391 seq_write(m, data, OPREGION_SIZE);
1392 }
1393
1394 mutex_unlock(&dev->struct_mutex);
1395
1396 out:
1397 kfree(data);
1398 return 0;
1399 }
1400
1401 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1402 {
1403 struct drm_info_node *node = (struct drm_info_node *) m->private;
1404 struct drm_device *dev = node->minor->dev;
1405 drm_i915_private_t *dev_priv = dev->dev_private;
1406 struct intel_fbdev *ifbdev;
1407 struct intel_framebuffer *fb;
1408 int ret;
1409
1410 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1411 if (ret)
1412 return ret;
1413
1414 ifbdev = dev_priv->fbdev;
1415 fb = to_intel_framebuffer(ifbdev->helper.fb);
1416
1417 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1418 fb->base.width,
1419 fb->base.height,
1420 fb->base.depth,
1421 fb->base.bits_per_pixel,
1422 atomic_read(&fb->base.refcount.refcount));
1423 describe_obj(m, fb->obj);
1424 seq_putc(m, '\n');
1425 mutex_unlock(&dev->mode_config.mutex);
1426
1427 mutex_lock(&dev->mode_config.fb_lock);
1428 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1429 if (&fb->base == ifbdev->helper.fb)
1430 continue;
1431
1432 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1433 fb->base.width,
1434 fb->base.height,
1435 fb->base.depth,
1436 fb->base.bits_per_pixel,
1437 atomic_read(&fb->base.refcount.refcount));
1438 describe_obj(m, fb->obj);
1439 seq_putc(m, '\n');
1440 }
1441 mutex_unlock(&dev->mode_config.fb_lock);
1442
1443 return 0;
1444 }
1445
1446 static int i915_context_status(struct seq_file *m, void *unused)
1447 {
1448 struct drm_info_node *node = (struct drm_info_node *) m->private;
1449 struct drm_device *dev = node->minor->dev;
1450 drm_i915_private_t *dev_priv = dev->dev_private;
1451 struct intel_ring_buffer *ring;
1452 struct i915_hw_context *ctx;
1453 int ret, i;
1454
1455 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1456 if (ret)
1457 return ret;
1458
1459 if (dev_priv->ips.pwrctx) {
1460 seq_puts(m, "power context ");
1461 describe_obj(m, dev_priv->ips.pwrctx);
1462 seq_putc(m, '\n');
1463 }
1464
1465 if (dev_priv->ips.renderctx) {
1466 seq_puts(m, "render context ");
1467 describe_obj(m, dev_priv->ips.renderctx);
1468 seq_putc(m, '\n');
1469 }
1470
1471 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1472 seq_puts(m, "HW context ");
1473 describe_ctx(m, ctx);
1474 for_each_ring(ring, dev_priv, i)
1475 if (ring->default_context == ctx)
1476 seq_printf(m, "(default context %s) ", ring->name);
1477
1478 describe_obj(m, ctx->obj);
1479 seq_putc(m, '\n');
1480 }
1481
1482 mutex_unlock(&dev->mode_config.mutex);
1483
1484 return 0;
1485 }
1486
1487 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1488 {
1489 struct drm_info_node *node = (struct drm_info_node *) m->private;
1490 struct drm_device *dev = node->minor->dev;
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 unsigned forcewake_count;
1493
1494 spin_lock_irq(&dev_priv->uncore.lock);
1495 forcewake_count = dev_priv->uncore.forcewake_count;
1496 spin_unlock_irq(&dev_priv->uncore.lock);
1497
1498 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1499
1500 return 0;
1501 }
1502
1503 static const char *swizzle_string(unsigned swizzle)
1504 {
1505 switch (swizzle) {
1506 case I915_BIT_6_SWIZZLE_NONE:
1507 return "none";
1508 case I915_BIT_6_SWIZZLE_9:
1509 return "bit9";
1510 case I915_BIT_6_SWIZZLE_9_10:
1511 return "bit9/bit10";
1512 case I915_BIT_6_SWIZZLE_9_11:
1513 return "bit9/bit11";
1514 case I915_BIT_6_SWIZZLE_9_10_11:
1515 return "bit9/bit10/bit11";
1516 case I915_BIT_6_SWIZZLE_9_17:
1517 return "bit9/bit17";
1518 case I915_BIT_6_SWIZZLE_9_10_17:
1519 return "bit9/bit10/bit17";
1520 case I915_BIT_6_SWIZZLE_UNKNOWN:
1521 return "unknown";
1522 }
1523
1524 return "bug";
1525 }
1526
1527 static int i915_swizzle_info(struct seq_file *m, void *data)
1528 {
1529 struct drm_info_node *node = (struct drm_info_node *) m->private;
1530 struct drm_device *dev = node->minor->dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 int ret;
1533
1534 ret = mutex_lock_interruptible(&dev->struct_mutex);
1535 if (ret)
1536 return ret;
1537
1538 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1539 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1540 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1541 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1542
1543 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1544 seq_printf(m, "DDC = 0x%08x\n",
1545 I915_READ(DCC));
1546 seq_printf(m, "C0DRB3 = 0x%04x\n",
1547 I915_READ16(C0DRB3));
1548 seq_printf(m, "C1DRB3 = 0x%04x\n",
1549 I915_READ16(C1DRB3));
1550 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1551 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1552 I915_READ(MAD_DIMM_C0));
1553 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1554 I915_READ(MAD_DIMM_C1));
1555 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1556 I915_READ(MAD_DIMM_C2));
1557 seq_printf(m, "TILECTL = 0x%08x\n",
1558 I915_READ(TILECTL));
1559 seq_printf(m, "ARB_MODE = 0x%08x\n",
1560 I915_READ(ARB_MODE));
1561 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1562 I915_READ(DISP_ARB_CTL));
1563 }
1564 mutex_unlock(&dev->struct_mutex);
1565
1566 return 0;
1567 }
1568
1569 static int i915_ppgtt_info(struct seq_file *m, void *data)
1570 {
1571 struct drm_info_node *node = (struct drm_info_node *) m->private;
1572 struct drm_device *dev = node->minor->dev;
1573 struct drm_i915_private *dev_priv = dev->dev_private;
1574 struct intel_ring_buffer *ring;
1575 int i, ret;
1576
1577
1578 ret = mutex_lock_interruptible(&dev->struct_mutex);
1579 if (ret)
1580 return ret;
1581 if (INTEL_INFO(dev)->gen == 6)
1582 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1583
1584 for_each_ring(ring, dev_priv, i) {
1585 seq_printf(m, "%s\n", ring->name);
1586 if (INTEL_INFO(dev)->gen == 7)
1587 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1588 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1589 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1590 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1591 }
1592 if (dev_priv->mm.aliasing_ppgtt) {
1593 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1594
1595 seq_puts(m, "aliasing PPGTT:\n");
1596 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1597 }
1598 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1599 mutex_unlock(&dev->struct_mutex);
1600
1601 return 0;
1602 }
1603
1604 static int i915_dpio_info(struct seq_file *m, void *data)
1605 {
1606 struct drm_info_node *node = (struct drm_info_node *) m->private;
1607 struct drm_device *dev = node->minor->dev;
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 int ret;
1610
1611
1612 if (!IS_VALLEYVIEW(dev)) {
1613 seq_puts(m, "unsupported\n");
1614 return 0;
1615 }
1616
1617 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1618 if (ret)
1619 return ret;
1620
1621 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1622
1623 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1624 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
1625 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1626 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
1627
1628 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1629 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
1630 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1631 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
1632
1633 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1634 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
1635 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1636 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
1637
1638 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
1639 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
1640 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
1641 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
1642
1643 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1644 vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
1645
1646 mutex_unlock(&dev_priv->dpio_lock);
1647
1648 return 0;
1649 }
1650
1651 static int i915_llc(struct seq_file *m, void *data)
1652 {
1653 struct drm_info_node *node = (struct drm_info_node *) m->private;
1654 struct drm_device *dev = node->minor->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1658 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1659 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1660
1661 return 0;
1662 }
1663
1664 static int i915_edp_psr_status(struct seq_file *m, void *data)
1665 {
1666 struct drm_info_node *node = m->private;
1667 struct drm_device *dev = node->minor->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 psrstat, psrperf;
1670
1671 if (!HAS_PSR(dev)) {
1672 seq_puts(m, "PSR not supported on this platform\n");
1673 } else if (HAS_PSR(dev) &&
1674 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE) {
1675 seq_puts(m, "PSR enabled\n");
1676 } else {
1677 seq_puts(m, "PSR disabled: ");
1678 switch (dev_priv->no_psr_reason) {
1679 case PSR_NO_SOURCE:
1680 seq_puts(m, "not supported on this platform");
1681 break;
1682 case PSR_NO_SINK:
1683 seq_puts(m, "not supported by panel");
1684 break;
1685 case PSR_MODULE_PARAM:
1686 seq_puts(m, "disabled by flag");
1687 break;
1688 case PSR_CRTC_NOT_ACTIVE:
1689 seq_puts(m, "crtc not active");
1690 break;
1691 case PSR_PWR_WELL_ENABLED:
1692 seq_puts(m, "power well enabled");
1693 break;
1694 case PSR_NOT_TILED:
1695 seq_puts(m, "not tiled");
1696 break;
1697 case PSR_SPRITE_ENABLED:
1698 seq_puts(m, "sprite enabled");
1699 break;
1700 case PSR_S3D_ENABLED:
1701 seq_puts(m, "stereo 3d enabled");
1702 break;
1703 case PSR_INTERLACED_ENABLED:
1704 seq_puts(m, "interlaced enabled");
1705 break;
1706 case PSR_HSW_NOT_DDIA:
1707 seq_puts(m, "HSW ties PSR to DDI A (eDP)");
1708 break;
1709 default:
1710 seq_puts(m, "unknown reason");
1711 }
1712 seq_puts(m, "\n");
1713 return 0;
1714 }
1715
1716 psrstat = I915_READ(EDP_PSR_STATUS_CTL(dev));
1717
1718 seq_puts(m, "PSR Current State: ");
1719 switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
1720 case EDP_PSR_STATUS_STATE_IDLE:
1721 seq_puts(m, "Reset state\n");
1722 break;
1723 case EDP_PSR_STATUS_STATE_SRDONACK:
1724 seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n");
1725 break;
1726 case EDP_PSR_STATUS_STATE_SRDENT:
1727 seq_puts(m, "SRD entry\n");
1728 break;
1729 case EDP_PSR_STATUS_STATE_BUFOFF:
1730 seq_puts(m, "Wait for buffer turn off\n");
1731 break;
1732 case EDP_PSR_STATUS_STATE_BUFON:
1733 seq_puts(m, "Wait for buffer turn on\n");
1734 break;
1735 case EDP_PSR_STATUS_STATE_AUXACK:
1736 seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n");
1737 break;
1738 case EDP_PSR_STATUS_STATE_SRDOFFACK:
1739 seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n");
1740 break;
1741 default:
1742 seq_puts(m, "Unknown\n");
1743 break;
1744 }
1745
1746 seq_puts(m, "Link Status: ");
1747 switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
1748 case EDP_PSR_STATUS_LINK_FULL_OFF:
1749 seq_puts(m, "Link is fully off\n");
1750 break;
1751 case EDP_PSR_STATUS_LINK_FULL_ON:
1752 seq_puts(m, "Link is fully on\n");
1753 break;
1754 case EDP_PSR_STATUS_LINK_STANDBY:
1755 seq_puts(m, "Link is in standby\n");
1756 break;
1757 default:
1758 seq_puts(m, "Unknown\n");
1759 break;
1760 }
1761
1762 seq_printf(m, "PSR Entry Count: %u\n",
1763 psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
1764 EDP_PSR_STATUS_COUNT_MASK);
1765
1766 seq_printf(m, "Max Sleep Timer Counter: %u\n",
1767 psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
1768 EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
1769
1770 seq_printf(m, "Had AUX error: %s\n",
1771 yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
1772
1773 seq_printf(m, "Sending AUX: %s\n",
1774 yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
1775
1776 seq_printf(m, "Sending Idle: %s\n",
1777 yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
1778
1779 seq_printf(m, "Sending TP2 TP3: %s\n",
1780 yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
1781
1782 seq_printf(m, "Sending TP1: %s\n",
1783 yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
1784
1785 seq_printf(m, "Idle Count: %u\n",
1786 psrstat & EDP_PSR_STATUS_IDLE_MASK);
1787
1788 psrperf = (I915_READ(EDP_PSR_PERF_CNT(dev))) & EDP_PSR_PERF_CNT_MASK;
1789 seq_printf(m, "Performance Counter: %u\n", psrperf);
1790
1791 return 0;
1792 }
1793
1794 static int i915_energy_uJ(struct seq_file *m, void *data)
1795 {
1796 struct drm_info_node *node = m->private;
1797 struct drm_device *dev = node->minor->dev;
1798 struct drm_i915_private *dev_priv = dev->dev_private;
1799 u64 power;
1800 u32 units;
1801
1802 if (INTEL_INFO(dev)->gen < 6)
1803 return -ENODEV;
1804
1805 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1806 power = (power & 0x1f00) >> 8;
1807 units = 1000000 / (1 << power); /* convert to uJ */
1808 power = I915_READ(MCH_SECP_NRG_STTS);
1809 power *= units;
1810
1811 seq_printf(m, "%llu", (long long unsigned)power);
1812
1813 return 0;
1814 }
1815
1816 static int i915_pc8_status(struct seq_file *m, void *unused)
1817 {
1818 struct drm_info_node *node = (struct drm_info_node *) m->private;
1819 struct drm_device *dev = node->minor->dev;
1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821
1822 if (!IS_HASWELL(dev)) {
1823 seq_puts(m, "not supported\n");
1824 return 0;
1825 }
1826
1827 mutex_lock(&dev_priv->pc8.lock);
1828 seq_printf(m, "Requirements met: %s\n",
1829 yesno(dev_priv->pc8.requirements_met));
1830 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1831 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1832 seq_printf(m, "IRQs disabled: %s\n",
1833 yesno(dev_priv->pc8.irqs_disabled));
1834 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1835 mutex_unlock(&dev_priv->pc8.lock);
1836
1837 return 0;
1838 }
1839
1840 static int
1841 i915_wedged_get(void *data, u64 *val)
1842 {
1843 struct drm_device *dev = data;
1844 drm_i915_private_t *dev_priv = dev->dev_private;
1845
1846 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
1847
1848 return 0;
1849 }
1850
1851 static int
1852 i915_wedged_set(void *data, u64 val)
1853 {
1854 struct drm_device *dev = data;
1855
1856 DRM_INFO("Manually setting wedged to %llu\n", val);
1857 i915_handle_error(dev, val);
1858
1859 return 0;
1860 }
1861
1862 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1863 i915_wedged_get, i915_wedged_set,
1864 "%llu\n");
1865
1866 static int
1867 i915_ring_stop_get(void *data, u64 *val)
1868 {
1869 struct drm_device *dev = data;
1870 drm_i915_private_t *dev_priv = dev->dev_private;
1871
1872 *val = dev_priv->gpu_error.stop_rings;
1873
1874 return 0;
1875 }
1876
1877 static int
1878 i915_ring_stop_set(void *data, u64 val)
1879 {
1880 struct drm_device *dev = data;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 int ret;
1883
1884 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
1885
1886 ret = mutex_lock_interruptible(&dev->struct_mutex);
1887 if (ret)
1888 return ret;
1889
1890 dev_priv->gpu_error.stop_rings = val;
1891 mutex_unlock(&dev->struct_mutex);
1892
1893 return 0;
1894 }
1895
1896 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
1897 i915_ring_stop_get, i915_ring_stop_set,
1898 "0x%08llx\n");
1899
1900 #define DROP_UNBOUND 0x1
1901 #define DROP_BOUND 0x2
1902 #define DROP_RETIRE 0x4
1903 #define DROP_ACTIVE 0x8
1904 #define DROP_ALL (DROP_UNBOUND | \
1905 DROP_BOUND | \
1906 DROP_RETIRE | \
1907 DROP_ACTIVE)
1908 static int
1909 i915_drop_caches_get(void *data, u64 *val)
1910 {
1911 *val = DROP_ALL;
1912
1913 return 0;
1914 }
1915
1916 static int
1917 i915_drop_caches_set(void *data, u64 val)
1918 {
1919 struct drm_device *dev = data;
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 struct drm_i915_gem_object *obj, *next;
1922 struct i915_address_space *vm;
1923 struct i915_vma *vma, *x;
1924 int ret;
1925
1926 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val);
1927
1928 /* No need to check and wait for gpu resets, only libdrm auto-restarts
1929 * on ioctls on -EAGAIN. */
1930 ret = mutex_lock_interruptible(&dev->struct_mutex);
1931 if (ret)
1932 return ret;
1933
1934 if (val & DROP_ACTIVE) {
1935 ret = i915_gpu_idle(dev);
1936 if (ret)
1937 goto unlock;
1938 }
1939
1940 if (val & (DROP_RETIRE | DROP_ACTIVE))
1941 i915_gem_retire_requests(dev);
1942
1943 if (val & DROP_BOUND) {
1944 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1945 list_for_each_entry_safe(vma, x, &vm->inactive_list,
1946 mm_list) {
1947 if (vma->obj->pin_count)
1948 continue;
1949
1950 ret = i915_vma_unbind(vma);
1951 if (ret)
1952 goto unlock;
1953 }
1954 }
1955 }
1956
1957 if (val & DROP_UNBOUND) {
1958 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1959 global_list)
1960 if (obj->pages_pin_count == 0) {
1961 ret = i915_gem_object_put_pages(obj);
1962 if (ret)
1963 goto unlock;
1964 }
1965 }
1966
1967 unlock:
1968 mutex_unlock(&dev->struct_mutex);
1969
1970 return ret;
1971 }
1972
1973 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1974 i915_drop_caches_get, i915_drop_caches_set,
1975 "0x%08llx\n");
1976
1977 static int
1978 i915_max_freq_get(void *data, u64 *val)
1979 {
1980 struct drm_device *dev = data;
1981 drm_i915_private_t *dev_priv = dev->dev_private;
1982 int ret;
1983
1984 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1985 return -ENODEV;
1986
1987 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1988 if (ret)
1989 return ret;
1990
1991 if (IS_VALLEYVIEW(dev))
1992 *val = vlv_gpu_freq(dev_priv->mem_freq,
1993 dev_priv->rps.max_delay);
1994 else
1995 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
1996 mutex_unlock(&dev_priv->rps.hw_lock);
1997
1998 return 0;
1999 }
2000
2001 static int
2002 i915_max_freq_set(void *data, u64 val)
2003 {
2004 struct drm_device *dev = data;
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 int ret;
2007
2008 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2009 return -ENODEV;
2010
2011 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2012
2013 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2014 if (ret)
2015 return ret;
2016
2017 /*
2018 * Turbo will still be enabled, but won't go above the set value.
2019 */
2020 if (IS_VALLEYVIEW(dev)) {
2021 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2022 dev_priv->rps.max_delay = val;
2023 gen6_set_rps(dev, val);
2024 } else {
2025 do_div(val, GT_FREQUENCY_MULTIPLIER);
2026 dev_priv->rps.max_delay = val;
2027 gen6_set_rps(dev, val);
2028 }
2029
2030 mutex_unlock(&dev_priv->rps.hw_lock);
2031
2032 return 0;
2033 }
2034
2035 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2036 i915_max_freq_get, i915_max_freq_set,
2037 "%llu\n");
2038
2039 static int
2040 i915_min_freq_get(void *data, u64 *val)
2041 {
2042 struct drm_device *dev = data;
2043 drm_i915_private_t *dev_priv = dev->dev_private;
2044 int ret;
2045
2046 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2047 return -ENODEV;
2048
2049 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2050 if (ret)
2051 return ret;
2052
2053 if (IS_VALLEYVIEW(dev))
2054 *val = vlv_gpu_freq(dev_priv->mem_freq,
2055 dev_priv->rps.min_delay);
2056 else
2057 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2058 mutex_unlock(&dev_priv->rps.hw_lock);
2059
2060 return 0;
2061 }
2062
2063 static int
2064 i915_min_freq_set(void *data, u64 val)
2065 {
2066 struct drm_device *dev = data;
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 int ret;
2069
2070 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2071 return -ENODEV;
2072
2073 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
2074
2075 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2076 if (ret)
2077 return ret;
2078
2079 /*
2080 * Turbo will still be enabled, but won't go below the set value.
2081 */
2082 if (IS_VALLEYVIEW(dev)) {
2083 val = vlv_freq_opcode(dev_priv->mem_freq, val);
2084 dev_priv->rps.min_delay = val;
2085 valleyview_set_rps(dev, val);
2086 } else {
2087 do_div(val, GT_FREQUENCY_MULTIPLIER);
2088 dev_priv->rps.min_delay = val;
2089 gen6_set_rps(dev, val);
2090 }
2091 mutex_unlock(&dev_priv->rps.hw_lock);
2092
2093 return 0;
2094 }
2095
2096 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
2097 i915_min_freq_get, i915_min_freq_set,
2098 "%llu\n");
2099
2100 static int
2101 i915_cache_sharing_get(void *data, u64 *val)
2102 {
2103 struct drm_device *dev = data;
2104 drm_i915_private_t *dev_priv = dev->dev_private;
2105 u32 snpcr;
2106 int ret;
2107
2108 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2109 return -ENODEV;
2110
2111 ret = mutex_lock_interruptible(&dev->struct_mutex);
2112 if (ret)
2113 return ret;
2114
2115 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2116 mutex_unlock(&dev_priv->dev->struct_mutex);
2117
2118 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
2119
2120 return 0;
2121 }
2122
2123 static int
2124 i915_cache_sharing_set(void *data, u64 val)
2125 {
2126 struct drm_device *dev = data;
2127 struct drm_i915_private *dev_priv = dev->dev_private;
2128 u32 snpcr;
2129
2130 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2131 return -ENODEV;
2132
2133 if (val > 3)
2134 return -EINVAL;
2135
2136 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
2137
2138 /* Update the cache sharing policy here as well */
2139 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
2140 snpcr &= ~GEN6_MBC_SNPCR_MASK;
2141 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
2142 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
2143
2144 return 0;
2145 }
2146
2147 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
2148 i915_cache_sharing_get, i915_cache_sharing_set,
2149 "%llu\n");
2150
2151 /* As the drm_debugfs_init() routines are called before dev->dev_private is
2152 * allocated we need to hook into the minor for release. */
2153 static int
2154 drm_add_fake_info_node(struct drm_minor *minor,
2155 struct dentry *ent,
2156 const void *key)
2157 {
2158 struct drm_info_node *node;
2159
2160 node = kmalloc(sizeof(*node), GFP_KERNEL);
2161 if (node == NULL) {
2162 debugfs_remove(ent);
2163 return -ENOMEM;
2164 }
2165
2166 node->minor = minor;
2167 node->dent = ent;
2168 node->info_ent = (void *) key;
2169
2170 mutex_lock(&minor->debugfs_lock);
2171 list_add(&node->list, &minor->debugfs_list);
2172 mutex_unlock(&minor->debugfs_lock);
2173
2174 return 0;
2175 }
2176
2177 static int i915_forcewake_open(struct inode *inode, struct file *file)
2178 {
2179 struct drm_device *dev = inode->i_private;
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181
2182 if (INTEL_INFO(dev)->gen < 6)
2183 return 0;
2184
2185 gen6_gt_force_wake_get(dev_priv);
2186
2187 return 0;
2188 }
2189
2190 static int i915_forcewake_release(struct inode *inode, struct file *file)
2191 {
2192 struct drm_device *dev = inode->i_private;
2193 struct drm_i915_private *dev_priv = dev->dev_private;
2194
2195 if (INTEL_INFO(dev)->gen < 6)
2196 return 0;
2197
2198 gen6_gt_force_wake_put(dev_priv);
2199
2200 return 0;
2201 }
2202
2203 static const struct file_operations i915_forcewake_fops = {
2204 .owner = THIS_MODULE,
2205 .open = i915_forcewake_open,
2206 .release = i915_forcewake_release,
2207 };
2208
2209 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
2210 {
2211 struct drm_device *dev = minor->dev;
2212 struct dentry *ent;
2213
2214 ent = debugfs_create_file("i915_forcewake_user",
2215 S_IRUSR,
2216 root, dev,
2217 &i915_forcewake_fops);
2218 if (IS_ERR(ent))
2219 return PTR_ERR(ent);
2220
2221 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
2222 }
2223
2224 static int i915_debugfs_create(struct dentry *root,
2225 struct drm_minor *minor,
2226 const char *name,
2227 const struct file_operations *fops)
2228 {
2229 struct drm_device *dev = minor->dev;
2230 struct dentry *ent;
2231
2232 ent = debugfs_create_file(name,
2233 S_IRUGO | S_IWUSR,
2234 root, dev,
2235 fops);
2236 if (IS_ERR(ent))
2237 return PTR_ERR(ent);
2238
2239 return drm_add_fake_info_node(minor, ent, fops);
2240 }
2241
2242 static struct drm_info_list i915_debugfs_list[] = {
2243 {"i915_capabilities", i915_capabilities, 0},
2244 {"i915_gem_objects", i915_gem_object_info, 0},
2245 {"i915_gem_gtt", i915_gem_gtt_info, 0},
2246 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
2247 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
2248 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
2249 {"i915_gem_stolen", i915_gem_stolen_list_info },
2250 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2251 {"i915_gem_request", i915_gem_request_info, 0},
2252 {"i915_gem_seqno", i915_gem_seqno_info, 0},
2253 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2254 {"i915_gem_interrupt", i915_interrupt_info, 0},
2255 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2256 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2257 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
2258 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
2259 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2260 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2261 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2262 {"i915_inttoext_table", i915_inttoext_table, 0},
2263 {"i915_drpc_info", i915_drpc_info, 0},
2264 {"i915_emon_status", i915_emon_status, 0},
2265 {"i915_ring_freq_table", i915_ring_freq_table, 0},
2266 {"i915_gfxec", i915_gfxec, 0},
2267 {"i915_fbc_status", i915_fbc_status, 0},
2268 {"i915_ips_status", i915_ips_status, 0},
2269 {"i915_sr_status", i915_sr_status, 0},
2270 {"i915_opregion", i915_opregion, 0},
2271 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2272 {"i915_context_status", i915_context_status, 0},
2273 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
2274 {"i915_swizzle_info", i915_swizzle_info, 0},
2275 {"i915_ppgtt_info", i915_ppgtt_info, 0},
2276 {"i915_dpio", i915_dpio_info, 0},
2277 {"i915_llc", i915_llc, 0},
2278 {"i915_edp_psr_status", i915_edp_psr_status, 0},
2279 {"i915_energy_uJ", i915_energy_uJ, 0},
2280 {"i915_pc8_status", i915_pc8_status, 0},
2281 };
2282 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2283
2284 static struct i915_debugfs_files {
2285 const char *name;
2286 const struct file_operations *fops;
2287 } i915_debugfs_files[] = {
2288 {"i915_wedged", &i915_wedged_fops},
2289 {"i915_max_freq", &i915_max_freq_fops},
2290 {"i915_min_freq", &i915_min_freq_fops},
2291 {"i915_cache_sharing", &i915_cache_sharing_fops},
2292 {"i915_ring_stop", &i915_ring_stop_fops},
2293 {"i915_gem_drop_caches", &i915_drop_caches_fops},
2294 {"i915_error_state", &i915_error_state_fops},
2295 {"i915_next_seqno", &i915_next_seqno_fops},
2296 };
2297
2298 int i915_debugfs_init(struct drm_minor *minor)
2299 {
2300 int ret, i;
2301
2302 ret = i915_forcewake_create(minor->debugfs_root, minor);
2303 if (ret)
2304 return ret;
2305
2306 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2307 ret = i915_debugfs_create(minor->debugfs_root, minor,
2308 i915_debugfs_files[i].name,
2309 i915_debugfs_files[i].fops);
2310 if (ret)
2311 return ret;
2312 }
2313
2314 return drm_debugfs_create_files(i915_debugfs_list,
2315 I915_DEBUGFS_ENTRIES,
2316 minor->debugfs_root, minor);
2317 }
2318
2319 void i915_debugfs_cleanup(struct drm_minor *minor)
2320 {
2321 int i;
2322
2323 drm_debugfs_remove_files(i915_debugfs_list,
2324 I915_DEBUGFS_ENTRIES, minor);
2325 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2326 1, minor);
2327 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
2328 struct drm_info_list *info_list =
2329 (struct drm_info_list *) i915_debugfs_files[i].fops;
2330
2331 drm_debugfs_remove_files(info_list, 1, minor);
2332 }
2333 }
2334
2335 #endif /* CONFIG_DEBUG_FS */
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