1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/async.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_legacy.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
54 static int i915_getparam(struct drm_device
*dev
, void *data
,
55 struct drm_file
*file_priv
)
57 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
58 drm_i915_getparam_t
*param
= data
;
61 switch (param
->param
) {
62 case I915_PARAM_IRQ_ACTIVE
:
63 case I915_PARAM_ALLOW_BATCHBUFFER
:
64 case I915_PARAM_LAST_DISPATCH
:
65 /* Reject all old ums/dri params. */
67 case I915_PARAM_CHIPSET_ID
:
68 value
= dev
->pdev
->device
;
70 case I915_PARAM_HAS_GEM
:
73 case I915_PARAM_NUM_FENCES_AVAIL
:
74 value
= dev_priv
->num_fence_regs
- dev_priv
->fence_reg_start
;
76 case I915_PARAM_HAS_OVERLAY
:
77 value
= dev_priv
->overlay
? 1 : 0;
79 case I915_PARAM_HAS_PAGEFLIPPING
:
82 case I915_PARAM_HAS_EXECBUF2
:
86 case I915_PARAM_HAS_BSD
:
87 value
= intel_ring_initialized(&dev_priv
->ring
[VCS
]);
89 case I915_PARAM_HAS_BLT
:
90 value
= intel_ring_initialized(&dev_priv
->ring
[BCS
]);
92 case I915_PARAM_HAS_VEBOX
:
93 value
= intel_ring_initialized(&dev_priv
->ring
[VECS
]);
95 case I915_PARAM_HAS_RELAXED_FENCING
:
98 case I915_PARAM_HAS_COHERENT_RINGS
:
101 case I915_PARAM_HAS_EXEC_CONSTANTS
:
102 value
= INTEL_INFO(dev
)->gen
>= 4;
104 case I915_PARAM_HAS_RELAXED_DELTA
:
107 case I915_PARAM_HAS_GEN7_SOL_RESET
:
110 case I915_PARAM_HAS_LLC
:
111 value
= HAS_LLC(dev
);
113 case I915_PARAM_HAS_WT
:
116 case I915_PARAM_HAS_ALIASING_PPGTT
:
117 value
= USES_PPGTT(dev
);
119 case I915_PARAM_HAS_WAIT_TIMEOUT
:
122 case I915_PARAM_HAS_SEMAPHORES
:
123 value
= i915_semaphore_is_enabled(dev
);
125 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
128 case I915_PARAM_HAS_SECURE_BATCHES
:
129 value
= capable(CAP_SYS_ADMIN
);
131 case I915_PARAM_HAS_PINNED_BATCHES
:
134 case I915_PARAM_HAS_EXEC_NO_RELOC
:
137 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
140 case I915_PARAM_CMD_PARSER_VERSION
:
141 value
= i915_cmd_parser_get_version();
143 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
146 case I915_PARAM_MMAP_VERSION
:
150 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
154 if (copy_to_user(param
->value
, &value
, sizeof(int))) {
155 DRM_ERROR("copy_to_user failed\n");
162 static int i915_setparam(struct drm_device
*dev
, void *data
,
163 struct drm_file
*file_priv
)
165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
166 drm_i915_setparam_t
*param
= data
;
168 switch (param
->param
) {
169 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
170 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
171 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
172 /* Reject all old ums/dri params. */
175 case I915_SETPARAM_NUM_USED_FENCES
:
176 if (param
->value
> dev_priv
->num_fence_regs
||
179 /* Userspace can use first N regs */
180 dev_priv
->fence_reg_start
= param
->value
;
183 DRM_DEBUG_DRIVER("unknown parameter %d\n",
191 static int i915_get_bridge_dev(struct drm_device
*dev
)
193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
195 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
196 if (!dev_priv
->bridge_dev
) {
197 DRM_ERROR("bridge device not found\n");
203 #define MCHBAR_I915 0x44
204 #define MCHBAR_I965 0x48
205 #define MCHBAR_SIZE (4*4096)
207 #define DEVEN_REG 0x54
208 #define DEVEN_MCHBAR_EN (1 << 28)
210 /* Allocate space for the MCH regs if needed, return nonzero on error */
212 intel_alloc_mchbar_resource(struct drm_device
*dev
)
214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
215 int reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
216 u32 temp_lo
, temp_hi
= 0;
220 if (INTEL_INFO(dev
)->gen
>= 4)
221 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
222 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
223 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
225 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
228 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
232 /* Get some space for it */
233 dev_priv
->mch_res
.name
= "i915 MCHBAR";
234 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
235 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
237 MCHBAR_SIZE
, MCHBAR_SIZE
,
239 0, pcibios_align_resource
,
240 dev_priv
->bridge_dev
);
242 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
243 dev_priv
->mch_res
.start
= 0;
247 if (INTEL_INFO(dev
)->gen
>= 4)
248 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
249 upper_32_bits(dev_priv
->mch_res
.start
));
251 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
252 lower_32_bits(dev_priv
->mch_res
.start
));
256 /* Setup MCHBAR if possible, return true if we should disable it again */
258 intel_setup_mchbar(struct drm_device
*dev
)
260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
261 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
265 if (IS_VALLEYVIEW(dev
))
268 dev_priv
->mchbar_need_disable
= false;
270 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
271 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
272 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
274 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
278 /* If it's already enabled, don't have to do anything */
282 if (intel_alloc_mchbar_resource(dev
))
285 dev_priv
->mchbar_need_disable
= true;
287 /* Space is allocated or reserved, so enable it. */
288 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
289 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
,
290 temp
| DEVEN_MCHBAR_EN
);
292 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
293 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
298 intel_teardown_mchbar(struct drm_device
*dev
)
300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
301 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
304 if (dev_priv
->mchbar_need_disable
) {
305 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
306 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
307 temp
&= ~DEVEN_MCHBAR_EN
;
308 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, temp
);
310 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
312 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
);
316 if (dev_priv
->mch_res
.start
)
317 release_resource(&dev_priv
->mch_res
);
320 /* true = enable decode, false = disable decoder */
321 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
323 struct drm_device
*dev
= cookie
;
325 intel_modeset_vga_set_state(dev
, state
);
327 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
328 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
330 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
333 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
335 struct drm_device
*dev
= pci_get_drvdata(pdev
);
336 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
338 if (state
== VGA_SWITCHEROO_ON
) {
339 pr_info("switched on\n");
340 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
341 /* i915 resume handler doesn't set to D0 */
342 pci_set_power_state(dev
->pdev
, PCI_D0
);
343 i915_resume_legacy(dev
);
344 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
346 pr_err("switched off\n");
347 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
348 i915_suspend_legacy(dev
, pmm
);
349 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
353 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
355 struct drm_device
*dev
= pci_get_drvdata(pdev
);
358 * FIXME: open_count is protected by drm_global_mutex but that would lead to
359 * locking inversion with the driver load path. And the access here is
360 * completely racy anyway. So don't bother with locking for now.
362 return dev
->open_count
== 0;
365 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
366 .set_gpu_state
= i915_switcheroo_set_state
,
368 .can_switch
= i915_switcheroo_can_switch
,
371 static int i915_load_modeset_init(struct drm_device
*dev
)
373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
376 ret
= intel_parse_bios(dev
);
378 DRM_INFO("failed to find VBIOS tables\n");
380 /* If we have > 1 VGA cards, then we need to arbitrate access
381 * to the common VGA resources.
383 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
384 * then we do not take part in VGA arbitration and the
385 * vga_client_register() fails with -ENODEV.
387 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
388 if (ret
&& ret
!= -ENODEV
)
391 intel_register_dsm_handler();
393 ret
= vga_switcheroo_register_client(dev
->pdev
, &i915_switcheroo_ops
, false);
395 goto cleanup_vga_client
;
397 /* Initialise stolen first so that we may reserve preallocated
398 * objects for the BIOS to KMS transition.
400 ret
= i915_gem_init_stolen(dev
);
402 goto cleanup_vga_switcheroo
;
404 intel_power_domains_init_hw(dev_priv
);
406 ret
= intel_irq_install(dev_priv
);
408 goto cleanup_gem_stolen
;
410 /* Important: The output setup functions called by modeset_init need
411 * working irqs for e.g. gmbus and dp aux transfers. */
412 intel_modeset_init(dev
);
414 ret
= i915_gem_init(dev
);
418 intel_modeset_gem_init(dev
);
420 /* Always safe in the mode setting case. */
421 /* FIXME: do pre/post-mode set stuff in core KMS code */
422 dev
->vblank_disable_allowed
= true;
423 if (INTEL_INFO(dev
)->num_pipes
== 0)
426 ret
= intel_fbdev_init(dev
);
430 /* Only enable hotplug handling once the fbdev is fully set up. */
431 intel_hpd_init(dev_priv
);
434 * Some ports require correctly set-up hpd registers for detection to
435 * work properly (leading to ghost connected connector status), e.g. VGA
436 * on gm45. Hence we can only set up the initial fbdev config after hpd
437 * irqs are fully enabled. Now we should scan for the initial config
438 * only once hotplug handling is enabled, but due to screwed-up locking
439 * around kms/fbdev init we can't protect the fdbev initial config
440 * scanning against hotplug events. Hence do this first and ignore the
441 * tiny window where we will loose hotplug notifactions.
443 async_schedule(intel_fbdev_initial_config
, dev_priv
);
445 drm_kms_helper_poll_init(dev
);
450 mutex_lock(&dev
->struct_mutex
);
451 i915_gem_cleanup_ringbuffer(dev
);
452 i915_gem_context_fini(dev
);
453 mutex_unlock(&dev
->struct_mutex
);
455 drm_irq_uninstall(dev
);
457 i915_gem_cleanup_stolen(dev
);
458 cleanup_vga_switcheroo
:
459 vga_switcheroo_unregister_client(dev
->pdev
);
461 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
466 #if IS_ENABLED(CONFIG_FB)
467 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
469 struct apertures_struct
*ap
;
470 struct pci_dev
*pdev
= dev_priv
->dev
->pdev
;
474 ap
= alloc_apertures(1);
478 ap
->ranges
[0].base
= dev_priv
->gtt
.mappable_base
;
479 ap
->ranges
[0].size
= dev_priv
->gtt
.mappable_end
;
482 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
484 ret
= remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
491 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
497 #if !defined(CONFIG_VGA_CONSOLE)
498 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
502 #elif !defined(CONFIG_DUMMY_CONSOLE)
503 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
508 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
512 DRM_INFO("Replacing VGA console driver\n");
515 if (con_is_bound(&vga_con
))
516 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
518 ret
= do_unregister_con_driver(&vga_con
);
520 /* Ignore "already unregistered". */
530 static void i915_dump_device_info(struct drm_i915_private
*dev_priv
)
532 const struct intel_device_info
*info
= &dev_priv
->info
;
534 #define PRINT_S(name) "%s"
536 #define PRINT_FLAG(name) info->name ? #name "," : ""
538 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
539 DEV_INFO_FOR_EACH_FLAG(PRINT_S
, SEP_EMPTY
),
541 dev_priv
->dev
->pdev
->device
,
542 dev_priv
->dev
->pdev
->revision
,
543 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_COMMA
));
551 * Determine various intel_device_info fields at runtime.
553 * Use it when either:
554 * - it's judged too laborious to fill n static structures with the limit
555 * when a simple if statement does the job,
556 * - run-time checks (eg read fuse/strap registers) are needed.
558 * This function needs to be called:
559 * - after the MMIO has been setup as we are reading registers,
560 * - after the PCH has been detected,
561 * - before the first usage of the fields it can tweak.
563 static void intel_device_info_runtime_init(struct drm_device
*dev
)
565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
566 struct intel_device_info
*info
;
569 info
= (struct intel_device_info
*)&dev_priv
->info
;
571 if (IS_VALLEYVIEW(dev
) || INTEL_INFO(dev
)->gen
== 9)
572 for_each_pipe(dev_priv
, pipe
)
573 info
->num_sprites
[pipe
] = 2;
575 for_each_pipe(dev_priv
, pipe
)
576 info
->num_sprites
[pipe
] = 1;
578 if (i915
.disable_display
) {
579 DRM_INFO("Display disabled (module parameter)\n");
581 } else if (info
->num_pipes
> 0 &&
582 (INTEL_INFO(dev
)->gen
== 7 || INTEL_INFO(dev
)->gen
== 8) &&
583 !IS_VALLEYVIEW(dev
)) {
584 u32 fuse_strap
= I915_READ(FUSE_STRAP
);
585 u32 sfuse_strap
= I915_READ(SFUSE_STRAP
);
588 * SFUSE_STRAP is supposed to have a bit signalling the display
589 * is fused off. Unfortunately it seems that, at least in
590 * certain cases, fused off display means that PCH display
591 * reads don't land anywhere. In that case, we read 0s.
593 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
594 * should be set when taking over after the firmware.
596 if (fuse_strap
& ILK_INTERNAL_DISPLAY_DISABLE
||
597 sfuse_strap
& SFUSE_STRAP_DISPLAY_DISABLED
||
598 (dev_priv
->pch_type
== PCH_CPT
&&
599 !(sfuse_strap
& SFUSE_STRAP_FUSE_LOCK
))) {
600 DRM_INFO("Display fused off, disabling\n");
607 * i915_driver_load - setup chip and create an initial config
609 * @flags: startup flags
611 * The driver load routine has to do several things:
612 * - drive output discovery via intel_modeset_init()
613 * - initialize the memory manager
614 * - allocate initial config memory
615 * - setup the DRM framebuffer with the allocated memory
617 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
619 struct drm_i915_private
*dev_priv
;
620 struct intel_device_info
*info
, *device_info
;
621 int ret
= 0, mmio_bar
, mmio_size
;
622 uint32_t aperture_size
;
624 info
= (struct intel_device_info
*) flags
;
626 /* Refuse to load on gen6+ without kms enabled. */
627 if (info
->gen
>= 6 && !drm_core_check_feature(dev
, DRIVER_MODESET
)) {
628 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
629 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
633 /* UMS needs agp support. */
634 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) && !dev
->agp
)
637 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
638 if (dev_priv
== NULL
)
641 dev
->dev_private
= dev_priv
;
644 /* Setup the write-once "constant" device info */
645 device_info
= (struct intel_device_info
*)&dev_priv
->info
;
646 memcpy(device_info
, info
, sizeof(dev_priv
->info
));
647 device_info
->device_id
= dev
->pdev
->device
;
649 spin_lock_init(&dev_priv
->irq_lock
);
650 spin_lock_init(&dev_priv
->gpu_error
.lock
);
651 mutex_init(&dev_priv
->backlight_lock
);
652 spin_lock_init(&dev_priv
->uncore
.lock
);
653 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
654 spin_lock_init(&dev_priv
->mmio_flip_lock
);
655 mutex_init(&dev_priv
->dpio_lock
);
656 mutex_init(&dev_priv
->modeset_restore_lock
);
660 intel_display_crc_init(dev
);
662 i915_dump_device_info(dev_priv
);
664 /* Not all pre-production machines fall into this category, only the
665 * very first ones. Almost everything should work, except for maybe
666 * suspend/resume. And we don't implement workarounds that affect only
667 * pre-production machines. */
668 if (IS_HSW_EARLY_SDV(dev
))
669 DRM_INFO("This is an early pre-production Haswell machine. "
670 "It may not be fully functional.\n");
672 if (i915_get_bridge_dev(dev
)) {
677 mmio_bar
= IS_GEN2(dev
) ? 1 : 0;
678 /* Before gen4, the registers and the GTT are behind different BARs.
679 * However, from gen4 onwards, the registers and the GTT are shared
680 * in the same BAR, so we want to restrict this ioremap from
681 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
682 * the register BAR remains the same size for all the earlier
683 * generations up to Ironlake.
686 mmio_size
= 512*1024;
688 mmio_size
= 2*1024*1024;
690 dev_priv
->regs
= pci_iomap(dev
->pdev
, mmio_bar
, mmio_size
);
691 if (!dev_priv
->regs
) {
692 DRM_ERROR("failed to map registers\n");
697 /* This must be called before any calls to HAS_PCH_* */
698 intel_detect_pch(dev
);
700 intel_uncore_init(dev
);
702 ret
= i915_gem_gtt_init(dev
);
706 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
707 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
708 * otherwise the vga fbdev driver falls over. */
709 ret
= i915_kick_out_firmware_fb(dev_priv
);
711 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
715 ret
= i915_kick_out_vgacon(dev_priv
);
717 DRM_ERROR("failed to remove conflicting VGA console\n");
722 pci_set_master(dev
->pdev
);
724 /* overlay on gen2 is broken and can't address above 1G */
726 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(30));
728 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
729 * using 32bit addressing, overwriting memory if HWS is located
732 * The documentation also mentions an issue with undefined
733 * behaviour if any general state is accessed within a page above 4GB,
734 * which also needs to be handled carefully.
736 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
737 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(32));
739 aperture_size
= dev_priv
->gtt
.mappable_end
;
741 dev_priv
->gtt
.mappable
=
742 io_mapping_create_wc(dev_priv
->gtt
.mappable_base
,
744 if (dev_priv
->gtt
.mappable
== NULL
) {
749 dev_priv
->gtt
.mtrr
= arch_phys_wc_add(dev_priv
->gtt
.mappable_base
,
752 /* The i915 workqueue is primarily used for batched retirement of
753 * requests (and thus managing bo) once the task has been completed
754 * by the GPU. i915_gem_retire_requests() is called directly when we
755 * need high-priority retirement, such as waiting for an explicit
758 * It is also used for periodic low-priority events, such as
759 * idle-timers and recording error state.
761 * All tasks on the workqueue are expected to acquire the dev mutex
762 * so there is no point in running more than one instance of the
763 * workqueue at any time. Use an ordered one.
765 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
766 if (dev_priv
->wq
== NULL
) {
767 DRM_ERROR("Failed to create our workqueue.\n");
772 dev_priv
->dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
773 if (dev_priv
->dp_wq
== NULL
) {
774 DRM_ERROR("Failed to create our dp workqueue.\n");
779 intel_irq_init(dev_priv
);
780 intel_uncore_sanitize(dev
);
782 /* Try to make sure MCHBAR is enabled before poking at it */
783 intel_setup_mchbar(dev
);
784 intel_setup_gmbus(dev
);
785 intel_opregion_setup(dev
);
787 intel_setup_bios(dev
);
791 /* On the 945G/GM, the chipset reports the MSI capability on the
792 * integrated graphics even though the support isn't actually there
793 * according to the published specs. It doesn't appear to function
794 * correctly in testing on 945G.
795 * This may be a side effect of MSI having been made available for PEG
796 * and the registers being closely associated.
798 * According to chipset errata, on the 965GM, MSI interrupts may
799 * be lost or delayed, but we use them anyways to avoid
800 * stuck interrupts on some machines.
802 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
803 pci_enable_msi(dev
->pdev
);
805 intel_device_info_runtime_init(dev
);
807 if (INTEL_INFO(dev
)->num_pipes
) {
808 ret
= drm_vblank_init(dev
, INTEL_INFO(dev
)->num_pipes
);
813 intel_power_domains_init(dev_priv
);
815 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
816 ret
= i915_load_modeset_init(dev
);
818 DRM_ERROR("failed to init modeset\n");
823 i915_setup_sysfs(dev
);
825 if (INTEL_INFO(dev
)->num_pipes
) {
826 /* Must be done after probing outputs */
827 intel_opregion_init(dev
);
828 acpi_video_register();
832 intel_gpu_ips_init(dev_priv
);
834 intel_runtime_pm_enable(dev_priv
);
836 i915_audio_component_init(dev_priv
);
841 intel_power_domains_fini(dev_priv
);
842 drm_vblank_cleanup(dev
);
844 WARN_ON(unregister_oom_notifier(&dev_priv
->mm
.oom_notifier
));
845 unregister_shrinker(&dev_priv
->mm
.shrinker
);
847 if (dev
->pdev
->msi_enabled
)
848 pci_disable_msi(dev
->pdev
);
850 intel_teardown_gmbus(dev
);
851 intel_teardown_mchbar(dev
);
852 pm_qos_remove_request(&dev_priv
->pm_qos
);
853 destroy_workqueue(dev_priv
->dp_wq
);
855 destroy_workqueue(dev_priv
->wq
);
857 arch_phys_wc_del(dev_priv
->gtt
.mtrr
);
858 io_mapping_free(dev_priv
->gtt
.mappable
);
860 i915_global_gtt_cleanup(dev
);
862 intel_uncore_fini(dev
);
863 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
865 pci_dev_put(dev_priv
->bridge_dev
);
868 kmem_cache_destroy(dev_priv
->slab
);
873 int i915_driver_unload(struct drm_device
*dev
)
875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
878 i915_audio_component_cleanup(dev_priv
);
880 ret
= i915_gem_suspend(dev
);
882 DRM_ERROR("failed to idle hardware: %d\n", ret
);
886 intel_power_domains_fini(dev_priv
);
888 intel_gpu_ips_teardown();
890 i915_teardown_sysfs(dev
);
892 WARN_ON(unregister_oom_notifier(&dev_priv
->mm
.oom_notifier
));
893 unregister_shrinker(&dev_priv
->mm
.shrinker
);
895 io_mapping_free(dev_priv
->gtt
.mappable
);
896 arch_phys_wc_del(dev_priv
->gtt
.mtrr
);
898 acpi_video_unregister();
900 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
901 intel_fbdev_fini(dev
);
903 drm_vblank_cleanup(dev
);
905 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
906 intel_modeset_cleanup(dev
);
909 * free the memory space allocated for the child device
910 * config parsed from VBT
912 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
913 kfree(dev_priv
->vbt
.child_dev
);
914 dev_priv
->vbt
.child_dev
= NULL
;
915 dev_priv
->vbt
.child_dev_num
= 0;
918 vga_switcheroo_unregister_client(dev
->pdev
);
919 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
922 /* Free error state after interrupts are fully disabled. */
923 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
924 cancel_work_sync(&dev_priv
->gpu_error
.work
);
925 i915_destroy_error_state(dev
);
927 if (dev
->pdev
->msi_enabled
)
928 pci_disable_msi(dev
->pdev
);
930 intel_opregion_fini(dev
);
932 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
933 /* Flush any outstanding unpin_work. */
934 flush_workqueue(dev_priv
->wq
);
936 mutex_lock(&dev
->struct_mutex
);
937 i915_gem_cleanup_ringbuffer(dev
);
938 i915_gem_batch_pool_fini(&dev_priv
->mm
.batch_pool
);
939 i915_gem_context_fini(dev
);
940 mutex_unlock(&dev
->struct_mutex
);
941 i915_gem_cleanup_stolen(dev
);
944 intel_teardown_gmbus(dev
);
945 intel_teardown_mchbar(dev
);
947 destroy_workqueue(dev_priv
->dp_wq
);
948 destroy_workqueue(dev_priv
->wq
);
949 pm_qos_remove_request(&dev_priv
->pm_qos
);
951 i915_global_gtt_cleanup(dev
);
953 intel_uncore_fini(dev
);
954 if (dev_priv
->regs
!= NULL
)
955 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
958 kmem_cache_destroy(dev_priv
->slab
);
960 pci_dev_put(dev_priv
->bridge_dev
);
966 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
970 ret
= i915_gem_open(dev
, file
);
978 * i915_driver_lastclose - clean up after all DRM clients have exited
981 * Take care of cleaning up after all DRM clients have exited. In the
982 * mode setting case, we want to restore the kernel's initial mode (just
983 * in case the last client left us in a bad state).
985 * Additionally, in the non-mode setting case, we'll tear down the GTT
986 * and DMA structures, since the kernel won't be using them, and clea
989 void i915_driver_lastclose(struct drm_device
*dev
)
991 intel_fbdev_restore_mode(dev
);
992 vga_switcheroo_process_delayed_switch();
995 void i915_driver_preclose(struct drm_device
*dev
, struct drm_file
*file
)
997 mutex_lock(&dev
->struct_mutex
);
998 i915_gem_context_close(dev
, file
);
999 i915_gem_release(dev
, file
);
1000 mutex_unlock(&dev
->struct_mutex
);
1002 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
1003 intel_modeset_preclose(dev
, file
);
1006 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1008 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1010 if (file_priv
&& file_priv
->bsd_ring
)
1011 file_priv
->bsd_ring
= NULL
;
1016 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
1017 struct drm_file
*file
)
1022 const struct drm_ioctl_desc i915_ioctls
[] = {
1023 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1024 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
1025 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
1026 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
1027 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
1028 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
1029 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
1030 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1031 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
1032 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
1033 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1034 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
1035 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1036 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1037 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
1038 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
1039 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1040 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1041 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
|DRM_UNLOCKED
),
1042 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1043 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1044 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1045 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1046 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1047 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1048 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1049 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1050 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1051 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1052 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1053 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1054 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1055 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1056 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1057 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1058 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1059 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1060 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1061 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, DRM_UNLOCKED
),
1062 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1063 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1064 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1065 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1066 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, intel_sprite_get_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1067 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1068 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1069 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1070 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1071 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_get_reset_stats_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1072 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1073 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1074 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1077 int i915_max_ioctl
= ARRAY_SIZE(i915_ioctls
);
1080 * This is really ugly: Because old userspace abused the linux agp interface to
1081 * manage the gtt, we need to claim that all intel devices are agp. For
1082 * otherwise the drm core refuses to initialize the agp support code.
1084 int i915_driver_device_is_agp(struct drm_device
*dev
)