1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "drm_crtc_helper.h"
32 #include "intel_drv.h"
36 /* Really want an OS-independent resettable timer. Would like to have
37 * this loop run for (eg) 3 sec, but have the timer reset every time
38 * the head pointer changes, so that EBUSY only happens if the ring
39 * actually stalls for (eg) 3 seconds.
41 int i915_wait_ring(struct drm_device
* dev
, int n
, const char *caller
)
43 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
44 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
45 drm_i915_ring_buffer_t
*ring
= &(dev_priv
->ring
);
46 u32 acthd_reg
= IS_I965G(dev
) ? ACTHD_I965
: ACTHD
;
47 u32 last_acthd
= I915_READ(acthd_reg
);
49 u32 last_head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
52 for (i
= 0; i
< 100000; i
++) {
53 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
54 acthd
= I915_READ(acthd_reg
);
55 ring
->space
= ring
->head
- (ring
->tail
+ 8);
57 ring
->space
+= ring
->Size
;
61 if (master_priv
->sarea_priv
)
62 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
64 if (ring
->head
!= last_head
)
66 if (acthd
!= last_acthd
)
69 last_head
= ring
->head
;
71 msleep_interruptible(10);
79 * Sets up the hardware status page for devices that need a physical address
82 static int i915_init_phys_hws(struct drm_device
*dev
)
84 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
85 /* Program Hardware Status Page */
86 dev_priv
->status_page_dmah
=
87 drm_pci_alloc(dev
, PAGE_SIZE
, PAGE_SIZE
, 0xffffffff);
89 if (!dev_priv
->status_page_dmah
) {
90 DRM_ERROR("Can not allocate hardware status page\n");
93 dev_priv
->hw_status_page
= dev_priv
->status_page_dmah
->vaddr
;
94 dev_priv
->dma_status_page
= dev_priv
->status_page_dmah
->busaddr
;
96 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
98 I915_WRITE(HWS_PGA
, dev_priv
->dma_status_page
);
99 DRM_DEBUG("Enabled hardware status page\n");
104 * Frees the hardware status page, whether it's a physical address or a virtual
105 * address set up by the X Server.
107 static void i915_free_hws(struct drm_device
*dev
)
109 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
110 if (dev_priv
->status_page_dmah
) {
111 drm_pci_free(dev
, dev_priv
->status_page_dmah
);
112 dev_priv
->status_page_dmah
= NULL
;
115 if (dev_priv
->status_gfx_addr
) {
116 dev_priv
->status_gfx_addr
= 0;
117 drm_core_ioremapfree(&dev_priv
->hws_map
, dev
);
120 /* Need to rewrite hardware status page */
121 I915_WRITE(HWS_PGA
, 0x1ffff000);
124 void i915_kernel_lost_context(struct drm_device
* dev
)
126 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
127 struct drm_i915_master_private
*master_priv
;
128 drm_i915_ring_buffer_t
*ring
= &(dev_priv
->ring
);
131 * We should never lose context on the ring with modesetting
132 * as we don't expose it to userspace
134 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
137 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
138 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
139 ring
->space
= ring
->head
- (ring
->tail
+ 8);
141 ring
->space
+= ring
->Size
;
143 if (!dev
->primary
->master
)
146 master_priv
= dev
->primary
->master
->driver_priv
;
147 if (ring
->head
== ring
->tail
&& master_priv
->sarea_priv
)
148 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_RING_EMPTY
;
151 static int i915_dma_cleanup(struct drm_device
* dev
)
153 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
154 /* Make sure interrupts are disabled here because the uninstall ioctl
155 * may not have been called from userspace and after dev_private
156 * is freed, it's too late.
158 if (dev
->irq_enabled
)
159 drm_irq_uninstall(dev
);
161 if (dev_priv
->ring
.virtual_start
) {
162 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
163 dev_priv
->ring
.virtual_start
= NULL
;
164 dev_priv
->ring
.map
.handle
= NULL
;
165 dev_priv
->ring
.map
.size
= 0;
168 /* Clear the HWS virtual address at teardown */
169 if (I915_NEED_GFX_HWS(dev
))
175 static int i915_initialize(struct drm_device
* dev
, drm_i915_init_t
* init
)
177 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
178 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
180 master_priv
->sarea
= drm_getsarea(dev
);
181 if (master_priv
->sarea
) {
182 master_priv
->sarea_priv
= (drm_i915_sarea_t
*)
183 ((u8
*)master_priv
->sarea
->handle
+ init
->sarea_priv_offset
);
185 DRM_DEBUG("sarea not found assuming DRI2 userspace\n");
188 if (init
->ring_size
!= 0) {
189 if (dev_priv
->ring
.ring_obj
!= NULL
) {
190 i915_dma_cleanup(dev
);
191 DRM_ERROR("Client tried to initialize ringbuffer in "
196 dev_priv
->ring
.Size
= init
->ring_size
;
197 dev_priv
->ring
.tail_mask
= dev_priv
->ring
.Size
- 1;
199 dev_priv
->ring
.map
.offset
= init
->ring_start
;
200 dev_priv
->ring
.map
.size
= init
->ring_size
;
201 dev_priv
->ring
.map
.type
= 0;
202 dev_priv
->ring
.map
.flags
= 0;
203 dev_priv
->ring
.map
.mtrr
= 0;
205 drm_core_ioremap_wc(&dev_priv
->ring
.map
, dev
);
207 if (dev_priv
->ring
.map
.handle
== NULL
) {
208 i915_dma_cleanup(dev
);
209 DRM_ERROR("can not ioremap virtual address for"
215 dev_priv
->ring
.virtual_start
= dev_priv
->ring
.map
.handle
;
217 dev_priv
->cpp
= init
->cpp
;
218 dev_priv
->back_offset
= init
->back_offset
;
219 dev_priv
->front_offset
= init
->front_offset
;
220 dev_priv
->current_page
= 0;
221 if (master_priv
->sarea_priv
)
222 master_priv
->sarea_priv
->pf_current_page
= 0;
224 /* Allow hardware batchbuffers unless told otherwise.
226 dev_priv
->allow_batchbuffer
= 1;
231 static int i915_dma_resume(struct drm_device
* dev
)
233 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
235 DRM_DEBUG("%s\n", __func__
);
237 if (dev_priv
->ring
.map
.handle
== NULL
) {
238 DRM_ERROR("can not ioremap virtual address for"
243 /* Program Hardware Status Page */
244 if (!dev_priv
->hw_status_page
) {
245 DRM_ERROR("Can not find hardware status page\n");
248 DRM_DEBUG("hw status page @ %p\n", dev_priv
->hw_status_page
);
250 if (dev_priv
->status_gfx_addr
!= 0)
251 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
253 I915_WRITE(HWS_PGA
, dev_priv
->dma_status_page
);
254 DRM_DEBUG("Enabled hardware status page\n");
259 static int i915_dma_init(struct drm_device
*dev
, void *data
,
260 struct drm_file
*file_priv
)
262 drm_i915_init_t
*init
= data
;
265 switch (init
->func
) {
267 retcode
= i915_initialize(dev
, init
);
269 case I915_CLEANUP_DMA
:
270 retcode
= i915_dma_cleanup(dev
);
272 case I915_RESUME_DMA
:
273 retcode
= i915_dma_resume(dev
);
283 /* Implement basically the same security restrictions as hardware does
284 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
286 * Most of the calculations below involve calculating the size of a
287 * particular instruction. It's important to get the size right as
288 * that tells us where the next instruction to check is. Any illegal
289 * instruction detected will be given a size of zero, which is a
290 * signal to abort the rest of the buffer.
292 static int do_validate_cmd(int cmd
)
294 switch (((cmd
>> 29) & 0x7)) {
296 switch ((cmd
>> 23) & 0x3f) {
298 return 1; /* MI_NOOP */
300 return 1; /* MI_FLUSH */
302 return 0; /* disallow everything else */
306 return 0; /* reserved */
308 return (cmd
& 0xff) + 2; /* 2d commands */
310 if (((cmd
>> 24) & 0x1f) <= 0x18)
313 switch ((cmd
>> 24) & 0x1f) {
317 switch ((cmd
>> 16) & 0xff) {
319 return (cmd
& 0x1f) + 2;
321 return (cmd
& 0xf) + 2;
323 return (cmd
& 0xffff) + 2;
327 return (cmd
& 0xffff) + 1;
331 if ((cmd
& (1 << 23)) == 0) /* inline vertices */
332 return (cmd
& 0x1ffff) + 2;
333 else if (cmd
& (1 << 17)) /* indirect random */
334 if ((cmd
& 0xffff) == 0)
335 return 0; /* unknown length, too hard */
337 return (((cmd
& 0xffff) + 1) / 2) + 1;
339 return 2; /* indirect sequential */
350 static int validate_cmd(int cmd
)
352 int ret
= do_validate_cmd(cmd
);
354 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
359 static int i915_emit_cmds(struct drm_device
* dev
, int __user
* buffer
, int dwords
)
361 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
365 if ((dwords
+1) * sizeof(int) >= dev_priv
->ring
.Size
- 8)
368 BEGIN_LP_RING((dwords
+1)&~1);
370 for (i
= 0; i
< dwords
;) {
373 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd
, &buffer
[i
], sizeof(cmd
)))
376 if ((sz
= validate_cmd(cmd
)) == 0 || i
+ sz
> dwords
)
382 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd
, &buffer
[i
],
399 i915_emit_box(struct drm_device
*dev
,
400 struct drm_clip_rect __user
*boxes
,
401 int i
, int DR1
, int DR4
)
403 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
404 struct drm_clip_rect box
;
407 if (DRM_COPY_FROM_USER_UNCHECKED(&box
, &boxes
[i
], sizeof(box
))) {
411 if (box
.y2
<= box
.y1
|| box
.x2
<= box
.x1
|| box
.y2
<= 0 || box
.x2
<= 0) {
412 DRM_ERROR("Bad box %d,%d..%d,%d\n",
413 box
.x1
, box
.y1
, box
.x2
, box
.y2
);
419 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
420 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
421 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
426 OUT_RING(GFX_OP_DRAWRECT_INFO
);
428 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
429 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
438 /* XXX: Emitting the counter should really be moved to part of the IRQ
439 * emit. For now, do it in both places:
442 static void i915_emit_breadcrumb(struct drm_device
*dev
)
444 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
445 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
449 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
450 dev_priv
->counter
= 0;
451 if (master_priv
->sarea_priv
)
452 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
455 OUT_RING(MI_STORE_DWORD_INDEX
);
456 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
457 OUT_RING(dev_priv
->counter
);
462 static int i915_dispatch_cmdbuffer(struct drm_device
* dev
,
463 drm_i915_cmdbuffer_t
* cmd
)
465 int nbox
= cmd
->num_cliprects
;
466 int i
= 0, count
, ret
;
469 DRM_ERROR("alignment");
473 i915_kernel_lost_context(dev
);
475 count
= nbox
? nbox
: 1;
477 for (i
= 0; i
< count
; i
++) {
479 ret
= i915_emit_box(dev
, cmd
->cliprects
, i
,
485 ret
= i915_emit_cmds(dev
, (int __user
*)cmd
->buf
, cmd
->sz
/ 4);
490 i915_emit_breadcrumb(dev
);
494 static int i915_dispatch_batchbuffer(struct drm_device
* dev
,
495 drm_i915_batchbuffer_t
* batch
)
497 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
498 struct drm_clip_rect __user
*boxes
= batch
->cliprects
;
499 int nbox
= batch
->num_cliprects
;
503 if ((batch
->start
| batch
->used
) & 0x7) {
504 DRM_ERROR("alignment");
508 i915_kernel_lost_context(dev
);
510 count
= nbox
? nbox
: 1;
512 for (i
= 0; i
< count
; i
++) {
514 int ret
= i915_emit_box(dev
, boxes
, i
,
515 batch
->DR1
, batch
->DR4
);
520 if (!IS_I830(dev
) && !IS_845G(dev
)) {
523 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6) | MI_BATCH_NON_SECURE_I965
);
524 OUT_RING(batch
->start
);
526 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
527 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
532 OUT_RING(MI_BATCH_BUFFER
);
533 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
534 OUT_RING(batch
->start
+ batch
->used
- 4);
540 i915_emit_breadcrumb(dev
);
545 static int i915_dispatch_flip(struct drm_device
* dev
)
547 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
548 struct drm_i915_master_private
*master_priv
=
549 dev
->primary
->master
->driver_priv
;
552 if (!master_priv
->sarea_priv
)
555 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
557 dev_priv
->current_page
,
558 master_priv
->sarea_priv
->pf_current_page
);
560 i915_kernel_lost_context(dev
);
563 OUT_RING(MI_FLUSH
| MI_READ_FLUSH
);
568 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
570 if (dev_priv
->current_page
== 0) {
571 OUT_RING(dev_priv
->back_offset
);
572 dev_priv
->current_page
= 1;
574 OUT_RING(dev_priv
->front_offset
);
575 dev_priv
->current_page
= 0;
581 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
585 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
++;
588 OUT_RING(MI_STORE_DWORD_INDEX
);
589 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
590 OUT_RING(dev_priv
->counter
);
594 master_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
598 static int i915_quiescent(struct drm_device
* dev
)
600 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
602 i915_kernel_lost_context(dev
);
603 return i915_wait_ring(dev
, dev_priv
->ring
.Size
- 8, __func__
);
606 static int i915_flush_ioctl(struct drm_device
*dev
, void *data
,
607 struct drm_file
*file_priv
)
611 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
613 mutex_lock(&dev
->struct_mutex
);
614 ret
= i915_quiescent(dev
);
615 mutex_unlock(&dev
->struct_mutex
);
620 static int i915_batchbuffer(struct drm_device
*dev
, void *data
,
621 struct drm_file
*file_priv
)
623 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
624 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
625 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
626 master_priv
->sarea_priv
;
627 drm_i915_batchbuffer_t
*batch
= data
;
630 if (!dev_priv
->allow_batchbuffer
) {
631 DRM_ERROR("Batchbuffer ioctl disabled\n");
635 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
636 batch
->start
, batch
->used
, batch
->num_cliprects
);
638 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
640 if (batch
->num_cliprects
&& DRM_VERIFYAREA_READ(batch
->cliprects
,
641 batch
->num_cliprects
*
642 sizeof(struct drm_clip_rect
)))
645 mutex_lock(&dev
->struct_mutex
);
646 ret
= i915_dispatch_batchbuffer(dev
, batch
);
647 mutex_unlock(&dev
->struct_mutex
);
650 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
654 static int i915_cmdbuffer(struct drm_device
*dev
, void *data
,
655 struct drm_file
*file_priv
)
657 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
658 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
659 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
660 master_priv
->sarea_priv
;
661 drm_i915_cmdbuffer_t
*cmdbuf
= data
;
664 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
665 cmdbuf
->buf
, cmdbuf
->sz
, cmdbuf
->num_cliprects
);
667 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
669 if (cmdbuf
->num_cliprects
&&
670 DRM_VERIFYAREA_READ(cmdbuf
->cliprects
,
671 cmdbuf
->num_cliprects
*
672 sizeof(struct drm_clip_rect
))) {
673 DRM_ERROR("Fault accessing cliprects\n");
677 mutex_lock(&dev
->struct_mutex
);
678 ret
= i915_dispatch_cmdbuffer(dev
, cmdbuf
);
679 mutex_unlock(&dev
->struct_mutex
);
681 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
686 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
690 static int i915_flip_bufs(struct drm_device
*dev
, void *data
,
691 struct drm_file
*file_priv
)
695 DRM_DEBUG("%s\n", __func__
);
697 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
699 mutex_lock(&dev
->struct_mutex
);
700 ret
= i915_dispatch_flip(dev
);
701 mutex_unlock(&dev
->struct_mutex
);
706 static int i915_getparam(struct drm_device
*dev
, void *data
,
707 struct drm_file
*file_priv
)
709 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
710 drm_i915_getparam_t
*param
= data
;
714 DRM_ERROR("called with no initialization\n");
718 switch (param
->param
) {
719 case I915_PARAM_IRQ_ACTIVE
:
720 value
= dev
->pdev
->irq
? 1 : 0;
722 case I915_PARAM_ALLOW_BATCHBUFFER
:
723 value
= dev_priv
->allow_batchbuffer
? 1 : 0;
725 case I915_PARAM_LAST_DISPATCH
:
726 value
= READ_BREADCRUMB(dev_priv
);
728 case I915_PARAM_CHIPSET_ID
:
729 value
= dev
->pci_device
;
731 case I915_PARAM_HAS_GEM
:
732 value
= dev_priv
->has_gem
;
734 case I915_PARAM_NUM_FENCES_AVAIL
:
735 value
= dev_priv
->num_fence_regs
- dev_priv
->fence_reg_start
;
738 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
742 if (DRM_COPY_TO_USER(param
->value
, &value
, sizeof(int))) {
743 DRM_ERROR("DRM_COPY_TO_USER failed\n");
750 static int i915_setparam(struct drm_device
*dev
, void *data
,
751 struct drm_file
*file_priv
)
753 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
754 drm_i915_setparam_t
*param
= data
;
757 DRM_ERROR("called with no initialization\n");
761 switch (param
->param
) {
762 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
764 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
765 dev_priv
->tex_lru_log_granularity
= param
->value
;
767 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
768 dev_priv
->allow_batchbuffer
= param
->value
;
770 case I915_SETPARAM_NUM_USED_FENCES
:
771 if (param
->value
> dev_priv
->num_fence_regs
||
774 /* Userspace can use first N regs */
775 dev_priv
->fence_reg_start
= param
->value
;
778 DRM_DEBUG("unknown parameter %d\n", param
->param
);
785 static int i915_set_status_page(struct drm_device
*dev
, void *data
,
786 struct drm_file
*file_priv
)
788 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
789 drm_i915_hws_addr_t
*hws
= data
;
791 if (!I915_NEED_GFX_HWS(dev
))
795 DRM_ERROR("called with no initialization\n");
799 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
800 WARN(1, "tried to set status page when mode setting active\n");
804 printk(KERN_DEBUG
"set status page addr 0x%08x\n", (u32
)hws
->addr
);
806 dev_priv
->status_gfx_addr
= hws
->addr
& (0x1ffff<<12);
808 dev_priv
->hws_map
.offset
= dev
->agp
->base
+ hws
->addr
;
809 dev_priv
->hws_map
.size
= 4*1024;
810 dev_priv
->hws_map
.type
= 0;
811 dev_priv
->hws_map
.flags
= 0;
812 dev_priv
->hws_map
.mtrr
= 0;
814 drm_core_ioremap_wc(&dev_priv
->hws_map
, dev
);
815 if (dev_priv
->hws_map
.handle
== NULL
) {
816 i915_dma_cleanup(dev
);
817 dev_priv
->status_gfx_addr
= 0;
818 DRM_ERROR("can not ioremap virtual address for"
819 " G33 hw status page\n");
822 dev_priv
->hw_status_page
= dev_priv
->hws_map
.handle
;
824 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
825 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
826 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
827 dev_priv
->status_gfx_addr
);
828 DRM_DEBUG("load hws at %p\n", dev_priv
->hw_status_page
);
833 * i915_probe_agp - get AGP bootup configuration
835 * @aperture_size: returns AGP aperture configured size
836 * @preallocated_size: returns size of BIOS preallocated AGP space
838 * Since Intel integrated graphics are UMA, the BIOS has to set aside
839 * some RAM for the framebuffer at early boot. This code figures out
840 * how much was set aside so we can use it for our own purposes.
842 static int i915_probe_agp(struct drm_device
*dev
, unsigned long *aperture_size
,
843 unsigned long *preallocated_size
)
845 struct pci_dev
*bridge_dev
;
847 unsigned long overhead
;
848 unsigned long stolen
;
850 bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
852 DRM_ERROR("bridge device not found\n");
856 /* Get the fb aperture size and "stolen" memory amount. */
857 pci_read_config_word(bridge_dev
, INTEL_GMCH_CTRL
, &tmp
);
858 pci_dev_put(bridge_dev
);
860 *aperture_size
= 1024 * 1024;
861 *preallocated_size
= 1024 * 1024;
863 switch (dev
->pdev
->device
) {
864 case PCI_DEVICE_ID_INTEL_82830_CGC
:
865 case PCI_DEVICE_ID_INTEL_82845G_IG
:
866 case PCI_DEVICE_ID_INTEL_82855GM_IG
:
867 case PCI_DEVICE_ID_INTEL_82865_IG
:
868 if ((tmp
& INTEL_GMCH_MEM_MASK
) == INTEL_GMCH_MEM_64M
)
869 *aperture_size
*= 64;
871 *aperture_size
*= 128;
874 /* 9xx supports large sizes, just look at the length */
875 *aperture_size
= pci_resource_len(dev
->pdev
, 2);
880 * Some of the preallocated space is taken by the GTT
881 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
886 overhead
= (*aperture_size
/ 1024) + 4096;
888 switch (tmp
& INTEL_GMCH_GMS_MASK
) {
889 case INTEL_855_GMCH_GMS_DISABLED
:
890 DRM_ERROR("video memory is disabled\n");
892 case INTEL_855_GMCH_GMS_STOLEN_1M
:
893 stolen
= 1 * 1024 * 1024;
895 case INTEL_855_GMCH_GMS_STOLEN_4M
:
896 stolen
= 4 * 1024 * 1024;
898 case INTEL_855_GMCH_GMS_STOLEN_8M
:
899 stolen
= 8 * 1024 * 1024;
901 case INTEL_855_GMCH_GMS_STOLEN_16M
:
902 stolen
= 16 * 1024 * 1024;
904 case INTEL_855_GMCH_GMS_STOLEN_32M
:
905 stolen
= 32 * 1024 * 1024;
907 case INTEL_915G_GMCH_GMS_STOLEN_48M
:
908 stolen
= 48 * 1024 * 1024;
910 case INTEL_915G_GMCH_GMS_STOLEN_64M
:
911 stolen
= 64 * 1024 * 1024;
913 case INTEL_GMCH_GMS_STOLEN_128M
:
914 stolen
= 128 * 1024 * 1024;
916 case INTEL_GMCH_GMS_STOLEN_256M
:
917 stolen
= 256 * 1024 * 1024;
919 case INTEL_GMCH_GMS_STOLEN_96M
:
920 stolen
= 96 * 1024 * 1024;
922 case INTEL_GMCH_GMS_STOLEN_160M
:
923 stolen
= 160 * 1024 * 1024;
925 case INTEL_GMCH_GMS_STOLEN_224M
:
926 stolen
= 224 * 1024 * 1024;
928 case INTEL_GMCH_GMS_STOLEN_352M
:
929 stolen
= 352 * 1024 * 1024;
932 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
933 tmp
& INTEL_GMCH_GMS_MASK
);
936 *preallocated_size
= stolen
- overhead
;
941 static int i915_load_modeset_init(struct drm_device
*dev
)
943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
944 unsigned long agp_size
, prealloc_size
;
945 int fb_bar
= IS_I9XX(dev
) ? 2 : 0;
948 dev
->devname
= kstrdup(DRIVER_NAME
, GFP_KERNEL
);
954 dev
->mode_config
.fb_base
= drm_get_resource_start(dev
, fb_bar
) &
957 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
958 dev_priv
->cursor_needs_physical
= true;
960 dev_priv
->cursor_needs_physical
= false;
962 if (IS_I965G(dev
) || IS_G33(dev
))
963 dev_priv
->cursor_needs_physical
= false;
965 ret
= i915_probe_agp(dev
, &agp_size
, &prealloc_size
);
969 /* Basic memrange allocator for stolen space (aka vram) */
970 drm_mm_init(&dev_priv
->vram
, 0, prealloc_size
);
972 /* Let GEM Manage from end of prealloc space to end of aperture */
973 i915_gem_do_init(dev
, prealloc_size
, agp_size
);
975 ret
= i915_gem_init_ringbuffer(dev
);
979 /* Allow hardware batchbuffers unless told otherwise.
981 dev_priv
->allow_batchbuffer
= 1;
983 ret
= intel_init_bios(dev
);
985 DRM_INFO("failed to find VBIOS tables\n");
987 ret
= drm_irq_install(dev
);
989 goto destroy_ringbuffer
;
991 /* FIXME: re-add hotplug support */
993 ret
= drm_hotplug_init(dev
);
995 goto destroy_ringbuffer
;
998 /* Always safe in the mode setting case. */
999 /* FIXME: do pre/post-mode set stuff in core KMS code */
1000 dev
->vblank_disable_allowed
= 1;
1003 * Initialize the hardware status page IRQ location.
1006 I915_WRITE(INSTPM
, (1 << 5) | (1 << 21));
1008 intel_modeset_init(dev
);
1010 drm_helper_initial_config(dev
, false);
1015 i915_gem_cleanup_ringbuffer(dev
);
1017 kfree(dev
->devname
);
1022 int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
)
1024 struct drm_i915_master_private
*master_priv
;
1026 master_priv
= drm_calloc(1, sizeof(*master_priv
), DRM_MEM_DRIVER
);
1030 master
->driver_priv
= master_priv
;
1034 void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
)
1036 struct drm_i915_master_private
*master_priv
= master
->driver_priv
;
1041 drm_free(master_priv
, sizeof(*master_priv
), DRM_MEM_DRIVER
);
1043 master
->driver_priv
= NULL
;
1047 * i915_driver_load - setup chip and create an initial config
1049 * @flags: startup flags
1051 * The driver load routine has to do several things:
1052 * - drive output discovery via intel_modeset_init()
1053 * - initialize the memory manager
1054 * - allocate initial config memory
1055 * - setup the DRM framebuffer with the allocated memory
1057 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
1059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1060 unsigned long base
, size
;
1061 int ret
= 0, mmio_bar
= IS_I9XX(dev
) ? 0 : 1;
1063 /* i915 has 4 more counters */
1065 dev
->types
[6] = _DRM_STAT_IRQ
;
1066 dev
->types
[7] = _DRM_STAT_PRIMARY
;
1067 dev
->types
[8] = _DRM_STAT_SECONDARY
;
1068 dev
->types
[9] = _DRM_STAT_DMA
;
1070 dev_priv
= drm_alloc(sizeof(drm_i915_private_t
), DRM_MEM_DRIVER
);
1071 if (dev_priv
== NULL
)
1074 memset(dev_priv
, 0, sizeof(drm_i915_private_t
));
1076 dev
->dev_private
= (void *)dev_priv
;
1077 dev_priv
->dev
= dev
;
1079 /* Add register map (needed for suspend/resume) */
1080 base
= drm_get_resource_start(dev
, mmio_bar
);
1081 size
= drm_get_resource_len(dev
, mmio_bar
);
1083 dev_priv
->regs
= ioremap(base
, size
);
1084 if (!dev_priv
->regs
) {
1085 DRM_ERROR("failed to map registers\n");
1090 dev_priv
->mm
.gtt_mapping
=
1091 io_mapping_create_wc(dev
->agp
->base
,
1092 dev
->agp
->agp_info
.aper_size
* 1024*1024);
1093 if (dev_priv
->mm
.gtt_mapping
== NULL
) {
1098 /* Set up a WC MTRR for non-PAT systems. This is more common than
1099 * one would think, because the kernel disables PAT on first
1100 * generation Core chips because WC PAT gets overridden by a UC
1101 * MTRR if present. Even if a UC MTRR isn't present.
1103 dev_priv
->mm
.gtt_mtrr
= mtrr_add(dev
->agp
->base
,
1104 dev
->agp
->agp_info
.aper_size
*
1106 MTRR_TYPE_WRCOMB
, 1);
1107 if (dev_priv
->mm
.gtt_mtrr
< 0) {
1108 DRM_INFO("MTRR allocation failed. Graphics "
1109 "performance may suffer.\n");
1112 #ifdef CONFIG_HIGHMEM64G
1113 /* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
1114 dev_priv
->has_gem
= 0;
1116 /* enable GEM by default */
1117 dev_priv
->has_gem
= 1;
1120 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
1122 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
1127 if (!I915_NEED_GFX_HWS(dev
)) {
1128 ret
= i915_init_phys_hws(dev
);
1133 /* On the 945G/GM, the chipset reports the MSI capability on the
1134 * integrated graphics even though the support isn't actually there
1135 * according to the published specs. It doesn't appear to function
1136 * correctly in testing on 945G.
1137 * This may be a side effect of MSI having been made available for PEG
1138 * and the registers being closely associated.
1140 * According to chipset errata, on the 965GM, MSI interrupts may
1141 * be lost or delayed, but we use them anyways to avoid
1142 * stuck interrupts on some machines.
1144 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
1145 pci_enable_msi(dev
->pdev
);
1147 intel_opregion_init(dev
);
1149 spin_lock_init(&dev_priv
->user_irq_lock
);
1150 dev_priv
->user_irq_refcount
= 0;
1152 ret
= drm_vblank_init(dev
, I915_NUM_PIPE
);
1155 (void) i915_driver_unload(dev
);
1159 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1160 ret
= i915_load_modeset_init(dev
);
1162 DRM_ERROR("failed to init modeset\n");
1170 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
1172 iounmap(dev_priv
->regs
);
1174 drm_free(dev_priv
, sizeof(struct drm_i915_private
), DRM_MEM_DRIVER
);
1178 int i915_driver_unload(struct drm_device
*dev
)
1180 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1182 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
1183 if (dev_priv
->mm
.gtt_mtrr
>= 0) {
1184 mtrr_del(dev_priv
->mm
.gtt_mtrr
, dev
->agp
->base
,
1185 dev
->agp
->agp_info
.aper_size
* 1024 * 1024);
1186 dev_priv
->mm
.gtt_mtrr
= -1;
1189 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1190 drm_irq_uninstall(dev
);
1193 if (dev
->pdev
->msi_enabled
)
1194 pci_disable_msi(dev
->pdev
);
1196 if (dev_priv
->regs
!= NULL
)
1197 iounmap(dev_priv
->regs
);
1199 intel_opregion_free(dev
);
1201 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1202 intel_modeset_cleanup(dev
);
1204 i915_gem_free_all_phys_object(dev
);
1206 mutex_lock(&dev
->struct_mutex
);
1207 i915_gem_cleanup_ringbuffer(dev
);
1208 mutex_unlock(&dev
->struct_mutex
);
1209 drm_mm_takedown(&dev_priv
->vram
);
1210 i915_gem_lastclose(dev
);
1213 drm_free(dev
->dev_private
, sizeof(drm_i915_private_t
),
1219 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
1221 struct drm_i915_file_private
*i915_file_priv
;
1224 i915_file_priv
= (struct drm_i915_file_private
*)
1225 drm_alloc(sizeof(*i915_file_priv
), DRM_MEM_FILES
);
1227 if (!i915_file_priv
)
1230 file_priv
->driver_priv
= i915_file_priv
;
1232 i915_file_priv
->mm
.last_gem_seqno
= 0;
1233 i915_file_priv
->mm
.last_gem_throttle_seqno
= 0;
1239 * i915_driver_lastclose - clean up after all DRM clients have exited
1242 * Take care of cleaning up after all DRM clients have exited. In the
1243 * mode setting case, we want to restore the kernel's initial mode (just
1244 * in case the last client left us in a bad state).
1246 * Additionally, in the non-mode setting case, we'll tear down the AGP
1247 * and DMA structures, since the kernel won't be using them, and clea
1250 void i915_driver_lastclose(struct drm_device
* dev
)
1252 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1254 if (!dev_priv
|| drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1259 i915_gem_lastclose(dev
);
1261 if (dev_priv
->agp_heap
)
1262 i915_mem_takedown(&(dev_priv
->agp_heap
));
1264 i915_dma_cleanup(dev
);
1267 void i915_driver_preclose(struct drm_device
* dev
, struct drm_file
*file_priv
)
1269 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1270 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
1271 i915_mem_release(dev
, file_priv
, dev_priv
->agp_heap
);
1274 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file_priv
)
1276 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
1278 drm_free(i915_file_priv
, sizeof(*i915_file_priv
), DRM_MEM_FILES
);
1281 struct drm_ioctl_desc i915_ioctls
[] = {
1282 DRM_IOCTL_DEF(DRM_I915_INIT
, i915_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1283 DRM_IOCTL_DEF(DRM_I915_FLUSH
, i915_flush_ioctl
, DRM_AUTH
),
1284 DRM_IOCTL_DEF(DRM_I915_FLIP
, i915_flip_bufs
, DRM_AUTH
),
1285 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER
, i915_batchbuffer
, DRM_AUTH
),
1286 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT
, i915_irq_emit
, DRM_AUTH
),
1287 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT
, i915_irq_wait
, DRM_AUTH
),
1288 DRM_IOCTL_DEF(DRM_I915_GETPARAM
, i915_getparam
, DRM_AUTH
),
1289 DRM_IOCTL_DEF(DRM_I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1290 DRM_IOCTL_DEF(DRM_I915_ALLOC
, i915_mem_alloc
, DRM_AUTH
),
1291 DRM_IOCTL_DEF(DRM_I915_FREE
, i915_mem_free
, DRM_AUTH
),
1292 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP
, i915_mem_init_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1293 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER
, i915_cmdbuffer
, DRM_AUTH
),
1294 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP
, i915_mem_destroy_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1295 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE
, i915_vblank_pipe_set
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1296 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE
, i915_vblank_pipe_get
, DRM_AUTH
),
1297 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP
, i915_vblank_swap
, DRM_AUTH
),
1298 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR
, i915_set_status_page
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1299 DRM_IOCTL_DEF(DRM_I915_GEM_INIT
, i915_gem_init_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1300 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
1301 DRM_IOCTL_DEF(DRM_I915_GEM_PIN
, i915_gem_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
1302 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN
, i915_gem_unpin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
1303 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
),
1304 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
),
1305 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT
, i915_gem_entervt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1306 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT
, i915_gem_leavevt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1307 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE
, i915_gem_create_ioctl
, 0),
1308 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD
, i915_gem_pread_ioctl
, 0),
1309 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, 0),
1310 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP
, i915_gem_mmap_ioctl
, 0),
1311 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, 0),
1312 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, 0),
1313 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, 0),
1314 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING
, i915_gem_set_tiling
, 0),
1315 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING
, i915_gem_get_tiling
, 0),
1316 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, 0),
1319 int i915_max_ioctl
= DRM_ARRAY_SIZE(i915_ioctls
);
1322 * Determine if the device really is AGP or not.
1324 * All Intel graphics chipsets are treated as AGP, even if they are really
1327 * \param dev The device to be tested.
1330 * A value of 1 is always retured to indictate every i9x5 is AGP.
1332 int i915_driver_device_is_agp(struct drm_device
* dev
)