1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
36 #include "i915_trace.h"
37 #include <linux/vgaarb.h>
38 #include <linux/acpi.h>
39 #include <linux/pnp.h>
41 /* Really want an OS-independent resettable timer. Would like to have
42 * this loop run for (eg) 3 sec, but have the timer reset every time
43 * the head pointer changes, so that EBUSY only happens if the ring
44 * actually stalls for (eg) 3 seconds.
46 int i915_wait_ring(struct drm_device
* dev
, int n
, const char *caller
)
48 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
49 drm_i915_ring_buffer_t
*ring
= &(dev_priv
->ring
);
50 u32 acthd_reg
= IS_I965G(dev
) ? ACTHD_I965
: ACTHD
;
51 u32 last_acthd
= I915_READ(acthd_reg
);
53 u32 last_head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
56 trace_i915_ring_wait_begin (dev
);
58 for (i
= 0; i
< 100000; i
++) {
59 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
60 acthd
= I915_READ(acthd_reg
);
61 ring
->space
= ring
->head
- (ring
->tail
+ 8);
63 ring
->space
+= ring
->Size
;
64 if (ring
->space
>= n
) {
65 trace_i915_ring_wait_end (dev
);
69 if (dev
->primary
->master
) {
70 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
71 if (master_priv
->sarea_priv
)
72 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
76 if (ring
->head
!= last_head
)
78 if (acthd
!= last_acthd
)
81 last_head
= ring
->head
;
83 msleep_interruptible(10);
87 trace_i915_ring_wait_end (dev
);
91 /* As a ringbuffer is only allowed to wrap between instructions, fill
92 * the tail with NOOPs.
94 int i915_wrap_ring(struct drm_device
*dev
)
96 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
97 volatile unsigned int *virt
;
100 rem
= dev_priv
->ring
.Size
- dev_priv
->ring
.tail
;
101 if (dev_priv
->ring
.space
< rem
) {
102 int ret
= i915_wait_ring(dev
, rem
, __func__
);
106 dev_priv
->ring
.space
-= rem
;
108 virt
= (unsigned int *)
109 (dev_priv
->ring
.virtual_start
+ dev_priv
->ring
.tail
);
114 dev_priv
->ring
.tail
= 0;
120 * Sets up the hardware status page for devices that need a physical address
123 static int i915_init_phys_hws(struct drm_device
*dev
)
125 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
126 /* Program Hardware Status Page */
127 dev_priv
->status_page_dmah
=
128 drm_pci_alloc(dev
, PAGE_SIZE
, PAGE_SIZE
);
130 if (!dev_priv
->status_page_dmah
) {
131 DRM_ERROR("Can not allocate hardware status page\n");
134 dev_priv
->hw_status_page
= dev_priv
->status_page_dmah
->vaddr
;
135 dev_priv
->dma_status_page
= dev_priv
->status_page_dmah
->busaddr
;
137 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
140 dev_priv
->dma_status_page
|= (dev_priv
->dma_status_page
>> 28) &
143 I915_WRITE(HWS_PGA
, dev_priv
->dma_status_page
);
144 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
149 * Frees the hardware status page, whether it's a physical address or a virtual
150 * address set up by the X Server.
152 static void i915_free_hws(struct drm_device
*dev
)
154 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
155 if (dev_priv
->status_page_dmah
) {
156 drm_pci_free(dev
, dev_priv
->status_page_dmah
);
157 dev_priv
->status_page_dmah
= NULL
;
160 if (dev_priv
->status_gfx_addr
) {
161 dev_priv
->status_gfx_addr
= 0;
162 drm_core_ioremapfree(&dev_priv
->hws_map
, dev
);
165 /* Need to rewrite hardware status page */
166 I915_WRITE(HWS_PGA
, 0x1ffff000);
169 void i915_kernel_lost_context(struct drm_device
* dev
)
171 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
172 struct drm_i915_master_private
*master_priv
;
173 drm_i915_ring_buffer_t
*ring
= &(dev_priv
->ring
);
176 * We should never lose context on the ring with modesetting
177 * as we don't expose it to userspace
179 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
182 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
183 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
184 ring
->space
= ring
->head
- (ring
->tail
+ 8);
186 ring
->space
+= ring
->Size
;
188 if (!dev
->primary
->master
)
191 master_priv
= dev
->primary
->master
->driver_priv
;
192 if (ring
->head
== ring
->tail
&& master_priv
->sarea_priv
)
193 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_RING_EMPTY
;
196 static int i915_dma_cleanup(struct drm_device
* dev
)
198 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
199 /* Make sure interrupts are disabled here because the uninstall ioctl
200 * may not have been called from userspace and after dev_private
201 * is freed, it's too late.
203 if (dev
->irq_enabled
)
204 drm_irq_uninstall(dev
);
206 if (dev_priv
->ring
.virtual_start
) {
207 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
208 dev_priv
->ring
.virtual_start
= NULL
;
209 dev_priv
->ring
.map
.handle
= NULL
;
210 dev_priv
->ring
.map
.size
= 0;
213 /* Clear the HWS virtual address at teardown */
214 if (I915_NEED_GFX_HWS(dev
))
220 static int i915_initialize(struct drm_device
* dev
, drm_i915_init_t
* init
)
222 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
223 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
225 master_priv
->sarea
= drm_getsarea(dev
);
226 if (master_priv
->sarea
) {
227 master_priv
->sarea_priv
= (drm_i915_sarea_t
*)
228 ((u8
*)master_priv
->sarea
->handle
+ init
->sarea_priv_offset
);
230 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
233 if (init
->ring_size
!= 0) {
234 if (dev_priv
->ring
.ring_obj
!= NULL
) {
235 i915_dma_cleanup(dev
);
236 DRM_ERROR("Client tried to initialize ringbuffer in "
241 dev_priv
->ring
.Size
= init
->ring_size
;
243 dev_priv
->ring
.map
.offset
= init
->ring_start
;
244 dev_priv
->ring
.map
.size
= init
->ring_size
;
245 dev_priv
->ring
.map
.type
= 0;
246 dev_priv
->ring
.map
.flags
= 0;
247 dev_priv
->ring
.map
.mtrr
= 0;
249 drm_core_ioremap_wc(&dev_priv
->ring
.map
, dev
);
251 if (dev_priv
->ring
.map
.handle
== NULL
) {
252 i915_dma_cleanup(dev
);
253 DRM_ERROR("can not ioremap virtual address for"
259 dev_priv
->ring
.virtual_start
= dev_priv
->ring
.map
.handle
;
261 dev_priv
->cpp
= init
->cpp
;
262 dev_priv
->back_offset
= init
->back_offset
;
263 dev_priv
->front_offset
= init
->front_offset
;
264 dev_priv
->current_page
= 0;
265 if (master_priv
->sarea_priv
)
266 master_priv
->sarea_priv
->pf_current_page
= 0;
268 /* Allow hardware batchbuffers unless told otherwise.
270 dev_priv
->allow_batchbuffer
= 1;
275 static int i915_dma_resume(struct drm_device
* dev
)
277 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
279 DRM_DEBUG_DRIVER("%s\n", __func__
);
281 if (dev_priv
->ring
.map
.handle
== NULL
) {
282 DRM_ERROR("can not ioremap virtual address for"
287 /* Program Hardware Status Page */
288 if (!dev_priv
->hw_status_page
) {
289 DRM_ERROR("Can not find hardware status page\n");
292 DRM_DEBUG_DRIVER("hw status page @ %p\n",
293 dev_priv
->hw_status_page
);
295 if (dev_priv
->status_gfx_addr
!= 0)
296 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
298 I915_WRITE(HWS_PGA
, dev_priv
->dma_status_page
);
299 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
304 static int i915_dma_init(struct drm_device
*dev
, void *data
,
305 struct drm_file
*file_priv
)
307 drm_i915_init_t
*init
= data
;
310 switch (init
->func
) {
312 retcode
= i915_initialize(dev
, init
);
314 case I915_CLEANUP_DMA
:
315 retcode
= i915_dma_cleanup(dev
);
317 case I915_RESUME_DMA
:
318 retcode
= i915_dma_resume(dev
);
328 /* Implement basically the same security restrictions as hardware does
329 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
331 * Most of the calculations below involve calculating the size of a
332 * particular instruction. It's important to get the size right as
333 * that tells us where the next instruction to check is. Any illegal
334 * instruction detected will be given a size of zero, which is a
335 * signal to abort the rest of the buffer.
337 static int do_validate_cmd(int cmd
)
339 switch (((cmd
>> 29) & 0x7)) {
341 switch ((cmd
>> 23) & 0x3f) {
343 return 1; /* MI_NOOP */
345 return 1; /* MI_FLUSH */
347 return 0; /* disallow everything else */
351 return 0; /* reserved */
353 return (cmd
& 0xff) + 2; /* 2d commands */
355 if (((cmd
>> 24) & 0x1f) <= 0x18)
358 switch ((cmd
>> 24) & 0x1f) {
362 switch ((cmd
>> 16) & 0xff) {
364 return (cmd
& 0x1f) + 2;
366 return (cmd
& 0xf) + 2;
368 return (cmd
& 0xffff) + 2;
372 return (cmd
& 0xffff) + 1;
376 if ((cmd
& (1 << 23)) == 0) /* inline vertices */
377 return (cmd
& 0x1ffff) + 2;
378 else if (cmd
& (1 << 17)) /* indirect random */
379 if ((cmd
& 0xffff) == 0)
380 return 0; /* unknown length, too hard */
382 return (((cmd
& 0xffff) + 1) / 2) + 1;
384 return 2; /* indirect sequential */
395 static int validate_cmd(int cmd
)
397 int ret
= do_validate_cmd(cmd
);
399 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
404 static int i915_emit_cmds(struct drm_device
* dev
, int *buffer
, int dwords
)
406 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
410 if ((dwords
+1) * sizeof(int) >= dev_priv
->ring
.Size
- 8)
413 BEGIN_LP_RING((dwords
+1)&~1);
415 for (i
= 0; i
< dwords
;) {
420 if ((sz
= validate_cmd(cmd
)) == 0 || i
+ sz
> dwords
)
439 i915_emit_box(struct drm_device
*dev
,
440 struct drm_clip_rect
*boxes
,
441 int i
, int DR1
, int DR4
)
443 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
444 struct drm_clip_rect box
= boxes
[i
];
447 if (box
.y2
<= box
.y1
|| box
.x2
<= box
.x1
|| box
.y2
<= 0 || box
.x2
<= 0) {
448 DRM_ERROR("Bad box %d,%d..%d,%d\n",
449 box
.x1
, box
.y1
, box
.x2
, box
.y2
);
455 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
456 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
457 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
462 OUT_RING(GFX_OP_DRAWRECT_INFO
);
464 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
465 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
474 /* XXX: Emitting the counter should really be moved to part of the IRQ
475 * emit. For now, do it in both places:
478 static void i915_emit_breadcrumb(struct drm_device
*dev
)
480 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
481 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
485 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
486 dev_priv
->counter
= 0;
487 if (master_priv
->sarea_priv
)
488 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
491 OUT_RING(MI_STORE_DWORD_INDEX
);
492 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
493 OUT_RING(dev_priv
->counter
);
498 static int i915_dispatch_cmdbuffer(struct drm_device
* dev
,
499 drm_i915_cmdbuffer_t
*cmd
,
500 struct drm_clip_rect
*cliprects
,
503 int nbox
= cmd
->num_cliprects
;
504 int i
= 0, count
, ret
;
507 DRM_ERROR("alignment");
511 i915_kernel_lost_context(dev
);
513 count
= nbox
? nbox
: 1;
515 for (i
= 0; i
< count
; i
++) {
517 ret
= i915_emit_box(dev
, cliprects
, i
,
523 ret
= i915_emit_cmds(dev
, cmdbuf
, cmd
->sz
/ 4);
528 i915_emit_breadcrumb(dev
);
532 static int i915_dispatch_batchbuffer(struct drm_device
* dev
,
533 drm_i915_batchbuffer_t
* batch
,
534 struct drm_clip_rect
*cliprects
)
536 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
537 int nbox
= batch
->num_cliprects
;
541 if ((batch
->start
| batch
->used
) & 0x7) {
542 DRM_ERROR("alignment");
546 i915_kernel_lost_context(dev
);
548 count
= nbox
? nbox
: 1;
550 for (i
= 0; i
< count
; i
++) {
552 int ret
= i915_emit_box(dev
, cliprects
, i
,
553 batch
->DR1
, batch
->DR4
);
558 if (!IS_I830(dev
) && !IS_845G(dev
)) {
561 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6) | MI_BATCH_NON_SECURE_I965
);
562 OUT_RING(batch
->start
);
564 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
565 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
570 OUT_RING(MI_BATCH_BUFFER
);
571 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
572 OUT_RING(batch
->start
+ batch
->used
- 4);
578 i915_emit_breadcrumb(dev
);
583 static int i915_dispatch_flip(struct drm_device
* dev
)
585 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
586 struct drm_i915_master_private
*master_priv
=
587 dev
->primary
->master
->driver_priv
;
590 if (!master_priv
->sarea_priv
)
593 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
595 dev_priv
->current_page
,
596 master_priv
->sarea_priv
->pf_current_page
);
598 i915_kernel_lost_context(dev
);
601 OUT_RING(MI_FLUSH
| MI_READ_FLUSH
);
606 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
608 if (dev_priv
->current_page
== 0) {
609 OUT_RING(dev_priv
->back_offset
);
610 dev_priv
->current_page
= 1;
612 OUT_RING(dev_priv
->front_offset
);
613 dev_priv
->current_page
= 0;
619 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
623 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
++;
626 OUT_RING(MI_STORE_DWORD_INDEX
);
627 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
628 OUT_RING(dev_priv
->counter
);
632 master_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
636 static int i915_quiescent(struct drm_device
* dev
)
638 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
640 i915_kernel_lost_context(dev
);
641 return i915_wait_ring(dev
, dev_priv
->ring
.Size
- 8, __func__
);
644 static int i915_flush_ioctl(struct drm_device
*dev
, void *data
,
645 struct drm_file
*file_priv
)
649 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
651 mutex_lock(&dev
->struct_mutex
);
652 ret
= i915_quiescent(dev
);
653 mutex_unlock(&dev
->struct_mutex
);
658 static int i915_batchbuffer(struct drm_device
*dev
, void *data
,
659 struct drm_file
*file_priv
)
661 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
662 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
663 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
664 master_priv
->sarea_priv
;
665 drm_i915_batchbuffer_t
*batch
= data
;
667 struct drm_clip_rect
*cliprects
= NULL
;
669 if (!dev_priv
->allow_batchbuffer
) {
670 DRM_ERROR("Batchbuffer ioctl disabled\n");
674 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
675 batch
->start
, batch
->used
, batch
->num_cliprects
);
677 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
679 if (batch
->num_cliprects
< 0)
682 if (batch
->num_cliprects
) {
683 cliprects
= kcalloc(batch
->num_cliprects
,
684 sizeof(struct drm_clip_rect
),
686 if (cliprects
== NULL
)
689 ret
= copy_from_user(cliprects
, batch
->cliprects
,
690 batch
->num_cliprects
*
691 sizeof(struct drm_clip_rect
));
696 mutex_lock(&dev
->struct_mutex
);
697 ret
= i915_dispatch_batchbuffer(dev
, batch
, cliprects
);
698 mutex_unlock(&dev
->struct_mutex
);
701 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
709 static int i915_cmdbuffer(struct drm_device
*dev
, void *data
,
710 struct drm_file
*file_priv
)
712 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
713 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
714 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
715 master_priv
->sarea_priv
;
716 drm_i915_cmdbuffer_t
*cmdbuf
= data
;
717 struct drm_clip_rect
*cliprects
= NULL
;
721 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
722 cmdbuf
->buf
, cmdbuf
->sz
, cmdbuf
->num_cliprects
);
724 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
726 if (cmdbuf
->num_cliprects
< 0)
729 batch_data
= kmalloc(cmdbuf
->sz
, GFP_KERNEL
);
730 if (batch_data
== NULL
)
733 ret
= copy_from_user(batch_data
, cmdbuf
->buf
, cmdbuf
->sz
);
735 goto fail_batch_free
;
737 if (cmdbuf
->num_cliprects
) {
738 cliprects
= kcalloc(cmdbuf
->num_cliprects
,
739 sizeof(struct drm_clip_rect
), GFP_KERNEL
);
740 if (cliprects
== NULL
) {
742 goto fail_batch_free
;
745 ret
= copy_from_user(cliprects
, cmdbuf
->cliprects
,
746 cmdbuf
->num_cliprects
*
747 sizeof(struct drm_clip_rect
));
752 mutex_lock(&dev
->struct_mutex
);
753 ret
= i915_dispatch_cmdbuffer(dev
, cmdbuf
, cliprects
, batch_data
);
754 mutex_unlock(&dev
->struct_mutex
);
756 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
761 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
771 static int i915_flip_bufs(struct drm_device
*dev
, void *data
,
772 struct drm_file
*file_priv
)
776 DRM_DEBUG_DRIVER("%s\n", __func__
);
778 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
780 mutex_lock(&dev
->struct_mutex
);
781 ret
= i915_dispatch_flip(dev
);
782 mutex_unlock(&dev
->struct_mutex
);
787 static int i915_getparam(struct drm_device
*dev
, void *data
,
788 struct drm_file
*file_priv
)
790 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
791 drm_i915_getparam_t
*param
= data
;
795 DRM_ERROR("called with no initialization\n");
799 switch (param
->param
) {
800 case I915_PARAM_IRQ_ACTIVE
:
801 value
= dev
->pdev
->irq
? 1 : 0;
803 case I915_PARAM_ALLOW_BATCHBUFFER
:
804 value
= dev_priv
->allow_batchbuffer
? 1 : 0;
806 case I915_PARAM_LAST_DISPATCH
:
807 value
= READ_BREADCRUMB(dev_priv
);
809 case I915_PARAM_CHIPSET_ID
:
810 value
= dev
->pci_device
;
812 case I915_PARAM_HAS_GEM
:
813 value
= dev_priv
->has_gem
;
815 case I915_PARAM_NUM_FENCES_AVAIL
:
816 value
= dev_priv
->num_fence_regs
- dev_priv
->fence_reg_start
;
818 case I915_PARAM_HAS_OVERLAY
:
819 value
= dev_priv
->overlay
? 1 : 0;
821 case I915_PARAM_HAS_PAGEFLIPPING
:
824 case I915_PARAM_HAS_EXECBUF2
:
826 value
= dev_priv
->has_gem
;
829 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
834 if (DRM_COPY_TO_USER(param
->value
, &value
, sizeof(int))) {
835 DRM_ERROR("DRM_COPY_TO_USER failed\n");
842 static int i915_setparam(struct drm_device
*dev
, void *data
,
843 struct drm_file
*file_priv
)
845 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
846 drm_i915_setparam_t
*param
= data
;
849 DRM_ERROR("called with no initialization\n");
853 switch (param
->param
) {
854 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
856 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
857 dev_priv
->tex_lru_log_granularity
= param
->value
;
859 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
860 dev_priv
->allow_batchbuffer
= param
->value
;
862 case I915_SETPARAM_NUM_USED_FENCES
:
863 if (param
->value
> dev_priv
->num_fence_regs
||
866 /* Userspace can use first N regs */
867 dev_priv
->fence_reg_start
= param
->value
;
870 DRM_DEBUG_DRIVER("unknown parameter %d\n",
878 static int i915_set_status_page(struct drm_device
*dev
, void *data
,
879 struct drm_file
*file_priv
)
881 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
882 drm_i915_hws_addr_t
*hws
= data
;
884 if (!I915_NEED_GFX_HWS(dev
))
888 DRM_ERROR("called with no initialization\n");
892 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
893 WARN(1, "tried to set status page when mode setting active\n");
897 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32
)hws
->addr
);
899 dev_priv
->status_gfx_addr
= hws
->addr
& (0x1ffff<<12);
901 dev_priv
->hws_map
.offset
= dev
->agp
->base
+ hws
->addr
;
902 dev_priv
->hws_map
.size
= 4*1024;
903 dev_priv
->hws_map
.type
= 0;
904 dev_priv
->hws_map
.flags
= 0;
905 dev_priv
->hws_map
.mtrr
= 0;
907 drm_core_ioremap_wc(&dev_priv
->hws_map
, dev
);
908 if (dev_priv
->hws_map
.handle
== NULL
) {
909 i915_dma_cleanup(dev
);
910 dev_priv
->status_gfx_addr
= 0;
911 DRM_ERROR("can not ioremap virtual address for"
912 " G33 hw status page\n");
915 dev_priv
->hw_status_page
= dev_priv
->hws_map
.handle
;
917 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
918 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
919 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
920 dev_priv
->status_gfx_addr
);
921 DRM_DEBUG_DRIVER("load hws at %p\n",
922 dev_priv
->hw_status_page
);
926 static int i915_get_bridge_dev(struct drm_device
*dev
)
928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
930 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
931 if (!dev_priv
->bridge_dev
) {
932 DRM_ERROR("bridge device not found\n");
938 #define MCHBAR_I915 0x44
939 #define MCHBAR_I965 0x48
940 #define MCHBAR_SIZE (4*4096)
942 #define DEVEN_REG 0x54
943 #define DEVEN_MCHBAR_EN (1 << 28)
945 /* Allocate space for the MCH regs if needed, return nonzero on error */
947 intel_alloc_mchbar_resource(struct drm_device
*dev
)
949 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
950 int reg
= IS_I965G(dev
) ? MCHBAR_I965
: MCHBAR_I915
;
951 u32 temp_lo
, temp_hi
= 0;
956 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
957 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
958 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
960 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
963 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
)) {
969 /* Get some space for it */
970 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
, &dev_priv
->mch_res
,
971 MCHBAR_SIZE
, MCHBAR_SIZE
,
973 0, pcibios_align_resource
,
974 dev_priv
->bridge_dev
);
976 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
977 dev_priv
->mch_res
.start
= 0;
982 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
983 upper_32_bits(dev_priv
->mch_res
.start
));
985 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
986 lower_32_bits(dev_priv
->mch_res
.start
));
991 /* Setup MCHBAR if possible, return true if we should disable it again */
993 intel_setup_mchbar(struct drm_device
*dev
)
995 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
996 int mchbar_reg
= IS_I965G(dev
) ? MCHBAR_I965
: MCHBAR_I915
;
1000 dev_priv
->mchbar_need_disable
= false;
1002 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1003 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
1004 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
1006 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1010 /* If it's already enabled, don't have to do anything */
1014 if (intel_alloc_mchbar_resource(dev
))
1017 dev_priv
->mchbar_need_disable
= true;
1019 /* Space is allocated or reserved, so enable it. */
1020 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1021 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
,
1022 temp
| DEVEN_MCHBAR_EN
);
1024 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1025 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
1030 intel_teardown_mchbar(struct drm_device
*dev
)
1032 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1033 int mchbar_reg
= IS_I965G(dev
) ? MCHBAR_I965
: MCHBAR_I915
;
1036 if (dev_priv
->mchbar_need_disable
) {
1037 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1038 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
1039 temp
&= ~DEVEN_MCHBAR_EN
;
1040 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, temp
);
1042 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1044 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
);
1048 if (dev_priv
->mch_res
.start
)
1049 release_resource(&dev_priv
->mch_res
);
1053 * i915_probe_agp - get AGP bootup configuration
1055 * @aperture_size: returns AGP aperture configured size
1056 * @preallocated_size: returns size of BIOS preallocated AGP space
1058 * Since Intel integrated graphics are UMA, the BIOS has to set aside
1059 * some RAM for the framebuffer at early boot. This code figures out
1060 * how much was set aside so we can use it for our own purposes.
1062 static int i915_probe_agp(struct drm_device
*dev
, uint32_t *aperture_size
,
1063 uint32_t *preallocated_size
,
1066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1068 unsigned long overhead
;
1069 unsigned long stolen
;
1071 /* Get the fb aperture size and "stolen" memory amount. */
1072 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &tmp
);
1074 *aperture_size
= 1024 * 1024;
1075 *preallocated_size
= 1024 * 1024;
1077 switch (dev
->pdev
->device
) {
1078 case PCI_DEVICE_ID_INTEL_82830_CGC
:
1079 case PCI_DEVICE_ID_INTEL_82845G_IG
:
1080 case PCI_DEVICE_ID_INTEL_82855GM_IG
:
1081 case PCI_DEVICE_ID_INTEL_82865_IG
:
1082 if ((tmp
& INTEL_GMCH_MEM_MASK
) == INTEL_GMCH_MEM_64M
)
1083 *aperture_size
*= 64;
1085 *aperture_size
*= 128;
1088 /* 9xx supports large sizes, just look at the length */
1089 *aperture_size
= pci_resource_len(dev
->pdev
, 2);
1094 * Some of the preallocated space is taken by the GTT
1095 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1097 if (IS_G4X(dev
) || IS_PINEVIEW(dev
) || IS_IRONLAKE(dev
) || IS_GEN6(dev
))
1100 overhead
= (*aperture_size
/ 1024) + 4096;
1102 switch (tmp
& INTEL_GMCH_GMS_MASK
) {
1103 case INTEL_855_GMCH_GMS_DISABLED
:
1104 /* XXX: This is what my A1 silicon has. */
1106 stolen
= 64 * 1024 * 1024;
1108 DRM_ERROR("video memory is disabled\n");
1112 case INTEL_855_GMCH_GMS_STOLEN_1M
:
1113 stolen
= 1 * 1024 * 1024;
1115 case INTEL_855_GMCH_GMS_STOLEN_4M
:
1116 stolen
= 4 * 1024 * 1024;
1118 case INTEL_855_GMCH_GMS_STOLEN_8M
:
1119 stolen
= 8 * 1024 * 1024;
1121 case INTEL_855_GMCH_GMS_STOLEN_16M
:
1122 stolen
= 16 * 1024 * 1024;
1124 case INTEL_855_GMCH_GMS_STOLEN_32M
:
1125 stolen
= 32 * 1024 * 1024;
1127 case INTEL_915G_GMCH_GMS_STOLEN_48M
:
1128 stolen
= 48 * 1024 * 1024;
1130 case INTEL_915G_GMCH_GMS_STOLEN_64M
:
1131 stolen
= 64 * 1024 * 1024;
1133 case INTEL_GMCH_GMS_STOLEN_128M
:
1134 stolen
= 128 * 1024 * 1024;
1136 case INTEL_GMCH_GMS_STOLEN_256M
:
1137 stolen
= 256 * 1024 * 1024;
1139 case INTEL_GMCH_GMS_STOLEN_96M
:
1140 stolen
= 96 * 1024 * 1024;
1142 case INTEL_GMCH_GMS_STOLEN_160M
:
1143 stolen
= 160 * 1024 * 1024;
1145 case INTEL_GMCH_GMS_STOLEN_224M
:
1146 stolen
= 224 * 1024 * 1024;
1148 case INTEL_GMCH_GMS_STOLEN_352M
:
1149 stolen
= 352 * 1024 * 1024;
1152 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1153 tmp
& INTEL_GMCH_GMS_MASK
);
1156 *preallocated_size
= stolen
- overhead
;
1162 #define PTE_ADDRESS_MASK 0xfffff000
1163 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1164 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1165 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1166 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1167 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1168 #define PTE_VALID (1 << 0)
1171 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1173 * @gtt_addr: address to translate
1175 * Some chip functions require allocations from stolen space but need the
1176 * physical address of the memory in question. We use this routine
1177 * to get a physical address suitable for register programming from a given
1180 static unsigned long i915_gtt_to_phys(struct drm_device
*dev
,
1181 unsigned long gtt_addr
)
1184 unsigned long entry
, phys
;
1185 int gtt_bar
= IS_I9XX(dev
) ? 0 : 1;
1186 int gtt_offset
, gtt_size
;
1188 if (IS_I965G(dev
)) {
1189 if (IS_G4X(dev
) || IS_IRONLAKE(dev
) || IS_GEN6(dev
)) {
1190 gtt_offset
= 2*1024*1024;
1191 gtt_size
= 2*1024*1024;
1193 gtt_offset
= 512*1024;
1194 gtt_size
= 512*1024;
1199 gtt_size
= pci_resource_len(dev
->pdev
, gtt_bar
);
1202 gtt
= ioremap_wc(pci_resource_start(dev
->pdev
, gtt_bar
) + gtt_offset
,
1205 DRM_ERROR("ioremap of GTT failed\n");
1209 entry
= *(volatile u32
*)(gtt
+ (gtt_addr
/ 1024));
1211 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr
, entry
);
1213 /* Mask out these reserved bits on this hardware. */
1214 if (!IS_I9XX(dev
) || IS_I915G(dev
) || IS_I915GM(dev
) ||
1215 IS_I945G(dev
) || IS_I945GM(dev
)) {
1216 entry
&= ~PTE_ADDRESS_MASK_HIGH
;
1219 /* If it's not a mapping type we know, then bail. */
1220 if ((entry
& PTE_MAPPING_TYPE_MASK
) != PTE_MAPPING_TYPE_UNCACHED
&&
1221 (entry
& PTE_MAPPING_TYPE_MASK
) != PTE_MAPPING_TYPE_CACHED
) {
1226 if (!(entry
& PTE_VALID
)) {
1227 DRM_ERROR("bad GTT entry in stolen space\n");
1234 phys
=(entry
& PTE_ADDRESS_MASK
) |
1235 ((uint64_t)(entry
& PTE_ADDRESS_MASK_HIGH
) << (32 - 4));
1237 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr
, phys
);
1242 static void i915_warn_stolen(struct drm_device
*dev
)
1244 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1245 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1248 static void i915_setup_compression(struct drm_device
*dev
, int size
)
1250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1251 struct drm_mm_node
*compressed_fb
, *compressed_llb
;
1252 unsigned long cfb_base
;
1253 unsigned long ll_base
= 0;
1255 /* Leave 1M for line length buffer & misc. */
1256 compressed_fb
= drm_mm_search_free(&dev_priv
->vram
, size
, 4096, 0);
1257 if (!compressed_fb
) {
1258 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1259 i915_warn_stolen(dev
);
1263 compressed_fb
= drm_mm_get_block(compressed_fb
, size
, 4096);
1264 if (!compressed_fb
) {
1265 i915_warn_stolen(dev
);
1266 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1270 cfb_base
= i915_gtt_to_phys(dev
, compressed_fb
->start
);
1272 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1273 drm_mm_put_block(compressed_fb
);
1276 if (!IS_GM45(dev
)) {
1277 compressed_llb
= drm_mm_search_free(&dev_priv
->vram
, 4096,
1279 if (!compressed_llb
) {
1280 i915_warn_stolen(dev
);
1284 compressed_llb
= drm_mm_get_block(compressed_llb
, 4096, 4096);
1285 if (!compressed_llb
) {
1286 i915_warn_stolen(dev
);
1290 ll_base
= i915_gtt_to_phys(dev
, compressed_llb
->start
);
1292 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1293 drm_mm_put_block(compressed_fb
);
1294 drm_mm_put_block(compressed_llb
);
1298 dev_priv
->cfb_size
= size
;
1301 g4x_disable_fbc(dev
);
1302 I915_WRITE(DPFC_CB_BASE
, compressed_fb
->start
);
1304 i8xx_disable_fbc(dev
);
1305 I915_WRITE(FBC_CFB_BASE
, cfb_base
);
1306 I915_WRITE(FBC_LL_BASE
, ll_base
);
1309 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base
,
1310 ll_base
, size
>> 20);
1313 /* true = enable decode, false = disable decoder */
1314 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
1316 struct drm_device
*dev
= cookie
;
1318 intel_modeset_vga_set_state(dev
, state
);
1320 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1321 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1323 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1326 static int i915_load_modeset_init(struct drm_device
*dev
,
1327 unsigned long prealloc_start
,
1328 unsigned long prealloc_size
,
1329 unsigned long agp_size
)
1331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1332 int fb_bar
= IS_I9XX(dev
) ? 2 : 0;
1335 dev
->mode_config
.fb_base
= drm_get_resource_start(dev
, fb_bar
) &
1338 /* Basic memrange allocator for stolen space (aka vram) */
1339 drm_mm_init(&dev_priv
->vram
, 0, prealloc_size
);
1340 DRM_INFO("set up %ldM of stolen space\n", prealloc_size
/ (1024*1024));
1342 /* We're off and running w/KMS */
1343 dev_priv
->mm
.suspended
= 0;
1345 /* Let GEM Manage from end of prealloc space to end of aperture.
1347 * However, leave one page at the end still bound to the scratch page.
1348 * There are a number of places where the hardware apparently
1349 * prefetches past the end of the object, and we've seen multiple
1350 * hangs with the GPU head pointer stuck in a batchbuffer bound
1351 * at the last page of the aperture. One page should be enough to
1352 * keep any prefetching inside of the aperture.
1354 i915_gem_do_init(dev
, prealloc_size
, agp_size
- 4096);
1356 mutex_lock(&dev
->struct_mutex
);
1357 ret
= i915_gem_init_ringbuffer(dev
);
1358 mutex_unlock(&dev
->struct_mutex
);
1362 /* Try to set up FBC with a reasonable compressed buffer size */
1363 if (I915_HAS_FBC(dev
) && i915_powersave
) {
1366 /* Try to get an 8M buffer... */
1367 if (prealloc_size
> (9*1024*1024))
1368 cfb_size
= 8*1024*1024;
1369 else /* fall back to 7/8 of the stolen space */
1370 cfb_size
= prealloc_size
* 7 / 8;
1371 i915_setup_compression(dev
, cfb_size
);
1374 /* Allow hardware batchbuffers unless told otherwise.
1376 dev_priv
->allow_batchbuffer
= 1;
1378 ret
= intel_init_bios(dev
);
1380 DRM_INFO("failed to find VBIOS tables\n");
1382 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1383 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
1385 goto destroy_ringbuffer
;
1387 intel_modeset_init(dev
);
1389 ret
= drm_irq_install(dev
);
1391 goto destroy_ringbuffer
;
1393 /* Always safe in the mode setting case. */
1394 /* FIXME: do pre/post-mode set stuff in core KMS code */
1395 dev
->vblank_disable_allowed
= 1;
1398 * Initialize the hardware status page IRQ location.
1401 I915_WRITE(INSTPM
, (1 << 5) | (1 << 21));
1403 drm_helper_initial_config(dev
);
1408 mutex_lock(&dev
->struct_mutex
);
1409 i915_gem_cleanup_ringbuffer(dev
);
1410 mutex_unlock(&dev
->struct_mutex
);
1415 int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
)
1417 struct drm_i915_master_private
*master_priv
;
1419 master_priv
= kzalloc(sizeof(*master_priv
), GFP_KERNEL
);
1423 master
->driver_priv
= master_priv
;
1427 void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
)
1429 struct drm_i915_master_private
*master_priv
= master
->driver_priv
;
1436 master
->driver_priv
= NULL
;
1439 static void i915_get_mem_freq(struct drm_device
*dev
)
1441 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1444 if (!IS_PINEVIEW(dev
))
1447 tmp
= I915_READ(CLKCFG
);
1449 switch (tmp
& CLKCFG_FSB_MASK
) {
1450 case CLKCFG_FSB_533
:
1451 dev_priv
->fsb_freq
= 533; /* 133*4 */
1453 case CLKCFG_FSB_800
:
1454 dev_priv
->fsb_freq
= 800; /* 200*4 */
1456 case CLKCFG_FSB_667
:
1457 dev_priv
->fsb_freq
= 667; /* 167*4 */
1459 case CLKCFG_FSB_400
:
1460 dev_priv
->fsb_freq
= 400; /* 100*4 */
1464 switch (tmp
& CLKCFG_MEM_MASK
) {
1465 case CLKCFG_MEM_533
:
1466 dev_priv
->mem_freq
= 533;
1468 case CLKCFG_MEM_667
:
1469 dev_priv
->mem_freq
= 667;
1471 case CLKCFG_MEM_800
:
1472 dev_priv
->mem_freq
= 800;
1478 * i915_driver_load - setup chip and create an initial config
1480 * @flags: startup flags
1482 * The driver load routine has to do several things:
1483 * - drive output discovery via intel_modeset_init()
1484 * - initialize the memory manager
1485 * - allocate initial config memory
1486 * - setup the DRM framebuffer with the allocated memory
1488 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
1490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1491 resource_size_t base
, size
;
1492 int ret
= 0, mmio_bar
;
1493 uint32_t agp_size
, prealloc_size
, prealloc_start
;
1495 /* i915 has 4 more counters */
1497 dev
->types
[6] = _DRM_STAT_IRQ
;
1498 dev
->types
[7] = _DRM_STAT_PRIMARY
;
1499 dev
->types
[8] = _DRM_STAT_SECONDARY
;
1500 dev
->types
[9] = _DRM_STAT_DMA
;
1502 dev_priv
= kzalloc(sizeof(drm_i915_private_t
), GFP_KERNEL
);
1503 if (dev_priv
== NULL
)
1506 dev
->dev_private
= (void *)dev_priv
;
1507 dev_priv
->dev
= dev
;
1508 dev_priv
->info
= (struct intel_device_info
*) flags
;
1510 /* Add register map (needed for suspend/resume) */
1511 mmio_bar
= IS_I9XX(dev
) ? 0 : 1;
1512 base
= drm_get_resource_start(dev
, mmio_bar
);
1513 size
= drm_get_resource_len(dev
, mmio_bar
);
1515 if (i915_get_bridge_dev(dev
)) {
1520 dev_priv
->regs
= ioremap(base
, size
);
1521 if (!dev_priv
->regs
) {
1522 DRM_ERROR("failed to map registers\n");
1527 dev_priv
->mm
.gtt_mapping
=
1528 io_mapping_create_wc(dev
->agp
->base
,
1529 dev
->agp
->agp_info
.aper_size
* 1024*1024);
1530 if (dev_priv
->mm
.gtt_mapping
== NULL
) {
1535 /* Set up a WC MTRR for non-PAT systems. This is more common than
1536 * one would think, because the kernel disables PAT on first
1537 * generation Core chips because WC PAT gets overridden by a UC
1538 * MTRR if present. Even if a UC MTRR isn't present.
1540 dev_priv
->mm
.gtt_mtrr
= mtrr_add(dev
->agp
->base
,
1541 dev
->agp
->agp_info
.aper_size
*
1543 MTRR_TYPE_WRCOMB
, 1);
1544 if (dev_priv
->mm
.gtt_mtrr
< 0) {
1545 DRM_INFO("MTRR allocation failed. Graphics "
1546 "performance may suffer.\n");
1549 ret
= i915_probe_agp(dev
, &agp_size
, &prealloc_size
, &prealloc_start
);
1553 dev_priv
->wq
= create_singlethread_workqueue("i915");
1554 if (dev_priv
->wq
== NULL
) {
1555 DRM_ERROR("Failed to create our workqueue.\n");
1560 /* enable GEM by default */
1561 dev_priv
->has_gem
= 1;
1563 if (prealloc_size
> agp_size
* 3 / 4) {
1564 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1566 prealloc_size
/ 1024, agp_size
/ 1024);
1567 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1568 "updating the BIOS to fix).\n");
1569 dev_priv
->has_gem
= 0;
1572 dev
->driver
->get_vblank_counter
= i915_get_vblank_counter
;
1573 dev
->max_vblank_count
= 0xffffff; /* only 24 bits of frame count */
1574 if (IS_G4X(dev
) || IS_IRONLAKE(dev
) || IS_GEN6(dev
)) {
1575 dev
->max_vblank_count
= 0xffffffff; /* full 32 bit counter */
1576 dev
->driver
->get_vblank_counter
= gm45_get_vblank_counter
;
1579 /* Try to make sure MCHBAR is enabled before poking at it */
1580 intel_setup_mchbar(dev
);
1585 if (!I915_NEED_GFX_HWS(dev
)) {
1586 ret
= i915_init_phys_hws(dev
);
1588 goto out_workqueue_free
;
1591 i915_get_mem_freq(dev
);
1593 /* On the 945G/GM, the chipset reports the MSI capability on the
1594 * integrated graphics even though the support isn't actually there
1595 * according to the published specs. It doesn't appear to function
1596 * correctly in testing on 945G.
1597 * This may be a side effect of MSI having been made available for PEG
1598 * and the registers being closely associated.
1600 * According to chipset errata, on the 965GM, MSI interrupts may
1601 * be lost or delayed, but we use them anyways to avoid
1602 * stuck interrupts on some machines.
1604 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
1605 pci_enable_msi(dev
->pdev
);
1607 spin_lock_init(&dev_priv
->user_irq_lock
);
1608 spin_lock_init(&dev_priv
->error_lock
);
1609 dev_priv
->user_irq_refcount
= 0;
1610 dev_priv
->trace_irq_seqno
= 0;
1612 ret
= drm_vblank_init(dev
, I915_NUM_PIPE
);
1615 (void) i915_driver_unload(dev
);
1619 /* Start out suspended */
1620 dev_priv
->mm
.suspended
= 1;
1622 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1623 ret
= i915_load_modeset_init(dev
, prealloc_start
,
1624 prealloc_size
, agp_size
);
1626 DRM_ERROR("failed to init modeset\n");
1627 goto out_workqueue_free
;
1631 /* Must be done after probing outputs */
1632 intel_opregion_init(dev
, 0);
1634 setup_timer(&dev_priv
->hangcheck_timer
, i915_hangcheck_elapsed
,
1635 (unsigned long) dev
);
1639 destroy_workqueue(dev_priv
->wq
);
1641 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
1643 iounmap(dev_priv
->regs
);
1645 pci_dev_put(dev_priv
->bridge_dev
);
1651 int i915_driver_unload(struct drm_device
*dev
)
1653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1655 i915_destroy_error_state(dev
);
1657 destroy_workqueue(dev_priv
->wq
);
1658 del_timer_sync(&dev_priv
->hangcheck_timer
);
1660 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
1661 if (dev_priv
->mm
.gtt_mtrr
>= 0) {
1662 mtrr_del(dev_priv
->mm
.gtt_mtrr
, dev
->agp
->base
,
1663 dev
->agp
->agp_info
.aper_size
* 1024 * 1024);
1664 dev_priv
->mm
.gtt_mtrr
= -1;
1667 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1669 * free the memory space allocated for the child device
1670 * config parsed from VBT
1672 if (dev_priv
->child_dev
&& dev_priv
->child_dev_num
) {
1673 kfree(dev_priv
->child_dev
);
1674 dev_priv
->child_dev
= NULL
;
1675 dev_priv
->child_dev_num
= 0;
1677 drm_irq_uninstall(dev
);
1678 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1681 if (dev
->pdev
->msi_enabled
)
1682 pci_disable_msi(dev
->pdev
);
1684 if (dev_priv
->regs
!= NULL
)
1685 iounmap(dev_priv
->regs
);
1687 intel_opregion_free(dev
, 0);
1689 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1690 intel_modeset_cleanup(dev
);
1692 i915_gem_free_all_phys_object(dev
);
1694 mutex_lock(&dev
->struct_mutex
);
1695 i915_gem_cleanup_ringbuffer(dev
);
1696 mutex_unlock(&dev
->struct_mutex
);
1697 drm_mm_takedown(&dev_priv
->vram
);
1698 i915_gem_lastclose(dev
);
1700 intel_cleanup_overlay(dev
);
1703 intel_teardown_mchbar(dev
);
1705 pci_dev_put(dev_priv
->bridge_dev
);
1706 kfree(dev
->dev_private
);
1711 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
1713 struct drm_i915_file_private
*i915_file_priv
;
1715 DRM_DEBUG_DRIVER("\n");
1716 i915_file_priv
= (struct drm_i915_file_private
*)
1717 kmalloc(sizeof(*i915_file_priv
), GFP_KERNEL
);
1719 if (!i915_file_priv
)
1722 file_priv
->driver_priv
= i915_file_priv
;
1724 INIT_LIST_HEAD(&i915_file_priv
->mm
.request_list
);
1730 * i915_driver_lastclose - clean up after all DRM clients have exited
1733 * Take care of cleaning up after all DRM clients have exited. In the
1734 * mode setting case, we want to restore the kernel's initial mode (just
1735 * in case the last client left us in a bad state).
1737 * Additionally, in the non-mode setting case, we'll tear down the AGP
1738 * and DMA structures, since the kernel won't be using them, and clea
1741 void i915_driver_lastclose(struct drm_device
* dev
)
1743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1745 if (!dev_priv
|| drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1746 drm_fb_helper_restore();
1750 i915_gem_lastclose(dev
);
1752 if (dev_priv
->agp_heap
)
1753 i915_mem_takedown(&(dev_priv
->agp_heap
));
1755 i915_dma_cleanup(dev
);
1758 void i915_driver_preclose(struct drm_device
* dev
, struct drm_file
*file_priv
)
1760 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1761 i915_gem_release(dev
, file_priv
);
1762 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
1763 i915_mem_release(dev
, file_priv
, dev_priv
->agp_heap
);
1766 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file_priv
)
1768 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
1770 kfree(i915_file_priv
);
1773 struct drm_ioctl_desc i915_ioctls
[] = {
1774 DRM_IOCTL_DEF(DRM_I915_INIT
, i915_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1775 DRM_IOCTL_DEF(DRM_I915_FLUSH
, i915_flush_ioctl
, DRM_AUTH
),
1776 DRM_IOCTL_DEF(DRM_I915_FLIP
, i915_flip_bufs
, DRM_AUTH
),
1777 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER
, i915_batchbuffer
, DRM_AUTH
),
1778 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT
, i915_irq_emit
, DRM_AUTH
),
1779 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT
, i915_irq_wait
, DRM_AUTH
),
1780 DRM_IOCTL_DEF(DRM_I915_GETPARAM
, i915_getparam
, DRM_AUTH
),
1781 DRM_IOCTL_DEF(DRM_I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1782 DRM_IOCTL_DEF(DRM_I915_ALLOC
, i915_mem_alloc
, DRM_AUTH
),
1783 DRM_IOCTL_DEF(DRM_I915_FREE
, i915_mem_free
, DRM_AUTH
),
1784 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP
, i915_mem_init_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1785 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER
, i915_cmdbuffer
, DRM_AUTH
),
1786 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP
, i915_mem_destroy_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1787 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE
, i915_vblank_pipe_set
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1788 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE
, i915_vblank_pipe_get
, DRM_AUTH
),
1789 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP
, i915_vblank_swap
, DRM_AUTH
),
1790 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR
, i915_set_status_page
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1791 DRM_IOCTL_DEF(DRM_I915_GEM_INIT
, i915_gem_init_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1792 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
1793 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
),
1794 DRM_IOCTL_DEF(DRM_I915_GEM_PIN
, i915_gem_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
1795 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN
, i915_gem_unpin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
1796 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
),
1797 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
),
1798 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT
, i915_gem_entervt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1799 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT
, i915_gem_leavevt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1800 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE
, i915_gem_create_ioctl
, 0),
1801 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD
, i915_gem_pread_ioctl
, 0),
1802 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, 0),
1803 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP
, i915_gem_mmap_ioctl
, 0),
1804 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, 0),
1805 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, 0),
1806 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, 0),
1807 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING
, i915_gem_set_tiling
, 0),
1808 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING
, i915_gem_get_tiling
, 0),
1809 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, 0),
1810 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
1811 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, 0),
1812 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
1813 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS
, intel_overlay_attrs
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
1816 int i915_max_ioctl
= DRM_ARRAY_SIZE(i915_ioctls
);
1819 * Determine if the device really is AGP or not.
1821 * All Intel graphics chipsets are treated as AGP, even if they are really
1824 * \param dev The device to be tested.
1827 * A value of 1 is always retured to indictate every i9x5 is AGP.
1829 int i915_driver_device_is_agp(struct drm_device
* dev
)