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Merge branch 'kconfig-text' into release
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "../../../platform/x86/intel_ips.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <acpi/video.h>
45
46 /**
47 * Sets up the hardware status page for devices that need a physical address
48 * in the register.
49 */
50 static int i915_init_phys_hws(struct drm_device *dev)
51 {
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 /* Program Hardware Status Page */
54 dev_priv->status_page_dmah =
55 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
56
57 if (!dev_priv->status_page_dmah) {
58 DRM_ERROR("Can not allocate hardware status page\n");
59 return -ENOMEM;
60 }
61 dev_priv->render_ring.status_page.page_addr
62 = dev_priv->status_page_dmah->vaddr;
63 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
64
65 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
66
67 if (INTEL_INFO(dev)->gen >= 4)
68 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
69 0xf0;
70
71 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
72 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
73 return 0;
74 }
75
76 /**
77 * Frees the hardware status page, whether it's a physical address or a virtual
78 * address set up by the X Server.
79 */
80 static void i915_free_hws(struct drm_device *dev)
81 {
82 drm_i915_private_t *dev_priv = dev->dev_private;
83 if (dev_priv->status_page_dmah) {
84 drm_pci_free(dev, dev_priv->status_page_dmah);
85 dev_priv->status_page_dmah = NULL;
86 }
87
88 if (dev_priv->render_ring.status_page.gfx_addr) {
89 dev_priv->render_ring.status_page.gfx_addr = 0;
90 drm_core_ioremapfree(&dev_priv->hws_map, dev);
91 }
92
93 /* Need to rewrite hardware status page */
94 I915_WRITE(HWS_PGA, 0x1ffff000);
95 }
96
97 void i915_kernel_lost_context(struct drm_device * dev)
98 {
99 drm_i915_private_t *dev_priv = dev->dev_private;
100 struct drm_i915_master_private *master_priv;
101 struct intel_ring_buffer *ring = &dev_priv->render_ring;
102
103 /*
104 * We should never lose context on the ring with modesetting
105 * as we don't expose it to userspace
106 */
107 if (drm_core_check_feature(dev, DRIVER_MODESET))
108 return;
109
110 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
111 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
112 ring->space = ring->head - (ring->tail + 8);
113 if (ring->space < 0)
114 ring->space += ring->size;
115
116 if (!dev->primary->master)
117 return;
118
119 master_priv = dev->primary->master->driver_priv;
120 if (ring->head == ring->tail && master_priv->sarea_priv)
121 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
122 }
123
124 static int i915_dma_cleanup(struct drm_device * dev)
125 {
126 drm_i915_private_t *dev_priv = dev->dev_private;
127 /* Make sure interrupts are disabled here because the uninstall ioctl
128 * may not have been called from userspace and after dev_private
129 * is freed, it's too late.
130 */
131 if (dev->irq_enabled)
132 drm_irq_uninstall(dev);
133
134 mutex_lock(&dev->struct_mutex);
135 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
136 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
137 intel_cleanup_ring_buffer(dev, &dev_priv->blt_ring);
138 mutex_unlock(&dev->struct_mutex);
139
140 /* Clear the HWS virtual address at teardown */
141 if (I915_NEED_GFX_HWS(dev))
142 i915_free_hws(dev);
143
144 return 0;
145 }
146
147 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
148 {
149 drm_i915_private_t *dev_priv = dev->dev_private;
150 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
151
152 master_priv->sarea = drm_getsarea(dev);
153 if (master_priv->sarea) {
154 master_priv->sarea_priv = (drm_i915_sarea_t *)
155 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
156 } else {
157 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
158 }
159
160 if (init->ring_size != 0) {
161 if (dev_priv->render_ring.gem_object != NULL) {
162 i915_dma_cleanup(dev);
163 DRM_ERROR("Client tried to initialize ringbuffer in "
164 "GEM mode\n");
165 return -EINVAL;
166 }
167
168 dev_priv->render_ring.size = init->ring_size;
169
170 dev_priv->render_ring.map.offset = init->ring_start;
171 dev_priv->render_ring.map.size = init->ring_size;
172 dev_priv->render_ring.map.type = 0;
173 dev_priv->render_ring.map.flags = 0;
174 dev_priv->render_ring.map.mtrr = 0;
175
176 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
177
178 if (dev_priv->render_ring.map.handle == NULL) {
179 i915_dma_cleanup(dev);
180 DRM_ERROR("can not ioremap virtual address for"
181 " ring buffer\n");
182 return -ENOMEM;
183 }
184 }
185
186 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
187
188 dev_priv->cpp = init->cpp;
189 dev_priv->back_offset = init->back_offset;
190 dev_priv->front_offset = init->front_offset;
191 dev_priv->current_page = 0;
192 if (master_priv->sarea_priv)
193 master_priv->sarea_priv->pf_current_page = 0;
194
195 /* Allow hardware batchbuffers unless told otherwise.
196 */
197 dev_priv->allow_batchbuffer = 1;
198
199 return 0;
200 }
201
202 static int i915_dma_resume(struct drm_device * dev)
203 {
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
205
206 struct intel_ring_buffer *ring;
207 DRM_DEBUG_DRIVER("%s\n", __func__);
208
209 ring = &dev_priv->render_ring;
210
211 if (ring->map.handle == NULL) {
212 DRM_ERROR("can not ioremap virtual address for"
213 " ring buffer\n");
214 return -ENOMEM;
215 }
216
217 /* Program Hardware Status Page */
218 if (!ring->status_page.page_addr) {
219 DRM_ERROR("Can not find hardware status page\n");
220 return -EINVAL;
221 }
222 DRM_DEBUG_DRIVER("hw status page @ %p\n",
223 ring->status_page.page_addr);
224 if (ring->status_page.gfx_addr != 0)
225 intel_ring_setup_status_page(dev, ring);
226 else
227 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
228
229 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
230
231 return 0;
232 }
233
234 static int i915_dma_init(struct drm_device *dev, void *data,
235 struct drm_file *file_priv)
236 {
237 drm_i915_init_t *init = data;
238 int retcode = 0;
239
240 switch (init->func) {
241 case I915_INIT_DMA:
242 retcode = i915_initialize(dev, init);
243 break;
244 case I915_CLEANUP_DMA:
245 retcode = i915_dma_cleanup(dev);
246 break;
247 case I915_RESUME_DMA:
248 retcode = i915_dma_resume(dev);
249 break;
250 default:
251 retcode = -EINVAL;
252 break;
253 }
254
255 return retcode;
256 }
257
258 /* Implement basically the same security restrictions as hardware does
259 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
260 *
261 * Most of the calculations below involve calculating the size of a
262 * particular instruction. It's important to get the size right as
263 * that tells us where the next instruction to check is. Any illegal
264 * instruction detected will be given a size of zero, which is a
265 * signal to abort the rest of the buffer.
266 */
267 static int do_validate_cmd(int cmd)
268 {
269 switch (((cmd >> 29) & 0x7)) {
270 case 0x0:
271 switch ((cmd >> 23) & 0x3f) {
272 case 0x0:
273 return 1; /* MI_NOOP */
274 case 0x4:
275 return 1; /* MI_FLUSH */
276 default:
277 return 0; /* disallow everything else */
278 }
279 break;
280 case 0x1:
281 return 0; /* reserved */
282 case 0x2:
283 return (cmd & 0xff) + 2; /* 2d commands */
284 case 0x3:
285 if (((cmd >> 24) & 0x1f) <= 0x18)
286 return 1;
287
288 switch ((cmd >> 24) & 0x1f) {
289 case 0x1c:
290 return 1;
291 case 0x1d:
292 switch ((cmd >> 16) & 0xff) {
293 case 0x3:
294 return (cmd & 0x1f) + 2;
295 case 0x4:
296 return (cmd & 0xf) + 2;
297 default:
298 return (cmd & 0xffff) + 2;
299 }
300 case 0x1e:
301 if (cmd & (1 << 23))
302 return (cmd & 0xffff) + 1;
303 else
304 return 1;
305 case 0x1f:
306 if ((cmd & (1 << 23)) == 0) /* inline vertices */
307 return (cmd & 0x1ffff) + 2;
308 else if (cmd & (1 << 17)) /* indirect random */
309 if ((cmd & 0xffff) == 0)
310 return 0; /* unknown length, too hard */
311 else
312 return (((cmd & 0xffff) + 1) / 2) + 1;
313 else
314 return 2; /* indirect sequential */
315 default:
316 return 0;
317 }
318 default:
319 return 0;
320 }
321
322 return 0;
323 }
324
325 static int validate_cmd(int cmd)
326 {
327 int ret = do_validate_cmd(cmd);
328
329 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
330
331 return ret;
332 }
333
334 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
335 {
336 drm_i915_private_t *dev_priv = dev->dev_private;
337 int i;
338
339 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
340 return -EINVAL;
341
342 BEGIN_LP_RING((dwords+1)&~1);
343
344 for (i = 0; i < dwords;) {
345 int cmd, sz;
346
347 cmd = buffer[i];
348
349 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
350 return -EINVAL;
351
352 OUT_RING(cmd);
353
354 while (++i, --sz) {
355 OUT_RING(buffer[i]);
356 }
357 }
358
359 if (dwords & 1)
360 OUT_RING(0);
361
362 ADVANCE_LP_RING();
363
364 return 0;
365 }
366
367 int
368 i915_emit_box(struct drm_device *dev,
369 struct drm_clip_rect *boxes,
370 int i, int DR1, int DR4)
371 {
372 struct drm_clip_rect box = boxes[i];
373
374 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
375 DRM_ERROR("Bad box %d,%d..%d,%d\n",
376 box.x1, box.y1, box.x2, box.y2);
377 return -EINVAL;
378 }
379
380 if (INTEL_INFO(dev)->gen >= 4) {
381 BEGIN_LP_RING(4);
382 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
383 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
384 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
385 OUT_RING(DR4);
386 ADVANCE_LP_RING();
387 } else {
388 BEGIN_LP_RING(6);
389 OUT_RING(GFX_OP_DRAWRECT_INFO);
390 OUT_RING(DR1);
391 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
392 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
393 OUT_RING(DR4);
394 OUT_RING(0);
395 ADVANCE_LP_RING();
396 }
397
398 return 0;
399 }
400
401 /* XXX: Emitting the counter should really be moved to part of the IRQ
402 * emit. For now, do it in both places:
403 */
404
405 static void i915_emit_breadcrumb(struct drm_device *dev)
406 {
407 drm_i915_private_t *dev_priv = dev->dev_private;
408 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
409
410 dev_priv->counter++;
411 if (dev_priv->counter > 0x7FFFFFFFUL)
412 dev_priv->counter = 0;
413 if (master_priv->sarea_priv)
414 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
415
416 BEGIN_LP_RING(4);
417 OUT_RING(MI_STORE_DWORD_INDEX);
418 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
419 OUT_RING(dev_priv->counter);
420 OUT_RING(0);
421 ADVANCE_LP_RING();
422 }
423
424 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
425 drm_i915_cmdbuffer_t *cmd,
426 struct drm_clip_rect *cliprects,
427 void *cmdbuf)
428 {
429 int nbox = cmd->num_cliprects;
430 int i = 0, count, ret;
431
432 if (cmd->sz & 0x3) {
433 DRM_ERROR("alignment");
434 return -EINVAL;
435 }
436
437 i915_kernel_lost_context(dev);
438
439 count = nbox ? nbox : 1;
440
441 for (i = 0; i < count; i++) {
442 if (i < nbox) {
443 ret = i915_emit_box(dev, cliprects, i,
444 cmd->DR1, cmd->DR4);
445 if (ret)
446 return ret;
447 }
448
449 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
450 if (ret)
451 return ret;
452 }
453
454 i915_emit_breadcrumb(dev);
455 return 0;
456 }
457
458 static int i915_dispatch_batchbuffer(struct drm_device * dev,
459 drm_i915_batchbuffer_t * batch,
460 struct drm_clip_rect *cliprects)
461 {
462 int nbox = batch->num_cliprects;
463 int i = 0, count;
464
465 if ((batch->start | batch->used) & 0x7) {
466 DRM_ERROR("alignment");
467 return -EINVAL;
468 }
469
470 i915_kernel_lost_context(dev);
471
472 count = nbox ? nbox : 1;
473
474 for (i = 0; i < count; i++) {
475 if (i < nbox) {
476 int ret = i915_emit_box(dev, cliprects, i,
477 batch->DR1, batch->DR4);
478 if (ret)
479 return ret;
480 }
481
482 if (!IS_I830(dev) && !IS_845G(dev)) {
483 BEGIN_LP_RING(2);
484 if (INTEL_INFO(dev)->gen >= 4) {
485 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
486 OUT_RING(batch->start);
487 } else {
488 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
489 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
490 }
491 ADVANCE_LP_RING();
492 } else {
493 BEGIN_LP_RING(4);
494 OUT_RING(MI_BATCH_BUFFER);
495 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
496 OUT_RING(batch->start + batch->used - 4);
497 OUT_RING(0);
498 ADVANCE_LP_RING();
499 }
500 }
501
502
503 if (IS_G4X(dev) || IS_GEN5(dev)) {
504 BEGIN_LP_RING(2);
505 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
506 OUT_RING(MI_NOOP);
507 ADVANCE_LP_RING();
508 }
509 i915_emit_breadcrumb(dev);
510
511 return 0;
512 }
513
514 static int i915_dispatch_flip(struct drm_device * dev)
515 {
516 drm_i915_private_t *dev_priv = dev->dev_private;
517 struct drm_i915_master_private *master_priv =
518 dev->primary->master->driver_priv;
519
520 if (!master_priv->sarea_priv)
521 return -EINVAL;
522
523 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
524 __func__,
525 dev_priv->current_page,
526 master_priv->sarea_priv->pf_current_page);
527
528 i915_kernel_lost_context(dev);
529
530 BEGIN_LP_RING(2);
531 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
532 OUT_RING(0);
533 ADVANCE_LP_RING();
534
535 BEGIN_LP_RING(6);
536 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
537 OUT_RING(0);
538 if (dev_priv->current_page == 0) {
539 OUT_RING(dev_priv->back_offset);
540 dev_priv->current_page = 1;
541 } else {
542 OUT_RING(dev_priv->front_offset);
543 dev_priv->current_page = 0;
544 }
545 OUT_RING(0);
546 ADVANCE_LP_RING();
547
548 BEGIN_LP_RING(2);
549 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
550 OUT_RING(0);
551 ADVANCE_LP_RING();
552
553 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
554
555 BEGIN_LP_RING(4);
556 OUT_RING(MI_STORE_DWORD_INDEX);
557 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
558 OUT_RING(dev_priv->counter);
559 OUT_RING(0);
560 ADVANCE_LP_RING();
561
562 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
563 return 0;
564 }
565
566 static int i915_quiescent(struct drm_device * dev)
567 {
568 drm_i915_private_t *dev_priv = dev->dev_private;
569
570 i915_kernel_lost_context(dev);
571 return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
572 dev_priv->render_ring.size - 8);
573 }
574
575 static int i915_flush_ioctl(struct drm_device *dev, void *data,
576 struct drm_file *file_priv)
577 {
578 int ret;
579
580 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
581
582 mutex_lock(&dev->struct_mutex);
583 ret = i915_quiescent(dev);
584 mutex_unlock(&dev->struct_mutex);
585
586 return ret;
587 }
588
589 static int i915_batchbuffer(struct drm_device *dev, void *data,
590 struct drm_file *file_priv)
591 {
592 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
593 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
594 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
595 master_priv->sarea_priv;
596 drm_i915_batchbuffer_t *batch = data;
597 int ret;
598 struct drm_clip_rect *cliprects = NULL;
599
600 if (!dev_priv->allow_batchbuffer) {
601 DRM_ERROR("Batchbuffer ioctl disabled\n");
602 return -EINVAL;
603 }
604
605 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
606 batch->start, batch->used, batch->num_cliprects);
607
608 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
609
610 if (batch->num_cliprects < 0)
611 return -EINVAL;
612
613 if (batch->num_cliprects) {
614 cliprects = kcalloc(batch->num_cliprects,
615 sizeof(struct drm_clip_rect),
616 GFP_KERNEL);
617 if (cliprects == NULL)
618 return -ENOMEM;
619
620 ret = copy_from_user(cliprects, batch->cliprects,
621 batch->num_cliprects *
622 sizeof(struct drm_clip_rect));
623 if (ret != 0) {
624 ret = -EFAULT;
625 goto fail_free;
626 }
627 }
628
629 mutex_lock(&dev->struct_mutex);
630 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
631 mutex_unlock(&dev->struct_mutex);
632
633 if (sarea_priv)
634 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
635
636 fail_free:
637 kfree(cliprects);
638
639 return ret;
640 }
641
642 static int i915_cmdbuffer(struct drm_device *dev, void *data,
643 struct drm_file *file_priv)
644 {
645 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
646 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
647 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
648 master_priv->sarea_priv;
649 drm_i915_cmdbuffer_t *cmdbuf = data;
650 struct drm_clip_rect *cliprects = NULL;
651 void *batch_data;
652 int ret;
653
654 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
655 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
656
657 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
658
659 if (cmdbuf->num_cliprects < 0)
660 return -EINVAL;
661
662 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
663 if (batch_data == NULL)
664 return -ENOMEM;
665
666 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
667 if (ret != 0) {
668 ret = -EFAULT;
669 goto fail_batch_free;
670 }
671
672 if (cmdbuf->num_cliprects) {
673 cliprects = kcalloc(cmdbuf->num_cliprects,
674 sizeof(struct drm_clip_rect), GFP_KERNEL);
675 if (cliprects == NULL) {
676 ret = -ENOMEM;
677 goto fail_batch_free;
678 }
679
680 ret = copy_from_user(cliprects, cmdbuf->cliprects,
681 cmdbuf->num_cliprects *
682 sizeof(struct drm_clip_rect));
683 if (ret != 0) {
684 ret = -EFAULT;
685 goto fail_clip_free;
686 }
687 }
688
689 mutex_lock(&dev->struct_mutex);
690 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
691 mutex_unlock(&dev->struct_mutex);
692 if (ret) {
693 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
694 goto fail_clip_free;
695 }
696
697 if (sarea_priv)
698 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
699
700 fail_clip_free:
701 kfree(cliprects);
702 fail_batch_free:
703 kfree(batch_data);
704
705 return ret;
706 }
707
708 static int i915_flip_bufs(struct drm_device *dev, void *data,
709 struct drm_file *file_priv)
710 {
711 int ret;
712
713 DRM_DEBUG_DRIVER("%s\n", __func__);
714
715 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
716
717 mutex_lock(&dev->struct_mutex);
718 ret = i915_dispatch_flip(dev);
719 mutex_unlock(&dev->struct_mutex);
720
721 return ret;
722 }
723
724 static int i915_getparam(struct drm_device *dev, void *data,
725 struct drm_file *file_priv)
726 {
727 drm_i915_private_t *dev_priv = dev->dev_private;
728 drm_i915_getparam_t *param = data;
729 int value;
730
731 if (!dev_priv) {
732 DRM_ERROR("called with no initialization\n");
733 return -EINVAL;
734 }
735
736 switch (param->param) {
737 case I915_PARAM_IRQ_ACTIVE:
738 value = dev->pdev->irq ? 1 : 0;
739 break;
740 case I915_PARAM_ALLOW_BATCHBUFFER:
741 value = dev_priv->allow_batchbuffer ? 1 : 0;
742 break;
743 case I915_PARAM_LAST_DISPATCH:
744 value = READ_BREADCRUMB(dev_priv);
745 break;
746 case I915_PARAM_CHIPSET_ID:
747 value = dev->pci_device;
748 break;
749 case I915_PARAM_HAS_GEM:
750 value = dev_priv->has_gem;
751 break;
752 case I915_PARAM_NUM_FENCES_AVAIL:
753 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
754 break;
755 case I915_PARAM_HAS_OVERLAY:
756 value = dev_priv->overlay ? 1 : 0;
757 break;
758 case I915_PARAM_HAS_PAGEFLIPPING:
759 value = 1;
760 break;
761 case I915_PARAM_HAS_EXECBUF2:
762 /* depends on GEM */
763 value = dev_priv->has_gem;
764 break;
765 case I915_PARAM_HAS_BSD:
766 value = HAS_BSD(dev);
767 break;
768 case I915_PARAM_HAS_BLT:
769 value = HAS_BLT(dev);
770 break;
771 case I915_PARAM_HAS_COHERENT_RINGS:
772 value = 1;
773 break;
774 default:
775 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
776 param->param);
777 return -EINVAL;
778 }
779
780 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
781 DRM_ERROR("DRM_COPY_TO_USER failed\n");
782 return -EFAULT;
783 }
784
785 return 0;
786 }
787
788 static int i915_setparam(struct drm_device *dev, void *data,
789 struct drm_file *file_priv)
790 {
791 drm_i915_private_t *dev_priv = dev->dev_private;
792 drm_i915_setparam_t *param = data;
793
794 if (!dev_priv) {
795 DRM_ERROR("called with no initialization\n");
796 return -EINVAL;
797 }
798
799 switch (param->param) {
800 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
801 break;
802 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
803 dev_priv->tex_lru_log_granularity = param->value;
804 break;
805 case I915_SETPARAM_ALLOW_BATCHBUFFER:
806 dev_priv->allow_batchbuffer = param->value;
807 break;
808 case I915_SETPARAM_NUM_USED_FENCES:
809 if (param->value > dev_priv->num_fence_regs ||
810 param->value < 0)
811 return -EINVAL;
812 /* Userspace can use first N regs */
813 dev_priv->fence_reg_start = param->value;
814 break;
815 default:
816 DRM_DEBUG_DRIVER("unknown parameter %d\n",
817 param->param);
818 return -EINVAL;
819 }
820
821 return 0;
822 }
823
824 static int i915_set_status_page(struct drm_device *dev, void *data,
825 struct drm_file *file_priv)
826 {
827 drm_i915_private_t *dev_priv = dev->dev_private;
828 drm_i915_hws_addr_t *hws = data;
829 struct intel_ring_buffer *ring = &dev_priv->render_ring;
830
831 if (!I915_NEED_GFX_HWS(dev))
832 return -EINVAL;
833
834 if (!dev_priv) {
835 DRM_ERROR("called with no initialization\n");
836 return -EINVAL;
837 }
838
839 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
840 WARN(1, "tried to set status page when mode setting active\n");
841 return 0;
842 }
843
844 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
845
846 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
847
848 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
849 dev_priv->hws_map.size = 4*1024;
850 dev_priv->hws_map.type = 0;
851 dev_priv->hws_map.flags = 0;
852 dev_priv->hws_map.mtrr = 0;
853
854 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
855 if (dev_priv->hws_map.handle == NULL) {
856 i915_dma_cleanup(dev);
857 ring->status_page.gfx_addr = 0;
858 DRM_ERROR("can not ioremap virtual address for"
859 " G33 hw status page\n");
860 return -ENOMEM;
861 }
862 ring->status_page.page_addr = dev_priv->hws_map.handle;
863 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
864 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
865
866 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
867 ring->status_page.gfx_addr);
868 DRM_DEBUG_DRIVER("load hws at %p\n",
869 ring->status_page.page_addr);
870 return 0;
871 }
872
873 static int i915_get_bridge_dev(struct drm_device *dev)
874 {
875 struct drm_i915_private *dev_priv = dev->dev_private;
876
877 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
878 if (!dev_priv->bridge_dev) {
879 DRM_ERROR("bridge device not found\n");
880 return -1;
881 }
882 return 0;
883 }
884
885 #define MCHBAR_I915 0x44
886 #define MCHBAR_I965 0x48
887 #define MCHBAR_SIZE (4*4096)
888
889 #define DEVEN_REG 0x54
890 #define DEVEN_MCHBAR_EN (1 << 28)
891
892 /* Allocate space for the MCH regs if needed, return nonzero on error */
893 static int
894 intel_alloc_mchbar_resource(struct drm_device *dev)
895 {
896 drm_i915_private_t *dev_priv = dev->dev_private;
897 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
898 u32 temp_lo, temp_hi = 0;
899 u64 mchbar_addr;
900 int ret;
901
902 if (INTEL_INFO(dev)->gen >= 4)
903 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
904 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
905 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
906
907 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
908 #ifdef CONFIG_PNP
909 if (mchbar_addr &&
910 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
911 return 0;
912 #endif
913
914 /* Get some space for it */
915 dev_priv->mch_res.name = "i915 MCHBAR";
916 dev_priv->mch_res.flags = IORESOURCE_MEM;
917 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
918 &dev_priv->mch_res,
919 MCHBAR_SIZE, MCHBAR_SIZE,
920 PCIBIOS_MIN_MEM,
921 0, pcibios_align_resource,
922 dev_priv->bridge_dev);
923 if (ret) {
924 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
925 dev_priv->mch_res.start = 0;
926 return ret;
927 }
928
929 if (INTEL_INFO(dev)->gen >= 4)
930 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
931 upper_32_bits(dev_priv->mch_res.start));
932
933 pci_write_config_dword(dev_priv->bridge_dev, reg,
934 lower_32_bits(dev_priv->mch_res.start));
935 return 0;
936 }
937
938 /* Setup MCHBAR if possible, return true if we should disable it again */
939 static void
940 intel_setup_mchbar(struct drm_device *dev)
941 {
942 drm_i915_private_t *dev_priv = dev->dev_private;
943 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
944 u32 temp;
945 bool enabled;
946
947 dev_priv->mchbar_need_disable = false;
948
949 if (IS_I915G(dev) || IS_I915GM(dev)) {
950 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
951 enabled = !!(temp & DEVEN_MCHBAR_EN);
952 } else {
953 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
954 enabled = temp & 1;
955 }
956
957 /* If it's already enabled, don't have to do anything */
958 if (enabled)
959 return;
960
961 if (intel_alloc_mchbar_resource(dev))
962 return;
963
964 dev_priv->mchbar_need_disable = true;
965
966 /* Space is allocated or reserved, so enable it. */
967 if (IS_I915G(dev) || IS_I915GM(dev)) {
968 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
969 temp | DEVEN_MCHBAR_EN);
970 } else {
971 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
972 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
973 }
974 }
975
976 static void
977 intel_teardown_mchbar(struct drm_device *dev)
978 {
979 drm_i915_private_t *dev_priv = dev->dev_private;
980 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
981 u32 temp;
982
983 if (dev_priv->mchbar_need_disable) {
984 if (IS_I915G(dev) || IS_I915GM(dev)) {
985 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
986 temp &= ~DEVEN_MCHBAR_EN;
987 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
988 } else {
989 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
990 temp &= ~1;
991 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
992 }
993 }
994
995 if (dev_priv->mch_res.start)
996 release_resource(&dev_priv->mch_res);
997 }
998
999 #define PTE_ADDRESS_MASK 0xfffff000
1000 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1001 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1002 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1003 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1004 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1005 #define PTE_VALID (1 << 0)
1006
1007 /**
1008 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1009 * @dev: drm device
1010 * @gtt_addr: address to translate
1011 *
1012 * Some chip functions require allocations from stolen space but need the
1013 * physical address of the memory in question. We use this routine
1014 * to get a physical address suitable for register programming from a given
1015 * GTT address.
1016 */
1017 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1018 unsigned long gtt_addr)
1019 {
1020 unsigned long *gtt;
1021 unsigned long entry, phys;
1022 int gtt_bar = IS_GEN2(dev) ? 1 : 0;
1023 int gtt_offset, gtt_size;
1024
1025 if (INTEL_INFO(dev)->gen >= 4) {
1026 if (IS_G4X(dev) || INTEL_INFO(dev)->gen > 4) {
1027 gtt_offset = 2*1024*1024;
1028 gtt_size = 2*1024*1024;
1029 } else {
1030 gtt_offset = 512*1024;
1031 gtt_size = 512*1024;
1032 }
1033 } else {
1034 gtt_bar = 3;
1035 gtt_offset = 0;
1036 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1037 }
1038
1039 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1040 gtt_size);
1041 if (!gtt) {
1042 DRM_ERROR("ioremap of GTT failed\n");
1043 return 0;
1044 }
1045
1046 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1047
1048 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1049
1050 /* Mask out these reserved bits on this hardware. */
1051 if (INTEL_INFO(dev)->gen < 4 && !IS_G33(dev))
1052 entry &= ~PTE_ADDRESS_MASK_HIGH;
1053
1054 /* If it's not a mapping type we know, then bail. */
1055 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1056 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1057 iounmap(gtt);
1058 return 0;
1059 }
1060
1061 if (!(entry & PTE_VALID)) {
1062 DRM_ERROR("bad GTT entry in stolen space\n");
1063 iounmap(gtt);
1064 return 0;
1065 }
1066
1067 iounmap(gtt);
1068
1069 phys =(entry & PTE_ADDRESS_MASK) |
1070 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1071
1072 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1073
1074 return phys;
1075 }
1076
1077 static void i915_warn_stolen(struct drm_device *dev)
1078 {
1079 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1080 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1081 }
1082
1083 static void i915_setup_compression(struct drm_device *dev, int size)
1084 {
1085 struct drm_i915_private *dev_priv = dev->dev_private;
1086 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1087 unsigned long cfb_base;
1088 unsigned long ll_base = 0;
1089
1090 /* Leave 1M for line length buffer & misc. */
1091 compressed_fb = drm_mm_search_free(&dev_priv->mm.vram, size, 4096, 0);
1092 if (!compressed_fb) {
1093 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1094 i915_warn_stolen(dev);
1095 return;
1096 }
1097
1098 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1099 if (!compressed_fb) {
1100 i915_warn_stolen(dev);
1101 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1102 return;
1103 }
1104
1105 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1106 if (!cfb_base) {
1107 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1108 drm_mm_put_block(compressed_fb);
1109 }
1110
1111 if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1112 compressed_llb = drm_mm_search_free(&dev_priv->mm.vram, 4096,
1113 4096, 0);
1114 if (!compressed_llb) {
1115 i915_warn_stolen(dev);
1116 return;
1117 }
1118
1119 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1120 if (!compressed_llb) {
1121 i915_warn_stolen(dev);
1122 return;
1123 }
1124
1125 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1126 if (!ll_base) {
1127 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1128 drm_mm_put_block(compressed_fb);
1129 drm_mm_put_block(compressed_llb);
1130 }
1131 }
1132
1133 dev_priv->cfb_size = size;
1134
1135 intel_disable_fbc(dev);
1136 dev_priv->compressed_fb = compressed_fb;
1137 if (IS_IRONLAKE_M(dev))
1138 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1139 else if (IS_GM45(dev)) {
1140 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1141 } else {
1142 I915_WRITE(FBC_CFB_BASE, cfb_base);
1143 I915_WRITE(FBC_LL_BASE, ll_base);
1144 dev_priv->compressed_llb = compressed_llb;
1145 }
1146
1147 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1148 ll_base, size >> 20);
1149 }
1150
1151 static void i915_cleanup_compression(struct drm_device *dev)
1152 {
1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154
1155 drm_mm_put_block(dev_priv->compressed_fb);
1156 if (dev_priv->compressed_llb)
1157 drm_mm_put_block(dev_priv->compressed_llb);
1158 }
1159
1160 /* true = enable decode, false = disable decoder */
1161 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1162 {
1163 struct drm_device *dev = cookie;
1164
1165 intel_modeset_vga_set_state(dev, state);
1166 if (state)
1167 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1168 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1169 else
1170 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1171 }
1172
1173 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1174 {
1175 struct drm_device *dev = pci_get_drvdata(pdev);
1176 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1177 if (state == VGA_SWITCHEROO_ON) {
1178 printk(KERN_INFO "i915: switched on\n");
1179 /* i915 resume handler doesn't set to D0 */
1180 pci_set_power_state(dev->pdev, PCI_D0);
1181 i915_resume(dev);
1182 } else {
1183 printk(KERN_ERR "i915: switched off\n");
1184 i915_suspend(dev, pmm);
1185 }
1186 }
1187
1188 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1189 {
1190 struct drm_device *dev = pci_get_drvdata(pdev);
1191 bool can_switch;
1192
1193 spin_lock(&dev->count_lock);
1194 can_switch = (dev->open_count == 0);
1195 spin_unlock(&dev->count_lock);
1196 return can_switch;
1197 }
1198
1199 static int i915_load_modeset_init(struct drm_device *dev,
1200 unsigned long prealloc_size,
1201 unsigned long agp_size)
1202 {
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 int ret = 0;
1205
1206 /* Basic memrange allocator for stolen space (aka mm.vram) */
1207 drm_mm_init(&dev_priv->mm.vram, 0, prealloc_size);
1208
1209 /* Let GEM Manage from end of prealloc space to end of aperture.
1210 *
1211 * However, leave one page at the end still bound to the scratch page.
1212 * There are a number of places where the hardware apparently
1213 * prefetches past the end of the object, and we've seen multiple
1214 * hangs with the GPU head pointer stuck in a batchbuffer bound
1215 * at the last page of the aperture. One page should be enough to
1216 * keep any prefetching inside of the aperture.
1217 */
1218 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1219
1220 mutex_lock(&dev->struct_mutex);
1221 ret = i915_gem_init_ringbuffer(dev);
1222 mutex_unlock(&dev->struct_mutex);
1223 if (ret)
1224 goto out;
1225
1226 /* Try to set up FBC with a reasonable compressed buffer size */
1227 if (I915_HAS_FBC(dev) && i915_powersave) {
1228 int cfb_size;
1229
1230 /* Try to get an 8M buffer... */
1231 if (prealloc_size > (9*1024*1024))
1232 cfb_size = 8*1024*1024;
1233 else /* fall back to 7/8 of the stolen space */
1234 cfb_size = prealloc_size * 7 / 8;
1235 i915_setup_compression(dev, cfb_size);
1236 }
1237
1238 /* Allow hardware batchbuffers unless told otherwise.
1239 */
1240 dev_priv->allow_batchbuffer = 1;
1241
1242 ret = intel_parse_bios(dev);
1243 if (ret)
1244 DRM_INFO("failed to find VBIOS tables\n");
1245
1246 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1247 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1248 if (ret)
1249 goto cleanup_ringbuffer;
1250
1251 intel_register_dsm_handler();
1252
1253 ret = vga_switcheroo_register_client(dev->pdev,
1254 i915_switcheroo_set_state,
1255 i915_switcheroo_can_switch);
1256 if (ret)
1257 goto cleanup_vga_client;
1258
1259 /* IIR "flip pending" bit means done if this bit is set */
1260 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1261 dev_priv->flip_pending_is_done = true;
1262
1263 intel_modeset_init(dev);
1264
1265 ret = drm_irq_install(dev);
1266 if (ret)
1267 goto cleanup_vga_switcheroo;
1268
1269 /* Always safe in the mode setting case. */
1270 /* FIXME: do pre/post-mode set stuff in core KMS code */
1271 dev->vblank_disable_allowed = 1;
1272
1273 ret = intel_fbdev_init(dev);
1274 if (ret)
1275 goto cleanup_irq;
1276
1277 drm_kms_helper_poll_init(dev);
1278
1279 /* We're off and running w/KMS */
1280 dev_priv->mm.suspended = 0;
1281
1282 return 0;
1283
1284 cleanup_irq:
1285 drm_irq_uninstall(dev);
1286 cleanup_vga_switcheroo:
1287 vga_switcheroo_unregister_client(dev->pdev);
1288 cleanup_vga_client:
1289 vga_client_register(dev->pdev, NULL, NULL, NULL);
1290 cleanup_ringbuffer:
1291 mutex_lock(&dev->struct_mutex);
1292 i915_gem_cleanup_ringbuffer(dev);
1293 mutex_unlock(&dev->struct_mutex);
1294 out:
1295 return ret;
1296 }
1297
1298 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1299 {
1300 struct drm_i915_master_private *master_priv;
1301
1302 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1303 if (!master_priv)
1304 return -ENOMEM;
1305
1306 master->driver_priv = master_priv;
1307 return 0;
1308 }
1309
1310 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1311 {
1312 struct drm_i915_master_private *master_priv = master->driver_priv;
1313
1314 if (!master_priv)
1315 return;
1316
1317 kfree(master_priv);
1318
1319 master->driver_priv = NULL;
1320 }
1321
1322 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1323 {
1324 drm_i915_private_t *dev_priv = dev->dev_private;
1325 u32 tmp;
1326
1327 tmp = I915_READ(CLKCFG);
1328
1329 switch (tmp & CLKCFG_FSB_MASK) {
1330 case CLKCFG_FSB_533:
1331 dev_priv->fsb_freq = 533; /* 133*4 */
1332 break;
1333 case CLKCFG_FSB_800:
1334 dev_priv->fsb_freq = 800; /* 200*4 */
1335 break;
1336 case CLKCFG_FSB_667:
1337 dev_priv->fsb_freq = 667; /* 167*4 */
1338 break;
1339 case CLKCFG_FSB_400:
1340 dev_priv->fsb_freq = 400; /* 100*4 */
1341 break;
1342 }
1343
1344 switch (tmp & CLKCFG_MEM_MASK) {
1345 case CLKCFG_MEM_533:
1346 dev_priv->mem_freq = 533;
1347 break;
1348 case CLKCFG_MEM_667:
1349 dev_priv->mem_freq = 667;
1350 break;
1351 case CLKCFG_MEM_800:
1352 dev_priv->mem_freq = 800;
1353 break;
1354 }
1355
1356 /* detect pineview DDR3 setting */
1357 tmp = I915_READ(CSHRDDR3CTL);
1358 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1359 }
1360
1361 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1362 {
1363 drm_i915_private_t *dev_priv = dev->dev_private;
1364 u16 ddrpll, csipll;
1365
1366 ddrpll = I915_READ16(DDRMPLL1);
1367 csipll = I915_READ16(CSIPLL0);
1368
1369 switch (ddrpll & 0xff) {
1370 case 0xc:
1371 dev_priv->mem_freq = 800;
1372 break;
1373 case 0x10:
1374 dev_priv->mem_freq = 1066;
1375 break;
1376 case 0x14:
1377 dev_priv->mem_freq = 1333;
1378 break;
1379 case 0x18:
1380 dev_priv->mem_freq = 1600;
1381 break;
1382 default:
1383 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1384 ddrpll & 0xff);
1385 dev_priv->mem_freq = 0;
1386 break;
1387 }
1388
1389 dev_priv->r_t = dev_priv->mem_freq;
1390
1391 switch (csipll & 0x3ff) {
1392 case 0x00c:
1393 dev_priv->fsb_freq = 3200;
1394 break;
1395 case 0x00e:
1396 dev_priv->fsb_freq = 3733;
1397 break;
1398 case 0x010:
1399 dev_priv->fsb_freq = 4266;
1400 break;
1401 case 0x012:
1402 dev_priv->fsb_freq = 4800;
1403 break;
1404 case 0x014:
1405 dev_priv->fsb_freq = 5333;
1406 break;
1407 case 0x016:
1408 dev_priv->fsb_freq = 5866;
1409 break;
1410 case 0x018:
1411 dev_priv->fsb_freq = 6400;
1412 break;
1413 default:
1414 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1415 csipll & 0x3ff);
1416 dev_priv->fsb_freq = 0;
1417 break;
1418 }
1419
1420 if (dev_priv->fsb_freq == 3200) {
1421 dev_priv->c_m = 0;
1422 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1423 dev_priv->c_m = 1;
1424 } else {
1425 dev_priv->c_m = 2;
1426 }
1427 }
1428
1429 struct v_table {
1430 u8 vid;
1431 unsigned long vd; /* in .1 mil */
1432 unsigned long vm; /* in .1 mil */
1433 u8 pvid;
1434 };
1435
1436 static struct v_table v_table[] = {
1437 { 0, 16125, 15000, 0x7f, },
1438 { 1, 16000, 14875, 0x7e, },
1439 { 2, 15875, 14750, 0x7d, },
1440 { 3, 15750, 14625, 0x7c, },
1441 { 4, 15625, 14500, 0x7b, },
1442 { 5, 15500, 14375, 0x7a, },
1443 { 6, 15375, 14250, 0x79, },
1444 { 7, 15250, 14125, 0x78, },
1445 { 8, 15125, 14000, 0x77, },
1446 { 9, 15000, 13875, 0x76, },
1447 { 10, 14875, 13750, 0x75, },
1448 { 11, 14750, 13625, 0x74, },
1449 { 12, 14625, 13500, 0x73, },
1450 { 13, 14500, 13375, 0x72, },
1451 { 14, 14375, 13250, 0x71, },
1452 { 15, 14250, 13125, 0x70, },
1453 { 16, 14125, 13000, 0x6f, },
1454 { 17, 14000, 12875, 0x6e, },
1455 { 18, 13875, 12750, 0x6d, },
1456 { 19, 13750, 12625, 0x6c, },
1457 { 20, 13625, 12500, 0x6b, },
1458 { 21, 13500, 12375, 0x6a, },
1459 { 22, 13375, 12250, 0x69, },
1460 { 23, 13250, 12125, 0x68, },
1461 { 24, 13125, 12000, 0x67, },
1462 { 25, 13000, 11875, 0x66, },
1463 { 26, 12875, 11750, 0x65, },
1464 { 27, 12750, 11625, 0x64, },
1465 { 28, 12625, 11500, 0x63, },
1466 { 29, 12500, 11375, 0x62, },
1467 { 30, 12375, 11250, 0x61, },
1468 { 31, 12250, 11125, 0x60, },
1469 { 32, 12125, 11000, 0x5f, },
1470 { 33, 12000, 10875, 0x5e, },
1471 { 34, 11875, 10750, 0x5d, },
1472 { 35, 11750, 10625, 0x5c, },
1473 { 36, 11625, 10500, 0x5b, },
1474 { 37, 11500, 10375, 0x5a, },
1475 { 38, 11375, 10250, 0x59, },
1476 { 39, 11250, 10125, 0x58, },
1477 { 40, 11125, 10000, 0x57, },
1478 { 41, 11000, 9875, 0x56, },
1479 { 42, 10875, 9750, 0x55, },
1480 { 43, 10750, 9625, 0x54, },
1481 { 44, 10625, 9500, 0x53, },
1482 { 45, 10500, 9375, 0x52, },
1483 { 46, 10375, 9250, 0x51, },
1484 { 47, 10250, 9125, 0x50, },
1485 { 48, 10125, 9000, 0x4f, },
1486 { 49, 10000, 8875, 0x4e, },
1487 { 50, 9875, 8750, 0x4d, },
1488 { 51, 9750, 8625, 0x4c, },
1489 { 52, 9625, 8500, 0x4b, },
1490 { 53, 9500, 8375, 0x4a, },
1491 { 54, 9375, 8250, 0x49, },
1492 { 55, 9250, 8125, 0x48, },
1493 { 56, 9125, 8000, 0x47, },
1494 { 57, 9000, 7875, 0x46, },
1495 { 58, 8875, 7750, 0x45, },
1496 { 59, 8750, 7625, 0x44, },
1497 { 60, 8625, 7500, 0x43, },
1498 { 61, 8500, 7375, 0x42, },
1499 { 62, 8375, 7250, 0x41, },
1500 { 63, 8250, 7125, 0x40, },
1501 { 64, 8125, 7000, 0x3f, },
1502 { 65, 8000, 6875, 0x3e, },
1503 { 66, 7875, 6750, 0x3d, },
1504 { 67, 7750, 6625, 0x3c, },
1505 { 68, 7625, 6500, 0x3b, },
1506 { 69, 7500, 6375, 0x3a, },
1507 { 70, 7375, 6250, 0x39, },
1508 { 71, 7250, 6125, 0x38, },
1509 { 72, 7125, 6000, 0x37, },
1510 { 73, 7000, 5875, 0x36, },
1511 { 74, 6875, 5750, 0x35, },
1512 { 75, 6750, 5625, 0x34, },
1513 { 76, 6625, 5500, 0x33, },
1514 { 77, 6500, 5375, 0x32, },
1515 { 78, 6375, 5250, 0x31, },
1516 { 79, 6250, 5125, 0x30, },
1517 { 80, 6125, 5000, 0x2f, },
1518 { 81, 6000, 4875, 0x2e, },
1519 { 82, 5875, 4750, 0x2d, },
1520 { 83, 5750, 4625, 0x2c, },
1521 { 84, 5625, 4500, 0x2b, },
1522 { 85, 5500, 4375, 0x2a, },
1523 { 86, 5375, 4250, 0x29, },
1524 { 87, 5250, 4125, 0x28, },
1525 { 88, 5125, 4000, 0x27, },
1526 { 89, 5000, 3875, 0x26, },
1527 { 90, 4875, 3750, 0x25, },
1528 { 91, 4750, 3625, 0x24, },
1529 { 92, 4625, 3500, 0x23, },
1530 { 93, 4500, 3375, 0x22, },
1531 { 94, 4375, 3250, 0x21, },
1532 { 95, 4250, 3125, 0x20, },
1533 { 96, 4125, 3000, 0x1f, },
1534 { 97, 4125, 3000, 0x1e, },
1535 { 98, 4125, 3000, 0x1d, },
1536 { 99, 4125, 3000, 0x1c, },
1537 { 100, 4125, 3000, 0x1b, },
1538 { 101, 4125, 3000, 0x1a, },
1539 { 102, 4125, 3000, 0x19, },
1540 { 103, 4125, 3000, 0x18, },
1541 { 104, 4125, 3000, 0x17, },
1542 { 105, 4125, 3000, 0x16, },
1543 { 106, 4125, 3000, 0x15, },
1544 { 107, 4125, 3000, 0x14, },
1545 { 108, 4125, 3000, 0x13, },
1546 { 109, 4125, 3000, 0x12, },
1547 { 110, 4125, 3000, 0x11, },
1548 { 111, 4125, 3000, 0x10, },
1549 { 112, 4125, 3000, 0x0f, },
1550 { 113, 4125, 3000, 0x0e, },
1551 { 114, 4125, 3000, 0x0d, },
1552 { 115, 4125, 3000, 0x0c, },
1553 { 116, 4125, 3000, 0x0b, },
1554 { 117, 4125, 3000, 0x0a, },
1555 { 118, 4125, 3000, 0x09, },
1556 { 119, 4125, 3000, 0x08, },
1557 { 120, 1125, 0, 0x07, },
1558 { 121, 1000, 0, 0x06, },
1559 { 122, 875, 0, 0x05, },
1560 { 123, 750, 0, 0x04, },
1561 { 124, 625, 0, 0x03, },
1562 { 125, 500, 0, 0x02, },
1563 { 126, 375, 0, 0x01, },
1564 { 127, 0, 0, 0x00, },
1565 };
1566
1567 struct cparams {
1568 int i;
1569 int t;
1570 int m;
1571 int c;
1572 };
1573
1574 static struct cparams cparams[] = {
1575 { 1, 1333, 301, 28664 },
1576 { 1, 1066, 294, 24460 },
1577 { 1, 800, 294, 25192 },
1578 { 0, 1333, 276, 27605 },
1579 { 0, 1066, 276, 27605 },
1580 { 0, 800, 231, 23784 },
1581 };
1582
1583 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1584 {
1585 u64 total_count, diff, ret;
1586 u32 count1, count2, count3, m = 0, c = 0;
1587 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1588 int i;
1589
1590 diff1 = now - dev_priv->last_time1;
1591
1592 count1 = I915_READ(DMIEC);
1593 count2 = I915_READ(DDREC);
1594 count3 = I915_READ(CSIEC);
1595
1596 total_count = count1 + count2 + count3;
1597
1598 /* FIXME: handle per-counter overflow */
1599 if (total_count < dev_priv->last_count1) {
1600 diff = ~0UL - dev_priv->last_count1;
1601 diff += total_count;
1602 } else {
1603 diff = total_count - dev_priv->last_count1;
1604 }
1605
1606 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1607 if (cparams[i].i == dev_priv->c_m &&
1608 cparams[i].t == dev_priv->r_t) {
1609 m = cparams[i].m;
1610 c = cparams[i].c;
1611 break;
1612 }
1613 }
1614
1615 diff = div_u64(diff, diff1);
1616 ret = ((m * diff) + c);
1617 ret = div_u64(ret, 10);
1618
1619 dev_priv->last_count1 = total_count;
1620 dev_priv->last_time1 = now;
1621
1622 return ret;
1623 }
1624
1625 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1626 {
1627 unsigned long m, x, b;
1628 u32 tsfs;
1629
1630 tsfs = I915_READ(TSFS);
1631
1632 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1633 x = I915_READ8(TR1);
1634
1635 b = tsfs & TSFS_INTR_MASK;
1636
1637 return ((m * x) / 127) - b;
1638 }
1639
1640 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1641 {
1642 unsigned long val = 0;
1643 int i;
1644
1645 for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1646 if (v_table[i].pvid == pxvid) {
1647 if (IS_MOBILE(dev_priv->dev))
1648 val = v_table[i].vm;
1649 else
1650 val = v_table[i].vd;
1651 }
1652 }
1653
1654 return val;
1655 }
1656
1657 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1658 {
1659 struct timespec now, diff1;
1660 u64 diff;
1661 unsigned long diffms;
1662 u32 count;
1663
1664 getrawmonotonic(&now);
1665 diff1 = timespec_sub(now, dev_priv->last_time2);
1666
1667 /* Don't divide by 0 */
1668 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1669 if (!diffms)
1670 return;
1671
1672 count = I915_READ(GFXEC);
1673
1674 if (count < dev_priv->last_count2) {
1675 diff = ~0UL - dev_priv->last_count2;
1676 diff += count;
1677 } else {
1678 diff = count - dev_priv->last_count2;
1679 }
1680
1681 dev_priv->last_count2 = count;
1682 dev_priv->last_time2 = now;
1683
1684 /* More magic constants... */
1685 diff = diff * 1181;
1686 diff = div_u64(diff, diffms * 10);
1687 dev_priv->gfx_power = diff;
1688 }
1689
1690 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1691 {
1692 unsigned long t, corr, state1, corr2, state2;
1693 u32 pxvid, ext_v;
1694
1695 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1696 pxvid = (pxvid >> 24) & 0x7f;
1697 ext_v = pvid_to_extvid(dev_priv, pxvid);
1698
1699 state1 = ext_v;
1700
1701 t = i915_mch_val(dev_priv);
1702
1703 /* Revel in the empirically derived constants */
1704
1705 /* Correction factor in 1/100000 units */
1706 if (t > 80)
1707 corr = ((t * 2349) + 135940);
1708 else if (t >= 50)
1709 corr = ((t * 964) + 29317);
1710 else /* < 50 */
1711 corr = ((t * 301) + 1004);
1712
1713 corr = corr * ((150142 * state1) / 10000 - 78642);
1714 corr /= 100000;
1715 corr2 = (corr * dev_priv->corr);
1716
1717 state2 = (corr2 * state1) / 10000;
1718 state2 /= 100; /* convert to mW */
1719
1720 i915_update_gfx_val(dev_priv);
1721
1722 return dev_priv->gfx_power + state2;
1723 }
1724
1725 /* Global for IPS driver to get at the current i915 device */
1726 static struct drm_i915_private *i915_mch_dev;
1727 /*
1728 * Lock protecting IPS related data structures
1729 * - i915_mch_dev
1730 * - dev_priv->max_delay
1731 * - dev_priv->min_delay
1732 * - dev_priv->fmax
1733 * - dev_priv->gpu_busy
1734 */
1735 static DEFINE_SPINLOCK(mchdev_lock);
1736
1737 /**
1738 * i915_read_mch_val - return value for IPS use
1739 *
1740 * Calculate and return a value for the IPS driver to use when deciding whether
1741 * we have thermal and power headroom to increase CPU or GPU power budget.
1742 */
1743 unsigned long i915_read_mch_val(void)
1744 {
1745 struct drm_i915_private *dev_priv;
1746 unsigned long chipset_val, graphics_val, ret = 0;
1747
1748 spin_lock(&mchdev_lock);
1749 if (!i915_mch_dev)
1750 goto out_unlock;
1751 dev_priv = i915_mch_dev;
1752
1753 chipset_val = i915_chipset_val(dev_priv);
1754 graphics_val = i915_gfx_val(dev_priv);
1755
1756 ret = chipset_val + graphics_val;
1757
1758 out_unlock:
1759 spin_unlock(&mchdev_lock);
1760
1761 return ret;
1762 }
1763 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1764
1765 /**
1766 * i915_gpu_raise - raise GPU frequency limit
1767 *
1768 * Raise the limit; IPS indicates we have thermal headroom.
1769 */
1770 bool i915_gpu_raise(void)
1771 {
1772 struct drm_i915_private *dev_priv;
1773 bool ret = true;
1774
1775 spin_lock(&mchdev_lock);
1776 if (!i915_mch_dev) {
1777 ret = false;
1778 goto out_unlock;
1779 }
1780 dev_priv = i915_mch_dev;
1781
1782 if (dev_priv->max_delay > dev_priv->fmax)
1783 dev_priv->max_delay--;
1784
1785 out_unlock:
1786 spin_unlock(&mchdev_lock);
1787
1788 return ret;
1789 }
1790 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1791
1792 /**
1793 * i915_gpu_lower - lower GPU frequency limit
1794 *
1795 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1796 * frequency maximum.
1797 */
1798 bool i915_gpu_lower(void)
1799 {
1800 struct drm_i915_private *dev_priv;
1801 bool ret = true;
1802
1803 spin_lock(&mchdev_lock);
1804 if (!i915_mch_dev) {
1805 ret = false;
1806 goto out_unlock;
1807 }
1808 dev_priv = i915_mch_dev;
1809
1810 if (dev_priv->max_delay < dev_priv->min_delay)
1811 dev_priv->max_delay++;
1812
1813 out_unlock:
1814 spin_unlock(&mchdev_lock);
1815
1816 return ret;
1817 }
1818 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1819
1820 /**
1821 * i915_gpu_busy - indicate GPU business to IPS
1822 *
1823 * Tell the IPS driver whether or not the GPU is busy.
1824 */
1825 bool i915_gpu_busy(void)
1826 {
1827 struct drm_i915_private *dev_priv;
1828 bool ret = false;
1829
1830 spin_lock(&mchdev_lock);
1831 if (!i915_mch_dev)
1832 goto out_unlock;
1833 dev_priv = i915_mch_dev;
1834
1835 ret = dev_priv->busy;
1836
1837 out_unlock:
1838 spin_unlock(&mchdev_lock);
1839
1840 return ret;
1841 }
1842 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1843
1844 /**
1845 * i915_gpu_turbo_disable - disable graphics turbo
1846 *
1847 * Disable graphics turbo by resetting the max frequency and setting the
1848 * current frequency to the default.
1849 */
1850 bool i915_gpu_turbo_disable(void)
1851 {
1852 struct drm_i915_private *dev_priv;
1853 bool ret = true;
1854
1855 spin_lock(&mchdev_lock);
1856 if (!i915_mch_dev) {
1857 ret = false;
1858 goto out_unlock;
1859 }
1860 dev_priv = i915_mch_dev;
1861
1862 dev_priv->max_delay = dev_priv->fstart;
1863
1864 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1865 ret = false;
1866
1867 out_unlock:
1868 spin_unlock(&mchdev_lock);
1869
1870 return ret;
1871 }
1872 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1873
1874 /**
1875 * Tells the intel_ips driver that the i915 driver is now loaded, if
1876 * IPS got loaded first.
1877 *
1878 * This awkward dance is so that neither module has to depend on the
1879 * other in order for IPS to do the appropriate communication of
1880 * GPU turbo limits to i915.
1881 */
1882 static void
1883 ips_ping_for_i915_load(void)
1884 {
1885 void (*link)(void);
1886
1887 link = symbol_get(ips_link_to_i915_driver);
1888 if (link) {
1889 link();
1890 symbol_put(ips_link_to_i915_driver);
1891 }
1892 }
1893
1894 /**
1895 * i915_driver_load - setup chip and create an initial config
1896 * @dev: DRM device
1897 * @flags: startup flags
1898 *
1899 * The driver load routine has to do several things:
1900 * - drive output discovery via intel_modeset_init()
1901 * - initialize the memory manager
1902 * - allocate initial config memory
1903 * - setup the DRM framebuffer with the allocated memory
1904 */
1905 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1906 {
1907 struct drm_i915_private *dev_priv;
1908 resource_size_t base, size;
1909 int ret = 0, mmio_bar;
1910 uint32_t agp_size, prealloc_size;
1911 /* i915 has 4 more counters */
1912 dev->counters += 4;
1913 dev->types[6] = _DRM_STAT_IRQ;
1914 dev->types[7] = _DRM_STAT_PRIMARY;
1915 dev->types[8] = _DRM_STAT_SECONDARY;
1916 dev->types[9] = _DRM_STAT_DMA;
1917
1918 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1919 if (dev_priv == NULL)
1920 return -ENOMEM;
1921
1922 dev->dev_private = (void *)dev_priv;
1923 dev_priv->dev = dev;
1924 dev_priv->info = (struct intel_device_info *) flags;
1925
1926 /* Add register map (needed for suspend/resume) */
1927 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1928 base = pci_resource_start(dev->pdev, mmio_bar);
1929 size = pci_resource_len(dev->pdev, mmio_bar);
1930
1931 if (i915_get_bridge_dev(dev)) {
1932 ret = -EIO;
1933 goto free_priv;
1934 }
1935
1936 /* overlay on gen2 is broken and can't address above 1G */
1937 if (IS_GEN2(dev))
1938 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1939
1940 dev_priv->regs = ioremap(base, size);
1941 if (!dev_priv->regs) {
1942 DRM_ERROR("failed to map registers\n");
1943 ret = -EIO;
1944 goto put_bridge;
1945 }
1946
1947 dev_priv->mm.gtt_mapping =
1948 io_mapping_create_wc(dev->agp->base,
1949 dev->agp->agp_info.aper_size * 1024*1024);
1950 if (dev_priv->mm.gtt_mapping == NULL) {
1951 ret = -EIO;
1952 goto out_rmmap;
1953 }
1954
1955 /* Set up a WC MTRR for non-PAT systems. This is more common than
1956 * one would think, because the kernel disables PAT on first
1957 * generation Core chips because WC PAT gets overridden by a UC
1958 * MTRR if present. Even if a UC MTRR isn't present.
1959 */
1960 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1961 dev->agp->agp_info.aper_size *
1962 1024 * 1024,
1963 MTRR_TYPE_WRCOMB, 1);
1964 if (dev_priv->mm.gtt_mtrr < 0) {
1965 DRM_INFO("MTRR allocation failed. Graphics "
1966 "performance may suffer.\n");
1967 }
1968
1969 dev_priv->mm.gtt = intel_gtt_get();
1970 if (!dev_priv->mm.gtt) {
1971 DRM_ERROR("Failed to initialize GTT\n");
1972 ret = -ENODEV;
1973 goto out_iomapfree;
1974 }
1975
1976 prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT;
1977 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1978
1979 /* The i915 workqueue is primarily used for batched retirement of
1980 * requests (and thus managing bo) once the task has been completed
1981 * by the GPU. i915_gem_retire_requests() is called directly when we
1982 * need high-priority retirement, such as waiting for an explicit
1983 * bo.
1984 *
1985 * It is also used for periodic low-priority events, such as
1986 * idle-timers and hangcheck.
1987 *
1988 * All tasks on the workqueue are expected to acquire the dev mutex
1989 * so there is no point in running more than one instance of the
1990 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1991 */
1992 dev_priv->wq = alloc_workqueue("i915",
1993 WQ_UNBOUND | WQ_NON_REENTRANT,
1994 1);
1995 if (dev_priv->wq == NULL) {
1996 DRM_ERROR("Failed to create our workqueue.\n");
1997 ret = -ENOMEM;
1998 goto out_iomapfree;
1999 }
2000
2001 /* enable GEM by default */
2002 dev_priv->has_gem = 1;
2003
2004 if (prealloc_size > agp_size * 3 / 4) {
2005 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2006 "memory stolen.\n",
2007 prealloc_size / 1024, agp_size / 1024);
2008 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2009 "updating the BIOS to fix).\n");
2010 dev_priv->has_gem = 0;
2011 }
2012
2013 if (dev_priv->has_gem == 0 &&
2014 drm_core_check_feature(dev, DRIVER_MODESET)) {
2015 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2016 ret = -ENODEV;
2017 goto out_iomapfree;
2018 }
2019
2020 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2021 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2022 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
2023 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2024 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2025 }
2026
2027 /* Try to make sure MCHBAR is enabled before poking at it */
2028 intel_setup_mchbar(dev);
2029 intel_setup_gmbus(dev);
2030 intel_opregion_setup(dev);
2031
2032 /* Make sure the bios did its job and set up vital registers */
2033 intel_setup_bios(dev);
2034
2035 i915_gem_load(dev);
2036
2037 /* Init HWS */
2038 if (!I915_NEED_GFX_HWS(dev)) {
2039 ret = i915_init_phys_hws(dev);
2040 if (ret != 0)
2041 goto out_workqueue_free;
2042 }
2043
2044 if (IS_PINEVIEW(dev))
2045 i915_pineview_get_mem_freq(dev);
2046 else if (IS_GEN5(dev))
2047 i915_ironlake_get_mem_freq(dev);
2048
2049 /* On the 945G/GM, the chipset reports the MSI capability on the
2050 * integrated graphics even though the support isn't actually there
2051 * according to the published specs. It doesn't appear to function
2052 * correctly in testing on 945G.
2053 * This may be a side effect of MSI having been made available for PEG
2054 * and the registers being closely associated.
2055 *
2056 * According to chipset errata, on the 965GM, MSI interrupts may
2057 * be lost or delayed, but we use them anyways to avoid
2058 * stuck interrupts on some machines.
2059 */
2060 if (!IS_I945G(dev) && !IS_I945GM(dev))
2061 pci_enable_msi(dev->pdev);
2062
2063 spin_lock_init(&dev_priv->user_irq_lock);
2064 spin_lock_init(&dev_priv->error_lock);
2065 dev_priv->trace_irq_seqno = 0;
2066
2067 ret = drm_vblank_init(dev, I915_NUM_PIPE);
2068
2069 if (ret) {
2070 (void) i915_driver_unload(dev);
2071 return ret;
2072 }
2073
2074 /* Start out suspended */
2075 dev_priv->mm.suspended = 1;
2076
2077 intel_detect_pch(dev);
2078
2079 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2080 ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
2081 if (ret < 0) {
2082 DRM_ERROR("failed to init modeset\n");
2083 goto out_workqueue_free;
2084 }
2085 }
2086
2087 /* Must be done after probing outputs */
2088 intel_opregion_init(dev);
2089 acpi_video_register();
2090
2091 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2092 (unsigned long) dev);
2093
2094 spin_lock(&mchdev_lock);
2095 i915_mch_dev = dev_priv;
2096 dev_priv->mchdev_lock = &mchdev_lock;
2097 spin_unlock(&mchdev_lock);
2098
2099 ips_ping_for_i915_load();
2100
2101 return 0;
2102
2103 out_workqueue_free:
2104 destroy_workqueue(dev_priv->wq);
2105 out_iomapfree:
2106 io_mapping_free(dev_priv->mm.gtt_mapping);
2107 out_rmmap:
2108 iounmap(dev_priv->regs);
2109 put_bridge:
2110 pci_dev_put(dev_priv->bridge_dev);
2111 free_priv:
2112 kfree(dev_priv);
2113 return ret;
2114 }
2115
2116 int i915_driver_unload(struct drm_device *dev)
2117 {
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119 int ret;
2120
2121 spin_lock(&mchdev_lock);
2122 i915_mch_dev = NULL;
2123 spin_unlock(&mchdev_lock);
2124
2125 mutex_lock(&dev->struct_mutex);
2126 ret = i915_gpu_idle(dev);
2127 if (ret)
2128 DRM_ERROR("failed to idle hardware: %d\n", ret);
2129 mutex_unlock(&dev->struct_mutex);
2130
2131 /* Cancel the retire work handler, which should be idle now. */
2132 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2133
2134 io_mapping_free(dev_priv->mm.gtt_mapping);
2135 if (dev_priv->mm.gtt_mtrr >= 0) {
2136 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2137 dev->agp->agp_info.aper_size * 1024 * 1024);
2138 dev_priv->mm.gtt_mtrr = -1;
2139 }
2140
2141 acpi_video_unregister();
2142
2143 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2144 intel_fbdev_fini(dev);
2145 intel_modeset_cleanup(dev);
2146
2147 /*
2148 * free the memory space allocated for the child device
2149 * config parsed from VBT
2150 */
2151 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2152 kfree(dev_priv->child_dev);
2153 dev_priv->child_dev = NULL;
2154 dev_priv->child_dev_num = 0;
2155 }
2156
2157 vga_switcheroo_unregister_client(dev->pdev);
2158 vga_client_register(dev->pdev, NULL, NULL, NULL);
2159 }
2160
2161 /* Free error state after interrupts are fully disabled. */
2162 del_timer_sync(&dev_priv->hangcheck_timer);
2163 cancel_work_sync(&dev_priv->error_work);
2164 i915_destroy_error_state(dev);
2165
2166 if (dev->pdev->msi_enabled)
2167 pci_disable_msi(dev->pdev);
2168
2169 intel_opregion_fini(dev);
2170
2171 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2172 /* Flush any outstanding unpin_work. */
2173 flush_workqueue(dev_priv->wq);
2174
2175 i915_gem_free_all_phys_object(dev);
2176
2177 mutex_lock(&dev->struct_mutex);
2178 i915_gem_cleanup_ringbuffer(dev);
2179 mutex_unlock(&dev->struct_mutex);
2180 if (I915_HAS_FBC(dev) && i915_powersave)
2181 i915_cleanup_compression(dev);
2182 drm_mm_takedown(&dev_priv->mm.vram);
2183
2184 intel_cleanup_overlay(dev);
2185
2186 if (!I915_NEED_GFX_HWS(dev))
2187 i915_free_hws(dev);
2188 }
2189
2190 if (dev_priv->regs != NULL)
2191 iounmap(dev_priv->regs);
2192
2193 intel_teardown_gmbus(dev);
2194 intel_teardown_mchbar(dev);
2195
2196 destroy_workqueue(dev_priv->wq);
2197
2198 pci_dev_put(dev_priv->bridge_dev);
2199 kfree(dev->dev_private);
2200
2201 return 0;
2202 }
2203
2204 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2205 {
2206 struct drm_i915_file_private *file_priv;
2207
2208 DRM_DEBUG_DRIVER("\n");
2209 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2210 if (!file_priv)
2211 return -ENOMEM;
2212
2213 file->driver_priv = file_priv;
2214
2215 spin_lock_init(&file_priv->mm.lock);
2216 INIT_LIST_HEAD(&file_priv->mm.request_list);
2217
2218 return 0;
2219 }
2220
2221 /**
2222 * i915_driver_lastclose - clean up after all DRM clients have exited
2223 * @dev: DRM device
2224 *
2225 * Take care of cleaning up after all DRM clients have exited. In the
2226 * mode setting case, we want to restore the kernel's initial mode (just
2227 * in case the last client left us in a bad state).
2228 *
2229 * Additionally, in the non-mode setting case, we'll tear down the AGP
2230 * and DMA structures, since the kernel won't be using them, and clea
2231 * up any GEM state.
2232 */
2233 void i915_driver_lastclose(struct drm_device * dev)
2234 {
2235 drm_i915_private_t *dev_priv = dev->dev_private;
2236
2237 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2238 drm_fb_helper_restore();
2239 vga_switcheroo_process_delayed_switch();
2240 return;
2241 }
2242
2243 i915_gem_lastclose(dev);
2244
2245 if (dev_priv->agp_heap)
2246 i915_mem_takedown(&(dev_priv->agp_heap));
2247
2248 i915_dma_cleanup(dev);
2249 }
2250
2251 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2252 {
2253 drm_i915_private_t *dev_priv = dev->dev_private;
2254 i915_gem_release(dev, file_priv);
2255 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2256 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2257 }
2258
2259 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2260 {
2261 struct drm_i915_file_private *file_priv = file->driver_priv;
2262
2263 kfree(file_priv);
2264 }
2265
2266 struct drm_ioctl_desc i915_ioctls[] = {
2267 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2268 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2269 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2270 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2271 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2272 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2273 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2274 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2275 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2276 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2277 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2278 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2279 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2280 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2281 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2282 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2283 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2284 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2285 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2286 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2287 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2288 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2289 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2290 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2291 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2292 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2293 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2294 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2295 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2296 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2297 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2298 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2299 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2300 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2301 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2302 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2303 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2304 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2305 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2306 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2307 };
2308
2309 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2310
2311 /**
2312 * Determine if the device really is AGP or not.
2313 *
2314 * All Intel graphics chipsets are treated as AGP, even if they are really
2315 * PCI-e.
2316 *
2317 * \param dev The device to be tested.
2318 *
2319 * \returns
2320 * A value of 1 is always retured to indictate every i9x5 is AGP.
2321 */
2322 int i915_driver_device_is_agp(struct drm_device * dev)
2323 {
2324 return 1;
2325 }
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