1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver
;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 static const struct intel_device_info intel_i830_info
= {
67 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
68 .has_overlay
= 1, .overlay_needs_physical
= 1,
69 .ring_mask
= RENDER_RING
,
70 GEN_DEFAULT_PIPEOFFSETS
,
74 static const struct intel_device_info intel_845g_info
= {
75 .gen
= 2, .num_pipes
= 1,
76 .has_overlay
= 1, .overlay_needs_physical
= 1,
77 .ring_mask
= RENDER_RING
,
78 GEN_DEFAULT_PIPEOFFSETS
,
82 static const struct intel_device_info intel_i85x_info
= {
83 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
84 .cursor_needs_physical
= 1,
85 .has_overlay
= 1, .overlay_needs_physical
= 1,
87 .ring_mask
= RENDER_RING
,
88 GEN_DEFAULT_PIPEOFFSETS
,
92 static const struct intel_device_info intel_i865g_info
= {
93 .gen
= 2, .num_pipes
= 1,
94 .has_overlay
= 1, .overlay_needs_physical
= 1,
95 .ring_mask
= RENDER_RING
,
96 GEN_DEFAULT_PIPEOFFSETS
,
100 static const struct intel_device_info intel_i915g_info
= {
101 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
102 .has_overlay
= 1, .overlay_needs_physical
= 1,
103 .ring_mask
= RENDER_RING
,
104 GEN_DEFAULT_PIPEOFFSETS
,
107 static const struct intel_device_info intel_i915gm_info
= {
108 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
109 .cursor_needs_physical
= 1,
110 .has_overlay
= 1, .overlay_needs_physical
= 1,
113 .ring_mask
= RENDER_RING
,
114 GEN_DEFAULT_PIPEOFFSETS
,
117 static const struct intel_device_info intel_i945g_info
= {
118 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
119 .has_overlay
= 1, .overlay_needs_physical
= 1,
120 .ring_mask
= RENDER_RING
,
121 GEN_DEFAULT_PIPEOFFSETS
,
124 static const struct intel_device_info intel_i945gm_info
= {
125 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
126 .has_hotplug
= 1, .cursor_needs_physical
= 1,
127 .has_overlay
= 1, .overlay_needs_physical
= 1,
130 .ring_mask
= RENDER_RING
,
131 GEN_DEFAULT_PIPEOFFSETS
,
135 static const struct intel_device_info intel_i965g_info
= {
136 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
139 .ring_mask
= RENDER_RING
,
140 GEN_DEFAULT_PIPEOFFSETS
,
144 static const struct intel_device_info intel_i965gm_info
= {
145 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
146 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
149 .ring_mask
= RENDER_RING
,
150 GEN_DEFAULT_PIPEOFFSETS
,
154 static const struct intel_device_info intel_g33_info
= {
155 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
156 .need_gfx_hws
= 1, .has_hotplug
= 1,
158 .ring_mask
= RENDER_RING
,
159 GEN_DEFAULT_PIPEOFFSETS
,
163 static const struct intel_device_info intel_g45_info
= {
164 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
165 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
166 .ring_mask
= RENDER_RING
| BSD_RING
,
167 GEN_DEFAULT_PIPEOFFSETS
,
171 static const struct intel_device_info intel_gm45_info
= {
172 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
173 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
174 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
176 .ring_mask
= RENDER_RING
| BSD_RING
,
177 GEN_DEFAULT_PIPEOFFSETS
,
181 static const struct intel_device_info intel_pineview_info
= {
182 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
183 .need_gfx_hws
= 1, .has_hotplug
= 1,
185 GEN_DEFAULT_PIPEOFFSETS
,
189 static const struct intel_device_info intel_ironlake_d_info
= {
190 .gen
= 5, .num_pipes
= 2,
191 .need_gfx_hws
= 1, .has_hotplug
= 1,
192 .ring_mask
= RENDER_RING
| BSD_RING
,
193 GEN_DEFAULT_PIPEOFFSETS
,
197 static const struct intel_device_info intel_ironlake_m_info
= {
198 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
199 .need_gfx_hws
= 1, .has_hotplug
= 1,
201 .ring_mask
= RENDER_RING
| BSD_RING
,
202 GEN_DEFAULT_PIPEOFFSETS
,
206 static const struct intel_device_info intel_sandybridge_d_info
= {
207 .gen
= 6, .num_pipes
= 2,
208 .need_gfx_hws
= 1, .has_hotplug
= 1,
210 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
212 GEN_DEFAULT_PIPEOFFSETS
,
216 static const struct intel_device_info intel_sandybridge_m_info
= {
217 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
218 .need_gfx_hws
= 1, .has_hotplug
= 1,
220 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
222 GEN_DEFAULT_PIPEOFFSETS
,
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
232 GEN_DEFAULT_PIPEOFFSETS, \
235 static const struct intel_device_info intel_ivybridge_d_info
= {
240 static const struct intel_device_info intel_ivybridge_m_info
= {
246 static const struct intel_device_info intel_ivybridge_q_info
= {
249 .num_pipes
= 0, /* legal, last one wins */
252 #define VLV_FEATURES \
253 .gen = 7, .num_pipes = 2, \
254 .need_gfx_hws = 1, .has_hotplug = 1, \
255 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
256 .display_mmio_offset = VLV_DISPLAY_BASE, \
257 GEN_DEFAULT_PIPEOFFSETS, \
260 static const struct intel_device_info intel_valleyview_m_info
= {
266 static const struct intel_device_info intel_valleyview_d_info
= {
271 #define HSW_FEATURES \
273 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
277 static const struct intel_device_info intel_haswell_d_info
= {
282 static const struct intel_device_info intel_haswell_m_info
= {
288 static const struct intel_device_info intel_broadwell_d_info
= {
293 static const struct intel_device_info intel_broadwell_m_info
= {
295 .gen
= 8, .is_mobile
= 1,
298 static const struct intel_device_info intel_broadwell_gt3d_info
= {
301 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
304 static const struct intel_device_info intel_broadwell_gt3m_info
= {
306 .gen
= 8, .is_mobile
= 1,
307 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
310 static const struct intel_device_info intel_cherryview_info
= {
311 .gen
= 8, .num_pipes
= 3,
312 .need_gfx_hws
= 1, .has_hotplug
= 1,
313 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
315 .display_mmio_offset
= VLV_DISPLAY_BASE
,
320 static const struct intel_device_info intel_skylake_info
= {
326 static const struct intel_device_info intel_skylake_gt3_info
= {
330 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
333 static const struct intel_device_info intel_broxton_info
= {
337 .need_gfx_hws
= 1, .has_hotplug
= 1,
338 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
343 GEN_DEFAULT_PIPEOFFSETS
,
347 static const struct intel_device_info intel_kabylake_info
= {
354 static const struct intel_device_info intel_kabylake_gt3_info
= {
359 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
363 * Make sure any device matches here are from most specific to most
364 * general. For example, since the Quanta match is based on the subsystem
365 * and subvendor IDs, we need it to come before the more general IVB
366 * PCI ID matches, otherwise we'll use the wrong info struct above.
368 static const struct pci_device_id pciidlist
[] = {
369 INTEL_I830_IDS(&intel_i830_info
),
370 INTEL_I845G_IDS(&intel_845g_info
),
371 INTEL_I85X_IDS(&intel_i85x_info
),
372 INTEL_I865G_IDS(&intel_i865g_info
),
373 INTEL_I915G_IDS(&intel_i915g_info
),
374 INTEL_I915GM_IDS(&intel_i915gm_info
),
375 INTEL_I945G_IDS(&intel_i945g_info
),
376 INTEL_I945GM_IDS(&intel_i945gm_info
),
377 INTEL_I965G_IDS(&intel_i965g_info
),
378 INTEL_G33_IDS(&intel_g33_info
),
379 INTEL_I965GM_IDS(&intel_i965gm_info
),
380 INTEL_GM45_IDS(&intel_gm45_info
),
381 INTEL_G45_IDS(&intel_g45_info
),
382 INTEL_PINEVIEW_IDS(&intel_pineview_info
),
383 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info
),
384 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info
),
385 INTEL_SNB_D_IDS(&intel_sandybridge_d_info
),
386 INTEL_SNB_M_IDS(&intel_sandybridge_m_info
),
387 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info
), /* must be first IVB */
388 INTEL_IVB_M_IDS(&intel_ivybridge_m_info
),
389 INTEL_IVB_D_IDS(&intel_ivybridge_d_info
),
390 INTEL_HSW_D_IDS(&intel_haswell_d_info
),
391 INTEL_HSW_M_IDS(&intel_haswell_m_info
),
392 INTEL_VLV_M_IDS(&intel_valleyview_m_info
),
393 INTEL_VLV_D_IDS(&intel_valleyview_d_info
),
394 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info
),
395 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info
),
396 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info
),
397 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info
),
398 INTEL_CHV_IDS(&intel_cherryview_info
),
399 INTEL_SKL_GT1_IDS(&intel_skylake_info
),
400 INTEL_SKL_GT2_IDS(&intel_skylake_info
),
401 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info
),
402 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info
),
403 INTEL_BXT_IDS(&intel_broxton_info
),
404 INTEL_KBL_GT1_IDS(&intel_kabylake_info
),
405 INTEL_KBL_GT2_IDS(&intel_kabylake_info
),
406 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info
),
407 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info
),
411 MODULE_DEVICE_TABLE(pci
, pciidlist
);
413 static enum intel_pch
intel_virt_detect_pch(struct drm_device
*dev
)
415 enum intel_pch ret
= PCH_NOP
;
418 * In a virtualized passthrough environment we can be in a
419 * setup where the ISA bridge is not able to be passed through.
420 * In this case, a south bridge can be emulated and we have to
421 * make an educated guess as to which PCH is really there.
426 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
427 } else if (IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)) {
429 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
430 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
432 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
433 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
435 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
441 void intel_detect_pch(struct drm_device
*dev
)
443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
444 struct pci_dev
*pch
= NULL
;
446 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
447 * (which really amounts to a PCH but no South Display).
449 if (INTEL_INFO(dev
)->num_pipes
== 0) {
450 dev_priv
->pch_type
= PCH_NOP
;
455 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
456 * make graphics device passthrough work easy for VMM, that only
457 * need to expose ISA bridge to let driver know the real hardware
458 * underneath. This is a requirement from virtualization team.
460 * In some virtualized environments (e.g. XEN), there is irrelevant
461 * ISA bridge in the system. To work reliably, we should scan trhough
462 * all the ISA bridge devices and check for the first match, instead
463 * of only checking the first one.
465 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
466 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
467 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
468 dev_priv
->pch_id
= id
;
470 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
471 dev_priv
->pch_type
= PCH_IBX
;
472 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
473 WARN_ON(!IS_GEN5(dev
));
474 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
475 dev_priv
->pch_type
= PCH_CPT
;
476 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
477 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
478 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
479 /* PantherPoint is CPT compatible */
480 dev_priv
->pch_type
= PCH_CPT
;
481 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
482 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
483 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
484 dev_priv
->pch_type
= PCH_LPT
;
485 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
486 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
487 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
488 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
489 dev_priv
->pch_type
= PCH_LPT
;
490 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
491 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
492 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
493 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
494 dev_priv
->pch_type
= PCH_SPT
;
495 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
496 WARN_ON(!IS_SKYLAKE(dev
) &&
498 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
499 dev_priv
->pch_type
= PCH_SPT
;
500 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
501 WARN_ON(!IS_SKYLAKE(dev
) &&
503 } else if ((id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
) ||
504 (id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
)) {
505 dev_priv
->pch_type
= intel_virt_detect_pch(dev
);
513 DRM_DEBUG_KMS("No PCH found.\n");
518 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
520 if (INTEL_INFO(dev
)->gen
< 6)
523 if (i915
.semaphores
>= 0)
524 return i915
.semaphores
;
526 /* TODO: make semaphores and Execlists play nicely together */
527 if (i915
.enable_execlists
)
530 /* Until we get further testing... */
534 #ifdef CONFIG_INTEL_IOMMU
535 /* Enable semaphores on SNB when IO remapping is off */
536 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
543 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
545 struct drm_device
*dev
= dev_priv
->dev
;
546 struct intel_encoder
*encoder
;
548 drm_modeset_lock_all(dev
);
549 for_each_intel_encoder(dev
, encoder
)
550 if (encoder
->suspend
)
551 encoder
->suspend(encoder
);
552 drm_modeset_unlock_all(dev
);
555 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
);
556 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
558 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
);
560 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
562 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
563 if (acpi_target_system_state() < ACPI_STATE_S3
)
569 static int i915_drm_suspend(struct drm_device
*dev
)
571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
572 pci_power_t opregion_target_state
;
575 /* ignore lid events during suspend */
576 mutex_lock(&dev_priv
->modeset_restore_lock
);
577 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
578 mutex_unlock(&dev_priv
->modeset_restore_lock
);
580 disable_rpm_wakeref_asserts(dev_priv
);
582 /* We do a lot of poking in a lot of registers, make sure they work
584 intel_display_set_init_power(dev_priv
, true);
586 drm_kms_helper_poll_disable(dev
);
588 pci_save_state(dev
->pdev
);
590 error
= i915_gem_suspend(dev
);
592 dev_err(&dev
->pdev
->dev
,
593 "GEM idle failed, resume might fail\n");
597 intel_guc_suspend(dev
);
599 intel_suspend_gt_powersave(dev
);
602 * Disable CRTCs directly since we want to preserve sw state
603 * for _thaw. Also, power gate the CRTC power wells.
605 drm_modeset_lock_all(dev
);
606 intel_display_suspend(dev
);
607 drm_modeset_unlock_all(dev
);
609 intel_dp_mst_suspend(dev
);
611 intel_runtime_pm_disable_interrupts(dev_priv
);
612 intel_hpd_cancel_work(dev_priv
);
614 intel_suspend_encoders(dev_priv
);
616 intel_suspend_hw(dev
);
618 i915_gem_suspend_gtt_mappings(dev
);
620 i915_save_state(dev
);
622 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
623 intel_opregion_notify_adapter(dev
, opregion_target_state
);
625 intel_uncore_forcewake_reset(dev
, false);
626 intel_opregion_fini(dev
);
628 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
630 dev_priv
->suspend_count
++;
632 intel_display_set_init_power(dev_priv
, false);
634 if (HAS_CSR(dev_priv
))
635 flush_work(&dev_priv
->csr
.work
);
638 enable_rpm_wakeref_asserts(dev_priv
);
643 static int i915_drm_suspend_late(struct drm_device
*drm_dev
, bool hibernation
)
645 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
649 disable_rpm_wakeref_asserts(dev_priv
);
651 fw_csr
= suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
653 * In case of firmware assisted context save/restore don't manually
654 * deinit the power domains. This also means the CSR/DMC firmware will
655 * stay active, it will power down any HW resources as required and
656 * also enable deeper system power states that would be blocked if the
657 * firmware was inactive.
660 intel_power_domains_suspend(dev_priv
);
662 ret
= intel_suspend_complete(dev_priv
);
665 DRM_ERROR("Suspend complete failed: %d\n", ret
);
667 intel_power_domains_init_hw(dev_priv
, true);
672 pci_disable_device(drm_dev
->pdev
);
674 * During hibernation on some platforms the BIOS may try to access
675 * the device even though it's already in D3 and hang the machine. So
676 * leave the device in D0 on those platforms and hope the BIOS will
677 * power down the device properly. The issue was seen on multiple old
678 * GENs with different BIOS vendors, so having an explicit blacklist
679 * is inpractical; apply the workaround on everything pre GEN6. The
680 * platforms where the issue was seen:
681 * Lenovo Thinkpad X301, X61s, X60, T60, X41
685 if (!(hibernation
&& INTEL_INFO(dev_priv
)->gen
< 6))
686 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
688 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
691 enable_rpm_wakeref_asserts(dev_priv
);
696 int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
700 if (!dev
|| !dev
->dev_private
) {
701 DRM_ERROR("dev: %p\n", dev
);
702 DRM_ERROR("DRM not initialized, aborting suspend.\n");
706 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
707 state
.event
!= PM_EVENT_FREEZE
))
710 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
713 error
= i915_drm_suspend(dev
);
717 return i915_drm_suspend_late(dev
, false);
720 static int i915_drm_resume(struct drm_device
*dev
)
722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
724 disable_rpm_wakeref_asserts(dev_priv
);
726 mutex_lock(&dev
->struct_mutex
);
727 i915_gem_restore_gtt_mappings(dev
);
728 mutex_unlock(&dev
->struct_mutex
);
730 i915_restore_state(dev
);
731 intel_opregion_setup(dev
);
733 intel_init_pch_refclk(dev
);
734 drm_mode_config_reset(dev
);
737 * Interrupts have to be enabled before any batches are run. If not the
738 * GPU will hang. i915_gem_init_hw() will initiate batches to
739 * update/restore the context.
741 * Modeset enabling in intel_modeset_init_hw() also needs working
744 intel_runtime_pm_enable_interrupts(dev_priv
);
746 mutex_lock(&dev
->struct_mutex
);
747 if (i915_gem_init_hw(dev
)) {
748 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
749 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
751 mutex_unlock(&dev
->struct_mutex
);
753 intel_guc_resume(dev
);
755 intel_modeset_init_hw(dev
);
757 spin_lock_irq(&dev_priv
->irq_lock
);
758 if (dev_priv
->display
.hpd_irq_setup
)
759 dev_priv
->display
.hpd_irq_setup(dev
);
760 spin_unlock_irq(&dev_priv
->irq_lock
);
762 drm_modeset_lock_all(dev
);
763 intel_display_resume(dev
);
764 drm_modeset_unlock_all(dev
);
766 intel_dp_mst_resume(dev
);
769 * ... but also need to make sure that hotplug processing
770 * doesn't cause havoc. Like in the driver load code we don't
771 * bother with the tiny race here where we might loose hotplug
774 intel_hpd_init(dev_priv
);
775 /* Config may have changed between suspend and resume */
776 drm_helper_hpd_irq_event(dev
);
778 intel_opregion_init(dev
);
780 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
782 mutex_lock(&dev_priv
->modeset_restore_lock
);
783 dev_priv
->modeset_restore
= MODESET_DONE
;
784 mutex_unlock(&dev_priv
->modeset_restore_lock
);
786 intel_opregion_notify_adapter(dev
, PCI_D0
);
788 drm_kms_helper_poll_enable(dev
);
790 enable_rpm_wakeref_asserts(dev_priv
);
795 static int i915_drm_resume_early(struct drm_device
*dev
)
797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
801 * We have a resume ordering issue with the snd-hda driver also
802 * requiring our device to be power up. Due to the lack of a
803 * parent/child relationship we currently solve this with an early
806 * FIXME: This should be solved with a special hdmi sink device or
807 * similar so that power domains can be employed.
809 if (pci_enable_device(dev
->pdev
)) {
814 pci_set_master(dev
->pdev
);
816 disable_rpm_wakeref_asserts(dev_priv
);
818 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
819 ret
= vlv_resume_prepare(dev_priv
, false);
821 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
824 intel_uncore_early_sanitize(dev
, true);
827 ret
= bxt_resume_prepare(dev_priv
);
828 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
829 hsw_disable_pc8(dev_priv
);
831 intel_uncore_sanitize(dev
);
833 if (!(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
834 intel_power_domains_init_hw(dev_priv
, true);
837 dev_priv
->suspended_to_idle
= false;
839 enable_rpm_wakeref_asserts(dev_priv
);
844 int i915_resume_switcheroo(struct drm_device
*dev
)
848 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
851 ret
= i915_drm_resume_early(dev
);
855 return i915_drm_resume(dev
);
859 * i915_reset - reset chip after a hang
860 * @dev: drm device to reset
862 * Reset the chip. Useful if a hang is detected. Returns zero on successful
863 * reset or otherwise an error code.
865 * Procedure is fairly simple:
866 * - reset the chip using the reset reg
867 * - re-init context state
868 * - re-init hardware status page
869 * - re-init ring buffer
870 * - re-init interrupt state
873 int i915_reset(struct drm_device
*dev
)
875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
879 intel_reset_gt_powersave(dev
);
881 mutex_lock(&dev
->struct_mutex
);
885 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
887 ret
= intel_gpu_reset(dev
);
889 /* Also reset the gpu hangman. */
891 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
892 dev_priv
->gpu_error
.stop_rings
= 0;
893 if (ret
== -ENODEV
) {
894 DRM_INFO("Reset not implemented, but ignoring "
895 "error for simulated gpu hangs\n");
900 if (i915_stop_ring_allow_warn(dev_priv
))
901 pr_notice("drm/i915: Resetting chip after gpu hang\n");
904 DRM_ERROR("Failed to reset chip: %i\n", ret
);
905 mutex_unlock(&dev
->struct_mutex
);
909 intel_overlay_reset(dev_priv
);
911 /* Ok, now get things going again... */
914 * Everything depends on having the GTT running, so we need to start
915 * there. Fortunately we don't need to do this unless we reset the
916 * chip at a PCI level.
918 * Next we need to restore the context, but we don't use those
921 * Ring buffer needs to be re-initialized in the KMS case, or if X
922 * was running at the time of the reset (i.e. we weren't VT
926 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
927 dev_priv
->gpu_error
.reload_in_reset
= true;
929 ret
= i915_gem_init_hw(dev
);
931 dev_priv
->gpu_error
.reload_in_reset
= false;
933 mutex_unlock(&dev
->struct_mutex
);
935 DRM_ERROR("Failed hw init on reset %d\n", ret
);
940 * rps/rc6 re-init is necessary to restore state lost after the
941 * reset and the re-install of gt irqs. Skip for ironlake per
942 * previous concerns that it doesn't respond well to some forms
943 * of re-init after reset.
945 if (INTEL_INFO(dev
)->gen
> 5)
946 intel_enable_gt_powersave(dev
);
951 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
953 struct intel_device_info
*intel_info
=
954 (struct intel_device_info
*) ent
->driver_data
;
956 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
957 DRM_INFO("This hardware requires preliminary hardware support.\n"
958 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
962 /* Only bind to function 0 of the device. Early generations
963 * used function 1 as a placeholder for multi-head. This causes
964 * us confusion instead, especially on the systems where both
965 * functions have the same PCI-ID!
967 if (PCI_FUNC(pdev
->devfn
))
970 return drm_get_pci_dev(pdev
, ent
, &driver
);
974 i915_pci_remove(struct pci_dev
*pdev
)
976 struct drm_device
*dev
= pci_get_drvdata(pdev
);
981 static int i915_pm_suspend(struct device
*dev
)
983 struct pci_dev
*pdev
= to_pci_dev(dev
);
984 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
986 if (!drm_dev
|| !drm_dev
->dev_private
) {
987 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
991 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
994 return i915_drm_suspend(drm_dev
);
997 static int i915_pm_suspend_late(struct device
*dev
)
999 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1002 * We have a suspend ordering issue with the snd-hda driver also
1003 * requiring our device to be power up. Due to the lack of a
1004 * parent/child relationship we currently solve this with an late
1007 * FIXME: This should be solved with a special hdmi sink device or
1008 * similar so that power domains can be employed.
1010 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1013 return i915_drm_suspend_late(drm_dev
, false);
1016 static int i915_pm_poweroff_late(struct device
*dev
)
1018 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1020 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1023 return i915_drm_suspend_late(drm_dev
, true);
1026 static int i915_pm_resume_early(struct device
*dev
)
1028 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1030 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1033 return i915_drm_resume_early(drm_dev
);
1036 static int i915_pm_resume(struct device
*dev
)
1038 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1040 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1043 return i915_drm_resume(drm_dev
);
1046 static int hsw_suspend_complete(struct drm_i915_private
*dev_priv
)
1048 hsw_enable_pc8(dev_priv
);
1053 static int bxt_suspend_complete(struct drm_i915_private
*dev_priv
)
1055 struct drm_device
*dev
= dev_priv
->dev
;
1057 /* TODO: when DC5 support is added disable DC5 here. */
1059 broxton_ddi_phy_uninit(dev
);
1060 broxton_uninit_cdclk(dev
);
1061 bxt_enable_dc9(dev_priv
);
1066 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
)
1068 struct drm_device
*dev
= dev_priv
->dev
;
1070 /* TODO: when CSR FW support is added make sure the FW is loaded */
1072 bxt_disable_dc9(dev_priv
);
1075 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1078 broxton_init_cdclk(dev
);
1079 broxton_ddi_phy_init(dev
);
1080 intel_prepare_ddi(dev
);
1086 * Save all Gunit registers that may be lost after a D3 and a subsequent
1087 * S0i[R123] transition. The list of registers needing a save/restore is
1088 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1089 * registers in the following way:
1090 * - Driver: saved/restored by the driver
1091 * - Punit : saved/restored by the Punit firmware
1092 * - No, w/o marking: no need to save/restore, since the register is R/O or
1093 * used internally by the HW in a way that doesn't depend
1094 * keeping the content across a suspend/resume.
1095 * - Debug : used for debugging
1097 * We save/restore all registers marked with 'Driver', with the following
1099 * - Registers out of use, including also registers marked with 'Debug'.
1100 * These have no effect on the driver's operation, so we don't save/restore
1101 * them to reduce the overhead.
1102 * - Registers that are fully setup by an initialization function called from
1103 * the resume path. For example many clock gating and RPS/RC6 registers.
1104 * - Registers that provide the right functionality with their reset defaults.
1106 * TODO: Except for registers that based on the above 3 criteria can be safely
1107 * ignored, we save/restore all others, practically treating the HW context as
1108 * a black-box for the driver. Further investigation is needed to reduce the
1109 * saved/restored registers even further, by following the same 3 criteria.
1111 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1113 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1116 /* GAM 0x4000-0x4770 */
1117 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1118 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1119 s
->arb_mode
= I915_READ(ARB_MODE
);
1120 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1121 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1123 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1124 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
1126 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1127 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1129 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1130 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1131 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1132 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1134 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1136 /* MBC 0x9024-0x91D0, 0x8500 */
1137 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1138 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1139 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1141 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1142 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1143 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1144 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1145 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1146 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1147 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1149 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1150 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1151 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1152 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1153 s
->ecobus
= I915_READ(ECOBUS
);
1154 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1155 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1156 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1157 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1158 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1159 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1161 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1162 s
->gt_imr
= I915_READ(GTIMR
);
1163 s
->gt_ier
= I915_READ(GTIER
);
1164 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1165 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1167 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1168 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
1170 /* GT SA CZ domain, 0x100000-0x138124 */
1171 s
->tilectl
= I915_READ(TILECTL
);
1172 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1173 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1174 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1175 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1177 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1178 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1179 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1180 s
->pcbr
= I915_READ(VLV_PCBR
);
1181 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1184 * Not saving any of:
1185 * DFT, 0x9800-0x9EC0
1186 * SARB, 0xB000-0xB1FC
1187 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1192 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1194 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1198 /* GAM 0x4000-0x4770 */
1199 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1200 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1201 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1202 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1203 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1205 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1206 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
1208 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1209 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1211 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1212 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1213 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1214 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1216 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1218 /* MBC 0x9024-0x91D0, 0x8500 */
1219 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1220 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1221 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1223 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1224 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1225 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1226 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1227 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1228 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1229 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1231 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1232 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1233 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1234 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1235 I915_WRITE(ECOBUS
, s
->ecobus
);
1236 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1237 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1238 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1239 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1240 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1241 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1243 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1244 I915_WRITE(GTIMR
, s
->gt_imr
);
1245 I915_WRITE(GTIER
, s
->gt_ier
);
1246 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1247 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1249 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1250 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
1252 /* GT SA CZ domain, 0x100000-0x138124 */
1253 I915_WRITE(TILECTL
, s
->tilectl
);
1254 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1256 * Preserve the GT allow wake and GFX force clock bit, they are not
1257 * be restored, as they are used to control the s0ix suspend/resume
1258 * sequence by the caller.
1260 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1261 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1262 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1263 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1265 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1266 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1267 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1268 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1270 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1272 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1273 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1274 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1275 I915_WRITE(VLV_PCBR
, s
->pcbr
);
1276 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1279 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1284 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1286 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1287 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1289 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1290 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1295 err
= wait_for(COND
, 20);
1297 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1298 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1304 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1309 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1310 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1312 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1313 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1314 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1316 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1318 err
= wait_for(COND
, 1);
1320 DRM_ERROR("timeout disabling GT waking\n");
1325 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1332 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1333 val
= wait_for_on
? mask
: 0;
1334 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1338 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1339 wait_for_on
? "on" : "off",
1340 I915_READ(VLV_GTLC_PW_STATUS
));
1343 * RC6 transitioning can be delayed up to 2 msec (see
1344 * valleyview_enable_rps), use 3 msec for safety.
1346 err
= wait_for(COND
, 3);
1348 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1349 wait_for_on
? "on" : "off");
1355 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1357 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1360 DRM_ERROR("GT register access while GT waking disabled\n");
1361 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1364 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
1370 * Bspec defines the following GT well on flags as debug only, so
1371 * don't treat them as hard failures.
1373 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1375 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1376 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1378 vlv_check_no_gt_access(dev_priv
);
1380 err
= vlv_force_gfx_clock(dev_priv
, true);
1384 err
= vlv_allow_gt_wake(dev_priv
, false);
1388 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1389 vlv_save_gunit_s0ix_state(dev_priv
);
1391 err
= vlv_force_gfx_clock(dev_priv
, false);
1398 /* For safety always re-enable waking and disable gfx clock forcing */
1399 vlv_allow_gt_wake(dev_priv
, true);
1401 vlv_force_gfx_clock(dev_priv
, false);
1406 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1409 struct drm_device
*dev
= dev_priv
->dev
;
1414 * If any of the steps fail just try to continue, that's the best we
1415 * can do at this point. Return the first error code (which will also
1416 * leave RPM permanently disabled).
1418 ret
= vlv_force_gfx_clock(dev_priv
, true);
1420 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1421 vlv_restore_gunit_s0ix_state(dev_priv
);
1423 err
= vlv_allow_gt_wake(dev_priv
, true);
1427 err
= vlv_force_gfx_clock(dev_priv
, false);
1431 vlv_check_no_gt_access(dev_priv
);
1434 intel_init_clock_gating(dev
);
1435 i915_gem_restore_fences(dev
);
1441 static int intel_runtime_suspend(struct device
*device
)
1443 struct pci_dev
*pdev
= to_pci_dev(device
);
1444 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1448 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1451 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1454 DRM_DEBUG_KMS("Suspending device\n");
1457 * We could deadlock here in case another thread holding struct_mutex
1458 * calls RPM suspend concurrently, since the RPM suspend will wait
1459 * first for this RPM suspend to finish. In this case the concurrent
1460 * RPM resume will be followed by its RPM suspend counterpart. Still
1461 * for consistency return -EAGAIN, which will reschedule this suspend.
1463 if (!mutex_trylock(&dev
->struct_mutex
)) {
1464 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1466 * Bump the expiration timestamp, otherwise the suspend won't
1469 pm_runtime_mark_last_busy(device
);
1474 disable_rpm_wakeref_asserts(dev_priv
);
1477 * We are safe here against re-faults, since the fault handler takes
1480 i915_gem_release_all_mmaps(dev_priv
);
1481 mutex_unlock(&dev
->struct_mutex
);
1483 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1485 intel_guc_suspend(dev
);
1487 intel_suspend_gt_powersave(dev
);
1488 intel_runtime_pm_disable_interrupts(dev_priv
);
1490 ret
= intel_suspend_complete(dev_priv
);
1492 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1493 intel_runtime_pm_enable_interrupts(dev_priv
);
1495 enable_rpm_wakeref_asserts(dev_priv
);
1500 intel_uncore_forcewake_reset(dev
, false);
1502 enable_rpm_wakeref_asserts(dev_priv
);
1503 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
1504 dev_priv
->pm
.suspended
= true;
1507 * FIXME: We really should find a document that references the arguments
1510 if (IS_BROADWELL(dev
)) {
1512 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1513 * being detected, and the call we do at intel_runtime_resume()
1514 * won't be able to restore them. Since PCI_D3hot matches the
1515 * actual specification and appears to be working, use it.
1517 intel_opregion_notify_adapter(dev
, PCI_D3hot
);
1520 * current versions of firmware which depend on this opregion
1521 * notification have repurposed the D1 definition to mean
1522 * "runtime suspended" vs. what you would normally expect (D3)
1523 * to distinguish it from notifications that might be sent via
1526 intel_opregion_notify_adapter(dev
, PCI_D1
);
1529 assert_forcewakes_inactive(dev_priv
);
1531 DRM_DEBUG_KMS("Device suspended\n");
1535 static int intel_runtime_resume(struct device
*device
)
1537 struct pci_dev
*pdev
= to_pci_dev(device
);
1538 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1542 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1545 DRM_DEBUG_KMS("Resuming device\n");
1547 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
1548 disable_rpm_wakeref_asserts(dev_priv
);
1550 intel_opregion_notify_adapter(dev
, PCI_D0
);
1551 dev_priv
->pm
.suspended
= false;
1553 intel_guc_resume(dev
);
1555 if (IS_GEN6(dev_priv
))
1556 intel_init_pch_refclk(dev
);
1558 if (IS_BROXTON(dev
))
1559 ret
= bxt_resume_prepare(dev_priv
);
1560 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1561 hsw_disable_pc8(dev_priv
);
1562 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1563 ret
= vlv_resume_prepare(dev_priv
, true);
1566 * No point of rolling back things in case of an error, as the best
1567 * we can do is to hope that things will still work (and disable RPM).
1569 i915_gem_init_swizzling(dev
);
1570 gen6_update_ring_freq(dev
);
1572 intel_runtime_pm_enable_interrupts(dev_priv
);
1575 * On VLV/CHV display interrupts are part of the display
1576 * power well, so hpd is reinitialized from there. For
1577 * everyone else do it here.
1579 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
1580 intel_hpd_init(dev_priv
);
1582 intel_enable_gt_powersave(dev
);
1584 enable_rpm_wakeref_asserts(dev_priv
);
1587 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1589 DRM_DEBUG_KMS("Device resumed\n");
1595 * This function implements common functionality of runtime and system
1598 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
)
1602 if (IS_BROXTON(dev_priv
))
1603 ret
= bxt_suspend_complete(dev_priv
);
1604 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1605 ret
= hsw_suspend_complete(dev_priv
);
1606 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1607 ret
= vlv_suspend_complete(dev_priv
);
1614 static const struct dev_pm_ops i915_pm_ops
= {
1616 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1619 .suspend
= i915_pm_suspend
,
1620 .suspend_late
= i915_pm_suspend_late
,
1621 .resume_early
= i915_pm_resume_early
,
1622 .resume
= i915_pm_resume
,
1626 * @freeze, @freeze_late : called (1) before creating the
1627 * hibernation image [PMSG_FREEZE] and
1628 * (2) after rebooting, before restoring
1629 * the image [PMSG_QUIESCE]
1630 * @thaw, @thaw_early : called (1) after creating the hibernation
1631 * image, before writing it [PMSG_THAW]
1632 * and (2) after failing to create or
1633 * restore the image [PMSG_RECOVER]
1634 * @poweroff, @poweroff_late: called after writing the hibernation
1635 * image, before rebooting [PMSG_HIBERNATE]
1636 * @restore, @restore_early : called after rebooting and restoring the
1637 * hibernation image [PMSG_RESTORE]
1639 .freeze
= i915_pm_suspend
,
1640 .freeze_late
= i915_pm_suspend_late
,
1641 .thaw_early
= i915_pm_resume_early
,
1642 .thaw
= i915_pm_resume
,
1643 .poweroff
= i915_pm_suspend
,
1644 .poweroff_late
= i915_pm_poweroff_late
,
1645 .restore_early
= i915_pm_resume_early
,
1646 .restore
= i915_pm_resume
,
1648 /* S0ix (via runtime suspend) event handlers */
1649 .runtime_suspend
= intel_runtime_suspend
,
1650 .runtime_resume
= intel_runtime_resume
,
1653 static const struct vm_operations_struct i915_gem_vm_ops
= {
1654 .fault
= i915_gem_fault
,
1655 .open
= drm_gem_vm_open
,
1656 .close
= drm_gem_vm_close
,
1659 static const struct file_operations i915_driver_fops
= {
1660 .owner
= THIS_MODULE
,
1662 .release
= drm_release
,
1663 .unlocked_ioctl
= drm_ioctl
,
1664 .mmap
= drm_gem_mmap
,
1667 #ifdef CONFIG_COMPAT
1668 .compat_ioctl
= i915_compat_ioctl
,
1670 .llseek
= noop_llseek
,
1673 static struct drm_driver driver
= {
1674 /* Don't use MTRRs here; the Xserver or userspace app should
1675 * deal with them for Intel hardware.
1678 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1679 DRIVER_RENDER
| DRIVER_MODESET
,
1680 .load
= i915_driver_load
,
1681 .unload
= i915_driver_unload
,
1682 .open
= i915_driver_open
,
1683 .lastclose
= i915_driver_lastclose
,
1684 .preclose
= i915_driver_preclose
,
1685 .postclose
= i915_driver_postclose
,
1686 .set_busid
= drm_pci_set_busid
,
1688 #if defined(CONFIG_DEBUG_FS)
1689 .debugfs_init
= i915_debugfs_init
,
1690 .debugfs_cleanup
= i915_debugfs_cleanup
,
1692 .gem_free_object
= i915_gem_free_object
,
1693 .gem_vm_ops
= &i915_gem_vm_ops
,
1695 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1696 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1697 .gem_prime_export
= i915_gem_prime_export
,
1698 .gem_prime_import
= i915_gem_prime_import
,
1700 .dumb_create
= i915_gem_dumb_create
,
1701 .dumb_map_offset
= i915_gem_mmap_gtt
,
1702 .dumb_destroy
= drm_gem_dumb_destroy
,
1703 .ioctls
= i915_ioctls
,
1704 .fops
= &i915_driver_fops
,
1705 .name
= DRIVER_NAME
,
1706 .desc
= DRIVER_DESC
,
1707 .date
= DRIVER_DATE
,
1708 .major
= DRIVER_MAJOR
,
1709 .minor
= DRIVER_MINOR
,
1710 .patchlevel
= DRIVER_PATCHLEVEL
,
1713 static struct pci_driver i915_pci_driver
= {
1714 .name
= DRIVER_NAME
,
1715 .id_table
= pciidlist
,
1716 .probe
= i915_pci_probe
,
1717 .remove
= i915_pci_remove
,
1718 .driver
.pm
= &i915_pm_ops
,
1721 static int __init
i915_init(void)
1723 driver
.num_ioctls
= i915_max_ioctl
;
1726 * Enable KMS by default, unless explicitly overriden by
1727 * either the i915.modeset prarameter or by the
1728 * vga_text_mode_force boot option.
1731 if (i915
.modeset
== 0)
1732 driver
.driver_features
&= ~DRIVER_MODESET
;
1734 #ifdef CONFIG_VGA_CONSOLE
1735 if (vgacon_text_force() && i915
.modeset
== -1)
1736 driver
.driver_features
&= ~DRIVER_MODESET
;
1739 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1740 /* Silently fail loading to not upset userspace. */
1741 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1745 if (i915
.nuclear_pageflip
)
1746 driver
.driver_features
|= DRIVER_ATOMIC
;
1748 return drm_pci_init(&driver
, &i915_pci_driver
);
1751 static void __exit
i915_exit(void)
1753 if (!(driver
.driver_features
& DRIVER_MODESET
))
1754 return; /* Never loaded a driver. */
1756 drm_pci_exit(&driver
, &i915_pci_driver
);
1759 module_init(i915_init
);
1760 module_exit(i915_exit
);
1762 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1763 MODULE_AUTHOR("Intel Corporation");
1765 MODULE_DESCRIPTION(DRIVER_DESC
);
1766 MODULE_LICENSE("GPL and additional rights");