1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/i915_drm.h>
49 #include "i915_trace.h"
50 #include "i915_vgpu.h"
51 #include "intel_drv.h"
54 static struct drm_driver driver
;
56 static unsigned int i915_load_fail_count
;
58 bool __i915_inject_load_failure(const char *func
, int line
)
60 if (i915_load_fail_count
>= i915
.inject_load_failure
)
63 if (++i915_load_fail_count
== i915
.inject_load_failure
) {
64 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
65 i915
.inject_load_failure
, func
, line
);
72 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
73 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
74 "providing the dmesg log by booting with drm.debug=0xf"
77 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
80 static bool shown_bug_once
;
81 struct device
*kdev
= dev_priv
->drm
.dev
;
82 bool is_error
= level
[1] <= KERN_ERR
[1];
83 bool is_debug
= level
[1] == KERN_DEBUG
[1];
87 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
95 dev_printk(level
, kdev
, "[" DRM_NAME
":%ps] %pV",
96 __builtin_return_address(0), &vaf
);
98 if (is_error
&& !shown_bug_once
) {
99 dev_notice(kdev
, "%s", FDO_BUG_MSG
);
100 shown_bug_once
= true;
106 static bool i915_error_injected(struct drm_i915_private
*dev_priv
)
108 return i915
.inject_load_failure
&&
109 i915_load_fail_count
== i915
.inject_load_failure
;
112 #define i915_load_error(dev_priv, fmt, ...) \
113 __i915_printk(dev_priv, \
114 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
118 static enum intel_pch
intel_virt_detect_pch(struct drm_i915_private
*dev_priv
)
120 enum intel_pch ret
= PCH_NOP
;
123 * In a virtualized passthrough environment we can be in a
124 * setup where the ISA bridge is not able to be passed through.
125 * In this case, a south bridge can be emulated and we have to
126 * make an educated guess as to which PCH is really there.
129 if (IS_GEN5(dev_priv
)) {
131 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
132 } else if (IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
)) {
134 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
135 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
137 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
138 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
140 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
146 static void intel_detect_pch(struct drm_i915_private
*dev_priv
)
148 struct pci_dev
*pch
= NULL
;
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
153 if (INTEL_INFO(dev_priv
)->num_pipes
== 0) {
154 dev_priv
->pch_type
= PCH_NOP
;
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
169 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
170 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
171 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
172 dev_priv
->pch_id
= id
;
174 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
175 dev_priv
->pch_type
= PCH_IBX
;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
177 WARN_ON(!IS_GEN5(dev_priv
));
178 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
179 dev_priv
->pch_type
= PCH_CPT
;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
181 WARN_ON(!(IS_GEN6(dev_priv
) ||
182 IS_IVYBRIDGE(dev_priv
)));
183 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
184 /* PantherPoint is CPT compatible */
185 dev_priv
->pch_type
= PCH_CPT
;
186 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
187 WARN_ON(!(IS_GEN6(dev_priv
) ||
188 IS_IVYBRIDGE(dev_priv
)));
189 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
190 dev_priv
->pch_type
= PCH_LPT
;
191 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
192 WARN_ON(!IS_HASWELL(dev_priv
) &&
193 !IS_BROADWELL(dev_priv
));
194 WARN_ON(IS_HSW_ULT(dev_priv
) ||
195 IS_BDW_ULT(dev_priv
));
196 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
197 dev_priv
->pch_type
= PCH_LPT
;
198 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
199 WARN_ON(!IS_HASWELL(dev_priv
) &&
200 !IS_BROADWELL(dev_priv
));
201 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
202 !IS_BDW_ULT(dev_priv
));
203 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
204 dev_priv
->pch_type
= PCH_SPT
;
205 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
206 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
207 !IS_KABYLAKE(dev_priv
));
208 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
209 dev_priv
->pch_type
= PCH_SPT
;
210 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
211 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
212 !IS_KABYLAKE(dev_priv
));
213 } else if (id
== INTEL_PCH_KBP_DEVICE_ID_TYPE
) {
214 dev_priv
->pch_type
= PCH_KBP
;
215 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
216 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
217 !IS_KABYLAKE(dev_priv
));
218 } else if ((id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
) ||
219 (id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
) ||
220 ((id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
) &&
221 pch
->subsystem_vendor
==
222 PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
223 pch
->subsystem_device
==
224 PCI_SUBDEVICE_ID_QEMU
)) {
226 intel_virt_detect_pch(dev_priv
);
234 DRM_DEBUG_KMS("No PCH found.\n");
239 static int i915_getparam(struct drm_device
*dev
, void *data
,
240 struct drm_file
*file_priv
)
242 struct drm_i915_private
*dev_priv
= to_i915(dev
);
243 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
244 drm_i915_getparam_t
*param
= data
;
247 switch (param
->param
) {
248 case I915_PARAM_IRQ_ACTIVE
:
249 case I915_PARAM_ALLOW_BATCHBUFFER
:
250 case I915_PARAM_LAST_DISPATCH
:
251 /* Reject all old ums/dri params. */
253 case I915_PARAM_CHIPSET_ID
:
254 value
= pdev
->device
;
256 case I915_PARAM_REVISION
:
257 value
= pdev
->revision
;
259 case I915_PARAM_NUM_FENCES_AVAIL
:
260 value
= dev_priv
->num_fence_regs
;
262 case I915_PARAM_HAS_OVERLAY
:
263 value
= dev_priv
->overlay
? 1 : 0;
265 case I915_PARAM_HAS_BSD
:
266 value
= !!dev_priv
->engine
[VCS
];
268 case I915_PARAM_HAS_BLT
:
269 value
= !!dev_priv
->engine
[BCS
];
271 case I915_PARAM_HAS_VEBOX
:
272 value
= !!dev_priv
->engine
[VECS
];
274 case I915_PARAM_HAS_BSD2
:
275 value
= !!dev_priv
->engine
[VCS2
];
277 case I915_PARAM_HAS_EXEC_CONSTANTS
:
278 value
= INTEL_GEN(dev_priv
) >= 4;
280 case I915_PARAM_HAS_LLC
:
281 value
= HAS_LLC(dev_priv
);
283 case I915_PARAM_HAS_WT
:
284 value
= HAS_WT(dev_priv
);
286 case I915_PARAM_HAS_ALIASING_PPGTT
:
287 value
= USES_PPGTT(dev_priv
);
289 case I915_PARAM_HAS_SEMAPHORES
:
290 value
= i915
.semaphores
;
292 case I915_PARAM_HAS_SECURE_BATCHES
:
293 value
= capable(CAP_SYS_ADMIN
);
295 case I915_PARAM_CMD_PARSER_VERSION
:
296 value
= i915_cmd_parser_get_version(dev_priv
);
298 case I915_PARAM_SUBSLICE_TOTAL
:
299 value
= sseu_subslice_total(&INTEL_INFO(dev_priv
)->sseu
);
303 case I915_PARAM_EU_TOTAL
:
304 value
= INTEL_INFO(dev_priv
)->sseu
.eu_total
;
308 case I915_PARAM_HAS_GPU_RESET
:
309 value
= i915
.enable_hangcheck
&& intel_has_gpu_reset(dev_priv
);
311 case I915_PARAM_HAS_RESOURCE_STREAMER
:
312 value
= HAS_RESOURCE_STREAMER(dev_priv
);
314 case I915_PARAM_HAS_POOLED_EU
:
315 value
= HAS_POOLED_EU(dev_priv
);
317 case I915_PARAM_MIN_EU_IN_POOL
:
318 value
= INTEL_INFO(dev_priv
)->sseu
.min_eu_in_pool
;
320 case I915_PARAM_HUC_STATUS
:
321 /* The register is already force-woken. We dont need
324 value
= I915_READ(HUC_STATUS2
) & HUC_FW_VERIFIED
;
326 case I915_PARAM_MMAP_GTT_VERSION
:
327 /* Though we've started our numbering from 1, and so class all
328 * earlier versions as 0, in effect their value is undefined as
329 * the ioctl will report EINVAL for the unknown param!
331 value
= i915_gem_mmap_gtt_version();
333 case I915_PARAM_HAS_SCHEDULER
:
334 value
= dev_priv
->engine
[RCS
] &&
335 dev_priv
->engine
[RCS
]->schedule
;
337 case I915_PARAM_MMAP_VERSION
:
338 /* Remember to bump this if the version changes! */
339 case I915_PARAM_HAS_GEM
:
340 case I915_PARAM_HAS_PAGEFLIPPING
:
341 case I915_PARAM_HAS_EXECBUF2
: /* depends on GEM */
342 case I915_PARAM_HAS_RELAXED_FENCING
:
343 case I915_PARAM_HAS_COHERENT_RINGS
:
344 case I915_PARAM_HAS_RELAXED_DELTA
:
345 case I915_PARAM_HAS_GEN7_SOL_RESET
:
346 case I915_PARAM_HAS_WAIT_TIMEOUT
:
347 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
348 case I915_PARAM_HAS_PINNED_BATCHES
:
349 case I915_PARAM_HAS_EXEC_NO_RELOC
:
350 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
351 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
352 case I915_PARAM_HAS_EXEC_SOFTPIN
:
353 /* For the time being all of these are always true;
354 * if some supported hardware does not have one of these
355 * features this value needs to be provided from
356 * INTEL_INFO(), a feature macro, or similar.
361 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
365 if (put_user(value
, param
->value
))
371 static int i915_get_bridge_dev(struct drm_i915_private
*dev_priv
)
373 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
374 if (!dev_priv
->bridge_dev
) {
375 DRM_ERROR("bridge device not found\n");
381 /* Allocate space for the MCH regs if needed, return nonzero on error */
383 intel_alloc_mchbar_resource(struct drm_i915_private
*dev_priv
)
385 int reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
386 u32 temp_lo
, temp_hi
= 0;
390 if (INTEL_GEN(dev_priv
) >= 4)
391 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
392 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
393 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
395 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
398 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
402 /* Get some space for it */
403 dev_priv
->mch_res
.name
= "i915 MCHBAR";
404 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
405 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
407 MCHBAR_SIZE
, MCHBAR_SIZE
,
409 0, pcibios_align_resource
,
410 dev_priv
->bridge_dev
);
412 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
413 dev_priv
->mch_res
.start
= 0;
417 if (INTEL_GEN(dev_priv
) >= 4)
418 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
419 upper_32_bits(dev_priv
->mch_res
.start
));
421 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
422 lower_32_bits(dev_priv
->mch_res
.start
));
426 /* Setup MCHBAR if possible, return true if we should disable it again */
428 intel_setup_mchbar(struct drm_i915_private
*dev_priv
)
430 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
434 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
437 dev_priv
->mchbar_need_disable
= false;
439 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
440 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
441 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
443 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
447 /* If it's already enabled, don't have to do anything */
451 if (intel_alloc_mchbar_resource(dev_priv
))
454 dev_priv
->mchbar_need_disable
= true;
456 /* Space is allocated or reserved, so enable it. */
457 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
458 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
459 temp
| DEVEN_MCHBAR_EN
);
461 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
462 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
467 intel_teardown_mchbar(struct drm_i915_private
*dev_priv
)
469 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
471 if (dev_priv
->mchbar_need_disable
) {
472 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
475 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
477 deven_val
&= ~DEVEN_MCHBAR_EN
;
478 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
483 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
486 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
491 if (dev_priv
->mch_res
.start
)
492 release_resource(&dev_priv
->mch_res
);
495 /* true = enable decode, false = disable decoder */
496 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
498 struct drm_i915_private
*dev_priv
= cookie
;
500 intel_modeset_vga_set_state(dev_priv
, state
);
502 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
503 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
505 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
508 static int i915_resume_switcheroo(struct drm_device
*dev
);
509 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
511 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
513 struct drm_device
*dev
= pci_get_drvdata(pdev
);
514 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
516 if (state
== VGA_SWITCHEROO_ON
) {
517 pr_info("switched on\n");
518 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
519 /* i915 resume handler doesn't set to D0 */
520 pci_set_power_state(pdev
, PCI_D0
);
521 i915_resume_switcheroo(dev
);
522 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
524 pr_info("switched off\n");
525 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
526 i915_suspend_switcheroo(dev
, pmm
);
527 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
531 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
533 struct drm_device
*dev
= pci_get_drvdata(pdev
);
536 * FIXME: open_count is protected by drm_global_mutex but that would lead to
537 * locking inversion with the driver load path. And the access here is
538 * completely racy anyway. So don't bother with locking for now.
540 return dev
->open_count
== 0;
543 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
544 .set_gpu_state
= i915_switcheroo_set_state
,
546 .can_switch
= i915_switcheroo_can_switch
,
549 static void i915_gem_fini(struct drm_i915_private
*dev_priv
)
551 mutex_lock(&dev_priv
->drm
.struct_mutex
);
552 i915_gem_cleanup_engines(dev_priv
);
553 i915_gem_context_fini(dev_priv
);
554 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
556 i915_gem_drain_freed_objects(dev_priv
);
558 WARN_ON(!list_empty(&dev_priv
->context_list
));
561 static int i915_load_modeset_init(struct drm_device
*dev
)
563 struct drm_i915_private
*dev_priv
= to_i915(dev
);
564 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
567 if (i915_inject_load_failure())
570 ret
= intel_bios_init(dev_priv
);
572 DRM_INFO("failed to find VBIOS tables\n");
574 /* If we have > 1 VGA cards, then we need to arbitrate access
575 * to the common VGA resources.
577 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
578 * then we do not take part in VGA arbitration and the
579 * vga_client_register() fails with -ENODEV.
581 ret
= vga_client_register(pdev
, dev_priv
, NULL
, i915_vga_set_decode
);
582 if (ret
&& ret
!= -ENODEV
)
585 intel_register_dsm_handler();
587 ret
= vga_switcheroo_register_client(pdev
, &i915_switcheroo_ops
, false);
589 goto cleanup_vga_client
;
591 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
592 intel_update_rawclk(dev_priv
);
594 intel_power_domains_init_hw(dev_priv
, false);
596 intel_csr_ucode_init(dev_priv
);
598 ret
= intel_irq_install(dev_priv
);
602 intel_setup_gmbus(dev_priv
);
604 /* Important: The output setup functions called by modeset_init need
605 * working irqs for e.g. gmbus and dp aux transfers. */
606 ret
= intel_modeset_init(dev
);
610 intel_huc_init(dev_priv
);
611 intel_guc_init(dev_priv
);
613 ret
= i915_gem_init(dev_priv
);
617 intel_modeset_gem_init(dev
);
619 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
622 ret
= intel_fbdev_init(dev
);
626 /* Only enable hotplug handling once the fbdev is fully set up. */
627 intel_hpd_init(dev_priv
);
629 drm_kms_helper_poll_init(dev
);
634 if (i915_gem_suspend(dev_priv
))
635 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
636 i915_gem_fini(dev_priv
);
638 intel_guc_fini(dev_priv
);
639 intel_huc_fini(dev_priv
);
640 drm_irq_uninstall(dev
);
641 intel_teardown_gmbus(dev_priv
);
643 intel_csr_ucode_fini(dev_priv
);
644 intel_power_domains_fini(dev_priv
);
645 vga_switcheroo_unregister_client(pdev
);
647 vga_client_register(pdev
, NULL
, NULL
, NULL
);
652 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
654 struct apertures_struct
*ap
;
655 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
656 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
660 ap
= alloc_apertures(1);
664 ap
->ranges
[0].base
= ggtt
->mappable_base
;
665 ap
->ranges
[0].size
= ggtt
->mappable_end
;
668 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
670 ret
= drm_fb_helper_remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
677 #if !defined(CONFIG_VGA_CONSOLE)
678 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
682 #elif !defined(CONFIG_DUMMY_CONSOLE)
683 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
688 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
692 DRM_INFO("Replacing VGA console driver\n");
695 if (con_is_bound(&vga_con
))
696 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
698 ret
= do_unregister_con_driver(&vga_con
);
700 /* Ignore "already unregistered". */
710 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
713 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
714 * CHV x1 PHY (DP/HDMI D)
715 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
717 if (IS_CHERRYVIEW(dev_priv
)) {
718 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
719 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
720 } else if (IS_VALLEYVIEW(dev_priv
)) {
721 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
725 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
728 * The i915 workqueue is primarily used for batched retirement of
729 * requests (and thus managing bo) once the task has been completed
730 * by the GPU. i915_gem_retire_requests() is called directly when we
731 * need high-priority retirement, such as waiting for an explicit
734 * It is also used for periodic low-priority events, such as
735 * idle-timers and recording error state.
737 * All tasks on the workqueue are expected to acquire the dev mutex
738 * so there is no point in running more than one instance of the
739 * workqueue at any time. Use an ordered one.
741 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
742 if (dev_priv
->wq
== NULL
)
745 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
746 if (dev_priv
->hotplug
.dp_wq
== NULL
)
752 destroy_workqueue(dev_priv
->wq
);
754 DRM_ERROR("Failed to allocate workqueues.\n");
759 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
761 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
762 destroy_workqueue(dev_priv
->wq
);
766 * We don't keep the workarounds for pre-production hardware, so we expect our
767 * driver to fail on these machines in one way or another. A little warning on
768 * dmesg may help both the user and the bug triagers.
770 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
772 if (IS_HSW_EARLY_SDV(dev_priv
) ||
773 IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
))
774 DRM_ERROR("This is a pre-production stepping. "
775 "It may not be fully functional.\n");
779 * i915_driver_init_early - setup state not requiring device access
780 * @dev_priv: device private
782 * Initialize everything that is a "SW-only" state, that is state not
783 * requiring accessing the device or exposing the driver via kernel internal
784 * or userspace interfaces. Example steps belonging here: lock initialization,
785 * system memory allocation, setting up device specific attributes and
786 * function hooks not requiring accessing the device.
788 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
,
789 const struct pci_device_id
*ent
)
791 const struct intel_device_info
*match_info
=
792 (struct intel_device_info
*)ent
->driver_data
;
793 struct intel_device_info
*device_info
;
796 if (i915_inject_load_failure())
799 /* Setup the write-once "constant" device info */
800 device_info
= mkwrite_device_info(dev_priv
);
801 memcpy(device_info
, match_info
, sizeof(*device_info
));
802 device_info
->device_id
= dev_priv
->drm
.pdev
->device
;
804 BUG_ON(device_info
->gen
> sizeof(device_info
->gen_mask
) * BITS_PER_BYTE
);
805 device_info
->gen_mask
= BIT(device_info
->gen
- 1);
807 spin_lock_init(&dev_priv
->irq_lock
);
808 spin_lock_init(&dev_priv
->gpu_error
.lock
);
809 mutex_init(&dev_priv
->backlight_lock
);
810 spin_lock_init(&dev_priv
->uncore
.lock
);
811 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
812 spin_lock_init(&dev_priv
->mmio_flip_lock
);
813 spin_lock_init(&dev_priv
->wm
.dsparb_lock
);
814 mutex_init(&dev_priv
->sb_lock
);
815 mutex_init(&dev_priv
->modeset_restore_lock
);
816 mutex_init(&dev_priv
->av_mutex
);
817 mutex_init(&dev_priv
->wm
.wm_mutex
);
818 mutex_init(&dev_priv
->pps_mutex
);
820 intel_uc_init_early(dev_priv
);
822 i915_memcpy_init_early(dev_priv
);
824 ret
= i915_workqueues_init(dev_priv
);
828 /* This must be called before any calls to HAS_PCH_* */
829 intel_detect_pch(dev_priv
);
831 intel_pm_setup(dev_priv
);
832 intel_init_dpio(dev_priv
);
833 intel_power_domains_init(dev_priv
);
834 intel_irq_init(dev_priv
);
835 intel_hangcheck_init(dev_priv
);
836 intel_init_display_hooks(dev_priv
);
837 intel_init_clock_gating_hooks(dev_priv
);
838 intel_init_audio_hooks(dev_priv
);
839 ret
= i915_gem_load_init(dev_priv
);
843 intel_display_crc_init(dev_priv
);
845 intel_device_info_dump(dev_priv
);
847 intel_detect_preproduction_hw(dev_priv
);
849 i915_perf_init(dev_priv
);
854 i915_workqueues_cleanup(dev_priv
);
859 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
860 * @dev_priv: device private
862 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
864 i915_perf_fini(dev_priv
);
865 i915_gem_load_cleanup(dev_priv
);
866 i915_workqueues_cleanup(dev_priv
);
869 static int i915_mmio_setup(struct drm_i915_private
*dev_priv
)
871 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
875 mmio_bar
= IS_GEN2(dev_priv
) ? 1 : 0;
877 * Before gen4, the registers and the GTT are behind different BARs.
878 * However, from gen4 onwards, the registers and the GTT are shared
879 * in the same BAR, so we want to restrict this ioremap from
880 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
881 * the register BAR remains the same size for all the earlier
882 * generations up to Ironlake.
884 if (INTEL_GEN(dev_priv
) < 5)
885 mmio_size
= 512 * 1024;
887 mmio_size
= 2 * 1024 * 1024;
888 dev_priv
->regs
= pci_iomap(pdev
, mmio_bar
, mmio_size
);
889 if (dev_priv
->regs
== NULL
) {
890 DRM_ERROR("failed to map registers\n");
895 /* Try to make sure MCHBAR is enabled before poking at it */
896 intel_setup_mchbar(dev_priv
);
901 static void i915_mmio_cleanup(struct drm_i915_private
*dev_priv
)
903 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
905 intel_teardown_mchbar(dev_priv
);
906 pci_iounmap(pdev
, dev_priv
->regs
);
910 * i915_driver_init_mmio - setup device MMIO
911 * @dev_priv: device private
913 * Setup minimal device state necessary for MMIO accesses later in the
914 * initialization sequence. The setup here should avoid any other device-wide
915 * side effects or exposing the driver via kernel internal or user space
918 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
922 if (i915_inject_load_failure())
925 if (i915_get_bridge_dev(dev_priv
))
928 ret
= i915_mmio_setup(dev_priv
);
932 intel_uncore_init(dev_priv
);
937 pci_dev_put(dev_priv
->bridge_dev
);
943 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
944 * @dev_priv: device private
946 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
948 intel_uncore_fini(dev_priv
);
949 i915_mmio_cleanup(dev_priv
);
950 pci_dev_put(dev_priv
->bridge_dev
);
953 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
955 i915
.enable_execlists
=
956 intel_sanitize_enable_execlists(dev_priv
,
957 i915
.enable_execlists
);
960 * i915.enable_ppgtt is read-only, so do an early pass to validate the
961 * user's requested state against the hardware/driver capabilities. We
962 * do this now so that we can print out any log messages once rather
963 * than every time we check intel_enable_ppgtt().
966 intel_sanitize_enable_ppgtt(dev_priv
, i915
.enable_ppgtt
);
967 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
969 i915
.semaphores
= intel_sanitize_semaphores(dev_priv
, i915
.semaphores
);
970 DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915
.semaphores
));
974 * i915_driver_init_hw - setup state requiring device access
975 * @dev_priv: device private
977 * Setup state that requires accessing the device, but doesn't require
978 * exposing the driver via kernel internal or userspace interfaces.
980 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
982 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
985 if (i915_inject_load_failure())
988 intel_device_info_runtime_init(dev_priv
);
990 intel_sanitize_options(dev_priv
);
992 ret
= i915_ggtt_probe_hw(dev_priv
);
996 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
997 * otherwise the vga fbdev driver falls over. */
998 ret
= i915_kick_out_firmware_fb(dev_priv
);
1000 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1004 ret
= i915_kick_out_vgacon(dev_priv
);
1006 DRM_ERROR("failed to remove conflicting VGA console\n");
1010 ret
= i915_ggtt_init_hw(dev_priv
);
1014 ret
= i915_ggtt_enable_hw(dev_priv
);
1016 DRM_ERROR("failed to enable GGTT\n");
1020 pci_set_master(pdev
);
1022 /* overlay on gen2 is broken and can't address above 1G */
1023 if (IS_GEN2(dev_priv
)) {
1024 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1026 DRM_ERROR("failed to set DMA mask\n");
1032 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1033 * using 32bit addressing, overwriting memory if HWS is located
1036 * The documentation also mentions an issue with undefined
1037 * behaviour if any general state is accessed within a page above 4GB,
1038 * which also needs to be handled carefully.
1040 if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
)) {
1041 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1044 DRM_ERROR("failed to set DMA mask\n");
1050 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1051 PM_QOS_DEFAULT_VALUE
);
1053 intel_uncore_sanitize(dev_priv
);
1055 intel_opregion_setup(dev_priv
);
1057 i915_gem_load_init_fences(dev_priv
);
1059 /* On the 945G/GM, the chipset reports the MSI capability on the
1060 * integrated graphics even though the support isn't actually there
1061 * according to the published specs. It doesn't appear to function
1062 * correctly in testing on 945G.
1063 * This may be a side effect of MSI having been made available for PEG
1064 * and the registers being closely associated.
1066 * According to chipset errata, on the 965GM, MSI interrupts may
1067 * be lost or delayed, but we use them anyways to avoid
1068 * stuck interrupts on some machines.
1070 if (!IS_I945G(dev_priv
) && !IS_I945GM(dev_priv
)) {
1071 if (pci_enable_msi(pdev
) < 0)
1072 DRM_DEBUG_DRIVER("can't enable MSI");
1075 ret
= intel_gvt_init(dev_priv
);
1082 i915_ggtt_cleanup_hw(dev_priv
);
1088 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1089 * @dev_priv: device private
1091 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1093 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1095 if (pdev
->msi_enabled
)
1096 pci_disable_msi(pdev
);
1098 pm_qos_remove_request(&dev_priv
->pm_qos
);
1099 i915_ggtt_cleanup_hw(dev_priv
);
1103 * i915_driver_register - register the driver with the rest of the system
1104 * @dev_priv: device private
1106 * Perform any steps necessary to make the driver available via kernel
1107 * internal or userspace interfaces.
1109 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1111 struct drm_device
*dev
= &dev_priv
->drm
;
1113 i915_gem_shrinker_init(dev_priv
);
1116 * Notify a valid surface after modesetting,
1117 * when running inside a VM.
1119 if (intel_vgpu_active(dev_priv
))
1120 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1122 /* Reveal our presence to userspace */
1123 if (drm_dev_register(dev
, 0) == 0) {
1124 i915_debugfs_register(dev_priv
);
1125 i915_guc_log_register(dev_priv
);
1126 i915_setup_sysfs(dev_priv
);
1128 /* Depends on sysfs having been initialized */
1129 i915_perf_register(dev_priv
);
1131 DRM_ERROR("Failed to register driver for userspace access!\n");
1133 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1134 /* Must be done after probing outputs */
1135 intel_opregion_register(dev_priv
);
1136 acpi_video_register();
1139 if (IS_GEN5(dev_priv
))
1140 intel_gpu_ips_init(dev_priv
);
1142 intel_audio_init(dev_priv
);
1145 * Some ports require correctly set-up hpd registers for detection to
1146 * work properly (leading to ghost connected connector status), e.g. VGA
1147 * on gm45. Hence we can only set up the initial fbdev config after hpd
1148 * irqs are fully enabled. We do it last so that the async config
1149 * cannot run before the connectors are registered.
1151 intel_fbdev_initial_config_async(dev
);
1155 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1156 * @dev_priv: device private
1158 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1160 intel_audio_deinit(dev_priv
);
1162 intel_gpu_ips_teardown();
1163 acpi_video_unregister();
1164 intel_opregion_unregister(dev_priv
);
1166 i915_perf_unregister(dev_priv
);
1168 i915_teardown_sysfs(dev_priv
);
1169 i915_guc_log_unregister(dev_priv
);
1170 drm_dev_unregister(&dev_priv
->drm
);
1172 i915_gem_shrinker_cleanup(dev_priv
);
1176 * i915_driver_load - setup chip and create an initial config
1178 * @ent: matching PCI ID entry
1180 * The driver load routine has to do several things:
1181 * - drive output discovery via intel_modeset_init()
1182 * - initialize the memory manager
1183 * - allocate initial config memory
1184 * - setup the DRM framebuffer with the allocated memory
1186 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1188 struct drm_i915_private
*dev_priv
;
1191 if (i915
.nuclear_pageflip
)
1192 driver
.driver_features
|= DRIVER_ATOMIC
;
1195 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1197 ret
= drm_dev_init(&dev_priv
->drm
, &driver
, &pdev
->dev
);
1199 DRM_DEV_ERROR(&pdev
->dev
, "allocation failed\n");
1204 dev_priv
->drm
.pdev
= pdev
;
1205 dev_priv
->drm
.dev_private
= dev_priv
;
1207 ret
= pci_enable_device(pdev
);
1211 pci_set_drvdata(pdev
, &dev_priv
->drm
);
1213 ret
= i915_driver_init_early(dev_priv
, ent
);
1215 goto out_pci_disable
;
1217 intel_runtime_pm_get(dev_priv
);
1219 ret
= i915_driver_init_mmio(dev_priv
);
1221 goto out_runtime_pm_put
;
1223 ret
= i915_driver_init_hw(dev_priv
);
1225 goto out_cleanup_mmio
;
1228 * TODO: move the vblank init and parts of modeset init steps into one
1229 * of the i915_driver_init_/i915_driver_register functions according
1230 * to the role/effect of the given init step.
1232 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1233 ret
= drm_vblank_init(&dev_priv
->drm
,
1234 INTEL_INFO(dev_priv
)->num_pipes
);
1236 goto out_cleanup_hw
;
1239 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1241 goto out_cleanup_vblank
;
1243 i915_driver_register(dev_priv
);
1245 intel_runtime_pm_enable(dev_priv
);
1247 dev_priv
->ipc_enabled
= false;
1249 /* Everything is in place, we can now relax! */
1250 DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1251 driver
.name
, driver
.major
, driver
.minor
, driver
.patchlevel
,
1252 driver
.date
, pci_name(pdev
), dev_priv
->drm
.primary
->index
);
1253 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
1254 DRM_INFO("DRM_I915_DEBUG enabled\n");
1255 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1256 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1258 intel_runtime_pm_put(dev_priv
);
1263 drm_vblank_cleanup(&dev_priv
->drm
);
1265 i915_driver_cleanup_hw(dev_priv
);
1267 i915_driver_cleanup_mmio(dev_priv
);
1269 intel_runtime_pm_put(dev_priv
);
1270 i915_driver_cleanup_early(dev_priv
);
1272 pci_disable_device(pdev
);
1274 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1275 drm_dev_unref(&dev_priv
->drm
);
1279 void i915_driver_unload(struct drm_device
*dev
)
1281 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1282 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1284 intel_fbdev_fini(dev
);
1286 if (i915_gem_suspend(dev_priv
))
1287 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1289 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
1291 intel_gvt_cleanup(dev_priv
);
1293 i915_driver_unregister(dev_priv
);
1295 drm_vblank_cleanup(dev
);
1297 intel_modeset_cleanup(dev
);
1300 * free the memory space allocated for the child device
1301 * config parsed from VBT
1303 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1304 kfree(dev_priv
->vbt
.child_dev
);
1305 dev_priv
->vbt
.child_dev
= NULL
;
1306 dev_priv
->vbt
.child_dev_num
= 0;
1308 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1309 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1310 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1311 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1313 vga_switcheroo_unregister_client(pdev
);
1314 vga_client_register(pdev
, NULL
, NULL
, NULL
);
1316 intel_csr_ucode_fini(dev_priv
);
1318 /* Free error state after interrupts are fully disabled. */
1319 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1320 i915_destroy_error_state(dev_priv
);
1322 /* Flush any outstanding unpin_work. */
1323 drain_workqueue(dev_priv
->wq
);
1325 intel_guc_fini(dev_priv
);
1326 intel_huc_fini(dev_priv
);
1327 i915_gem_fini(dev_priv
);
1328 intel_fbc_cleanup_cfb(dev_priv
);
1330 intel_power_domains_fini(dev_priv
);
1332 i915_driver_cleanup_hw(dev_priv
);
1333 i915_driver_cleanup_mmio(dev_priv
);
1335 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
1337 i915_driver_cleanup_early(dev_priv
);
1340 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1344 ret
= i915_gem_open(dev
, file
);
1352 * i915_driver_lastclose - clean up after all DRM clients have exited
1355 * Take care of cleaning up after all DRM clients have exited. In the
1356 * mode setting case, we want to restore the kernel's initial mode (just
1357 * in case the last client left us in a bad state).
1359 * Additionally, in the non-mode setting case, we'll tear down the GTT
1360 * and DMA structures, since the kernel won't be using them, and clea
1363 static void i915_driver_lastclose(struct drm_device
*dev
)
1365 intel_fbdev_restore_mode(dev
);
1366 vga_switcheroo_process_delayed_switch();
1369 static void i915_driver_preclose(struct drm_device
*dev
, struct drm_file
*file
)
1371 mutex_lock(&dev
->struct_mutex
);
1372 i915_gem_context_close(dev
, file
);
1373 i915_gem_release(dev
, file
);
1374 mutex_unlock(&dev
->struct_mutex
);
1377 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1379 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1384 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1386 struct drm_device
*dev
= &dev_priv
->drm
;
1387 struct intel_encoder
*encoder
;
1389 drm_modeset_lock_all(dev
);
1390 for_each_intel_encoder(dev
, encoder
)
1391 if (encoder
->suspend
)
1392 encoder
->suspend(encoder
);
1393 drm_modeset_unlock_all(dev
);
1396 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1398 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1400 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1402 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1403 if (acpi_target_system_state() < ACPI_STATE_S3
)
1409 static int i915_drm_suspend(struct drm_device
*dev
)
1411 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1412 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1413 pci_power_t opregion_target_state
;
1416 /* ignore lid events during suspend */
1417 mutex_lock(&dev_priv
->modeset_restore_lock
);
1418 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
1419 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1421 disable_rpm_wakeref_asserts(dev_priv
);
1423 /* We do a lot of poking in a lot of registers, make sure they work
1425 intel_display_set_init_power(dev_priv
, true);
1427 drm_kms_helper_poll_disable(dev
);
1429 pci_save_state(pdev
);
1431 error
= i915_gem_suspend(dev_priv
);
1434 "GEM idle failed, resume might fail\n");
1438 intel_guc_suspend(dev_priv
);
1440 intel_display_suspend(dev
);
1442 intel_dp_mst_suspend(dev
);
1444 intel_runtime_pm_disable_interrupts(dev_priv
);
1445 intel_hpd_cancel_work(dev_priv
);
1447 intel_suspend_encoders(dev_priv
);
1449 intel_suspend_hw(dev_priv
);
1451 i915_gem_suspend_gtt_mappings(dev_priv
);
1453 i915_save_state(dev_priv
);
1455 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1456 intel_opregion_notify_adapter(dev_priv
, opregion_target_state
);
1458 intel_uncore_forcewake_reset(dev_priv
, false);
1459 intel_opregion_unregister(dev_priv
);
1461 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1463 dev_priv
->suspend_count
++;
1465 intel_csr_ucode_suspend(dev_priv
);
1468 enable_rpm_wakeref_asserts(dev_priv
);
1473 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1475 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1476 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1480 disable_rpm_wakeref_asserts(dev_priv
);
1482 intel_display_set_init_power(dev_priv
, false);
1484 fw_csr
= !IS_GEN9_LP(dev_priv
) &&
1485 suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
1487 * In case of firmware assisted context save/restore don't manually
1488 * deinit the power domains. This also means the CSR/DMC firmware will
1489 * stay active, it will power down any HW resources as required and
1490 * also enable deeper system power states that would be blocked if the
1491 * firmware was inactive.
1494 intel_power_domains_suspend(dev_priv
);
1497 if (IS_GEN9_LP(dev_priv
))
1498 bxt_enable_dc9(dev_priv
);
1499 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1500 hsw_enable_pc8(dev_priv
);
1501 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1502 ret
= vlv_suspend_complete(dev_priv
);
1505 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1507 intel_power_domains_init_hw(dev_priv
, true);
1512 pci_disable_device(pdev
);
1514 * During hibernation on some platforms the BIOS may try to access
1515 * the device even though it's already in D3 and hang the machine. So
1516 * leave the device in D0 on those platforms and hope the BIOS will
1517 * power down the device properly. The issue was seen on multiple old
1518 * GENs with different BIOS vendors, so having an explicit blacklist
1519 * is inpractical; apply the workaround on everything pre GEN6. The
1520 * platforms where the issue was seen:
1521 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1525 if (!(hibernation
&& INTEL_GEN(dev_priv
) < 6))
1526 pci_set_power_state(pdev
, PCI_D3hot
);
1528 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
1531 enable_rpm_wakeref_asserts(dev_priv
);
1536 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
1541 DRM_ERROR("dev: %p\n", dev
);
1542 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1546 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1547 state
.event
!= PM_EVENT_FREEZE
))
1550 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1553 error
= i915_drm_suspend(dev
);
1557 return i915_drm_suspend_late(dev
, false);
1560 static int i915_drm_resume(struct drm_device
*dev
)
1562 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1565 disable_rpm_wakeref_asserts(dev_priv
);
1566 intel_sanitize_gt_powersave(dev_priv
);
1568 ret
= i915_ggtt_enable_hw(dev_priv
);
1570 DRM_ERROR("failed to re-enable GGTT\n");
1572 intel_csr_ucode_resume(dev_priv
);
1574 i915_gem_resume(dev_priv
);
1576 i915_restore_state(dev_priv
);
1577 intel_pps_unlock_regs_wa(dev_priv
);
1578 intel_opregion_setup(dev_priv
);
1580 intel_init_pch_refclk(dev_priv
);
1583 * Interrupts have to be enabled before any batches are run. If not the
1584 * GPU will hang. i915_gem_init_hw() will initiate batches to
1585 * update/restore the context.
1587 * drm_mode_config_reset() needs AUX interrupts.
1589 * Modeset enabling in intel_modeset_init_hw() also needs working
1592 intel_runtime_pm_enable_interrupts(dev_priv
);
1594 drm_mode_config_reset(dev
);
1596 mutex_lock(&dev
->struct_mutex
);
1597 if (i915_gem_init_hw(dev_priv
)) {
1598 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1599 i915_gem_set_wedged(dev_priv
);
1601 mutex_unlock(&dev
->struct_mutex
);
1603 intel_guc_resume(dev_priv
);
1605 intel_modeset_init_hw(dev
);
1607 spin_lock_irq(&dev_priv
->irq_lock
);
1608 if (dev_priv
->display
.hpd_irq_setup
)
1609 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1610 spin_unlock_irq(&dev_priv
->irq_lock
);
1612 intel_dp_mst_resume(dev
);
1614 intel_display_resume(dev
);
1616 drm_kms_helper_poll_enable(dev
);
1619 * ... but also need to make sure that hotplug processing
1620 * doesn't cause havoc. Like in the driver load code we don't
1621 * bother with the tiny race here where we might loose hotplug
1624 intel_hpd_init(dev_priv
);
1626 intel_opregion_register(dev_priv
);
1628 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1630 mutex_lock(&dev_priv
->modeset_restore_lock
);
1631 dev_priv
->modeset_restore
= MODESET_DONE
;
1632 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1634 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1636 intel_autoenable_gt_powersave(dev_priv
);
1638 enable_rpm_wakeref_asserts(dev_priv
);
1643 static int i915_drm_resume_early(struct drm_device
*dev
)
1645 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1646 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1650 * We have a resume ordering issue with the snd-hda driver also
1651 * requiring our device to be power up. Due to the lack of a
1652 * parent/child relationship we currently solve this with an early
1655 * FIXME: This should be solved with a special hdmi sink device or
1656 * similar so that power domains can be employed.
1660 * Note that we need to set the power state explicitly, since we
1661 * powered off the device during freeze and the PCI core won't power
1662 * it back up for us during thaw. Powering off the device during
1663 * freeze is not a hard requirement though, and during the
1664 * suspend/resume phases the PCI core makes sure we get here with the
1665 * device powered on. So in case we change our freeze logic and keep
1666 * the device powered we can also remove the following set power state
1669 ret
= pci_set_power_state(pdev
, PCI_D0
);
1671 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1676 * Note that pci_enable_device() first enables any parent bridge
1677 * device and only then sets the power state for this device. The
1678 * bridge enabling is a nop though, since bridge devices are resumed
1679 * first. The order of enabling power and enabling the device is
1680 * imposed by the PCI core as described above, so here we preserve the
1681 * same order for the freeze/thaw phases.
1683 * TODO: eventually we should remove pci_disable_device() /
1684 * pci_enable_enable_device() from suspend/resume. Due to how they
1685 * depend on the device enable refcount we can't anyway depend on them
1686 * disabling/enabling the device.
1688 if (pci_enable_device(pdev
)) {
1693 pci_set_master(pdev
);
1695 disable_rpm_wakeref_asserts(dev_priv
);
1697 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1698 ret
= vlv_resume_prepare(dev_priv
, false);
1700 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1703 intel_uncore_early_sanitize(dev_priv
, true);
1705 if (IS_GEN9_LP(dev_priv
)) {
1706 if (!dev_priv
->suspended_to_idle
)
1707 gen9_sanitize_dc_state(dev_priv
);
1708 bxt_disable_dc9(dev_priv
);
1709 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1710 hsw_disable_pc8(dev_priv
);
1713 intel_uncore_sanitize(dev_priv
);
1715 if (IS_GEN9_LP(dev_priv
) ||
1716 !(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
1717 intel_power_domains_init_hw(dev_priv
, true);
1719 enable_rpm_wakeref_asserts(dev_priv
);
1722 dev_priv
->suspended_to_idle
= false;
1727 static int i915_resume_switcheroo(struct drm_device
*dev
)
1731 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1734 ret
= i915_drm_resume_early(dev
);
1738 return i915_drm_resume(dev
);
1742 * i915_reset - reset chip after a hang
1743 * @dev_priv: device private to reset
1745 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1748 * Caller must hold the struct_mutex.
1750 * Procedure is fairly simple:
1751 * - reset the chip using the reset reg
1752 * - re-init context state
1753 * - re-init hardware status page
1754 * - re-init ring buffer
1755 * - re-init interrupt state
1758 void i915_reset(struct drm_i915_private
*dev_priv
)
1760 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
1763 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
1765 if (!test_and_clear_bit(I915_RESET_IN_PROGRESS
, &error
->flags
))
1768 /* Clear any previous failed attempts at recovery. Time to try again. */
1769 __clear_bit(I915_WEDGED
, &error
->flags
);
1770 error
->reset_count
++;
1772 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1773 disable_irq(dev_priv
->drm
.irq
);
1774 ret
= i915_gem_reset_prepare(dev_priv
);
1776 DRM_ERROR("GPU recovery failed\n");
1777 intel_gpu_reset(dev_priv
, ALL_ENGINES
);
1781 ret
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
1784 DRM_ERROR("Failed to reset chip: %i\n", ret
);
1786 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1790 i915_gem_reset_finish(dev_priv
);
1791 intel_overlay_reset(dev_priv
);
1793 /* Ok, now get things going again... */
1796 * Everything depends on having the GTT running, so we need to start
1797 * there. Fortunately we don't need to do this unless we reset the
1798 * chip at a PCI level.
1800 * Next we need to restore the context, but we don't use those
1803 * Ring buffer needs to be re-initialized in the KMS case, or if X
1804 * was running at the time of the reset (i.e. we weren't VT
1807 ret
= i915_gem_init_hw(dev_priv
);
1809 DRM_ERROR("Failed hw init on reset %d\n", ret
);
1813 i915_queue_hangcheck(dev_priv
);
1816 enable_irq(dev_priv
->drm
.irq
);
1817 wake_up_bit(&error
->flags
, I915_RESET_IN_PROGRESS
);
1821 i915_gem_set_wedged(dev_priv
);
1825 static int i915_pm_suspend(struct device
*kdev
)
1827 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1828 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1831 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
1835 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1838 return i915_drm_suspend(dev
);
1841 static int i915_pm_suspend_late(struct device
*kdev
)
1843 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1846 * We have a suspend ordering issue with the snd-hda driver also
1847 * requiring our device to be power up. Due to the lack of a
1848 * parent/child relationship we currently solve this with an late
1851 * FIXME: This should be solved with a special hdmi sink device or
1852 * similar so that power domains can be employed.
1854 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1857 return i915_drm_suspend_late(dev
, false);
1860 static int i915_pm_poweroff_late(struct device
*kdev
)
1862 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1864 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1867 return i915_drm_suspend_late(dev
, true);
1870 static int i915_pm_resume_early(struct device
*kdev
)
1872 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1874 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1877 return i915_drm_resume_early(dev
);
1880 static int i915_pm_resume(struct device
*kdev
)
1882 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1884 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1887 return i915_drm_resume(dev
);
1890 /* freeze: before creating the hibernation_image */
1891 static int i915_pm_freeze(struct device
*kdev
)
1895 ret
= i915_pm_suspend(kdev
);
1899 ret
= i915_gem_freeze(kdev_to_i915(kdev
));
1906 static int i915_pm_freeze_late(struct device
*kdev
)
1910 ret
= i915_pm_suspend_late(kdev
);
1914 ret
= i915_gem_freeze_late(kdev_to_i915(kdev
));
1921 /* thaw: called after creating the hibernation image, but before turning off. */
1922 static int i915_pm_thaw_early(struct device
*kdev
)
1924 return i915_pm_resume_early(kdev
);
1927 static int i915_pm_thaw(struct device
*kdev
)
1929 return i915_pm_resume(kdev
);
1932 /* restore: called after loading the hibernation image. */
1933 static int i915_pm_restore_early(struct device
*kdev
)
1935 return i915_pm_resume_early(kdev
);
1938 static int i915_pm_restore(struct device
*kdev
)
1940 return i915_pm_resume(kdev
);
1944 * Save all Gunit registers that may be lost after a D3 and a subsequent
1945 * S0i[R123] transition. The list of registers needing a save/restore is
1946 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1947 * registers in the following way:
1948 * - Driver: saved/restored by the driver
1949 * - Punit : saved/restored by the Punit firmware
1950 * - No, w/o marking: no need to save/restore, since the register is R/O or
1951 * used internally by the HW in a way that doesn't depend
1952 * keeping the content across a suspend/resume.
1953 * - Debug : used for debugging
1955 * We save/restore all registers marked with 'Driver', with the following
1957 * - Registers out of use, including also registers marked with 'Debug'.
1958 * These have no effect on the driver's operation, so we don't save/restore
1959 * them to reduce the overhead.
1960 * - Registers that are fully setup by an initialization function called from
1961 * the resume path. For example many clock gating and RPS/RC6 registers.
1962 * - Registers that provide the right functionality with their reset defaults.
1964 * TODO: Except for registers that based on the above 3 criteria can be safely
1965 * ignored, we save/restore all others, practically treating the HW context as
1966 * a black-box for the driver. Further investigation is needed to reduce the
1967 * saved/restored registers even further, by following the same 3 criteria.
1969 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1971 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1974 /* GAM 0x4000-0x4770 */
1975 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1976 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1977 s
->arb_mode
= I915_READ(ARB_MODE
);
1978 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1979 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1981 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1982 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
1984 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1985 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1987 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1988 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1989 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1990 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1992 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1994 /* MBC 0x9024-0x91D0, 0x8500 */
1995 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1996 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1997 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1999 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2000 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2001 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2002 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2003 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2004 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2005 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2007 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2008 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2009 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2010 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2011 s
->ecobus
= I915_READ(ECOBUS
);
2012 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2013 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2014 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2015 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2016 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2017 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2019 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2020 s
->gt_imr
= I915_READ(GTIMR
);
2021 s
->gt_ier
= I915_READ(GTIER
);
2022 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2023 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2025 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2026 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2028 /* GT SA CZ domain, 0x100000-0x138124 */
2029 s
->tilectl
= I915_READ(TILECTL
);
2030 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2031 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2032 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2033 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2035 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2036 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2037 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2038 s
->pcbr
= I915_READ(VLV_PCBR
);
2039 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2042 * Not saving any of:
2043 * DFT, 0x9800-0x9EC0
2044 * SARB, 0xB000-0xB1FC
2045 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2050 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2052 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2056 /* GAM 0x4000-0x4770 */
2057 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2058 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2059 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2060 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2061 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2063 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2064 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2066 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2067 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2069 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2070 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2071 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2072 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2074 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2076 /* MBC 0x9024-0x91D0, 0x8500 */
2077 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2078 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2079 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2081 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2082 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2083 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2084 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2085 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2086 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2087 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2089 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2090 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2091 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2092 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2093 I915_WRITE(ECOBUS
, s
->ecobus
);
2094 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2095 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2096 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2097 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2098 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2099 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2101 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2102 I915_WRITE(GTIMR
, s
->gt_imr
);
2103 I915_WRITE(GTIER
, s
->gt_ier
);
2104 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2105 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2107 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2108 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2110 /* GT SA CZ domain, 0x100000-0x138124 */
2111 I915_WRITE(TILECTL
, s
->tilectl
);
2112 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2114 * Preserve the GT allow wake and GFX force clock bit, they are not
2115 * be restored, as they are used to control the s0ix suspend/resume
2116 * sequence by the caller.
2118 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2119 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2120 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2121 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2123 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2124 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2125 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2126 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2128 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2130 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2131 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2132 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2133 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2134 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2137 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2142 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2143 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2145 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2146 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2151 err
= intel_wait_for_register(dev_priv
,
2152 VLV_GTLC_SURVIVABILITY_REG
,
2153 VLV_GFX_CLK_STATUS_BIT
,
2154 VLV_GFX_CLK_STATUS_BIT
,
2157 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2158 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2163 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2168 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2169 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2171 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2172 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2173 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2175 err
= intel_wait_for_register(dev_priv
,
2177 VLV_GTLC_ALLOWWAKEACK
,
2181 DRM_ERROR("timeout disabling GT waking\n");
2186 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2193 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2194 val
= wait_for_on
? mask
: 0;
2195 if ((I915_READ(VLV_GTLC_PW_STATUS
) & mask
) == val
)
2198 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2200 I915_READ(VLV_GTLC_PW_STATUS
));
2203 * RC6 transitioning can be delayed up to 2 msec (see
2204 * valleyview_enable_rps), use 3 msec for safety.
2206 err
= intel_wait_for_register(dev_priv
,
2207 VLV_GTLC_PW_STATUS
, mask
, val
,
2210 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2211 onoff(wait_for_on
));
2216 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2218 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2221 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2222 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2225 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2231 * Bspec defines the following GT well on flags as debug only, so
2232 * don't treat them as hard failures.
2234 (void)vlv_wait_for_gt_wells(dev_priv
, false);
2236 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2237 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2239 vlv_check_no_gt_access(dev_priv
);
2241 err
= vlv_force_gfx_clock(dev_priv
, true);
2245 err
= vlv_allow_gt_wake(dev_priv
, false);
2249 if (!IS_CHERRYVIEW(dev_priv
))
2250 vlv_save_gunit_s0ix_state(dev_priv
);
2252 err
= vlv_force_gfx_clock(dev_priv
, false);
2259 /* For safety always re-enable waking and disable gfx clock forcing */
2260 vlv_allow_gt_wake(dev_priv
, true);
2262 vlv_force_gfx_clock(dev_priv
, false);
2267 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2274 * If any of the steps fail just try to continue, that's the best we
2275 * can do at this point. Return the first error code (which will also
2276 * leave RPM permanently disabled).
2278 ret
= vlv_force_gfx_clock(dev_priv
, true);
2280 if (!IS_CHERRYVIEW(dev_priv
))
2281 vlv_restore_gunit_s0ix_state(dev_priv
);
2283 err
= vlv_allow_gt_wake(dev_priv
, true);
2287 err
= vlv_force_gfx_clock(dev_priv
, false);
2291 vlv_check_no_gt_access(dev_priv
);
2294 intel_init_clock_gating(dev_priv
);
2299 static int intel_runtime_suspend(struct device
*kdev
)
2301 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2302 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2303 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2306 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6())))
2309 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2312 DRM_DEBUG_KMS("Suspending device\n");
2314 disable_rpm_wakeref_asserts(dev_priv
);
2317 * We are safe here against re-faults, since the fault handler takes
2320 i915_gem_runtime_suspend(dev_priv
);
2322 intel_guc_suspend(dev_priv
);
2324 intel_runtime_pm_disable_interrupts(dev_priv
);
2327 if (IS_GEN9_LP(dev_priv
)) {
2328 bxt_display_core_uninit(dev_priv
);
2329 bxt_enable_dc9(dev_priv
);
2330 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2331 hsw_enable_pc8(dev_priv
);
2332 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2333 ret
= vlv_suspend_complete(dev_priv
);
2337 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2338 intel_runtime_pm_enable_interrupts(dev_priv
);
2340 enable_rpm_wakeref_asserts(dev_priv
);
2345 intel_uncore_forcewake_reset(dev_priv
, false);
2347 enable_rpm_wakeref_asserts(dev_priv
);
2348 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2350 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
2351 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2353 dev_priv
->pm
.suspended
= true;
2356 * FIXME: We really should find a document that references the arguments
2359 if (IS_BROADWELL(dev_priv
)) {
2361 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2362 * being detected, and the call we do at intel_runtime_resume()
2363 * won't be able to restore them. Since PCI_D3hot matches the
2364 * actual specification and appears to be working, use it.
2366 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2369 * current versions of firmware which depend on this opregion
2370 * notification have repurposed the D1 definition to mean
2371 * "runtime suspended" vs. what you would normally expect (D3)
2372 * to distinguish it from notifications that might be sent via
2375 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2378 assert_forcewakes_inactive(dev_priv
);
2380 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2381 intel_hpd_poll_init(dev_priv
);
2383 DRM_DEBUG_KMS("Device suspended\n");
2387 static int intel_runtime_resume(struct device
*kdev
)
2389 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2390 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2391 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2394 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2397 DRM_DEBUG_KMS("Resuming device\n");
2399 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2400 disable_rpm_wakeref_asserts(dev_priv
);
2402 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2403 dev_priv
->pm
.suspended
= false;
2404 if (intel_uncore_unclaimed_mmio(dev_priv
))
2405 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2407 intel_guc_resume(dev_priv
);
2409 if (IS_GEN6(dev_priv
))
2410 intel_init_pch_refclk(dev_priv
);
2412 if (IS_GEN9_LP(dev_priv
)) {
2413 bxt_disable_dc9(dev_priv
);
2414 bxt_display_core_init(dev_priv
, true);
2415 if (dev_priv
->csr
.dmc_payload
&&
2416 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
2417 gen9_enable_dc5(dev_priv
);
2418 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2419 hsw_disable_pc8(dev_priv
);
2420 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2421 ret
= vlv_resume_prepare(dev_priv
, true);
2425 * No point of rolling back things in case of an error, as the best
2426 * we can do is to hope that things will still work (and disable RPM).
2428 i915_gem_init_swizzling(dev_priv
);
2429 i915_gem_restore_fences(dev_priv
);
2431 intel_runtime_pm_enable_interrupts(dev_priv
);
2434 * On VLV/CHV display interrupts are part of the display
2435 * power well, so hpd is reinitialized from there. For
2436 * everyone else do it here.
2438 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2439 intel_hpd_init(dev_priv
);
2441 enable_rpm_wakeref_asserts(dev_priv
);
2444 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2446 DRM_DEBUG_KMS("Device resumed\n");
2451 const struct dev_pm_ops i915_pm_ops
= {
2453 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2456 .suspend
= i915_pm_suspend
,
2457 .suspend_late
= i915_pm_suspend_late
,
2458 .resume_early
= i915_pm_resume_early
,
2459 .resume
= i915_pm_resume
,
2463 * @freeze, @freeze_late : called (1) before creating the
2464 * hibernation image [PMSG_FREEZE] and
2465 * (2) after rebooting, before restoring
2466 * the image [PMSG_QUIESCE]
2467 * @thaw, @thaw_early : called (1) after creating the hibernation
2468 * image, before writing it [PMSG_THAW]
2469 * and (2) after failing to create or
2470 * restore the image [PMSG_RECOVER]
2471 * @poweroff, @poweroff_late: called after writing the hibernation
2472 * image, before rebooting [PMSG_HIBERNATE]
2473 * @restore, @restore_early : called after rebooting and restoring the
2474 * hibernation image [PMSG_RESTORE]
2476 .freeze
= i915_pm_freeze
,
2477 .freeze_late
= i915_pm_freeze_late
,
2478 .thaw_early
= i915_pm_thaw_early
,
2479 .thaw
= i915_pm_thaw
,
2480 .poweroff
= i915_pm_suspend
,
2481 .poweroff_late
= i915_pm_poweroff_late
,
2482 .restore_early
= i915_pm_restore_early
,
2483 .restore
= i915_pm_restore
,
2485 /* S0ix (via runtime suspend) event handlers */
2486 .runtime_suspend
= intel_runtime_suspend
,
2487 .runtime_resume
= intel_runtime_resume
,
2490 static const struct vm_operations_struct i915_gem_vm_ops
= {
2491 .fault
= i915_gem_fault
,
2492 .open
= drm_gem_vm_open
,
2493 .close
= drm_gem_vm_close
,
2496 static const struct file_operations i915_driver_fops
= {
2497 .owner
= THIS_MODULE
,
2499 .release
= drm_release
,
2500 .unlocked_ioctl
= drm_ioctl
,
2501 .mmap
= drm_gem_mmap
,
2504 .compat_ioctl
= i915_compat_ioctl
,
2505 .llseek
= noop_llseek
,
2509 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2510 struct drm_file
*file
)
2515 static const struct drm_ioctl_desc i915_ioctls
[] = {
2516 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2517 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2518 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2519 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2520 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2521 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2522 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2523 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2524 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2525 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2526 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2527 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2528 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2529 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2530 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2531 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2532 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2533 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2534 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
2535 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2536 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2537 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2538 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2539 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2540 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2541 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2542 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2543 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2544 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2545 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2546 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2547 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2548 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
2549 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2550 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2551 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
2552 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
2553 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2554 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
2555 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2556 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2557 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2558 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2559 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2560 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2561 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2562 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2563 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2564 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2565 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2566 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2567 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2568 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
2571 static struct drm_driver driver
= {
2572 /* Don't use MTRRs here; the Xserver or userspace app should
2573 * deal with them for Intel hardware.
2576 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
2577 DRIVER_RENDER
| DRIVER_MODESET
,
2578 .open
= i915_driver_open
,
2579 .lastclose
= i915_driver_lastclose
,
2580 .preclose
= i915_driver_preclose
,
2581 .postclose
= i915_driver_postclose
,
2582 .set_busid
= drm_pci_set_busid
,
2584 .gem_close_object
= i915_gem_close_object
,
2585 .gem_free_object_unlocked
= i915_gem_free_object
,
2586 .gem_vm_ops
= &i915_gem_vm_ops
,
2588 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2589 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2590 .gem_prime_export
= i915_gem_prime_export
,
2591 .gem_prime_import
= i915_gem_prime_import
,
2593 .dumb_create
= i915_gem_dumb_create
,
2594 .dumb_map_offset
= i915_gem_mmap_gtt
,
2595 .dumb_destroy
= drm_gem_dumb_destroy
,
2596 .ioctls
= i915_ioctls
,
2597 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2598 .fops
= &i915_driver_fops
,
2599 .name
= DRIVER_NAME
,
2600 .desc
= DRIVER_DESC
,
2601 .date
= DRIVER_DATE
,
2602 .major
= DRIVER_MAJOR
,
2603 .minor
= DRIVER_MINOR
,
2604 .patchlevel
= DRIVER_PATCHLEVEL
,