1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver
;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 static const struct intel_device_info intel_i830_info
= {
67 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
68 .has_overlay
= 1, .overlay_needs_physical
= 1,
69 .ring_mask
= RENDER_RING
,
70 GEN_DEFAULT_PIPEOFFSETS
,
74 static const struct intel_device_info intel_845g_info
= {
75 .gen
= 2, .num_pipes
= 1,
76 .has_overlay
= 1, .overlay_needs_physical
= 1,
77 .ring_mask
= RENDER_RING
,
78 GEN_DEFAULT_PIPEOFFSETS
,
82 static const struct intel_device_info intel_i85x_info
= {
83 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
84 .cursor_needs_physical
= 1,
85 .has_overlay
= 1, .overlay_needs_physical
= 1,
87 .ring_mask
= RENDER_RING
,
88 GEN_DEFAULT_PIPEOFFSETS
,
92 static const struct intel_device_info intel_i865g_info
= {
93 .gen
= 2, .num_pipes
= 1,
94 .has_overlay
= 1, .overlay_needs_physical
= 1,
95 .ring_mask
= RENDER_RING
,
96 GEN_DEFAULT_PIPEOFFSETS
,
100 static const struct intel_device_info intel_i915g_info
= {
101 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
102 .has_overlay
= 1, .overlay_needs_physical
= 1,
103 .ring_mask
= RENDER_RING
,
104 GEN_DEFAULT_PIPEOFFSETS
,
107 static const struct intel_device_info intel_i915gm_info
= {
108 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
109 .cursor_needs_physical
= 1,
110 .has_overlay
= 1, .overlay_needs_physical
= 1,
113 .ring_mask
= RENDER_RING
,
114 GEN_DEFAULT_PIPEOFFSETS
,
117 static const struct intel_device_info intel_i945g_info
= {
118 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
119 .has_overlay
= 1, .overlay_needs_physical
= 1,
120 .ring_mask
= RENDER_RING
,
121 GEN_DEFAULT_PIPEOFFSETS
,
124 static const struct intel_device_info intel_i945gm_info
= {
125 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
126 .has_hotplug
= 1, .cursor_needs_physical
= 1,
127 .has_overlay
= 1, .overlay_needs_physical
= 1,
130 .ring_mask
= RENDER_RING
,
131 GEN_DEFAULT_PIPEOFFSETS
,
135 static const struct intel_device_info intel_i965g_info
= {
136 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
139 .ring_mask
= RENDER_RING
,
140 GEN_DEFAULT_PIPEOFFSETS
,
144 static const struct intel_device_info intel_i965gm_info
= {
145 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
146 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
149 .ring_mask
= RENDER_RING
,
150 GEN_DEFAULT_PIPEOFFSETS
,
154 static const struct intel_device_info intel_g33_info
= {
155 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
156 .need_gfx_hws
= 1, .has_hotplug
= 1,
158 .ring_mask
= RENDER_RING
,
159 GEN_DEFAULT_PIPEOFFSETS
,
163 static const struct intel_device_info intel_g45_info
= {
164 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
165 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
166 .ring_mask
= RENDER_RING
| BSD_RING
,
167 GEN_DEFAULT_PIPEOFFSETS
,
171 static const struct intel_device_info intel_gm45_info
= {
172 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
173 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
174 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
176 .ring_mask
= RENDER_RING
| BSD_RING
,
177 GEN_DEFAULT_PIPEOFFSETS
,
181 static const struct intel_device_info intel_pineview_info
= {
182 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
183 .need_gfx_hws
= 1, .has_hotplug
= 1,
185 GEN_DEFAULT_PIPEOFFSETS
,
189 static const struct intel_device_info intel_ironlake_d_info
= {
190 .gen
= 5, .num_pipes
= 2,
191 .need_gfx_hws
= 1, .has_hotplug
= 1,
192 .ring_mask
= RENDER_RING
| BSD_RING
,
193 GEN_DEFAULT_PIPEOFFSETS
,
197 static const struct intel_device_info intel_ironlake_m_info
= {
198 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
199 .need_gfx_hws
= 1, .has_hotplug
= 1,
201 .ring_mask
= RENDER_RING
| BSD_RING
,
202 GEN_DEFAULT_PIPEOFFSETS
,
206 static const struct intel_device_info intel_sandybridge_d_info
= {
207 .gen
= 6, .num_pipes
= 2,
208 .need_gfx_hws
= 1, .has_hotplug
= 1,
210 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
212 GEN_DEFAULT_PIPEOFFSETS
,
216 static const struct intel_device_info intel_sandybridge_m_info
= {
217 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
218 .need_gfx_hws
= 1, .has_hotplug
= 1,
220 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
222 GEN_DEFAULT_PIPEOFFSETS
,
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
233 static const struct intel_device_info intel_ivybridge_d_info
= {
236 GEN_DEFAULT_PIPEOFFSETS
,
240 static const struct intel_device_info intel_ivybridge_m_info
= {
244 GEN_DEFAULT_PIPEOFFSETS
,
248 static const struct intel_device_info intel_ivybridge_q_info
= {
251 .num_pipes
= 0, /* legal, last one wins */
252 GEN_DEFAULT_PIPEOFFSETS
,
256 static const struct intel_device_info intel_valleyview_m_info
= {
261 .display_mmio_offset
= VLV_DISPLAY_BASE
,
262 .has_fbc
= 0, /* legal, last one wins */
263 .has_llc
= 0, /* legal, last one wins */
264 GEN_DEFAULT_PIPEOFFSETS
,
268 static const struct intel_device_info intel_valleyview_d_info
= {
272 .display_mmio_offset
= VLV_DISPLAY_BASE
,
273 .has_fbc
= 0, /* legal, last one wins */
274 .has_llc
= 0, /* legal, last one wins */
275 GEN_DEFAULT_PIPEOFFSETS
,
279 static const struct intel_device_info intel_haswell_d_info
= {
284 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
285 GEN_DEFAULT_PIPEOFFSETS
,
289 static const struct intel_device_info intel_haswell_m_info
= {
295 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
296 GEN_DEFAULT_PIPEOFFSETS
,
300 static const struct intel_device_info intel_broadwell_d_info
= {
301 .gen
= 8, .num_pipes
= 3,
302 .need_gfx_hws
= 1, .has_hotplug
= 1,
303 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
308 GEN_DEFAULT_PIPEOFFSETS
,
312 static const struct intel_device_info intel_broadwell_m_info
= {
313 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
314 .need_gfx_hws
= 1, .has_hotplug
= 1,
315 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
320 GEN_DEFAULT_PIPEOFFSETS
,
324 static const struct intel_device_info intel_broadwell_gt3d_info
= {
325 .gen
= 8, .num_pipes
= 3,
326 .need_gfx_hws
= 1, .has_hotplug
= 1,
327 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
332 GEN_DEFAULT_PIPEOFFSETS
,
336 static const struct intel_device_info intel_broadwell_gt3m_info
= {
337 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
338 .need_gfx_hws
= 1, .has_hotplug
= 1,
339 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
344 GEN_DEFAULT_PIPEOFFSETS
,
348 static const struct intel_device_info intel_cherryview_info
= {
350 .gen
= 8, .num_pipes
= 3,
351 .need_gfx_hws
= 1, .has_hotplug
= 1,
352 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
354 .display_mmio_offset
= VLV_DISPLAY_BASE
,
359 static const struct intel_device_info intel_skylake_info
= {
362 .gen
= 9, .num_pipes
= 3,
363 .need_gfx_hws
= 1, .has_hotplug
= 1,
364 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
368 GEN_DEFAULT_PIPEOFFSETS
,
372 static const struct intel_device_info intel_skylake_gt3_info
= {
375 .gen
= 9, .num_pipes
= 3,
376 .need_gfx_hws
= 1, .has_hotplug
= 1,
377 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
381 GEN_DEFAULT_PIPEOFFSETS
,
386 * Make sure any device matches here are from most specific to most
387 * general. For example, since the Quanta match is based on the subsystem
388 * and subvendor IDs, we need it to come before the more general IVB
389 * PCI ID matches, otherwise we'll use the wrong info struct above.
391 #define INTEL_PCI_IDS \
392 INTEL_I830_IDS(&intel_i830_info), \
393 INTEL_I845G_IDS(&intel_845g_info), \
394 INTEL_I85X_IDS(&intel_i85x_info), \
395 INTEL_I865G_IDS(&intel_i865g_info), \
396 INTEL_I915G_IDS(&intel_i915g_info), \
397 INTEL_I915GM_IDS(&intel_i915gm_info), \
398 INTEL_I945G_IDS(&intel_i945g_info), \
399 INTEL_I945GM_IDS(&intel_i945gm_info), \
400 INTEL_I965G_IDS(&intel_i965g_info), \
401 INTEL_G33_IDS(&intel_g33_info), \
402 INTEL_I965GM_IDS(&intel_i965gm_info), \
403 INTEL_GM45_IDS(&intel_gm45_info), \
404 INTEL_G45_IDS(&intel_g45_info), \
405 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
406 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
407 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
408 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
409 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
410 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
411 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
412 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
413 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
414 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
415 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
416 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
417 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
418 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
419 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
420 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
421 INTEL_CHV_IDS(&intel_cherryview_info), \
422 INTEL_SKL_GT1_IDS(&intel_skylake_info), \
423 INTEL_SKL_GT2_IDS(&intel_skylake_info), \
424 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info) \
426 static const struct pci_device_id pciidlist[] = { /* aka */
431 #if defined(CONFIG_DRM_I915_KMS)
432 MODULE_DEVICE_TABLE(pci
, pciidlist
);
435 void intel_detect_pch(struct drm_device
*dev
)
437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
438 struct pci_dev
*pch
= NULL
;
440 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
441 * (which really amounts to a PCH but no South Display).
443 if (INTEL_INFO(dev
)->num_pipes
== 0) {
444 dev_priv
->pch_type
= PCH_NOP
;
449 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
450 * make graphics device passthrough work easy for VMM, that only
451 * need to expose ISA bridge to let driver know the real hardware
452 * underneath. This is a requirement from virtualization team.
454 * In some virtualized environments (e.g. XEN), there is irrelevant
455 * ISA bridge in the system. To work reliably, we should scan trhough
456 * all the ISA bridge devices and check for the first match, instead
457 * of only checking the first one.
459 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
460 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
461 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
462 dev_priv
->pch_id
= id
;
464 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
465 dev_priv
->pch_type
= PCH_IBX
;
466 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
467 WARN_ON(!IS_GEN5(dev
));
468 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
469 dev_priv
->pch_type
= PCH_CPT
;
470 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
471 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
472 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
473 /* PantherPoint is CPT compatible */
474 dev_priv
->pch_type
= PCH_CPT
;
475 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
476 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
477 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
478 dev_priv
->pch_type
= PCH_LPT
;
479 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
480 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
481 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
482 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
483 dev_priv
->pch_type
= PCH_LPT
;
484 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
485 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
486 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
487 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
488 dev_priv
->pch_type
= PCH_SPT
;
489 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
490 WARN_ON(!IS_SKYLAKE(dev
));
491 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
492 dev_priv
->pch_type
= PCH_SPT
;
493 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
494 WARN_ON(!IS_SKYLAKE(dev
));
502 DRM_DEBUG_KMS("No PCH found.\n");
507 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
509 if (INTEL_INFO(dev
)->gen
< 6)
512 if (i915
.semaphores
>= 0)
513 return i915
.semaphores
;
515 /* TODO: make semaphores and Execlists play nicely together */
516 if (i915
.enable_execlists
)
519 /* Until we get further testing... */
523 #ifdef CONFIG_INTEL_IOMMU
524 /* Enable semaphores on SNB when IO remapping is off */
525 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
532 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
)
534 spin_lock_irq(&dev_priv
->irq_lock
);
536 dev_priv
->long_hpd_port_mask
= 0;
537 dev_priv
->short_hpd_port_mask
= 0;
538 dev_priv
->hpd_event_bits
= 0;
540 spin_unlock_irq(&dev_priv
->irq_lock
);
542 cancel_work_sync(&dev_priv
->dig_port_work
);
543 cancel_work_sync(&dev_priv
->hotplug_work
);
544 cancel_delayed_work_sync(&dev_priv
->hotplug_reenable_work
);
547 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
549 struct drm_device
*dev
= dev_priv
->dev
;
550 struct drm_encoder
*encoder
;
552 drm_modeset_lock_all(dev
);
553 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
554 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
556 if (intel_encoder
->suspend
)
557 intel_encoder
->suspend(intel_encoder
);
559 drm_modeset_unlock_all(dev
);
562 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
);
563 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
566 static int i915_drm_suspend(struct drm_device
*dev
)
568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
569 struct drm_crtc
*crtc
;
570 pci_power_t opregion_target_state
;
573 /* ignore lid events during suspend */
574 mutex_lock(&dev_priv
->modeset_restore_lock
);
575 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
576 mutex_unlock(&dev_priv
->modeset_restore_lock
);
578 /* We do a lot of poking in a lot of registers, make sure they work
580 intel_display_set_init_power(dev_priv
, true);
582 drm_kms_helper_poll_disable(dev
);
584 pci_save_state(dev
->pdev
);
586 error
= i915_gem_suspend(dev
);
588 dev_err(&dev
->pdev
->dev
,
589 "GEM idle failed, resume might fail\n");
593 intel_suspend_gt_powersave(dev
);
596 * Disable CRTCs directly since we want to preserve sw state
597 * for _thaw. Also, power gate the CRTC power wells.
599 drm_modeset_lock_all(dev
);
600 for_each_crtc(dev
, crtc
)
601 intel_crtc_control(crtc
, false);
602 drm_modeset_unlock_all(dev
);
604 intel_dp_mst_suspend(dev
);
606 intel_runtime_pm_disable_interrupts(dev_priv
);
607 intel_hpd_cancel_work(dev_priv
);
609 intel_suspend_encoders(dev_priv
);
611 intel_suspend_hw(dev
);
613 i915_gem_suspend_gtt_mappings(dev
);
615 i915_save_state(dev
);
617 opregion_target_state
= PCI_D3cold
;
618 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
619 if (acpi_target_system_state() < ACPI_STATE_S3
)
620 opregion_target_state
= PCI_D1
;
622 intel_opregion_notify_adapter(dev
, opregion_target_state
);
624 intel_uncore_forcewake_reset(dev
, false);
625 intel_opregion_fini(dev
);
627 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
629 dev_priv
->suspend_count
++;
631 intel_display_set_init_power(dev_priv
, false);
636 static int i915_drm_suspend_late(struct drm_device
*drm_dev
)
638 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
641 ret
= intel_suspend_complete(dev_priv
);
644 DRM_ERROR("Suspend complete failed: %d\n", ret
);
649 pci_disable_device(drm_dev
->pdev
);
650 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
655 int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
)
659 if (!dev
|| !dev
->dev_private
) {
660 DRM_ERROR("dev: %p\n", dev
);
661 DRM_ERROR("DRM not initialized, aborting suspend.\n");
665 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
666 state
.event
!= PM_EVENT_FREEZE
))
669 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
672 error
= i915_drm_suspend(dev
);
676 return i915_drm_suspend_late(dev
);
679 static int i915_drm_resume(struct drm_device
*dev
)
681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
683 mutex_lock(&dev
->struct_mutex
);
684 i915_gem_restore_gtt_mappings(dev
);
685 mutex_unlock(&dev
->struct_mutex
);
687 i915_restore_state(dev
);
688 intel_opregion_setup(dev
);
690 intel_init_pch_refclk(dev
);
691 drm_mode_config_reset(dev
);
693 mutex_lock(&dev
->struct_mutex
);
694 if (i915_gem_init_hw(dev
)) {
695 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
696 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
698 mutex_unlock(&dev
->struct_mutex
);
700 /* We need working interrupts for modeset enabling ... */
701 intel_runtime_pm_enable_interrupts(dev_priv
);
703 intel_modeset_init_hw(dev
);
705 spin_lock_irq(&dev_priv
->irq_lock
);
706 if (dev_priv
->display
.hpd_irq_setup
)
707 dev_priv
->display
.hpd_irq_setup(dev
);
708 spin_unlock_irq(&dev_priv
->irq_lock
);
710 drm_modeset_lock_all(dev
);
711 intel_modeset_setup_hw_state(dev
, true);
712 drm_modeset_unlock_all(dev
);
714 intel_dp_mst_resume(dev
);
717 * ... but also need to make sure that hotplug processing
718 * doesn't cause havoc. Like in the driver load code we don't
719 * bother with the tiny race here where we might loose hotplug
722 intel_hpd_init(dev_priv
);
723 /* Config may have changed between suspend and resume */
724 drm_helper_hpd_irq_event(dev
);
726 intel_opregion_init(dev
);
728 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
730 mutex_lock(&dev_priv
->modeset_restore_lock
);
731 dev_priv
->modeset_restore
= MODESET_DONE
;
732 mutex_unlock(&dev_priv
->modeset_restore_lock
);
734 intel_opregion_notify_adapter(dev
, PCI_D0
);
736 drm_kms_helper_poll_enable(dev
);
741 static int i915_drm_resume_early(struct drm_device
*dev
)
743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
747 * We have a resume ordering issue with the snd-hda driver also
748 * requiring our device to be power up. Due to the lack of a
749 * parent/child relationship we currently solve this with an early
752 * FIXME: This should be solved with a special hdmi sink device or
753 * similar so that power domains can be employed.
755 if (pci_enable_device(dev
->pdev
))
758 pci_set_master(dev
->pdev
);
760 if (IS_VALLEYVIEW(dev_priv
))
761 ret
= vlv_resume_prepare(dev_priv
, false);
763 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret
);
765 intel_uncore_early_sanitize(dev
, true);
767 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
768 hsw_disable_pc8(dev_priv
);
770 intel_uncore_sanitize(dev
);
771 intel_power_domains_init_hw(dev_priv
);
776 int i915_resume_legacy(struct drm_device
*dev
)
780 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
783 ret
= i915_drm_resume_early(dev
);
787 return i915_drm_resume(dev
);
791 * i915_reset - reset chip after a hang
792 * @dev: drm device to reset
794 * Reset the chip. Useful if a hang is detected. Returns zero on successful
795 * reset or otherwise an error code.
797 * Procedure is fairly simple:
798 * - reset the chip using the reset reg
799 * - re-init context state
800 * - re-init hardware status page
801 * - re-init ring buffer
802 * - re-init interrupt state
805 int i915_reset(struct drm_device
*dev
)
807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
814 intel_reset_gt_powersave(dev
);
816 mutex_lock(&dev
->struct_mutex
);
820 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
822 ret
= intel_gpu_reset(dev
);
824 /* Also reset the gpu hangman. */
826 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
827 dev_priv
->gpu_error
.stop_rings
= 0;
828 if (ret
== -ENODEV
) {
829 DRM_INFO("Reset not implemented, but ignoring "
830 "error for simulated gpu hangs\n");
835 if (i915_stop_ring_allow_warn(dev_priv
))
836 pr_notice("drm/i915: Resetting chip after gpu hang\n");
839 DRM_ERROR("Failed to reset chip: %i\n", ret
);
840 mutex_unlock(&dev
->struct_mutex
);
844 intel_overlay_reset(dev_priv
);
846 /* Ok, now get things going again... */
849 * Everything depends on having the GTT running, so we need to start
850 * there. Fortunately we don't need to do this unless we reset the
851 * chip at a PCI level.
853 * Next we need to restore the context, but we don't use those
856 * Ring buffer needs to be re-initialized in the KMS case, or if X
857 * was running at the time of the reset (i.e. we weren't VT
861 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
862 dev_priv
->gpu_error
.reload_in_reset
= true;
864 ret
= i915_gem_init_hw(dev
);
866 dev_priv
->gpu_error
.reload_in_reset
= false;
868 mutex_unlock(&dev
->struct_mutex
);
870 DRM_ERROR("Failed hw init on reset %d\n", ret
);
875 * FIXME: This races pretty badly against concurrent holders of
876 * ring interrupts. This is possible since we've started to drop
877 * dev->struct_mutex in select places when waiting for the gpu.
881 * rps/rc6 re-init is necessary to restore state lost after the
882 * reset and the re-install of gt irqs. Skip for ironlake per
883 * previous concerns that it doesn't respond well to some forms
884 * of re-init after reset.
886 if (INTEL_INFO(dev
)->gen
> 5)
887 intel_enable_gt_powersave(dev
);
892 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
894 struct intel_device_info
*intel_info
=
895 (struct intel_device_info
*) ent
->driver_data
;
897 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
898 DRM_INFO("This hardware requires preliminary hardware support.\n"
899 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
903 /* Only bind to function 0 of the device. Early generations
904 * used function 1 as a placeholder for multi-head. This causes
905 * us confusion instead, especially on the systems where both
906 * functions have the same PCI-ID!
908 if (PCI_FUNC(pdev
->devfn
))
911 driver
.driver_features
&= ~(DRIVER_USE_AGP
);
913 return drm_get_pci_dev(pdev
, ent
, &driver
);
917 i915_pci_remove(struct pci_dev
*pdev
)
919 struct drm_device
*dev
= pci_get_drvdata(pdev
);
924 static int i915_pm_suspend(struct device
*dev
)
926 struct pci_dev
*pdev
= to_pci_dev(dev
);
927 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
929 if (!drm_dev
|| !drm_dev
->dev_private
) {
930 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
934 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
937 return i915_drm_suspend(drm_dev
);
940 static int i915_pm_suspend_late(struct device
*dev
)
942 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
945 * We have a suspedn ordering issue with the snd-hda driver also
946 * requiring our device to be power up. Due to the lack of a
947 * parent/child relationship we currently solve this with an late
950 * FIXME: This should be solved with a special hdmi sink device or
951 * similar so that power domains can be employed.
953 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
956 return i915_drm_suspend_late(drm_dev
);
959 static int i915_pm_resume_early(struct device
*dev
)
961 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
963 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
966 return i915_drm_resume_early(drm_dev
);
969 static int i915_pm_resume(struct device
*dev
)
971 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
973 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
976 return i915_drm_resume(drm_dev
);
979 static int hsw_suspend_complete(struct drm_i915_private
*dev_priv
)
981 hsw_enable_pc8(dev_priv
);
987 * Save all Gunit registers that may be lost after a D3 and a subsequent
988 * S0i[R123] transition. The list of registers needing a save/restore is
989 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
990 * registers in the following way:
991 * - Driver: saved/restored by the driver
992 * - Punit : saved/restored by the Punit firmware
993 * - No, w/o marking: no need to save/restore, since the register is R/O or
994 * used internally by the HW in a way that doesn't depend
995 * keeping the content across a suspend/resume.
996 * - Debug : used for debugging
998 * We save/restore all registers marked with 'Driver', with the following
1000 * - Registers out of use, including also registers marked with 'Debug'.
1001 * These have no effect on the driver's operation, so we don't save/restore
1002 * them to reduce the overhead.
1003 * - Registers that are fully setup by an initialization function called from
1004 * the resume path. For example many clock gating and RPS/RC6 registers.
1005 * - Registers that provide the right functionality with their reset defaults.
1007 * TODO: Except for registers that based on the above 3 criteria can be safely
1008 * ignored, we save/restore all others, practically treating the HW context as
1009 * a black-box for the driver. Further investigation is needed to reduce the
1010 * saved/restored registers even further, by following the same 3 criteria.
1012 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1014 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1017 /* GAM 0x4000-0x4770 */
1018 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1019 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1020 s
->arb_mode
= I915_READ(ARB_MODE
);
1021 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1022 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1024 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1025 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS_BASE
+ i
* 4);
1027 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1028 s
->gfx_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1030 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1031 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1032 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1033 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1035 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1037 /* MBC 0x9024-0x91D0, 0x8500 */
1038 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1039 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1040 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1042 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1043 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1044 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1045 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1046 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1047 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1048 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1050 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1051 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1052 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1053 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1054 s
->ecobus
= I915_READ(ECOBUS
);
1055 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1056 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1057 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1058 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1059 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1060 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1062 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1063 s
->gt_imr
= I915_READ(GTIMR
);
1064 s
->gt_ier
= I915_READ(GTIER
);
1065 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1066 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1068 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1069 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH_BASE
+ i
* 4);
1071 /* GT SA CZ domain, 0x100000-0x138124 */
1072 s
->tilectl
= I915_READ(TILECTL
);
1073 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1074 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1075 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1076 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1078 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1079 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1080 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1081 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1084 * Not saving any of:
1085 * DFT, 0x9800-0x9EC0
1086 * SARB, 0xB000-0xB1FC
1087 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1092 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1094 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1098 /* GAM 0x4000-0x4770 */
1099 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1100 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1101 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1102 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1103 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1105 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1106 I915_WRITE(GEN7_LRA_LIMITS_BASE
+ i
* 4, s
->lra_limits
[i
]);
1108 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1109 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1111 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1112 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1113 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1114 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1116 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1118 /* MBC 0x9024-0x91D0, 0x8500 */
1119 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1120 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1121 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1123 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1124 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1125 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1126 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1127 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1128 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1129 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1131 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1132 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1133 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1134 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1135 I915_WRITE(ECOBUS
, s
->ecobus
);
1136 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1137 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1138 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1139 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1140 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1141 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1143 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1144 I915_WRITE(GTIMR
, s
->gt_imr
);
1145 I915_WRITE(GTIER
, s
->gt_ier
);
1146 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1147 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1149 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1150 I915_WRITE(GEN7_GT_SCRATCH_BASE
+ i
* 4, s
->gt_scratch
[i
]);
1152 /* GT SA CZ domain, 0x100000-0x138124 */
1153 I915_WRITE(TILECTL
, s
->tilectl
);
1154 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1156 * Preserve the GT allow wake and GFX force clock bit, they are not
1157 * be restored, as they are used to control the s0ix suspend/resume
1158 * sequence by the caller.
1160 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1161 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1162 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1163 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1165 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1166 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1167 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1168 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1170 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1172 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1173 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1174 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1175 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1178 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1183 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1184 WARN_ON(!!(val
& VLV_GFX_CLK_FORCE_ON_BIT
) == force_on
);
1186 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1187 /* Wait for a previous force-off to settle */
1189 err
= wait_for(!COND
, 20);
1191 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1192 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1197 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1198 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1200 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1201 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1206 err
= wait_for(COND
, 20);
1208 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1209 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1215 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1220 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1221 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1223 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1224 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1225 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1227 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1229 err
= wait_for(COND
, 1);
1231 DRM_ERROR("timeout disabling GT waking\n");
1236 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1243 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1244 val
= wait_for_on
? mask
: 0;
1245 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1249 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1250 wait_for_on
? "on" : "off",
1251 I915_READ(VLV_GTLC_PW_STATUS
));
1254 * RC6 transitioning can be delayed up to 2 msec (see
1255 * valleyview_enable_rps), use 3 msec for safety.
1257 err
= wait_for(COND
, 3);
1259 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1260 wait_for_on
? "on" : "off");
1266 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1268 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1271 DRM_ERROR("GT register access while GT waking disabled\n");
1272 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1275 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
1281 * Bspec defines the following GT well on flags as debug only, so
1282 * don't treat them as hard failures.
1284 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1286 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1287 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1289 vlv_check_no_gt_access(dev_priv
);
1291 err
= vlv_force_gfx_clock(dev_priv
, true);
1295 err
= vlv_allow_gt_wake(dev_priv
, false);
1299 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1300 vlv_save_gunit_s0ix_state(dev_priv
);
1302 err
= vlv_force_gfx_clock(dev_priv
, false);
1309 /* For safety always re-enable waking and disable gfx clock forcing */
1310 vlv_allow_gt_wake(dev_priv
, true);
1312 vlv_force_gfx_clock(dev_priv
, false);
1317 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1320 struct drm_device
*dev
= dev_priv
->dev
;
1325 * If any of the steps fail just try to continue, that's the best we
1326 * can do at this point. Return the first error code (which will also
1327 * leave RPM permanently disabled).
1329 ret
= vlv_force_gfx_clock(dev_priv
, true);
1331 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1332 vlv_restore_gunit_s0ix_state(dev_priv
);
1334 err
= vlv_allow_gt_wake(dev_priv
, true);
1338 err
= vlv_force_gfx_clock(dev_priv
, false);
1342 vlv_check_no_gt_access(dev_priv
);
1345 intel_init_clock_gating(dev
);
1346 i915_gem_restore_fences(dev
);
1352 static int intel_runtime_suspend(struct device
*device
)
1354 struct pci_dev
*pdev
= to_pci_dev(device
);
1355 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1359 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1362 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1365 DRM_DEBUG_KMS("Suspending device\n");
1368 * We could deadlock here in case another thread holding struct_mutex
1369 * calls RPM suspend concurrently, since the RPM suspend will wait
1370 * first for this RPM suspend to finish. In this case the concurrent
1371 * RPM resume will be followed by its RPM suspend counterpart. Still
1372 * for consistency return -EAGAIN, which will reschedule this suspend.
1374 if (!mutex_trylock(&dev
->struct_mutex
)) {
1375 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1377 * Bump the expiration timestamp, otherwise the suspend won't
1380 pm_runtime_mark_last_busy(device
);
1385 * We are safe here against re-faults, since the fault handler takes
1388 i915_gem_release_all_mmaps(dev_priv
);
1389 mutex_unlock(&dev
->struct_mutex
);
1391 intel_suspend_gt_powersave(dev
);
1392 intel_runtime_pm_disable_interrupts(dev_priv
);
1394 ret
= intel_suspend_complete(dev_priv
);
1396 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1397 intel_runtime_pm_enable_interrupts(dev_priv
);
1402 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1403 intel_uncore_forcewake_reset(dev
, false);
1404 dev_priv
->pm
.suspended
= true;
1407 * FIXME: We really should find a document that references the arguments
1410 if (IS_HASWELL(dev
)) {
1412 * current versions of firmware which depend on this opregion
1413 * notification have repurposed the D1 definition to mean
1414 * "runtime suspended" vs. what you would normally expect (D3)
1415 * to distinguish it from notifications that might be sent via
1418 intel_opregion_notify_adapter(dev
, PCI_D1
);
1421 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1422 * being detected, and the call we do at intel_runtime_resume()
1423 * won't be able to restore them. Since PCI_D3hot matches the
1424 * actual specification and appears to be working, use it. Let's
1425 * assume the other non-Haswell platforms will stay the same as
1428 intel_opregion_notify_adapter(dev
, PCI_D3hot
);
1431 assert_forcewakes_inactive(dev_priv
);
1433 DRM_DEBUG_KMS("Device suspended\n");
1437 static int intel_runtime_resume(struct device
*device
)
1439 struct pci_dev
*pdev
= to_pci_dev(device
);
1440 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1447 DRM_DEBUG_KMS("Resuming device\n");
1449 intel_opregion_notify_adapter(dev
, PCI_D0
);
1450 dev_priv
->pm
.suspended
= false;
1452 if (IS_GEN6(dev_priv
))
1453 intel_init_pch_refclk(dev
);
1454 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1455 hsw_disable_pc8(dev_priv
);
1456 else if (IS_VALLEYVIEW(dev_priv
))
1457 ret
= vlv_resume_prepare(dev_priv
, true);
1460 * No point of rolling back things in case of an error, as the best
1461 * we can do is to hope that things will still work (and disable RPM).
1463 i915_gem_init_swizzling(dev
);
1464 gen6_update_ring_freq(dev
);
1466 intel_runtime_pm_enable_interrupts(dev_priv
);
1467 intel_enable_gt_powersave(dev
);
1470 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1472 DRM_DEBUG_KMS("Device resumed\n");
1478 * This function implements common functionality of runtime and system
1481 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
)
1483 struct drm_device
*dev
= dev_priv
->dev
;
1486 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1487 ret
= hsw_suspend_complete(dev_priv
);
1488 else if (IS_VALLEYVIEW(dev
))
1489 ret
= vlv_suspend_complete(dev_priv
);
1496 static const struct dev_pm_ops i915_pm_ops
= {
1498 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1501 .suspend
= i915_pm_suspend
,
1502 .suspend_late
= i915_pm_suspend_late
,
1503 .resume_early
= i915_pm_resume_early
,
1504 .resume
= i915_pm_resume
,
1508 * @freeze, @freeze_late : called (1) before creating the
1509 * hibernation image [PMSG_FREEZE] and
1510 * (2) after rebooting, before restoring
1511 * the image [PMSG_QUIESCE]
1512 * @thaw, @thaw_early : called (1) after creating the hibernation
1513 * image, before writing it [PMSG_THAW]
1514 * and (2) after failing to create or
1515 * restore the image [PMSG_RECOVER]
1516 * @poweroff, @poweroff_late: called after writing the hibernation
1517 * image, before rebooting [PMSG_HIBERNATE]
1518 * @restore, @restore_early : called after rebooting and restoring the
1519 * hibernation image [PMSG_RESTORE]
1521 .freeze
= i915_pm_suspend
,
1522 .freeze_late
= i915_pm_suspend_late
,
1523 .thaw_early
= i915_pm_resume_early
,
1524 .thaw
= i915_pm_resume
,
1525 .poweroff
= i915_pm_suspend
,
1526 .poweroff_late
= i915_pm_suspend_late
,
1527 .restore_early
= i915_pm_resume_early
,
1528 .restore
= i915_pm_resume
,
1530 /* S0ix (via runtime suspend) event handlers */
1531 .runtime_suspend
= intel_runtime_suspend
,
1532 .runtime_resume
= intel_runtime_resume
,
1535 static const struct vm_operations_struct i915_gem_vm_ops
= {
1536 .fault
= i915_gem_fault
,
1537 .open
= drm_gem_vm_open
,
1538 .close
= drm_gem_vm_close
,
1541 static const struct file_operations i915_driver_fops
= {
1542 .owner
= THIS_MODULE
,
1544 .release
= drm_release
,
1545 .unlocked_ioctl
= drm_ioctl
,
1546 .mmap
= drm_gem_mmap
,
1549 #ifdef CONFIG_COMPAT
1550 .compat_ioctl
= i915_compat_ioctl
,
1552 .llseek
= noop_llseek
,
1555 static struct drm_driver driver
= {
1556 /* Don't use MTRRs here; the Xserver or userspace app should
1557 * deal with them for Intel hardware.
1561 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1563 .load
= i915_driver_load
,
1564 .unload
= i915_driver_unload
,
1565 .open
= i915_driver_open
,
1566 .lastclose
= i915_driver_lastclose
,
1567 .preclose
= i915_driver_preclose
,
1568 .postclose
= i915_driver_postclose
,
1569 .set_busid
= drm_pci_set_busid
,
1571 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1572 .suspend
= i915_suspend_legacy
,
1573 .resume
= i915_resume_legacy
,
1575 .device_is_agp
= i915_driver_device_is_agp
,
1576 #if defined(CONFIG_DEBUG_FS)
1577 .debugfs_init
= i915_debugfs_init
,
1578 .debugfs_cleanup
= i915_debugfs_cleanup
,
1580 .gem_free_object
= i915_gem_free_object
,
1581 .gem_vm_ops
= &i915_gem_vm_ops
,
1583 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1584 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1585 .gem_prime_export
= i915_gem_prime_export
,
1586 .gem_prime_import
= i915_gem_prime_import
,
1588 .dumb_create
= i915_gem_dumb_create
,
1589 .dumb_map_offset
= i915_gem_mmap_gtt
,
1590 .dumb_destroy
= drm_gem_dumb_destroy
,
1591 .ioctls
= i915_ioctls
,
1592 .fops
= &i915_driver_fops
,
1593 .name
= DRIVER_NAME
,
1594 .desc
= DRIVER_DESC
,
1595 .date
= DRIVER_DATE
,
1596 .major
= DRIVER_MAJOR
,
1597 .minor
= DRIVER_MINOR
,
1598 .patchlevel
= DRIVER_PATCHLEVEL
,
1601 static struct pci_driver i915_pci_driver
= {
1602 .name
= DRIVER_NAME
,
1603 .id_table
= pciidlist
,
1604 .probe
= i915_pci_probe
,
1605 .remove
= i915_pci_remove
,
1606 .driver
.pm
= &i915_pm_ops
,
1609 static int __init
i915_init(void)
1611 driver
.num_ioctls
= i915_max_ioctl
;
1614 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1615 * explicitly disabled with the module pararmeter.
1617 * Otherwise, just follow the parameter (defaulting to off).
1619 * Allow optional vga_text_mode_force boot option to override
1620 * the default behavior.
1622 #if defined(CONFIG_DRM_I915_KMS)
1623 if (i915
.modeset
!= 0)
1624 driver
.driver_features
|= DRIVER_MODESET
;
1626 if (i915
.modeset
== 1)
1627 driver
.driver_features
|= DRIVER_MODESET
;
1629 #ifdef CONFIG_VGA_CONSOLE
1630 if (vgacon_text_force() && i915
.modeset
== -1)
1631 driver
.driver_features
&= ~DRIVER_MODESET
;
1634 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1635 driver
.get_vblank_timestamp
= NULL
;
1636 /* Silently fail loading to not upset userspace. */
1637 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1642 * FIXME: Note that we're lying to the DRM core here so that we can get access
1643 * to the atomic ioctl and the atomic properties. Only plane operations on
1644 * a single CRTC will actually work.
1646 if (i915
.nuclear_pageflip
)
1647 driver
.driver_features
|= DRIVER_ATOMIC
;
1649 return drm_pci_init(&driver
, &i915_pci_driver
);
1652 static void __exit
i915_exit(void)
1654 if (!(driver
.driver_features
& DRIVER_MODESET
))
1655 return; /* Never loaded a driver. */
1657 drm_pci_exit(&driver
, &i915_pci_driver
);
1660 module_init(i915_init
);
1661 module_exit(i915_exit
);
1663 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1664 MODULE_AUTHOR("Intel Corporation");
1666 MODULE_DESCRIPTION(DRIVER_DESC
);
1667 MODULE_LICENSE("GPL and additional rights");