1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
41 static int i915_modeset __read_mostly
= -1;
42 module_param_named(modeset
, i915_modeset
, int, 0400);
43 MODULE_PARM_DESC(modeset
,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused
= 0;
48 module_param_named(fbpercrtc
, i915_fbpercrtc
, int, 0400);
50 int i915_panel_ignore_lid __read_mostly
= 1;
51 module_param_named(panel_ignore_lid
, i915_panel_ignore_lid
, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid
,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
56 unsigned int i915_powersave __read_mostly
= 1;
57 module_param_named(powersave
, i915_powersave
, int, 0600);
58 MODULE_PARM_DESC(powersave
,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly
= -1;
62 module_param_named(semaphores
, i915_semaphores
, int, 0600);
63 MODULE_PARM_DESC(semaphores
,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly
= -1;
67 module_param_named(i915_enable_rc6
, i915_enable_rc6
, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6
,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
75 int i915_enable_fbc __read_mostly
= -1;
76 module_param_named(i915_enable_fbc
, i915_enable_fbc
, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc
,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
81 unsigned int i915_lvds_downclock __read_mostly
= 0;
82 module_param_named(lvds_downclock
, i915_lvds_downclock
, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock
,
84 "Use panel (LVDS/eDP) downclocking for power savings "
87 int i915_lvds_channel_mode __read_mostly
;
88 module_param_named(lvds_channel_mode
, i915_lvds_channel_mode
, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode
,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93 int i915_panel_use_ssc __read_mostly
= -1;
94 module_param_named(lvds_use_ssc
, i915_panel_use_ssc
, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc
,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
99 int i915_vbt_sdvo_panel_type __read_mostly
= -1;
100 module_param_named(vbt_sdvo_panel_type
, i915_vbt_sdvo_panel_type
, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type
,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
105 static bool i915_try_reset __read_mostly
= true;
106 module_param_named(reset
, i915_try_reset
, bool, 0600);
107 MODULE_PARM_DESC(reset
, "Attempt GPU resets (default: true)");
109 bool i915_enable_hangcheck __read_mostly
= true;
110 module_param_named(enable_hangcheck
, i915_enable_hangcheck
, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck
,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
116 int i915_enable_ppgtt __read_mostly
= -1;
117 module_param_named(i915_enable_ppgtt
, i915_enable_ppgtt
, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt
,
119 "Enable PPGTT (default: true)");
121 unsigned int i915_preliminary_hw_support __read_mostly
= 0;
122 module_param_named(preliminary_hw_support
, i915_preliminary_hw_support
, int, 0600);
123 MODULE_PARM_DESC(preliminary_hw_support
,
124 "Enable preliminary hardware support. (default: false)");
126 int i915_disable_power_well __read_mostly
= 1;
127 module_param_named(disable_power_well
, i915_disable_power_well
, int, 0600);
128 MODULE_PARM_DESC(disable_power_well
,
129 "Disable the power well when possible (default: true)");
131 int i915_enable_ips __read_mostly
= 1;
132 module_param_named(enable_ips
, i915_enable_ips
, int, 0600);
133 MODULE_PARM_DESC(enable_ips
, "Enable IPS (default: true)");
135 bool i915_fastboot __read_mostly
= 0;
136 module_param_named(fastboot
, i915_fastboot
, bool, 0600);
137 MODULE_PARM_DESC(fastboot
, "Try to skip unnecessary mode sets at boot time "
140 static struct drm_driver driver
;
141 extern int intel_agp_enabled
;
143 #define INTEL_VGA_DEVICE(id, info) { \
144 .class = PCI_BASE_CLASS_DISPLAY << 16, \
145 .class_mask = 0xff0000, \
148 .subvendor = PCI_ANY_ID, \
149 .subdevice = PCI_ANY_ID, \
150 .driver_data = (unsigned long) info }
152 #define INTEL_QUANTA_VGA_DEVICE(info) { \
153 .class = PCI_BASE_CLASS_DISPLAY << 16, \
154 .class_mask = 0xff0000, \
157 .subvendor = 0x152d, \
158 .subdevice = 0x8990, \
159 .driver_data = (unsigned long) info }
162 static const struct intel_device_info intel_i830_info
= {
163 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
164 .has_overlay
= 1, .overlay_needs_physical
= 1,
167 static const struct intel_device_info intel_845g_info
= {
168 .gen
= 2, .num_pipes
= 1,
169 .has_overlay
= 1, .overlay_needs_physical
= 1,
172 static const struct intel_device_info intel_i85x_info
= {
173 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
174 .cursor_needs_physical
= 1,
175 .has_overlay
= 1, .overlay_needs_physical
= 1,
178 static const struct intel_device_info intel_i865g_info
= {
179 .gen
= 2, .num_pipes
= 1,
180 .has_overlay
= 1, .overlay_needs_physical
= 1,
183 static const struct intel_device_info intel_i915g_info
= {
184 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
185 .has_overlay
= 1, .overlay_needs_physical
= 1,
187 static const struct intel_device_info intel_i915gm_info
= {
188 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
189 .cursor_needs_physical
= 1,
190 .has_overlay
= 1, .overlay_needs_physical
= 1,
193 static const struct intel_device_info intel_i945g_info
= {
194 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
195 .has_overlay
= 1, .overlay_needs_physical
= 1,
197 static const struct intel_device_info intel_i945gm_info
= {
198 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
199 .has_hotplug
= 1, .cursor_needs_physical
= 1,
200 .has_overlay
= 1, .overlay_needs_physical
= 1,
204 static const struct intel_device_info intel_i965g_info
= {
205 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
210 static const struct intel_device_info intel_i965gm_info
= {
211 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
212 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
217 static const struct intel_device_info intel_g33_info
= {
218 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
219 .need_gfx_hws
= 1, .has_hotplug
= 1,
223 static const struct intel_device_info intel_g45_info
= {
224 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
225 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
229 static const struct intel_device_info intel_gm45_info
= {
230 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
231 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
232 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
237 static const struct intel_device_info intel_pineview_info
= {
238 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
239 .need_gfx_hws
= 1, .has_hotplug
= 1,
243 static const struct intel_device_info intel_ironlake_d_info
= {
244 .gen
= 5, .num_pipes
= 2,
245 .need_gfx_hws
= 1, .has_hotplug
= 1,
249 static const struct intel_device_info intel_ironlake_m_info
= {
250 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
251 .need_gfx_hws
= 1, .has_hotplug
= 1,
256 static const struct intel_device_info intel_sandybridge_d_info
= {
257 .gen
= 6, .num_pipes
= 2,
258 .need_gfx_hws
= 1, .has_hotplug
= 1,
265 static const struct intel_device_info intel_sandybridge_m_info
= {
266 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
267 .need_gfx_hws
= 1, .has_hotplug
= 1,
275 #define GEN7_FEATURES \
276 .gen = 7, .num_pipes = 3, \
277 .need_gfx_hws = 1, .has_hotplug = 1, \
283 static const struct intel_device_info intel_ivybridge_d_info
= {
288 static const struct intel_device_info intel_ivybridge_m_info
= {
295 static const struct intel_device_info intel_ivybridge_q_info
= {
298 .num_pipes
= 0, /* legal, last one wins */
301 static const struct intel_device_info intel_valleyview_m_info
= {
306 .display_mmio_offset
= VLV_DISPLAY_BASE
,
307 .has_llc
= 0, /* legal, last one wins */
310 static const struct intel_device_info intel_valleyview_d_info
= {
314 .display_mmio_offset
= VLV_DISPLAY_BASE
,
315 .has_llc
= 0, /* legal, last one wins */
318 static const struct intel_device_info intel_haswell_d_info
= {
326 static const struct intel_device_info intel_haswell_m_info
= {
336 static const struct pci_device_id pciidlist
[] = { /* aka */
337 INTEL_VGA_DEVICE(0x3577, &intel_i830_info
), /* I830_M */
338 INTEL_VGA_DEVICE(0x2562, &intel_845g_info
), /* 845_G */
339 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info
), /* I855_GM */
340 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info
),
341 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info
), /* I865_G */
342 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info
), /* I915_G */
343 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info
), /* E7221_G */
344 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info
), /* I915_GM */
345 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info
), /* I945_G */
346 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info
), /* I945_GM */
347 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info
), /* I945_GME */
348 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info
), /* I946_GZ */
349 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info
), /* G35_G */
350 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info
), /* I965_Q */
351 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info
), /* I965_G */
352 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info
), /* Q35_G */
353 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info
), /* G33_G */
354 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info
), /* Q33_G */
355 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info
), /* I965_GM */
356 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info
), /* I965_GME */
357 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info
), /* GM45_G */
358 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info
), /* IGD_E_G */
359 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info
), /* Q45_G */
360 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info
), /* G45_G */
361 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info
), /* G41_G */
362 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info
), /* B43_G */
363 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info
), /* B43_G.1 */
364 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info
),
365 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info
),
366 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info
),
367 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info
),
368 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info
),
369 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info
),
370 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info
),
371 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info
),
372 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info
),
373 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info
),
374 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info
),
375 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info
), /* GT1 mobile */
376 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info
), /* GT2 mobile */
377 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info
), /* GT1 desktop */
378 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info
), /* GT2 desktop */
379 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info
), /* GT1 server */
380 INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info
), /* Quanta transcode */
381 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info
), /* GT2 server */
382 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info
), /* GT1 desktop */
383 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info
), /* GT2 desktop */
384 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info
), /* GT3 desktop */
385 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info
), /* GT1 server */
386 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info
), /* GT2 server */
387 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info
), /* GT3 server */
388 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info
), /* GT1 mobile */
389 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info
), /* GT2 mobile */
390 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info
), /* GT2 mobile */
391 INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info
), /* GT1 reserved */
392 INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info
), /* GT2 reserved */
393 INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info
), /* GT3 reserved */
394 INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info
), /* GT1 reserved */
395 INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info
), /* GT2 reserved */
396 INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info
), /* GT3 reserved */
397 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info
), /* SDV GT1 desktop */
398 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info
), /* SDV GT2 desktop */
399 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info
), /* SDV GT3 desktop */
400 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info
), /* SDV GT1 server */
401 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info
), /* SDV GT2 server */
402 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info
), /* SDV GT3 server */
403 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info
), /* SDV GT1 mobile */
404 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info
), /* SDV GT2 mobile */
405 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info
), /* SDV GT3 mobile */
406 INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info
), /* SDV GT1 reserved */
407 INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info
), /* SDV GT2 reserved */
408 INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info
), /* SDV GT3 reserved */
409 INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info
), /* SDV GT1 reserved */
410 INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info
), /* SDV GT2 reserved */
411 INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info
), /* SDV GT3 reserved */
412 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info
), /* ULT GT1 desktop */
413 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info
), /* ULT GT2 desktop */
414 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info
), /* ULT GT3 desktop */
415 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info
), /* ULT GT1 server */
416 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info
), /* ULT GT2 server */
417 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info
), /* ULT GT3 server */
418 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info
), /* ULT GT1 mobile */
419 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info
), /* ULT GT2 mobile */
420 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info
), /* ULT GT3 mobile */
421 INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info
), /* ULT GT1 reserved */
422 INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info
), /* ULT GT2 reserved */
423 INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info
), /* ULT GT3 reserved */
424 INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info
), /* ULT GT1 reserved */
425 INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info
), /* ULT GT2 reserved */
426 INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info
), /* ULT GT3 reserved */
427 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info
), /* CRW GT1 desktop */
428 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info
), /* CRW GT2 desktop */
429 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info
), /* CRW GT3 desktop */
430 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info
), /* CRW GT1 server */
431 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info
), /* CRW GT2 server */
432 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info
), /* CRW GT3 server */
433 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info
), /* CRW GT1 mobile */
434 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info
), /* CRW GT2 mobile */
435 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info
), /* CRW GT3 mobile */
436 INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info
), /* CRW GT1 reserved */
437 INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info
), /* CRW GT2 reserved */
438 INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info
), /* CRW GT3 reserved */
439 INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info
), /* CRW GT1 reserved */
440 INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info
), /* CRW GT2 reserved */
441 INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info
), /* CRW GT3 reserved */
442 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info
),
443 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info
),
444 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info
),
445 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info
),
446 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info
),
447 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info
),
451 #if defined(CONFIG_DRM_I915_KMS)
452 MODULE_DEVICE_TABLE(pci
, pciidlist
);
455 void intel_detect_pch(struct drm_device
*dev
)
457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
460 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
461 * (which really amounts to a PCH but no South Display).
463 if (INTEL_INFO(dev
)->num_pipes
== 0) {
464 dev_priv
->pch_type
= PCH_NOP
;
469 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
470 * make graphics device passthrough work easy for VMM, that only
471 * need to expose ISA bridge to let driver know the real hardware
472 * underneath. This is a requirement from virtualization team.
474 * In some virtualized environments (e.g. XEN), there is irrelevant
475 * ISA bridge in the system. To work reliably, we should scan trhough
476 * all the ISA bridge devices and check for the first match, instead
477 * of only checking the first one.
479 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
481 struct pci_dev
*curr
= pch
;
482 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
484 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
485 dev_priv
->pch_id
= id
;
487 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
488 dev_priv
->pch_type
= PCH_IBX
;
489 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
490 WARN_ON(!IS_GEN5(dev
));
491 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
492 dev_priv
->pch_type
= PCH_CPT
;
493 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
494 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
495 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
496 /* PantherPoint is CPT compatible */
497 dev_priv
->pch_type
= PCH_CPT
;
498 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
499 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
500 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
501 dev_priv
->pch_type
= PCH_LPT
;
502 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
503 WARN_ON(!IS_HASWELL(dev
));
504 WARN_ON(IS_ULT(dev
));
505 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
506 dev_priv
->pch_type
= PCH_LPT
;
507 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
508 WARN_ON(!IS_HASWELL(dev
));
509 WARN_ON(!IS_ULT(dev
));
517 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, curr
);
521 DRM_DEBUG_KMS("No PCH found?\n");
524 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
526 if (INTEL_INFO(dev
)->gen
< 6)
529 if (i915_semaphores
>= 0)
530 return i915_semaphores
;
532 #ifdef CONFIG_INTEL_IOMMU
533 /* Enable semaphores on SNB when IO remapping is off */
534 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
541 static int i915_drm_freeze(struct drm_device
*dev
)
543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
544 struct drm_crtc
*crtc
;
546 /* ignore lid events during suspend */
547 mutex_lock(&dev_priv
->modeset_restore_lock
);
548 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
549 mutex_unlock(&dev_priv
->modeset_restore_lock
);
551 intel_set_power_well(dev
, true);
553 drm_kms_helper_poll_disable(dev
);
555 pci_save_state(dev
->pdev
);
557 /* If KMS is active, we do the leavevt stuff here */
558 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
561 mutex_lock(&dev
->struct_mutex
);
562 error
= i915_gem_idle(dev
);
563 mutex_unlock(&dev
->struct_mutex
);
565 dev_err(&dev
->pdev
->dev
,
566 "GEM idle failed, resume might fail\n");
570 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
572 drm_irq_uninstall(dev
);
573 dev_priv
->enable_hotplug_processing
= false;
575 * Disable CRTCs directly since we want to preserve sw state
578 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
579 dev_priv
->display
.crtc_disable(crtc
);
581 intel_modeset_suspend_hw(dev
);
584 i915_save_state(dev
);
586 intel_opregion_fini(dev
);
589 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
);
595 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
599 if (!dev
|| !dev
->dev_private
) {
600 DRM_ERROR("dev: %p\n", dev
);
601 DRM_ERROR("DRM not initialized, aborting suspend.\n");
605 if (state
.event
== PM_EVENT_PRETHAW
)
609 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
612 error
= i915_drm_freeze(dev
);
616 if (state
.event
== PM_EVENT_SUSPEND
) {
617 /* Shut down the device */
618 pci_disable_device(dev
->pdev
);
619 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
625 void intel_console_resume(struct work_struct
*work
)
627 struct drm_i915_private
*dev_priv
=
628 container_of(work
, struct drm_i915_private
,
629 console_resume_work
);
630 struct drm_device
*dev
= dev_priv
->dev
;
633 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
637 static void intel_resume_hotplug(struct drm_device
*dev
)
639 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
640 struct intel_encoder
*encoder
;
642 mutex_lock(&mode_config
->mutex
);
643 DRM_DEBUG_KMS("running encoder hotplug functions\n");
645 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
646 if (encoder
->hot_plug
)
647 encoder
->hot_plug(encoder
);
649 mutex_unlock(&mode_config
->mutex
);
651 /* Just fire off a uevent and let userspace tell us what to do */
652 drm_helper_hpd_irq_event(dev
);
655 static int __i915_drm_thaw(struct drm_device
*dev
)
657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
660 i915_restore_state(dev
);
661 intel_opregion_setup(dev
);
663 /* KMS EnterVT equivalent */
664 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
665 intel_init_pch_refclk(dev
);
667 mutex_lock(&dev
->struct_mutex
);
669 error
= i915_gem_init_hw(dev
);
670 mutex_unlock(&dev
->struct_mutex
);
672 /* We need working interrupts for modeset enabling ... */
673 drm_irq_install(dev
);
675 intel_modeset_init_hw(dev
);
677 drm_modeset_lock_all(dev
);
678 intel_modeset_setup_hw_state(dev
, true);
679 drm_modeset_unlock_all(dev
);
682 * ... but also need to make sure that hotplug processing
683 * doesn't cause havoc. Like in the driver load code we don't
684 * bother with the tiny race here where we might loose hotplug
688 dev_priv
->enable_hotplug_processing
= true;
689 /* Config may have changed between suspend and resume */
690 intel_resume_hotplug(dev
);
693 intel_opregion_init(dev
);
696 * The console lock can be pretty contented on resume due
697 * to all the printk activity. Try to keep it out of the hot
698 * path of resume if possible.
700 if (console_trylock()) {
701 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
704 schedule_work(&dev_priv
->console_resume_work
);
707 mutex_lock(&dev_priv
->modeset_restore_lock
);
708 dev_priv
->modeset_restore
= MODESET_DONE
;
709 mutex_unlock(&dev_priv
->modeset_restore_lock
);
713 static int i915_drm_thaw(struct drm_device
*dev
)
719 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
720 mutex_lock(&dev
->struct_mutex
);
721 i915_gem_restore_gtt_mappings(dev
);
722 mutex_unlock(&dev
->struct_mutex
);
725 __i915_drm_thaw(dev
);
730 int i915_resume(struct drm_device
*dev
)
732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
735 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
738 if (pci_enable_device(dev
->pdev
))
741 pci_set_master(dev
->pdev
);
746 * Platforms with opregion should have sane BIOS, older ones (gen3 and
747 * earlier) need this since the BIOS might clear all our scratch PTEs.
749 if (drm_core_check_feature(dev
, DRIVER_MODESET
) &&
750 !dev_priv
->opregion
.header
) {
751 mutex_lock(&dev
->struct_mutex
);
752 i915_gem_restore_gtt_mappings(dev
);
753 mutex_unlock(&dev
->struct_mutex
);
756 ret
= __i915_drm_thaw(dev
);
760 drm_kms_helper_poll_enable(dev
);
764 static int i8xx_do_reset(struct drm_device
*dev
)
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
771 I915_WRITE(D_STATE
, I915_READ(D_STATE
) | DSTATE_GFX_RESET_I830
);
772 POSTING_READ(D_STATE
);
774 if (IS_I830(dev
) || IS_845G(dev
)) {
775 I915_WRITE(DEBUG_RESET_I830
,
776 DEBUG_RESET_DISPLAY
|
779 POSTING_READ(DEBUG_RESET_I830
);
782 I915_WRITE(DEBUG_RESET_I830
, 0);
783 POSTING_READ(DEBUG_RESET_I830
);
788 I915_WRITE(D_STATE
, I915_READ(D_STATE
) & ~DSTATE_GFX_RESET_I830
);
789 POSTING_READ(D_STATE
);
794 static int i965_reset_complete(struct drm_device
*dev
)
797 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
798 return (gdrst
& GRDOM_RESET_ENABLE
) == 0;
801 static int i965_do_reset(struct drm_device
*dev
)
806 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
807 * well as the reset bit (GR/bit 0). Setting the GR bit
808 * triggers the reset; when done, the hardware will clear it.
810 pci_write_config_byte(dev
->pdev
, I965_GDRST
,
811 GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
812 ret
= wait_for(i965_reset_complete(dev
), 500);
816 /* We can't reset render&media without also resetting display ... */
817 pci_write_config_byte(dev
->pdev
, I965_GDRST
,
818 GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
820 ret
= wait_for(i965_reset_complete(dev
), 500);
824 pci_write_config_byte(dev
->pdev
, I965_GDRST
, 0);
829 static int ironlake_do_reset(struct drm_device
*dev
)
831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
835 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
836 gdrst
&= ~GRDOM_MASK
;
837 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
,
838 gdrst
| GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
839 ret
= wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
843 /* We can't reset render&media without also resetting display ... */
844 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
845 gdrst
&= ~GRDOM_MASK
;
846 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
,
847 gdrst
| GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
848 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
851 static int gen6_do_reset(struct drm_device
*dev
)
853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
855 unsigned long irqflags
;
857 /* Hold gt_lock across reset to prevent any register access
858 * with forcewake not set correctly
860 spin_lock_irqsave(&dev_priv
->gt_lock
, irqflags
);
864 /* GEN6_GDRST is not in the gt power well, no need to check
865 * for fifo space for the write or forcewake the chip for
868 I915_WRITE_NOTRACE(GEN6_GDRST
, GEN6_GRDOM_FULL
);
870 /* Spin waiting for the device to ack the reset request */
871 ret
= wait_for((I915_READ_NOTRACE(GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
873 /* If reset with a user forcewake, try to restore, otherwise turn it off */
874 if (dev_priv
->forcewake_count
)
875 dev_priv
->gt
.force_wake_get(dev_priv
);
877 dev_priv
->gt
.force_wake_put(dev_priv
);
879 /* Restore fifo count */
880 dev_priv
->gt_fifo_count
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
882 spin_unlock_irqrestore(&dev_priv
->gt_lock
, irqflags
);
886 int intel_gpu_reset(struct drm_device
*dev
)
888 switch (INTEL_INFO(dev
)->gen
) {
890 case 6: return gen6_do_reset(dev
);
891 case 5: return ironlake_do_reset(dev
);
892 case 4: return i965_do_reset(dev
);
893 case 2: return i8xx_do_reset(dev
);
894 default: return -ENODEV
;
899 * i915_reset - reset chip after a hang
900 * @dev: drm device to reset
902 * Reset the chip. Useful if a hang is detected. Returns zero on successful
903 * reset or otherwise an error code.
905 * Procedure is fairly simple:
906 * - reset the chip using the reset reg
907 * - re-init context state
908 * - re-init hardware status page
909 * - re-init ring buffer
910 * - re-init interrupt state
913 int i915_reset(struct drm_device
*dev
)
915 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
922 mutex_lock(&dev
->struct_mutex
);
926 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
928 if (!simulated
&& get_seconds() - dev_priv
->gpu_error
.last_reset
< 5) {
929 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
932 ret
= intel_gpu_reset(dev
);
934 /* Also reset the gpu hangman. */
936 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
937 dev_priv
->gpu_error
.stop_rings
= 0;
938 if (ret
== -ENODEV
) {
939 DRM_ERROR("Reset not implemented, but ignoring "
940 "error for simulated gpu hangs\n");
944 dev_priv
->gpu_error
.last_reset
= get_seconds();
947 DRM_ERROR("Failed to reset chip.\n");
948 mutex_unlock(&dev
->struct_mutex
);
952 /* Ok, now get things going again... */
955 * Everything depends on having the GTT running, so we need to start
956 * there. Fortunately we don't need to do this unless we reset the
957 * chip at a PCI level.
959 * Next we need to restore the context, but we don't use those
962 * Ring buffer needs to be re-initialized in the KMS case, or if X
963 * was running at the time of the reset (i.e. we weren't VT
966 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
967 !dev_priv
->ums
.mm_suspended
) {
968 struct intel_ring_buffer
*ring
;
971 dev_priv
->ums
.mm_suspended
= 0;
973 i915_gem_init_swizzling(dev
);
975 for_each_ring(ring
, dev_priv
, i
)
978 i915_gem_context_init(dev
);
979 if (dev_priv
->mm
.aliasing_ppgtt
) {
980 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
982 i915_gem_cleanup_aliasing_ppgtt(dev
);
986 * It would make sense to re-init all the other hw state, at
987 * least the rps/rc6/emon init done within modeset_init_hw. For
988 * some unknown reason, this blows up my ilk, so don't.
991 mutex_unlock(&dev
->struct_mutex
);
993 drm_irq_uninstall(dev
);
994 drm_irq_install(dev
);
997 mutex_unlock(&dev
->struct_mutex
);
1003 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1005 struct intel_device_info
*intel_info
=
1006 (struct intel_device_info
*) ent
->driver_data
;
1008 /* Only bind to function 0 of the device. Early generations
1009 * used function 1 as a placeholder for multi-head. This causes
1010 * us confusion instead, especially on the systems where both
1011 * functions have the same PCI-ID!
1013 if (PCI_FUNC(pdev
->devfn
))
1016 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
1017 * implementation for gen3 (and only gen3) that used legacy drm maps
1018 * (gasp!) to share buffers between X and the client. Hence we need to
1019 * keep around the fake agp stuff for gen3, even when kms is enabled. */
1020 if (intel_info
->gen
!= 3) {
1021 driver
.driver_features
&=
1022 ~(DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
);
1023 } else if (!intel_agp_enabled
) {
1024 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1028 return drm_get_pci_dev(pdev
, ent
, &driver
);
1032 i915_pci_remove(struct pci_dev
*pdev
)
1034 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1039 static int i915_pm_suspend(struct device
*dev
)
1041 struct pci_dev
*pdev
= to_pci_dev(dev
);
1042 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1045 if (!drm_dev
|| !drm_dev
->dev_private
) {
1046 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
1050 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1053 error
= i915_drm_freeze(drm_dev
);
1057 pci_disable_device(pdev
);
1058 pci_set_power_state(pdev
, PCI_D3hot
);
1063 static int i915_pm_resume(struct device
*dev
)
1065 struct pci_dev
*pdev
= to_pci_dev(dev
);
1066 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1068 return i915_resume(drm_dev
);
1071 static int i915_pm_freeze(struct device
*dev
)
1073 struct pci_dev
*pdev
= to_pci_dev(dev
);
1074 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1076 if (!drm_dev
|| !drm_dev
->dev_private
) {
1077 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
1081 return i915_drm_freeze(drm_dev
);
1084 static int i915_pm_thaw(struct device
*dev
)
1086 struct pci_dev
*pdev
= to_pci_dev(dev
);
1087 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1089 return i915_drm_thaw(drm_dev
);
1092 static int i915_pm_poweroff(struct device
*dev
)
1094 struct pci_dev
*pdev
= to_pci_dev(dev
);
1095 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1097 return i915_drm_freeze(drm_dev
);
1100 static const struct dev_pm_ops i915_pm_ops
= {
1101 .suspend
= i915_pm_suspend
,
1102 .resume
= i915_pm_resume
,
1103 .freeze
= i915_pm_freeze
,
1104 .thaw
= i915_pm_thaw
,
1105 .poweroff
= i915_pm_poweroff
,
1106 .restore
= i915_pm_resume
,
1109 static const struct vm_operations_struct i915_gem_vm_ops
= {
1110 .fault
= i915_gem_fault
,
1111 .open
= drm_gem_vm_open
,
1112 .close
= drm_gem_vm_close
,
1115 static const struct file_operations i915_driver_fops
= {
1116 .owner
= THIS_MODULE
,
1118 .release
= drm_release
,
1119 .unlocked_ioctl
= drm_ioctl
,
1120 .mmap
= drm_gem_mmap
,
1122 .fasync
= drm_fasync
,
1124 #ifdef CONFIG_COMPAT
1125 .compat_ioctl
= i915_compat_ioctl
,
1127 .llseek
= noop_llseek
,
1130 static struct drm_driver driver
= {
1131 /* Don't use MTRRs here; the Xserver or userspace app should
1132 * deal with them for Intel hardware.
1135 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
| /* DRIVER_USE_MTRR |*/
1136 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
,
1137 .load
= i915_driver_load
,
1138 .unload
= i915_driver_unload
,
1139 .open
= i915_driver_open
,
1140 .lastclose
= i915_driver_lastclose
,
1141 .preclose
= i915_driver_preclose
,
1142 .postclose
= i915_driver_postclose
,
1144 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1145 .suspend
= i915_suspend
,
1146 .resume
= i915_resume
,
1148 .device_is_agp
= i915_driver_device_is_agp
,
1149 .master_create
= i915_master_create
,
1150 .master_destroy
= i915_master_destroy
,
1151 #if defined(CONFIG_DEBUG_FS)
1152 .debugfs_init
= i915_debugfs_init
,
1153 .debugfs_cleanup
= i915_debugfs_cleanup
,
1155 .gem_init_object
= i915_gem_init_object
,
1156 .gem_free_object
= i915_gem_free_object
,
1157 .gem_vm_ops
= &i915_gem_vm_ops
,
1159 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1160 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1161 .gem_prime_export
= i915_gem_prime_export
,
1162 .gem_prime_import
= i915_gem_prime_import
,
1164 .dumb_create
= i915_gem_dumb_create
,
1165 .dumb_map_offset
= i915_gem_mmap_gtt
,
1166 .dumb_destroy
= i915_gem_dumb_destroy
,
1167 .ioctls
= i915_ioctls
,
1168 .fops
= &i915_driver_fops
,
1169 .name
= DRIVER_NAME
,
1170 .desc
= DRIVER_DESC
,
1171 .date
= DRIVER_DATE
,
1172 .major
= DRIVER_MAJOR
,
1173 .minor
= DRIVER_MINOR
,
1174 .patchlevel
= DRIVER_PATCHLEVEL
,
1177 static struct pci_driver i915_pci_driver
= {
1178 .name
= DRIVER_NAME
,
1179 .id_table
= pciidlist
,
1180 .probe
= i915_pci_probe
,
1181 .remove
= i915_pci_remove
,
1182 .driver
.pm
= &i915_pm_ops
,
1185 static int __init
i915_init(void)
1187 driver
.num_ioctls
= i915_max_ioctl
;
1190 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1191 * explicitly disabled with the module pararmeter.
1193 * Otherwise, just follow the parameter (defaulting to off).
1195 * Allow optional vga_text_mode_force boot option to override
1196 * the default behavior.
1198 #if defined(CONFIG_DRM_I915_KMS)
1199 if (i915_modeset
!= 0)
1200 driver
.driver_features
|= DRIVER_MODESET
;
1202 if (i915_modeset
== 1)
1203 driver
.driver_features
|= DRIVER_MODESET
;
1205 #ifdef CONFIG_VGA_CONSOLE
1206 if (vgacon_text_force() && i915_modeset
== -1)
1207 driver
.driver_features
&= ~DRIVER_MODESET
;
1210 if (!(driver
.driver_features
& DRIVER_MODESET
))
1211 driver
.get_vblank_timestamp
= NULL
;
1213 return drm_pci_init(&driver
, &i915_pci_driver
);
1216 static void __exit
i915_exit(void)
1218 drm_pci_exit(&driver
, &i915_pci_driver
);
1221 module_init(i915_init
);
1222 module_exit(i915_exit
);
1224 MODULE_AUTHOR(DRIVER_AUTHOR
);
1225 MODULE_DESCRIPTION(DRIVER_DESC
);
1226 MODULE_LICENSE("GPL and additional rights");
1228 /* We give fast paths for the really cool registers */
1229 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1230 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1231 ((reg) < 0x40000) && \
1232 ((reg) != FORCEWAKE))
1234 ilk_dummy_write(struct drm_i915_private
*dev_priv
)
1236 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1237 * the chip from rc6 before touching it for real. MI_MODE is masked,
1238 * hence harmless to write 0 into. */
1239 I915_WRITE_NOTRACE(MI_MODE
, 0);
1243 hsw_unclaimed_reg_clear(struct drm_i915_private
*dev_priv
, u32 reg
)
1245 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv
->dev
) &&
1246 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1247 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1249 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1254 hsw_unclaimed_reg_check(struct drm_i915_private
*dev_priv
, u32 reg
)
1256 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv
->dev
) &&
1257 (I915_READ_NOTRACE(FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1258 DRM_ERROR("Unclaimed write to %x\n", reg
);
1259 I915_WRITE_NOTRACE(FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
1263 #define __i915_read(x, y) \
1264 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1266 if (IS_GEN5(dev_priv->dev)) \
1267 ilk_dummy_write(dev_priv); \
1268 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1269 unsigned long irqflags; \
1270 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1271 if (dev_priv->forcewake_count == 0) \
1272 dev_priv->gt.force_wake_get(dev_priv); \
1273 val = read##y(dev_priv->regs + reg); \
1274 if (dev_priv->forcewake_count == 0) \
1275 dev_priv->gt.force_wake_put(dev_priv); \
1276 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1278 val = read##y(dev_priv->regs + reg); \
1280 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1290 #define __i915_write(x, y) \
1291 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1292 u32 __fifo_ret = 0; \
1293 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1294 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1295 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1297 if (IS_GEN5(dev_priv->dev)) \
1298 ilk_dummy_write(dev_priv); \
1299 hsw_unclaimed_reg_clear(dev_priv, reg); \
1300 write##y(val, dev_priv->regs + reg); \
1301 if (unlikely(__fifo_ret)) { \
1302 gen6_gt_check_fifodbg(dev_priv); \
1304 hsw_unclaimed_reg_check(dev_priv, reg); \
1312 static const struct register_whitelist
{
1315 uint32_t gen_bitmask
; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1317 { RING_TIMESTAMP(RENDER_RING_BASE
), 8, 0xF0 },
1320 int i915_reg_read_ioctl(struct drm_device
*dev
,
1321 void *data
, struct drm_file
*file
)
1323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1324 struct drm_i915_reg_read
*reg
= data
;
1325 struct register_whitelist
const *entry
= whitelist
;
1328 for (i
= 0; i
< ARRAY_SIZE(whitelist
); i
++, entry
++) {
1329 if (entry
->offset
== reg
->offset
&&
1330 (1 << INTEL_INFO(dev
)->gen
& entry
->gen_bitmask
))
1334 if (i
== ARRAY_SIZE(whitelist
))
1337 switch (entry
->size
) {
1339 reg
->val
= I915_READ64(reg
->offset
);
1342 reg
->val
= I915_READ(reg
->offset
);
1345 reg
->val
= I915_READ16(reg
->offset
);
1348 reg
->val
= I915_READ8(reg
->offset
);