1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_ioctl.h>
46 #include <drm/drm_irq.h>
47 #include <drm/drm_probe_helper.h>
48 #include <drm/i915_drm.h>
50 #include "display/intel_acpi.h"
51 #include "display/intel_audio.h"
52 #include "display/intel_bw.h"
53 #include "display/intel_cdclk.h"
54 #include "display/intel_dp.h"
55 #include "display/intel_fbdev.h"
56 #include "display/intel_gmbus.h"
57 #include "display/intel_hotplug.h"
58 #include "display/intel_overlay.h"
59 #include "display/intel_pipe_crc.h"
60 #include "display/intel_sprite.h"
62 #include "gem/i915_gem_context.h"
63 #include "gem/i915_gem_ioctls.h"
64 #include "gt/intel_gt_pm.h"
65 #include "gt/intel_reset.h"
66 #include "gt/intel_workarounds.h"
68 #include "i915_debugfs.h"
72 #include "i915_query.h"
73 #include "i915_trace.h"
74 #include "i915_vgpu.h"
75 #include "intel_csr.h"
76 #include "intel_drv.h"
80 static struct drm_driver driver
;
82 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
83 static unsigned int i915_load_fail_count
;
85 bool __i915_inject_load_failure(const char *func
, int line
)
87 if (i915_load_fail_count
>= i915_modparams
.inject_load_failure
)
90 if (++i915_load_fail_count
== i915_modparams
.inject_load_failure
) {
91 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
92 i915_modparams
.inject_load_failure
, func
, line
);
93 i915_modparams
.inject_load_failure
= 0;
100 bool i915_error_injected(void)
102 return i915_load_fail_count
&& !i915_modparams
.inject_load_failure
;
107 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
108 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
109 "providing the dmesg log by booting with drm.debug=0xf"
112 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
113 const char *fmt
, ...)
115 static bool shown_bug_once
;
116 struct device
*kdev
= dev_priv
->drm
.dev
;
117 bool is_error
= level
[1] <= KERN_ERR
[1];
118 bool is_debug
= level
[1] == KERN_DEBUG
[1];
119 struct va_format vaf
;
122 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
131 dev_printk(level
, kdev
, "%pV", &vaf
);
133 dev_printk(level
, kdev
, "[" DRM_NAME
":%ps] %pV",
134 __builtin_return_address(0), &vaf
);
138 if (is_error
&& !shown_bug_once
) {
140 * Ask the user to file a bug report for the error, except
141 * if they may have caused the bug by fiddling with unsafe
144 if (!test_taint(TAINT_USER
))
145 dev_notice(kdev
, "%s", FDO_BUG_MSG
);
146 shown_bug_once
= true;
150 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
151 static enum intel_pch
152 intel_pch_type(const struct drm_i915_private
*dev_priv
, unsigned short id
)
155 case INTEL_PCH_IBX_DEVICE_ID_TYPE
:
156 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
157 WARN_ON(!IS_GEN(dev_priv
, 5));
159 case INTEL_PCH_CPT_DEVICE_ID_TYPE
:
160 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
161 WARN_ON(!IS_GEN(dev_priv
, 6) && !IS_IVYBRIDGE(dev_priv
));
163 case INTEL_PCH_PPT_DEVICE_ID_TYPE
:
164 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
165 WARN_ON(!IS_GEN(dev_priv
, 6) && !IS_IVYBRIDGE(dev_priv
));
166 /* PantherPoint is CPT compatible */
168 case INTEL_PCH_LPT_DEVICE_ID_TYPE
:
169 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
170 WARN_ON(!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
));
171 WARN_ON(IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
));
173 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
:
174 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
175 WARN_ON(!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
));
176 WARN_ON(!IS_HSW_ULT(dev_priv
) && !IS_BDW_ULT(dev_priv
));
178 case INTEL_PCH_WPT_DEVICE_ID_TYPE
:
179 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
180 WARN_ON(!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
));
181 WARN_ON(IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
));
182 /* WildcatPoint is LPT compatible */
184 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE
:
185 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
186 WARN_ON(!IS_HASWELL(dev_priv
) && !IS_BROADWELL(dev_priv
));
187 WARN_ON(!IS_HSW_ULT(dev_priv
) && !IS_BDW_ULT(dev_priv
));
188 /* WildcatPoint is LPT compatible */
190 case INTEL_PCH_SPT_DEVICE_ID_TYPE
:
191 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
192 WARN_ON(!IS_SKYLAKE(dev_priv
) && !IS_KABYLAKE(dev_priv
));
194 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
:
195 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
196 WARN_ON(!IS_SKYLAKE(dev_priv
) && !IS_KABYLAKE(dev_priv
));
198 case INTEL_PCH_KBP_DEVICE_ID_TYPE
:
199 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
200 WARN_ON(!IS_SKYLAKE(dev_priv
) && !IS_KABYLAKE(dev_priv
) &&
201 !IS_COFFEELAKE(dev_priv
));
202 /* KBP is SPT compatible */
204 case INTEL_PCH_CNP_DEVICE_ID_TYPE
:
205 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
206 WARN_ON(!IS_CANNONLAKE(dev_priv
) && !IS_COFFEELAKE(dev_priv
));
208 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE
:
209 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
210 WARN_ON(!IS_CANNONLAKE(dev_priv
) && !IS_COFFEELAKE(dev_priv
));
212 case INTEL_PCH_CMP_DEVICE_ID_TYPE
:
213 DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
214 WARN_ON(!IS_COFFEELAKE(dev_priv
));
215 /* CometPoint is CNP Compatible */
217 case INTEL_PCH_ICP_DEVICE_ID_TYPE
:
218 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
219 WARN_ON(!IS_ICELAKE(dev_priv
));
221 case INTEL_PCH_MCC_DEVICE_ID_TYPE
:
222 DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
223 WARN_ON(!IS_ELKHARTLAKE(dev_priv
));
230 static bool intel_is_virt_pch(unsigned short id
,
231 unsigned short svendor
, unsigned short sdevice
)
233 return (id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
||
234 id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
||
235 (id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
&&
236 svendor
== PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
237 sdevice
== PCI_SUBDEVICE_ID_QEMU
));
240 static unsigned short
241 intel_virt_detect_pch(const struct drm_i915_private
*dev_priv
)
243 unsigned short id
= 0;
246 * In a virtualized passthrough environment we can be in a
247 * setup where the ISA bridge is not able to be passed through.
248 * In this case, a south bridge can be emulated and we have to
249 * make an educated guess as to which PCH is really there.
252 if (IS_ELKHARTLAKE(dev_priv
))
253 id
= INTEL_PCH_MCC_DEVICE_ID_TYPE
;
254 else if (IS_ICELAKE(dev_priv
))
255 id
= INTEL_PCH_ICP_DEVICE_ID_TYPE
;
256 else if (IS_CANNONLAKE(dev_priv
) || IS_COFFEELAKE(dev_priv
))
257 id
= INTEL_PCH_CNP_DEVICE_ID_TYPE
;
258 else if (IS_KABYLAKE(dev_priv
) || IS_SKYLAKE(dev_priv
))
259 id
= INTEL_PCH_SPT_DEVICE_ID_TYPE
;
260 else if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
261 id
= INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
;
262 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
263 id
= INTEL_PCH_LPT_DEVICE_ID_TYPE
;
264 else if (IS_GEN(dev_priv
, 6) || IS_IVYBRIDGE(dev_priv
))
265 id
= INTEL_PCH_CPT_DEVICE_ID_TYPE
;
266 else if (IS_GEN(dev_priv
, 5))
267 id
= INTEL_PCH_IBX_DEVICE_ID_TYPE
;
270 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id
);
272 DRM_DEBUG_KMS("Assuming no PCH\n");
277 static void intel_detect_pch(struct drm_i915_private
*dev_priv
)
279 struct pci_dev
*pch
= NULL
;
282 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
283 * make graphics device passthrough work easy for VMM, that only
284 * need to expose ISA bridge to let driver know the real hardware
285 * underneath. This is a requirement from virtualization team.
287 * In some virtualized environments (e.g. XEN), there is irrelevant
288 * ISA bridge in the system. To work reliably, we should scan trhough
289 * all the ISA bridge devices and check for the first match, instead
290 * of only checking the first one.
292 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
294 enum intel_pch pch_type
;
296 if (pch
->vendor
!= PCI_VENDOR_ID_INTEL
)
299 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
301 pch_type
= intel_pch_type(dev_priv
, id
);
302 if (pch_type
!= PCH_NONE
) {
303 dev_priv
->pch_type
= pch_type
;
304 dev_priv
->pch_id
= id
;
306 } else if (intel_is_virt_pch(id
, pch
->subsystem_vendor
,
307 pch
->subsystem_device
)) {
308 id
= intel_virt_detect_pch(dev_priv
);
309 pch_type
= intel_pch_type(dev_priv
, id
);
311 /* Sanity check virtual PCH id */
312 if (WARN_ON(id
&& pch_type
== PCH_NONE
))
315 dev_priv
->pch_type
= pch_type
;
316 dev_priv
->pch_id
= id
;
322 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
325 if (pch
&& !HAS_DISPLAY(dev_priv
)) {
326 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
327 dev_priv
->pch_type
= PCH_NOP
;
328 dev_priv
->pch_id
= 0;
332 DRM_DEBUG_KMS("No PCH found.\n");
337 static int i915_getparam_ioctl(struct drm_device
*dev
, void *data
,
338 struct drm_file
*file_priv
)
340 struct drm_i915_private
*dev_priv
= to_i915(dev
);
341 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
342 const struct sseu_dev_info
*sseu
= &RUNTIME_INFO(dev_priv
)->sseu
;
343 drm_i915_getparam_t
*param
= data
;
346 switch (param
->param
) {
347 case I915_PARAM_IRQ_ACTIVE
:
348 case I915_PARAM_ALLOW_BATCHBUFFER
:
349 case I915_PARAM_LAST_DISPATCH
:
350 case I915_PARAM_HAS_EXEC_CONSTANTS
:
351 /* Reject all old ums/dri params. */
353 case I915_PARAM_CHIPSET_ID
:
354 value
= pdev
->device
;
356 case I915_PARAM_REVISION
:
357 value
= pdev
->revision
;
359 case I915_PARAM_NUM_FENCES_AVAIL
:
360 value
= dev_priv
->ggtt
.num_fences
;
362 case I915_PARAM_HAS_OVERLAY
:
363 value
= dev_priv
->overlay
? 1 : 0;
365 case I915_PARAM_HAS_BSD
:
366 value
= !!dev_priv
->engine
[VCS0
];
368 case I915_PARAM_HAS_BLT
:
369 value
= !!dev_priv
->engine
[BCS0
];
371 case I915_PARAM_HAS_VEBOX
:
372 value
= !!dev_priv
->engine
[VECS0
];
374 case I915_PARAM_HAS_BSD2
:
375 value
= !!dev_priv
->engine
[VCS1
];
377 case I915_PARAM_HAS_LLC
:
378 value
= HAS_LLC(dev_priv
);
380 case I915_PARAM_HAS_WT
:
381 value
= HAS_WT(dev_priv
);
383 case I915_PARAM_HAS_ALIASING_PPGTT
:
384 value
= INTEL_PPGTT(dev_priv
);
386 case I915_PARAM_HAS_SEMAPHORES
:
387 value
= !!(dev_priv
->caps
.scheduler
& I915_SCHEDULER_CAP_SEMAPHORES
);
389 case I915_PARAM_HAS_SECURE_BATCHES
:
390 value
= capable(CAP_SYS_ADMIN
);
392 case I915_PARAM_CMD_PARSER_VERSION
:
393 value
= i915_cmd_parser_get_version(dev_priv
);
395 case I915_PARAM_SUBSLICE_TOTAL
:
396 value
= intel_sseu_subslice_total(sseu
);
400 case I915_PARAM_EU_TOTAL
:
401 value
= sseu
->eu_total
;
405 case I915_PARAM_HAS_GPU_RESET
:
406 value
= i915_modparams
.enable_hangcheck
&&
407 intel_has_gpu_reset(dev_priv
);
408 if (value
&& intel_has_reset_engine(dev_priv
))
411 case I915_PARAM_HAS_RESOURCE_STREAMER
:
414 case I915_PARAM_HAS_POOLED_EU
:
415 value
= HAS_POOLED_EU(dev_priv
);
417 case I915_PARAM_MIN_EU_IN_POOL
:
418 value
= sseu
->min_eu_in_pool
;
420 case I915_PARAM_HUC_STATUS
:
421 value
= intel_huc_check_status(&dev_priv
->huc
);
425 case I915_PARAM_MMAP_GTT_VERSION
:
426 /* Though we've started our numbering from 1, and so class all
427 * earlier versions as 0, in effect their value is undefined as
428 * the ioctl will report EINVAL for the unknown param!
430 value
= i915_gem_mmap_gtt_version();
432 case I915_PARAM_HAS_SCHEDULER
:
433 value
= dev_priv
->caps
.scheduler
;
436 case I915_PARAM_MMAP_VERSION
:
437 /* Remember to bump this if the version changes! */
438 case I915_PARAM_HAS_GEM
:
439 case I915_PARAM_HAS_PAGEFLIPPING
:
440 case I915_PARAM_HAS_EXECBUF2
: /* depends on GEM */
441 case I915_PARAM_HAS_RELAXED_FENCING
:
442 case I915_PARAM_HAS_COHERENT_RINGS
:
443 case I915_PARAM_HAS_RELAXED_DELTA
:
444 case I915_PARAM_HAS_GEN7_SOL_RESET
:
445 case I915_PARAM_HAS_WAIT_TIMEOUT
:
446 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
447 case I915_PARAM_HAS_PINNED_BATCHES
:
448 case I915_PARAM_HAS_EXEC_NO_RELOC
:
449 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
450 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
451 case I915_PARAM_HAS_EXEC_SOFTPIN
:
452 case I915_PARAM_HAS_EXEC_ASYNC
:
453 case I915_PARAM_HAS_EXEC_FENCE
:
454 case I915_PARAM_HAS_EXEC_CAPTURE
:
455 case I915_PARAM_HAS_EXEC_BATCH_FIRST
:
456 case I915_PARAM_HAS_EXEC_FENCE_ARRAY
:
457 case I915_PARAM_HAS_EXEC_SUBMIT_FENCE
:
458 /* For the time being all of these are always true;
459 * if some supported hardware does not have one of these
460 * features this value needs to be provided from
461 * INTEL_INFO(), a feature macro, or similar.
465 case I915_PARAM_HAS_CONTEXT_ISOLATION
:
466 value
= intel_engines_has_context_isolation(dev_priv
);
468 case I915_PARAM_SLICE_MASK
:
469 value
= sseu
->slice_mask
;
473 case I915_PARAM_SUBSLICE_MASK
:
474 value
= sseu
->subslice_mask
[0];
478 case I915_PARAM_CS_TIMESTAMP_FREQUENCY
:
479 value
= 1000 * RUNTIME_INFO(dev_priv
)->cs_timestamp_frequency_khz
;
481 case I915_PARAM_MMAP_GTT_COHERENT
:
482 value
= INTEL_INFO(dev_priv
)->has_coherent_ggtt
;
485 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
489 if (put_user(value
, param
->value
))
495 static int i915_get_bridge_dev(struct drm_i915_private
*dev_priv
)
497 int domain
= pci_domain_nr(dev_priv
->drm
.pdev
->bus
);
499 dev_priv
->bridge_dev
=
500 pci_get_domain_bus_and_slot(domain
, 0, PCI_DEVFN(0, 0));
501 if (!dev_priv
->bridge_dev
) {
502 DRM_ERROR("bridge device not found\n");
508 /* Allocate space for the MCH regs if needed, return nonzero on error */
510 intel_alloc_mchbar_resource(struct drm_i915_private
*dev_priv
)
512 int reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
513 u32 temp_lo
, temp_hi
= 0;
517 if (INTEL_GEN(dev_priv
) >= 4)
518 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
519 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
520 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
522 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
525 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
529 /* Get some space for it */
530 dev_priv
->mch_res
.name
= "i915 MCHBAR";
531 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
532 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
534 MCHBAR_SIZE
, MCHBAR_SIZE
,
536 0, pcibios_align_resource
,
537 dev_priv
->bridge_dev
);
539 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
540 dev_priv
->mch_res
.start
= 0;
544 if (INTEL_GEN(dev_priv
) >= 4)
545 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
546 upper_32_bits(dev_priv
->mch_res
.start
));
548 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
549 lower_32_bits(dev_priv
->mch_res
.start
));
553 /* Setup MCHBAR if possible, return true if we should disable it again */
555 intel_setup_mchbar(struct drm_i915_private
*dev_priv
)
557 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
561 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
564 dev_priv
->mchbar_need_disable
= false;
566 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
567 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
568 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
570 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
574 /* If it's already enabled, don't have to do anything */
578 if (intel_alloc_mchbar_resource(dev_priv
))
581 dev_priv
->mchbar_need_disable
= true;
583 /* Space is allocated or reserved, so enable it. */
584 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
585 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
586 temp
| DEVEN_MCHBAR_EN
);
588 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
589 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
594 intel_teardown_mchbar(struct drm_i915_private
*dev_priv
)
596 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
598 if (dev_priv
->mchbar_need_disable
) {
599 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
602 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
604 deven_val
&= ~DEVEN_MCHBAR_EN
;
605 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
610 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
613 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
618 if (dev_priv
->mch_res
.start
)
619 release_resource(&dev_priv
->mch_res
);
622 /* true = enable decode, false = disable decoder */
623 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
625 struct drm_i915_private
*dev_priv
= cookie
;
627 intel_modeset_vga_set_state(dev_priv
, state
);
629 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
630 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
632 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
635 static int i915_resume_switcheroo(struct drm_device
*dev
);
636 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
638 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
640 struct drm_device
*dev
= pci_get_drvdata(pdev
);
641 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
643 if (state
== VGA_SWITCHEROO_ON
) {
644 pr_info("switched on\n");
645 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
646 /* i915 resume handler doesn't set to D0 */
647 pci_set_power_state(pdev
, PCI_D0
);
648 i915_resume_switcheroo(dev
);
649 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
651 pr_info("switched off\n");
652 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
653 i915_suspend_switcheroo(dev
, pmm
);
654 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
658 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
660 struct drm_device
*dev
= pci_get_drvdata(pdev
);
663 * FIXME: open_count is protected by drm_global_mutex but that would lead to
664 * locking inversion with the driver load path. And the access here is
665 * completely racy anyway. So don't bother with locking for now.
667 return dev
->open_count
== 0;
670 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
671 .set_gpu_state
= i915_switcheroo_set_state
,
673 .can_switch
= i915_switcheroo_can_switch
,
676 static int i915_load_modeset_init(struct drm_device
*dev
)
678 struct drm_i915_private
*dev_priv
= to_i915(dev
);
679 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
682 if (i915_inject_load_failure())
685 if (HAS_DISPLAY(dev_priv
)) {
686 ret
= drm_vblank_init(&dev_priv
->drm
,
687 INTEL_INFO(dev_priv
)->num_pipes
);
692 intel_bios_init(dev_priv
);
694 /* If we have > 1 VGA cards, then we need to arbitrate access
695 * to the common VGA resources.
697 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
698 * then we do not take part in VGA arbitration and the
699 * vga_client_register() fails with -ENODEV.
701 ret
= vga_client_register(pdev
, dev_priv
, NULL
, i915_vga_set_decode
);
702 if (ret
&& ret
!= -ENODEV
)
705 intel_register_dsm_handler();
707 ret
= vga_switcheroo_register_client(pdev
, &i915_switcheroo_ops
, false);
709 goto cleanup_vga_client
;
711 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
712 intel_update_rawclk(dev_priv
);
714 intel_power_domains_init_hw(dev_priv
, false);
716 intel_csr_ucode_init(dev_priv
);
718 ret
= intel_irq_install(dev_priv
);
722 intel_gmbus_setup(dev_priv
);
724 /* Important: The output setup functions called by modeset_init need
725 * working irqs for e.g. gmbus and dp aux transfers. */
726 ret
= intel_modeset_init(dev
);
730 ret
= i915_gem_init(dev_priv
);
732 goto cleanup_modeset
;
734 intel_overlay_setup(dev_priv
);
736 if (!HAS_DISPLAY(dev_priv
))
739 ret
= intel_fbdev_init(dev
);
743 /* Only enable hotplug handling once the fbdev is fully set up. */
744 intel_hpd_init(dev_priv
);
746 intel_init_ipc(dev_priv
);
751 i915_gem_suspend(dev_priv
);
752 i915_gem_fini_hw(dev_priv
);
753 i915_gem_fini(dev_priv
);
755 intel_modeset_cleanup(dev
);
757 drm_irq_uninstall(dev
);
758 intel_gmbus_teardown(dev_priv
);
760 intel_csr_ucode_fini(dev_priv
);
761 intel_power_domains_fini_hw(dev_priv
);
762 vga_switcheroo_unregister_client(pdev
);
764 vga_client_register(pdev
, NULL
, NULL
, NULL
);
769 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
771 struct apertures_struct
*ap
;
772 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
773 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
777 ap
= alloc_apertures(1);
781 ap
->ranges
[0].base
= ggtt
->gmadr
.start
;
782 ap
->ranges
[0].size
= ggtt
->mappable_end
;
785 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
787 ret
= drm_fb_helper_remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
794 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
797 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
798 * CHV x1 PHY (DP/HDMI D)
799 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
801 if (IS_CHERRYVIEW(dev_priv
)) {
802 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
803 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
804 } else if (IS_VALLEYVIEW(dev_priv
)) {
805 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
809 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
812 * The i915 workqueue is primarily used for batched retirement of
813 * requests (and thus managing bo) once the task has been completed
814 * by the GPU. i915_retire_requests() is called directly when we
815 * need high-priority retirement, such as waiting for an explicit
818 * It is also used for periodic low-priority events, such as
819 * idle-timers and recording error state.
821 * All tasks on the workqueue are expected to acquire the dev mutex
822 * so there is no point in running more than one instance of the
823 * workqueue at any time. Use an ordered one.
825 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
826 if (dev_priv
->wq
== NULL
)
829 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
830 if (dev_priv
->hotplug
.dp_wq
== NULL
)
836 destroy_workqueue(dev_priv
->wq
);
838 DRM_ERROR("Failed to allocate workqueues.\n");
843 static void i915_engines_cleanup(struct drm_i915_private
*i915
)
845 struct intel_engine_cs
*engine
;
846 enum intel_engine_id id
;
848 for_each_engine(engine
, i915
, id
)
852 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
854 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
855 destroy_workqueue(dev_priv
->wq
);
859 * We don't keep the workarounds for pre-production hardware, so we expect our
860 * driver to fail on these machines in one way or another. A little warning on
861 * dmesg may help both the user and the bug triagers.
863 * Our policy for removing pre-production workarounds is to keep the
864 * current gen workarounds as a guide to the bring-up of the next gen
865 * (workarounds have a habit of persisting!). Anything older than that
866 * should be removed along with the complications they introduce.
868 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
872 pre
|= IS_HSW_EARLY_SDV(dev_priv
);
873 pre
|= IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
);
874 pre
|= IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B_LAST
);
875 pre
|= IS_KBL_REVID(dev_priv
, 0, KBL_REVID_A0
);
878 DRM_ERROR("This is a pre-production stepping. "
879 "It may not be fully functional.\n");
880 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_STILL_OK
);
885 * i915_driver_init_early - setup state not requiring device access
886 * @dev_priv: device private
888 * Initialize everything that is a "SW-only" state, that is state not
889 * requiring accessing the device or exposing the driver via kernel internal
890 * or userspace interfaces. Example steps belonging here: lock initialization,
891 * system memory allocation, setting up device specific attributes and
892 * function hooks not requiring accessing the device.
894 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
)
898 if (i915_inject_load_failure())
901 intel_device_info_subplatform_init(dev_priv
);
903 intel_uncore_init_early(&dev_priv
->uncore
);
905 spin_lock_init(&dev_priv
->irq_lock
);
906 spin_lock_init(&dev_priv
->gpu_error
.lock
);
907 mutex_init(&dev_priv
->backlight_lock
);
909 mutex_init(&dev_priv
->sb_lock
);
910 pm_qos_add_request(&dev_priv
->sb_qos
,
911 PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
913 mutex_init(&dev_priv
->av_mutex
);
914 mutex_init(&dev_priv
->wm
.wm_mutex
);
915 mutex_init(&dev_priv
->pps_mutex
);
916 mutex_init(&dev_priv
->hdcp_comp_mutex
);
918 i915_memcpy_init_early(dev_priv
);
919 intel_runtime_pm_init_early(&dev_priv
->runtime_pm
);
921 ret
= i915_workqueues_init(dev_priv
);
925 ret
= i915_gem_init_early(dev_priv
);
929 /* This must be called before any calls to HAS_PCH_* */
930 intel_detect_pch(dev_priv
);
932 intel_wopcm_init_early(&dev_priv
->wopcm
);
933 intel_uc_init_early(dev_priv
);
934 intel_pm_setup(dev_priv
);
935 intel_init_dpio(dev_priv
);
936 ret
= intel_power_domains_init(dev_priv
);
939 intel_irq_init(dev_priv
);
940 intel_hangcheck_init(dev_priv
);
941 intel_init_display_hooks(dev_priv
);
942 intel_init_clock_gating_hooks(dev_priv
);
943 intel_init_audio_hooks(dev_priv
);
944 intel_display_crc_init(dev_priv
);
946 intel_detect_preproduction_hw(dev_priv
);
951 intel_uc_cleanup_early(dev_priv
);
952 i915_gem_cleanup_early(dev_priv
);
954 i915_workqueues_cleanup(dev_priv
);
956 i915_engines_cleanup(dev_priv
);
961 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
962 * @dev_priv: device private
964 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
966 intel_irq_fini(dev_priv
);
967 intel_power_domains_cleanup(dev_priv
);
968 intel_uc_cleanup_early(dev_priv
);
969 i915_gem_cleanup_early(dev_priv
);
970 i915_workqueues_cleanup(dev_priv
);
971 i915_engines_cleanup(dev_priv
);
973 pm_qos_remove_request(&dev_priv
->sb_qos
);
974 mutex_destroy(&dev_priv
->sb_lock
);
978 * i915_driver_init_mmio - setup device MMIO
979 * @dev_priv: device private
981 * Setup minimal device state necessary for MMIO accesses later in the
982 * initialization sequence. The setup here should avoid any other device-wide
983 * side effects or exposing the driver via kernel internal or user space
986 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
990 if (i915_inject_load_failure())
993 if (i915_get_bridge_dev(dev_priv
))
996 ret
= intel_uncore_init_mmio(&dev_priv
->uncore
);
1000 /* Try to make sure MCHBAR is enabled before poking at it */
1001 intel_setup_mchbar(dev_priv
);
1003 intel_device_info_init_mmio(dev_priv
);
1005 intel_uncore_prune_mmio_domains(&dev_priv
->uncore
);
1007 intel_uc_init_mmio(dev_priv
);
1009 ret
= intel_engines_init_mmio(dev_priv
);
1013 i915_gem_init_mmio(dev_priv
);
1018 intel_teardown_mchbar(dev_priv
);
1019 intel_uncore_fini_mmio(&dev_priv
->uncore
);
1021 pci_dev_put(dev_priv
->bridge_dev
);
1027 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1028 * @dev_priv: device private
1030 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
1032 intel_teardown_mchbar(dev_priv
);
1033 intel_uncore_fini_mmio(&dev_priv
->uncore
);
1034 pci_dev_put(dev_priv
->bridge_dev
);
1037 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
1039 intel_gvt_sanitize_options(dev_priv
);
1042 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
1044 static const char *intel_dram_type_str(enum intel_dram_type type
)
1046 static const char * const str
[] = {
1047 DRAM_TYPE_STR(UNKNOWN
),
1048 DRAM_TYPE_STR(DDR3
),
1049 DRAM_TYPE_STR(DDR4
),
1050 DRAM_TYPE_STR(LPDDR3
),
1051 DRAM_TYPE_STR(LPDDR4
),
1054 if (type
>= ARRAY_SIZE(str
))
1055 type
= INTEL_DRAM_UNKNOWN
;
1060 #undef DRAM_TYPE_STR
1062 static int intel_dimm_num_devices(const struct dram_dimm_info
*dimm
)
1064 return dimm
->ranks
* 64 / (dimm
->width
?: 1);
1067 /* Returns total GB for the whole DIMM */
1068 static int skl_get_dimm_size(u16 val
)
1070 return val
& SKL_DRAM_SIZE_MASK
;
1073 static int skl_get_dimm_width(u16 val
)
1075 if (skl_get_dimm_size(val
) == 0)
1078 switch (val
& SKL_DRAM_WIDTH_MASK
) {
1079 case SKL_DRAM_WIDTH_X8
:
1080 case SKL_DRAM_WIDTH_X16
:
1081 case SKL_DRAM_WIDTH_X32
:
1082 val
= (val
& SKL_DRAM_WIDTH_MASK
) >> SKL_DRAM_WIDTH_SHIFT
;
1090 static int skl_get_dimm_ranks(u16 val
)
1092 if (skl_get_dimm_size(val
) == 0)
1095 val
= (val
& SKL_DRAM_RANK_MASK
) >> SKL_DRAM_RANK_SHIFT
;
1100 /* Returns total GB for the whole DIMM */
1101 static int cnl_get_dimm_size(u16 val
)
1103 return (val
& CNL_DRAM_SIZE_MASK
) / 2;
1106 static int cnl_get_dimm_width(u16 val
)
1108 if (cnl_get_dimm_size(val
) == 0)
1111 switch (val
& CNL_DRAM_WIDTH_MASK
) {
1112 case CNL_DRAM_WIDTH_X8
:
1113 case CNL_DRAM_WIDTH_X16
:
1114 case CNL_DRAM_WIDTH_X32
:
1115 val
= (val
& CNL_DRAM_WIDTH_MASK
) >> CNL_DRAM_WIDTH_SHIFT
;
1123 static int cnl_get_dimm_ranks(u16 val
)
1125 if (cnl_get_dimm_size(val
) == 0)
1128 val
= (val
& CNL_DRAM_RANK_MASK
) >> CNL_DRAM_RANK_SHIFT
;
1134 skl_is_16gb_dimm(const struct dram_dimm_info
*dimm
)
1136 /* Convert total GB to Gb per DRAM device */
1137 return 8 * dimm
->size
/ (intel_dimm_num_devices(dimm
) ?: 1) == 16;
1141 skl_dram_get_dimm_info(struct drm_i915_private
*dev_priv
,
1142 struct dram_dimm_info
*dimm
,
1143 int channel
, char dimm_name
, u16 val
)
1145 if (INTEL_GEN(dev_priv
) >= 10) {
1146 dimm
->size
= cnl_get_dimm_size(val
);
1147 dimm
->width
= cnl_get_dimm_width(val
);
1148 dimm
->ranks
= cnl_get_dimm_ranks(val
);
1150 dimm
->size
= skl_get_dimm_size(val
);
1151 dimm
->width
= skl_get_dimm_width(val
);
1152 dimm
->ranks
= skl_get_dimm_ranks(val
);
1155 DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
1156 channel
, dimm_name
, dimm
->size
, dimm
->width
, dimm
->ranks
,
1157 yesno(skl_is_16gb_dimm(dimm
)));
1161 skl_dram_get_channel_info(struct drm_i915_private
*dev_priv
,
1162 struct dram_channel_info
*ch
,
1163 int channel
, u32 val
)
1165 skl_dram_get_dimm_info(dev_priv
, &ch
->dimm_l
,
1166 channel
, 'L', val
& 0xffff);
1167 skl_dram_get_dimm_info(dev_priv
, &ch
->dimm_s
,
1168 channel
, 'S', val
>> 16);
1170 if (ch
->dimm_l
.size
== 0 && ch
->dimm_s
.size
== 0) {
1171 DRM_DEBUG_KMS("CH%u not populated\n", channel
);
1175 if (ch
->dimm_l
.ranks
== 2 || ch
->dimm_s
.ranks
== 2)
1177 else if (ch
->dimm_l
.ranks
== 1 && ch
->dimm_s
.ranks
== 1)
1183 skl_is_16gb_dimm(&ch
->dimm_l
) ||
1184 skl_is_16gb_dimm(&ch
->dimm_s
);
1186 DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
1187 channel
, ch
->ranks
, yesno(ch
->is_16gb_dimm
));
1193 intel_is_dram_symmetric(const struct dram_channel_info
*ch0
,
1194 const struct dram_channel_info
*ch1
)
1196 return !memcmp(ch0
, ch1
, sizeof(*ch0
)) &&
1197 (ch0
->dimm_s
.size
== 0 ||
1198 !memcmp(&ch0
->dimm_l
, &ch0
->dimm_s
, sizeof(ch0
->dimm_l
)));
1202 skl_dram_get_channels_info(struct drm_i915_private
*dev_priv
)
1204 struct dram_info
*dram_info
= &dev_priv
->dram_info
;
1205 struct dram_channel_info ch0
= {}, ch1
= {};
1209 val
= I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN
);
1210 ret
= skl_dram_get_channel_info(dev_priv
, &ch0
, 0, val
);
1212 dram_info
->num_channels
++;
1214 val
= I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN
);
1215 ret
= skl_dram_get_channel_info(dev_priv
, &ch1
, 1, val
);
1217 dram_info
->num_channels
++;
1219 if (dram_info
->num_channels
== 0) {
1220 DRM_INFO("Number of memory channels is zero\n");
1225 * If any of the channel is single rank channel, worst case output
1226 * will be same as if single rank memory, so consider single rank
1229 if (ch0
.ranks
== 1 || ch1
.ranks
== 1)
1230 dram_info
->ranks
= 1;
1232 dram_info
->ranks
= max(ch0
.ranks
, ch1
.ranks
);
1234 if (dram_info
->ranks
== 0) {
1235 DRM_INFO("couldn't get memory rank information\n");
1239 dram_info
->is_16gb_dimm
= ch0
.is_16gb_dimm
|| ch1
.is_16gb_dimm
;
1241 dram_info
->symmetric_memory
= intel_is_dram_symmetric(&ch0
, &ch1
);
1243 DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
1244 yesno(dram_info
->symmetric_memory
));
1248 static enum intel_dram_type
1249 skl_get_dram_type(struct drm_i915_private
*dev_priv
)
1253 val
= I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN
);
1255 switch (val
& SKL_DRAM_DDR_TYPE_MASK
) {
1256 case SKL_DRAM_DDR_TYPE_DDR3
:
1257 return INTEL_DRAM_DDR3
;
1258 case SKL_DRAM_DDR_TYPE_DDR4
:
1259 return INTEL_DRAM_DDR4
;
1260 case SKL_DRAM_DDR_TYPE_LPDDR3
:
1261 return INTEL_DRAM_LPDDR3
;
1262 case SKL_DRAM_DDR_TYPE_LPDDR4
:
1263 return INTEL_DRAM_LPDDR4
;
1266 return INTEL_DRAM_UNKNOWN
;
1271 skl_get_dram_info(struct drm_i915_private
*dev_priv
)
1273 struct dram_info
*dram_info
= &dev_priv
->dram_info
;
1274 u32 mem_freq_khz
, val
;
1277 dram_info
->type
= skl_get_dram_type(dev_priv
);
1278 DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info
->type
));
1280 ret
= skl_dram_get_channels_info(dev_priv
);
1284 val
= I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU
);
1285 mem_freq_khz
= DIV_ROUND_UP((val
& SKL_REQ_DATA_MASK
) *
1286 SKL_MEMORY_FREQ_MULTIPLIER_HZ
, 1000);
1288 dram_info
->bandwidth_kbps
= dram_info
->num_channels
*
1291 if (dram_info
->bandwidth_kbps
== 0) {
1292 DRM_INFO("Couldn't get system memory bandwidth\n");
1296 dram_info
->valid
= true;
1300 /* Returns Gb per DRAM device */
1301 static int bxt_get_dimm_size(u32 val
)
1303 switch (val
& BXT_DRAM_SIZE_MASK
) {
1304 case BXT_DRAM_SIZE_4GBIT
:
1306 case BXT_DRAM_SIZE_6GBIT
:
1308 case BXT_DRAM_SIZE_8GBIT
:
1310 case BXT_DRAM_SIZE_12GBIT
:
1312 case BXT_DRAM_SIZE_16GBIT
:
1320 static int bxt_get_dimm_width(u32 val
)
1322 if (!bxt_get_dimm_size(val
))
1325 val
= (val
& BXT_DRAM_WIDTH_MASK
) >> BXT_DRAM_WIDTH_SHIFT
;
1330 static int bxt_get_dimm_ranks(u32 val
)
1332 if (!bxt_get_dimm_size(val
))
1335 switch (val
& BXT_DRAM_RANK_MASK
) {
1336 case BXT_DRAM_RANK_SINGLE
:
1338 case BXT_DRAM_RANK_DUAL
:
1346 static enum intel_dram_type
bxt_get_dimm_type(u32 val
)
1348 if (!bxt_get_dimm_size(val
))
1349 return INTEL_DRAM_UNKNOWN
;
1351 switch (val
& BXT_DRAM_TYPE_MASK
) {
1352 case BXT_DRAM_TYPE_DDR3
:
1353 return INTEL_DRAM_DDR3
;
1354 case BXT_DRAM_TYPE_LPDDR3
:
1355 return INTEL_DRAM_LPDDR3
;
1356 case BXT_DRAM_TYPE_DDR4
:
1357 return INTEL_DRAM_DDR4
;
1358 case BXT_DRAM_TYPE_LPDDR4
:
1359 return INTEL_DRAM_LPDDR4
;
1362 return INTEL_DRAM_UNKNOWN
;
1366 static void bxt_get_dimm_info(struct dram_dimm_info
*dimm
,
1369 dimm
->width
= bxt_get_dimm_width(val
);
1370 dimm
->ranks
= bxt_get_dimm_ranks(val
);
1373 * Size in register is Gb per DRAM device. Convert to total
1374 * GB to match the way we report this for non-LP platforms.
1376 dimm
->size
= bxt_get_dimm_size(val
) * intel_dimm_num_devices(dimm
) / 8;
1380 bxt_get_dram_info(struct drm_i915_private
*dev_priv
)
1382 struct dram_info
*dram_info
= &dev_priv
->dram_info
;
1384 u32 mem_freq_khz
, val
;
1385 u8 num_active_channels
;
1388 val
= I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0
);
1389 mem_freq_khz
= DIV_ROUND_UP((val
& BXT_REQ_DATA_MASK
) *
1390 BXT_MEMORY_FREQ_MULTIPLIER_HZ
, 1000);
1392 dram_channels
= val
& BXT_DRAM_CHANNEL_ACTIVE_MASK
;
1393 num_active_channels
= hweight32(dram_channels
);
1395 /* Each active bit represents 4-byte channel */
1396 dram_info
->bandwidth_kbps
= (mem_freq_khz
* num_active_channels
* 4);
1398 if (dram_info
->bandwidth_kbps
== 0) {
1399 DRM_INFO("Couldn't get system memory bandwidth\n");
1404 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1406 for (i
= BXT_D_CR_DRP0_DUNIT_START
; i
<= BXT_D_CR_DRP0_DUNIT_END
; i
++) {
1407 struct dram_dimm_info dimm
;
1408 enum intel_dram_type type
;
1410 val
= I915_READ(BXT_D_CR_DRP0_DUNIT(i
));
1411 if (val
== 0xFFFFFFFF)
1414 dram_info
->num_channels
++;
1416 bxt_get_dimm_info(&dimm
, val
);
1417 type
= bxt_get_dimm_type(val
);
1419 WARN_ON(type
!= INTEL_DRAM_UNKNOWN
&&
1420 dram_info
->type
!= INTEL_DRAM_UNKNOWN
&&
1421 dram_info
->type
!= type
);
1423 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1424 i
- BXT_D_CR_DRP0_DUNIT_START
,
1425 dimm
.size
, dimm
.width
, dimm
.ranks
,
1426 intel_dram_type_str(type
));
1429 * If any of the channel is single rank channel,
1430 * worst case output will be same as if single rank
1431 * memory, so consider single rank memory.
1433 if (dram_info
->ranks
== 0)
1434 dram_info
->ranks
= dimm
.ranks
;
1435 else if (dimm
.ranks
== 1)
1436 dram_info
->ranks
= 1;
1438 if (type
!= INTEL_DRAM_UNKNOWN
)
1439 dram_info
->type
= type
;
1442 if (dram_info
->type
== INTEL_DRAM_UNKNOWN
||
1443 dram_info
->ranks
== 0) {
1444 DRM_INFO("couldn't get memory information\n");
1448 dram_info
->valid
= true;
1453 intel_get_dram_info(struct drm_i915_private
*dev_priv
)
1455 struct dram_info
*dram_info
= &dev_priv
->dram_info
;
1459 * Assume 16Gb DIMMs are present until proven otherwise.
1460 * This is only used for the level 0 watermark latency
1461 * w/a which does not apply to bxt/glk.
1463 dram_info
->is_16gb_dimm
= !IS_GEN9_LP(dev_priv
);
1465 if (INTEL_GEN(dev_priv
) < 9)
1468 if (IS_GEN9_LP(dev_priv
))
1469 ret
= bxt_get_dram_info(dev_priv
);
1471 ret
= skl_get_dram_info(dev_priv
);
1475 DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1476 dram_info
->bandwidth_kbps
,
1477 dram_info
->num_channels
);
1479 DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1480 dram_info
->ranks
, yesno(dram_info
->is_16gb_dimm
));
1483 static u32
gen9_edram_size_mb(struct drm_i915_private
*dev_priv
, u32 cap
)
1485 const unsigned int ways
[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1486 const unsigned int sets
[4] = { 1, 1, 2, 2 };
1488 return EDRAM_NUM_BANKS(cap
) *
1489 ways
[EDRAM_WAYS_IDX(cap
)] *
1490 sets
[EDRAM_SETS_IDX(cap
)];
1493 static void edram_detect(struct drm_i915_private
*dev_priv
)
1497 if (!(IS_HASWELL(dev_priv
) ||
1498 IS_BROADWELL(dev_priv
) ||
1499 INTEL_GEN(dev_priv
) >= 9))
1502 edram_cap
= __raw_uncore_read32(&dev_priv
->uncore
, HSW_EDRAM_CAP
);
1504 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1506 if (!(edram_cap
& EDRAM_ENABLED
))
1510 * The needed capability bits for size calculation are not there with
1511 * pre gen9 so return 128MB always.
1513 if (INTEL_GEN(dev_priv
) < 9)
1514 dev_priv
->edram_size_mb
= 128;
1516 dev_priv
->edram_size_mb
=
1517 gen9_edram_size_mb(dev_priv
, edram_cap
);
1519 DRM_INFO("Found %uMB of eDRAM\n", dev_priv
->edram_size_mb
);
1523 * i915_driver_init_hw - setup state requiring device access
1524 * @dev_priv: device private
1526 * Setup state that requires accessing the device, but doesn't require
1527 * exposing the driver via kernel internal or userspace interfaces.
1529 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
1531 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1534 if (i915_inject_load_failure())
1537 intel_device_info_runtime_init(dev_priv
);
1539 if (HAS_PPGTT(dev_priv
)) {
1540 if (intel_vgpu_active(dev_priv
) &&
1541 !intel_vgpu_has_full_ppgtt(dev_priv
)) {
1542 i915_report_error(dev_priv
,
1543 "incompatible vGPU found, support for isolated ppGTT required\n");
1548 if (HAS_EXECLISTS(dev_priv
)) {
1550 * Older GVT emulation depends upon intercepting CSB mmio,
1551 * which we no longer use, preferring to use the HWSP cache
1554 if (intel_vgpu_active(dev_priv
) &&
1555 !intel_vgpu_has_hwsp_emulation(dev_priv
)) {
1556 i915_report_error(dev_priv
,
1557 "old vGPU host found, support for HWSP emulation required\n");
1562 intel_sanitize_options(dev_priv
);
1564 /* needs to be done before ggtt probe */
1565 edram_detect(dev_priv
);
1567 i915_perf_init(dev_priv
);
1569 ret
= i915_ggtt_probe_hw(dev_priv
);
1574 * WARNING: Apparently we must kick fbdev drivers before vgacon,
1575 * otherwise the vga fbdev driver falls over.
1577 ret
= i915_kick_out_firmware_fb(dev_priv
);
1579 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1583 ret
= vga_remove_vgacon(pdev
);
1585 DRM_ERROR("failed to remove conflicting VGA console\n");
1589 ret
= i915_ggtt_init_hw(dev_priv
);
1593 ret
= i915_ggtt_enable_hw(dev_priv
);
1595 DRM_ERROR("failed to enable GGTT\n");
1599 pci_set_master(pdev
);
1601 /* overlay on gen2 is broken and can't address above 1G */
1602 if (IS_GEN(dev_priv
, 2)) {
1603 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1605 DRM_ERROR("failed to set DMA mask\n");
1611 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1612 * using 32bit addressing, overwriting memory if HWS is located
1615 * The documentation also mentions an issue with undefined
1616 * behaviour if any general state is accessed within a page above 4GB,
1617 * which also needs to be handled carefully.
1619 if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
)) {
1620 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1623 DRM_ERROR("failed to set DMA mask\n");
1629 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1630 PM_QOS_DEFAULT_VALUE
);
1632 intel_uncore_sanitize(dev_priv
);
1634 intel_gt_init_workarounds(dev_priv
);
1636 /* On the 945G/GM, the chipset reports the MSI capability on the
1637 * integrated graphics even though the support isn't actually there
1638 * according to the published specs. It doesn't appear to function
1639 * correctly in testing on 945G.
1640 * This may be a side effect of MSI having been made available for PEG
1641 * and the registers being closely associated.
1643 * According to chipset errata, on the 965GM, MSI interrupts may
1644 * be lost or delayed, and was defeatured. MSI interrupts seem to
1645 * get lost on g4x as well, and interrupt delivery seems to stay
1646 * properly dead afterwards. So we'll just disable them for all
1647 * pre-gen5 chipsets.
1649 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1650 * interrupts even when in MSI mode. This results in spurious
1651 * interrupt warnings if the legacy irq no. is shared with another
1652 * device. The kernel then disables that interrupt source and so
1653 * prevents the other device from working properly.
1655 if (INTEL_GEN(dev_priv
) >= 5) {
1656 if (pci_enable_msi(pdev
) < 0)
1657 DRM_DEBUG_DRIVER("can't enable MSI");
1660 ret
= intel_gvt_init(dev_priv
);
1664 intel_opregion_setup(dev_priv
);
1666 * Fill the dram structure to get the system raw bandwidth and
1667 * dram info. This will be used for memory latency calculation.
1669 intel_get_dram_info(dev_priv
);
1671 intel_bw_init_hw(dev_priv
);
1676 if (pdev
->msi_enabled
)
1677 pci_disable_msi(pdev
);
1678 pm_qos_remove_request(&dev_priv
->pm_qos
);
1680 i915_ggtt_cleanup_hw(dev_priv
);
1682 i915_perf_fini(dev_priv
);
1687 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1688 * @dev_priv: device private
1690 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1692 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1694 i915_perf_fini(dev_priv
);
1696 if (pdev
->msi_enabled
)
1697 pci_disable_msi(pdev
);
1699 pm_qos_remove_request(&dev_priv
->pm_qos
);
1703 * i915_driver_register - register the driver with the rest of the system
1704 * @dev_priv: device private
1706 * Perform any steps necessary to make the driver available via kernel
1707 * internal or userspace interfaces.
1709 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1711 struct drm_device
*dev
= &dev_priv
->drm
;
1713 i915_gem_shrinker_register(dev_priv
);
1714 i915_pmu_register(dev_priv
);
1717 * Notify a valid surface after modesetting,
1718 * when running inside a VM.
1720 if (intel_vgpu_active(dev_priv
))
1721 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1723 /* Reveal our presence to userspace */
1724 if (drm_dev_register(dev
, 0) == 0) {
1725 i915_debugfs_register(dev_priv
);
1726 i915_setup_sysfs(dev_priv
);
1728 /* Depends on sysfs having been initialized */
1729 i915_perf_register(dev_priv
);
1731 DRM_ERROR("Failed to register driver for userspace access!\n");
1733 if (HAS_DISPLAY(dev_priv
)) {
1734 /* Must be done after probing outputs */
1735 intel_opregion_register(dev_priv
);
1736 acpi_video_register();
1739 if (IS_GEN(dev_priv
, 5))
1740 intel_gpu_ips_init(dev_priv
);
1742 intel_audio_init(dev_priv
);
1745 * Some ports require correctly set-up hpd registers for detection to
1746 * work properly (leading to ghost connected connector status), e.g. VGA
1747 * on gm45. Hence we can only set up the initial fbdev config after hpd
1748 * irqs are fully enabled. We do it last so that the async config
1749 * cannot run before the connectors are registered.
1751 intel_fbdev_initial_config_async(dev
);
1754 * We need to coordinate the hotplugs with the asynchronous fbdev
1755 * configuration, for which we use the fbdev->async_cookie.
1757 if (HAS_DISPLAY(dev_priv
))
1758 drm_kms_helper_poll_init(dev
);
1760 intel_power_domains_enable(dev_priv
);
1761 intel_runtime_pm_enable(&dev_priv
->runtime_pm
);
1765 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1766 * @dev_priv: device private
1768 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1770 intel_runtime_pm_disable(&dev_priv
->runtime_pm
);
1771 intel_power_domains_disable(dev_priv
);
1773 intel_fbdev_unregister(dev_priv
);
1774 intel_audio_deinit(dev_priv
);
1777 * After flushing the fbdev (incl. a late async config which will
1778 * have delayed queuing of a hotplug event), then flush the hotplug
1781 drm_kms_helper_poll_fini(&dev_priv
->drm
);
1783 intel_gpu_ips_teardown();
1784 acpi_video_unregister();
1785 intel_opregion_unregister(dev_priv
);
1787 i915_perf_unregister(dev_priv
);
1788 i915_pmu_unregister(dev_priv
);
1790 i915_teardown_sysfs(dev_priv
);
1791 drm_dev_unplug(&dev_priv
->drm
);
1793 i915_gem_shrinker_unregister(dev_priv
);
1796 static void i915_welcome_messages(struct drm_i915_private
*dev_priv
)
1798 if (drm_debug
& DRM_UT_DRIVER
) {
1799 struct drm_printer p
= drm_debug_printer("i915 device info:");
1801 drm_printf(&p
, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1802 INTEL_DEVID(dev_priv
),
1803 INTEL_REVID(dev_priv
),
1804 intel_platform_name(INTEL_INFO(dev_priv
)->platform
),
1805 intel_subplatform(RUNTIME_INFO(dev_priv
),
1806 INTEL_INFO(dev_priv
)->platform
),
1807 INTEL_GEN(dev_priv
));
1809 intel_device_info_dump_flags(INTEL_INFO(dev_priv
), &p
);
1810 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv
), &p
);
1813 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
1814 DRM_INFO("DRM_I915_DEBUG enabled\n");
1815 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1816 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1817 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM
))
1818 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1821 static struct drm_i915_private
*
1822 i915_driver_create(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1824 const struct intel_device_info
*match_info
=
1825 (struct intel_device_info
*)ent
->driver_data
;
1826 struct intel_device_info
*device_info
;
1827 struct drm_i915_private
*i915
;
1830 i915
= kzalloc(sizeof(*i915
), GFP_KERNEL
);
1832 return ERR_PTR(-ENOMEM
);
1834 err
= drm_dev_init(&i915
->drm
, &driver
, &pdev
->dev
);
1837 return ERR_PTR(err
);
1840 i915
->drm
.pdev
= pdev
;
1841 i915
->drm
.dev_private
= i915
;
1842 pci_set_drvdata(pdev
, &i915
->drm
);
1844 /* Setup the write-once "constant" device info */
1845 device_info
= mkwrite_device_info(i915
);
1846 memcpy(device_info
, match_info
, sizeof(*device_info
));
1847 RUNTIME_INFO(i915
)->device_id
= pdev
->device
;
1849 BUG_ON(device_info
->gen
> BITS_PER_TYPE(device_info
->gen_mask
));
1854 static void i915_driver_destroy(struct drm_i915_private
*i915
)
1856 struct pci_dev
*pdev
= i915
->drm
.pdev
;
1858 drm_dev_fini(&i915
->drm
);
1861 /* And make sure we never chase our dangling pointer from pci_dev */
1862 pci_set_drvdata(pdev
, NULL
);
1866 * i915_driver_load - setup chip and create an initial config
1868 * @ent: matching PCI ID entry
1870 * The driver load routine has to do several things:
1871 * - drive output discovery via intel_modeset_init()
1872 * - initialize the memory manager
1873 * - allocate initial config memory
1874 * - setup the DRM framebuffer with the allocated memory
1876 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1878 const struct intel_device_info
*match_info
=
1879 (struct intel_device_info
*)ent
->driver_data
;
1880 struct drm_i915_private
*dev_priv
;
1883 dev_priv
= i915_driver_create(pdev
, ent
);
1884 if (IS_ERR(dev_priv
))
1885 return PTR_ERR(dev_priv
);
1887 /* Disable nuclear pageflip by default on pre-ILK */
1888 if (!i915_modparams
.nuclear_pageflip
&& match_info
->gen
< 5)
1889 dev_priv
->drm
.driver_features
&= ~DRIVER_ATOMIC
;
1891 ret
= pci_enable_device(pdev
);
1895 ret
= i915_driver_init_early(dev_priv
);
1897 goto out_pci_disable
;
1899 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1901 ret
= i915_driver_init_mmio(dev_priv
);
1903 goto out_runtime_pm_put
;
1905 ret
= i915_driver_init_hw(dev_priv
);
1907 goto out_cleanup_mmio
;
1909 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1911 goto out_cleanup_hw
;
1913 i915_driver_register(dev_priv
);
1915 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1917 i915_welcome_messages(dev_priv
);
1922 i915_driver_cleanup_hw(dev_priv
);
1923 i915_ggtt_cleanup_hw(dev_priv
);
1925 i915_driver_cleanup_mmio(dev_priv
);
1927 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1928 i915_driver_cleanup_early(dev_priv
);
1930 pci_disable_device(pdev
);
1932 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1933 i915_driver_destroy(dev_priv
);
1937 void i915_driver_unload(struct drm_device
*dev
)
1939 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1940 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1942 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1944 i915_driver_unregister(dev_priv
);
1947 * After unregistering the device to prevent any new users, cancel
1948 * all in-flight requests so that we can quickly unbind the active
1951 i915_gem_set_wedged(dev_priv
);
1953 /* Flush any external code that still may be under the RCU lock */
1956 i915_gem_suspend(dev_priv
);
1958 drm_atomic_helper_shutdown(dev
);
1960 intel_gvt_cleanup(dev_priv
);
1962 intel_modeset_cleanup(dev
);
1964 intel_bios_cleanup(dev_priv
);
1966 vga_switcheroo_unregister_client(pdev
);
1967 vga_client_register(pdev
, NULL
, NULL
, NULL
);
1969 intel_csr_ucode_fini(dev_priv
);
1971 /* Free error state after interrupts are fully disabled. */
1972 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1973 i915_reset_error_state(dev_priv
);
1975 i915_gem_fini_hw(dev_priv
);
1977 intel_power_domains_fini_hw(dev_priv
);
1979 i915_driver_cleanup_hw(dev_priv
);
1981 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1984 static void i915_driver_release(struct drm_device
*dev
)
1986 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1987 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
1989 disable_rpm_wakeref_asserts(rpm
);
1991 i915_gem_fini(dev_priv
);
1993 i915_ggtt_cleanup_hw(dev_priv
);
1994 i915_driver_cleanup_mmio(dev_priv
);
1996 enable_rpm_wakeref_asserts(rpm
);
1997 intel_runtime_pm_cleanup(rpm
);
1999 i915_driver_cleanup_early(dev_priv
);
2000 i915_driver_destroy(dev_priv
);
2003 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
2005 struct drm_i915_private
*i915
= to_i915(dev
);
2008 ret
= i915_gem_open(i915
, file
);
2016 * i915_driver_lastclose - clean up after all DRM clients have exited
2019 * Take care of cleaning up after all DRM clients have exited. In the
2020 * mode setting case, we want to restore the kernel's initial mode (just
2021 * in case the last client left us in a bad state).
2023 * Additionally, in the non-mode setting case, we'll tear down the GTT
2024 * and DMA structures, since the kernel won't be using them, and clea
2027 static void i915_driver_lastclose(struct drm_device
*dev
)
2029 intel_fbdev_restore_mode(dev
);
2030 vga_switcheroo_process_delayed_switch();
2033 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
2035 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2037 mutex_lock(&dev
->struct_mutex
);
2038 i915_gem_context_close(file
);
2039 i915_gem_release(dev
, file
);
2040 mutex_unlock(&dev
->struct_mutex
);
2045 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
2047 struct drm_device
*dev
= &dev_priv
->drm
;
2048 struct intel_encoder
*encoder
;
2050 drm_modeset_lock_all(dev
);
2051 for_each_intel_encoder(dev
, encoder
)
2052 if (encoder
->suspend
)
2053 encoder
->suspend(encoder
);
2054 drm_modeset_unlock_all(dev
);
2057 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2059 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
2061 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
2063 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
2064 if (acpi_target_system_state() < ACPI_STATE_S3
)
2070 static int i915_drm_prepare(struct drm_device
*dev
)
2072 struct drm_i915_private
*i915
= to_i915(dev
);
2075 * NB intel_display_suspend() may issue new requests after we've
2076 * ostensibly marked the GPU as ready-to-sleep here. We need to
2077 * split out that work and pull it forward so that after point,
2078 * the GPU is not woken again.
2080 i915_gem_suspend(i915
);
2085 static int i915_drm_suspend(struct drm_device
*dev
)
2087 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2088 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2089 pci_power_t opregion_target_state
;
2091 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
2093 /* We do a lot of poking in a lot of registers, make sure they work
2095 intel_power_domains_disable(dev_priv
);
2097 drm_kms_helper_poll_disable(dev
);
2099 pci_save_state(pdev
);
2101 intel_display_suspend(dev
);
2103 intel_dp_mst_suspend(dev_priv
);
2105 intel_runtime_pm_disable_interrupts(dev_priv
);
2106 intel_hpd_cancel_work(dev_priv
);
2108 intel_suspend_encoders(dev_priv
);
2110 intel_suspend_hw(dev_priv
);
2112 i915_gem_suspend_gtt_mappings(dev_priv
);
2114 i915_save_state(dev_priv
);
2116 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
2117 intel_opregion_suspend(dev_priv
, opregion_target_state
);
2119 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
2121 dev_priv
->suspend_count
++;
2123 intel_csr_ucode_suspend(dev_priv
);
2125 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
2130 static enum i915_drm_suspend_mode
2131 get_suspend_mode(struct drm_i915_private
*dev_priv
, bool hibernate
)
2134 return I915_DRM_SUSPEND_HIBERNATE
;
2136 if (suspend_to_idle(dev_priv
))
2137 return I915_DRM_SUSPEND_IDLE
;
2139 return I915_DRM_SUSPEND_MEM
;
2142 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
2144 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2145 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2146 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
2149 disable_rpm_wakeref_asserts(rpm
);
2151 i915_gem_suspend_late(dev_priv
);
2153 intel_uncore_suspend(&dev_priv
->uncore
);
2155 intel_power_domains_suspend(dev_priv
,
2156 get_suspend_mode(dev_priv
, hibernation
));
2159 if (INTEL_GEN(dev_priv
) >= 11 || IS_GEN9_LP(dev_priv
))
2160 bxt_enable_dc9(dev_priv
);
2161 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2162 hsw_enable_pc8(dev_priv
);
2163 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2164 ret
= vlv_suspend_complete(dev_priv
);
2167 DRM_ERROR("Suspend complete failed: %d\n", ret
);
2168 intel_power_domains_resume(dev_priv
);
2173 pci_disable_device(pdev
);
2175 * During hibernation on some platforms the BIOS may try to access
2176 * the device even though it's already in D3 and hang the machine. So
2177 * leave the device in D0 on those platforms and hope the BIOS will
2178 * power down the device properly. The issue was seen on multiple old
2179 * GENs with different BIOS vendors, so having an explicit blacklist
2180 * is inpractical; apply the workaround on everything pre GEN6. The
2181 * platforms where the issue was seen:
2182 * Lenovo Thinkpad X301, X61s, X60, T60, X41
2186 if (!(hibernation
&& INTEL_GEN(dev_priv
) < 6))
2187 pci_set_power_state(pdev
, PCI_D3hot
);
2190 enable_rpm_wakeref_asserts(rpm
);
2191 if (!dev_priv
->uncore
.user_forcewake
.count
)
2192 intel_runtime_pm_cleanup(rpm
);
2197 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
2202 DRM_ERROR("dev: %p\n", dev
);
2203 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2207 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
2208 state
.event
!= PM_EVENT_FREEZE
))
2211 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2214 error
= i915_drm_suspend(dev
);
2218 return i915_drm_suspend_late(dev
, false);
2221 static int i915_drm_resume(struct drm_device
*dev
)
2223 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2226 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
2227 intel_sanitize_gt_powersave(dev_priv
);
2229 i915_gem_sanitize(dev_priv
);
2231 ret
= i915_ggtt_enable_hw(dev_priv
);
2233 DRM_ERROR("failed to re-enable GGTT\n");
2235 intel_csr_ucode_resume(dev_priv
);
2237 i915_restore_state(dev_priv
);
2238 intel_pps_unlock_regs_wa(dev_priv
);
2240 intel_init_pch_refclk(dev_priv
);
2243 * Interrupts have to be enabled before any batches are run. If not the
2244 * GPU will hang. i915_gem_init_hw() will initiate batches to
2245 * update/restore the context.
2247 * drm_mode_config_reset() needs AUX interrupts.
2249 * Modeset enabling in intel_modeset_init_hw() also needs working
2252 intel_runtime_pm_enable_interrupts(dev_priv
);
2254 drm_mode_config_reset(dev
);
2256 i915_gem_resume(dev_priv
);
2258 intel_modeset_init_hw(dev
);
2259 intel_init_clock_gating(dev_priv
);
2261 spin_lock_irq(&dev_priv
->irq_lock
);
2262 if (dev_priv
->display
.hpd_irq_setup
)
2263 dev_priv
->display
.hpd_irq_setup(dev_priv
);
2264 spin_unlock_irq(&dev_priv
->irq_lock
);
2266 intel_dp_mst_resume(dev_priv
);
2268 intel_display_resume(dev
);
2270 drm_kms_helper_poll_enable(dev
);
2273 * ... but also need to make sure that hotplug processing
2274 * doesn't cause havoc. Like in the driver load code we don't
2275 * bother with the tiny race here where we might lose hotplug
2278 intel_hpd_init(dev_priv
);
2280 intel_opregion_resume(dev_priv
);
2282 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
2284 intel_power_domains_enable(dev_priv
);
2286 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
2291 static int i915_drm_resume_early(struct drm_device
*dev
)
2293 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2294 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2298 * We have a resume ordering issue with the snd-hda driver also
2299 * requiring our device to be power up. Due to the lack of a
2300 * parent/child relationship we currently solve this with an early
2303 * FIXME: This should be solved with a special hdmi sink device or
2304 * similar so that power domains can be employed.
2308 * Note that we need to set the power state explicitly, since we
2309 * powered off the device during freeze and the PCI core won't power
2310 * it back up for us during thaw. Powering off the device during
2311 * freeze is not a hard requirement though, and during the
2312 * suspend/resume phases the PCI core makes sure we get here with the
2313 * device powered on. So in case we change our freeze logic and keep
2314 * the device powered we can also remove the following set power state
2317 ret
= pci_set_power_state(pdev
, PCI_D0
);
2319 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
2324 * Note that pci_enable_device() first enables any parent bridge
2325 * device and only then sets the power state for this device. The
2326 * bridge enabling is a nop though, since bridge devices are resumed
2327 * first. The order of enabling power and enabling the device is
2328 * imposed by the PCI core as described above, so here we preserve the
2329 * same order for the freeze/thaw phases.
2331 * TODO: eventually we should remove pci_disable_device() /
2332 * pci_enable_enable_device() from suspend/resume. Due to how they
2333 * depend on the device enable refcount we can't anyway depend on them
2334 * disabling/enabling the device.
2336 if (pci_enable_device(pdev
))
2339 pci_set_master(pdev
);
2341 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
2343 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2344 ret
= vlv_resume_prepare(dev_priv
, false);
2346 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2349 intel_uncore_resume_early(&dev_priv
->uncore
);
2351 i915_check_and_clear_faults(dev_priv
);
2353 if (INTEL_GEN(dev_priv
) >= 11 || IS_GEN9_LP(dev_priv
)) {
2354 gen9_sanitize_dc_state(dev_priv
);
2355 bxt_disable_dc9(dev_priv
);
2356 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2357 hsw_disable_pc8(dev_priv
);
2360 intel_uncore_sanitize(dev_priv
);
2362 intel_power_domains_resume(dev_priv
);
2364 intel_gt_sanitize(dev_priv
, true);
2366 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
2371 static int i915_resume_switcheroo(struct drm_device
*dev
)
2375 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2378 ret
= i915_drm_resume_early(dev
);
2382 return i915_drm_resume(dev
);
2385 static int i915_pm_prepare(struct device
*kdev
)
2387 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2388 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2391 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
2395 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2398 return i915_drm_prepare(dev
);
2401 static int i915_pm_suspend(struct device
*kdev
)
2403 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2404 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2407 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
2411 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2414 return i915_drm_suspend(dev
);
2417 static int i915_pm_suspend_late(struct device
*kdev
)
2419 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2422 * We have a suspend ordering issue with the snd-hda driver also
2423 * requiring our device to be power up. Due to the lack of a
2424 * parent/child relationship we currently solve this with an late
2427 * FIXME: This should be solved with a special hdmi sink device or
2428 * similar so that power domains can be employed.
2430 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2433 return i915_drm_suspend_late(dev
, false);
2436 static int i915_pm_poweroff_late(struct device
*kdev
)
2438 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2440 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2443 return i915_drm_suspend_late(dev
, true);
2446 static int i915_pm_resume_early(struct device
*kdev
)
2448 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2450 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2453 return i915_drm_resume_early(dev
);
2456 static int i915_pm_resume(struct device
*kdev
)
2458 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2460 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2463 return i915_drm_resume(dev
);
2466 /* freeze: before creating the hibernation_image */
2467 static int i915_pm_freeze(struct device
*kdev
)
2469 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2472 if (dev
->switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
2473 ret
= i915_drm_suspend(dev
);
2478 ret
= i915_gem_freeze(kdev_to_i915(kdev
));
2485 static int i915_pm_freeze_late(struct device
*kdev
)
2487 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2490 if (dev
->switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
2491 ret
= i915_drm_suspend_late(dev
, true);
2496 ret
= i915_gem_freeze_late(kdev_to_i915(kdev
));
2503 /* thaw: called after creating the hibernation image, but before turning off. */
2504 static int i915_pm_thaw_early(struct device
*kdev
)
2506 return i915_pm_resume_early(kdev
);
2509 static int i915_pm_thaw(struct device
*kdev
)
2511 return i915_pm_resume(kdev
);
2514 /* restore: called after loading the hibernation image. */
2515 static int i915_pm_restore_early(struct device
*kdev
)
2517 return i915_pm_resume_early(kdev
);
2520 static int i915_pm_restore(struct device
*kdev
)
2522 return i915_pm_resume(kdev
);
2526 * Save all Gunit registers that may be lost after a D3 and a subsequent
2527 * S0i[R123] transition. The list of registers needing a save/restore is
2528 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2529 * registers in the following way:
2530 * - Driver: saved/restored by the driver
2531 * - Punit : saved/restored by the Punit firmware
2532 * - No, w/o marking: no need to save/restore, since the register is R/O or
2533 * used internally by the HW in a way that doesn't depend
2534 * keeping the content across a suspend/resume.
2535 * - Debug : used for debugging
2537 * We save/restore all registers marked with 'Driver', with the following
2539 * - Registers out of use, including also registers marked with 'Debug'.
2540 * These have no effect on the driver's operation, so we don't save/restore
2541 * them to reduce the overhead.
2542 * - Registers that are fully setup by an initialization function called from
2543 * the resume path. For example many clock gating and RPS/RC6 registers.
2544 * - Registers that provide the right functionality with their reset defaults.
2546 * TODO: Except for registers that based on the above 3 criteria can be safely
2547 * ignored, we save/restore all others, practically treating the HW context as
2548 * a black-box for the driver. Further investigation is needed to reduce the
2549 * saved/restored registers even further, by following the same 3 criteria.
2551 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2553 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2556 /* GAM 0x4000-0x4770 */
2557 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
2558 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
2559 s
->arb_mode
= I915_READ(ARB_MODE
);
2560 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
2561 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
2563 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2564 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
2566 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
2567 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
2569 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
2570 s
->ecochk
= I915_READ(GAM_ECOCHK
);
2571 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
2572 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
2574 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
2576 /* MBC 0x9024-0x91D0, 0x8500 */
2577 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
2578 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
2579 s
->mbctl
= I915_READ(GEN6_MBCTL
);
2581 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2582 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2583 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2584 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2585 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2586 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2587 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2589 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2590 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2591 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2592 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2593 s
->ecobus
= I915_READ(ECOBUS
);
2594 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2595 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2596 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2597 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2598 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2599 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2601 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2602 s
->gt_imr
= I915_READ(GTIMR
);
2603 s
->gt_ier
= I915_READ(GTIER
);
2604 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2605 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2607 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2608 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2610 /* GT SA CZ domain, 0x100000-0x138124 */
2611 s
->tilectl
= I915_READ(TILECTL
);
2612 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2613 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2614 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2615 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2617 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2618 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2619 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2620 s
->pcbr
= I915_READ(VLV_PCBR
);
2621 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2624 * Not saving any of:
2625 * DFT, 0x9800-0x9EC0
2626 * SARB, 0xB000-0xB1FC
2627 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2632 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2634 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2638 /* GAM 0x4000-0x4770 */
2639 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2640 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2641 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2642 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2643 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2645 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2646 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2648 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2649 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2651 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2652 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2653 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2654 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2656 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2658 /* MBC 0x9024-0x91D0, 0x8500 */
2659 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2660 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2661 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2663 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2664 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2665 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2666 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2667 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2668 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2669 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2671 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2672 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2673 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2674 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2675 I915_WRITE(ECOBUS
, s
->ecobus
);
2676 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2677 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2678 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2679 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2680 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2681 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2683 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2684 I915_WRITE(GTIMR
, s
->gt_imr
);
2685 I915_WRITE(GTIER
, s
->gt_ier
);
2686 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2687 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2689 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2690 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2692 /* GT SA CZ domain, 0x100000-0x138124 */
2693 I915_WRITE(TILECTL
, s
->tilectl
);
2694 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2696 * Preserve the GT allow wake and GFX force clock bit, they are not
2697 * be restored, as they are used to control the s0ix suspend/resume
2698 * sequence by the caller.
2700 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2701 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2702 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2703 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2705 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2706 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2707 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2708 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2710 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2712 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2713 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2714 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2715 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2716 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2719 static int vlv_wait_for_pw_status(struct drm_i915_private
*i915
,
2722 i915_reg_t reg
= VLV_GTLC_PW_STATUS
;
2726 /* The HW does not like us polling for PW_STATUS frequently, so
2727 * use the sleeping loop rather than risk the busy spin within
2728 * intel_wait_for_register().
2730 * Transitioning between RC6 states should be at most 2ms (see
2731 * valleyview_enable_rps) so use a 3ms timeout.
2733 ret
= wait_for(((reg_value
=
2734 intel_uncore_read_notrace(&i915
->uncore
, reg
)) & mask
)
2737 /* just trace the final value */
2738 trace_i915_reg_rw(false, reg
, reg_value
, sizeof(reg_value
), true);
2743 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2748 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2749 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2751 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2752 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2757 err
= intel_wait_for_register(&dev_priv
->uncore
,
2758 VLV_GTLC_SURVIVABILITY_REG
,
2759 VLV_GFX_CLK_STATUS_BIT
,
2760 VLV_GFX_CLK_STATUS_BIT
,
2763 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2764 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2769 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2775 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2776 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2778 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2779 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2780 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2782 mask
= VLV_GTLC_ALLOWWAKEACK
;
2783 val
= allow
? mask
: 0;
2785 err
= vlv_wait_for_pw_status(dev_priv
, mask
, val
);
2787 DRM_ERROR("timeout disabling GT waking\n");
2792 static void vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2798 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2799 val
= wait_for_on
? mask
: 0;
2802 * RC6 transitioning can be delayed up to 2 msec (see
2803 * valleyview_enable_rps), use 3 msec for safety.
2805 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2806 * reset and we are trying to force the machine to sleep.
2808 if (vlv_wait_for_pw_status(dev_priv
, mask
, val
))
2809 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2810 onoff(wait_for_on
));
2813 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2815 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2818 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2819 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2822 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2828 * Bspec defines the following GT well on flags as debug only, so
2829 * don't treat them as hard failures.
2831 vlv_wait_for_gt_wells(dev_priv
, false);
2833 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2834 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2836 vlv_check_no_gt_access(dev_priv
);
2838 err
= vlv_force_gfx_clock(dev_priv
, true);
2842 err
= vlv_allow_gt_wake(dev_priv
, false);
2846 if (!IS_CHERRYVIEW(dev_priv
))
2847 vlv_save_gunit_s0ix_state(dev_priv
);
2849 err
= vlv_force_gfx_clock(dev_priv
, false);
2856 /* For safety always re-enable waking and disable gfx clock forcing */
2857 vlv_allow_gt_wake(dev_priv
, true);
2859 vlv_force_gfx_clock(dev_priv
, false);
2864 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2871 * If any of the steps fail just try to continue, that's the best we
2872 * can do at this point. Return the first error code (which will also
2873 * leave RPM permanently disabled).
2875 ret
= vlv_force_gfx_clock(dev_priv
, true);
2877 if (!IS_CHERRYVIEW(dev_priv
))
2878 vlv_restore_gunit_s0ix_state(dev_priv
);
2880 err
= vlv_allow_gt_wake(dev_priv
, true);
2884 err
= vlv_force_gfx_clock(dev_priv
, false);
2888 vlv_check_no_gt_access(dev_priv
);
2891 intel_init_clock_gating(dev_priv
);
2896 static int intel_runtime_suspend(struct device
*kdev
)
2898 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2899 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2900 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2901 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
2904 if (WARN_ON_ONCE(!(dev_priv
->gt_pm
.rc6
.enabled
&& HAS_RC6(dev_priv
))))
2907 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2910 DRM_DEBUG_KMS("Suspending device\n");
2912 disable_rpm_wakeref_asserts(rpm
);
2915 * We are safe here against re-faults, since the fault handler takes
2918 i915_gem_runtime_suspend(dev_priv
);
2920 intel_uc_runtime_suspend(dev_priv
);
2922 intel_runtime_pm_disable_interrupts(dev_priv
);
2924 intel_uncore_suspend(&dev_priv
->uncore
);
2927 if (INTEL_GEN(dev_priv
) >= 11) {
2928 icl_display_core_uninit(dev_priv
);
2929 bxt_enable_dc9(dev_priv
);
2930 } else if (IS_GEN9_LP(dev_priv
)) {
2931 bxt_display_core_uninit(dev_priv
);
2932 bxt_enable_dc9(dev_priv
);
2933 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2934 hsw_enable_pc8(dev_priv
);
2935 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2936 ret
= vlv_suspend_complete(dev_priv
);
2940 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2941 intel_uncore_runtime_resume(&dev_priv
->uncore
);
2943 intel_runtime_pm_enable_interrupts(dev_priv
);
2945 intel_uc_resume(dev_priv
);
2947 i915_gem_init_swizzling(dev_priv
);
2948 i915_gem_restore_fences(dev_priv
);
2950 enable_rpm_wakeref_asserts(rpm
);
2955 enable_rpm_wakeref_asserts(rpm
);
2956 intel_runtime_pm_cleanup(rpm
);
2958 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
))
2959 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2961 rpm
->suspended
= true;
2964 * FIXME: We really should find a document that references the arguments
2967 if (IS_BROADWELL(dev_priv
)) {
2969 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2970 * being detected, and the call we do at intel_runtime_resume()
2971 * won't be able to restore them. Since PCI_D3hot matches the
2972 * actual specification and appears to be working, use it.
2974 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2977 * current versions of firmware which depend on this opregion
2978 * notification have repurposed the D1 definition to mean
2979 * "runtime suspended" vs. what you would normally expect (D3)
2980 * to distinguish it from notifications that might be sent via
2983 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2986 assert_forcewakes_inactive(&dev_priv
->uncore
);
2988 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2989 intel_hpd_poll_init(dev_priv
);
2991 DRM_DEBUG_KMS("Device suspended\n");
2995 static int intel_runtime_resume(struct device
*kdev
)
2997 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2998 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2999 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3000 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
3003 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
3006 DRM_DEBUG_KMS("Resuming device\n");
3008 WARN_ON_ONCE(atomic_read(&rpm
->wakeref_count
));
3009 disable_rpm_wakeref_asserts(rpm
);
3011 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
3012 rpm
->suspended
= false;
3013 if (intel_uncore_unclaimed_mmio(&dev_priv
->uncore
))
3014 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
3016 if (INTEL_GEN(dev_priv
) >= 11) {
3017 bxt_disable_dc9(dev_priv
);
3018 icl_display_core_init(dev_priv
, true);
3019 if (dev_priv
->csr
.dmc_payload
) {
3020 if (dev_priv
->csr
.allowed_dc_mask
&
3021 DC_STATE_EN_UPTO_DC6
)
3022 skl_enable_dc6(dev_priv
);
3023 else if (dev_priv
->csr
.allowed_dc_mask
&
3024 DC_STATE_EN_UPTO_DC5
)
3025 gen9_enable_dc5(dev_priv
);
3027 } else if (IS_GEN9_LP(dev_priv
)) {
3028 bxt_disable_dc9(dev_priv
);
3029 bxt_display_core_init(dev_priv
, true);
3030 if (dev_priv
->csr
.dmc_payload
&&
3031 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
3032 gen9_enable_dc5(dev_priv
);
3033 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
3034 hsw_disable_pc8(dev_priv
);
3035 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3036 ret
= vlv_resume_prepare(dev_priv
, true);
3039 intel_uncore_runtime_resume(&dev_priv
->uncore
);
3041 intel_runtime_pm_enable_interrupts(dev_priv
);
3043 intel_uc_resume(dev_priv
);
3046 * No point of rolling back things in case of an error, as the best
3047 * we can do is to hope that things will still work (and disable RPM).
3049 i915_gem_init_swizzling(dev_priv
);
3050 i915_gem_restore_fences(dev_priv
);
3053 * On VLV/CHV display interrupts are part of the display
3054 * power well, so hpd is reinitialized from there. For
3055 * everyone else do it here.
3057 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
3058 intel_hpd_init(dev_priv
);
3060 intel_enable_ipc(dev_priv
);
3062 enable_rpm_wakeref_asserts(rpm
);
3065 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
3067 DRM_DEBUG_KMS("Device resumed\n");
3072 const struct dev_pm_ops i915_pm_ops
= {
3074 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3077 .prepare
= i915_pm_prepare
,
3078 .suspend
= i915_pm_suspend
,
3079 .suspend_late
= i915_pm_suspend_late
,
3080 .resume_early
= i915_pm_resume_early
,
3081 .resume
= i915_pm_resume
,
3085 * @freeze, @freeze_late : called (1) before creating the
3086 * hibernation image [PMSG_FREEZE] and
3087 * (2) after rebooting, before restoring
3088 * the image [PMSG_QUIESCE]
3089 * @thaw, @thaw_early : called (1) after creating the hibernation
3090 * image, before writing it [PMSG_THAW]
3091 * and (2) after failing to create or
3092 * restore the image [PMSG_RECOVER]
3093 * @poweroff, @poweroff_late: called after writing the hibernation
3094 * image, before rebooting [PMSG_HIBERNATE]
3095 * @restore, @restore_early : called after rebooting and restoring the
3096 * hibernation image [PMSG_RESTORE]
3098 .freeze
= i915_pm_freeze
,
3099 .freeze_late
= i915_pm_freeze_late
,
3100 .thaw_early
= i915_pm_thaw_early
,
3101 .thaw
= i915_pm_thaw
,
3102 .poweroff
= i915_pm_suspend
,
3103 .poweroff_late
= i915_pm_poweroff_late
,
3104 .restore_early
= i915_pm_restore_early
,
3105 .restore
= i915_pm_restore
,
3107 /* S0ix (via runtime suspend) event handlers */
3108 .runtime_suspend
= intel_runtime_suspend
,
3109 .runtime_resume
= intel_runtime_resume
,
3112 static const struct vm_operations_struct i915_gem_vm_ops
= {
3113 .fault
= i915_gem_fault
,
3114 .open
= drm_gem_vm_open
,
3115 .close
= drm_gem_vm_close
,
3118 static const struct file_operations i915_driver_fops
= {
3119 .owner
= THIS_MODULE
,
3121 .release
= drm_release
,
3122 .unlocked_ioctl
= drm_ioctl
,
3123 .mmap
= drm_gem_mmap
,
3126 .compat_ioctl
= i915_compat_ioctl
,
3127 .llseek
= noop_llseek
,
3131 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
3132 struct drm_file
*file
)
3137 static const struct drm_ioctl_desc i915_ioctls
[] = {
3138 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3139 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
3140 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
3141 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
3142 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
3143 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
3144 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam_ioctl
, DRM_RENDER_ALLOW
),
3145 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3146 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
3147 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
3148 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3149 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
3150 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3151 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3152 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
3153 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
3154 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3155 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3156 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer_ioctl
, DRM_AUTH
),
3157 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR
, i915_gem_execbuffer2_ioctl
, DRM_RENDER_ALLOW
),
3158 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
3159 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
3160 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_RENDER_ALLOW
),
3161 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
3162 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
3163 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_RENDER_ALLOW
),
3164 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3165 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
3166 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
3167 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
3168 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
3169 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
3170 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
3171 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
3172 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
3173 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
3174 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
3175 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
3176 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id_ioctl
, 0),
3177 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
3178 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
),
3179 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
),
3180 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey_ioctl
, DRM_MASTER
),
3181 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
),
3182 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_RENDER_ALLOW
),
3183 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
3184 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
3185 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
3186 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
3187 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
3188 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
3189 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
3190 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
3191 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG
, i915_perf_add_config_ioctl
, DRM_RENDER_ALLOW
),
3192 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG
, i915_perf_remove_config_ioctl
, DRM_RENDER_ALLOW
),
3193 DRM_IOCTL_DEF_DRV(I915_QUERY
, i915_query_ioctl
, DRM_RENDER_ALLOW
),
3194 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE
, i915_gem_vm_create_ioctl
, DRM_RENDER_ALLOW
),
3195 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY
, i915_gem_vm_destroy_ioctl
, DRM_RENDER_ALLOW
),
3198 static struct drm_driver driver
= {
3199 /* Don't use MTRRs here; the Xserver or userspace app should
3200 * deal with them for Intel hardware.
3204 DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_ATOMIC
| DRIVER_SYNCOBJ
,
3205 .release
= i915_driver_release
,
3206 .open
= i915_driver_open
,
3207 .lastclose
= i915_driver_lastclose
,
3208 .postclose
= i915_driver_postclose
,
3210 .gem_close_object
= i915_gem_close_object
,
3211 .gem_free_object_unlocked
= i915_gem_free_object
,
3212 .gem_vm_ops
= &i915_gem_vm_ops
,
3214 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
3215 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
3216 .gem_prime_export
= i915_gem_prime_export
,
3217 .gem_prime_import
= i915_gem_prime_import
,
3219 .dumb_create
= i915_gem_dumb_create
,
3220 .dumb_map_offset
= i915_gem_mmap_gtt
,
3221 .ioctls
= i915_ioctls
,
3222 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
3223 .fops
= &i915_driver_fops
,
3224 .name
= DRIVER_NAME
,
3225 .desc
= DRIVER_DESC
,
3226 .date
= DRIVER_DATE
,
3227 .major
= DRIVER_MAJOR
,
3228 .minor
= DRIVER_MINOR
,
3229 .patchlevel
= DRIVER_PATCHLEVEL
,
3232 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3233 #include "selftests/mock_drm.c"