1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
55 static struct drm_driver driver
;
57 static unsigned int i915_load_fail_count
;
59 bool __i915_inject_load_failure(const char *func
, int line
)
61 if (i915_load_fail_count
>= i915
.inject_load_failure
)
64 if (++i915_load_fail_count
== i915
.inject_load_failure
) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915
.inject_load_failure
, func
, line
);
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
78 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
81 static bool shown_bug_once
;
82 struct device
*kdev
= dev_priv
->drm
.dev
;
83 bool is_error
= level
[1] <= KERN_ERR
[1];
84 bool is_debug
= level
[1] == KERN_DEBUG
[1];
88 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
96 dev_printk(level
, kdev
, "[" DRM_NAME
":%ps] %pV",
97 __builtin_return_address(0), &vaf
);
99 if (is_error
&& !shown_bug_once
) {
100 dev_notice(kdev
, "%s", FDO_BUG_MSG
);
101 shown_bug_once
= true;
107 static bool i915_error_injected(struct drm_i915_private
*dev_priv
)
109 return i915
.inject_load_failure
&&
110 i915_load_fail_count
== i915
.inject_load_failure
;
113 #define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
119 static enum intel_pch
intel_virt_detect_pch(struct drm_i915_private
*dev_priv
)
121 enum intel_pch ret
= PCH_NOP
;
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
130 if (IS_GEN5(dev_priv
)) {
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133 } else if (IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
)) {
135 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
136 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
138 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
139 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
141 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
147 static void intel_detect_pch(struct drm_i915_private
*dev_priv
)
149 struct pci_dev
*pch
= NULL
;
151 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
152 * (which really amounts to a PCH but no South Display).
154 if (INTEL_INFO(dev_priv
)->num_pipes
== 0) {
155 dev_priv
->pch_type
= PCH_NOP
;
160 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
161 * make graphics device passthrough work easy for VMM, that only
162 * need to expose ISA bridge to let driver know the real hardware
163 * underneath. This is a requirement from virtualization team.
165 * In some virtualized environments (e.g. XEN), there is irrelevant
166 * ISA bridge in the system. To work reliably, we should scan trhough
167 * all the ISA bridge devices and check for the first match, instead
168 * of only checking the first one.
170 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
171 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
172 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
173 dev_priv
->pch_id
= id
;
175 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
176 dev_priv
->pch_type
= PCH_IBX
;
177 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
178 WARN_ON(!IS_GEN5(dev_priv
));
179 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
180 dev_priv
->pch_type
= PCH_CPT
;
181 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
182 WARN_ON(!(IS_GEN6(dev_priv
) ||
183 IS_IVYBRIDGE(dev_priv
)));
184 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
185 /* PantherPoint is CPT compatible */
186 dev_priv
->pch_type
= PCH_CPT
;
187 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
188 WARN_ON(!(IS_GEN6(dev_priv
) ||
189 IS_IVYBRIDGE(dev_priv
)));
190 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
191 dev_priv
->pch_type
= PCH_LPT
;
192 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
193 WARN_ON(!IS_HASWELL(dev_priv
) &&
194 !IS_BROADWELL(dev_priv
));
195 WARN_ON(IS_HSW_ULT(dev_priv
) ||
196 IS_BDW_ULT(dev_priv
));
197 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
198 dev_priv
->pch_type
= PCH_LPT
;
199 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
200 WARN_ON(!IS_HASWELL(dev_priv
) &&
201 !IS_BROADWELL(dev_priv
));
202 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
203 !IS_BDW_ULT(dev_priv
));
204 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
205 dev_priv
->pch_type
= PCH_SPT
;
206 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
207 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
208 !IS_KABYLAKE(dev_priv
));
209 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
210 dev_priv
->pch_type
= PCH_SPT
;
211 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
212 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
213 !IS_KABYLAKE(dev_priv
));
214 } else if (id
== INTEL_PCH_KBP_DEVICE_ID_TYPE
) {
215 dev_priv
->pch_type
= PCH_KBP
;
216 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
217 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
218 !IS_KABYLAKE(dev_priv
));
219 } else if ((id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
) ||
220 (id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
) ||
221 ((id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
) &&
222 pch
->subsystem_vendor
==
223 PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
224 pch
->subsystem_device
==
225 PCI_SUBDEVICE_ID_QEMU
)) {
227 intel_virt_detect_pch(dev_priv
);
235 DRM_DEBUG_KMS("No PCH found.\n");
240 static int i915_getparam(struct drm_device
*dev
, void *data
,
241 struct drm_file
*file_priv
)
243 struct drm_i915_private
*dev_priv
= to_i915(dev
);
244 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
245 drm_i915_getparam_t
*param
= data
;
248 switch (param
->param
) {
249 case I915_PARAM_IRQ_ACTIVE
:
250 case I915_PARAM_ALLOW_BATCHBUFFER
:
251 case I915_PARAM_LAST_DISPATCH
:
252 case I915_PARAM_HAS_EXEC_CONSTANTS
:
253 /* Reject all old ums/dri params. */
255 case I915_PARAM_CHIPSET_ID
:
256 value
= pdev
->device
;
258 case I915_PARAM_REVISION
:
259 value
= pdev
->revision
;
261 case I915_PARAM_NUM_FENCES_AVAIL
:
262 value
= dev_priv
->num_fence_regs
;
264 case I915_PARAM_HAS_OVERLAY
:
265 value
= dev_priv
->overlay
? 1 : 0;
267 case I915_PARAM_HAS_BSD
:
268 value
= !!dev_priv
->engine
[VCS
];
270 case I915_PARAM_HAS_BLT
:
271 value
= !!dev_priv
->engine
[BCS
];
273 case I915_PARAM_HAS_VEBOX
:
274 value
= !!dev_priv
->engine
[VECS
];
276 case I915_PARAM_HAS_BSD2
:
277 value
= !!dev_priv
->engine
[VCS2
];
279 case I915_PARAM_HAS_LLC
:
280 value
= HAS_LLC(dev_priv
);
282 case I915_PARAM_HAS_WT
:
283 value
= HAS_WT(dev_priv
);
285 case I915_PARAM_HAS_ALIASING_PPGTT
:
286 value
= USES_PPGTT(dev_priv
);
288 case I915_PARAM_HAS_SEMAPHORES
:
289 value
= i915
.semaphores
;
291 case I915_PARAM_HAS_SECURE_BATCHES
:
292 value
= capable(CAP_SYS_ADMIN
);
294 case I915_PARAM_CMD_PARSER_VERSION
:
295 value
= i915_cmd_parser_get_version(dev_priv
);
297 case I915_PARAM_SUBSLICE_TOTAL
:
298 value
= sseu_subslice_total(&INTEL_INFO(dev_priv
)->sseu
);
302 case I915_PARAM_EU_TOTAL
:
303 value
= INTEL_INFO(dev_priv
)->sseu
.eu_total
;
307 case I915_PARAM_HAS_GPU_RESET
:
308 value
= i915
.enable_hangcheck
&& intel_has_gpu_reset(dev_priv
);
310 case I915_PARAM_HAS_RESOURCE_STREAMER
:
311 value
= HAS_RESOURCE_STREAMER(dev_priv
);
313 case I915_PARAM_HAS_POOLED_EU
:
314 value
= HAS_POOLED_EU(dev_priv
);
316 case I915_PARAM_MIN_EU_IN_POOL
:
317 value
= INTEL_INFO(dev_priv
)->sseu
.min_eu_in_pool
;
319 case I915_PARAM_HUC_STATUS
:
320 intel_runtime_pm_get(dev_priv
);
321 value
= I915_READ(HUC_STATUS2
) & HUC_FW_VERIFIED
;
322 intel_runtime_pm_put(dev_priv
);
324 case I915_PARAM_MMAP_GTT_VERSION
:
325 /* Though we've started our numbering from 1, and so class all
326 * earlier versions as 0, in effect their value is undefined as
327 * the ioctl will report EINVAL for the unknown param!
329 value
= i915_gem_mmap_gtt_version();
331 case I915_PARAM_HAS_SCHEDULER
:
332 value
= dev_priv
->engine
[RCS
] &&
333 dev_priv
->engine
[RCS
]->schedule
;
335 case I915_PARAM_MMAP_VERSION
:
336 /* Remember to bump this if the version changes! */
337 case I915_PARAM_HAS_GEM
:
338 case I915_PARAM_HAS_PAGEFLIPPING
:
339 case I915_PARAM_HAS_EXECBUF2
: /* depends on GEM */
340 case I915_PARAM_HAS_RELAXED_FENCING
:
341 case I915_PARAM_HAS_COHERENT_RINGS
:
342 case I915_PARAM_HAS_RELAXED_DELTA
:
343 case I915_PARAM_HAS_GEN7_SOL_RESET
:
344 case I915_PARAM_HAS_WAIT_TIMEOUT
:
345 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
346 case I915_PARAM_HAS_PINNED_BATCHES
:
347 case I915_PARAM_HAS_EXEC_NO_RELOC
:
348 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
349 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
350 case I915_PARAM_HAS_EXEC_SOFTPIN
:
351 case I915_PARAM_HAS_EXEC_ASYNC
:
352 case I915_PARAM_HAS_EXEC_FENCE
:
353 case I915_PARAM_HAS_EXEC_CAPTURE
:
354 /* For the time being all of these are always true;
355 * if some supported hardware does not have one of these
356 * features this value needs to be provided from
357 * INTEL_INFO(), a feature macro, or similar.
362 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
366 if (put_user(value
, param
->value
))
372 static int i915_get_bridge_dev(struct drm_i915_private
*dev_priv
)
374 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
375 if (!dev_priv
->bridge_dev
) {
376 DRM_ERROR("bridge device not found\n");
382 /* Allocate space for the MCH regs if needed, return nonzero on error */
384 intel_alloc_mchbar_resource(struct drm_i915_private
*dev_priv
)
386 int reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
387 u32 temp_lo
, temp_hi
= 0;
391 if (INTEL_GEN(dev_priv
) >= 4)
392 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
393 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
394 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
396 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
399 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
403 /* Get some space for it */
404 dev_priv
->mch_res
.name
= "i915 MCHBAR";
405 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
406 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
408 MCHBAR_SIZE
, MCHBAR_SIZE
,
410 0, pcibios_align_resource
,
411 dev_priv
->bridge_dev
);
413 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
414 dev_priv
->mch_res
.start
= 0;
418 if (INTEL_GEN(dev_priv
) >= 4)
419 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
420 upper_32_bits(dev_priv
->mch_res
.start
));
422 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
423 lower_32_bits(dev_priv
->mch_res
.start
));
427 /* Setup MCHBAR if possible, return true if we should disable it again */
429 intel_setup_mchbar(struct drm_i915_private
*dev_priv
)
431 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
435 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
438 dev_priv
->mchbar_need_disable
= false;
440 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
441 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
442 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
444 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
448 /* If it's already enabled, don't have to do anything */
452 if (intel_alloc_mchbar_resource(dev_priv
))
455 dev_priv
->mchbar_need_disable
= true;
457 /* Space is allocated or reserved, so enable it. */
458 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
459 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
460 temp
| DEVEN_MCHBAR_EN
);
462 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
463 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
468 intel_teardown_mchbar(struct drm_i915_private
*dev_priv
)
470 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
472 if (dev_priv
->mchbar_need_disable
) {
473 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
476 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
478 deven_val
&= ~DEVEN_MCHBAR_EN
;
479 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
484 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
487 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
492 if (dev_priv
->mch_res
.start
)
493 release_resource(&dev_priv
->mch_res
);
496 /* true = enable decode, false = disable decoder */
497 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
499 struct drm_i915_private
*dev_priv
= cookie
;
501 intel_modeset_vga_set_state(dev_priv
, state
);
503 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
504 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
506 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
509 static int i915_resume_switcheroo(struct drm_device
*dev
);
510 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
512 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
514 struct drm_device
*dev
= pci_get_drvdata(pdev
);
515 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
517 if (state
== VGA_SWITCHEROO_ON
) {
518 pr_info("switched on\n");
519 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
520 /* i915 resume handler doesn't set to D0 */
521 pci_set_power_state(pdev
, PCI_D0
);
522 i915_resume_switcheroo(dev
);
523 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
525 pr_info("switched off\n");
526 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
527 i915_suspend_switcheroo(dev
, pmm
);
528 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
532 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
534 struct drm_device
*dev
= pci_get_drvdata(pdev
);
537 * FIXME: open_count is protected by drm_global_mutex but that would lead to
538 * locking inversion with the driver load path. And the access here is
539 * completely racy anyway. So don't bother with locking for now.
541 return dev
->open_count
== 0;
544 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
545 .set_gpu_state
= i915_switcheroo_set_state
,
547 .can_switch
= i915_switcheroo_can_switch
,
550 static void i915_gem_fini(struct drm_i915_private
*dev_priv
)
552 mutex_lock(&dev_priv
->drm
.struct_mutex
);
553 intel_uc_fini_hw(dev_priv
);
554 i915_gem_cleanup_engines(dev_priv
);
555 i915_gem_context_fini(dev_priv
);
556 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
558 i915_gem_drain_freed_objects(dev_priv
);
560 WARN_ON(!list_empty(&dev_priv
->context_list
));
563 static int i915_load_modeset_init(struct drm_device
*dev
)
565 struct drm_i915_private
*dev_priv
= to_i915(dev
);
566 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
569 if (i915_inject_load_failure())
572 intel_bios_init(dev_priv
);
574 /* If we have > 1 VGA cards, then we need to arbitrate access
575 * to the common VGA resources.
577 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
578 * then we do not take part in VGA arbitration and the
579 * vga_client_register() fails with -ENODEV.
581 ret
= vga_client_register(pdev
, dev_priv
, NULL
, i915_vga_set_decode
);
582 if (ret
&& ret
!= -ENODEV
)
585 intel_register_dsm_handler();
587 ret
= vga_switcheroo_register_client(pdev
, &i915_switcheroo_ops
, false);
589 goto cleanup_vga_client
;
591 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
592 intel_update_rawclk(dev_priv
);
594 intel_power_domains_init_hw(dev_priv
, false);
596 intel_csr_ucode_init(dev_priv
);
598 ret
= intel_irq_install(dev_priv
);
602 intel_setup_gmbus(dev_priv
);
604 /* Important: The output setup functions called by modeset_init need
605 * working irqs for e.g. gmbus and dp aux transfers. */
606 ret
= intel_modeset_init(dev
);
610 intel_uc_init_fw(dev_priv
);
612 ret
= i915_gem_init(dev_priv
);
616 intel_modeset_gem_init(dev
);
618 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
621 ret
= intel_fbdev_init(dev
);
625 /* Only enable hotplug handling once the fbdev is fully set up. */
626 intel_hpd_init(dev_priv
);
628 drm_kms_helper_poll_init(dev
);
633 if (i915_gem_suspend(dev_priv
))
634 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
635 i915_gem_fini(dev_priv
);
637 intel_uc_fini_fw(dev_priv
);
639 drm_irq_uninstall(dev
);
640 intel_teardown_gmbus(dev_priv
);
642 intel_csr_ucode_fini(dev_priv
);
643 intel_power_domains_fini(dev_priv
);
644 vga_switcheroo_unregister_client(pdev
);
646 vga_client_register(pdev
, NULL
, NULL
, NULL
);
651 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
653 struct apertures_struct
*ap
;
654 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
655 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
659 ap
= alloc_apertures(1);
663 ap
->ranges
[0].base
= ggtt
->mappable_base
;
664 ap
->ranges
[0].size
= ggtt
->mappable_end
;
667 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
669 ret
= drm_fb_helper_remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
676 #if !defined(CONFIG_VGA_CONSOLE)
677 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
681 #elif !defined(CONFIG_DUMMY_CONSOLE)
682 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
687 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
691 DRM_INFO("Replacing VGA console driver\n");
694 if (con_is_bound(&vga_con
))
695 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
697 ret
= do_unregister_con_driver(&vga_con
);
699 /* Ignore "already unregistered". */
709 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
712 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
713 * CHV x1 PHY (DP/HDMI D)
714 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
716 if (IS_CHERRYVIEW(dev_priv
)) {
717 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
718 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
719 } else if (IS_VALLEYVIEW(dev_priv
)) {
720 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
724 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
727 * The i915 workqueue is primarily used for batched retirement of
728 * requests (and thus managing bo) once the task has been completed
729 * by the GPU. i915_gem_retire_requests() is called directly when we
730 * need high-priority retirement, such as waiting for an explicit
733 * It is also used for periodic low-priority events, such as
734 * idle-timers and recording error state.
736 * All tasks on the workqueue are expected to acquire the dev mutex
737 * so there is no point in running more than one instance of the
738 * workqueue at any time. Use an ordered one.
740 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
741 if (dev_priv
->wq
== NULL
)
744 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
745 if (dev_priv
->hotplug
.dp_wq
== NULL
)
751 destroy_workqueue(dev_priv
->wq
);
753 DRM_ERROR("Failed to allocate workqueues.\n");
758 static void i915_engines_cleanup(struct drm_i915_private
*i915
)
760 struct intel_engine_cs
*engine
;
761 enum intel_engine_id id
;
763 for_each_engine(engine
, i915
, id
)
767 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
769 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
770 destroy_workqueue(dev_priv
->wq
);
774 * We don't keep the workarounds for pre-production hardware, so we expect our
775 * driver to fail on these machines in one way or another. A little warning on
776 * dmesg may help both the user and the bug triagers.
778 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
782 pre
|= IS_HSW_EARLY_SDV(dev_priv
);
783 pre
|= IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
);
784 pre
|= IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B_LAST
);
787 DRM_ERROR("This is a pre-production stepping. "
788 "It may not be fully functional.\n");
789 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_STILL_OK
);
794 * i915_driver_init_early - setup state not requiring device access
795 * @dev_priv: device private
797 * Initialize everything that is a "SW-only" state, that is state not
798 * requiring accessing the device or exposing the driver via kernel internal
799 * or userspace interfaces. Example steps belonging here: lock initialization,
800 * system memory allocation, setting up device specific attributes and
801 * function hooks not requiring accessing the device.
803 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
,
804 const struct pci_device_id
*ent
)
806 const struct intel_device_info
*match_info
=
807 (struct intel_device_info
*)ent
->driver_data
;
808 struct intel_device_info
*device_info
;
811 if (i915_inject_load_failure())
814 /* Setup the write-once "constant" device info */
815 device_info
= mkwrite_device_info(dev_priv
);
816 memcpy(device_info
, match_info
, sizeof(*device_info
));
817 device_info
->device_id
= dev_priv
->drm
.pdev
->device
;
819 BUG_ON(device_info
->gen
> sizeof(device_info
->gen_mask
) * BITS_PER_BYTE
);
820 device_info
->gen_mask
= BIT(device_info
->gen
- 1);
822 spin_lock_init(&dev_priv
->irq_lock
);
823 spin_lock_init(&dev_priv
->gpu_error
.lock
);
824 mutex_init(&dev_priv
->backlight_lock
);
825 spin_lock_init(&dev_priv
->uncore
.lock
);
827 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
828 spin_lock_init(&dev_priv
->mmio_flip_lock
);
829 mutex_init(&dev_priv
->sb_lock
);
830 mutex_init(&dev_priv
->modeset_restore_lock
);
831 mutex_init(&dev_priv
->av_mutex
);
832 mutex_init(&dev_priv
->wm
.wm_mutex
);
833 mutex_init(&dev_priv
->pps_mutex
);
835 intel_uc_init_early(dev_priv
);
836 i915_memcpy_init_early(dev_priv
);
838 ret
= i915_workqueues_init(dev_priv
);
842 /* This must be called before any calls to HAS_PCH_* */
843 intel_detect_pch(dev_priv
);
845 intel_pm_setup(dev_priv
);
846 intel_init_dpio(dev_priv
);
847 intel_power_domains_init(dev_priv
);
848 intel_irq_init(dev_priv
);
849 intel_hangcheck_init(dev_priv
);
850 intel_init_display_hooks(dev_priv
);
851 intel_init_clock_gating_hooks(dev_priv
);
852 intel_init_audio_hooks(dev_priv
);
853 ret
= i915_gem_load_init(dev_priv
);
857 intel_display_crc_init(dev_priv
);
859 intel_device_info_dump(dev_priv
);
861 intel_detect_preproduction_hw(dev_priv
);
863 i915_perf_init(dev_priv
);
868 intel_irq_fini(dev_priv
);
869 i915_workqueues_cleanup(dev_priv
);
871 i915_engines_cleanup(dev_priv
);
876 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
877 * @dev_priv: device private
879 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
881 i915_perf_fini(dev_priv
);
882 i915_gem_load_cleanup(dev_priv
);
883 intel_irq_fini(dev_priv
);
884 i915_workqueues_cleanup(dev_priv
);
885 i915_engines_cleanup(dev_priv
);
888 static int i915_mmio_setup(struct drm_i915_private
*dev_priv
)
890 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
894 mmio_bar
= IS_GEN2(dev_priv
) ? 1 : 0;
896 * Before gen4, the registers and the GTT are behind different BARs.
897 * However, from gen4 onwards, the registers and the GTT are shared
898 * in the same BAR, so we want to restrict this ioremap from
899 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
900 * the register BAR remains the same size for all the earlier
901 * generations up to Ironlake.
903 if (INTEL_GEN(dev_priv
) < 5)
904 mmio_size
= 512 * 1024;
906 mmio_size
= 2 * 1024 * 1024;
907 dev_priv
->regs
= pci_iomap(pdev
, mmio_bar
, mmio_size
);
908 if (dev_priv
->regs
== NULL
) {
909 DRM_ERROR("failed to map registers\n");
914 /* Try to make sure MCHBAR is enabled before poking at it */
915 intel_setup_mchbar(dev_priv
);
920 static void i915_mmio_cleanup(struct drm_i915_private
*dev_priv
)
922 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
924 intel_teardown_mchbar(dev_priv
);
925 pci_iounmap(pdev
, dev_priv
->regs
);
929 * i915_driver_init_mmio - setup device MMIO
930 * @dev_priv: device private
932 * Setup minimal device state necessary for MMIO accesses later in the
933 * initialization sequence. The setup here should avoid any other device-wide
934 * side effects or exposing the driver via kernel internal or user space
937 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
941 if (i915_inject_load_failure())
944 if (i915_get_bridge_dev(dev_priv
))
947 ret
= i915_mmio_setup(dev_priv
);
951 intel_uncore_init(dev_priv
);
953 ret
= intel_engines_init_mmio(dev_priv
);
957 i915_gem_init_mmio(dev_priv
);
962 intel_uncore_fini(dev_priv
);
964 pci_dev_put(dev_priv
->bridge_dev
);
970 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
971 * @dev_priv: device private
973 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
975 intel_uncore_fini(dev_priv
);
976 i915_mmio_cleanup(dev_priv
);
977 pci_dev_put(dev_priv
->bridge_dev
);
980 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
982 i915
.enable_execlists
=
983 intel_sanitize_enable_execlists(dev_priv
,
984 i915
.enable_execlists
);
987 * i915.enable_ppgtt is read-only, so do an early pass to validate the
988 * user's requested state against the hardware/driver capabilities. We
989 * do this now so that we can print out any log messages once rather
990 * than every time we check intel_enable_ppgtt().
993 intel_sanitize_enable_ppgtt(dev_priv
, i915
.enable_ppgtt
);
994 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
996 i915
.semaphores
= intel_sanitize_semaphores(dev_priv
, i915
.semaphores
);
997 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915
.semaphores
));
999 intel_uc_sanitize_options(dev_priv
);
1003 * i915_driver_init_hw - setup state requiring device access
1004 * @dev_priv: device private
1006 * Setup state that requires accessing the device, but doesn't require
1007 * exposing the driver via kernel internal or userspace interfaces.
1009 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
1011 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1014 if (i915_inject_load_failure())
1017 intel_device_info_runtime_init(dev_priv
);
1019 intel_sanitize_options(dev_priv
);
1021 ret
= i915_ggtt_probe_hw(dev_priv
);
1025 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1026 * otherwise the vga fbdev driver falls over. */
1027 ret
= i915_kick_out_firmware_fb(dev_priv
);
1029 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1033 ret
= i915_kick_out_vgacon(dev_priv
);
1035 DRM_ERROR("failed to remove conflicting VGA console\n");
1039 ret
= i915_ggtt_init_hw(dev_priv
);
1043 ret
= i915_ggtt_enable_hw(dev_priv
);
1045 DRM_ERROR("failed to enable GGTT\n");
1049 pci_set_master(pdev
);
1051 /* overlay on gen2 is broken and can't address above 1G */
1052 if (IS_GEN2(dev_priv
)) {
1053 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1055 DRM_ERROR("failed to set DMA mask\n");
1061 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1062 * using 32bit addressing, overwriting memory if HWS is located
1065 * The documentation also mentions an issue with undefined
1066 * behaviour if any general state is accessed within a page above 4GB,
1067 * which also needs to be handled carefully.
1069 if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
)) {
1070 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1073 DRM_ERROR("failed to set DMA mask\n");
1079 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1080 PM_QOS_DEFAULT_VALUE
);
1082 intel_uncore_sanitize(dev_priv
);
1084 intel_opregion_setup(dev_priv
);
1086 i915_gem_load_init_fences(dev_priv
);
1088 /* On the 945G/GM, the chipset reports the MSI capability on the
1089 * integrated graphics even though the support isn't actually there
1090 * according to the published specs. It doesn't appear to function
1091 * correctly in testing on 945G.
1092 * This may be a side effect of MSI having been made available for PEG
1093 * and the registers being closely associated.
1095 * According to chipset errata, on the 965GM, MSI interrupts may
1096 * be lost or delayed, but we use them anyways to avoid
1097 * stuck interrupts on some machines.
1099 if (!IS_I945G(dev_priv
) && !IS_I945GM(dev_priv
)) {
1100 if (pci_enable_msi(pdev
) < 0)
1101 DRM_DEBUG_DRIVER("can't enable MSI");
1104 ret
= intel_gvt_init(dev_priv
);
1111 i915_ggtt_cleanup_hw(dev_priv
);
1117 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1118 * @dev_priv: device private
1120 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1122 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1124 if (pdev
->msi_enabled
)
1125 pci_disable_msi(pdev
);
1127 pm_qos_remove_request(&dev_priv
->pm_qos
);
1128 i915_ggtt_cleanup_hw(dev_priv
);
1132 * i915_driver_register - register the driver with the rest of the system
1133 * @dev_priv: device private
1135 * Perform any steps necessary to make the driver available via kernel
1136 * internal or userspace interfaces.
1138 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1140 struct drm_device
*dev
= &dev_priv
->drm
;
1142 i915_gem_shrinker_init(dev_priv
);
1145 * Notify a valid surface after modesetting,
1146 * when running inside a VM.
1148 if (intel_vgpu_active(dev_priv
))
1149 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1151 /* Reveal our presence to userspace */
1152 if (drm_dev_register(dev
, 0) == 0) {
1153 i915_debugfs_register(dev_priv
);
1154 i915_guc_log_register(dev_priv
);
1155 i915_setup_sysfs(dev_priv
);
1157 /* Depends on sysfs having been initialized */
1158 i915_perf_register(dev_priv
);
1160 DRM_ERROR("Failed to register driver for userspace access!\n");
1162 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1163 /* Must be done after probing outputs */
1164 intel_opregion_register(dev_priv
);
1165 acpi_video_register();
1168 if (IS_GEN5(dev_priv
))
1169 intel_gpu_ips_init(dev_priv
);
1171 intel_audio_init(dev_priv
);
1174 * Some ports require correctly set-up hpd registers for detection to
1175 * work properly (leading to ghost connected connector status), e.g. VGA
1176 * on gm45. Hence we can only set up the initial fbdev config after hpd
1177 * irqs are fully enabled. We do it last so that the async config
1178 * cannot run before the connectors are registered.
1180 intel_fbdev_initial_config_async(dev
);
1184 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1185 * @dev_priv: device private
1187 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1189 intel_audio_deinit(dev_priv
);
1191 intel_gpu_ips_teardown();
1192 acpi_video_unregister();
1193 intel_opregion_unregister(dev_priv
);
1195 i915_perf_unregister(dev_priv
);
1197 i915_teardown_sysfs(dev_priv
);
1198 i915_guc_log_unregister(dev_priv
);
1199 drm_dev_unregister(&dev_priv
->drm
);
1201 i915_gem_shrinker_cleanup(dev_priv
);
1205 * i915_driver_load - setup chip and create an initial config
1207 * @ent: matching PCI ID entry
1209 * The driver load routine has to do several things:
1210 * - drive output discovery via intel_modeset_init()
1211 * - initialize the memory manager
1212 * - allocate initial config memory
1213 * - setup the DRM framebuffer with the allocated memory
1215 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1217 const struct intel_device_info
*match_info
=
1218 (struct intel_device_info
*)ent
->driver_data
;
1219 struct drm_i915_private
*dev_priv
;
1222 /* Enable nuclear pageflip on ILK+ */
1223 if (!i915
.nuclear_pageflip
&& match_info
->gen
< 5)
1224 driver
.driver_features
&= ~DRIVER_ATOMIC
;
1227 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1229 ret
= drm_dev_init(&dev_priv
->drm
, &driver
, &pdev
->dev
);
1231 DRM_DEV_ERROR(&pdev
->dev
, "allocation failed\n");
1235 dev_priv
->drm
.pdev
= pdev
;
1236 dev_priv
->drm
.dev_private
= dev_priv
;
1238 ret
= pci_enable_device(pdev
);
1242 pci_set_drvdata(pdev
, &dev_priv
->drm
);
1244 * Disable the system suspend direct complete optimization, which can
1245 * leave the device suspended skipping the driver's suspend handlers
1246 * if the device was already runtime suspended. This is needed due to
1247 * the difference in our runtime and system suspend sequence and
1248 * becaue the HDA driver may require us to enable the audio power
1249 * domain during system suspend.
1251 pdev
->dev_flags
|= PCI_DEV_FLAGS_NEEDS_RESUME
;
1253 ret
= i915_driver_init_early(dev_priv
, ent
);
1255 goto out_pci_disable
;
1257 intel_runtime_pm_get(dev_priv
);
1259 ret
= i915_driver_init_mmio(dev_priv
);
1261 goto out_runtime_pm_put
;
1263 ret
= i915_driver_init_hw(dev_priv
);
1265 goto out_cleanup_mmio
;
1268 * TODO: move the vblank init and parts of modeset init steps into one
1269 * of the i915_driver_init_/i915_driver_register functions according
1270 * to the role/effect of the given init step.
1272 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1273 ret
= drm_vblank_init(&dev_priv
->drm
,
1274 INTEL_INFO(dev_priv
)->num_pipes
);
1276 goto out_cleanup_hw
;
1279 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1281 goto out_cleanup_vblank
;
1283 i915_driver_register(dev_priv
);
1285 intel_runtime_pm_enable(dev_priv
);
1287 dev_priv
->ipc_enabled
= false;
1289 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
1290 DRM_INFO("DRM_I915_DEBUG enabled\n");
1291 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1292 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1294 intel_runtime_pm_put(dev_priv
);
1299 drm_vblank_cleanup(&dev_priv
->drm
);
1301 i915_driver_cleanup_hw(dev_priv
);
1303 i915_driver_cleanup_mmio(dev_priv
);
1305 intel_runtime_pm_put(dev_priv
);
1306 i915_driver_cleanup_early(dev_priv
);
1308 pci_disable_device(pdev
);
1310 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1311 drm_dev_fini(&dev_priv
->drm
);
1317 void i915_driver_unload(struct drm_device
*dev
)
1319 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1320 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1322 intel_fbdev_fini(dev
);
1324 if (i915_gem_suspend(dev_priv
))
1325 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1327 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
1329 drm_atomic_helper_shutdown(dev
);
1331 intel_gvt_cleanup(dev_priv
);
1333 i915_driver_unregister(dev_priv
);
1335 drm_vblank_cleanup(dev
);
1337 intel_modeset_cleanup(dev
);
1340 * free the memory space allocated for the child device
1341 * config parsed from VBT
1343 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1344 kfree(dev_priv
->vbt
.child_dev
);
1345 dev_priv
->vbt
.child_dev
= NULL
;
1346 dev_priv
->vbt
.child_dev_num
= 0;
1348 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1349 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1350 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1351 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1353 vga_switcheroo_unregister_client(pdev
);
1354 vga_client_register(pdev
, NULL
, NULL
, NULL
);
1356 intel_csr_ucode_fini(dev_priv
);
1358 /* Free error state after interrupts are fully disabled. */
1359 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1360 i915_reset_error_state(dev_priv
);
1362 /* Flush any outstanding unpin_work. */
1363 drain_workqueue(dev_priv
->wq
);
1365 i915_gem_fini(dev_priv
);
1366 intel_uc_fini_fw(dev_priv
);
1367 intel_fbc_cleanup_cfb(dev_priv
);
1369 intel_power_domains_fini(dev_priv
);
1371 i915_driver_cleanup_hw(dev_priv
);
1372 i915_driver_cleanup_mmio(dev_priv
);
1374 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
1377 static void i915_driver_release(struct drm_device
*dev
)
1379 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1381 i915_driver_cleanup_early(dev_priv
);
1382 drm_dev_fini(&dev_priv
->drm
);
1387 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1391 ret
= i915_gem_open(dev
, file
);
1399 * i915_driver_lastclose - clean up after all DRM clients have exited
1402 * Take care of cleaning up after all DRM clients have exited. In the
1403 * mode setting case, we want to restore the kernel's initial mode (just
1404 * in case the last client left us in a bad state).
1406 * Additionally, in the non-mode setting case, we'll tear down the GTT
1407 * and DMA structures, since the kernel won't be using them, and clea
1410 static void i915_driver_lastclose(struct drm_device
*dev
)
1412 intel_fbdev_restore_mode(dev
);
1413 vga_switcheroo_process_delayed_switch();
1416 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1418 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1420 mutex_lock(&dev
->struct_mutex
);
1421 i915_gem_context_close(dev
, file
);
1422 i915_gem_release(dev
, file
);
1423 mutex_unlock(&dev
->struct_mutex
);
1428 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1430 struct drm_device
*dev
= &dev_priv
->drm
;
1431 struct intel_encoder
*encoder
;
1433 drm_modeset_lock_all(dev
);
1434 for_each_intel_encoder(dev
, encoder
)
1435 if (encoder
->suspend
)
1436 encoder
->suspend(encoder
);
1437 drm_modeset_unlock_all(dev
);
1440 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1442 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1444 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1446 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1447 if (acpi_target_system_state() < ACPI_STATE_S3
)
1453 static int i915_drm_suspend(struct drm_device
*dev
)
1455 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1456 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1457 pci_power_t opregion_target_state
;
1460 /* ignore lid events during suspend */
1461 mutex_lock(&dev_priv
->modeset_restore_lock
);
1462 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
1463 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1465 disable_rpm_wakeref_asserts(dev_priv
);
1467 /* We do a lot of poking in a lot of registers, make sure they work
1469 intel_display_set_init_power(dev_priv
, true);
1471 drm_kms_helper_poll_disable(dev
);
1473 pci_save_state(pdev
);
1475 error
= i915_gem_suspend(dev_priv
);
1478 "GEM idle failed, resume might fail\n");
1482 intel_display_suspend(dev
);
1484 intel_dp_mst_suspend(dev
);
1486 intel_runtime_pm_disable_interrupts(dev_priv
);
1487 intel_hpd_cancel_work(dev_priv
);
1489 intel_suspend_encoders(dev_priv
);
1491 intel_suspend_hw(dev_priv
);
1493 i915_gem_suspend_gtt_mappings(dev_priv
);
1495 i915_save_state(dev_priv
);
1497 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1498 intel_opregion_notify_adapter(dev_priv
, opregion_target_state
);
1500 intel_uncore_suspend(dev_priv
);
1501 intel_opregion_unregister(dev_priv
);
1503 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1505 dev_priv
->suspend_count
++;
1507 intel_csr_ucode_suspend(dev_priv
);
1510 enable_rpm_wakeref_asserts(dev_priv
);
1515 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1517 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1518 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1522 disable_rpm_wakeref_asserts(dev_priv
);
1524 intel_display_set_init_power(dev_priv
, false);
1526 fw_csr
= !IS_GEN9_LP(dev_priv
) &&
1527 suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
1529 * In case of firmware assisted context save/restore don't manually
1530 * deinit the power domains. This also means the CSR/DMC firmware will
1531 * stay active, it will power down any HW resources as required and
1532 * also enable deeper system power states that would be blocked if the
1533 * firmware was inactive.
1536 intel_power_domains_suspend(dev_priv
);
1539 if (IS_GEN9_LP(dev_priv
))
1540 bxt_enable_dc9(dev_priv
);
1541 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1542 hsw_enable_pc8(dev_priv
);
1543 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1544 ret
= vlv_suspend_complete(dev_priv
);
1547 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1549 intel_power_domains_init_hw(dev_priv
, true);
1554 pci_disable_device(pdev
);
1556 * During hibernation on some platforms the BIOS may try to access
1557 * the device even though it's already in D3 and hang the machine. So
1558 * leave the device in D0 on those platforms and hope the BIOS will
1559 * power down the device properly. The issue was seen on multiple old
1560 * GENs with different BIOS vendors, so having an explicit blacklist
1561 * is inpractical; apply the workaround on everything pre GEN6. The
1562 * platforms where the issue was seen:
1563 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1567 if (!(hibernation
&& INTEL_GEN(dev_priv
) < 6))
1568 pci_set_power_state(pdev
, PCI_D3hot
);
1570 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
1573 enable_rpm_wakeref_asserts(dev_priv
);
1578 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
1583 DRM_ERROR("dev: %p\n", dev
);
1584 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1588 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1589 state
.event
!= PM_EVENT_FREEZE
))
1592 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1595 error
= i915_drm_suspend(dev
);
1599 return i915_drm_suspend_late(dev
, false);
1602 static int i915_drm_resume(struct drm_device
*dev
)
1604 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1607 disable_rpm_wakeref_asserts(dev_priv
);
1608 intel_sanitize_gt_powersave(dev_priv
);
1610 ret
= i915_ggtt_enable_hw(dev_priv
);
1612 DRM_ERROR("failed to re-enable GGTT\n");
1614 intel_csr_ucode_resume(dev_priv
);
1616 i915_gem_resume(dev_priv
);
1618 i915_restore_state(dev_priv
);
1619 intel_pps_unlock_regs_wa(dev_priv
);
1620 intel_opregion_setup(dev_priv
);
1622 intel_init_pch_refclk(dev_priv
);
1625 * Interrupts have to be enabled before any batches are run. If not the
1626 * GPU will hang. i915_gem_init_hw() will initiate batches to
1627 * update/restore the context.
1629 * drm_mode_config_reset() needs AUX interrupts.
1631 * Modeset enabling in intel_modeset_init_hw() also needs working
1634 intel_runtime_pm_enable_interrupts(dev_priv
);
1636 drm_mode_config_reset(dev
);
1638 mutex_lock(&dev
->struct_mutex
);
1639 if (i915_gem_init_hw(dev_priv
)) {
1640 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1641 i915_gem_set_wedged(dev_priv
);
1643 mutex_unlock(&dev
->struct_mutex
);
1645 intel_guc_resume(dev_priv
);
1647 intel_modeset_init_hw(dev
);
1649 spin_lock_irq(&dev_priv
->irq_lock
);
1650 if (dev_priv
->display
.hpd_irq_setup
)
1651 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1652 spin_unlock_irq(&dev_priv
->irq_lock
);
1654 intel_dp_mst_resume(dev
);
1656 intel_display_resume(dev
);
1658 drm_kms_helper_poll_enable(dev
);
1661 * ... but also need to make sure that hotplug processing
1662 * doesn't cause havoc. Like in the driver load code we don't
1663 * bother with the tiny race here where we might loose hotplug
1666 intel_hpd_init(dev_priv
);
1668 intel_opregion_register(dev_priv
);
1670 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1672 mutex_lock(&dev_priv
->modeset_restore_lock
);
1673 dev_priv
->modeset_restore
= MODESET_DONE
;
1674 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1676 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1678 intel_autoenable_gt_powersave(dev_priv
);
1680 enable_rpm_wakeref_asserts(dev_priv
);
1685 static int i915_drm_resume_early(struct drm_device
*dev
)
1687 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1688 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1692 * We have a resume ordering issue with the snd-hda driver also
1693 * requiring our device to be power up. Due to the lack of a
1694 * parent/child relationship we currently solve this with an early
1697 * FIXME: This should be solved with a special hdmi sink device or
1698 * similar so that power domains can be employed.
1702 * Note that we need to set the power state explicitly, since we
1703 * powered off the device during freeze and the PCI core won't power
1704 * it back up for us during thaw. Powering off the device during
1705 * freeze is not a hard requirement though, and during the
1706 * suspend/resume phases the PCI core makes sure we get here with the
1707 * device powered on. So in case we change our freeze logic and keep
1708 * the device powered we can also remove the following set power state
1711 ret
= pci_set_power_state(pdev
, PCI_D0
);
1713 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1718 * Note that pci_enable_device() first enables any parent bridge
1719 * device and only then sets the power state for this device. The
1720 * bridge enabling is a nop though, since bridge devices are resumed
1721 * first. The order of enabling power and enabling the device is
1722 * imposed by the PCI core as described above, so here we preserve the
1723 * same order for the freeze/thaw phases.
1725 * TODO: eventually we should remove pci_disable_device() /
1726 * pci_enable_enable_device() from suspend/resume. Due to how they
1727 * depend on the device enable refcount we can't anyway depend on them
1728 * disabling/enabling the device.
1730 if (pci_enable_device(pdev
)) {
1735 pci_set_master(pdev
);
1737 disable_rpm_wakeref_asserts(dev_priv
);
1739 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1740 ret
= vlv_resume_prepare(dev_priv
, false);
1742 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1745 intel_uncore_resume_early(dev_priv
);
1747 if (IS_GEN9_LP(dev_priv
)) {
1748 if (!dev_priv
->suspended_to_idle
)
1749 gen9_sanitize_dc_state(dev_priv
);
1750 bxt_disable_dc9(dev_priv
);
1751 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1752 hsw_disable_pc8(dev_priv
);
1755 intel_uncore_sanitize(dev_priv
);
1757 if (IS_GEN9_LP(dev_priv
) ||
1758 !(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
1759 intel_power_domains_init_hw(dev_priv
, true);
1761 i915_gem_sanitize(dev_priv
);
1763 enable_rpm_wakeref_asserts(dev_priv
);
1766 dev_priv
->suspended_to_idle
= false;
1771 static int i915_resume_switcheroo(struct drm_device
*dev
)
1775 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1778 ret
= i915_drm_resume_early(dev
);
1782 return i915_drm_resume(dev
);
1786 * i915_reset - reset chip after a hang
1787 * @dev_priv: device private to reset
1789 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1792 * Caller must hold the struct_mutex.
1794 * Procedure is fairly simple:
1795 * - reset the chip using the reset reg
1796 * - re-init context state
1797 * - re-init hardware status page
1798 * - re-init ring buffer
1799 * - re-init interrupt state
1802 void i915_reset(struct drm_i915_private
*dev_priv
)
1804 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
1807 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
1808 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF
, &error
->flags
));
1810 if (!test_bit(I915_RESET_HANDOFF
, &error
->flags
))
1813 /* Clear any previous failed attempts at recovery. Time to try again. */
1814 if (!i915_gem_unset_wedged(dev_priv
))
1817 error
->reset_count
++;
1819 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1820 disable_irq(dev_priv
->drm
.irq
);
1821 ret
= i915_gem_reset_prepare(dev_priv
);
1823 DRM_ERROR("GPU recovery failed\n");
1824 intel_gpu_reset(dev_priv
, ALL_ENGINES
);
1828 ret
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
1831 DRM_ERROR("Failed to reset chip: %i\n", ret
);
1833 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1837 i915_gem_reset(dev_priv
);
1838 intel_overlay_reset(dev_priv
);
1840 /* Ok, now get things going again... */
1843 * Everything depends on having the GTT running, so we need to start
1844 * there. Fortunately we don't need to do this unless we reset the
1845 * chip at a PCI level.
1847 * Next we need to restore the context, but we don't use those
1850 * Ring buffer needs to be re-initialized in the KMS case, or if X
1851 * was running at the time of the reset (i.e. we weren't VT
1854 ret
= i915_gem_init_hw(dev_priv
);
1856 DRM_ERROR("Failed hw init on reset %d\n", ret
);
1860 i915_queue_hangcheck(dev_priv
);
1863 i915_gem_reset_finish(dev_priv
);
1864 enable_irq(dev_priv
->drm
.irq
);
1867 clear_bit(I915_RESET_HANDOFF
, &error
->flags
);
1868 wake_up_bit(&error
->flags
, I915_RESET_HANDOFF
);
1872 i915_gem_set_wedged(dev_priv
);
1876 static int i915_pm_suspend(struct device
*kdev
)
1878 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1879 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1882 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
1886 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1889 return i915_drm_suspend(dev
);
1892 static int i915_pm_suspend_late(struct device
*kdev
)
1894 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1897 * We have a suspend ordering issue with the snd-hda driver also
1898 * requiring our device to be power up. Due to the lack of a
1899 * parent/child relationship we currently solve this with an late
1902 * FIXME: This should be solved with a special hdmi sink device or
1903 * similar so that power domains can be employed.
1905 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1908 return i915_drm_suspend_late(dev
, false);
1911 static int i915_pm_poweroff_late(struct device
*kdev
)
1913 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1915 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1918 return i915_drm_suspend_late(dev
, true);
1921 static int i915_pm_resume_early(struct device
*kdev
)
1923 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1925 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1928 return i915_drm_resume_early(dev
);
1931 static int i915_pm_resume(struct device
*kdev
)
1933 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
1935 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1938 return i915_drm_resume(dev
);
1941 /* freeze: before creating the hibernation_image */
1942 static int i915_pm_freeze(struct device
*kdev
)
1946 ret
= i915_pm_suspend(kdev
);
1950 ret
= i915_gem_freeze(kdev_to_i915(kdev
));
1957 static int i915_pm_freeze_late(struct device
*kdev
)
1961 ret
= i915_pm_suspend_late(kdev
);
1965 ret
= i915_gem_freeze_late(kdev_to_i915(kdev
));
1972 /* thaw: called after creating the hibernation image, but before turning off. */
1973 static int i915_pm_thaw_early(struct device
*kdev
)
1975 return i915_pm_resume_early(kdev
);
1978 static int i915_pm_thaw(struct device
*kdev
)
1980 return i915_pm_resume(kdev
);
1983 /* restore: called after loading the hibernation image. */
1984 static int i915_pm_restore_early(struct device
*kdev
)
1986 return i915_pm_resume_early(kdev
);
1989 static int i915_pm_restore(struct device
*kdev
)
1991 return i915_pm_resume(kdev
);
1995 * Save all Gunit registers that may be lost after a D3 and a subsequent
1996 * S0i[R123] transition. The list of registers needing a save/restore is
1997 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1998 * registers in the following way:
1999 * - Driver: saved/restored by the driver
2000 * - Punit : saved/restored by the Punit firmware
2001 * - No, w/o marking: no need to save/restore, since the register is R/O or
2002 * used internally by the HW in a way that doesn't depend
2003 * keeping the content across a suspend/resume.
2004 * - Debug : used for debugging
2006 * We save/restore all registers marked with 'Driver', with the following
2008 * - Registers out of use, including also registers marked with 'Debug'.
2009 * These have no effect on the driver's operation, so we don't save/restore
2010 * them to reduce the overhead.
2011 * - Registers that are fully setup by an initialization function called from
2012 * the resume path. For example many clock gating and RPS/RC6 registers.
2013 * - Registers that provide the right functionality with their reset defaults.
2015 * TODO: Except for registers that based on the above 3 criteria can be safely
2016 * ignored, we save/restore all others, practically treating the HW context as
2017 * a black-box for the driver. Further investigation is needed to reduce the
2018 * saved/restored registers even further, by following the same 3 criteria.
2020 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2022 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2025 /* GAM 0x4000-0x4770 */
2026 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
2027 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
2028 s
->arb_mode
= I915_READ(ARB_MODE
);
2029 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
2030 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
2032 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2033 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
2035 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
2036 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
2038 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
2039 s
->ecochk
= I915_READ(GAM_ECOCHK
);
2040 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
2041 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
2043 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
2045 /* MBC 0x9024-0x91D0, 0x8500 */
2046 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
2047 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
2048 s
->mbctl
= I915_READ(GEN6_MBCTL
);
2050 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2051 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2052 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2053 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2054 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2055 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2056 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2058 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2059 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2060 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2061 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2062 s
->ecobus
= I915_READ(ECOBUS
);
2063 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2064 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2065 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2066 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2067 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2068 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2070 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2071 s
->gt_imr
= I915_READ(GTIMR
);
2072 s
->gt_ier
= I915_READ(GTIER
);
2073 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2074 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2076 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2077 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2079 /* GT SA CZ domain, 0x100000-0x138124 */
2080 s
->tilectl
= I915_READ(TILECTL
);
2081 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2082 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2083 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2084 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2086 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2087 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2088 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2089 s
->pcbr
= I915_READ(VLV_PCBR
);
2090 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2093 * Not saving any of:
2094 * DFT, 0x9800-0x9EC0
2095 * SARB, 0xB000-0xB1FC
2096 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2101 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2103 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2107 /* GAM 0x4000-0x4770 */
2108 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2109 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2110 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2111 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2112 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2114 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2115 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2117 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2118 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2120 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2121 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2122 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2123 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2125 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2127 /* MBC 0x9024-0x91D0, 0x8500 */
2128 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2129 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2130 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2132 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2133 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2134 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2135 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2136 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2137 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2138 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2140 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2141 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2142 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2143 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2144 I915_WRITE(ECOBUS
, s
->ecobus
);
2145 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2146 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2147 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2148 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2149 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2150 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2152 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2153 I915_WRITE(GTIMR
, s
->gt_imr
);
2154 I915_WRITE(GTIER
, s
->gt_ier
);
2155 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2156 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2158 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2159 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2161 /* GT SA CZ domain, 0x100000-0x138124 */
2162 I915_WRITE(TILECTL
, s
->tilectl
);
2163 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2165 * Preserve the GT allow wake and GFX force clock bit, they are not
2166 * be restored, as they are used to control the s0ix suspend/resume
2167 * sequence by the caller.
2169 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2170 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2171 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2172 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2174 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2175 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2176 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2177 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2179 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2181 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2182 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2183 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2184 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2185 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2188 static int vlv_wait_for_pw_status(struct drm_i915_private
*dev_priv
,
2191 /* The HW does not like us polling for PW_STATUS frequently, so
2192 * use the sleeping loop rather than risk the busy spin within
2193 * intel_wait_for_register().
2195 * Transitioning between RC6 states should be at most 2ms (see
2196 * valleyview_enable_rps) so use a 3ms timeout.
2198 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS
) & mask
) == val
,
2202 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2207 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2208 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2210 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2211 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2216 err
= intel_wait_for_register(dev_priv
,
2217 VLV_GTLC_SURVIVABILITY_REG
,
2218 VLV_GFX_CLK_STATUS_BIT
,
2219 VLV_GFX_CLK_STATUS_BIT
,
2222 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2223 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2228 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2234 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2235 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2237 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2238 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2239 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2241 mask
= VLV_GTLC_ALLOWWAKEACK
;
2242 val
= allow
? mask
: 0;
2244 err
= vlv_wait_for_pw_status(dev_priv
, mask
, val
);
2246 DRM_ERROR("timeout disabling GT waking\n");
2251 static void vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2257 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2258 val
= wait_for_on
? mask
: 0;
2261 * RC6 transitioning can be delayed up to 2 msec (see
2262 * valleyview_enable_rps), use 3 msec for safety.
2264 if (vlv_wait_for_pw_status(dev_priv
, mask
, val
))
2265 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2266 onoff(wait_for_on
));
2269 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2271 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2274 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2275 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2278 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2284 * Bspec defines the following GT well on flags as debug only, so
2285 * don't treat them as hard failures.
2287 vlv_wait_for_gt_wells(dev_priv
, false);
2289 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2290 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2292 vlv_check_no_gt_access(dev_priv
);
2294 err
= vlv_force_gfx_clock(dev_priv
, true);
2298 err
= vlv_allow_gt_wake(dev_priv
, false);
2302 if (!IS_CHERRYVIEW(dev_priv
))
2303 vlv_save_gunit_s0ix_state(dev_priv
);
2305 err
= vlv_force_gfx_clock(dev_priv
, false);
2312 /* For safety always re-enable waking and disable gfx clock forcing */
2313 vlv_allow_gt_wake(dev_priv
, true);
2315 vlv_force_gfx_clock(dev_priv
, false);
2320 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2327 * If any of the steps fail just try to continue, that's the best we
2328 * can do at this point. Return the first error code (which will also
2329 * leave RPM permanently disabled).
2331 ret
= vlv_force_gfx_clock(dev_priv
, true);
2333 if (!IS_CHERRYVIEW(dev_priv
))
2334 vlv_restore_gunit_s0ix_state(dev_priv
);
2336 err
= vlv_allow_gt_wake(dev_priv
, true);
2340 err
= vlv_force_gfx_clock(dev_priv
, false);
2344 vlv_check_no_gt_access(dev_priv
);
2347 intel_init_clock_gating(dev_priv
);
2352 static int intel_runtime_suspend(struct device
*kdev
)
2354 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2355 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2356 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2359 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6())))
2362 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2365 DRM_DEBUG_KMS("Suspending device\n");
2367 disable_rpm_wakeref_asserts(dev_priv
);
2370 * We are safe here against re-faults, since the fault handler takes
2373 i915_gem_runtime_suspend(dev_priv
);
2375 intel_guc_suspend(dev_priv
);
2377 intel_runtime_pm_disable_interrupts(dev_priv
);
2380 if (IS_GEN9_LP(dev_priv
)) {
2381 bxt_display_core_uninit(dev_priv
);
2382 bxt_enable_dc9(dev_priv
);
2383 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2384 hsw_enable_pc8(dev_priv
);
2385 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2386 ret
= vlv_suspend_complete(dev_priv
);
2390 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2391 intel_runtime_pm_enable_interrupts(dev_priv
);
2393 enable_rpm_wakeref_asserts(dev_priv
);
2398 intel_uncore_suspend(dev_priv
);
2400 enable_rpm_wakeref_asserts(dev_priv
);
2401 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2403 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
2404 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2406 dev_priv
->pm
.suspended
= true;
2409 * FIXME: We really should find a document that references the arguments
2412 if (IS_BROADWELL(dev_priv
)) {
2414 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2415 * being detected, and the call we do at intel_runtime_resume()
2416 * won't be able to restore them. Since PCI_D3hot matches the
2417 * actual specification and appears to be working, use it.
2419 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2422 * current versions of firmware which depend on this opregion
2423 * notification have repurposed the D1 definition to mean
2424 * "runtime suspended" vs. what you would normally expect (D3)
2425 * to distinguish it from notifications that might be sent via
2428 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2431 assert_forcewakes_inactive(dev_priv
);
2433 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2434 intel_hpd_poll_init(dev_priv
);
2436 DRM_DEBUG_KMS("Device suspended\n");
2440 static int intel_runtime_resume(struct device
*kdev
)
2442 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2443 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2444 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2447 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2450 DRM_DEBUG_KMS("Resuming device\n");
2452 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2453 disable_rpm_wakeref_asserts(dev_priv
);
2455 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2456 dev_priv
->pm
.suspended
= false;
2457 if (intel_uncore_unclaimed_mmio(dev_priv
))
2458 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2460 intel_guc_resume(dev_priv
);
2462 if (IS_GEN6(dev_priv
))
2463 intel_init_pch_refclk(dev_priv
);
2465 if (IS_GEN9_LP(dev_priv
)) {
2466 bxt_disable_dc9(dev_priv
);
2467 bxt_display_core_init(dev_priv
, true);
2468 if (dev_priv
->csr
.dmc_payload
&&
2469 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
2470 gen9_enable_dc5(dev_priv
);
2471 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2472 hsw_disable_pc8(dev_priv
);
2473 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2474 ret
= vlv_resume_prepare(dev_priv
, true);
2478 * No point of rolling back things in case of an error, as the best
2479 * we can do is to hope that things will still work (and disable RPM).
2481 i915_gem_init_swizzling(dev_priv
);
2482 i915_gem_restore_fences(dev_priv
);
2484 intel_runtime_pm_enable_interrupts(dev_priv
);
2487 * On VLV/CHV display interrupts are part of the display
2488 * power well, so hpd is reinitialized from there. For
2489 * everyone else do it here.
2491 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2492 intel_hpd_init(dev_priv
);
2494 enable_rpm_wakeref_asserts(dev_priv
);
2497 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2499 DRM_DEBUG_KMS("Device resumed\n");
2504 const struct dev_pm_ops i915_pm_ops
= {
2506 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2509 .suspend
= i915_pm_suspend
,
2510 .suspend_late
= i915_pm_suspend_late
,
2511 .resume_early
= i915_pm_resume_early
,
2512 .resume
= i915_pm_resume
,
2516 * @freeze, @freeze_late : called (1) before creating the
2517 * hibernation image [PMSG_FREEZE] and
2518 * (2) after rebooting, before restoring
2519 * the image [PMSG_QUIESCE]
2520 * @thaw, @thaw_early : called (1) after creating the hibernation
2521 * image, before writing it [PMSG_THAW]
2522 * and (2) after failing to create or
2523 * restore the image [PMSG_RECOVER]
2524 * @poweroff, @poweroff_late: called after writing the hibernation
2525 * image, before rebooting [PMSG_HIBERNATE]
2526 * @restore, @restore_early : called after rebooting and restoring the
2527 * hibernation image [PMSG_RESTORE]
2529 .freeze
= i915_pm_freeze
,
2530 .freeze_late
= i915_pm_freeze_late
,
2531 .thaw_early
= i915_pm_thaw_early
,
2532 .thaw
= i915_pm_thaw
,
2533 .poweroff
= i915_pm_suspend
,
2534 .poweroff_late
= i915_pm_poweroff_late
,
2535 .restore_early
= i915_pm_restore_early
,
2536 .restore
= i915_pm_restore
,
2538 /* S0ix (via runtime suspend) event handlers */
2539 .runtime_suspend
= intel_runtime_suspend
,
2540 .runtime_resume
= intel_runtime_resume
,
2543 static const struct vm_operations_struct i915_gem_vm_ops
= {
2544 .fault
= i915_gem_fault
,
2545 .open
= drm_gem_vm_open
,
2546 .close
= drm_gem_vm_close
,
2549 static const struct file_operations i915_driver_fops
= {
2550 .owner
= THIS_MODULE
,
2552 .release
= drm_release
,
2553 .unlocked_ioctl
= drm_ioctl
,
2554 .mmap
= drm_gem_mmap
,
2557 .compat_ioctl
= i915_compat_ioctl
,
2558 .llseek
= noop_llseek
,
2562 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2563 struct drm_file
*file
)
2568 static const struct drm_ioctl_desc i915_ioctls
[] = {
2569 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2570 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2571 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2572 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2573 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2574 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2575 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2576 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2577 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2578 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2579 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2580 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2581 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2582 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2583 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2584 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2585 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2586 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2587 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
2588 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2589 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2590 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2591 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2592 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2593 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2594 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2595 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2596 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2597 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2598 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2599 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2600 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2601 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
2602 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2603 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2604 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
2605 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
2606 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2607 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
2608 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2609 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2610 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2611 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2612 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2613 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2614 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2615 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2616 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2617 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2618 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2619 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2620 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2621 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
2624 static struct drm_driver driver
= {
2625 /* Don't use MTRRs here; the Xserver or userspace app should
2626 * deal with them for Intel hardware.
2629 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
2630 DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_ATOMIC
,
2631 .release
= i915_driver_release
,
2632 .open
= i915_driver_open
,
2633 .lastclose
= i915_driver_lastclose
,
2634 .postclose
= i915_driver_postclose
,
2635 .set_busid
= drm_pci_set_busid
,
2637 .gem_close_object
= i915_gem_close_object
,
2638 .gem_free_object_unlocked
= i915_gem_free_object
,
2639 .gem_vm_ops
= &i915_gem_vm_ops
,
2641 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2642 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2643 .gem_prime_export
= i915_gem_prime_export
,
2644 .gem_prime_import
= i915_gem_prime_import
,
2646 .dumb_create
= i915_gem_dumb_create
,
2647 .dumb_map_offset
= i915_gem_mmap_gtt
,
2648 .dumb_destroy
= drm_gem_dumb_destroy
,
2649 .ioctls
= i915_ioctls
,
2650 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2651 .fops
= &i915_driver_fops
,
2652 .name
= DRIVER_NAME
,
2653 .desc
= DRIVER_DESC
,
2654 .date
= DRIVER_DATE
,
2655 .major
= DRIVER_MAJOR
,
2656 .minor
= DRIVER_MINOR
,
2657 .patchlevel
= DRIVER_PATCHLEVEL
,
2660 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2661 #include "selftests/mock_drm.c"