1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
41 #include <acpi/video.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_irq.h>
46 #include <drm/drm_probe_helper.h>
47 #include <drm/i915_drm.h>
49 #include "display/intel_acpi.h"
50 #include "display/intel_audio.h"
51 #include "display/intel_bw.h"
52 #include "display/intel_cdclk.h"
53 #include "display/intel_display_types.h"
54 #include "display/intel_dp.h"
55 #include "display/intel_fbdev.h"
56 #include "display/intel_hotplug.h"
57 #include "display/intel_overlay.h"
58 #include "display/intel_pipe_crc.h"
59 #include "display/intel_psr.h"
60 #include "display/intel_sprite.h"
61 #include "display/intel_vga.h"
63 #include "gem/i915_gem_context.h"
64 #include "gem/i915_gem_ioctls.h"
65 #include "gem/i915_gem_mman.h"
66 #include "gt/intel_gt.h"
67 #include "gt/intel_gt_pm.h"
68 #include "gt/intel_rc6.h"
70 #include "i915_debugfs.h"
73 #include "i915_memcpy.h"
74 #include "i915_perf.h"
75 #include "i915_query.h"
76 #include "i915_suspend.h"
77 #include "i915_switcheroo.h"
78 #include "i915_sysfs.h"
79 #include "i915_trace.h"
80 #include "i915_vgpu.h"
81 #include "intel_csr.h"
82 #include "intel_memory_region.h"
85 static struct drm_driver driver
;
87 struct vlv_s0ix_state
{
94 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
95 u32 media_max_req_count
;
96 u32 gfx_max_req_count
;
128 /* Display 1 CZ domain */
133 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
135 /* GT SA CZ domain */
142 /* Display 2 CZ domain */
149 static int i915_get_bridge_dev(struct drm_i915_private
*dev_priv
)
151 int domain
= pci_domain_nr(dev_priv
->drm
.pdev
->bus
);
153 dev_priv
->bridge_dev
=
154 pci_get_domain_bus_and_slot(domain
, 0, PCI_DEVFN(0, 0));
155 if (!dev_priv
->bridge_dev
) {
156 DRM_ERROR("bridge device not found\n");
162 /* Allocate space for the MCH regs if needed, return nonzero on error */
164 intel_alloc_mchbar_resource(struct drm_i915_private
*dev_priv
)
166 int reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
167 u32 temp_lo
, temp_hi
= 0;
171 if (INTEL_GEN(dev_priv
) >= 4)
172 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
173 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
174 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
176 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
179 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
183 /* Get some space for it */
184 dev_priv
->mch_res
.name
= "i915 MCHBAR";
185 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
186 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
188 MCHBAR_SIZE
, MCHBAR_SIZE
,
190 0, pcibios_align_resource
,
191 dev_priv
->bridge_dev
);
193 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
194 dev_priv
->mch_res
.start
= 0;
198 if (INTEL_GEN(dev_priv
) >= 4)
199 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
200 upper_32_bits(dev_priv
->mch_res
.start
));
202 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
203 lower_32_bits(dev_priv
->mch_res
.start
));
207 /* Setup MCHBAR if possible, return true if we should disable it again */
209 intel_setup_mchbar(struct drm_i915_private
*dev_priv
)
211 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
215 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
218 dev_priv
->mchbar_need_disable
= false;
220 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
221 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
222 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
224 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
228 /* If it's already enabled, don't have to do anything */
232 if (intel_alloc_mchbar_resource(dev_priv
))
235 dev_priv
->mchbar_need_disable
= true;
237 /* Space is allocated or reserved, so enable it. */
238 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
239 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
240 temp
| DEVEN_MCHBAR_EN
);
242 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
243 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
248 intel_teardown_mchbar(struct drm_i915_private
*dev_priv
)
250 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
252 if (dev_priv
->mchbar_need_disable
) {
253 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
256 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
258 deven_val
&= ~DEVEN_MCHBAR_EN
;
259 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
264 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
267 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
272 if (dev_priv
->mch_res
.start
)
273 release_resource(&dev_priv
->mch_res
);
276 static int i915_driver_modeset_probe(struct drm_i915_private
*i915
)
280 if (i915_inject_probe_failure(i915
))
283 if (HAS_DISPLAY(i915
) && INTEL_DISPLAY_ENABLED(i915
)) {
284 ret
= drm_vblank_init(&i915
->drm
,
285 INTEL_NUM_PIPES(i915
));
290 intel_bios_init(i915
);
292 ret
= intel_vga_register(i915
);
296 intel_register_dsm_handler();
298 ret
= i915_switcheroo_register(i915
);
300 goto cleanup_vga_client
;
302 intel_power_domains_init_hw(i915
, false);
304 intel_csr_ucode_init(i915
);
306 ret
= intel_irq_install(i915
);
310 /* Important: The output setup functions called by modeset_init need
311 * working irqs for e.g. gmbus and dp aux transfers. */
312 ret
= intel_modeset_init(i915
);
316 ret
= i915_gem_init(i915
);
318 goto cleanup_modeset
;
320 intel_overlay_setup(i915
);
322 if (!HAS_DISPLAY(i915
) || !INTEL_DISPLAY_ENABLED(i915
))
325 ret
= intel_fbdev_init(&i915
->drm
);
329 /* Only enable hotplug handling once the fbdev is fully set up. */
330 intel_hpd_init(i915
);
332 intel_init_ipc(i915
);
334 intel_psr_set_force_mode_changed(i915
->psr
.dp
);
339 i915_gem_suspend(i915
);
340 i915_gem_driver_remove(i915
);
341 i915_gem_driver_release(i915
);
343 intel_modeset_driver_remove(i915
);
345 intel_irq_uninstall(i915
);
347 intel_csr_ucode_fini(i915
);
348 intel_power_domains_driver_remove(i915
);
349 i915_switcheroo_unregister(i915
);
351 intel_vga_unregister(i915
);
356 static void i915_driver_modeset_remove(struct drm_i915_private
*i915
)
358 intel_modeset_driver_remove(i915
);
360 intel_irq_uninstall(i915
);
362 intel_bios_driver_remove(i915
);
364 i915_switcheroo_unregister(i915
);
366 intel_vga_unregister(i915
);
368 intel_csr_ucode_fini(i915
);
371 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
374 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
375 * CHV x1 PHY (DP/HDMI D)
376 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
378 if (IS_CHERRYVIEW(dev_priv
)) {
379 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
380 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
381 } else if (IS_VALLEYVIEW(dev_priv
)) {
382 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
386 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
389 * The i915 workqueue is primarily used for batched retirement of
390 * requests (and thus managing bo) once the task has been completed
391 * by the GPU. i915_retire_requests() is called directly when we
392 * need high-priority retirement, such as waiting for an explicit
395 * It is also used for periodic low-priority events, such as
396 * idle-timers and recording error state.
398 * All tasks on the workqueue are expected to acquire the dev mutex
399 * so there is no point in running more than one instance of the
400 * workqueue at any time. Use an ordered one.
402 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
403 if (dev_priv
->wq
== NULL
)
406 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
407 if (dev_priv
->hotplug
.dp_wq
== NULL
)
413 destroy_workqueue(dev_priv
->wq
);
415 DRM_ERROR("Failed to allocate workqueues.\n");
420 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
422 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
423 destroy_workqueue(dev_priv
->wq
);
427 * We don't keep the workarounds for pre-production hardware, so we expect our
428 * driver to fail on these machines in one way or another. A little warning on
429 * dmesg may help both the user and the bug triagers.
431 * Our policy for removing pre-production workarounds is to keep the
432 * current gen workarounds as a guide to the bring-up of the next gen
433 * (workarounds have a habit of persisting!). Anything older than that
434 * should be removed along with the complications they introduce.
436 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
440 pre
|= IS_HSW_EARLY_SDV(dev_priv
);
441 pre
|= IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
);
442 pre
|= IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B_LAST
);
443 pre
|= IS_KBL_REVID(dev_priv
, 0, KBL_REVID_A0
);
446 DRM_ERROR("This is a pre-production stepping. "
447 "It may not be fully functional.\n");
448 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_STILL_OK
);
452 static int vlv_alloc_s0ix_state(struct drm_i915_private
*i915
)
454 if (!IS_VALLEYVIEW(i915
))
457 /* we write all the values in the struct, so no need to zero it out */
458 i915
->vlv_s0ix_state
= kmalloc(sizeof(*i915
->vlv_s0ix_state
),
460 if (!i915
->vlv_s0ix_state
)
466 static void vlv_free_s0ix_state(struct drm_i915_private
*i915
)
468 if (!i915
->vlv_s0ix_state
)
471 kfree(i915
->vlv_s0ix_state
);
472 i915
->vlv_s0ix_state
= NULL
;
475 static void sanitize_gpu(struct drm_i915_private
*i915
)
477 if (!INTEL_INFO(i915
)->gpu_reset_clobbers_display
)
478 __intel_gt_reset(&i915
->gt
, ALL_ENGINES
);
482 * i915_driver_early_probe - setup state not requiring device access
483 * @dev_priv: device private
485 * Initialize everything that is a "SW-only" state, that is state not
486 * requiring accessing the device or exposing the driver via kernel internal
487 * or userspace interfaces. Example steps belonging here: lock initialization,
488 * system memory allocation, setting up device specific attributes and
489 * function hooks not requiring accessing the device.
491 static int i915_driver_early_probe(struct drm_i915_private
*dev_priv
)
495 if (i915_inject_probe_failure(dev_priv
))
498 intel_device_info_subplatform_init(dev_priv
);
500 intel_uncore_mmio_debug_init_early(&dev_priv
->mmio_debug
);
501 intel_uncore_init_early(&dev_priv
->uncore
, dev_priv
);
503 spin_lock_init(&dev_priv
->irq_lock
);
504 spin_lock_init(&dev_priv
->gpu_error
.lock
);
505 mutex_init(&dev_priv
->backlight_lock
);
507 mutex_init(&dev_priv
->sb_lock
);
508 pm_qos_add_request(&dev_priv
->sb_qos
,
509 PM_QOS_CPU_DMA_LATENCY
, PM_QOS_DEFAULT_VALUE
);
511 mutex_init(&dev_priv
->av_mutex
);
512 mutex_init(&dev_priv
->wm
.wm_mutex
);
513 mutex_init(&dev_priv
->pps_mutex
);
514 mutex_init(&dev_priv
->hdcp_comp_mutex
);
516 i915_memcpy_init_early(dev_priv
);
517 intel_runtime_pm_init_early(&dev_priv
->runtime_pm
);
519 ret
= i915_workqueues_init(dev_priv
);
523 ret
= vlv_alloc_s0ix_state(dev_priv
);
527 intel_wopcm_init_early(&dev_priv
->wopcm
);
529 intel_gt_init_early(&dev_priv
->gt
, dev_priv
);
531 i915_gem_init_early(dev_priv
);
533 /* This must be called before any calls to HAS_PCH_* */
534 intel_detect_pch(dev_priv
);
536 intel_pm_setup(dev_priv
);
537 intel_init_dpio(dev_priv
);
538 ret
= intel_power_domains_init(dev_priv
);
541 intel_irq_init(dev_priv
);
542 intel_init_display_hooks(dev_priv
);
543 intel_init_clock_gating_hooks(dev_priv
);
544 intel_init_audio_hooks(dev_priv
);
545 intel_display_crc_init(dev_priv
);
547 intel_detect_preproduction_hw(dev_priv
);
552 i915_gem_cleanup_early(dev_priv
);
553 intel_gt_driver_late_release(&dev_priv
->gt
);
554 vlv_free_s0ix_state(dev_priv
);
556 i915_workqueues_cleanup(dev_priv
);
561 * i915_driver_late_release - cleanup the setup done in
562 * i915_driver_early_probe()
563 * @dev_priv: device private
565 static void i915_driver_late_release(struct drm_i915_private
*dev_priv
)
567 intel_irq_fini(dev_priv
);
568 intel_power_domains_cleanup(dev_priv
);
569 i915_gem_cleanup_early(dev_priv
);
570 intel_gt_driver_late_release(&dev_priv
->gt
);
571 vlv_free_s0ix_state(dev_priv
);
572 i915_workqueues_cleanup(dev_priv
);
574 pm_qos_remove_request(&dev_priv
->sb_qos
);
575 mutex_destroy(&dev_priv
->sb_lock
);
579 * i915_driver_mmio_probe - setup device MMIO
580 * @dev_priv: device private
582 * Setup minimal device state necessary for MMIO accesses later in the
583 * initialization sequence. The setup here should avoid any other device-wide
584 * side effects or exposing the driver via kernel internal or user space
587 static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv
)
591 if (i915_inject_probe_failure(dev_priv
))
594 if (i915_get_bridge_dev(dev_priv
))
597 ret
= intel_uncore_init_mmio(&dev_priv
->uncore
);
601 /* Try to make sure MCHBAR is enabled before poking at it */
602 intel_setup_mchbar(dev_priv
);
604 intel_device_info_init_mmio(dev_priv
);
606 intel_uncore_prune_mmio_domains(&dev_priv
->uncore
);
608 intel_uc_init_mmio(&dev_priv
->gt
.uc
);
610 ret
= intel_engines_init_mmio(&dev_priv
->gt
);
614 /* As early as possible, scrub existing GPU state before clobbering */
615 sanitize_gpu(dev_priv
);
620 intel_teardown_mchbar(dev_priv
);
621 intel_uncore_fini_mmio(&dev_priv
->uncore
);
623 pci_dev_put(dev_priv
->bridge_dev
);
629 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
630 * @dev_priv: device private
632 static void i915_driver_mmio_release(struct drm_i915_private
*dev_priv
)
634 intel_teardown_mchbar(dev_priv
);
635 intel_uncore_fini_mmio(&dev_priv
->uncore
);
636 pci_dev_put(dev_priv
->bridge_dev
);
639 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
641 intel_gvt_sanitize_options(dev_priv
);
644 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
646 static const char *intel_dram_type_str(enum intel_dram_type type
)
648 static const char * const str
[] = {
649 DRAM_TYPE_STR(UNKNOWN
),
652 DRAM_TYPE_STR(LPDDR3
),
653 DRAM_TYPE_STR(LPDDR4
),
656 if (type
>= ARRAY_SIZE(str
))
657 type
= INTEL_DRAM_UNKNOWN
;
664 static int intel_dimm_num_devices(const struct dram_dimm_info
*dimm
)
666 return dimm
->ranks
* 64 / (dimm
->width
?: 1);
669 /* Returns total GB for the whole DIMM */
670 static int skl_get_dimm_size(u16 val
)
672 return val
& SKL_DRAM_SIZE_MASK
;
675 static int skl_get_dimm_width(u16 val
)
677 if (skl_get_dimm_size(val
) == 0)
680 switch (val
& SKL_DRAM_WIDTH_MASK
) {
681 case SKL_DRAM_WIDTH_X8
:
682 case SKL_DRAM_WIDTH_X16
:
683 case SKL_DRAM_WIDTH_X32
:
684 val
= (val
& SKL_DRAM_WIDTH_MASK
) >> SKL_DRAM_WIDTH_SHIFT
;
692 static int skl_get_dimm_ranks(u16 val
)
694 if (skl_get_dimm_size(val
) == 0)
697 val
= (val
& SKL_DRAM_RANK_MASK
) >> SKL_DRAM_RANK_SHIFT
;
702 /* Returns total GB for the whole DIMM */
703 static int cnl_get_dimm_size(u16 val
)
705 return (val
& CNL_DRAM_SIZE_MASK
) / 2;
708 static int cnl_get_dimm_width(u16 val
)
710 if (cnl_get_dimm_size(val
) == 0)
713 switch (val
& CNL_DRAM_WIDTH_MASK
) {
714 case CNL_DRAM_WIDTH_X8
:
715 case CNL_DRAM_WIDTH_X16
:
716 case CNL_DRAM_WIDTH_X32
:
717 val
= (val
& CNL_DRAM_WIDTH_MASK
) >> CNL_DRAM_WIDTH_SHIFT
;
725 static int cnl_get_dimm_ranks(u16 val
)
727 if (cnl_get_dimm_size(val
) == 0)
730 val
= (val
& CNL_DRAM_RANK_MASK
) >> CNL_DRAM_RANK_SHIFT
;
736 skl_is_16gb_dimm(const struct dram_dimm_info
*dimm
)
738 /* Convert total GB to Gb per DRAM device */
739 return 8 * dimm
->size
/ (intel_dimm_num_devices(dimm
) ?: 1) == 16;
743 skl_dram_get_dimm_info(struct drm_i915_private
*dev_priv
,
744 struct dram_dimm_info
*dimm
,
745 int channel
, char dimm_name
, u16 val
)
747 if (INTEL_GEN(dev_priv
) >= 10) {
748 dimm
->size
= cnl_get_dimm_size(val
);
749 dimm
->width
= cnl_get_dimm_width(val
);
750 dimm
->ranks
= cnl_get_dimm_ranks(val
);
752 dimm
->size
= skl_get_dimm_size(val
);
753 dimm
->width
= skl_get_dimm_width(val
);
754 dimm
->ranks
= skl_get_dimm_ranks(val
);
757 DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
758 channel
, dimm_name
, dimm
->size
, dimm
->width
, dimm
->ranks
,
759 yesno(skl_is_16gb_dimm(dimm
)));
763 skl_dram_get_channel_info(struct drm_i915_private
*dev_priv
,
764 struct dram_channel_info
*ch
,
765 int channel
, u32 val
)
767 skl_dram_get_dimm_info(dev_priv
, &ch
->dimm_l
,
768 channel
, 'L', val
& 0xffff);
769 skl_dram_get_dimm_info(dev_priv
, &ch
->dimm_s
,
770 channel
, 'S', val
>> 16);
772 if (ch
->dimm_l
.size
== 0 && ch
->dimm_s
.size
== 0) {
773 DRM_DEBUG_KMS("CH%u not populated\n", channel
);
777 if (ch
->dimm_l
.ranks
== 2 || ch
->dimm_s
.ranks
== 2)
779 else if (ch
->dimm_l
.ranks
== 1 && ch
->dimm_s
.ranks
== 1)
785 skl_is_16gb_dimm(&ch
->dimm_l
) ||
786 skl_is_16gb_dimm(&ch
->dimm_s
);
788 DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
789 channel
, ch
->ranks
, yesno(ch
->is_16gb_dimm
));
795 intel_is_dram_symmetric(const struct dram_channel_info
*ch0
,
796 const struct dram_channel_info
*ch1
)
798 return !memcmp(ch0
, ch1
, sizeof(*ch0
)) &&
799 (ch0
->dimm_s
.size
== 0 ||
800 !memcmp(&ch0
->dimm_l
, &ch0
->dimm_s
, sizeof(ch0
->dimm_l
)));
804 skl_dram_get_channels_info(struct drm_i915_private
*dev_priv
)
806 struct dram_info
*dram_info
= &dev_priv
->dram_info
;
807 struct dram_channel_info ch0
= {}, ch1
= {};
811 val
= I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN
);
812 ret
= skl_dram_get_channel_info(dev_priv
, &ch0
, 0, val
);
814 dram_info
->num_channels
++;
816 val
= I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN
);
817 ret
= skl_dram_get_channel_info(dev_priv
, &ch1
, 1, val
);
819 dram_info
->num_channels
++;
821 if (dram_info
->num_channels
== 0) {
822 DRM_INFO("Number of memory channels is zero\n");
827 * If any of the channel is single rank channel, worst case output
828 * will be same as if single rank memory, so consider single rank
831 if (ch0
.ranks
== 1 || ch1
.ranks
== 1)
832 dram_info
->ranks
= 1;
834 dram_info
->ranks
= max(ch0
.ranks
, ch1
.ranks
);
836 if (dram_info
->ranks
== 0) {
837 DRM_INFO("couldn't get memory rank information\n");
841 dram_info
->is_16gb_dimm
= ch0
.is_16gb_dimm
|| ch1
.is_16gb_dimm
;
843 dram_info
->symmetric_memory
= intel_is_dram_symmetric(&ch0
, &ch1
);
845 DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
846 yesno(dram_info
->symmetric_memory
));
850 static enum intel_dram_type
851 skl_get_dram_type(struct drm_i915_private
*dev_priv
)
855 val
= I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN
);
857 switch (val
& SKL_DRAM_DDR_TYPE_MASK
) {
858 case SKL_DRAM_DDR_TYPE_DDR3
:
859 return INTEL_DRAM_DDR3
;
860 case SKL_DRAM_DDR_TYPE_DDR4
:
861 return INTEL_DRAM_DDR4
;
862 case SKL_DRAM_DDR_TYPE_LPDDR3
:
863 return INTEL_DRAM_LPDDR3
;
864 case SKL_DRAM_DDR_TYPE_LPDDR4
:
865 return INTEL_DRAM_LPDDR4
;
868 return INTEL_DRAM_UNKNOWN
;
873 skl_get_dram_info(struct drm_i915_private
*dev_priv
)
875 struct dram_info
*dram_info
= &dev_priv
->dram_info
;
876 u32 mem_freq_khz
, val
;
879 dram_info
->type
= skl_get_dram_type(dev_priv
);
880 DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info
->type
));
882 ret
= skl_dram_get_channels_info(dev_priv
);
886 val
= I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU
);
887 mem_freq_khz
= DIV_ROUND_UP((val
& SKL_REQ_DATA_MASK
) *
888 SKL_MEMORY_FREQ_MULTIPLIER_HZ
, 1000);
890 dram_info
->bandwidth_kbps
= dram_info
->num_channels
*
893 if (dram_info
->bandwidth_kbps
== 0) {
894 DRM_INFO("Couldn't get system memory bandwidth\n");
898 dram_info
->valid
= true;
902 /* Returns Gb per DRAM device */
903 static int bxt_get_dimm_size(u32 val
)
905 switch (val
& BXT_DRAM_SIZE_MASK
) {
906 case BXT_DRAM_SIZE_4GBIT
:
908 case BXT_DRAM_SIZE_6GBIT
:
910 case BXT_DRAM_SIZE_8GBIT
:
912 case BXT_DRAM_SIZE_12GBIT
:
914 case BXT_DRAM_SIZE_16GBIT
:
922 static int bxt_get_dimm_width(u32 val
)
924 if (!bxt_get_dimm_size(val
))
927 val
= (val
& BXT_DRAM_WIDTH_MASK
) >> BXT_DRAM_WIDTH_SHIFT
;
932 static int bxt_get_dimm_ranks(u32 val
)
934 if (!bxt_get_dimm_size(val
))
937 switch (val
& BXT_DRAM_RANK_MASK
) {
938 case BXT_DRAM_RANK_SINGLE
:
940 case BXT_DRAM_RANK_DUAL
:
948 static enum intel_dram_type
bxt_get_dimm_type(u32 val
)
950 if (!bxt_get_dimm_size(val
))
951 return INTEL_DRAM_UNKNOWN
;
953 switch (val
& BXT_DRAM_TYPE_MASK
) {
954 case BXT_DRAM_TYPE_DDR3
:
955 return INTEL_DRAM_DDR3
;
956 case BXT_DRAM_TYPE_LPDDR3
:
957 return INTEL_DRAM_LPDDR3
;
958 case BXT_DRAM_TYPE_DDR4
:
959 return INTEL_DRAM_DDR4
;
960 case BXT_DRAM_TYPE_LPDDR4
:
961 return INTEL_DRAM_LPDDR4
;
964 return INTEL_DRAM_UNKNOWN
;
968 static void bxt_get_dimm_info(struct dram_dimm_info
*dimm
,
971 dimm
->width
= bxt_get_dimm_width(val
);
972 dimm
->ranks
= bxt_get_dimm_ranks(val
);
975 * Size in register is Gb per DRAM device. Convert to total
976 * GB to match the way we report this for non-LP platforms.
978 dimm
->size
= bxt_get_dimm_size(val
) * intel_dimm_num_devices(dimm
) / 8;
982 bxt_get_dram_info(struct drm_i915_private
*dev_priv
)
984 struct dram_info
*dram_info
= &dev_priv
->dram_info
;
986 u32 mem_freq_khz
, val
;
987 u8 num_active_channels
;
990 val
= I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0
);
991 mem_freq_khz
= DIV_ROUND_UP((val
& BXT_REQ_DATA_MASK
) *
992 BXT_MEMORY_FREQ_MULTIPLIER_HZ
, 1000);
994 dram_channels
= val
& BXT_DRAM_CHANNEL_ACTIVE_MASK
;
995 num_active_channels
= hweight32(dram_channels
);
997 /* Each active bit represents 4-byte channel */
998 dram_info
->bandwidth_kbps
= (mem_freq_khz
* num_active_channels
* 4);
1000 if (dram_info
->bandwidth_kbps
== 0) {
1001 DRM_INFO("Couldn't get system memory bandwidth\n");
1006 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1008 for (i
= BXT_D_CR_DRP0_DUNIT_START
; i
<= BXT_D_CR_DRP0_DUNIT_END
; i
++) {
1009 struct dram_dimm_info dimm
;
1010 enum intel_dram_type type
;
1012 val
= I915_READ(BXT_D_CR_DRP0_DUNIT(i
));
1013 if (val
== 0xFFFFFFFF)
1016 dram_info
->num_channels
++;
1018 bxt_get_dimm_info(&dimm
, val
);
1019 type
= bxt_get_dimm_type(val
);
1021 WARN_ON(type
!= INTEL_DRAM_UNKNOWN
&&
1022 dram_info
->type
!= INTEL_DRAM_UNKNOWN
&&
1023 dram_info
->type
!= type
);
1025 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1026 i
- BXT_D_CR_DRP0_DUNIT_START
,
1027 dimm
.size
, dimm
.width
, dimm
.ranks
,
1028 intel_dram_type_str(type
));
1031 * If any of the channel is single rank channel,
1032 * worst case output will be same as if single rank
1033 * memory, so consider single rank memory.
1035 if (dram_info
->ranks
== 0)
1036 dram_info
->ranks
= dimm
.ranks
;
1037 else if (dimm
.ranks
== 1)
1038 dram_info
->ranks
= 1;
1040 if (type
!= INTEL_DRAM_UNKNOWN
)
1041 dram_info
->type
= type
;
1044 if (dram_info
->type
== INTEL_DRAM_UNKNOWN
||
1045 dram_info
->ranks
== 0) {
1046 DRM_INFO("couldn't get memory information\n");
1050 dram_info
->valid
= true;
1055 intel_get_dram_info(struct drm_i915_private
*dev_priv
)
1057 struct dram_info
*dram_info
= &dev_priv
->dram_info
;
1061 * Assume 16Gb DIMMs are present until proven otherwise.
1062 * This is only used for the level 0 watermark latency
1063 * w/a which does not apply to bxt/glk.
1065 dram_info
->is_16gb_dimm
= !IS_GEN9_LP(dev_priv
);
1067 if (INTEL_GEN(dev_priv
) < 9 || !HAS_DISPLAY(dev_priv
))
1070 if (IS_GEN9_LP(dev_priv
))
1071 ret
= bxt_get_dram_info(dev_priv
);
1073 ret
= skl_get_dram_info(dev_priv
);
1077 DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1078 dram_info
->bandwidth_kbps
,
1079 dram_info
->num_channels
);
1081 DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1082 dram_info
->ranks
, yesno(dram_info
->is_16gb_dimm
));
1085 static u32
gen9_edram_size_mb(struct drm_i915_private
*dev_priv
, u32 cap
)
1087 static const u8 ways
[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1088 static const u8 sets
[4] = { 1, 1, 2, 2 };
1090 return EDRAM_NUM_BANKS(cap
) *
1091 ways
[EDRAM_WAYS_IDX(cap
)] *
1092 sets
[EDRAM_SETS_IDX(cap
)];
1095 static void edram_detect(struct drm_i915_private
*dev_priv
)
1099 if (!(IS_HASWELL(dev_priv
) ||
1100 IS_BROADWELL(dev_priv
) ||
1101 INTEL_GEN(dev_priv
) >= 9))
1104 edram_cap
= __raw_uncore_read32(&dev_priv
->uncore
, HSW_EDRAM_CAP
);
1106 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1108 if (!(edram_cap
& EDRAM_ENABLED
))
1112 * The needed capability bits for size calculation are not there with
1113 * pre gen9 so return 128MB always.
1115 if (INTEL_GEN(dev_priv
) < 9)
1116 dev_priv
->edram_size_mb
= 128;
1118 dev_priv
->edram_size_mb
=
1119 gen9_edram_size_mb(dev_priv
, edram_cap
);
1121 dev_info(dev_priv
->drm
.dev
,
1122 "Found %uMB of eDRAM\n", dev_priv
->edram_size_mb
);
1126 * i915_driver_hw_probe - setup state requiring device access
1127 * @dev_priv: device private
1129 * Setup state that requires accessing the device, but doesn't require
1130 * exposing the driver via kernel internal or userspace interfaces.
1132 static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv
)
1134 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1137 if (i915_inject_probe_failure(dev_priv
))
1140 intel_device_info_runtime_init(dev_priv
);
1142 if (HAS_PPGTT(dev_priv
)) {
1143 if (intel_vgpu_active(dev_priv
) &&
1144 !intel_vgpu_has_full_ppgtt(dev_priv
)) {
1145 i915_report_error(dev_priv
,
1146 "incompatible vGPU found, support for isolated ppGTT required\n");
1151 if (HAS_EXECLISTS(dev_priv
)) {
1153 * Older GVT emulation depends upon intercepting CSB mmio,
1154 * which we no longer use, preferring to use the HWSP cache
1157 if (intel_vgpu_active(dev_priv
) &&
1158 !intel_vgpu_has_hwsp_emulation(dev_priv
)) {
1159 i915_report_error(dev_priv
,
1160 "old vGPU host found, support for HWSP emulation required\n");
1165 intel_sanitize_options(dev_priv
);
1167 /* needs to be done before ggtt probe */
1168 edram_detect(dev_priv
);
1170 i915_perf_init(dev_priv
);
1172 ret
= i915_ggtt_probe_hw(dev_priv
);
1176 ret
= drm_fb_helper_remove_conflicting_pci_framebuffers(pdev
, "inteldrmfb");
1180 ret
= i915_ggtt_init_hw(dev_priv
);
1184 ret
= intel_memory_regions_hw_probe(dev_priv
);
1188 intel_gt_init_hw_early(&dev_priv
->gt
, &dev_priv
->ggtt
);
1190 ret
= i915_ggtt_enable_hw(dev_priv
);
1192 DRM_ERROR("failed to enable GGTT\n");
1193 goto err_mem_regions
;
1196 pci_set_master(pdev
);
1199 * We don't have a max segment size, so set it to the max so sg's
1200 * debugging layer doesn't complain
1202 dma_set_max_seg_size(&pdev
->dev
, UINT_MAX
);
1204 /* overlay on gen2 is broken and can't address above 1G */
1205 if (IS_GEN(dev_priv
, 2)) {
1206 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1208 DRM_ERROR("failed to set DMA mask\n");
1210 goto err_mem_regions
;
1214 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1215 * using 32bit addressing, overwriting memory if HWS is located
1218 * The documentation also mentions an issue with undefined
1219 * behaviour if any general state is accessed within a page above 4GB,
1220 * which also needs to be handled carefully.
1222 if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
)) {
1223 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1226 DRM_ERROR("failed to set DMA mask\n");
1228 goto err_mem_regions
;
1232 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1233 PM_QOS_DEFAULT_VALUE
);
1235 intel_gt_init_workarounds(dev_priv
);
1237 /* On the 945G/GM, the chipset reports the MSI capability on the
1238 * integrated graphics even though the support isn't actually there
1239 * according to the published specs. It doesn't appear to function
1240 * correctly in testing on 945G.
1241 * This may be a side effect of MSI having been made available for PEG
1242 * and the registers being closely associated.
1244 * According to chipset errata, on the 965GM, MSI interrupts may
1245 * be lost or delayed, and was defeatured. MSI interrupts seem to
1246 * get lost on g4x as well, and interrupt delivery seems to stay
1247 * properly dead afterwards. So we'll just disable them for all
1248 * pre-gen5 chipsets.
1250 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1251 * interrupts even when in MSI mode. This results in spurious
1252 * interrupt warnings if the legacy irq no. is shared with another
1253 * device. The kernel then disables that interrupt source and so
1254 * prevents the other device from working properly.
1256 if (INTEL_GEN(dev_priv
) >= 5) {
1257 if (pci_enable_msi(pdev
) < 0)
1258 DRM_DEBUG_DRIVER("can't enable MSI");
1261 ret
= intel_gvt_init(dev_priv
);
1265 intel_opregion_setup(dev_priv
);
1267 * Fill the dram structure to get the system raw bandwidth and
1268 * dram info. This will be used for memory latency calculation.
1270 intel_get_dram_info(dev_priv
);
1272 intel_bw_init_hw(dev_priv
);
1277 if (pdev
->msi_enabled
)
1278 pci_disable_msi(pdev
);
1279 pm_qos_remove_request(&dev_priv
->pm_qos
);
1281 intel_memory_regions_driver_release(dev_priv
);
1283 i915_ggtt_driver_release(dev_priv
);
1285 i915_perf_fini(dev_priv
);
1290 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
1291 * @dev_priv: device private
1293 static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv
)
1295 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1297 i915_perf_fini(dev_priv
);
1299 if (pdev
->msi_enabled
)
1300 pci_disable_msi(pdev
);
1302 pm_qos_remove_request(&dev_priv
->pm_qos
);
1306 * i915_driver_register - register the driver with the rest of the system
1307 * @dev_priv: device private
1309 * Perform any steps necessary to make the driver available via kernel
1310 * internal or userspace interfaces.
1312 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1314 struct drm_device
*dev
= &dev_priv
->drm
;
1316 i915_gem_driver_register(dev_priv
);
1317 i915_pmu_register(dev_priv
);
1320 * Notify a valid surface after modesetting,
1321 * when running inside a VM.
1323 if (intel_vgpu_active(dev_priv
))
1324 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1326 /* Reveal our presence to userspace */
1327 if (drm_dev_register(dev
, 0) == 0) {
1328 i915_debugfs_register(dev_priv
);
1329 i915_setup_sysfs(dev_priv
);
1331 /* Depends on sysfs having been initialized */
1332 i915_perf_register(dev_priv
);
1334 DRM_ERROR("Failed to register driver for userspace access!\n");
1336 if (HAS_DISPLAY(dev_priv
) && INTEL_DISPLAY_ENABLED(dev_priv
)) {
1337 /* Must be done after probing outputs */
1338 intel_opregion_register(dev_priv
);
1339 acpi_video_register();
1342 intel_gt_driver_register(&dev_priv
->gt
);
1344 intel_audio_init(dev_priv
);
1347 * Some ports require correctly set-up hpd registers for detection to
1348 * work properly (leading to ghost connected connector status), e.g. VGA
1349 * on gm45. Hence we can only set up the initial fbdev config after hpd
1350 * irqs are fully enabled. We do it last so that the async config
1351 * cannot run before the connectors are registered.
1353 intel_fbdev_initial_config_async(dev
);
1356 * We need to coordinate the hotplugs with the asynchronous fbdev
1357 * configuration, for which we use the fbdev->async_cookie.
1359 if (HAS_DISPLAY(dev_priv
) && INTEL_DISPLAY_ENABLED(dev_priv
))
1360 drm_kms_helper_poll_init(dev
);
1362 intel_power_domains_enable(dev_priv
);
1363 intel_runtime_pm_enable(&dev_priv
->runtime_pm
);
1367 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1368 * @dev_priv: device private
1370 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1372 intel_runtime_pm_disable(&dev_priv
->runtime_pm
);
1373 intel_power_domains_disable(dev_priv
);
1375 intel_fbdev_unregister(dev_priv
);
1376 intel_audio_deinit(dev_priv
);
1379 * After flushing the fbdev (incl. a late async config which will
1380 * have delayed queuing of a hotplug event), then flush the hotplug
1383 drm_kms_helper_poll_fini(&dev_priv
->drm
);
1385 intel_gt_driver_unregister(&dev_priv
->gt
);
1386 acpi_video_unregister();
1387 intel_opregion_unregister(dev_priv
);
1389 i915_perf_unregister(dev_priv
);
1390 i915_pmu_unregister(dev_priv
);
1392 i915_teardown_sysfs(dev_priv
);
1393 drm_dev_unplug(&dev_priv
->drm
);
1395 i915_gem_driver_unregister(dev_priv
);
1398 static void i915_welcome_messages(struct drm_i915_private
*dev_priv
)
1400 if (drm_debug_enabled(DRM_UT_DRIVER
)) {
1401 struct drm_printer p
= drm_debug_printer("i915 device info:");
1403 drm_printf(&p
, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1404 INTEL_DEVID(dev_priv
),
1405 INTEL_REVID(dev_priv
),
1406 intel_platform_name(INTEL_INFO(dev_priv
)->platform
),
1407 intel_subplatform(RUNTIME_INFO(dev_priv
),
1408 INTEL_INFO(dev_priv
)->platform
),
1409 INTEL_GEN(dev_priv
));
1411 intel_device_info_print_static(INTEL_INFO(dev_priv
), &p
);
1412 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv
), &p
);
1415 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
1416 DRM_INFO("DRM_I915_DEBUG enabled\n");
1417 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1418 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1419 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM
))
1420 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1423 static struct drm_i915_private
*
1424 i915_driver_create(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1426 const struct intel_device_info
*match_info
=
1427 (struct intel_device_info
*)ent
->driver_data
;
1428 struct intel_device_info
*device_info
;
1429 struct drm_i915_private
*i915
;
1432 i915
= kzalloc(sizeof(*i915
), GFP_KERNEL
);
1434 return ERR_PTR(-ENOMEM
);
1436 err
= drm_dev_init(&i915
->drm
, &driver
, &pdev
->dev
);
1439 return ERR_PTR(err
);
1442 i915
->drm
.dev_private
= i915
;
1444 i915
->drm
.pdev
= pdev
;
1445 pci_set_drvdata(pdev
, i915
);
1447 /* Setup the write-once "constant" device info */
1448 device_info
= mkwrite_device_info(i915
);
1449 memcpy(device_info
, match_info
, sizeof(*device_info
));
1450 RUNTIME_INFO(i915
)->device_id
= pdev
->device
;
1452 BUG_ON(device_info
->gen
> BITS_PER_TYPE(device_info
->gen_mask
));
1457 static void i915_driver_destroy(struct drm_i915_private
*i915
)
1459 struct pci_dev
*pdev
= i915
->drm
.pdev
;
1461 drm_dev_fini(&i915
->drm
);
1464 /* And make sure we never chase our dangling pointer from pci_dev */
1465 pci_set_drvdata(pdev
, NULL
);
1469 * i915_driver_probe - setup chip and create an initial config
1471 * @ent: matching PCI ID entry
1473 * The driver probe routine has to do several things:
1474 * - drive output discovery via intel_modeset_init()
1475 * - initialize the memory manager
1476 * - allocate initial config memory
1477 * - setup the DRM framebuffer with the allocated memory
1479 int i915_driver_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1481 const struct intel_device_info
*match_info
=
1482 (struct intel_device_info
*)ent
->driver_data
;
1483 struct drm_i915_private
*dev_priv
;
1486 dev_priv
= i915_driver_create(pdev
, ent
);
1487 if (IS_ERR(dev_priv
))
1488 return PTR_ERR(dev_priv
);
1490 /* Disable nuclear pageflip by default on pre-ILK */
1491 if (!i915_modparams
.nuclear_pageflip
&& match_info
->gen
< 5)
1492 dev_priv
->drm
.driver_features
&= ~DRIVER_ATOMIC
;
1495 * Check if we support fake LMEM -- for now we only unleash this for
1496 * the live selftests(test-and-exit).
1498 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1499 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM
)) {
1500 if (INTEL_GEN(dev_priv
) >= 9 && i915_selftest
.live
< 0 &&
1501 i915_modparams
.fake_lmem_start
) {
1502 mkwrite_device_info(dev_priv
)->memory_regions
=
1503 REGION_SMEM
| REGION_LMEM
| REGION_STOLEN
;
1504 mkwrite_device_info(dev_priv
)->is_dgfx
= true;
1505 GEM_BUG_ON(!HAS_LMEM(dev_priv
));
1506 GEM_BUG_ON(!IS_DGFX(dev_priv
));
1511 ret
= pci_enable_device(pdev
);
1515 ret
= i915_driver_early_probe(dev_priv
);
1517 goto out_pci_disable
;
1519 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1521 i915_detect_vgpu(dev_priv
);
1523 ret
= i915_driver_mmio_probe(dev_priv
);
1525 goto out_runtime_pm_put
;
1527 ret
= i915_driver_hw_probe(dev_priv
);
1529 goto out_cleanup_mmio
;
1531 ret
= i915_driver_modeset_probe(dev_priv
);
1533 goto out_cleanup_hw
;
1535 i915_driver_register(dev_priv
);
1537 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1539 i915_welcome_messages(dev_priv
);
1544 i915_driver_hw_remove(dev_priv
);
1545 intel_memory_regions_driver_release(dev_priv
);
1546 i915_ggtt_driver_release(dev_priv
);
1548 i915_driver_mmio_release(dev_priv
);
1550 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1551 i915_driver_late_release(dev_priv
);
1553 pci_disable_device(pdev
);
1555 i915_probe_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1556 i915_driver_destroy(dev_priv
);
1560 void i915_driver_remove(struct drm_i915_private
*i915
)
1562 disable_rpm_wakeref_asserts(&i915
->runtime_pm
);
1564 i915_driver_unregister(i915
);
1567 * After unregistering the device to prevent any new users, cancel
1568 * all in-flight requests so that we can quickly unbind the active
1571 intel_gt_set_wedged(&i915
->gt
);
1573 /* Flush any external code that still may be under the RCU lock */
1576 i915_gem_suspend(i915
);
1578 drm_atomic_helper_shutdown(&i915
->drm
);
1580 intel_gvt_driver_remove(i915
);
1582 i915_driver_modeset_remove(i915
);
1584 i915_reset_error_state(i915
);
1585 i915_gem_driver_remove(i915
);
1587 intel_power_domains_driver_remove(i915
);
1589 i915_driver_hw_remove(i915
);
1591 enable_rpm_wakeref_asserts(&i915
->runtime_pm
);
1594 static void i915_driver_release(struct drm_device
*dev
)
1596 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1597 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
1599 disable_rpm_wakeref_asserts(rpm
);
1601 i915_gem_driver_release(dev_priv
);
1603 intel_memory_regions_driver_release(dev_priv
);
1604 i915_ggtt_driver_release(dev_priv
);
1606 i915_driver_mmio_release(dev_priv
);
1608 enable_rpm_wakeref_asserts(rpm
);
1609 intel_runtime_pm_driver_release(rpm
);
1611 i915_driver_late_release(dev_priv
);
1612 i915_driver_destroy(dev_priv
);
1615 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1617 struct drm_i915_private
*i915
= to_i915(dev
);
1620 ret
= i915_gem_open(i915
, file
);
1628 * i915_driver_lastclose - clean up after all DRM clients have exited
1631 * Take care of cleaning up after all DRM clients have exited. In the
1632 * mode setting case, we want to restore the kernel's initial mode (just
1633 * in case the last client left us in a bad state).
1635 * Additionally, in the non-mode setting case, we'll tear down the GTT
1636 * and DMA structures, since the kernel won't be using them, and clea
1639 static void i915_driver_lastclose(struct drm_device
*dev
)
1641 intel_fbdev_restore_mode(dev
);
1642 vga_switcheroo_process_delayed_switch();
1645 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1647 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1649 i915_gem_context_close(file
);
1650 i915_gem_release(dev
, file
);
1652 kfree_rcu(file_priv
, rcu
);
1654 /* Catch up with all the deferred frees from "this" client */
1655 i915_gem_flush_free_objects(to_i915(dev
));
1658 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1660 struct drm_device
*dev
= &dev_priv
->drm
;
1661 struct intel_encoder
*encoder
;
1663 drm_modeset_lock_all(dev
);
1664 for_each_intel_encoder(dev
, encoder
)
1665 if (encoder
->suspend
)
1666 encoder
->suspend(encoder
);
1667 drm_modeset_unlock_all(dev
);
1670 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1672 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1674 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1676 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1677 if (acpi_target_system_state() < ACPI_STATE_S3
)
1683 static int i915_drm_prepare(struct drm_device
*dev
)
1685 struct drm_i915_private
*i915
= to_i915(dev
);
1688 * NB intel_display_suspend() may issue new requests after we've
1689 * ostensibly marked the GPU as ready-to-sleep here. We need to
1690 * split out that work and pull it forward so that after point,
1691 * the GPU is not woken again.
1693 i915_gem_suspend(i915
);
1698 static int i915_drm_suspend(struct drm_device
*dev
)
1700 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1701 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1702 pci_power_t opregion_target_state
;
1704 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1706 /* We do a lot of poking in a lot of registers, make sure they work
1708 intel_power_domains_disable(dev_priv
);
1710 drm_kms_helper_poll_disable(dev
);
1712 pci_save_state(pdev
);
1714 intel_display_suspend(dev
);
1716 intel_dp_mst_suspend(dev_priv
);
1718 intel_runtime_pm_disable_interrupts(dev_priv
);
1719 intel_hpd_cancel_work(dev_priv
);
1721 intel_suspend_encoders(dev_priv
);
1723 intel_suspend_hw(dev_priv
);
1725 i915_gem_suspend_gtt_mappings(dev_priv
);
1727 i915_save_state(dev_priv
);
1729 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1730 intel_opregion_suspend(dev_priv
, opregion_target_state
);
1732 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1734 dev_priv
->suspend_count
++;
1736 intel_csr_ucode_suspend(dev_priv
);
1738 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1743 static enum i915_drm_suspend_mode
1744 get_suspend_mode(struct drm_i915_private
*dev_priv
, bool hibernate
)
1747 return I915_DRM_SUSPEND_HIBERNATE
;
1749 if (suspend_to_idle(dev_priv
))
1750 return I915_DRM_SUSPEND_IDLE
;
1752 return I915_DRM_SUSPEND_MEM
;
1755 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1757 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1758 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1759 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
1762 disable_rpm_wakeref_asserts(rpm
);
1764 i915_gem_suspend_late(dev_priv
);
1766 intel_uncore_suspend(&dev_priv
->uncore
);
1768 intel_power_domains_suspend(dev_priv
,
1769 get_suspend_mode(dev_priv
, hibernation
));
1771 intel_display_power_suspend_late(dev_priv
);
1773 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1774 ret
= vlv_suspend_complete(dev_priv
);
1777 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1778 intel_power_domains_resume(dev_priv
);
1783 pci_disable_device(pdev
);
1785 * During hibernation on some platforms the BIOS may try to access
1786 * the device even though it's already in D3 and hang the machine. So
1787 * leave the device in D0 on those platforms and hope the BIOS will
1788 * power down the device properly. The issue was seen on multiple old
1789 * GENs with different BIOS vendors, so having an explicit blacklist
1790 * is inpractical; apply the workaround on everything pre GEN6. The
1791 * platforms where the issue was seen:
1792 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1796 if (!(hibernation
&& INTEL_GEN(dev_priv
) < 6))
1797 pci_set_power_state(pdev
, PCI_D3hot
);
1800 enable_rpm_wakeref_asserts(rpm
);
1801 if (!dev_priv
->uncore
.user_forcewake_count
)
1802 intel_runtime_pm_driver_release(rpm
);
1807 int i915_suspend_switcheroo(struct drm_i915_private
*i915
, pm_message_t state
)
1811 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1812 state
.event
!= PM_EVENT_FREEZE
))
1815 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1818 error
= i915_drm_suspend(&i915
->drm
);
1822 return i915_drm_suspend_late(&i915
->drm
, false);
1825 static int i915_drm_resume(struct drm_device
*dev
)
1827 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1830 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1832 sanitize_gpu(dev_priv
);
1834 ret
= i915_ggtt_enable_hw(dev_priv
);
1836 DRM_ERROR("failed to re-enable GGTT\n");
1838 i915_gem_restore_gtt_mappings(dev_priv
);
1839 i915_gem_restore_fences(&dev_priv
->ggtt
);
1841 intel_csr_ucode_resume(dev_priv
);
1843 i915_restore_state(dev_priv
);
1844 intel_pps_unlock_regs_wa(dev_priv
);
1846 intel_init_pch_refclk(dev_priv
);
1849 * Interrupts have to be enabled before any batches are run. If not the
1850 * GPU will hang. i915_gem_init_hw() will initiate batches to
1851 * update/restore the context.
1853 * drm_mode_config_reset() needs AUX interrupts.
1855 * Modeset enabling in intel_modeset_init_hw() also needs working
1858 intel_runtime_pm_enable_interrupts(dev_priv
);
1860 drm_mode_config_reset(dev
);
1862 i915_gem_resume(dev_priv
);
1864 intel_modeset_init_hw(dev_priv
);
1865 intel_init_clock_gating(dev_priv
);
1867 spin_lock_irq(&dev_priv
->irq_lock
);
1868 if (dev_priv
->display
.hpd_irq_setup
)
1869 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1870 spin_unlock_irq(&dev_priv
->irq_lock
);
1872 intel_dp_mst_resume(dev_priv
);
1874 intel_display_resume(dev
);
1876 drm_kms_helper_poll_enable(dev
);
1879 * ... but also need to make sure that hotplug processing
1880 * doesn't cause havoc. Like in the driver load code we don't
1881 * bother with the tiny race here where we might lose hotplug
1884 intel_hpd_init(dev_priv
);
1886 intel_opregion_resume(dev_priv
);
1888 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1890 intel_power_domains_enable(dev_priv
);
1892 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1897 static int i915_drm_resume_early(struct drm_device
*dev
)
1899 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1900 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1904 * We have a resume ordering issue with the snd-hda driver also
1905 * requiring our device to be power up. Due to the lack of a
1906 * parent/child relationship we currently solve this with an early
1909 * FIXME: This should be solved with a special hdmi sink device or
1910 * similar so that power domains can be employed.
1914 * Note that we need to set the power state explicitly, since we
1915 * powered off the device during freeze and the PCI core won't power
1916 * it back up for us during thaw. Powering off the device during
1917 * freeze is not a hard requirement though, and during the
1918 * suspend/resume phases the PCI core makes sure we get here with the
1919 * device powered on. So in case we change our freeze logic and keep
1920 * the device powered we can also remove the following set power state
1923 ret
= pci_set_power_state(pdev
, PCI_D0
);
1925 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1930 * Note that pci_enable_device() first enables any parent bridge
1931 * device and only then sets the power state for this device. The
1932 * bridge enabling is a nop though, since bridge devices are resumed
1933 * first. The order of enabling power and enabling the device is
1934 * imposed by the PCI core as described above, so here we preserve the
1935 * same order for the freeze/thaw phases.
1937 * TODO: eventually we should remove pci_disable_device() /
1938 * pci_enable_enable_device() from suspend/resume. Due to how they
1939 * depend on the device enable refcount we can't anyway depend on them
1940 * disabling/enabling the device.
1942 if (pci_enable_device(pdev
))
1945 pci_set_master(pdev
);
1947 disable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1949 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1950 ret
= vlv_resume_prepare(dev_priv
, false);
1952 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1955 intel_uncore_resume_early(&dev_priv
->uncore
);
1957 intel_gt_check_and_clear_faults(&dev_priv
->gt
);
1959 intel_display_power_resume_early(dev_priv
);
1961 intel_power_domains_resume(dev_priv
);
1963 enable_rpm_wakeref_asserts(&dev_priv
->runtime_pm
);
1968 int i915_resume_switcheroo(struct drm_i915_private
*i915
)
1972 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1975 ret
= i915_drm_resume_early(&i915
->drm
);
1979 return i915_drm_resume(&i915
->drm
);
1982 static int i915_pm_prepare(struct device
*kdev
)
1984 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
1987 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
1991 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
1994 return i915_drm_prepare(&i915
->drm
);
1997 static int i915_pm_suspend(struct device
*kdev
)
1999 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
2002 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
2006 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
2009 return i915_drm_suspend(&i915
->drm
);
2012 static int i915_pm_suspend_late(struct device
*kdev
)
2014 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
2017 * We have a suspend ordering issue with the snd-hda driver also
2018 * requiring our device to be power up. Due to the lack of a
2019 * parent/child relationship we currently solve this with an late
2022 * FIXME: This should be solved with a special hdmi sink device or
2023 * similar so that power domains can be employed.
2025 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
2028 return i915_drm_suspend_late(&i915
->drm
, false);
2031 static int i915_pm_poweroff_late(struct device
*kdev
)
2033 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
2035 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
2038 return i915_drm_suspend_late(&i915
->drm
, true);
2041 static int i915_pm_resume_early(struct device
*kdev
)
2043 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
2045 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
2048 return i915_drm_resume_early(&i915
->drm
);
2051 static int i915_pm_resume(struct device
*kdev
)
2053 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
2055 if (i915
->drm
.switch_power_state
== DRM_SWITCH_POWER_OFF
)
2058 return i915_drm_resume(&i915
->drm
);
2061 /* freeze: before creating the hibernation_image */
2062 static int i915_pm_freeze(struct device
*kdev
)
2064 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
2067 if (i915
->drm
.switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
2068 ret
= i915_drm_suspend(&i915
->drm
);
2073 ret
= i915_gem_freeze(i915
);
2080 static int i915_pm_freeze_late(struct device
*kdev
)
2082 struct drm_i915_private
*i915
= kdev_to_i915(kdev
);
2085 if (i915
->drm
.switch_power_state
!= DRM_SWITCH_POWER_OFF
) {
2086 ret
= i915_drm_suspend_late(&i915
->drm
, true);
2091 ret
= i915_gem_freeze_late(i915
);
2098 /* thaw: called after creating the hibernation image, but before turning off. */
2099 static int i915_pm_thaw_early(struct device
*kdev
)
2101 return i915_pm_resume_early(kdev
);
2104 static int i915_pm_thaw(struct device
*kdev
)
2106 return i915_pm_resume(kdev
);
2109 /* restore: called after loading the hibernation image. */
2110 static int i915_pm_restore_early(struct device
*kdev
)
2112 return i915_pm_resume_early(kdev
);
2115 static int i915_pm_restore(struct device
*kdev
)
2117 return i915_pm_resume(kdev
);
2121 * Save all Gunit registers that may be lost after a D3 and a subsequent
2122 * S0i[R123] transition. The list of registers needing a save/restore is
2123 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2124 * registers in the following way:
2125 * - Driver: saved/restored by the driver
2126 * - Punit : saved/restored by the Punit firmware
2127 * - No, w/o marking: no need to save/restore, since the register is R/O or
2128 * used internally by the HW in a way that doesn't depend
2129 * keeping the content across a suspend/resume.
2130 * - Debug : used for debugging
2132 * We save/restore all registers marked with 'Driver', with the following
2134 * - Registers out of use, including also registers marked with 'Debug'.
2135 * These have no effect on the driver's operation, so we don't save/restore
2136 * them to reduce the overhead.
2137 * - Registers that are fully setup by an initialization function called from
2138 * the resume path. For example many clock gating and RPS/RC6 registers.
2139 * - Registers that provide the right functionality with their reset defaults.
2141 * TODO: Except for registers that based on the above 3 criteria can be safely
2142 * ignored, we save/restore all others, practically treating the HW context as
2143 * a black-box for the driver. Further investigation is needed to reduce the
2144 * saved/restored registers even further, by following the same 3 criteria.
2146 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2148 struct vlv_s0ix_state
*s
= dev_priv
->vlv_s0ix_state
;
2154 /* GAM 0x4000-0x4770 */
2155 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
2156 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
2157 s
->arb_mode
= I915_READ(ARB_MODE
);
2158 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
2159 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
2161 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2162 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
2164 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
2165 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
2167 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
2168 s
->ecochk
= I915_READ(GAM_ECOCHK
);
2169 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
2170 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
2172 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
2174 /* MBC 0x9024-0x91D0, 0x8500 */
2175 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
2176 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
2177 s
->mbctl
= I915_READ(GEN6_MBCTL
);
2179 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2180 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2181 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2182 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2183 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2184 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2185 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2187 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2188 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2189 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2190 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2191 s
->ecobus
= I915_READ(ECOBUS
);
2192 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2193 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2194 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2195 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2196 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2197 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2199 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2200 s
->gt_imr
= I915_READ(GTIMR
);
2201 s
->gt_ier
= I915_READ(GTIER
);
2202 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2203 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2205 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2206 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2208 /* GT SA CZ domain, 0x100000-0x138124 */
2209 s
->tilectl
= I915_READ(TILECTL
);
2210 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2211 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2212 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2213 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2215 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2216 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2217 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2218 s
->pcbr
= I915_READ(VLV_PCBR
);
2219 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2222 * Not saving any of:
2223 * DFT, 0x9800-0x9EC0
2224 * SARB, 0xB000-0xB1FC
2225 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2230 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2232 struct vlv_s0ix_state
*s
= dev_priv
->vlv_s0ix_state
;
2239 /* GAM 0x4000-0x4770 */
2240 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2241 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2242 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2243 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2244 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2246 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2247 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2249 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2250 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2252 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2253 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2254 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2255 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2257 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2259 /* MBC 0x9024-0x91D0, 0x8500 */
2260 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2261 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2262 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2264 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2265 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2266 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2267 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2268 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2269 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2270 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2272 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2273 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2274 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2275 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2276 I915_WRITE(ECOBUS
, s
->ecobus
);
2277 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2278 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2279 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2280 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2281 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2282 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2284 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2285 I915_WRITE(GTIMR
, s
->gt_imr
);
2286 I915_WRITE(GTIER
, s
->gt_ier
);
2287 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2288 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2290 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2291 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2293 /* GT SA CZ domain, 0x100000-0x138124 */
2294 I915_WRITE(TILECTL
, s
->tilectl
);
2295 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2297 * Preserve the GT allow wake and GFX force clock bit, they are not
2298 * be restored, as they are used to control the s0ix suspend/resume
2299 * sequence by the caller.
2301 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2302 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2303 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2304 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2306 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2307 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2308 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2309 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2311 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2313 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2314 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2315 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2316 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2317 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2320 static int vlv_wait_for_pw_status(struct drm_i915_private
*i915
,
2323 i915_reg_t reg
= VLV_GTLC_PW_STATUS
;
2327 /* The HW does not like us polling for PW_STATUS frequently, so
2328 * use the sleeping loop rather than risk the busy spin within
2329 * intel_wait_for_register().
2331 * Transitioning between RC6 states should be at most 2ms (see
2332 * valleyview_enable_rps) so use a 3ms timeout.
2334 ret
= wait_for(((reg_value
=
2335 intel_uncore_read_notrace(&i915
->uncore
, reg
)) & mask
)
2338 /* just trace the final value */
2339 trace_i915_reg_rw(false, reg
, reg_value
, sizeof(reg_value
), true);
2344 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2349 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2350 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2352 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2353 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2358 err
= intel_wait_for_register(&dev_priv
->uncore
,
2359 VLV_GTLC_SURVIVABILITY_REG
,
2360 VLV_GFX_CLK_STATUS_BIT
,
2361 VLV_GFX_CLK_STATUS_BIT
,
2364 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2365 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2370 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2376 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2377 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2379 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2380 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2381 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2383 mask
= VLV_GTLC_ALLOWWAKEACK
;
2384 val
= allow
? mask
: 0;
2386 err
= vlv_wait_for_pw_status(dev_priv
, mask
, val
);
2388 DRM_ERROR("timeout disabling GT waking\n");
2393 static void vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2399 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2400 val
= wait_for_on
? mask
: 0;
2403 * RC6 transitioning can be delayed up to 2 msec (see
2404 * valleyview_enable_rps), use 3 msec for safety.
2406 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2407 * reset and we are trying to force the machine to sleep.
2409 if (vlv_wait_for_pw_status(dev_priv
, mask
, val
))
2410 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2411 onoff(wait_for_on
));
2414 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2416 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2419 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2420 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2423 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2429 * Bspec defines the following GT well on flags as debug only, so
2430 * don't treat them as hard failures.
2432 vlv_wait_for_gt_wells(dev_priv
, false);
2434 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2435 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2437 vlv_check_no_gt_access(dev_priv
);
2439 err
= vlv_force_gfx_clock(dev_priv
, true);
2443 err
= vlv_allow_gt_wake(dev_priv
, false);
2447 vlv_save_gunit_s0ix_state(dev_priv
);
2449 err
= vlv_force_gfx_clock(dev_priv
, false);
2456 /* For safety always re-enable waking and disable gfx clock forcing */
2457 vlv_allow_gt_wake(dev_priv
, true);
2459 vlv_force_gfx_clock(dev_priv
, false);
2464 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2471 * If any of the steps fail just try to continue, that's the best we
2472 * can do at this point. Return the first error code (which will also
2473 * leave RPM permanently disabled).
2475 ret
= vlv_force_gfx_clock(dev_priv
, true);
2477 vlv_restore_gunit_s0ix_state(dev_priv
);
2479 err
= vlv_allow_gt_wake(dev_priv
, true);
2483 err
= vlv_force_gfx_clock(dev_priv
, false);
2487 vlv_check_no_gt_access(dev_priv
);
2490 intel_init_clock_gating(dev_priv
);
2495 static int intel_runtime_suspend(struct device
*kdev
)
2497 struct drm_i915_private
*dev_priv
= kdev_to_i915(kdev
);
2498 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
2501 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2504 DRM_DEBUG_KMS("Suspending device\n");
2506 disable_rpm_wakeref_asserts(rpm
);
2509 * We are safe here against re-faults, since the fault handler takes
2512 i915_gem_runtime_suspend(dev_priv
);
2514 intel_gt_runtime_suspend(&dev_priv
->gt
);
2516 intel_runtime_pm_disable_interrupts(dev_priv
);
2518 intel_uncore_suspend(&dev_priv
->uncore
);
2520 intel_display_power_suspend(dev_priv
);
2522 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2523 ret
= vlv_suspend_complete(dev_priv
);
2526 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2527 intel_uncore_runtime_resume(&dev_priv
->uncore
);
2529 intel_runtime_pm_enable_interrupts(dev_priv
);
2531 intel_gt_runtime_resume(&dev_priv
->gt
);
2533 i915_gem_restore_fences(&dev_priv
->ggtt
);
2535 enable_rpm_wakeref_asserts(rpm
);
2540 enable_rpm_wakeref_asserts(rpm
);
2541 intel_runtime_pm_driver_release(rpm
);
2543 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv
->uncore
))
2544 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2546 rpm
->suspended
= true;
2549 * FIXME: We really should find a document that references the arguments
2552 if (IS_BROADWELL(dev_priv
)) {
2554 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2555 * being detected, and the call we do at intel_runtime_resume()
2556 * won't be able to restore them. Since PCI_D3hot matches the
2557 * actual specification and appears to be working, use it.
2559 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2562 * current versions of firmware which depend on this opregion
2563 * notification have repurposed the D1 definition to mean
2564 * "runtime suspended" vs. what you would normally expect (D3)
2565 * to distinguish it from notifications that might be sent via
2568 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2571 assert_forcewakes_inactive(&dev_priv
->uncore
);
2573 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2574 intel_hpd_poll_init(dev_priv
);
2576 DRM_DEBUG_KMS("Device suspended\n");
2580 static int intel_runtime_resume(struct device
*kdev
)
2582 struct drm_i915_private
*dev_priv
= kdev_to_i915(kdev
);
2583 struct intel_runtime_pm
*rpm
= &dev_priv
->runtime_pm
;
2586 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2589 DRM_DEBUG_KMS("Resuming device\n");
2591 WARN_ON_ONCE(atomic_read(&rpm
->wakeref_count
));
2592 disable_rpm_wakeref_asserts(rpm
);
2594 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2595 rpm
->suspended
= false;
2596 if (intel_uncore_unclaimed_mmio(&dev_priv
->uncore
))
2597 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2599 intel_display_power_resume(dev_priv
);
2601 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
2602 ret
= vlv_resume_prepare(dev_priv
, true);
2604 intel_uncore_runtime_resume(&dev_priv
->uncore
);
2606 intel_runtime_pm_enable_interrupts(dev_priv
);
2609 * No point of rolling back things in case of an error, as the best
2610 * we can do is to hope that things will still work (and disable RPM).
2612 intel_gt_runtime_resume(&dev_priv
->gt
);
2613 i915_gem_restore_fences(&dev_priv
->ggtt
);
2616 * On VLV/CHV display interrupts are part of the display
2617 * power well, so hpd is reinitialized from there. For
2618 * everyone else do it here.
2620 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2621 intel_hpd_init(dev_priv
);
2623 intel_enable_ipc(dev_priv
);
2625 enable_rpm_wakeref_asserts(rpm
);
2628 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2630 DRM_DEBUG_KMS("Device resumed\n");
2635 const struct dev_pm_ops i915_pm_ops
= {
2637 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2640 .prepare
= i915_pm_prepare
,
2641 .suspend
= i915_pm_suspend
,
2642 .suspend_late
= i915_pm_suspend_late
,
2643 .resume_early
= i915_pm_resume_early
,
2644 .resume
= i915_pm_resume
,
2648 * @freeze, @freeze_late : called (1) before creating the
2649 * hibernation image [PMSG_FREEZE] and
2650 * (2) after rebooting, before restoring
2651 * the image [PMSG_QUIESCE]
2652 * @thaw, @thaw_early : called (1) after creating the hibernation
2653 * image, before writing it [PMSG_THAW]
2654 * and (2) after failing to create or
2655 * restore the image [PMSG_RECOVER]
2656 * @poweroff, @poweroff_late: called after writing the hibernation
2657 * image, before rebooting [PMSG_HIBERNATE]
2658 * @restore, @restore_early : called after rebooting and restoring the
2659 * hibernation image [PMSG_RESTORE]
2661 .freeze
= i915_pm_freeze
,
2662 .freeze_late
= i915_pm_freeze_late
,
2663 .thaw_early
= i915_pm_thaw_early
,
2664 .thaw
= i915_pm_thaw
,
2665 .poweroff
= i915_pm_suspend
,
2666 .poweroff_late
= i915_pm_poweroff_late
,
2667 .restore_early
= i915_pm_restore_early
,
2668 .restore
= i915_pm_restore
,
2670 /* S0ix (via runtime suspend) event handlers */
2671 .runtime_suspend
= intel_runtime_suspend
,
2672 .runtime_resume
= intel_runtime_resume
,
2675 static const struct file_operations i915_driver_fops
= {
2676 .owner
= THIS_MODULE
,
2678 .release
= drm_release
,
2679 .unlocked_ioctl
= drm_ioctl
,
2680 .mmap
= i915_gem_mmap
,
2683 .compat_ioctl
= i915_compat_ioctl
,
2684 .llseek
= noop_llseek
,
2688 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2689 struct drm_file
*file
)
2694 static const struct drm_ioctl_desc i915_ioctls
[] = {
2695 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2696 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2697 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2698 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2699 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2700 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2701 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam_ioctl
, DRM_RENDER_ALLOW
),
2702 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2703 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2704 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2705 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2706 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2707 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2708 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2709 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2710 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2711 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2712 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2713 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer_ioctl
, DRM_AUTH
),
2714 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR
, i915_gem_execbuffer2_ioctl
, DRM_RENDER_ALLOW
),
2715 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2716 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2717 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_RENDER_ALLOW
),
2718 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2719 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2720 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_RENDER_ALLOW
),
2721 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2722 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2723 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2724 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2725 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2726 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2727 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET
, i915_gem_mmap_offset_ioctl
, DRM_RENDER_ALLOW
),
2728 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2729 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2730 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
2731 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
2732 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2733 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id_ioctl
, 0),
2734 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2735 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
),
2736 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
),
2737 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey_ioctl
, DRM_MASTER
),
2738 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
),
2739 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_RENDER_ALLOW
),
2740 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2741 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2742 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2743 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2744 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2745 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2746 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2747 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
2748 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG
, i915_perf_add_config_ioctl
, DRM_RENDER_ALLOW
),
2749 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG
, i915_perf_remove_config_ioctl
, DRM_RENDER_ALLOW
),
2750 DRM_IOCTL_DEF_DRV(I915_QUERY
, i915_query_ioctl
, DRM_RENDER_ALLOW
),
2751 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE
, i915_gem_vm_create_ioctl
, DRM_RENDER_ALLOW
),
2752 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY
, i915_gem_vm_destroy_ioctl
, DRM_RENDER_ALLOW
),
2755 static struct drm_driver driver
= {
2756 /* Don't use MTRRs here; the Xserver or userspace app should
2757 * deal with them for Intel hardware.
2761 DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_ATOMIC
| DRIVER_SYNCOBJ
,
2762 .release
= i915_driver_release
,
2763 .open
= i915_driver_open
,
2764 .lastclose
= i915_driver_lastclose
,
2765 .postclose
= i915_driver_postclose
,
2767 .gem_close_object
= i915_gem_close_object
,
2768 .gem_free_object_unlocked
= i915_gem_free_object
,
2770 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2771 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2772 .gem_prime_export
= i915_gem_prime_export
,
2773 .gem_prime_import
= i915_gem_prime_import
,
2775 .get_vblank_timestamp
= drm_calc_vbltimestamp_from_scanoutpos
,
2776 .get_scanout_position
= i915_get_crtc_scanoutpos
,
2778 .dumb_create
= i915_gem_dumb_create
,
2779 .dumb_map_offset
= i915_gem_dumb_mmap_offset
,
2781 .ioctls
= i915_ioctls
,
2782 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2783 .fops
= &i915_driver_fops
,
2784 .name
= DRIVER_NAME
,
2785 .desc
= DRIVER_DESC
,
2786 .date
= DRIVER_DATE
,
2787 .major
= DRIVER_MAJOR
,
2788 .minor
= DRIVER_MINOR
,
2789 .patchlevel
= DRIVER_PATCHLEVEL
,