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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include "drm_crtc_helper.h"
39
40 static int i915_modeset = -1;
41 module_param_named(modeset, i915_modeset, int, 0400);
42
43 unsigned int i915_fbpercrtc = 0;
44 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
45
46 unsigned int i915_powersave = 1;
47 module_param_named(powersave, i915_powersave, int, 0600);
48
49 unsigned int i915_semaphores = 0;
50 module_param_named(semaphores, i915_semaphores, int, 0600);
51
52 unsigned int i915_enable_rc6 = 0;
53 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
54
55 unsigned int i915_lvds_downclock = 0;
56 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
57
58 unsigned int i915_panel_use_ssc = 1;
59 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
60
61 bool i915_try_reset = true;
62 module_param_named(reset, i915_try_reset, bool, 0600);
63
64 static struct drm_driver driver;
65 extern int intel_agp_enabled;
66
67 #define INTEL_VGA_DEVICE(id, info) { \
68 .class = PCI_CLASS_DISPLAY_VGA << 8, \
69 .class_mask = 0xff0000, \
70 .vendor = 0x8086, \
71 .device = id, \
72 .subvendor = PCI_ANY_ID, \
73 .subdevice = PCI_ANY_ID, \
74 .driver_data = (unsigned long) info }
75
76 static const struct intel_device_info intel_i830_info = {
77 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
78 .has_overlay = 1, .overlay_needs_physical = 1,
79 };
80
81 static const struct intel_device_info intel_845g_info = {
82 .gen = 2,
83 .has_overlay = 1, .overlay_needs_physical = 1,
84 };
85
86 static const struct intel_device_info intel_i85x_info = {
87 .gen = 2, .is_i85x = 1, .is_mobile = 1,
88 .cursor_needs_physical = 1,
89 .has_overlay = 1, .overlay_needs_physical = 1,
90 };
91
92 static const struct intel_device_info intel_i865g_info = {
93 .gen = 2,
94 .has_overlay = 1, .overlay_needs_physical = 1,
95 };
96
97 static const struct intel_device_info intel_i915g_info = {
98 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
99 .has_overlay = 1, .overlay_needs_physical = 1,
100 };
101 static const struct intel_device_info intel_i915gm_info = {
102 .gen = 3, .is_mobile = 1,
103 .cursor_needs_physical = 1,
104 .has_overlay = 1, .overlay_needs_physical = 1,
105 .supports_tv = 1,
106 };
107 static const struct intel_device_info intel_i945g_info = {
108 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
109 .has_overlay = 1, .overlay_needs_physical = 1,
110 };
111 static const struct intel_device_info intel_i945gm_info = {
112 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
113 .has_hotplug = 1, .cursor_needs_physical = 1,
114 .has_overlay = 1, .overlay_needs_physical = 1,
115 .supports_tv = 1,
116 };
117
118 static const struct intel_device_info intel_i965g_info = {
119 .gen = 4, .is_broadwater = 1,
120 .has_hotplug = 1,
121 .has_overlay = 1,
122 };
123
124 static const struct intel_device_info intel_i965gm_info = {
125 .gen = 4, .is_crestline = 1,
126 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
127 .has_overlay = 1,
128 .supports_tv = 1,
129 };
130
131 static const struct intel_device_info intel_g33_info = {
132 .gen = 3, .is_g33 = 1,
133 .need_gfx_hws = 1, .has_hotplug = 1,
134 .has_overlay = 1,
135 };
136
137 static const struct intel_device_info intel_g45_info = {
138 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
139 .has_pipe_cxsr = 1, .has_hotplug = 1,
140 .has_bsd_ring = 1,
141 };
142
143 static const struct intel_device_info intel_gm45_info = {
144 .gen = 4, .is_g4x = 1,
145 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
146 .has_pipe_cxsr = 1, .has_hotplug = 1,
147 .supports_tv = 1,
148 .has_bsd_ring = 1,
149 };
150
151 static const struct intel_device_info intel_pineview_info = {
152 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
153 .need_gfx_hws = 1, .has_hotplug = 1,
154 .has_overlay = 1,
155 };
156
157 static const struct intel_device_info intel_ironlake_d_info = {
158 .gen = 5,
159 .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
160 .has_bsd_ring = 1,
161 };
162
163 static const struct intel_device_info intel_ironlake_m_info = {
164 .gen = 5, .is_mobile = 1,
165 .need_gfx_hws = 1, .has_hotplug = 1,
166 .has_fbc = 0, /* disabled due to buggy hardware */
167 .has_bsd_ring = 1,
168 };
169
170 static const struct intel_device_info intel_sandybridge_d_info = {
171 .gen = 6,
172 .need_gfx_hws = 1, .has_hotplug = 1,
173 .has_bsd_ring = 1,
174 .has_blt_ring = 1,
175 };
176
177 static const struct intel_device_info intel_sandybridge_m_info = {
178 .gen = 6, .is_mobile = 1,
179 .need_gfx_hws = 1, .has_hotplug = 1,
180 .has_fbc = 1,
181 .has_bsd_ring = 1,
182 .has_blt_ring = 1,
183 };
184
185 static const struct pci_device_id pciidlist[] = { /* aka */
186 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
187 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
188 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
189 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
190 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
191 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
192 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
193 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
194 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
195 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
196 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
197 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
198 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
199 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
200 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
201 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
202 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
203 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
204 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
205 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
206 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
207 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
208 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
209 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
210 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
211 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
212 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
213 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
214 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
215 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
216 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
217 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
218 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
219 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
220 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
221 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
222 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
223 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
224 {0, 0, 0}
225 };
226
227 #if defined(CONFIG_DRM_I915_KMS)
228 MODULE_DEVICE_TABLE(pci, pciidlist);
229 #endif
230
231 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
232 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
233
234 void intel_detect_pch (struct drm_device *dev)
235 {
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 struct pci_dev *pch;
238
239 /*
240 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
241 * make graphics device passthrough work easy for VMM, that only
242 * need to expose ISA bridge to let driver know the real hardware
243 * underneath. This is a requirement from virtualization team.
244 */
245 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
246 if (pch) {
247 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
248 int id;
249 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
250
251 if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
252 dev_priv->pch_type = PCH_CPT;
253 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
254 }
255 }
256 pci_dev_put(pch);
257 }
258 }
259
260 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
261 {
262 int count;
263
264 count = 0;
265 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
266 udelay(10);
267
268 I915_WRITE_NOTRACE(FORCEWAKE, 1);
269 POSTING_READ(FORCEWAKE);
270
271 count = 0;
272 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
273 udelay(10);
274 }
275
276 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
277 {
278 I915_WRITE_NOTRACE(FORCEWAKE, 0);
279 POSTING_READ(FORCEWAKE);
280 }
281
282 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
283 {
284 int loop = 500;
285 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
286 while (fifo < 20 && loop--) {
287 udelay(10);
288 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
289 }
290 }
291
292 static int i915_drm_freeze(struct drm_device *dev)
293 {
294 struct drm_i915_private *dev_priv = dev->dev_private;
295
296 drm_kms_helper_poll_disable(dev);
297
298 pci_save_state(dev->pdev);
299
300 /* If KMS is active, we do the leavevt stuff here */
301 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
302 int error = i915_gem_idle(dev);
303 if (error) {
304 dev_err(&dev->pdev->dev,
305 "GEM idle failed, resume might fail\n");
306 return error;
307 }
308 drm_irq_uninstall(dev);
309 }
310
311 i915_save_state(dev);
312
313 intel_opregion_fini(dev);
314
315 /* Modeset on resume, not lid events */
316 dev_priv->modeset_on_lid = 0;
317
318 return 0;
319 }
320
321 int i915_suspend(struct drm_device *dev, pm_message_t state)
322 {
323 int error;
324
325 if (!dev || !dev->dev_private) {
326 DRM_ERROR("dev: %p\n", dev);
327 DRM_ERROR("DRM not initialized, aborting suspend.\n");
328 return -ENODEV;
329 }
330
331 if (state.event == PM_EVENT_PRETHAW)
332 return 0;
333
334
335 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
336 return 0;
337
338 error = i915_drm_freeze(dev);
339 if (error)
340 return error;
341
342 if (state.event == PM_EVENT_SUSPEND) {
343 /* Shut down the device */
344 pci_disable_device(dev->pdev);
345 pci_set_power_state(dev->pdev, PCI_D3hot);
346 }
347
348 return 0;
349 }
350
351 static int i915_drm_thaw(struct drm_device *dev)
352 {
353 struct drm_i915_private *dev_priv = dev->dev_private;
354 int error = 0;
355
356 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
357 mutex_lock(&dev->struct_mutex);
358 i915_gem_restore_gtt_mappings(dev);
359 mutex_unlock(&dev->struct_mutex);
360 }
361
362 i915_restore_state(dev);
363 intel_opregion_setup(dev);
364
365 /* KMS EnterVT equivalent */
366 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
367 mutex_lock(&dev->struct_mutex);
368 dev_priv->mm.suspended = 0;
369
370 error = i915_gem_init_ringbuffer(dev);
371 mutex_unlock(&dev->struct_mutex);
372
373 drm_mode_config_reset(dev);
374 drm_irq_install(dev);
375
376 /* Resume the modeset for every activated CRTC */
377 drm_helper_resume_force_mode(dev);
378
379 if (IS_IRONLAKE_M(dev))
380 ironlake_enable_rc6(dev);
381 }
382
383 intel_opregion_init(dev);
384
385 dev_priv->modeset_on_lid = 0;
386
387 return error;
388 }
389
390 int i915_resume(struct drm_device *dev)
391 {
392 int ret;
393
394 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
395 return 0;
396
397 if (pci_enable_device(dev->pdev))
398 return -EIO;
399
400 pci_set_master(dev->pdev);
401
402 ret = i915_drm_thaw(dev);
403 if (ret)
404 return ret;
405
406 drm_kms_helper_poll_enable(dev);
407 return 0;
408 }
409
410 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
411 {
412 struct drm_i915_private *dev_priv = dev->dev_private;
413
414 if (IS_I85X(dev))
415 return -ENODEV;
416
417 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
418 POSTING_READ(D_STATE);
419
420 if (IS_I830(dev) || IS_845G(dev)) {
421 I915_WRITE(DEBUG_RESET_I830,
422 DEBUG_RESET_DISPLAY |
423 DEBUG_RESET_RENDER |
424 DEBUG_RESET_FULL);
425 POSTING_READ(DEBUG_RESET_I830);
426 msleep(1);
427
428 I915_WRITE(DEBUG_RESET_I830, 0);
429 POSTING_READ(DEBUG_RESET_I830);
430 }
431
432 msleep(1);
433
434 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
435 POSTING_READ(D_STATE);
436
437 return 0;
438 }
439
440 static int i965_reset_complete(struct drm_device *dev)
441 {
442 u8 gdrst;
443 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
444 return gdrst & 0x1;
445 }
446
447 static int i965_do_reset(struct drm_device *dev, u8 flags)
448 {
449 u8 gdrst;
450
451 /*
452 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
453 * well as the reset bit (GR/bit 0). Setting the GR bit
454 * triggers the reset; when done, the hardware will clear it.
455 */
456 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
457 pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
458
459 return wait_for(i965_reset_complete(dev), 500);
460 }
461
462 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
463 {
464 struct drm_i915_private *dev_priv = dev->dev_private;
465 u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
466 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
467 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
468 }
469
470 static int gen6_do_reset(struct drm_device *dev, u8 flags)
471 {
472 struct drm_i915_private *dev_priv = dev->dev_private;
473
474 I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
475 return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
476 }
477
478 /**
479 * i965_reset - reset chip after a hang
480 * @dev: drm device to reset
481 * @flags: reset domains
482 *
483 * Reset the chip. Useful if a hang is detected. Returns zero on successful
484 * reset or otherwise an error code.
485 *
486 * Procedure is fairly simple:
487 * - reset the chip using the reset reg
488 * - re-init context state
489 * - re-init hardware status page
490 * - re-init ring buffer
491 * - re-init interrupt state
492 * - re-init display
493 */
494 int i915_reset(struct drm_device *dev, u8 flags)
495 {
496 drm_i915_private_t *dev_priv = dev->dev_private;
497 /*
498 * We really should only reset the display subsystem if we actually
499 * need to
500 */
501 bool need_display = true;
502 int ret;
503
504 if (!i915_try_reset)
505 return 0;
506
507 if (!mutex_trylock(&dev->struct_mutex))
508 return -EBUSY;
509
510 i915_gem_reset(dev);
511
512 ret = -ENODEV;
513 if (get_seconds() - dev_priv->last_gpu_reset < 5) {
514 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
515 } else switch (INTEL_INFO(dev)->gen) {
516 case 6:
517 ret = gen6_do_reset(dev, flags);
518 break;
519 case 5:
520 ret = ironlake_do_reset(dev, flags);
521 break;
522 case 4:
523 ret = i965_do_reset(dev, flags);
524 break;
525 case 2:
526 ret = i8xx_do_reset(dev, flags);
527 break;
528 }
529 dev_priv->last_gpu_reset = get_seconds();
530 if (ret) {
531 DRM_ERROR("Failed to reset chip.\n");
532 mutex_unlock(&dev->struct_mutex);
533 return ret;
534 }
535
536 /* Ok, now get things going again... */
537
538 /*
539 * Everything depends on having the GTT running, so we need to start
540 * there. Fortunately we don't need to do this unless we reset the
541 * chip at a PCI level.
542 *
543 * Next we need to restore the context, but we don't use those
544 * yet either...
545 *
546 * Ring buffer needs to be re-initialized in the KMS case, or if X
547 * was running at the time of the reset (i.e. we weren't VT
548 * switched away).
549 */
550 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
551 !dev_priv->mm.suspended) {
552 dev_priv->mm.suspended = 0;
553
554 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
555 if (HAS_BSD(dev))
556 dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
557 if (HAS_BLT(dev))
558 dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
559
560 mutex_unlock(&dev->struct_mutex);
561 drm_irq_uninstall(dev);
562 drm_mode_config_reset(dev);
563 drm_irq_install(dev);
564 mutex_lock(&dev->struct_mutex);
565 }
566
567 mutex_unlock(&dev->struct_mutex);
568
569 /*
570 * Perform a full modeset as on later generations, e.g. Ironlake, we may
571 * need to retrain the display link and cannot just restore the register
572 * values.
573 */
574 if (need_display) {
575 mutex_lock(&dev->mode_config.mutex);
576 drm_helper_resume_force_mode(dev);
577 mutex_unlock(&dev->mode_config.mutex);
578 }
579
580 return 0;
581 }
582
583
584 static int __devinit
585 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
586 {
587 /* Only bind to function 0 of the device. Early generations
588 * used function 1 as a placeholder for multi-head. This causes
589 * us confusion instead, especially on the systems where both
590 * functions have the same PCI-ID!
591 */
592 if (PCI_FUNC(pdev->devfn))
593 return -ENODEV;
594
595 return drm_get_pci_dev(pdev, ent, &driver);
596 }
597
598 static void
599 i915_pci_remove(struct pci_dev *pdev)
600 {
601 struct drm_device *dev = pci_get_drvdata(pdev);
602
603 drm_put_dev(dev);
604 }
605
606 static int i915_pm_suspend(struct device *dev)
607 {
608 struct pci_dev *pdev = to_pci_dev(dev);
609 struct drm_device *drm_dev = pci_get_drvdata(pdev);
610 int error;
611
612 if (!drm_dev || !drm_dev->dev_private) {
613 dev_err(dev, "DRM not initialized, aborting suspend.\n");
614 return -ENODEV;
615 }
616
617 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
618 return 0;
619
620 error = i915_drm_freeze(drm_dev);
621 if (error)
622 return error;
623
624 pci_disable_device(pdev);
625 pci_set_power_state(pdev, PCI_D3hot);
626
627 return 0;
628 }
629
630 static int i915_pm_resume(struct device *dev)
631 {
632 struct pci_dev *pdev = to_pci_dev(dev);
633 struct drm_device *drm_dev = pci_get_drvdata(pdev);
634
635 return i915_resume(drm_dev);
636 }
637
638 static int i915_pm_freeze(struct device *dev)
639 {
640 struct pci_dev *pdev = to_pci_dev(dev);
641 struct drm_device *drm_dev = pci_get_drvdata(pdev);
642
643 if (!drm_dev || !drm_dev->dev_private) {
644 dev_err(dev, "DRM not initialized, aborting suspend.\n");
645 return -ENODEV;
646 }
647
648 return i915_drm_freeze(drm_dev);
649 }
650
651 static int i915_pm_thaw(struct device *dev)
652 {
653 struct pci_dev *pdev = to_pci_dev(dev);
654 struct drm_device *drm_dev = pci_get_drvdata(pdev);
655
656 return i915_drm_thaw(drm_dev);
657 }
658
659 static int i915_pm_poweroff(struct device *dev)
660 {
661 struct pci_dev *pdev = to_pci_dev(dev);
662 struct drm_device *drm_dev = pci_get_drvdata(pdev);
663
664 return i915_drm_freeze(drm_dev);
665 }
666
667 static const struct dev_pm_ops i915_pm_ops = {
668 .suspend = i915_pm_suspend,
669 .resume = i915_pm_resume,
670 .freeze = i915_pm_freeze,
671 .thaw = i915_pm_thaw,
672 .poweroff = i915_pm_poweroff,
673 .restore = i915_pm_resume,
674 };
675
676 static struct vm_operations_struct i915_gem_vm_ops = {
677 .fault = i915_gem_fault,
678 .open = drm_gem_vm_open,
679 .close = drm_gem_vm_close,
680 };
681
682 static struct drm_driver driver = {
683 /* don't use mtrr's here, the Xserver or user space app should
684 * deal with them for intel hardware.
685 */
686 .driver_features =
687 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
688 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
689 .load = i915_driver_load,
690 .unload = i915_driver_unload,
691 .open = i915_driver_open,
692 .lastclose = i915_driver_lastclose,
693 .preclose = i915_driver_preclose,
694 .postclose = i915_driver_postclose,
695
696 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
697 .suspend = i915_suspend,
698 .resume = i915_resume,
699
700 .device_is_agp = i915_driver_device_is_agp,
701 .enable_vblank = i915_enable_vblank,
702 .disable_vblank = i915_disable_vblank,
703 .get_vblank_timestamp = i915_get_vblank_timestamp,
704 .get_scanout_position = i915_get_crtc_scanoutpos,
705 .irq_preinstall = i915_driver_irq_preinstall,
706 .irq_postinstall = i915_driver_irq_postinstall,
707 .irq_uninstall = i915_driver_irq_uninstall,
708 .irq_handler = i915_driver_irq_handler,
709 .reclaim_buffers = drm_core_reclaim_buffers,
710 .master_create = i915_master_create,
711 .master_destroy = i915_master_destroy,
712 #if defined(CONFIG_DEBUG_FS)
713 .debugfs_init = i915_debugfs_init,
714 .debugfs_cleanup = i915_debugfs_cleanup,
715 #endif
716 .gem_init_object = i915_gem_init_object,
717 .gem_free_object = i915_gem_free_object,
718 .gem_vm_ops = &i915_gem_vm_ops,
719 .ioctls = i915_ioctls,
720 .fops = {
721 .owner = THIS_MODULE,
722 .open = drm_open,
723 .release = drm_release,
724 .unlocked_ioctl = drm_ioctl,
725 .mmap = drm_gem_mmap,
726 .poll = drm_poll,
727 .fasync = drm_fasync,
728 .read = drm_read,
729 #ifdef CONFIG_COMPAT
730 .compat_ioctl = i915_compat_ioctl,
731 #endif
732 .llseek = noop_llseek,
733 },
734
735 .pci_driver = {
736 .name = DRIVER_NAME,
737 .id_table = pciidlist,
738 .probe = i915_pci_probe,
739 .remove = i915_pci_remove,
740 .driver.pm = &i915_pm_ops,
741 },
742
743 .name = DRIVER_NAME,
744 .desc = DRIVER_DESC,
745 .date = DRIVER_DATE,
746 .major = DRIVER_MAJOR,
747 .minor = DRIVER_MINOR,
748 .patchlevel = DRIVER_PATCHLEVEL,
749 };
750
751 static int __init i915_init(void)
752 {
753 if (!intel_agp_enabled) {
754 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
755 return -ENODEV;
756 }
757
758 driver.num_ioctls = i915_max_ioctl;
759
760 /*
761 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
762 * explicitly disabled with the module pararmeter.
763 *
764 * Otherwise, just follow the parameter (defaulting to off).
765 *
766 * Allow optional vga_text_mode_force boot option to override
767 * the default behavior.
768 */
769 #if defined(CONFIG_DRM_I915_KMS)
770 if (i915_modeset != 0)
771 driver.driver_features |= DRIVER_MODESET;
772 #endif
773 if (i915_modeset == 1)
774 driver.driver_features |= DRIVER_MODESET;
775
776 #ifdef CONFIG_VGA_CONSOLE
777 if (vgacon_text_force() && i915_modeset == -1)
778 driver.driver_features &= ~DRIVER_MODESET;
779 #endif
780
781 if (!(driver.driver_features & DRIVER_MODESET))
782 driver.get_vblank_timestamp = NULL;
783
784 return drm_init(&driver);
785 }
786
787 static void __exit i915_exit(void)
788 {
789 drm_exit(&driver);
790 }
791
792 module_init(i915_init);
793 module_exit(i915_exit);
794
795 MODULE_AUTHOR(DRIVER_AUTHOR);
796 MODULE_DESCRIPTION(DRIVER_DESC);
797 MODULE_LICENSE("GPL and additional rights");