drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include <linux/io-mapping.h>
  36
  37 /* General customization:
  38  */
  39
  40 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  41
  42 #define DRIVER_NAME             "i915"
  43 #define DRIVER_DESC             "Intel Graphics"
  44 #define DRIVER_DATE             "20080730"
  45
  46 enum pipe {
  47         PIPE_A = 0,
  48         PIPE_B,
  49 };
  50
  51 #define I915_NUM_PIPE   2
  52
  53 /* Interface history:
  54  *
  55  * 1.1: Original.
  56  * 1.2: Add Power Management
  57  * 1.3: Add vblank support
  58  * 1.4: Fix cmdbuffer path, add heap destroy
  59  * 1.5: Add vblank pipe configuration
  60  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  61  *      - Support vertical blank on secondary display pipe
  62  */
  63 #define DRIVER_MAJOR            1
  64 #define DRIVER_MINOR            6
  65 #define DRIVER_PATCHLEVEL       0
  66
  67 #define WATCH_COHERENCY 0
  68 #define WATCH_BUF       0
  69 #define WATCH_EXEC      0
  70 #define WATCH_LRU       0
  71 #define WATCH_RELOC     0
  72 #define WATCH_INACTIVE  0
  73 #define WATCH_PWRITE    0
  74
  75 #define I915_GEM_PHYS_CURSOR_0 1
  76 #define I915_GEM_PHYS_CURSOR_1 2
  77 #define I915_GEM_PHYS_OVERLAY_REGS 3
  78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  79
  80 struct drm_i915_gem_phys_object {
  81         int id;
  82         struct page **page_list;
  83         drm_dma_handle_t *handle;
  84         struct drm_gem_object *cur_obj;
  85 };
  86
  87 typedef struct _drm_i915_ring_buffer {
  88         int tail_mask;
  89         unsigned long Size;
  90         u8 *virtual_start;
  91         int head;
  92         int tail;
  93         int space;
  94         drm_local_map_t map;
  95         struct drm_gem_object *ring_obj;
  96 } drm_i915_ring_buffer_t;
  97
  98 struct mem_block {
  99         struct mem_block *next;
 100         struct mem_block *prev;
 101         int start;
 102         int size;
 103         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 104 };
 105
 106 struct opregion_header;
 107 struct opregion_acpi;
 108 struct opregion_swsci;
 109 struct opregion_asle;
 110
 111 struct intel_opregion {
 112         struct opregion_header *header;
 113         struct opregion_acpi *acpi;
 114         struct opregion_swsci *swsci;
 115         struct opregion_asle *asle;
 116         int enabled;
 117 };
 118
 119 struct drm_i915_master_private {
 120         drm_local_map_t *sarea;
 121         struct _drm_i915_sarea *sarea_priv;
 122 };
 123 #define I915_FENCE_REG_NONE -1
 124
 125 struct drm_i915_fence_reg {
 126         struct drm_gem_object *obj;
 127 };
 128
 129 typedef struct drm_i915_private {
 130         struct drm_device *dev;
 131
 132         int has_gem;
 133
 134         void __iomem *regs;
 135
 136         drm_i915_ring_buffer_t ring;
 137
 138         drm_dma_handle_t *status_page_dmah;
 139         void *hw_status_page;
 140         dma_addr_t dma_status_page;
 141         uint32_t counter;
 142         unsigned int status_gfx_addr;
 143         drm_local_map_t hws_map;
 144         struct drm_gem_object *hws_obj;
 145
 146         unsigned int cpp;
 147         int back_offset;
 148         int front_offset;
 149         int current_page;
 150         int page_flipping;
 151
 152         wait_queue_head_t irq_queue;
 153         atomic_t irq_received;
 154         /** Protects user_irq_refcount and irq_mask_reg */
 155         spinlock_t user_irq_lock;
 156         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 157         int user_irq_refcount;
 158         /** Cached value of IMR to avoid reads in updating the bitfield */
 159         u32 irq_mask_reg;
 160         u32 pipestat[2];
 161
 162         int tex_lru_log_granularity;
 163         int allow_batchbuffer;
 164         struct mem_block *agp_heap;
 165         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 166         int vblank_pipe;
 167
 168         bool cursor_needs_physical;
 169
 170         struct drm_mm vram;
 171
 172         int irq_enabled;
 173
 174         struct intel_opregion opregion;
 175
 176         /* LVDS info */
 177         int backlight_duty_cycle;  /* restore backlight to this value */
 178         bool panel_wants_dither;
 179         struct drm_display_mode *panel_fixed_mode;
 180         struct drm_display_mode *vbt_mode; /* if any */
 181
 182         /* Feature bits from the VBIOS */
 183         unsigned int int_tv_support:1;
 184         unsigned int lvds_dither:1;
 185         unsigned int lvds_vbt:1;
 186         unsigned int int_crt_support:1;
 187         unsigned int lvds_use_ssc:1;
 188         int lvds_ssc_freq;
 189
 190         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 191         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 192         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 193
 194         /* Register state */
 195         u8 saveLBB;
 196         u32 saveDSPACNTR;
 197         u32 saveDSPBCNTR;
 198         u32 saveDSPARB;
 199         u32 saveRENDERSTANDBY;
 200         u32 saveHWS;
 201         u32 savePIPEACONF;
 202         u32 savePIPEBCONF;
 203         u32 savePIPEASRC;
 204         u32 savePIPEBSRC;
 205         u32 saveFPA0;
 206         u32 saveFPA1;
 207         u32 saveDPLL_A;
 208         u32 saveDPLL_A_MD;
 209         u32 saveHTOTAL_A;
 210         u32 saveHBLANK_A;
 211         u32 saveHSYNC_A;
 212         u32 saveVTOTAL_A;
 213         u32 saveVBLANK_A;
 214         u32 saveVSYNC_A;
 215         u32 saveBCLRPAT_A;
 216         u32 savePIPEASTAT;
 217         u32 saveDSPASTRIDE;
 218         u32 saveDSPASIZE;
 219         u32 saveDSPAPOS;
 220         u32 saveDSPAADDR;
 221         u32 saveDSPASURF;
 222         u32 saveDSPATILEOFF;
 223         u32 savePFIT_PGM_RATIOS;
 224         u32 saveBLC_PWM_CTL;
 225         u32 saveBLC_PWM_CTL2;
 226         u32 saveFPB0;
 227         u32 saveFPB1;
 228         u32 saveDPLL_B;
 229         u32 saveDPLL_B_MD;
 230         u32 saveHTOTAL_B;
 231         u32 saveHBLANK_B;
 232         u32 saveHSYNC_B;
 233         u32 saveVTOTAL_B;
 234         u32 saveVBLANK_B;
 235         u32 saveVSYNC_B;
 236         u32 saveBCLRPAT_B;
 237         u32 savePIPEBSTAT;
 238         u32 saveDSPBSTRIDE;
 239         u32 saveDSPBSIZE;
 240         u32 saveDSPBPOS;
 241         u32 saveDSPBADDR;
 242         u32 saveDSPBSURF;
 243         u32 saveDSPBTILEOFF;
 244         u32 saveVGA0;
 245         u32 saveVGA1;
 246         u32 saveVGA_PD;
 247         u32 saveVGACNTRL;
 248         u32 saveADPA;
 249         u32 saveLVDS;
 250         u32 savePP_ON_DELAYS;
 251         u32 savePP_OFF_DELAYS;
 252         u32 saveDVOA;
 253         u32 saveDVOB;
 254         u32 saveDVOC;
 255         u32 savePP_ON;
 256         u32 savePP_OFF;
 257         u32 savePP_CONTROL;
 258         u32 savePP_DIVISOR;
 259         u32 savePFIT_CONTROL;
 260         u32 save_palette_a[256];
 261         u32 save_palette_b[256];
 262         u32 saveFBC_CFB_BASE;
 263         u32 saveFBC_LL_BASE;
 264         u32 saveFBC_CONTROL;
 265         u32 saveFBC_CONTROL2;
 266         u32 saveIER;
 267         u32 saveIIR;
 268         u32 saveIMR;
 269         u32 saveCACHE_MODE_0;
 270         u32 saveD_STATE;
 271         u32 saveCG_2D_DIS;
 272         u32 saveMI_ARB_STATE;
 273         u32 saveSWF0[16];
 274         u32 saveSWF1[16];
 275         u32 saveSWF2[3];
 276         u8 saveMSR;
 277         u8 saveSR[8];
 278         u8 saveGR[25];
 279         u8 saveAR_INDEX;
 280         u8 saveAR[21];
 281         u8 saveDACMASK;
 282         u8 saveDACDATA[256*3]; /* 256 3-byte colors */
 283         u8 saveCR[37];
 284
 285         struct {
 286                 struct drm_mm gtt_space;
 287
 288                 struct io_mapping *gtt_mapping;
 289                 int gtt_mtrr;
 290
 291                 /**
 292                  * List of objects currently involved in rendering from the
 293                  * ringbuffer.
 294                  *
 295                  * Includes buffers having the contents of their GPU caches
 296                  * flushed, not necessarily primitives.  last_rendering_seqno
 297                  * represents when the rendering involved will be completed.
 298                  *
 299                  * A reference is held on the buffer while on this list.
 300                  */
 301                 struct list_head active_list;
 302
 303                 /**
 304                  * List of objects which are not in the ringbuffer but which
 305                  * still have a write_domain which needs to be flushed before
 306                  * unbinding.
 307                  *
 308                  * last_rendering_seqno is 0 while an object is in this list.
 309                  *
 310                  * A reference is held on the buffer while on this list.
 311                  */
 312                 struct list_head flushing_list;
 313
 314                 /**
 315                  * LRU list of objects which are not in the ringbuffer and
 316                  * are ready to unbind, but are still in the GTT.
 317                  *
 318                  * last_rendering_seqno is 0 while an object is in this list.
 319                  *
 320                  * A reference is not held on the buffer while on this list,
 321                  * as merely being GTT-bound shouldn't prevent its being
 322                  * freed, and we'll pull it off the list in the free path.
 323                  */
 324                 struct list_head inactive_list;
 325
 326                 /**
 327                  * List of breadcrumbs associated with GPU requests currently
 328                  * outstanding.
 329                  */
 330                 struct list_head request_list;
 331
 332                 /**
 333                  * We leave the user IRQ off as much as possible,
 334                  * but this means that requests will finish and never
 335                  * be retired once the system goes idle. Set a timer to
 336                  * fire periodically while the ring is running. When it
 337                  * fires, go retire requests.
 338                  */
 339                 struct delayed_work retire_work;
 340
 341                 uint32_t next_gem_seqno;
 342
 343                 /**
 344                  * Waiting sequence number, if any
 345                  */
 346                 uint32_t waiting_gem_seqno;
 347
 348                 /**
 349                  * Last seq seen at irq time
 350                  */
 351                 uint32_t irq_gem_seqno;
 352
 353                 /**
 354                  * Flag if the X Server, and thus DRM, is not currently in
 355                  * control of the device.
 356                  *
 357                  * This is set between LeaveVT and EnterVT.  It needs to be
 358                  * replaced with a semaphore.  It also needs to be
 359                  * transitioned away from for kernel modesetting.
 360                  */
 361                 int suspended;
 362
 363                 /**
 364                  * Flag if the hardware appears to be wedged.
 365                  *
 366                  * This is set when attempts to idle the device timeout.
 367                  * It prevents command submission from occuring and makes
 368                  * every pending request fail
 369                  */
 370                 int wedged;
 371
 372                 /** Bit 6 swizzling required for X tiling */
 373                 uint32_t bit_6_swizzle_x;
 374                 /** Bit 6 swizzling required for Y tiling */
 375                 uint32_t bit_6_swizzle_y;
 376
 377                 /* storage for physical objects */
 378                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 379         } mm;
 380 } drm_i915_private_t;
 381
 382 /** driver private structure attached to each drm_gem_object */
 383 struct drm_i915_gem_object {
 384         struct drm_gem_object *obj;
 385
 386         /** Current space allocated to this object in the GTT, if any. */
 387         struct drm_mm_node *gtt_space;
 388
 389         /** This object's place on the active/flushing/inactive lists */
 390         struct list_head list;
 391
 392         /**
 393          * This is set if the object is on the active or flushing lists
 394          * (has pending rendering), and is not set if it's on inactive (ready
 395          * to be unbound).
 396          */
 397         int active;
 398
 399         /**
 400          * This is set if the object has been written to since last bound
 401          * to the GTT
 402          */
 403         int dirty;
 404
 405         /** AGP memory structure for our GTT binding. */
 406         DRM_AGP_MEM *agp_mem;
 407
 408         struct page **page_list;
 409
 410         /**
 411          * Current offset of the object in GTT space.
 412          *
 413          * This is the same as gtt_space->start
 414          */
 415         uint32_t gtt_offset;
 416         /**
 417          * Required alignment for the object
 418          */
 419         uint32_t gtt_alignment;
 420         /**
 421          * Fake offset for use by mmap(2)
 422          */
 423         uint64_t mmap_offset;
 424
 425         /**
 426          * Fence register bits (if any) for this object.  Will be set
 427          * as needed when mapped into the GTT.
 428          * Protected by dev->struct_mutex.
 429          */
 430         int fence_reg;
 431
 432         /** Boolean whether this object has a valid gtt offset. */
 433         int gtt_bound;
 434
 435         /** How many users have pinned this object in GTT space */
 436         int pin_count;
 437
 438         /** Breadcrumb of last rendering to the buffer. */
 439         uint32_t last_rendering_seqno;
 440
 441         /** Current tiling mode for the object. */
 442         uint32_t tiling_mode;
 443         uint32_t stride;
 444
 445         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 446         uint32_t agp_type;
 447
 448         /**
 449          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 450          * flags which individual pages are valid.
 451          */
 452         uint8_t *page_cpu_valid;
 453
 454         /** User space pin count and filp owning the pin */
 455         uint32_t user_pin_count;
 456         struct drm_file *pin_filp;
 457
 458         /** for phy allocated objects */
 459         struct drm_i915_gem_phys_object *phys_obj;
 460 };
 461
 462 /**
 463  * Request queue structure.
 464  *
 465  * The request queue allows us to note sequence numbers that have been emitted
 466  * and may be associated with active buffers to be retired.
 467  *
 468  * By keeping this list, we can avoid having to do questionable
 469  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 470  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 471  */
 472 struct drm_i915_gem_request {
 473         /** GEM sequence number associated with this request. */
 474         uint32_t seqno;
 475
 476         /** Time at which this request was emitted, in jiffies. */
 477         unsigned long emitted_jiffies;
 478
 479         struct list_head list;
 480 };
 481
 482 struct drm_i915_file_private {
 483         struct {
 484                 uint32_t last_gem_seqno;
 485                 uint32_t last_gem_throttle_seqno;
 486         } mm;
 487 };
 488
 489 enum intel_chip_family {
 490         CHIP_I8XX = 0x01,
 491         CHIP_I9XX = 0x02,
 492         CHIP_I915 = 0x04,
 493         CHIP_I965 = 0x08,
 494 };
 495
 496 extern struct drm_ioctl_desc i915_ioctls[];
 497 extern int i915_max_ioctl;
 498 extern unsigned int i915_fbpercrtc;
 499
 500 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 501 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 502
 503                                 /* i915_dma.c */
 504 extern void i915_kernel_lost_context(struct drm_device * dev);
 505 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 506 extern int i915_driver_unload(struct drm_device *);
 507 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 508 extern void i915_driver_lastclose(struct drm_device * dev);
 509 extern void i915_driver_preclose(struct drm_device *dev,
 510                                  struct drm_file *file_priv);
 511 extern void i915_driver_postclose(struct drm_device *dev,
 512                                   struct drm_file *file_priv);
 513 extern int i915_driver_device_is_agp(struct drm_device * dev);
 514 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 515                               unsigned long arg);
 516 extern int i915_emit_box(struct drm_device *dev,
 517                          struct drm_clip_rect __user *boxes,
 518                          int i, int DR1, int DR4);
 519
 520 /* i915_irq.c */
 521 extern int i915_irq_emit(struct drm_device *dev, void *data,
 522                          struct drm_file *file_priv);
 523 extern int i915_irq_wait(struct drm_device *dev, void *data,
 524                          struct drm_file *file_priv);
 525 void i915_user_irq_get(struct drm_device *dev);
 526 void i915_user_irq_put(struct drm_device *dev);
 527 extern void i915_enable_interrupt (struct drm_device *dev);
 528
 529 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 530 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 531 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 532 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 533 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 534                                 struct drm_file *file_priv);
 535 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 536                                 struct drm_file *file_priv);
 537 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 538 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 539 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 540 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 541 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 542                             struct drm_file *file_priv);
 543 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 544
 545 void
 546 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 547
 548 void
 549 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 550
 551
 552 /* i915_mem.c */
 553 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 554                           struct drm_file *file_priv);
 555 extern int i915_mem_free(struct drm_device *dev, void *data,
 556                          struct drm_file *file_priv);
 557 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 558                               struct drm_file *file_priv);
 559 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 560                                  struct drm_file *file_priv);
 561 extern void i915_mem_takedown(struct mem_block **heap);
 562 extern void i915_mem_release(struct drm_device * dev,
 563                              struct drm_file *file_priv, struct mem_block *heap);
 564 /* i915_gem.c */
 565 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 566                         struct drm_file *file_priv);
 567 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 568                           struct drm_file *file_priv);
 569 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 570                          struct drm_file *file_priv);
 571 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 572                           struct drm_file *file_priv);
 573 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 574                         struct drm_file *file_priv);
 575 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 576                         struct drm_file *file_priv);
 577 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 578                               struct drm_file *file_priv);
 579 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 580                              struct drm_file *file_priv);
 581 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 582                         struct drm_file *file_priv);
 583 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 584                        struct drm_file *file_priv);
 585 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 586                          struct drm_file *file_priv);
 587 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 588                         struct drm_file *file_priv);
 589 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 590                             struct drm_file *file_priv);
 591 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 592                            struct drm_file *file_priv);
 593 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 594                            struct drm_file *file_priv);
 595 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 596                         struct drm_file *file_priv);
 597 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 598                         struct drm_file *file_priv);
 599 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 600                                 struct drm_file *file_priv);
 601 void i915_gem_load(struct drm_device *dev);
 602 int i915_gem_proc_init(struct drm_minor *minor);
 603 void i915_gem_proc_cleanup(struct drm_minor *minor);
 604 int i915_gem_init_object(struct drm_gem_object *obj);
 605 void i915_gem_free_object(struct drm_gem_object *obj);
 606 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 607 void i915_gem_object_unpin(struct drm_gem_object *obj);
 608 int i915_gem_object_unbind(struct drm_gem_object *obj);
 609 void i915_gem_lastclose(struct drm_device *dev);
 610 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 611 void i915_gem_retire_requests(struct drm_device *dev);
 612 void i915_gem_retire_work_handler(struct work_struct *work);
 613 void i915_gem_clflush_object(struct drm_gem_object *obj);
 614 int i915_gem_object_set_domain(struct drm_gem_object *obj,
 615                                uint32_t read_domains,
 616                                uint32_t write_domain);
 617 int i915_gem_init_ringbuffer(struct drm_device *dev);
 618 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 619 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
 620                      unsigned long end);
 621 int i915_gem_idle(struct drm_device *dev);
 622 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 623 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
 624                                       int write);
 625 int i915_gem_attach_phys_object(struct drm_device *dev,
 626                                 struct drm_gem_object *obj, int id);
 627 void i915_gem_detach_phys_object(struct drm_device *dev,
 628                                  struct drm_gem_object *obj);
 629 void i915_gem_free_all_phys_object(struct drm_device *dev);
 630
 631 /* i915_gem_tiling.c */
 632 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 633
 634 /* i915_gem_debug.c */
 635 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 636                           const char *where, uint32_t mark);
 637 #if WATCH_INACTIVE
 638 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 639 #else
 640 #define i915_verify_inactive(dev, file, line)
 641 #endif
 642 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 643 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 644                           const char *where, uint32_t mark);
 645 void i915_dump_lru(struct drm_device *dev, const char *where);
 646
 647 /* i915_suspend.c */
 648 extern int i915_save_state(struct drm_device *dev);
 649 extern int i915_restore_state(struct drm_device *dev);
 650
 651 /* i915_suspend.c */
 652 extern int i915_save_state(struct drm_device *dev);
 653 extern int i915_restore_state(struct drm_device *dev);
 654
 655 #ifdef CONFIG_ACPI
 656 /* i915_opregion.c */
 657 extern int intel_opregion_init(struct drm_device *dev);
 658 extern void intel_opregion_free(struct drm_device *dev);
 659 extern void opregion_asle_intr(struct drm_device *dev);
 660 extern void opregion_enable_asle(struct drm_device *dev);
 661 #else
 662 static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
 663 static inline void intel_opregion_free(struct drm_device *dev) { return; }
 664 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 665 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 666 #endif
 667
 668 /* modesetting */
 669 extern void intel_modeset_init(struct drm_device *dev);
 670 extern void intel_modeset_cleanup(struct drm_device *dev);
 671
 672 /**
 673  * Lock test for when it's just for synchronization of ring access.
 674  *
 675  * In that case, we don't need to do it when GEM is initialized as nobody else
 676  * has access to the ring.
 677  */
 678 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 679         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 680                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 681 } while (0)
 682
 683 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 684 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 685 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 686 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 687 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 688 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 689 #ifdef writeq
 690 #define I915_WRITE64(reg, val)  writeq(val, dev_priv->regs + (reg))
 691 #else
 692 #define I915_WRITE64(reg, val)  (writel(val, dev_priv->regs + (reg)), \
 693                                  writel(upper_32_bits(val), dev_priv->regs + \
 694                                         (reg) + 4))
 695 #endif
 696 #define POSTING_READ(reg)       (void)I915_READ(reg)
 697
 698 #define I915_VERBOSE 0
 699
 700 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 701                         volatile char *virt;
 702
 703 #define BEGIN_LP_RING(n) do {                           \
 704         if (I915_VERBOSE)                               \
 705                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));  \
 706         if (dev_priv->ring.space < (n)*4)               \
 707                 i915_wait_ring(dev, (n)*4, __func__);           \
 708         outcount = 0;                                   \
 709         outring = dev_priv->ring.tail;                  \
 710         ringmask = dev_priv->ring.tail_mask;            \
 711         virt = dev_priv->ring.virtual_start;            \
 712 } while (0)
 713
 714 #define OUT_RING(n) do {                                        \
 715         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 716         *(volatile unsigned int *)(virt + outring) = (n);       \
 717         outcount++;                                             \
 718         outring += 4;                                           \
 719         outring &= ringmask;                                    \
 720 } while (0)
 721
 722 #define ADVANCE_LP_RING() do {                                          \
 723         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 724         dev_priv->ring.tail = outring;                                  \
 725         dev_priv->ring.space -= outcount * 4;                           \
 726         I915_WRITE(PRB0_TAIL, outring);                 \
 727 } while(0)
 728
 729 /**
 730  * Reads a dword out of the status page, which is written to from the command
 731  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 732  * MI_STORE_DATA_IMM.
 733  *
 734  * The following dwords have a reserved meaning:
 735  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 736  * 0x04: ring 0 head pointer
 737  * 0x05: ring 1 head pointer (915-class)
 738  * 0x06: ring 2 head pointer (915-class)
 739  * 0x10-0x1b: Context status DWords (GM45)
 740  * 0x1f: Last written status offset. (GM45)
 741  *
 742  * The area from dword 0x20 to 0x3ff is available for driver usage.
 743  */
 744 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 745 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 746 #define I915_GEM_HWS_INDEX              0x20
 747 #define I915_BREADCRUMB_INDEX           0x21
 748
 749 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 750
 751 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 752 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 753 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 754 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 755 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 756
 757 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 758 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 759 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 760 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 761                         (dev)->pci_device == 0x27AE)
 762 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 763                        (dev)->pci_device == 0x2982 || \
 764                        (dev)->pci_device == 0x2992 || \
 765                        (dev)->pci_device == 0x29A2 || \
 766                        (dev)->pci_device == 0x2A02 || \
 767                        (dev)->pci_device == 0x2A12 || \
 768                        (dev)->pci_device == 0x2A42 || \
 769                        (dev)->pci_device == 0x2E02 || \
 770                        (dev)->pci_device == 0x2E12 || \
 771                        (dev)->pci_device == 0x2E22)
 772
 773 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 774
 775 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
 776
 777 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 778                      (dev)->pci_device == 0x2E12 || \
 779                      (dev)->pci_device == 0x2E22 || \
 780                      IS_GM45(dev))
 781
 782 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 783                         (dev)->pci_device == 0x29B2 ||  \
 784                         (dev)->pci_device == 0x29D2)
 785
 786 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 787                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
 788
 789 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 790                         IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
 791
 792 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
 793 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 794  * rows, which changed the alignment requirements and fence programming.
 795  */
 796 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
 797                                                       IS_I915GM(dev)))
 798 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev))
 799
 800 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 801
 802 #endif