1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
55 #include "i915_utils.h"
57 #include "intel_bios.h"
58 #include "intel_dpll_mgr.h"
60 #include "intel_lrc.h"
61 #include "intel_ringbuffer.h"
64 #include "i915_gem_context.h"
65 #include "i915_gem_fence_reg.h"
66 #include "i915_gem_object.h"
67 #include "i915_gem_gtt.h"
68 #include "i915_gem_render_state.h"
69 #include "i915_gem_request.h"
70 #include "i915_gem_timeline.h"
74 #include "intel_gvt.h"
76 /* General customization:
79 #define DRIVER_NAME "i915"
80 #define DRIVER_DESC "Intel Graphics"
81 #define DRIVER_DATE "20170123"
82 #define DRIVER_TIMESTAMP 1485156432
85 /* Many gcc seem to no see through this and fall over :( */
87 #define WARN_ON(x) ({ \
88 bool __i915_warn_cond = (x); \
89 if (__builtin_constant_p(__i915_warn_cond)) \
90 BUILD_BUG_ON(__i915_warn_cond); \
91 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
93 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
97 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
99 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
100 (long) (x), __func__);
102 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
103 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
104 * which may not necessarily be a user visible problem. This will either
105 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
106 * enable distros and users to tailor their preferred amount of i915 abrt
109 #define I915_STATE_WARN(condition, format...) ({ \
110 int __ret_warn_on = !!(condition); \
111 if (unlikely(__ret_warn_on)) \
112 if (!WARN(i915.verbose_state_checks, format)) \
114 unlikely(__ret_warn_on); \
117 #define I915_STATE_WARN_ON(x) \
118 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
120 bool __i915_inject_load_failure(const char *func
, int line
);
121 #define i915_inject_load_failure() \
122 __i915_inject_load_failure(__func__, __LINE__)
126 } uint_fixed_16_16_t
;
128 #define FP_16_16_MAX ({ \
129 uint_fixed_16_16_t fp; \
134 static inline uint_fixed_16_16_t
u32_to_fixed_16_16(uint32_t val
)
136 uint_fixed_16_16_t fp
;
144 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp
)
146 return DIV_ROUND_UP(fp
.val
, 1 << 16);
149 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp
)
154 static inline uint_fixed_16_16_t
min_fixed_16_16(uint_fixed_16_16_t min1
,
155 uint_fixed_16_16_t min2
)
157 uint_fixed_16_16_t min
;
159 min
.val
= min(min1
.val
, min2
.val
);
163 static inline uint_fixed_16_16_t
max_fixed_16_16(uint_fixed_16_16_t max1
,
164 uint_fixed_16_16_t max2
)
166 uint_fixed_16_16_t max
;
168 max
.val
= max(max1
.val
, max2
.val
);
172 static inline uint_fixed_16_16_t
fixed_16_16_div_round_up(uint32_t val
,
175 uint_fixed_16_16_t fp
, res
;
177 fp
= u32_to_fixed_16_16(val
);
178 res
.val
= DIV_ROUND_UP(fp
.val
, d
);
182 static inline uint_fixed_16_16_t
fixed_16_16_div_round_up_u64(uint32_t val
,
185 uint_fixed_16_16_t res
;
188 interm_val
= (uint64_t)val
<< 16;
189 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
);
190 WARN_ON(interm_val
>> 32);
191 res
.val
= (uint32_t) interm_val
;
196 static inline uint_fixed_16_16_t
mul_u32_fixed_16_16(uint32_t val
,
197 uint_fixed_16_16_t mul
)
199 uint64_t intermediate_val
;
200 uint_fixed_16_16_t fp
;
202 intermediate_val
= (uint64_t) val
* mul
.val
;
203 WARN_ON(intermediate_val
>> 32);
204 fp
.val
= (uint32_t) intermediate_val
;
208 static inline const char *yesno(bool v
)
210 return v
? "yes" : "no";
213 static inline const char *onoff(bool v
)
215 return v
? "on" : "off";
218 static inline const char *enableddisabled(bool v
)
220 return v
? "enabled" : "disabled";
229 I915_MAX_PIPES
= _PIPE_EDP
231 #define pipe_name(p) ((p) + 'A')
243 static inline const char *transcoder_name(enum transcoder transcoder
)
245 switch (transcoder
) {
254 case TRANSCODER_DSI_A
:
256 case TRANSCODER_DSI_C
:
263 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
265 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
269 * Global legacy plane identifier. Valid only for primary/sprite
270 * planes on pre-g4x, and only for primary planes on g4x+.
277 #define plane_name(p) ((p) + 'A')
279 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
282 * Per-pipe plane identifier.
283 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
284 * number of planes per CRTC. Not all platforms really have this many planes,
285 * which means some arrays of size I915_MAX_PLANES may have unused entries
286 * between the topmost sprite plane and the cursor plane.
288 * This is expected to be passed to various register macros
289 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
299 #define for_each_plane_id_on_crtc(__crtc, __p) \
300 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
301 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
312 #define port_name(p) ((p) + 'A')
314 #define I915_NUM_PHYS_VLV 2
327 enum intel_display_power_domain
{
331 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
332 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
333 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
334 POWER_DOMAIN_TRANSCODER_A
,
335 POWER_DOMAIN_TRANSCODER_B
,
336 POWER_DOMAIN_TRANSCODER_C
,
337 POWER_DOMAIN_TRANSCODER_EDP
,
338 POWER_DOMAIN_TRANSCODER_DSI_A
,
339 POWER_DOMAIN_TRANSCODER_DSI_C
,
340 POWER_DOMAIN_PORT_DDI_A_LANES
,
341 POWER_DOMAIN_PORT_DDI_B_LANES
,
342 POWER_DOMAIN_PORT_DDI_C_LANES
,
343 POWER_DOMAIN_PORT_DDI_D_LANES
,
344 POWER_DOMAIN_PORT_DDI_E_LANES
,
345 POWER_DOMAIN_PORT_DSI
,
346 POWER_DOMAIN_PORT_CRT
,
347 POWER_DOMAIN_PORT_OTHER
,
356 POWER_DOMAIN_MODESET
,
362 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
363 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
364 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
365 #define POWER_DOMAIN_TRANSCODER(tran) \
366 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
367 (tran) + POWER_DOMAIN_TRANSCODER_A)
371 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
383 #define for_each_hpd_pin(__pin) \
384 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
386 struct i915_hotplug
{
387 struct work_struct hotplug_work
;
390 unsigned long last_jiffies
;
395 HPD_MARK_DISABLED
= 2
397 } stats
[HPD_NUM_PINS
];
399 struct delayed_work reenable_work
;
401 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
404 struct work_struct dig_port_work
;
406 struct work_struct poll_init_work
;
410 * if we get a HPD irq from DP and a HPD irq from non-DP
411 * the non-DP HPD could block the workqueue on a mode config
412 * mutex getting, that userspace may have taken. However
413 * userspace is waiting on the DP workqueue to run which is
414 * blocked behind the non-DP one.
416 struct workqueue_struct
*dp_wq
;
419 #define I915_GEM_GPU_DOMAINS \
420 (I915_GEM_DOMAIN_RENDER | \
421 I915_GEM_DOMAIN_SAMPLER | \
422 I915_GEM_DOMAIN_COMMAND | \
423 I915_GEM_DOMAIN_INSTRUCTION | \
424 I915_GEM_DOMAIN_VERTEX)
426 #define for_each_pipe(__dev_priv, __p) \
427 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
428 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
429 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
430 for_each_if ((__mask) & (1 << (__p)))
431 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
433 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
435 #define for_each_sprite(__dev_priv, __p, __s) \
437 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
440 #define for_each_port_masked(__port, __ports_mask) \
441 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
442 for_each_if ((__ports_mask) & (1 << (__port)))
444 #define for_each_crtc(dev, crtc) \
445 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
447 #define for_each_intel_plane(dev, intel_plane) \
448 list_for_each_entry(intel_plane, \
449 &(dev)->mode_config.plane_list, \
452 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
453 list_for_each_entry(intel_plane, \
454 &(dev)->mode_config.plane_list, \
456 for_each_if ((plane_mask) & \
457 (1 << drm_plane_index(&intel_plane->base)))
459 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
460 list_for_each_entry(intel_plane, \
461 &(dev)->mode_config.plane_list, \
463 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
465 #define for_each_intel_crtc(dev, intel_crtc) \
466 list_for_each_entry(intel_crtc, \
467 &(dev)->mode_config.crtc_list, \
470 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
471 list_for_each_entry(intel_crtc, \
472 &(dev)->mode_config.crtc_list, \
474 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
476 #define for_each_intel_encoder(dev, intel_encoder) \
477 list_for_each_entry(intel_encoder, \
478 &(dev)->mode_config.encoder_list, \
481 #define for_each_intel_connector(dev, intel_connector) \
482 list_for_each_entry(intel_connector, \
483 &(dev)->mode_config.connector_list, \
486 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
487 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
488 for_each_if ((intel_encoder)->base.crtc == (__crtc))
490 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
491 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
492 for_each_if ((intel_connector)->base.encoder == (__encoder))
494 #define for_each_power_domain(domain, mask) \
495 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
496 for_each_if ((1 << (domain)) & (mask))
498 struct drm_i915_private
;
499 struct i915_mm_struct
;
500 struct i915_mmu_object
;
502 struct drm_i915_file_private
{
503 struct drm_i915_private
*dev_priv
;
504 struct drm_file
*file
;
508 struct list_head request_list
;
509 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
510 * chosen to prevent the CPU getting more than a frame ahead of the GPU
511 * (when using lax throttling for the frontbuffer). We also use it to
512 * offer free GPU waitboosts for severely congested workloads.
514 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
516 struct idr context_idr
;
518 struct intel_rps_client
{
519 struct list_head link
;
523 unsigned int bsd_engine
;
525 /* Client can have a maximum of 3 contexts banned before
526 * it is denied of creating new contexts. As one context
527 * ban needs 4 consecutive hangs, and more if there is
528 * progress in between, this is a last resort stop gap measure
529 * to limit the badly behaving clients access to gpu.
531 #define I915_MAX_CLIENT_CONTEXT_BANS 3
535 /* Used by dp and fdi links */
536 struct intel_link_m_n
{
544 void intel_link_compute_m_n(int bpp
, int nlanes
,
545 int pixel_clock
, int link_clock
,
546 struct intel_link_m_n
*m_n
);
548 /* Interface history:
551 * 1.2: Add Power Management
552 * 1.3: Add vblank support
553 * 1.4: Fix cmdbuffer path, add heap destroy
554 * 1.5: Add vblank pipe configuration
555 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
556 * - Support vertical blank on secondary display pipe
558 #define DRIVER_MAJOR 1
559 #define DRIVER_MINOR 6
560 #define DRIVER_PATCHLEVEL 0
562 struct opregion_header
;
563 struct opregion_acpi
;
564 struct opregion_swsci
;
565 struct opregion_asle
;
567 struct intel_opregion
{
568 struct opregion_header
*header
;
569 struct opregion_acpi
*acpi
;
570 struct opregion_swsci
*swsci
;
571 u32 swsci_gbda_sub_functions
;
572 u32 swsci_sbcb_sub_functions
;
573 struct opregion_asle
*asle
;
578 struct work_struct asle_work
;
580 #define OPREGION_SIZE (8*1024)
582 struct intel_overlay
;
583 struct intel_overlay_error_state
;
585 struct sdvo_device_mapping
{
594 struct intel_connector
;
595 struct intel_encoder
;
596 struct intel_atomic_state
;
597 struct intel_crtc_state
;
598 struct intel_initial_plane_config
;
603 struct drm_i915_display_funcs
{
604 int (*get_display_clock_speed
)(struct drm_i915_private
*dev_priv
);
605 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
606 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
607 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
608 struct intel_crtc
*intel_crtc
,
609 struct intel_crtc_state
*newstate
);
610 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
611 struct intel_crtc_state
*cstate
);
612 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
613 struct intel_crtc_state
*cstate
);
614 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
615 struct intel_crtc_state
*cstate
);
616 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
617 void (*update_wm
)(struct intel_crtc
*crtc
);
618 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
619 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
620 /* Returns the active state of the crtc, and if the crtc is active,
621 * fills out the pipe-config with the hw state. */
622 bool (*get_pipe_config
)(struct intel_crtc
*,
623 struct intel_crtc_state
*);
624 void (*get_initial_plane_config
)(struct intel_crtc
*,
625 struct intel_initial_plane_config
*);
626 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
627 struct intel_crtc_state
*crtc_state
);
628 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
629 struct drm_atomic_state
*old_state
);
630 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
631 struct drm_atomic_state
*old_state
);
632 void (*update_crtcs
)(struct drm_atomic_state
*state
,
633 unsigned int *crtc_vblank_mask
);
634 void (*audio_codec_enable
)(struct drm_connector
*connector
,
635 struct intel_encoder
*encoder
,
636 const struct drm_display_mode
*adjusted_mode
);
637 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
638 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
639 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
640 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
641 struct drm_framebuffer
*fb
,
642 struct drm_i915_gem_object
*obj
,
643 struct drm_i915_gem_request
*req
,
645 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
646 /* clock updates for mode set */
648 /* render clock increase/decrease */
649 /* display clock increase/decrease */
650 /* pll clock increase/decrease */
652 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
653 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
656 enum forcewake_domain_id
{
657 FW_DOMAIN_ID_RENDER
= 0,
658 FW_DOMAIN_ID_BLITTER
,
664 enum forcewake_domains
{
665 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
666 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
667 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
668 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
673 #define FW_REG_READ (1)
674 #define FW_REG_WRITE (2)
676 enum decoupled_power_domain
{
677 GEN9_DECOUPLED_PD_BLITTER
= 0,
678 GEN9_DECOUPLED_PD_RENDER
,
679 GEN9_DECOUPLED_PD_MEDIA
,
680 GEN9_DECOUPLED_PD_ALL
684 GEN9_DECOUPLED_OP_WRITE
= 0,
685 GEN9_DECOUPLED_OP_READ
688 enum forcewake_domains
689 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
690 i915_reg_t reg
, unsigned int op
);
692 struct intel_uncore_funcs
{
693 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
694 enum forcewake_domains domains
);
695 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
696 enum forcewake_domains domains
);
698 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
699 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
700 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
701 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
703 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
704 uint8_t val
, bool trace
);
705 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
706 uint16_t val
, bool trace
);
707 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
708 uint32_t val
, bool trace
);
711 struct intel_forcewake_range
{
715 enum forcewake_domains domains
;
718 struct intel_uncore
{
719 spinlock_t lock
; /** lock is also taken in irq contexts. */
721 const struct intel_forcewake_range
*fw_domains_table
;
722 unsigned int fw_domains_table_entries
;
724 struct intel_uncore_funcs funcs
;
728 enum forcewake_domains fw_domains
;
729 enum forcewake_domains fw_domains_active
;
731 struct intel_uncore_forcewake_domain
{
732 struct drm_i915_private
*i915
;
733 enum forcewake_domain_id id
;
734 enum forcewake_domains mask
;
736 struct hrtimer timer
;
743 } fw_domain
[FW_DOMAIN_ID_COUNT
];
745 int unclaimed_mmio_check
;
748 /* Iterate over initialised fw domains */
749 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
750 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
751 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
753 for_each_if ((mask__) & (domain__)->mask)
755 #define for_each_fw_domain(domain__, dev_priv__) \
756 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
758 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
759 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
760 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
763 struct work_struct work
;
765 uint32_t *dmc_payload
;
766 uint32_t dmc_fw_size
;
769 i915_reg_t mmioaddr
[8];
770 uint32_t mmiodata
[8];
772 uint32_t allowed_dc_mask
;
775 #define DEV_INFO_FOR_EACH_FLAG(func) \
778 func(is_alpha_support); \
779 /* Keep has_* in alphabetical order */ \
780 func(has_64bit_reloc); \
781 func(has_aliasing_ppgtt); \
784 func(has_decoupled_mmio); \
787 func(has_fpga_dbg); \
788 func(has_full_ppgtt); \
789 func(has_full_48bit_ppgtt); \
790 func(has_gmbus_irq); \
791 func(has_gmch_display); \
794 func(has_hw_contexts); \
797 func(has_logical_ring_contexts); \
799 func(has_pipe_cxsr); \
800 func(has_pooled_eu); \
804 func(has_resource_streamer); \
805 func(has_runtime_pm); \
807 func(cursor_needs_physical); \
808 func(hws_needs_physical); \
809 func(overlay_needs_physical); \
812 struct sseu_dev_info
{
818 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
821 u8 has_subslice_pg
:1;
825 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
827 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
830 /* Keep in gen based order, and chronological order within a gen */
831 enum intel_platform
{
832 INTEL_PLATFORM_UNINITIALIZED
= 0,
860 struct intel_device_info
{
861 u32 display_mmio_offset
;
864 u8 num_sprites
[I915_MAX_PIPES
];
865 u8 num_scalers
[I915_MAX_PIPES
];
868 enum intel_platform platform
;
869 u8 ring_mask
; /* Rings supported by the HW */
871 #define DEFINE_FLAG(name) u8 name:1
872 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
874 u16 ddb_size
; /* in blocks */
875 /* Register offsets for the various display pipes and transcoders */
876 int pipe_offsets
[I915_MAX_TRANSCODERS
];
877 int trans_offsets
[I915_MAX_TRANSCODERS
];
878 int palette_offsets
[I915_MAX_PIPES
];
879 int cursor_offsets
[I915_MAX_PIPES
];
881 /* Slice/subslice/EU info */
882 struct sseu_dev_info sseu
;
885 u16 degamma_lut_size
;
890 struct intel_display_error_state
;
892 struct drm_i915_error_state
{
895 struct timeval boottime
;
896 struct timeval uptime
;
898 struct drm_i915_private
*i915
;
905 struct intel_device_info device_info
;
907 /* Generic register state */
915 u32 error
; /* gen6+ */
916 u32 err_int
; /* gen7 */
917 u32 fault_data0
; /* gen8, gen9 */
918 u32 fault_data1
; /* gen8, gen9 */
925 u64 fence
[I915_MAX_NUM_FENCES
];
926 struct intel_overlay_error_state
*overlay
;
927 struct intel_display_error_state
*display
;
928 struct drm_i915_error_object
*semaphore
;
929 struct drm_i915_error_object
*guc_log
;
931 struct drm_i915_error_engine
{
933 /* Software tracked state */
936 unsigned long hangcheck_timestamp
;
937 bool hangcheck_stalled
;
938 enum intel_engine_hangcheck_action hangcheck_action
;
939 struct i915_address_space
*vm
;
942 /* position of active request inside the ring */
943 u32 rq_head
, rq_post
, rq_tail
;
945 /* our own tracking of ring head and tail */
968 u32 rc_psmi
; /* sleep state */
969 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
970 struct intel_instdone instdone
;
972 struct drm_i915_error_object
{
978 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
980 struct drm_i915_error_object
*wa_ctx
;
982 struct drm_i915_error_request
{
990 } *requests
, execlist
[2];
992 struct drm_i915_error_waiter
{
993 char comm
[TASK_COMM_LEN
];
1007 char comm
[TASK_COMM_LEN
];
1009 } engine
[I915_NUM_ENGINES
];
1011 struct drm_i915_error_buffer
{
1014 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
1018 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1025 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
1026 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
1027 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
1030 enum i915_cache_level
{
1031 I915_CACHE_NONE
= 0,
1032 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
1033 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
1034 caches, eg sampler/render caches, and the
1035 large Last-Level-Cache. LLC is coherent with
1036 the CPU, but L3 is only visible to the GPU. */
1037 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
1040 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1051 /* This is always the inner lock when overlapping with struct_mutex and
1052 * it's the outer lock when overlapping with stolen_lock. */
1055 unsigned int possible_framebuffer_bits
;
1056 unsigned int busy_bits
;
1057 unsigned int visible_pipes_mask
;
1058 struct intel_crtc
*crtc
;
1060 struct drm_mm_node compressed_fb
;
1061 struct drm_mm_node
*compressed_llb
;
1068 bool underrun_detected
;
1069 struct work_struct underrun_work
;
1071 struct intel_fbc_state_cache
{
1072 struct i915_vma
*vma
;
1075 unsigned int mode_flags
;
1076 uint32_t hsw_bdw_pixel_rate
;
1080 unsigned int rotation
;
1087 const struct drm_format_info
*format
;
1088 unsigned int stride
;
1092 struct intel_fbc_reg_params
{
1093 struct i915_vma
*vma
;
1098 unsigned int fence_y_offset
;
1102 const struct drm_format_info
*format
;
1103 unsigned int stride
;
1109 struct intel_fbc_work
{
1111 u32 scheduled_vblank
;
1112 struct work_struct work
;
1115 const char *no_fbc_reason
;
1119 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1120 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1121 * parsing for same resolution.
1123 enum drrs_refresh_rate_type
{
1126 DRRS_MAX_RR
, /* RR count */
1129 enum drrs_support_type
{
1130 DRRS_NOT_SUPPORTED
= 0,
1131 STATIC_DRRS_SUPPORT
= 1,
1132 SEAMLESS_DRRS_SUPPORT
= 2
1138 struct delayed_work work
;
1139 struct intel_dp
*dp
;
1140 unsigned busy_frontbuffer_bits
;
1141 enum drrs_refresh_rate_type refresh_rate_type
;
1142 enum drrs_support_type type
;
1149 struct intel_dp
*enabled
;
1151 struct delayed_work work
;
1152 unsigned busy_frontbuffer_bits
;
1154 bool aux_frame_sync
;
1156 bool y_cord_support
;
1157 bool colorimetry_support
;
1162 PCH_NONE
= 0, /* No PCH present */
1163 PCH_IBX
, /* Ibexpeak PCH */
1164 PCH_CPT
, /* Cougarpoint PCH */
1165 PCH_LPT
, /* Lynxpoint PCH */
1166 PCH_SPT
, /* Sunrisepoint PCH */
1167 PCH_KBP
, /* Kabypoint PCH */
1171 enum intel_sbi_destination
{
1176 #define QUIRK_PIPEA_FORCE (1<<0)
1177 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1178 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1179 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1180 #define QUIRK_PIPEB_FORCE (1<<4)
1181 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1184 struct intel_fbc_work
;
1186 struct intel_gmbus
{
1187 struct i2c_adapter adapter
;
1188 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1191 i915_reg_t gpio_reg
;
1192 struct i2c_algo_bit_data bit_algo
;
1193 struct drm_i915_private
*dev_priv
;
1196 struct i915_suspend_saved_registers
{
1198 u32 saveFBC_CONTROL
;
1199 u32 saveCACHE_MODE_0
;
1200 u32 saveMI_ARB_STATE
;
1204 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1205 u32 savePCH_PORT_HOTPLUG
;
1209 struct vlv_s0ix_state
{
1216 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1217 u32 media_max_req_count
;
1218 u32 gfx_max_req_count
;
1244 u32 rp_down_timeout
;
1250 /* Display 1 CZ domain */
1255 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1257 /* GT SA CZ domain */
1264 /* Display 2 CZ domain */
1268 u32 clock_gate_dis2
;
1271 struct intel_rps_ei
{
1277 struct intel_gen6_power_mgmt
{
1279 * work, interrupts_enabled and pm_iir are protected by
1280 * dev_priv->irq_lock
1282 struct work_struct work
;
1283 bool interrupts_enabled
;
1286 /* PM interrupt bits that should never be masked */
1289 /* Frequencies are stored in potentially platform dependent multiples.
1290 * In other words, *_freq needs to be multiplied by X to be interesting.
1291 * Soft limits are those which are used for the dynamic reclocking done
1292 * by the driver (raise frequencies under heavy loads, and lower for
1293 * lighter loads). Hard limits are those imposed by the hardware.
1295 * A distinction is made for overclocking, which is never enabled by
1296 * default, and is considered to be above the hard limit if it's
1299 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1300 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1301 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1302 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1303 u8 min_freq
; /* AKA RPn. Minimum frequency */
1304 u8 boost_freq
; /* Frequency to request when wait boosting */
1305 u8 idle_freq
; /* Frequency to request when we are idle */
1306 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1307 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1308 u8 rp0_freq
; /* Non-overclocked max frequency. */
1309 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1311 u8 up_threshold
; /* Current %busy required to uplock */
1312 u8 down_threshold
; /* Current %busy required to downclock */
1315 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1317 spinlock_t client_lock
;
1318 struct list_head clients
;
1322 struct delayed_work autoenable_work
;
1325 /* manual wa residency calculations */
1326 struct intel_rps_ei up_ei
, down_ei
;
1329 * Protects RPS/RC6 register access and PCU communication.
1330 * Must be taken after struct_mutex if nested. Note that
1331 * this lock may be held for long periods of time when
1332 * talking to hw - so only take it when talking to hw!
1334 struct mutex hw_lock
;
1337 /* defined intel_pm.c */
1338 extern spinlock_t mchdev_lock
;
1340 struct intel_ilk_power_mgmt
{
1348 unsigned long last_time1
;
1349 unsigned long chipset_power
;
1352 unsigned long gfx_power
;
1359 struct drm_i915_private
;
1360 struct i915_power_well
;
1362 struct i915_power_well_ops
{
1364 * Synchronize the well's hw state to match the current sw state, for
1365 * example enable/disable it based on the current refcount. Called
1366 * during driver init and resume time, possibly after first calling
1367 * the enable/disable handlers.
1369 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1370 struct i915_power_well
*power_well
);
1372 * Enable the well and resources that depend on it (for example
1373 * interrupts located on the well). Called after the 0->1 refcount
1376 void (*enable
)(struct drm_i915_private
*dev_priv
,
1377 struct i915_power_well
*power_well
);
1379 * Disable the well and resources that depend on it. Called after
1380 * the 1->0 refcount transition.
1382 void (*disable
)(struct drm_i915_private
*dev_priv
,
1383 struct i915_power_well
*power_well
);
1384 /* Returns the hw enabled state. */
1385 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1386 struct i915_power_well
*power_well
);
1389 /* Power well structure for haswell */
1390 struct i915_power_well
{
1393 /* power well enable/disable usage count */
1395 /* cached hw enabled state */
1397 unsigned long domains
;
1398 /* unique identifier for this power well */
1401 * Arbitraty data associated with this power well. Platform and power
1405 const struct i915_power_well_ops
*ops
;
1408 struct i915_power_domains
{
1410 * Power wells needed for initialization at driver init and suspend
1411 * time are on. They are kept on until after the first modeset.
1415 int power_well_count
;
1418 int domain_use_count
[POWER_DOMAIN_NUM
];
1419 struct i915_power_well
*power_wells
;
1422 #define MAX_L3_SLICES 2
1423 struct intel_l3_parity
{
1424 u32
*remap_info
[MAX_L3_SLICES
];
1425 struct work_struct error_work
;
1429 struct i915_gem_mm
{
1430 /** Memory allocator for GTT stolen memory */
1431 struct drm_mm stolen
;
1432 /** Protects the usage of the GTT stolen memory allocator. This is
1433 * always the inner lock when overlapping with struct_mutex. */
1434 struct mutex stolen_lock
;
1436 /** List of all objects in gtt_space. Used to restore gtt
1437 * mappings on resume */
1438 struct list_head bound_list
;
1440 * List of objects which are not bound to the GTT (thus
1441 * are idle and not used by the GPU). These objects may or may
1442 * not actually have any pages attached.
1444 struct list_head unbound_list
;
1446 /** List of all objects in gtt_space, currently mmaped by userspace.
1447 * All objects within this list must also be on bound_list.
1449 struct list_head userfault_list
;
1452 * List of objects which are pending destruction.
1454 struct llist_head free_list
;
1455 struct work_struct free_work
;
1457 /** Usable portion of the GTT for GEM */
1458 phys_addr_t stolen_base
; /* limited to low memory (32-bit) */
1460 /** PPGTT used for aliasing the PPGTT with the GTT */
1461 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1463 struct notifier_block oom_notifier
;
1464 struct notifier_block vmap_notifier
;
1465 struct shrinker shrinker
;
1467 /** LRU list of objects with fence regs on them. */
1468 struct list_head fence_list
;
1471 * Are we in a non-interruptible section of code like
1476 /* the indicator for dispatch video commands on two BSD rings */
1477 atomic_t bsd_engine_dispatch_index
;
1479 /** Bit 6 swizzling required for X tiling */
1480 uint32_t bit_6_swizzle_x
;
1481 /** Bit 6 swizzling required for Y tiling */
1482 uint32_t bit_6_swizzle_y
;
1484 /* accounting, useful for userland debugging */
1485 spinlock_t object_stat_lock
;
1490 struct drm_i915_error_state_buf
{
1491 struct drm_i915_private
*i915
;
1500 struct i915_error_state_file_priv
{
1501 struct drm_i915_private
*i915
;
1502 struct drm_i915_error_state
*error
;
1505 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1506 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1508 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1509 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1511 struct i915_gpu_error
{
1512 /* For hangcheck timer */
1513 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1514 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1516 struct delayed_work hangcheck_work
;
1518 /* For reset and error_state handling. */
1520 /* Protected by the above dev->gpu_error.lock. */
1521 struct drm_i915_error_state
*first_error
;
1523 unsigned long missed_irq_rings
;
1526 * State variable controlling the reset flow and count
1528 * This is a counter which gets incremented when reset is triggered,
1530 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1531 * meaning that any waiters holding onto the struct_mutex should
1532 * relinquish the lock immediately in order for the reset to start.
1534 * If reset is not completed succesfully, the I915_WEDGE bit is
1535 * set meaning that hardware is terminally sour and there is no
1536 * recovery. All waiters on the reset_queue will be woken when
1539 * This counter is used by the wait_seqno code to notice that reset
1540 * event happened and it needs to restart the entire ioctl (since most
1541 * likely the seqno it waited for won't ever signal anytime soon).
1543 * This is important for lock-free wait paths, where no contended lock
1544 * naturally enforces the correct ordering between the bail-out of the
1545 * waiter and the gpu reset work code.
1547 unsigned long reset_count
;
1549 unsigned long flags
;
1550 #define I915_RESET_IN_PROGRESS 0
1551 #define I915_WEDGED (BITS_PER_LONG - 1)
1554 * Waitqueue to signal when a hang is detected. Used to for waiters
1555 * to release the struct_mutex for the reset to procede.
1557 wait_queue_head_t wait_queue
;
1560 * Waitqueue to signal when the reset has completed. Used by clients
1561 * that wait for dev_priv->mm.wedged to settle.
1563 wait_queue_head_t reset_queue
;
1565 /* For missed irq/seqno simulation. */
1566 unsigned long test_irq_rings
;
1569 enum modeset_restore
{
1570 MODESET_ON_LID_OPEN
,
1575 #define DP_AUX_A 0x40
1576 #define DP_AUX_B 0x10
1577 #define DP_AUX_C 0x20
1578 #define DP_AUX_D 0x30
1580 #define DDC_PIN_B 0x05
1581 #define DDC_PIN_C 0x04
1582 #define DDC_PIN_D 0x06
1584 struct ddi_vbt_port_info
{
1586 * This is an index in the HDMI/DVI DDI buffer translation table.
1587 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1588 * populate this field.
1590 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1591 uint8_t hdmi_level_shift
;
1593 uint8_t supports_dvi
:1;
1594 uint8_t supports_hdmi
:1;
1595 uint8_t supports_dp
:1;
1596 uint8_t supports_edp
:1;
1598 uint8_t alternate_aux_channel
;
1599 uint8_t alternate_ddc_pin
;
1601 uint8_t dp_boost_level
;
1602 uint8_t hdmi_boost_level
;
1605 enum psr_lines_to_wait
{
1606 PSR_0_LINES_TO_WAIT
= 0,
1608 PSR_4_LINES_TO_WAIT
,
1612 struct intel_vbt_data
{
1613 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1614 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1617 unsigned int int_tv_support
:1;
1618 unsigned int lvds_dither
:1;
1619 unsigned int lvds_vbt
:1;
1620 unsigned int int_crt_support
:1;
1621 unsigned int lvds_use_ssc
:1;
1622 unsigned int display_clock_mode
:1;
1623 unsigned int fdi_rx_polarity_inverted
:1;
1624 unsigned int panel_type
:4;
1626 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1628 enum drrs_support_type drrs_type
;
1639 struct edp_power_seq pps
;
1644 bool require_aux_wakeup
;
1646 enum psr_lines_to_wait lines_to_wait
;
1647 int tp1_wakeup_time
;
1648 int tp2_tp3_wakeup_time
;
1654 bool active_low_pwm
;
1655 u8 min_brightness
; /* min_brightness/255 of max */
1656 u8 controller
; /* brightness controller number */
1657 enum intel_backlight_type type
;
1663 struct mipi_config
*config
;
1664 struct mipi_pps_data
*pps
;
1668 const u8
*sequence
[MIPI_SEQ_MAX
];
1674 union child_device_config
*child_dev
;
1676 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1677 struct sdvo_device_mapping sdvo_mappings
[2];
1680 enum intel_ddb_partitioning
{
1682 INTEL_DDB_PART_5_6
, /* IVB+ */
1685 struct intel_wm_level
{
1693 struct ilk_wm_values
{
1694 uint32_t wm_pipe
[3];
1696 uint32_t wm_lp_spr
[3];
1697 uint32_t wm_linetime
[3];
1699 enum intel_ddb_partitioning partitioning
;
1702 struct vlv_pipe_wm
{
1703 uint16_t plane
[I915_MAX_PLANES
];
1711 struct vlv_wm_ddl_values
{
1712 uint8_t plane
[I915_MAX_PLANES
];
1715 struct vlv_wm_values
{
1716 struct vlv_pipe_wm pipe
[3];
1717 struct vlv_sr_wm sr
;
1718 struct vlv_wm_ddl_values ddl
[3];
1723 struct skl_ddb_entry
{
1724 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1727 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1729 return entry
->end
- entry
->start
;
1732 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1733 const struct skl_ddb_entry
*e2
)
1735 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1741 struct skl_ddb_allocation
{
1742 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1743 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1746 struct skl_wm_values
{
1747 unsigned dirty_pipes
;
1748 struct skl_ddb_allocation ddb
;
1751 struct skl_wm_level
{
1753 uint16_t plane_res_b
;
1754 uint8_t plane_res_l
;
1758 * This struct helps tracking the state needed for runtime PM, which puts the
1759 * device in PCI D3 state. Notice that when this happens, nothing on the
1760 * graphics device works, even register access, so we don't get interrupts nor
1763 * Every piece of our code that needs to actually touch the hardware needs to
1764 * either call intel_runtime_pm_get or call intel_display_power_get with the
1765 * appropriate power domain.
1767 * Our driver uses the autosuspend delay feature, which means we'll only really
1768 * suspend if we stay with zero refcount for a certain amount of time. The
1769 * default value is currently very conservative (see intel_runtime_pm_enable), but
1770 * it can be changed with the standard runtime PM files from sysfs.
1772 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1773 * goes back to false exactly before we reenable the IRQs. We use this variable
1774 * to check if someone is trying to enable/disable IRQs while they're supposed
1775 * to be disabled. This shouldn't happen and we'll print some error messages in
1778 * For more, read the Documentation/power/runtime_pm.txt.
1780 struct i915_runtime_pm
{
1781 atomic_t wakeref_count
;
1786 enum intel_pipe_crc_source
{
1787 INTEL_PIPE_CRC_SOURCE_NONE
,
1788 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1789 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1790 INTEL_PIPE_CRC_SOURCE_PF
,
1791 INTEL_PIPE_CRC_SOURCE_PIPE
,
1792 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1793 INTEL_PIPE_CRC_SOURCE_TV
,
1794 INTEL_PIPE_CRC_SOURCE_DP_B
,
1795 INTEL_PIPE_CRC_SOURCE_DP_C
,
1796 INTEL_PIPE_CRC_SOURCE_DP_D
,
1797 INTEL_PIPE_CRC_SOURCE_AUTO
,
1798 INTEL_PIPE_CRC_SOURCE_MAX
,
1801 struct intel_pipe_crc_entry
{
1806 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1807 struct intel_pipe_crc
{
1809 bool opened
; /* exclusive access to the result file */
1810 struct intel_pipe_crc_entry
*entries
;
1811 enum intel_pipe_crc_source source
;
1813 wait_queue_head_t wq
;
1817 struct i915_frontbuffer_tracking
{
1821 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1828 struct i915_wa_reg
{
1831 /* bitmask representing WA bits */
1836 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1837 * allowing it for RCS as we don't foresee any requirement of having
1838 * a whitelist for other engines. When it is really required for
1839 * other engines then the limit need to be increased.
1841 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1843 struct i915_workarounds
{
1844 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1846 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1849 struct i915_virtual_gpu
{
1853 /* used in computing the new watermarks state */
1854 struct intel_wm_config
{
1855 unsigned int num_pipes_active
;
1856 bool sprites_enabled
;
1857 bool sprites_scaled
;
1860 struct i915_oa_format
{
1865 struct i915_oa_reg
{
1870 struct i915_perf_stream
;
1873 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1875 struct i915_perf_stream_ops
{
1877 * @enable: Enables the collection of HW samples, either in response to
1878 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1879 * without `I915_PERF_FLAG_DISABLED`.
1881 void (*enable
)(struct i915_perf_stream
*stream
);
1884 * @disable: Disables the collection of HW samples, either in response
1885 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1888 void (*disable
)(struct i915_perf_stream
*stream
);
1891 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1892 * once there is something ready to read() for the stream
1894 void (*poll_wait
)(struct i915_perf_stream
*stream
,
1899 * @wait_unlocked: For handling a blocking read, wait until there is
1900 * something to ready to read() for the stream. E.g. wait on the same
1901 * wait queue that would be passed to poll_wait().
1903 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
1906 * @read: Copy buffered metrics as records to userspace
1907 * **buf**: the userspace, destination buffer
1908 * **count**: the number of bytes to copy, requested by userspace
1909 * **offset**: zero at the start of the read, updated as the read
1910 * proceeds, it represents how many bytes have been copied so far and
1911 * the buffer offset for copying the next record.
1913 * Copy as many buffered i915 perf samples and records for this stream
1914 * to userspace as will fit in the given buffer.
1916 * Only write complete records; returning -%ENOSPC if there isn't room
1917 * for a complete record.
1919 * Return any error condition that results in a short read such as
1920 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1921 * returning to userspace.
1923 int (*read
)(struct i915_perf_stream
*stream
,
1929 * @destroy: Cleanup any stream specific resources.
1931 * The stream will always be disabled before this is called.
1933 void (*destroy
)(struct i915_perf_stream
*stream
);
1937 * struct i915_perf_stream - state for a single open stream FD
1939 struct i915_perf_stream
{
1941 * @dev_priv: i915 drm device
1943 struct drm_i915_private
*dev_priv
;
1946 * @link: Links the stream into ``&drm_i915_private->streams``
1948 struct list_head link
;
1951 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1952 * properties given when opening a stream, representing the contents
1953 * of a single sample as read() by userspace.
1958 * @sample_size: Considering the configured contents of a sample
1959 * combined with the required header size, this is the total size
1960 * of a single sample record.
1965 * @ctx: %NULL if measuring system-wide across all contexts or a
1966 * specific context that is being monitored.
1968 struct i915_gem_context
*ctx
;
1971 * @enabled: Whether the stream is currently enabled, considering
1972 * whether the stream was opened in a disabled state and based
1973 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1978 * @ops: The callbacks providing the implementation of this specific
1979 * type of configured stream.
1981 const struct i915_perf_stream_ops
*ops
;
1985 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1987 struct i915_oa_ops
{
1989 * @init_oa_buffer: Resets the head and tail pointers of the
1990 * circular buffer for periodic OA reports.
1992 * Called when first opening a stream for OA metrics, but also may be
1993 * called in response to an OA buffer overflow or other error
1996 * Note it may be necessary to clear the full OA buffer here as part of
1997 * maintaining the invariable that new reports must be written to
1998 * zeroed memory for us to be able to reliable detect if an expected
1999 * report has not yet landed in memory. (At least on Haswell the OA
2000 * buffer tail pointer is not synchronized with reports being visible
2003 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
2006 * @enable_metric_set: Applies any MUX configuration to set up the
2007 * Boolean and Custom (B/C) counters that are part of the counter
2008 * reports being sampled. May apply system constraints such as
2009 * disabling EU clock gating as required.
2011 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
);
2014 * @disable_metric_set: Remove system constraints associated with using
2017 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
2020 * @oa_enable: Enable periodic sampling
2022 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
2025 * @oa_disable: Disable periodic sampling
2027 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
2030 * @read: Copy data from the circular OA buffer into a given userspace
2033 int (*read
)(struct i915_perf_stream
*stream
,
2039 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
2041 * This is either called via fops or the poll check hrtimer (atomic
2042 * ctx) without any locks taken.
2044 * It's safe to read OA config state here unlocked, assuming that this
2045 * is only called while the stream is enabled, while the global OA
2046 * configuration can't be modified.
2048 * Efficiency is more important than avoiding some false positives
2049 * here, which will be handled gracefully - likely resulting in an
2050 * %EAGAIN error for userspace.
2052 bool (*oa_buffer_is_empty
)(struct drm_i915_private
*dev_priv
);
2055 struct drm_i915_private
{
2056 struct drm_device drm
;
2058 struct kmem_cache
*objects
;
2059 struct kmem_cache
*vmas
;
2060 struct kmem_cache
*requests
;
2061 struct kmem_cache
*dependencies
;
2063 const struct intel_device_info info
;
2065 int relative_constants_mode
;
2069 struct intel_uncore uncore
;
2071 struct i915_virtual_gpu vgpu
;
2073 struct intel_gvt
*gvt
;
2075 struct intel_huc huc
;
2076 struct intel_guc guc
;
2078 struct intel_csr csr
;
2080 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
2082 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2083 * controller on different i2c buses. */
2084 struct mutex gmbus_mutex
;
2087 * Base address of the gmbus and gpio block.
2089 uint32_t gpio_mmio_base
;
2091 /* MMIO base address for MIPI regs */
2092 uint32_t mipi_mmio_base
;
2094 uint32_t psr_mmio_base
;
2096 uint32_t pps_mmio_base
;
2098 wait_queue_head_t gmbus_wait_queue
;
2100 struct pci_dev
*bridge_dev
;
2101 struct i915_gem_context
*kernel_context
;
2102 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
2103 struct i915_vma
*semaphore
;
2105 struct drm_dma_handle
*status_page_dmah
;
2106 struct resource mch_res
;
2108 /* protects the irq masks */
2109 spinlock_t irq_lock
;
2111 /* protects the mmio flip data */
2112 spinlock_t mmio_flip_lock
;
2114 bool display_irqs_enabled
;
2116 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2117 struct pm_qos_request pm_qos
;
2119 /* Sideband mailbox protection */
2120 struct mutex sb_lock
;
2122 /** Cached value of IMR to avoid reads in updating the bitfield */
2125 u32 de_irq_mask
[I915_MAX_PIPES
];
2132 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
2134 struct i915_hotplug hotplug
;
2135 struct intel_fbc fbc
;
2136 struct i915_drrs drrs
;
2137 struct intel_opregion opregion
;
2138 struct intel_vbt_data vbt
;
2140 bool preserve_bios_swizzle
;
2143 struct intel_overlay
*overlay
;
2145 /* backlight registers and fields in struct intel_panel */
2146 struct mutex backlight_lock
;
2149 bool no_aux_handshake
;
2151 /* protects panel power sequencer state */
2152 struct mutex pps_mutex
;
2154 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2155 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2157 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2158 unsigned int skl_preferred_vco_freq
;
2159 unsigned int cdclk_freq
, max_cdclk_freq
;
2162 * For reading holding any crtc lock is sufficient,
2163 * for writing must hold all of them.
2165 unsigned int atomic_cdclk_freq
;
2167 unsigned int max_dotclk_freq
;
2168 unsigned int rawclk_freq
;
2169 unsigned int hpll_freq
;
2170 unsigned int czclk_freq
;
2173 unsigned int vco
, ref
;
2177 * wq - Driver workqueue for GEM.
2179 * NOTE: Work items scheduled here are not allowed to grab any modeset
2180 * locks, for otherwise the flushing done in the pageflip code will
2181 * result in deadlocks.
2183 struct workqueue_struct
*wq
;
2185 /* Display functions */
2186 struct drm_i915_display_funcs display
;
2188 /* PCH chipset type */
2189 enum intel_pch pch_type
;
2190 unsigned short pch_id
;
2192 unsigned long quirks
;
2194 enum modeset_restore modeset_restore
;
2195 struct mutex modeset_restore_lock
;
2196 struct drm_atomic_state
*modeset_restore_state
;
2197 struct drm_modeset_acquire_ctx reset_ctx
;
2199 struct list_head vm_list
; /* Global list of all address spaces */
2200 struct i915_ggtt ggtt
; /* VM representing the global address space */
2202 struct i915_gem_mm mm
;
2203 DECLARE_HASHTABLE(mm_structs
, 7);
2204 struct mutex mm_lock
;
2206 /* The hw wants to have a stable context identifier for the lifetime
2207 * of the context (for OA, PASID, faults, etc). This is limited
2208 * in execlists to 21 bits.
2210 struct ida context_hw_ida
;
2211 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2213 /* Kernel Modesetting */
2215 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2216 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2217 wait_queue_head_t pending_flip_queue
;
2219 #ifdef CONFIG_DEBUG_FS
2220 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2223 /* dpll and cdclk state is protected by connection_mutex */
2224 int num_shared_dpll
;
2225 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2226 const struct intel_dpll_mgr
*dpll_mgr
;
2229 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2230 * Must be global rather than per dpll, because on some platforms
2231 * plls share registers.
2233 struct mutex dpll_lock
;
2235 unsigned int active_crtcs
;
2236 unsigned int min_pixclk
[I915_MAX_PIPES
];
2238 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2240 struct i915_workarounds workarounds
;
2242 struct i915_frontbuffer_tracking fb_tracking
;
2244 struct intel_atomic_helper
{
2245 struct llist_head free_list
;
2246 struct work_struct free_work
;
2251 bool mchbar_need_disable
;
2253 struct intel_l3_parity l3_parity
;
2255 /* Cannot be determined by PCIID. You must always read a register. */
2258 /* gen6+ rps state */
2259 struct intel_gen6_power_mgmt rps
;
2261 /* ilk-only ips/rps state. Everything in here is protected by the global
2262 * mchdev_lock in intel_pm.c */
2263 struct intel_ilk_power_mgmt ips
;
2265 struct i915_power_domains power_domains
;
2267 struct i915_psr psr
;
2269 struct i915_gpu_error gpu_error
;
2271 struct drm_i915_gem_object
*vlv_pctx
;
2273 #ifdef CONFIG_DRM_FBDEV_EMULATION
2274 /* list of fbdev register on this device */
2275 struct intel_fbdev
*fbdev
;
2276 struct work_struct fbdev_suspend_work
;
2279 struct drm_property
*broadcast_rgb_property
;
2280 struct drm_property
*force_audio_property
;
2282 /* hda/i915 audio component */
2283 struct i915_audio_component
*audio_component
;
2284 bool audio_component_registered
;
2286 * av_mutex - mutex for audio/video sync
2289 struct mutex av_mutex
;
2291 uint32_t hw_context_size
;
2292 struct list_head context_list
;
2296 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2297 u32 chv_phy_control
;
2299 * Shadows for CHV DPLL_MD regs to keep the state
2300 * checker somewhat working in the presence hardware
2301 * crappiness (can't read out DPLL_MD for pipes B & C).
2303 u32 chv_dpll_md
[I915_MAX_PIPES
];
2307 bool suspended_to_idle
;
2308 struct i915_suspend_saved_registers regfile
;
2309 struct vlv_s0ix_state vlv_s0ix_state
;
2312 I915_SAGV_UNKNOWN
= 0,
2315 I915_SAGV_NOT_CONTROLLED
2319 /* protects DSPARB registers on pre-g4x/vlv/chv */
2320 spinlock_t dsparb_lock
;
2323 * Raw watermark latency values:
2324 * in 0.1us units for WM0,
2325 * in 0.5us units for WM1+.
2328 uint16_t pri_latency
[5];
2330 uint16_t spr_latency
[5];
2332 uint16_t cur_latency
[5];
2334 * Raw watermark memory latency values
2335 * for SKL for all 8 levels
2338 uint16_t skl_latency
[8];
2340 /* current hardware state */
2342 struct ilk_wm_values hw
;
2343 struct skl_wm_values skl_hw
;
2344 struct vlv_wm_values vlv
;
2350 * Should be held around atomic WM register writing; also
2351 * protects * intel_crtc->wm.active and
2352 * cstate->wm.need_postvbl_update.
2354 struct mutex wm_mutex
;
2357 * Set during HW readout of watermarks/DDB. Some platforms
2358 * need to know when we're still using BIOS-provided values
2359 * (which we don't fully trust).
2361 bool distrust_bios_wm
;
2364 struct i915_runtime_pm pm
;
2369 struct kobject
*metrics_kobj
;
2370 struct ctl_table_header
*sysctl_header
;
2373 struct list_head streams
;
2375 spinlock_t hook_lock
;
2378 struct i915_perf_stream
*exclusive_stream
;
2380 u32 specific_ctx_id
;
2382 struct hrtimer poll_check_timer
;
2383 wait_queue_head_t poll_wq
;
2387 int period_exponent
;
2388 int timestamp_frequency
;
2394 const struct i915_oa_reg
*mux_regs
;
2396 const struct i915_oa_reg
*b_counter_regs
;
2397 int b_counter_regs_len
;
2400 struct i915_vma
*vma
;
2406 u32 gen7_latched_oastatus1
;
2408 struct i915_oa_ops ops
;
2409 const struct i915_oa_format
*oa_formats
;
2414 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2416 void (*resume
)(struct drm_i915_private
*);
2417 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2419 struct list_head timelines
;
2420 struct i915_gem_timeline global_timeline
;
2421 u32 active_requests
;
2424 * Is the GPU currently considered idle, or busy executing
2425 * userspace requests? Whilst idle, we allow runtime power
2426 * management to power down the hardware and display clocks.
2427 * In order to reduce the effect on performance, there
2428 * is a slight delay before we do so.
2433 * We leave the user IRQ off as much as possible,
2434 * but this means that requests will finish and never
2435 * be retired once the system goes idle. Set a timer to
2436 * fire periodically while the ring is running. When it
2437 * fires, go retire requests.
2439 struct delayed_work retire_work
;
2442 * When we detect an idle GPU, we want to turn on
2443 * powersaving features. So once we see that there
2444 * are no more requests outstanding and no more
2445 * arrive within a small period of time, we fire
2446 * off the idle_work.
2448 struct delayed_work idle_work
;
2450 ktime_t last_init_time
;
2453 /* perform PHY state sanity checks? */
2454 bool chv_phy_assert
[2];
2458 /* Used to save the pipe-to-encoder mapping for audio */
2459 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2462 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2463 * will be rejected. Instead look for a better place.
2467 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2469 return container_of(dev
, struct drm_i915_private
, drm
);
2472 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2474 return to_i915(dev_get_drvdata(kdev
));
2477 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2479 return container_of(guc
, struct drm_i915_private
, guc
);
2482 /* Simple iterator over all initialised engines */
2483 #define for_each_engine(engine__, dev_priv__, id__) \
2485 (id__) < I915_NUM_ENGINES; \
2487 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2489 #define __mask_next_bit(mask) ({ \
2490 int __idx = ffs(mask) - 1; \
2491 mask &= ~BIT(__idx); \
2495 /* Iterator over subset of engines selected by mask */
2496 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2497 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2498 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2500 enum hdmi_force_audio
{
2501 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2502 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2503 HDMI_AUDIO_AUTO
, /* trust EDID */
2504 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2507 #define I915_GTT_OFFSET_NONE ((u32)-1)
2510 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2511 * considered to be the frontbuffer for the given plane interface-wise. This
2512 * doesn't mean that the hw necessarily already scans it out, but that any
2513 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2515 * We have one bit per pipe and per scanout plane type.
2517 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2518 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2519 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2520 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2521 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2522 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2523 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2524 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2525 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2526 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2527 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2528 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2531 * Optimised SGL iterator for GEM objects
2533 static __always_inline
struct sgt_iter
{
2534 struct scatterlist
*sgp
;
2541 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2542 struct sgt_iter s
= { .sgp
= sgl
};
2545 s
.max
= s
.curr
= s
.sgp
->offset
;
2546 s
.max
+= s
.sgp
->length
;
2548 s
.dma
= sg_dma_address(s
.sgp
);
2550 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2556 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2559 if (unlikely(sg_is_chain(sg
)))
2560 sg
= sg_chain_ptr(sg
);
2565 * __sg_next - return the next scatterlist entry in a list
2566 * @sg: The current sg entry
2569 * If the entry is the last, return NULL; otherwise, step to the next
2570 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2571 * otherwise just return the pointer to the current element.
2573 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2575 #ifdef CONFIG_DEBUG_SG
2576 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2578 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2582 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2583 * @__dmap: DMA address (output)
2584 * @__iter: 'struct sgt_iter' (iterator state, internal)
2585 * @__sgt: sg_table to iterate over (input)
2587 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2588 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2589 ((__dmap) = (__iter).dma + (__iter).curr); \
2590 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2591 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2594 * for_each_sgt_page - iterate over the pages of the given sg_table
2595 * @__pp: page pointer (output)
2596 * @__iter: 'struct sgt_iter' (iterator state, internal)
2597 * @__sgt: sg_table to iterate over (input)
2599 #define for_each_sgt_page(__pp, __iter, __sgt) \
2600 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2601 ((__pp) = (__iter).pfn == 0 ? NULL : \
2602 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2603 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2604 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2606 static inline const struct intel_device_info
*
2607 intel_info(const struct drm_i915_private
*dev_priv
)
2609 return &dev_priv
->info
;
2612 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2614 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2615 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2617 #define REVID_FOREVER 0xff
2618 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2620 #define GEN_FOREVER (0)
2622 * Returns true if Gen is in inclusive range [Start, End].
2624 * Use GEN_FOREVER for unbound start and or end.
2626 #define IS_GEN(dev_priv, s, e) ({ \
2627 unsigned int __s = (s), __e = (e); \
2628 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2629 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2630 if ((__s) != GEN_FOREVER) \
2632 if ((__e) == GEN_FOREVER) \
2633 __e = BITS_PER_LONG - 1; \
2636 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2640 * Return true if revision is in range [since,until] inclusive.
2642 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2644 #define IS_REVID(p, since, until) \
2645 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2647 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2648 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2649 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2650 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2651 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2652 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2653 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2654 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2655 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2656 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2657 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2658 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2659 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2660 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2661 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2662 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2663 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2664 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2665 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2666 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2667 INTEL_DEVID(dev_priv) == 0x0152 || \
2668 INTEL_DEVID(dev_priv) == 0x015a)
2669 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2670 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2671 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2672 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2673 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2674 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2675 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2676 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2677 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2678 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2679 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2680 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2681 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2682 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2683 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2684 /* ULX machines are also considered ULT. */
2685 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2686 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2687 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2688 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2689 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2690 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2691 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2692 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2693 /* ULX machines are also considered ULT. */
2694 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2695 INTEL_DEVID(dev_priv) == 0x0A1E)
2696 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2697 INTEL_DEVID(dev_priv) == 0x1913 || \
2698 INTEL_DEVID(dev_priv) == 0x1916 || \
2699 INTEL_DEVID(dev_priv) == 0x1921 || \
2700 INTEL_DEVID(dev_priv) == 0x1926)
2701 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2702 INTEL_DEVID(dev_priv) == 0x1915 || \
2703 INTEL_DEVID(dev_priv) == 0x191E)
2704 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2705 INTEL_DEVID(dev_priv) == 0x5913 || \
2706 INTEL_DEVID(dev_priv) == 0x5916 || \
2707 INTEL_DEVID(dev_priv) == 0x5921 || \
2708 INTEL_DEVID(dev_priv) == 0x5926)
2709 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2710 INTEL_DEVID(dev_priv) == 0x5915 || \
2711 INTEL_DEVID(dev_priv) == 0x591E)
2712 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2713 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2714 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2715 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2717 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2719 #define SKL_REVID_A0 0x0
2720 #define SKL_REVID_B0 0x1
2721 #define SKL_REVID_C0 0x2
2722 #define SKL_REVID_D0 0x3
2723 #define SKL_REVID_E0 0x4
2724 #define SKL_REVID_F0 0x5
2725 #define SKL_REVID_G0 0x6
2726 #define SKL_REVID_H0 0x7
2728 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2730 #define BXT_REVID_A0 0x0
2731 #define BXT_REVID_A1 0x1
2732 #define BXT_REVID_B0 0x3
2733 #define BXT_REVID_B_LAST 0x8
2734 #define BXT_REVID_C0 0x9
2736 #define IS_BXT_REVID(dev_priv, since, until) \
2737 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2739 #define KBL_REVID_A0 0x0
2740 #define KBL_REVID_B0 0x1
2741 #define KBL_REVID_C0 0x2
2742 #define KBL_REVID_D0 0x3
2743 #define KBL_REVID_E0 0x4
2745 #define IS_KBL_REVID(dev_priv, since, until) \
2746 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2749 * The genX designation typically refers to the render engine, so render
2750 * capability related checks should use IS_GEN, while display and other checks
2751 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2754 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2755 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2756 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2757 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2758 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2759 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2760 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2761 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2763 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2764 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2765 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2767 #define ENGINE_MASK(id) BIT(id)
2768 #define RENDER_RING ENGINE_MASK(RCS)
2769 #define BSD_RING ENGINE_MASK(VCS)
2770 #define BLT_RING ENGINE_MASK(BCS)
2771 #define VEBOX_RING ENGINE_MASK(VECS)
2772 #define BSD2_RING ENGINE_MASK(VCS2)
2773 #define ALL_ENGINES (~0)
2775 #define HAS_ENGINE(dev_priv, id) \
2776 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2778 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2779 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2780 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2781 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2783 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2784 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2785 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2786 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2787 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2789 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2791 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2792 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2793 ((dev_priv)->info.has_logical_ring_contexts)
2794 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2795 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2796 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2798 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2799 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2800 ((dev_priv)->info.overlay_needs_physical)
2802 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2803 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2805 /* WaRsDisableCoarsePowerGating:skl,bxt */
2806 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2807 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2808 IS_SKL_GT3(dev_priv) || \
2809 IS_SKL_GT4(dev_priv))
2812 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2813 * even when in MSI mode. This results in spurious interrupt warnings if the
2814 * legacy irq no. is shared with another device. The kernel then disables that
2815 * interrupt source and so prevents the other device from working properly.
2817 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2818 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2820 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2821 * rows, which changed the alignment requirements and fence programming.
2823 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2824 !(IS_I915G(dev_priv) || \
2825 IS_I915GM(dev_priv)))
2826 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2827 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2829 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2830 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2831 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2833 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2835 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2837 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2838 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2839 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2840 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2841 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2843 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2845 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2846 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2849 * For now, anything with a GuC requires uCode loading, and then supports
2850 * command submission once loaded. But these are logically independent
2851 * properties, so we have separate macros to test them.
2853 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2854 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2855 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2856 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2858 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2860 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2862 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2863 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2864 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2865 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2866 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2867 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2868 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2869 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2870 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2871 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2872 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2873 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2875 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2876 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2877 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2878 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2879 #define HAS_PCH_LPT_LP(dev_priv) \
2880 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2881 #define HAS_PCH_LPT_H(dev_priv) \
2882 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2883 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2884 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2885 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2886 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2888 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2890 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2892 /* DPF == dynamic parity feature */
2893 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2894 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2895 2 : HAS_L3_DPF(dev_priv))
2897 #define GT_FREQUENCY_MULTIPLIER 50
2898 #define GEN9_FREQ_SCALER 3
2900 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2902 #include "i915_trace.h"
2904 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2906 #ifdef CONFIG_INTEL_IOMMU
2907 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2913 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2916 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2920 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2921 const char *fmt
, ...);
2923 #define i915_report_error(dev_priv, fmt, ...) \
2924 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2926 #ifdef CONFIG_COMPAT
2927 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2930 #define i915_compat_ioctl NULL
2932 extern const struct dev_pm_ops i915_pm_ops
;
2934 extern int i915_driver_load(struct pci_dev
*pdev
,
2935 const struct pci_device_id
*ent
);
2936 extern void i915_driver_unload(struct drm_device
*dev
);
2937 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2938 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2939 extern void i915_reset(struct drm_i915_private
*dev_priv
);
2940 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2941 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2942 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
2943 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2944 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2945 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2946 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2947 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2949 int intel_engines_init_early(struct drm_i915_private
*dev_priv
);
2950 int intel_engines_init(struct drm_i915_private
*dev_priv
);
2952 /* intel_hotplug.c */
2953 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2954 u32 pin_mask
, u32 long_mask
);
2955 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2956 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2957 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2958 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2959 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2960 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2963 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2965 unsigned long delay
;
2967 if (unlikely(!i915
.enable_hangcheck
))
2970 /* Don't continually defer the hangcheck so that it is always run at
2971 * least once after work has been scheduled on any ring. Otherwise,
2972 * we will ignore a hung ring if a second ring is kept busy.
2975 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2976 queue_delayed_work(system_long_wq
,
2977 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2981 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2983 const char *fmt
, ...);
2985 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2986 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2987 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2989 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2990 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2991 bool restore_forcewake
);
2992 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2993 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2994 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2995 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2996 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2998 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2999 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
3000 enum forcewake_domains domains
);
3001 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
3002 enum forcewake_domains domains
);
3003 /* Like above but the caller must manage the uncore.lock itself.
3004 * Must be used with I915_READ_FW and friends.
3006 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
3007 enum forcewake_domains domains
);
3008 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
3009 enum forcewake_domains domains
);
3010 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
3012 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
3014 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
3018 const unsigned long timeout_ms
);
3019 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
3023 const unsigned long timeout_ms
);
3025 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3027 return dev_priv
->gvt
;
3030 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3032 return dev_priv
->vgpu
.active
;
3036 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3040 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3043 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3044 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3045 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3048 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3049 uint32_t interrupt_mask
,
3050 uint32_t enabled_irq_mask
);
3052 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3054 ilk_update_display_irq(dev_priv
, bits
, bits
);
3057 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3059 ilk_update_display_irq(dev_priv
, bits
, 0);
3061 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3063 uint32_t interrupt_mask
,
3064 uint32_t enabled_irq_mask
);
3065 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3066 enum pipe pipe
, uint32_t bits
)
3068 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3070 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3071 enum pipe pipe
, uint32_t bits
)
3073 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3075 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3076 uint32_t interrupt_mask
,
3077 uint32_t enabled_irq_mask
);
3079 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3081 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3084 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3086 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3090 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3091 struct drm_file
*file_priv
);
3092 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3093 struct drm_file
*file_priv
);
3094 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3095 struct drm_file
*file_priv
);
3096 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3097 struct drm_file
*file_priv
);
3098 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3099 struct drm_file
*file_priv
);
3100 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3101 struct drm_file
*file_priv
);
3102 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3103 struct drm_file
*file_priv
);
3104 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3105 struct drm_file
*file_priv
);
3106 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3107 struct drm_file
*file_priv
);
3108 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3109 struct drm_file
*file_priv
);
3110 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3111 struct drm_file
*file
);
3112 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3113 struct drm_file
*file
);
3114 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3115 struct drm_file
*file_priv
);
3116 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3117 struct drm_file
*file_priv
);
3118 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
3119 struct drm_file
*file_priv
);
3120 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
3121 struct drm_file
*file_priv
);
3122 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3123 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3124 struct drm_file
*file
);
3125 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3126 struct drm_file
*file_priv
);
3127 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3128 struct drm_file
*file_priv
);
3129 void i915_gem_sanitize(struct drm_i915_private
*i915
);
3130 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
3131 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
3132 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3133 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3134 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3136 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
3137 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3138 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3139 const struct drm_i915_gem_object_ops
*ops
);
3140 struct drm_i915_gem_object
*
3141 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
3142 struct drm_i915_gem_object
*
3143 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
3144 const void *data
, size_t size
);
3145 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3146 void i915_gem_free_object(struct drm_gem_object
*obj
);
3148 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
3150 /* A single pass should suffice to release all the freed objects (along
3151 * most call paths) , but be a little more paranoid in that freeing
3152 * the objects does take a little amount of time, during which the rcu
3153 * callbacks could have added new objects into the freed list, and
3154 * armed the work again.
3158 } while (flush_work(&i915
->mm
.free_work
));
3161 struct i915_vma
* __must_check
3162 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3163 const struct i915_ggtt_view
*view
,
3168 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3169 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3171 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3173 static inline int __sg_page_count(const struct scatterlist
*sg
)
3175 return sg
->length
>> PAGE_SHIFT
;
3178 struct scatterlist
*
3179 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3180 unsigned int n
, unsigned int *offset
);
3183 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3187 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3191 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3194 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3195 struct sg_table
*pages
);
3196 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3198 static inline int __must_check
3199 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3201 might_lock(&obj
->mm
.lock
);
3203 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3206 return __i915_gem_object_get_pages(obj
);
3210 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3212 GEM_BUG_ON(!obj
->mm
.pages
);
3214 atomic_inc(&obj
->mm
.pages_pin_count
);
3218 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3220 return atomic_read(&obj
->mm
.pages_pin_count
);
3224 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3226 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3227 GEM_BUG_ON(!obj
->mm
.pages
);
3229 atomic_dec(&obj
->mm
.pages_pin_count
);
3233 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3235 __i915_gem_object_unpin_pages(obj
);
3238 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3243 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3244 enum i915_mm_subclass subclass
);
3245 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3247 enum i915_map_type
{
3253 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3254 * @obj: the object to map into kernel address space
3255 * @type: the type of mapping, used to select pgprot_t
3257 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3258 * pages and then returns a contiguous mapping of the backing storage into
3259 * the kernel address space. Based on the @type of mapping, the PTE will be
3260 * set to either WriteBack or WriteCombine (via pgprot_t).
3262 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3263 * mapping is no longer required.
3265 * Returns the pointer through which to access the mapped object, or an
3266 * ERR_PTR() on error.
3268 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3269 enum i915_map_type type
);
3272 * i915_gem_object_unpin_map - releases an earlier mapping
3273 * @obj: the object to unmap
3275 * After pinning the object and mapping its pages, once you are finished
3276 * with your access, call i915_gem_object_unpin_map() to release the pin
3277 * upon the mapping. Once the pin count reaches zero, that mapping may be
3280 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3282 i915_gem_object_unpin_pages(obj
);
3285 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3286 unsigned int *needs_clflush
);
3287 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3288 unsigned int *needs_clflush
);
3289 #define CLFLUSH_BEFORE 0x1
3290 #define CLFLUSH_AFTER 0x2
3291 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3294 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3296 i915_gem_object_unpin_pages(obj
);
3299 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3300 void i915_vma_move_to_active(struct i915_vma
*vma
,
3301 struct drm_i915_gem_request
*req
,
3302 unsigned int flags
);
3303 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3304 struct drm_device
*dev
,
3305 struct drm_mode_create_dumb
*args
);
3306 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3307 uint32_t handle
, uint64_t *offset
);
3308 int i915_gem_mmap_gtt_version(void);
3310 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3311 struct drm_i915_gem_object
*new,
3312 unsigned frontbuffer_bits
);
3314 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3316 struct drm_i915_gem_request
*
3317 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3319 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3321 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3323 return unlikely(test_bit(I915_RESET_IN_PROGRESS
, &error
->flags
));
3326 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3328 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3331 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3333 return i915_reset_in_progress(error
) | i915_terminally_wedged(error
);
3336 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3338 return READ_ONCE(error
->reset_count
);
3341 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3342 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3343 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3344 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3345 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3346 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3347 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3348 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3349 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3350 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3351 unsigned int flags
);
3352 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3353 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3354 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3355 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3358 struct intel_rps_client
*rps
);
3359 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3362 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3365 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3368 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3369 struct i915_vma
* __must_check
3370 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3372 const struct i915_ggtt_view
*view
);
3373 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3374 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3376 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3377 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3379 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3380 enum i915_cache_level cache_level
);
3382 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3383 struct dma_buf
*dma_buf
);
3385 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3386 struct drm_gem_object
*gem_obj
, int flags
);
3388 static inline struct i915_hw_ppgtt
*
3389 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3391 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3394 /* i915_gem_fence_reg.c */
3395 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3396 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3398 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3399 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3401 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3402 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3403 struct sg_table
*pages
);
3404 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3405 struct sg_table
*pages
);
3407 static inline struct i915_gem_context
*
3408 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3410 struct i915_gem_context
*ctx
;
3412 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3414 ctx
= idr_find(&file_priv
->context_idr
, id
);
3416 return ERR_PTR(-ENOENT
);
3421 static inline struct i915_gem_context
*
3422 i915_gem_context_get(struct i915_gem_context
*ctx
)
3424 kref_get(&ctx
->ref
);
3428 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3430 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3431 kref_put(&ctx
->ref
, i915_gem_context_free
);
3434 static inline void i915_gem_context_put_unlocked(struct i915_gem_context
*ctx
)
3436 struct mutex
*lock
= &ctx
->i915
->drm
.struct_mutex
;
3438 if (kref_put_mutex(&ctx
->ref
, i915_gem_context_free
, lock
))
3442 static inline struct intel_timeline
*
3443 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3444 struct intel_engine_cs
*engine
)
3446 struct i915_address_space
*vm
;
3448 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3449 return &vm
->timeline
.engine
[engine
->id
];
3452 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3453 struct drm_file
*file
);
3455 /* i915_gem_evict.c */
3456 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3457 u64 min_size
, u64 alignment
,
3458 unsigned cache_level
,
3461 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3462 struct drm_mm_node
*node
,
3463 unsigned int flags
);
3464 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3466 /* belongs in i915_gem_gtt.h */
3467 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3470 if (INTEL_GEN(dev_priv
) < 6)
3471 intel_gtt_chipset_flush();
3474 /* i915_gem_stolen.c */
3475 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3476 struct drm_mm_node
*node
, u64 size
,
3477 unsigned alignment
);
3478 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3479 struct drm_mm_node
*node
, u64 size
,
3480 unsigned alignment
, u64 start
,
3482 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3483 struct drm_mm_node
*node
);
3484 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3485 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3486 struct drm_i915_gem_object
*
3487 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3488 struct drm_i915_gem_object
*
3489 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3494 /* i915_gem_internal.c */
3495 struct drm_i915_gem_object
*
3496 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3499 /* i915_gem_shrinker.c */
3500 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3501 unsigned long target
,
3503 #define I915_SHRINK_PURGEABLE 0x1
3504 #define I915_SHRINK_UNBOUND 0x2
3505 #define I915_SHRINK_BOUND 0x4
3506 #define I915_SHRINK_ACTIVE 0x8
3507 #define I915_SHRINK_VMAPS 0x10
3508 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3509 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3510 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3513 /* i915_gem_tiling.c */
3514 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3516 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3518 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3519 i915_gem_object_is_tiled(obj
);
3522 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3523 unsigned int tiling
, unsigned int stride
);
3524 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3525 unsigned int tiling
, unsigned int stride
);
3527 /* i915_debugfs.c */
3528 #ifdef CONFIG_DEBUG_FS
3529 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3530 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3531 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3532 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3534 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3535 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3536 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3538 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3541 /* i915_gpu_error.c */
3542 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3545 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3546 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3547 const struct i915_error_state_file_priv
*error
);
3548 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3549 struct drm_i915_private
*i915
,
3550 size_t count
, loff_t pos
);
3551 static inline void i915_error_state_buf_release(
3552 struct drm_i915_error_state_buf
*eb
)
3556 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3558 const char *error_msg
);
3559 void i915_error_state_get(struct drm_device
*dev
,
3560 struct i915_error_state_file_priv
*error_priv
);
3561 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3562 void i915_destroy_error_state(struct drm_i915_private
*dev_priv
);
3566 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3568 const char *error_msg
)
3572 static inline void i915_destroy_error_state(struct drm_i915_private
*dev_priv
)
3578 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3580 /* i915_cmd_parser.c */
3581 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3582 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3583 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3584 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3585 struct drm_i915_gem_object
*batch_obj
,
3586 struct drm_i915_gem_object
*shadow_batch_obj
,
3587 u32 batch_start_offset
,
3592 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3593 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3594 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3595 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3597 /* i915_suspend.c */
3598 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3599 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3602 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3603 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3606 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
3607 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
3608 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3611 extern struct i2c_adapter
*
3612 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3613 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3614 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3615 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3617 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3619 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
3622 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3623 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3624 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3625 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3626 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3627 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3628 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3629 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3630 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3632 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3636 /* intel_opregion.c */
3638 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3639 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3640 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3641 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3642 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3644 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3646 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3648 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3649 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3650 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3651 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3655 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3660 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3664 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3672 extern void intel_register_dsm_handler(void);
3673 extern void intel_unregister_dsm_handler(void);
3675 static inline void intel_register_dsm_handler(void) { return; }
3676 static inline void intel_unregister_dsm_handler(void) { return; }
3677 #endif /* CONFIG_ACPI */
3679 /* intel_device_info.c */
3680 static inline struct intel_device_info
*
3681 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3683 return (struct intel_device_info
*)&dev_priv
->info
;
3686 const char *intel_platform_name(enum intel_platform platform
);
3687 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3688 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3691 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3692 extern int intel_modeset_init(struct drm_device
*dev
);
3693 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3694 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3695 extern int intel_connector_register(struct drm_connector
*);
3696 extern void intel_connector_unregister(struct drm_connector
*);
3697 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
3699 extern void intel_display_resume(struct drm_device
*dev
);
3700 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
3701 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
3702 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3703 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
3704 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3705 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3708 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3709 struct drm_file
*file
);
3712 extern struct intel_overlay_error_state
*
3713 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3714 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3715 struct intel_overlay_error_state
*error
);
3717 extern struct intel_display_error_state
*
3718 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3719 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3720 struct drm_i915_private
*dev_priv
,
3721 struct intel_display_error_state
*error
);
3723 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3724 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3725 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
3726 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
3728 /* intel_sideband.c */
3729 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3730 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3731 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3732 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3733 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3734 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3735 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3736 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3737 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3738 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3739 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3740 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3741 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3742 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3743 enum intel_sbi_destination destination
);
3744 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3745 enum intel_sbi_destination destination
);
3746 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3747 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3749 /* intel_dpio_phy.c */
3750 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
3751 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3752 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3753 enum port port
, u32 margin
, u32 scale
,
3754 u32 enable
, u32 deemphasis
);
3755 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3756 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3757 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3759 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3761 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3762 uint8_t lane_count
);
3763 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3764 uint8_t lane_lat_optim_mask
);
3765 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3767 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3768 u32 deemph_reg_value
, u32 margin_reg_value
,
3769 bool uniq_trans_scale
);
3770 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3772 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3773 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3774 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3775 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3777 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3778 u32 demph_reg_value
, u32 preemph_reg_value
,
3779 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3780 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3781 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3782 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3784 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3785 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3787 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3788 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3790 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3791 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3792 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3793 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3795 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3796 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3797 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3798 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3800 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3801 * will be implemented using 2 32-bit writes in an arbitrary order with
3802 * an arbitrary delay between them. This can cause the hardware to
3803 * act upon the intermediate value, possibly leading to corruption and
3804 * machine death. For this reason we do not support I915_WRITE64, or
3805 * dev_priv->uncore.funcs.mmio_writeq.
3807 * When reading a 64-bit value as two 32-bit values, the delay may cause
3808 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3809 * occasionally a 64-bit register does not actualy support a full readq
3810 * and must be read using two 32-bit reads.
3812 * You have been warned.
3814 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3816 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3817 u32 upper, lower, old_upper, loop = 0; \
3818 upper = I915_READ(upper_reg); \
3820 old_upper = upper; \
3821 lower = I915_READ(lower_reg); \
3822 upper = I915_READ(upper_reg); \
3823 } while (upper != old_upper && loop++ < 2); \
3824 (u64)upper << 32 | lower; })
3826 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3827 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3829 #define __raw_read(x, s) \
3830 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3833 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3836 #define __raw_write(x, s) \
3837 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3838 i915_reg_t reg, uint##x##_t val) \
3840 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3855 /* These are untraced mmio-accessors that are only valid to be used inside
3856 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3859 * Think twice, and think again, before using these.
3861 * As an example, these accessors can possibly be used between:
3863 * spin_lock_irq(&dev_priv->uncore.lock);
3864 * intel_uncore_forcewake_get__locked();
3868 * intel_uncore_forcewake_put__locked();
3869 * spin_unlock_irq(&dev_priv->uncore.lock);
3872 * Note: some registers may not need forcewake held, so
3873 * intel_uncore_forcewake_{get,put} can be omitted, see
3874 * intel_uncore_forcewake_for_reg().
3876 * Certain architectures will die if the same cacheline is concurrently accessed
3877 * by different clients (e.g. on Ivybridge). Access to registers should
3878 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3879 * a more localised lock guarding all access to that bank of registers.
3881 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3882 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3883 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3884 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3886 /* "Broadcast RGB" property */
3887 #define INTEL_BROADCAST_RGB_AUTO 0
3888 #define INTEL_BROADCAST_RGB_FULL 1
3889 #define INTEL_BROADCAST_RGB_LIMITED 2
3891 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
3893 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3894 return VLV_VGACNTRL
;
3895 else if (INTEL_GEN(dev_priv
) >= 5)
3896 return CPU_VGACNTRL
;
3901 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3903 unsigned long j
= msecs_to_jiffies(m
);
3905 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3908 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3910 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3913 static inline unsigned long
3914 timespec_to_jiffies_timeout(const struct timespec
*value
)
3916 unsigned long j
= timespec_to_jiffies(value
);
3918 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3922 * If you need to wait X milliseconds between events A and B, but event B
3923 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3924 * when event A happened, then just before event B you call this function and
3925 * pass the timestamp as the first argument, and X as the second argument.
3928 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3930 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3933 * Don't re-read the value of "jiffies" every time since it may change
3934 * behind our back and break the math.
3936 tmp_jiffies
= jiffies
;
3937 target_jiffies
= timestamp_jiffies
+
3938 msecs_to_jiffies_timeout(to_wait_ms
);
3940 if (time_after(target_jiffies
, tmp_jiffies
)) {
3941 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3942 while (remaining_jiffies
)
3944 schedule_timeout_uninterruptible(remaining_jiffies
);
3949 __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3951 struct intel_engine_cs
*engine
= req
->engine
;
3953 /* Before we do the heavier coherent read of the seqno,
3954 * check the value (hopefully) in the CPU cacheline.
3956 if (__i915_gem_request_completed(req
))
3959 /* Ensure our read of the seqno is coherent so that we
3960 * do not "miss an interrupt" (i.e. if this is the last
3961 * request and the seqno write from the GPU is not visible
3962 * by the time the interrupt fires, we will see that the
3963 * request is incomplete and go back to sleep awaiting
3964 * another interrupt that will never come.)
3966 * Strictly, we only need to do this once after an interrupt,
3967 * but it is easier and safer to do it every time the waiter
3970 if (engine
->irq_seqno_barrier
&&
3971 rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
3972 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
3973 struct task_struct
*tsk
;
3975 /* The ordering of irq_posted versus applying the barrier
3976 * is crucial. The clearing of the current irq_posted must
3977 * be visible before we perform the barrier operation,
3978 * such that if a subsequent interrupt arrives, irq_posted
3979 * is reasserted and our task rewoken (which causes us to
3980 * do another __i915_request_irq_complete() immediately
3981 * and reapply the barrier). Conversely, if the clear
3982 * occurs after the barrier, then an interrupt that arrived
3983 * whilst we waited on the barrier would not trigger a
3984 * barrier on the next pass, and the read may not see the
3987 engine
->irq_seqno_barrier(engine
);
3989 /* If we consume the irq, but we are no longer the bottom-half,
3990 * the real bottom-half may not have serialised their own
3991 * seqno check with the irq-barrier (i.e. may have inspected
3992 * the seqno before we believe it coherent since they see
3993 * irq_posted == false but we are still running).
3996 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
3997 if (tsk
&& tsk
!= current
)
3998 /* Note that if the bottom-half is changed as we
3999 * are sending the wake-up, the new bottom-half will
4000 * be woken by whomever made the change. We only have
4001 * to worry about when we steal the irq-posted for
4004 wake_up_process(tsk
);
4007 if (__i915_gem_request_completed(req
))
4014 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4015 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4017 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4018 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4019 * perform the operation. To check beforehand, pass in the parameters to
4020 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4021 * you only need to pass in the minor offsets, page-aligned pointers are
4024 * For just checking for SSE4.1, in the foreknowledge that the future use
4025 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4027 #define i915_can_memcpy_from_wc(dst, src, len) \
4028 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4030 #define i915_has_memcpy_from_wc() \
4031 i915_memcpy_from_wc(NULL, NULL, 0)
4034 int remap_io_mapping(struct vm_area_struct
*vma
,
4035 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4036 struct io_mapping
*iomap
);