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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
36
37 /* General customization:
38 */
39
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
45
46 enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49 };
50
51 #define I915_NUM_PIPE 2
52
53 /* Interface history:
54 *
55 * 1.1: Original.
56 * 1.2: Add Power Management
57 * 1.3: Add vblank support
58 * 1.4: Fix cmdbuffer path, add heap destroy
59 * 1.5: Add vblank pipe configuration
60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
62 */
63 #define DRIVER_MAJOR 1
64 #define DRIVER_MINOR 6
65 #define DRIVER_PATCHLEVEL 0
66
67 #define WATCH_COHERENCY 0
68 #define WATCH_BUF 0
69 #define WATCH_EXEC 0
70 #define WATCH_LRU 0
71 #define WATCH_RELOC 0
72 #define WATCH_INACTIVE 0
73 #define WATCH_PWRITE 0
74
75 #define I915_GEM_PHYS_CURSOR_0 1
76 #define I915_GEM_PHYS_CURSOR_1 2
77 #define I915_GEM_PHYS_OVERLAY_REGS 3
78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
79
80 struct drm_i915_gem_phys_object {
81 int id;
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
85 };
86
87 typedef struct _drm_i915_ring_buffer {
88 int tail_mask;
89 unsigned long Size;
90 u8 *virtual_start;
91 int head;
92 int tail;
93 int space;
94 drm_local_map_t map;
95 struct drm_gem_object *ring_obj;
96 } drm_i915_ring_buffer_t;
97
98 struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
104 };
105
106 struct opregion_header;
107 struct opregion_acpi;
108 struct opregion_swsci;
109 struct opregion_asle;
110
111 struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
116 int enabled;
117 };
118
119 struct drm_i915_master_private {
120 drm_local_map_t *sarea;
121 struct _drm_i915_sarea *sarea_priv;
122 };
123 #define I915_FENCE_REG_NONE -1
124
125 struct drm_i915_fence_reg {
126 struct drm_gem_object *obj;
127 };
128
129 struct sdvo_device_mapping {
130 u8 dvo_port;
131 u8 slave_addr;
132 u8 dvo_wiring;
133 u8 initialized;
134 };
135
136 struct drm_i915_error_state {
137 u32 eir;
138 u32 pgtbl_er;
139 u32 pipeastat;
140 u32 pipebstat;
141 u32 ipeir;
142 u32 ipehr;
143 u32 instdone;
144 u32 acthd;
145 u32 instpm;
146 u32 instps;
147 u32 instdone1;
148 u32 seqno;
149 struct timeval time;
150 };
151
152 typedef struct drm_i915_private {
153 struct drm_device *dev;
154
155 int has_gem;
156
157 void __iomem *regs;
158
159 drm_i915_ring_buffer_t ring;
160
161 drm_dma_handle_t *status_page_dmah;
162 void *hw_status_page;
163 dma_addr_t dma_status_page;
164 uint32_t counter;
165 unsigned int status_gfx_addr;
166 drm_local_map_t hws_map;
167 struct drm_gem_object *hws_obj;
168
169 struct resource mch_res;
170
171 unsigned int cpp;
172 int back_offset;
173 int front_offset;
174 int current_page;
175 int page_flipping;
176
177 wait_queue_head_t irq_queue;
178 atomic_t irq_received;
179 /** Protects user_irq_refcount and irq_mask_reg */
180 spinlock_t user_irq_lock;
181 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
182 int user_irq_refcount;
183 /** Cached value of IMR to avoid reads in updating the bitfield */
184 u32 irq_mask_reg;
185 u32 pipestat[2];
186 /** splitted irq regs for graphics and display engine on IGDNG,
187 irq_mask_reg is still used for display irq. */
188 u32 gt_irq_mask_reg;
189 u32 gt_irq_enable_reg;
190 u32 de_irq_enable_reg;
191
192 u32 hotplug_supported_mask;
193 struct work_struct hotplug_work;
194
195 int tex_lru_log_granularity;
196 int allow_batchbuffer;
197 struct mem_block *agp_heap;
198 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
199 int vblank_pipe;
200
201 bool cursor_needs_physical;
202
203 struct drm_mm vram;
204
205 int irq_enabled;
206
207 struct intel_opregion opregion;
208
209 /* LVDS info */
210 int backlight_duty_cycle; /* restore backlight to this value */
211 bool panel_wants_dither;
212 struct drm_display_mode *panel_fixed_mode;
213 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
214 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
215
216 /* Feature bits from the VBIOS */
217 unsigned int int_tv_support:1;
218 unsigned int lvds_dither:1;
219 unsigned int lvds_vbt:1;
220 unsigned int int_crt_support:1;
221 unsigned int lvds_use_ssc:1;
222 int lvds_ssc_freq;
223
224 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
225 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
226 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
227
228 unsigned int fsb_freq, mem_freq;
229
230 spinlock_t error_lock;
231 struct drm_i915_error_state *first_error;
232
233 /* Register state */
234 u8 saveLBB;
235 u32 saveDSPACNTR;
236 u32 saveDSPBCNTR;
237 u32 saveDSPARB;
238 u32 saveRENDERSTANDBY;
239 u32 saveHWS;
240 u32 savePIPEACONF;
241 u32 savePIPEBCONF;
242 u32 savePIPEASRC;
243 u32 savePIPEBSRC;
244 u32 saveFPA0;
245 u32 saveFPA1;
246 u32 saveDPLL_A;
247 u32 saveDPLL_A_MD;
248 u32 saveHTOTAL_A;
249 u32 saveHBLANK_A;
250 u32 saveHSYNC_A;
251 u32 saveVTOTAL_A;
252 u32 saveVBLANK_A;
253 u32 saveVSYNC_A;
254 u32 saveBCLRPAT_A;
255 u32 savePIPEASTAT;
256 u32 saveDSPASTRIDE;
257 u32 saveDSPASIZE;
258 u32 saveDSPAPOS;
259 u32 saveDSPAADDR;
260 u32 saveDSPASURF;
261 u32 saveDSPATILEOFF;
262 u32 savePFIT_PGM_RATIOS;
263 u32 saveBLC_PWM_CTL;
264 u32 saveBLC_PWM_CTL2;
265 u32 saveFPB0;
266 u32 saveFPB1;
267 u32 saveDPLL_B;
268 u32 saveDPLL_B_MD;
269 u32 saveHTOTAL_B;
270 u32 saveHBLANK_B;
271 u32 saveHSYNC_B;
272 u32 saveVTOTAL_B;
273 u32 saveVBLANK_B;
274 u32 saveVSYNC_B;
275 u32 saveBCLRPAT_B;
276 u32 savePIPEBSTAT;
277 u32 saveDSPBSTRIDE;
278 u32 saveDSPBSIZE;
279 u32 saveDSPBPOS;
280 u32 saveDSPBADDR;
281 u32 saveDSPBSURF;
282 u32 saveDSPBTILEOFF;
283 u32 saveVGA0;
284 u32 saveVGA1;
285 u32 saveVGA_PD;
286 u32 saveVGACNTRL;
287 u32 saveADPA;
288 u32 saveLVDS;
289 u32 savePP_ON_DELAYS;
290 u32 savePP_OFF_DELAYS;
291 u32 saveDVOA;
292 u32 saveDVOB;
293 u32 saveDVOC;
294 u32 savePP_ON;
295 u32 savePP_OFF;
296 u32 savePP_CONTROL;
297 u32 savePP_DIVISOR;
298 u32 savePFIT_CONTROL;
299 u32 save_palette_a[256];
300 u32 save_palette_b[256];
301 u32 saveFBC_CFB_BASE;
302 u32 saveFBC_LL_BASE;
303 u32 saveFBC_CONTROL;
304 u32 saveFBC_CONTROL2;
305 u32 saveIER;
306 u32 saveIIR;
307 u32 saveIMR;
308 u32 saveCACHE_MODE_0;
309 u32 saveD_STATE;
310 u32 saveCG_2D_DIS;
311 u32 saveMI_ARB_STATE;
312 u32 saveSWF0[16];
313 u32 saveSWF1[16];
314 u32 saveSWF2[3];
315 u8 saveMSR;
316 u8 saveSR[8];
317 u8 saveGR[25];
318 u8 saveAR_INDEX;
319 u8 saveAR[21];
320 u8 saveDACMASK;
321 u8 saveCR[37];
322 uint64_t saveFENCE[16];
323 u32 saveCURACNTR;
324 u32 saveCURAPOS;
325 u32 saveCURABASE;
326 u32 saveCURBCNTR;
327 u32 saveCURBPOS;
328 u32 saveCURBBASE;
329 u32 saveCURSIZE;
330 u32 saveDP_B;
331 u32 saveDP_C;
332 u32 saveDP_D;
333 u32 savePIPEA_GMCH_DATA_M;
334 u32 savePIPEB_GMCH_DATA_M;
335 u32 savePIPEA_GMCH_DATA_N;
336 u32 savePIPEB_GMCH_DATA_N;
337 u32 savePIPEA_DP_LINK_M;
338 u32 savePIPEB_DP_LINK_M;
339 u32 savePIPEA_DP_LINK_N;
340 u32 savePIPEB_DP_LINK_N;
341
342 struct {
343 struct drm_mm gtt_space;
344
345 struct io_mapping *gtt_mapping;
346 int gtt_mtrr;
347
348 /**
349 * List of objects currently involved in rendering from the
350 * ringbuffer.
351 *
352 * Includes buffers having the contents of their GPU caches
353 * flushed, not necessarily primitives. last_rendering_seqno
354 * represents when the rendering involved will be completed.
355 *
356 * A reference is held on the buffer while on this list.
357 */
358 spinlock_t active_list_lock;
359 struct list_head active_list;
360
361 /**
362 * List of objects which are not in the ringbuffer but which
363 * still have a write_domain which needs to be flushed before
364 * unbinding.
365 *
366 * last_rendering_seqno is 0 while an object is in this list.
367 *
368 * A reference is held on the buffer while on this list.
369 */
370 struct list_head flushing_list;
371
372 /**
373 * LRU list of objects which are not in the ringbuffer and
374 * are ready to unbind, but are still in the GTT.
375 *
376 * last_rendering_seqno is 0 while an object is in this list.
377 *
378 * A reference is not held on the buffer while on this list,
379 * as merely being GTT-bound shouldn't prevent its being
380 * freed, and we'll pull it off the list in the free path.
381 */
382 struct list_head inactive_list;
383
384 /**
385 * List of breadcrumbs associated with GPU requests currently
386 * outstanding.
387 */
388 struct list_head request_list;
389
390 /**
391 * We leave the user IRQ off as much as possible,
392 * but this means that requests will finish and never
393 * be retired once the system goes idle. Set a timer to
394 * fire periodically while the ring is running. When it
395 * fires, go retire requests.
396 */
397 struct delayed_work retire_work;
398
399 uint32_t next_gem_seqno;
400
401 /**
402 * Waiting sequence number, if any
403 */
404 uint32_t waiting_gem_seqno;
405
406 /**
407 * Last seq seen at irq time
408 */
409 uint32_t irq_gem_seqno;
410
411 /**
412 * Flag if the X Server, and thus DRM, is not currently in
413 * control of the device.
414 *
415 * This is set between LeaveVT and EnterVT. It needs to be
416 * replaced with a semaphore. It also needs to be
417 * transitioned away from for kernel modesetting.
418 */
419 int suspended;
420
421 /**
422 * Flag if the hardware appears to be wedged.
423 *
424 * This is set when attempts to idle the device timeout.
425 * It prevents command submission from occuring and makes
426 * every pending request fail
427 */
428 int wedged;
429
430 /** Bit 6 swizzling required for X tiling */
431 uint32_t bit_6_swizzle_x;
432 /** Bit 6 swizzling required for Y tiling */
433 uint32_t bit_6_swizzle_y;
434
435 /* storage for physical objects */
436 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
437 } mm;
438 struct sdvo_device_mapping sdvo_mappings[2];
439 } drm_i915_private_t;
440
441 /** driver private structure attached to each drm_gem_object */
442 struct drm_i915_gem_object {
443 struct drm_gem_object *obj;
444
445 /** Current space allocated to this object in the GTT, if any. */
446 struct drm_mm_node *gtt_space;
447
448 /** This object's place on the active/flushing/inactive lists */
449 struct list_head list;
450
451 /**
452 * This is set if the object is on the active or flushing lists
453 * (has pending rendering), and is not set if it's on inactive (ready
454 * to be unbound).
455 */
456 int active;
457
458 /**
459 * This is set if the object has been written to since last bound
460 * to the GTT
461 */
462 int dirty;
463
464 /** AGP memory structure for our GTT binding. */
465 DRM_AGP_MEM *agp_mem;
466
467 struct page **pages;
468 int pages_refcount;
469
470 /**
471 * Current offset of the object in GTT space.
472 *
473 * This is the same as gtt_space->start
474 */
475 uint32_t gtt_offset;
476 /**
477 * Required alignment for the object
478 */
479 uint32_t gtt_alignment;
480 /**
481 * Fake offset for use by mmap(2)
482 */
483 uint64_t mmap_offset;
484
485 /**
486 * Fence register bits (if any) for this object. Will be set
487 * as needed when mapped into the GTT.
488 * Protected by dev->struct_mutex.
489 */
490 int fence_reg;
491
492 /** Boolean whether this object has a valid gtt offset. */
493 int gtt_bound;
494
495 /** How many users have pinned this object in GTT space */
496 int pin_count;
497
498 /** Breadcrumb of last rendering to the buffer. */
499 uint32_t last_rendering_seqno;
500
501 /** Current tiling mode for the object. */
502 uint32_t tiling_mode;
503 uint32_t stride;
504
505 /** Record of address bit 17 of each page at last unbind. */
506 long *bit_17;
507
508 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
509 uint32_t agp_type;
510
511 /**
512 * If present, while GEM_DOMAIN_CPU is in the read domain this array
513 * flags which individual pages are valid.
514 */
515 uint8_t *page_cpu_valid;
516
517 /** User space pin count and filp owning the pin */
518 uint32_t user_pin_count;
519 struct drm_file *pin_filp;
520
521 /** for phy allocated objects */
522 struct drm_i915_gem_phys_object *phys_obj;
523
524 /**
525 * Used for checking the object doesn't appear more than once
526 * in an execbuffer object list.
527 */
528 int in_execbuffer;
529 };
530
531 /**
532 * Request queue structure.
533 *
534 * The request queue allows us to note sequence numbers that have been emitted
535 * and may be associated with active buffers to be retired.
536 *
537 * By keeping this list, we can avoid having to do questionable
538 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
539 * an emission time with seqnos for tracking how far ahead of the GPU we are.
540 */
541 struct drm_i915_gem_request {
542 /** GEM sequence number associated with this request. */
543 uint32_t seqno;
544
545 /** Time at which this request was emitted, in jiffies. */
546 unsigned long emitted_jiffies;
547
548 /** global list entry for this request */
549 struct list_head list;
550
551 /** file_priv list entry for this request */
552 struct list_head client_list;
553 };
554
555 struct drm_i915_file_private {
556 struct {
557 struct list_head request_list;
558 } mm;
559 };
560
561 enum intel_chip_family {
562 CHIP_I8XX = 0x01,
563 CHIP_I9XX = 0x02,
564 CHIP_I915 = 0x04,
565 CHIP_I965 = 0x08,
566 };
567
568 extern struct drm_ioctl_desc i915_ioctls[];
569 extern int i915_max_ioctl;
570 extern unsigned int i915_fbpercrtc;
571
572 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
573 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
574
575 /* i915_dma.c */
576 extern void i915_kernel_lost_context(struct drm_device * dev);
577 extern int i915_driver_load(struct drm_device *, unsigned long flags);
578 extern int i915_driver_unload(struct drm_device *);
579 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
580 extern void i915_driver_lastclose(struct drm_device * dev);
581 extern void i915_driver_preclose(struct drm_device *dev,
582 struct drm_file *file_priv);
583 extern void i915_driver_postclose(struct drm_device *dev,
584 struct drm_file *file_priv);
585 extern int i915_driver_device_is_agp(struct drm_device * dev);
586 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
587 unsigned long arg);
588 extern int i915_emit_box(struct drm_device *dev,
589 struct drm_clip_rect *boxes,
590 int i, int DR1, int DR4);
591
592 /* i915_irq.c */
593 extern int i915_irq_emit(struct drm_device *dev, void *data,
594 struct drm_file *file_priv);
595 extern int i915_irq_wait(struct drm_device *dev, void *data,
596 struct drm_file *file_priv);
597 void i915_user_irq_get(struct drm_device *dev);
598 void i915_user_irq_put(struct drm_device *dev);
599 extern void i915_enable_interrupt (struct drm_device *dev);
600
601 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
602 extern void i915_driver_irq_preinstall(struct drm_device * dev);
603 extern int i915_driver_irq_postinstall(struct drm_device *dev);
604 extern void i915_driver_irq_uninstall(struct drm_device * dev);
605 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
606 struct drm_file *file_priv);
607 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
608 struct drm_file *file_priv);
609 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
610 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
611 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
612 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
613 extern int i915_vblank_swap(struct drm_device *dev, void *data,
614 struct drm_file *file_priv);
615 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
616
617 void
618 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
619
620 void
621 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
622
623
624 /* i915_mem.c */
625 extern int i915_mem_alloc(struct drm_device *dev, void *data,
626 struct drm_file *file_priv);
627 extern int i915_mem_free(struct drm_device *dev, void *data,
628 struct drm_file *file_priv);
629 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
630 struct drm_file *file_priv);
631 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
632 struct drm_file *file_priv);
633 extern void i915_mem_takedown(struct mem_block **heap);
634 extern void i915_mem_release(struct drm_device * dev,
635 struct drm_file *file_priv, struct mem_block *heap);
636 /* i915_gem.c */
637 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
638 struct drm_file *file_priv);
639 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
640 struct drm_file *file_priv);
641 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
642 struct drm_file *file_priv);
643 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
644 struct drm_file *file_priv);
645 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
646 struct drm_file *file_priv);
647 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
648 struct drm_file *file_priv);
649 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
650 struct drm_file *file_priv);
651 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
652 struct drm_file *file_priv);
653 int i915_gem_execbuffer(struct drm_device *dev, void *data,
654 struct drm_file *file_priv);
655 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
656 struct drm_file *file_priv);
657 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
658 struct drm_file *file_priv);
659 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
660 struct drm_file *file_priv);
661 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
662 struct drm_file *file_priv);
663 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
664 struct drm_file *file_priv);
665 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
666 struct drm_file *file_priv);
667 int i915_gem_set_tiling(struct drm_device *dev, void *data,
668 struct drm_file *file_priv);
669 int i915_gem_get_tiling(struct drm_device *dev, void *data,
670 struct drm_file *file_priv);
671 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
672 struct drm_file *file_priv);
673 void i915_gem_load(struct drm_device *dev);
674 int i915_gem_init_object(struct drm_gem_object *obj);
675 void i915_gem_free_object(struct drm_gem_object *obj);
676 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
677 void i915_gem_object_unpin(struct drm_gem_object *obj);
678 int i915_gem_object_unbind(struct drm_gem_object *obj);
679 void i915_gem_lastclose(struct drm_device *dev);
680 uint32_t i915_get_gem_seqno(struct drm_device *dev);
681 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
682 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
683 void i915_gem_retire_requests(struct drm_device *dev);
684 void i915_gem_retire_work_handler(struct work_struct *work);
685 void i915_gem_clflush_object(struct drm_gem_object *obj);
686 int i915_gem_object_set_domain(struct drm_gem_object *obj,
687 uint32_t read_domains,
688 uint32_t write_domain);
689 int i915_gem_init_ringbuffer(struct drm_device *dev);
690 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
691 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
692 unsigned long end);
693 int i915_gem_idle(struct drm_device *dev);
694 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
695 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
696 int write);
697 int i915_gem_attach_phys_object(struct drm_device *dev,
698 struct drm_gem_object *obj, int id);
699 void i915_gem_detach_phys_object(struct drm_device *dev,
700 struct drm_gem_object *obj);
701 void i915_gem_free_all_phys_object(struct drm_device *dev);
702 int i915_gem_object_get_pages(struct drm_gem_object *obj);
703 void i915_gem_object_put_pages(struct drm_gem_object *obj);
704 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
705
706 /* i915_gem_tiling.c */
707 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
708 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
709 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
710
711 /* i915_gem_debug.c */
712 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
713 const char *where, uint32_t mark);
714 #if WATCH_INACTIVE
715 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
716 #else
717 #define i915_verify_inactive(dev, file, line)
718 #endif
719 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
720 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
721 const char *where, uint32_t mark);
722 void i915_dump_lru(struct drm_device *dev, const char *where);
723
724 /* i915_debugfs.c */
725 int i915_gem_debugfs_init(struct drm_minor *minor);
726 void i915_gem_debugfs_cleanup(struct drm_minor *minor);
727
728 /* i915_suspend.c */
729 extern int i915_save_state(struct drm_device *dev);
730 extern int i915_restore_state(struct drm_device *dev);
731
732 /* i915_suspend.c */
733 extern int i915_save_state(struct drm_device *dev);
734 extern int i915_restore_state(struct drm_device *dev);
735
736 #ifdef CONFIG_ACPI
737 /* i915_opregion.c */
738 extern int intel_opregion_init(struct drm_device *dev, int resume);
739 extern void intel_opregion_free(struct drm_device *dev, int suspend);
740 extern void opregion_asle_intr(struct drm_device *dev);
741 extern void opregion_enable_asle(struct drm_device *dev);
742 #else
743 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
744 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
745 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
746 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
747 #endif
748
749 /* modesetting */
750 extern void intel_modeset_init(struct drm_device *dev);
751 extern void intel_modeset_cleanup(struct drm_device *dev);
752
753 /**
754 * Lock test for when it's just for synchronization of ring access.
755 *
756 * In that case, we don't need to do it when GEM is initialized as nobody else
757 * has access to the ring.
758 */
759 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
760 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
761 LOCK_TEST_WITH_RETURN(dev, file_priv); \
762 } while (0)
763
764 #define I915_READ(reg) readl(dev_priv->regs + (reg))
765 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
766 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
767 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
768 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
769 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
770 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
771 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
772 #define POSTING_READ(reg) (void)I915_READ(reg)
773
774 #define I915_VERBOSE 0
775
776 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
777 volatile char *virt;
778
779 #define BEGIN_LP_RING(n) do { \
780 if (I915_VERBOSE) \
781 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
782 if (dev_priv->ring.space < (n)*4) \
783 i915_wait_ring(dev, (n)*4, __func__); \
784 outcount = 0; \
785 outring = dev_priv->ring.tail; \
786 ringmask = dev_priv->ring.tail_mask; \
787 virt = dev_priv->ring.virtual_start; \
788 } while (0)
789
790 #define OUT_RING(n) do { \
791 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
792 *(volatile unsigned int *)(virt + outring) = (n); \
793 outcount++; \
794 outring += 4; \
795 outring &= ringmask; \
796 } while (0)
797
798 #define ADVANCE_LP_RING() do { \
799 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
800 dev_priv->ring.tail = outring; \
801 dev_priv->ring.space -= outcount * 4; \
802 I915_WRITE(PRB0_TAIL, outring); \
803 } while(0)
804
805 /**
806 * Reads a dword out of the status page, which is written to from the command
807 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
808 * MI_STORE_DATA_IMM.
809 *
810 * The following dwords have a reserved meaning:
811 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
812 * 0x04: ring 0 head pointer
813 * 0x05: ring 1 head pointer (915-class)
814 * 0x06: ring 2 head pointer (915-class)
815 * 0x10-0x1b: Context status DWords (GM45)
816 * 0x1f: Last written status offset. (GM45)
817 *
818 * The area from dword 0x20 to 0x3ff is available for driver usage.
819 */
820 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
821 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
822 #define I915_GEM_HWS_INDEX 0x20
823 #define I915_BREADCRUMB_INDEX 0x21
824
825 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
826
827 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
828 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
829 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
830 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
831 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
832
833 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
834 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
835 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
836 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
837 (dev)->pci_device == 0x27AE)
838 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
839 (dev)->pci_device == 0x2982 || \
840 (dev)->pci_device == 0x2992 || \
841 (dev)->pci_device == 0x29A2 || \
842 (dev)->pci_device == 0x2A02 || \
843 (dev)->pci_device == 0x2A12 || \
844 (dev)->pci_device == 0x2A42 || \
845 (dev)->pci_device == 0x2E02 || \
846 (dev)->pci_device == 0x2E12 || \
847 (dev)->pci_device == 0x2E22 || \
848 (dev)->pci_device == 0x2E32 || \
849 (dev)->pci_device == 0x0042 || \
850 (dev)->pci_device == 0x0046)
851
852 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
853 (dev)->pci_device == 0x2A12)
854
855 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
856
857 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
858 (dev)->pci_device == 0x2E12 || \
859 (dev)->pci_device == 0x2E22 || \
860 (dev)->pci_device == 0x2E32 || \
861 IS_GM45(dev))
862
863 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
864 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
865 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
866
867 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
868 (dev)->pci_device == 0x29B2 || \
869 (dev)->pci_device == 0x29D2 || \
870 (IS_IGD(dev)))
871
872 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
873 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
874 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
875
876 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
877 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
878 IS_IGDNG(dev))
879
880 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
881 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
882 IS_IGD(dev) || IS_IGDNG_M(dev))
883
884 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
885 IS_IGDNG(dev))
886 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
887 * rows, which changed the alignment requirements and fence programming.
888 */
889 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
890 IS_I915GM(dev)))
891 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
892 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
893 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
894 /* dsparb controlled by hw only */
895 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev))
896
897 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
898
899 #endif
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