drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include "i915_reg.h"
  36 #include "intel_bios.h"
  37 #include "intel_ringbuffer.h"
  38 #include <linux/io-mapping.h>
  39 #include <linux/i2c.h>
  40 #include <linux/i2c-algo-bit.h>
  41 #include <drm/intel-gtt.h>
  42 #include <linux/backlight.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/kref.h>
  45 #include <linux/pm_qos.h>
  46
  47 /* General customization:
  48  */
  49
  50 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  51
  52 #define DRIVER_NAME             "i915"
  53 #define DRIVER_DESC             "Intel Graphics"
  54 #define DRIVER_DATE             "20080730"
  55
  56 enum pipe {
  57         INVALID_PIPE = -1,
  58         PIPE_A = 0,
  59         PIPE_B,
  60         PIPE_C,
  61         _PIPE_EDP,
  62         I915_MAX_PIPES = _PIPE_EDP
  63 };
  64 #define pipe_name(p) ((p) + 'A')
  65
  66 enum transcoder {
  67         TRANSCODER_A = 0,
  68         TRANSCODER_B,
  69         TRANSCODER_C,
  70         TRANSCODER_EDP,
  71         I915_MAX_TRANSCODERS
  72 };
  73 #define transcoder_name(t) ((t) + 'A')
  74
  75 enum plane {
  76         PLANE_A = 0,
  77         PLANE_B,
  78         PLANE_C,
  79 };
  80 #define plane_name(p) ((p) + 'A')
  81
  82 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
  83
  84 enum port {
  85         PORT_A = 0,
  86         PORT_B,
  87         PORT_C,
  88         PORT_D,
  89         PORT_E,
  90         I915_MAX_PORTS
  91 };
  92 #define port_name(p) ((p) + 'A')
  93
  94 #define I915_NUM_PHYS_VLV 1
  95
  96 enum dpio_channel {
  97         DPIO_CH0,
  98         DPIO_CH1
  99 };
 100
 101 enum dpio_phy {
 102         DPIO_PHY0,
 103         DPIO_PHY1
 104 };
 105
 106 enum intel_display_power_domain {
 107         POWER_DOMAIN_PIPE_A,
 108         POWER_DOMAIN_PIPE_B,
 109         POWER_DOMAIN_PIPE_C,
 110         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 111         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 112         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 113         POWER_DOMAIN_TRANSCODER_A,
 114         POWER_DOMAIN_TRANSCODER_B,
 115         POWER_DOMAIN_TRANSCODER_C,
 116         POWER_DOMAIN_TRANSCODER_EDP,
 117         POWER_DOMAIN_VGA,
 118         POWER_DOMAIN_AUDIO,
 119         POWER_DOMAIN_INIT,
 120
 121         POWER_DOMAIN_NUM,
 122 };
 123
 124 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 125
 126 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 127 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 128                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 129 #define POWER_DOMAIN_TRANSCODER(tran) \
 130         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 131          (tran) + POWER_DOMAIN_TRANSCODER_A)
 132
 133 #define HSW_ALWAYS_ON_POWER_DOMAINS (           \
 134         BIT(POWER_DOMAIN_PIPE_A) |              \
 135         BIT(POWER_DOMAIN_TRANSCODER_EDP))
 136 #define BDW_ALWAYS_ON_POWER_DOMAINS (           \
 137         BIT(POWER_DOMAIN_PIPE_A) |              \
 138         BIT(POWER_DOMAIN_TRANSCODER_EDP) |      \
 139         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
 140
 141 enum hpd_pin {
 142         HPD_NONE = 0,
 143         HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
 144         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 145         HPD_CRT,
 146         HPD_SDVO_B,
 147         HPD_SDVO_C,
 148         HPD_PORT_B,
 149         HPD_PORT_C,
 150         HPD_PORT_D,
 151         HPD_NUM_PINS
 152 };
 153
 154 #define I915_GEM_GPU_DOMAINS \
 155         (I915_GEM_DOMAIN_RENDER | \
 156          I915_GEM_DOMAIN_SAMPLER | \
 157          I915_GEM_DOMAIN_COMMAND | \
 158          I915_GEM_DOMAIN_INSTRUCTION | \
 159          I915_GEM_DOMAIN_VERTEX)
 160
 161 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
 162
 163 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 164         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 165                 if ((intel_encoder)->base.crtc == (__crtc))
 166
 167 struct drm_i915_private;
 168
 169 enum intel_dpll_id {
 170         DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
 171         /* real shared dpll ids must be >= 0 */
 172         DPLL_ID_PCH_PLL_A,
 173         DPLL_ID_PCH_PLL_B,
 174 };
 175 #define I915_NUM_PLLS 2
 176
 177 struct intel_dpll_hw_state {
 178         uint32_t dpll;
 179         uint32_t dpll_md;
 180         uint32_t fp0;
 181         uint32_t fp1;
 182 };
 183
 184 struct intel_shared_dpll {
 185         int refcount; /* count of number of CRTCs sharing this PLL */
 186         int active; /* count of number of active CRTCs (i.e. DPMS on) */
 187         bool on; /* is the PLL actually active? Disabled during modeset */
 188         const char *name;
 189         /* should match the index in the dev_priv->shared_dplls array */
 190         enum intel_dpll_id id;
 191         struct intel_dpll_hw_state hw_state;
 192         void (*mode_set)(struct drm_i915_private *dev_priv,
 193                          struct intel_shared_dpll *pll);
 194         void (*enable)(struct drm_i915_private *dev_priv,
 195                        struct intel_shared_dpll *pll);
 196         void (*disable)(struct drm_i915_private *dev_priv,
 197                         struct intel_shared_dpll *pll);
 198         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 199                              struct intel_shared_dpll *pll,
 200                              struct intel_dpll_hw_state *hw_state);
 201 };
 202
 203 /* Used by dp and fdi links */
 204 struct intel_link_m_n {
 205         uint32_t        tu;
 206         uint32_t        gmch_m;
 207         uint32_t        gmch_n;
 208         uint32_t        link_m;
 209         uint32_t        link_n;
 210 };
 211
 212 void intel_link_compute_m_n(int bpp, int nlanes,
 213                             int pixel_clock, int link_clock,
 214                             struct intel_link_m_n *m_n);
 215
 216 struct intel_ddi_plls {
 217         int spll_refcount;
 218         int wrpll1_refcount;
 219         int wrpll2_refcount;
 220 };
 221
 222 /* Interface history:
 223  *
 224  * 1.1: Original.
 225  * 1.2: Add Power Management
 226  * 1.3: Add vblank support
 227  * 1.4: Fix cmdbuffer path, add heap destroy
 228  * 1.5: Add vblank pipe configuration
 229  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 230  *      - Support vertical blank on secondary display pipe
 231  */
 232 #define DRIVER_MAJOR            1
 233 #define DRIVER_MINOR            6
 234 #define DRIVER_PATCHLEVEL       0
 235
 236 #define WATCH_LISTS     0
 237 #define WATCH_GTT       0
 238
 239 #define I915_GEM_PHYS_CURSOR_0 1
 240 #define I915_GEM_PHYS_CURSOR_1 2
 241 #define I915_GEM_PHYS_OVERLAY_REGS 3
 242 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 243
 244 struct drm_i915_gem_phys_object {
 245         int id;
 246         struct page **page_list;
 247         drm_dma_handle_t *handle;
 248         struct drm_i915_gem_object *cur_obj;
 249 };
 250
 251 struct opregion_header;
 252 struct opregion_acpi;
 253 struct opregion_swsci;
 254 struct opregion_asle;
 255
 256 struct intel_opregion {
 257         struct opregion_header __iomem *header;
 258         struct opregion_acpi __iomem *acpi;
 259         struct opregion_swsci __iomem *swsci;
 260         u32 swsci_gbda_sub_functions;
 261         u32 swsci_sbcb_sub_functions;
 262         struct opregion_asle __iomem *asle;
 263         void __iomem *vbt;
 264         u32 __iomem *lid_state;
 265         struct work_struct asle_work;
 266 };
 267 #define OPREGION_SIZE            (8*1024)
 268
 269 struct intel_overlay;
 270 struct intel_overlay_error_state;
 271
 272 struct drm_i915_master_private {
 273         drm_local_map_t *sarea;
 274         struct _drm_i915_sarea *sarea_priv;
 275 };
 276 #define I915_FENCE_REG_NONE -1
 277 #define I915_MAX_NUM_FENCES 32
 278 /* 32 fences + sign bit for FENCE_REG_NONE */
 279 #define I915_MAX_NUM_FENCE_BITS 6
 280
 281 struct drm_i915_fence_reg {
 282         struct list_head lru_list;
 283         struct drm_i915_gem_object *obj;
 284         int pin_count;
 285 };
 286
 287 struct sdvo_device_mapping {
 288         u8 initialized;
 289         u8 dvo_port;
 290         u8 slave_addr;
 291         u8 dvo_wiring;
 292         u8 i2c_pin;
 293         u8 ddc_pin;
 294 };
 295
 296 struct intel_display_error_state;
 297
 298 struct drm_i915_error_state {
 299         struct kref ref;
 300         struct timeval time;
 301
 302         /* Generic register state */
 303         u32 eir;
 304         u32 pgtbl_er;
 305         u32 ier;
 306         u32 ccid;
 307         u32 derrmr;
 308         u32 forcewake;
 309         u32 error; /* gen6+ */
 310         u32 err_int; /* gen7 */
 311         u32 done_reg;
 312         u32 gac_eco;
 313         u32 gam_ecochk;
 314         u32 gab_ctl;
 315         u32 gfx_mode;
 316         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 317         u32 pipestat[I915_MAX_PIPES];
 318         u64 fence[I915_MAX_NUM_FENCES];
 319         struct intel_overlay_error_state *overlay;
 320         struct intel_display_error_state *display;
 321
 322         struct drm_i915_error_ring {
 323                 bool valid;
 324                 /* Software tracked state */
 325                 bool waiting;
 326                 int hangcheck_score;
 327                 enum intel_ring_hangcheck_action hangcheck_action;
 328                 int num_requests;
 329
 330                 /* our own tracking of ring head and tail */
 331                 u32 cpu_ring_head;
 332                 u32 cpu_ring_tail;
 333
 334                 u32 semaphore_seqno[I915_NUM_RINGS - 1];
 335
 336                 /* Register state */
 337                 u32 tail;
 338                 u32 head;
 339                 u32 ctl;
 340                 u32 hws;
 341                 u32 ipeir;
 342                 u32 ipehr;
 343                 u32 instdone;
 344                 u32 acthd;
 345                 u32 bbstate;
 346                 u32 instpm;
 347                 u32 instps;
 348                 u32 seqno;
 349                 u64 bbaddr;
 350                 u32 fault_reg;
 351                 u32 faddr;
 352                 u32 rc_psmi; /* sleep state */
 353                 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
 354
 355                 struct drm_i915_error_object {
 356                         int page_count;
 357                         u32 gtt_offset;
 358                         u32 *pages[0];
 359                 } *ringbuffer, *batchbuffer, *ctx, *hws_page;
 360
 361                 struct drm_i915_error_request {
 362                         long jiffies;
 363                         u32 seqno;
 364                         u32 tail;
 365                 } *requests;
 366
 367                 struct {
 368                         u32 gfx_mode;
 369                         union {
 370                                 u64 pdp[4];
 371                                 u32 pp_dir_base;
 372                         };
 373                 } vm_info;
 374         } ring[I915_NUM_RINGS];
 375         struct drm_i915_error_buffer {
 376                 u32 size;
 377                 u32 name;
 378                 u32 rseqno, wseqno;
 379                 u32 gtt_offset;
 380                 u32 read_domains;
 381                 u32 write_domain;
 382                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 383                 s32 pinned:2;
 384                 u32 tiling:2;
 385                 u32 dirty:1;
 386                 u32 purgeable:1;
 387                 s32 ring:4;
 388                 u32 cache_level:3;
 389         } **active_bo, **pinned_bo;
 390
 391         u32 *active_bo_count, *pinned_bo_count;
 392 };
 393
 394 struct intel_connector;
 395 struct intel_crtc_config;
 396 struct intel_crtc;
 397 struct intel_limit;
 398 struct dpll;
 399
 400 struct drm_i915_display_funcs {
 401         bool (*fbc_enabled)(struct drm_device *dev);
 402         void (*enable_fbc)(struct drm_crtc *crtc);
 403         void (*disable_fbc)(struct drm_device *dev);
 404         int (*get_display_clock_speed)(struct drm_device *dev);
 405         int (*get_fifo_size)(struct drm_device *dev, int plane);
 406         /**
 407          * find_dpll() - Find the best values for the PLL
 408          * @limit: limits for the PLL
 409          * @crtc: current CRTC
 410          * @target: target frequency in kHz
 411          * @refclk: reference clock frequency in kHz
 412          * @match_clock: if provided, @best_clock P divider must
 413          *               match the P divider from @match_clock
 414          *               used for LVDS downclocking
 415          * @best_clock: best PLL values found
 416          *
 417          * Returns true on success, false on failure.
 418          */
 419         bool (*find_dpll)(const struct intel_limit *limit,
 420                           struct drm_crtc *crtc,
 421                           int target, int refclk,
 422                           struct dpll *match_clock,
 423                           struct dpll *best_clock);
 424         void (*update_wm)(struct drm_crtc *crtc);
 425         void (*update_sprite_wm)(struct drm_plane *plane,
 426                                  struct drm_crtc *crtc,
 427                                  uint32_t sprite_width, int pixel_size,
 428                                  bool enable, bool scaled);
 429         void (*modeset_global_resources)(struct drm_device *dev);
 430         /* Returns the active state of the crtc, and if the crtc is active,
 431          * fills out the pipe-config with the hw state. */
 432         bool (*get_pipe_config)(struct intel_crtc *,
 433                                 struct intel_crtc_config *);
 434         int (*crtc_mode_set)(struct drm_crtc *crtc,
 435                              int x, int y,
 436                              struct drm_framebuffer *old_fb);
 437         void (*crtc_enable)(struct drm_crtc *crtc);
 438         void (*crtc_disable)(struct drm_crtc *crtc);
 439         void (*off)(struct drm_crtc *crtc);
 440         void (*write_eld)(struct drm_connector *connector,
 441                           struct drm_crtc *crtc,
 442                           struct drm_display_mode *mode);
 443         void (*fdi_link_train)(struct drm_crtc *crtc);
 444         void (*init_clock_gating)(struct drm_device *dev);
 445         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 446                           struct drm_framebuffer *fb,
 447                           struct drm_i915_gem_object *obj,
 448                           uint32_t flags);
 449         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 450                             int x, int y);
 451         void (*hpd_irq_setup)(struct drm_device *dev);
 452         /* clock updates for mode set */
 453         /* cursor updates */
 454         /* render clock increase/decrease */
 455         /* display clock increase/decrease */
 456         /* pll clock increase/decrease */
 457
 458         int (*setup_backlight)(struct intel_connector *connector);
 459         uint32_t (*get_backlight)(struct intel_connector *connector);
 460         void (*set_backlight)(struct intel_connector *connector,
 461                               uint32_t level);
 462         void (*disable_backlight)(struct intel_connector *connector);
 463         void (*enable_backlight)(struct intel_connector *connector);
 464 };
 465
 466 struct intel_uncore_funcs {
 467         void (*force_wake_get)(struct drm_i915_private *dev_priv,
 468                                                         int fw_engine);
 469         void (*force_wake_put)(struct drm_i915_private *dev_priv,
 470                                                         int fw_engine);
 471
 472         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 473         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 474         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 475         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 476
 477         void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
 478                                 uint8_t val, bool trace);
 479         void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
 480                                 uint16_t val, bool trace);
 481         void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
 482                                 uint32_t val, bool trace);
 483         void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
 484                                 uint64_t val, bool trace);
 485 };
 486
 487 struct intel_uncore {
 488         spinlock_t lock; /** lock is also taken in irq contexts. */
 489
 490         struct intel_uncore_funcs funcs;
 491
 492         unsigned fifo_count;
 493         unsigned forcewake_count;
 494
 495         unsigned fw_rendercount;
 496         unsigned fw_mediacount;
 497
 498         struct delayed_work force_wake_work;
 499 };
 500
 501 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
 502         func(is_mobile) sep \
 503         func(is_i85x) sep \
 504         func(is_i915g) sep \
 505         func(is_i945gm) sep \
 506         func(is_g33) sep \
 507         func(need_gfx_hws) sep \
 508         func(is_g4x) sep \
 509         func(is_pineview) sep \
 510         func(is_broadwater) sep \
 511         func(is_crestline) sep \
 512         func(is_ivybridge) sep \
 513         func(is_valleyview) sep \
 514         func(is_haswell) sep \
 515         func(is_preliminary) sep \
 516         func(has_fbc) sep \
 517         func(has_pipe_cxsr) sep \
 518         func(has_hotplug) sep \
 519         func(cursor_needs_physical) sep \
 520         func(has_overlay) sep \
 521         func(overlay_needs_physical) sep \
 522         func(supports_tv) sep \
 523         func(has_llc) sep \
 524         func(has_ddi) sep \
 525         func(has_fpga_dbg)
 526
 527 #define DEFINE_FLAG(name) u8 name:1
 528 #define SEP_SEMICOLON ;
 529
 530 struct intel_device_info {
 531         u32 display_mmio_offset;
 532         u8 num_pipes:3;
 533         u8 gen;
 534         u8 ring_mask; /* Rings supported by the HW */
 535         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
 536         /* Register offsets for the various display pipes and transcoders */
 537         int pipe_offsets[I915_MAX_TRANSCODERS];
 538         int trans_offsets[I915_MAX_TRANSCODERS];
 539         int dpll_offsets[I915_MAX_PIPES];
 540         int dpll_md_offsets[I915_MAX_PIPES];
 541         int palette_offsets[I915_MAX_PIPES];
 542 };
 543
 544 #undef DEFINE_FLAG
 545 #undef SEP_SEMICOLON
 546
 547 enum i915_cache_level {
 548         I915_CACHE_NONE = 0,
 549         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 550         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 551                               caches, eg sampler/render caches, and the
 552                               large Last-Level-Cache. LLC is coherent with
 553                               the CPU, but L3 is only visible to the GPU. */
 554         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 555 };
 556
 557 typedef uint32_t gen6_gtt_pte_t;
 558
 559 /**
 560  * A VMA represents a GEM BO that is bound into an address space. Therefore, a
 561  * VMA's presence cannot be guaranteed before binding, or after unbinding the
 562  * object into/from the address space.
 563  *
 564  * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
 565  * will always be <= an objects lifetime. So object refcounting should cover us.
 566  */
 567 struct i915_vma {
 568         struct drm_mm_node node;
 569         struct drm_i915_gem_object *obj;
 570         struct i915_address_space *vm;
 571
 572         /** This object's place on the active/inactive lists */
 573         struct list_head mm_list;
 574
 575         struct list_head vma_link; /* Link in the object's VMA list */
 576
 577         /** This vma's place in the batchbuffer or on the eviction list */
 578         struct list_head exec_list;
 579
 580         /**
 581          * Used for performing relocations during execbuffer insertion.
 582          */
 583         struct hlist_node exec_node;
 584         unsigned long exec_handle;
 585         struct drm_i915_gem_exec_object2 *exec_entry;
 586
 587         /**
 588          * How many users have pinned this object in GTT space. The following
 589          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 590          * (via user_pin_count), execbuffer (objects are not allowed multiple
 591          * times for the same batchbuffer), and the framebuffer code. When
 592          * switching/pageflipping, the framebuffer code has at most two buffers
 593          * pinned per crtc.
 594          *
 595          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 596          * bits with absolutely no headroom. So use 4 bits. */
 597         unsigned int pin_count:4;
 598 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 599
 600         /** Unmap an object from an address space. This usually consists of
 601          * setting the valid PTE entries to a reserved scratch page. */
 602         void (*unbind_vma)(struct i915_vma *vma);
 603         /* Map an object into an address space with the given cache flags. */
 604 #define GLOBAL_BIND (1<<0)
 605         void (*bind_vma)(struct i915_vma *vma,
 606                          enum i915_cache_level cache_level,
 607                          u32 flags);
 608 };
 609
 610 struct i915_address_space {
 611         struct drm_mm mm;
 612         struct drm_device *dev;
 613         struct list_head global_link;
 614         unsigned long start;            /* Start offset always 0 for dri2 */
 615         size_t total;           /* size addr space maps (ex. 2GB for ggtt) */
 616
 617         struct {
 618                 dma_addr_t addr;
 619                 struct page *page;
 620         } scratch;
 621
 622         /**
 623          * List of objects currently involved in rendering.
 624          *
 625          * Includes buffers having the contents of their GPU caches
 626          * flushed, not necessarily primitives.  last_rendering_seqno
 627          * represents when the rendering involved will be completed.
 628          *
 629          * A reference is held on the buffer while on this list.
 630          */
 631         struct list_head active_list;
 632
 633         /**
 634          * LRU list of objects which are not in the ringbuffer and
 635          * are ready to unbind, but are still in the GTT.
 636          *
 637          * last_rendering_seqno is 0 while an object is in this list.
 638          *
 639          * A reference is not held on the buffer while on this list,
 640          * as merely being GTT-bound shouldn't prevent its being
 641          * freed, and we'll pull it off the list in the free path.
 642          */
 643         struct list_head inactive_list;
 644
 645         /* FIXME: Need a more generic return type */
 646         gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
 647                                      enum i915_cache_level level,
 648                                      bool valid); /* Create a valid PTE */
 649         void (*clear_range)(struct i915_address_space *vm,
 650                             unsigned int first_entry,
 651                             unsigned int num_entries,
 652                             bool use_scratch);
 653         void (*insert_entries)(struct i915_address_space *vm,
 654                                struct sg_table *st,
 655                                unsigned int first_entry,
 656                                enum i915_cache_level cache_level);
 657         void (*cleanup)(struct i915_address_space *vm);
 658 };
 659
 660 /* The Graphics Translation Table is the way in which GEN hardware translates a
 661  * Graphics Virtual Address into a Physical Address. In addition to the normal
 662  * collateral associated with any va->pa translations GEN hardware also has a
 663  * portion of the GTT which can be mapped by the CPU and remain both coherent
 664  * and correct (in cases like swizzling). That region is referred to as GMADR in
 665  * the spec.
 666  */
 667 struct i915_gtt {
 668         struct i915_address_space base;
 669         size_t stolen_size;             /* Total size of stolen memory */
 670
 671         unsigned long mappable_end;     /* End offset that we can CPU map */
 672         struct io_mapping *mappable;    /* Mapping to our CPU mappable region */
 673         phys_addr_t mappable_base;      /* PA of our GMADR */
 674
 675         /** "Graphics Stolen Memory" holds the global PTEs */
 676         void __iomem *gsm;
 677
 678         bool do_idle_maps;
 679
 680         int mtrr;
 681
 682         /* global gtt ops */
 683         int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
 684                           size_t *stolen, phys_addr_t *mappable_base,
 685                           unsigned long *mappable_end);
 686 };
 687 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
 688
 689 struct i915_hw_ppgtt {
 690         struct i915_address_space base;
 691         struct kref ref;
 692         struct drm_mm_node node;
 693         unsigned num_pd_entries;
 694         union {
 695                 struct page **pt_pages;
 696                 struct page *gen8_pt_pages;
 697         };
 698         struct page *pd_pages;
 699         int num_pd_pages;
 700         int num_pt_pages;
 701         union {
 702                 uint32_t pd_offset;
 703                 dma_addr_t pd_dma_addr[4];
 704         };
 705         union {
 706                 dma_addr_t *pt_dma_addr;
 707                 dma_addr_t *gen8_pt_dma_addr[4];
 708         };
 709
 710         int (*enable)(struct i915_hw_ppgtt *ppgtt);
 711         int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
 712                          struct intel_ring_buffer *ring,
 713                          bool synchronous);
 714         void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
 715 };
 716
 717 struct i915_ctx_hang_stats {
 718         /* This context had batch pending when hang was declared */
 719         unsigned batch_pending;
 720
 721         /* This context had batch active when hang was declared */
 722         unsigned batch_active;
 723
 724         /* Time when this context was last blamed for a GPU reset */
 725         unsigned long guilty_ts;
 726
 727         /* This context is banned to submit more work */
 728         bool banned;
 729 };
 730
 731 /* This must match up with the value previously used for execbuf2.rsvd1. */
 732 #define DEFAULT_CONTEXT_ID 0
 733 struct i915_hw_context {
 734         struct kref ref;
 735         int id;
 736         bool is_initialized;
 737         uint8_t remap_slice;
 738         struct drm_i915_file_private *file_priv;
 739         struct intel_ring_buffer *last_ring;
 740         struct drm_i915_gem_object *obj;
 741         struct i915_ctx_hang_stats hang_stats;
 742         struct i915_address_space *vm;
 743
 744         struct list_head link;
 745 };
 746
 747 struct i915_fbc {
 748         unsigned long size;
 749         unsigned int fb_id;
 750         enum plane plane;
 751         int y;
 752
 753         struct drm_mm_node *compressed_fb;
 754         struct drm_mm_node *compressed_llb;
 755
 756         struct intel_fbc_work {
 757                 struct delayed_work work;
 758                 struct drm_crtc *crtc;
 759                 struct drm_framebuffer *fb;
 760         } *fbc_work;
 761
 762         enum no_fbc_reason {
 763                 FBC_OK, /* FBC is enabled */
 764                 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
 765                 FBC_NO_OUTPUT, /* no outputs enabled to compress */
 766                 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
 767                 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 768                 FBC_MODE_TOO_LARGE, /* mode too large for compression */
 769                 FBC_BAD_PLANE, /* fbc not supported on plane */
 770                 FBC_NOT_TILED, /* buffer not tiled */
 771                 FBC_MULTIPLE_PIPES, /* more than one pipe active */
 772                 FBC_MODULE_PARAM,
 773                 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
 774         } no_fbc_reason;
 775 };
 776
 777 struct i915_psr {
 778         bool sink_support;
 779         bool source_ok;
 780 };
 781
 782 enum intel_pch {
 783         PCH_NONE = 0,   /* No PCH present */
 784         PCH_IBX,        /* Ibexpeak PCH */
 785         PCH_CPT,        /* Cougarpoint PCH */
 786         PCH_LPT,        /* Lynxpoint PCH */
 787         PCH_NOP,
 788 };
 789
 790 enum intel_sbi_destination {
 791         SBI_ICLK,
 792         SBI_MPHY,
 793 };
 794
 795 #define QUIRK_PIPEA_FORCE (1<<0)
 796 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 797 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 798
 799 struct intel_fbdev;
 800 struct intel_fbc_work;
 801
 802 struct intel_gmbus {
 803         struct i2c_adapter adapter;
 804         u32 force_bit;
 805         u32 reg0;
 806         u32 gpio_reg;
 807         struct i2c_algo_bit_data bit_algo;
 808         struct drm_i915_private *dev_priv;
 809 };
 810
 811 struct i915_suspend_saved_registers {
 812         u8 saveLBB;
 813         u32 saveDSPACNTR;
 814         u32 saveDSPBCNTR;
 815         u32 saveDSPARB;
 816         u32 savePIPEACONF;
 817         u32 savePIPEBCONF;
 818         u32 savePIPEASRC;
 819         u32 savePIPEBSRC;
 820         u32 saveFPA0;
 821         u32 saveFPA1;
 822         u32 saveDPLL_A;
 823         u32 saveDPLL_A_MD;
 824         u32 saveHTOTAL_A;
 825         u32 saveHBLANK_A;
 826         u32 saveHSYNC_A;
 827         u32 saveVTOTAL_A;
 828         u32 saveVBLANK_A;
 829         u32 saveVSYNC_A;
 830         u32 saveBCLRPAT_A;
 831         u32 saveTRANSACONF;
 832         u32 saveTRANS_HTOTAL_A;
 833         u32 saveTRANS_HBLANK_A;
 834         u32 saveTRANS_HSYNC_A;
 835         u32 saveTRANS_VTOTAL_A;
 836         u32 saveTRANS_VBLANK_A;
 837         u32 saveTRANS_VSYNC_A;
 838         u32 savePIPEASTAT;
 839         u32 saveDSPASTRIDE;
 840         u32 saveDSPASIZE;
 841         u32 saveDSPAPOS;
 842         u32 saveDSPAADDR;
 843         u32 saveDSPASURF;
 844         u32 saveDSPATILEOFF;
 845         u32 savePFIT_PGM_RATIOS;
 846         u32 saveBLC_HIST_CTL;
 847         u32 saveBLC_PWM_CTL;
 848         u32 saveBLC_PWM_CTL2;
 849         u32 saveBLC_HIST_CTL_B;
 850         u32 saveBLC_CPU_PWM_CTL;
 851         u32 saveBLC_CPU_PWM_CTL2;
 852         u32 saveFPB0;
 853         u32 saveFPB1;
 854         u32 saveDPLL_B;
 855         u32 saveDPLL_B_MD;
 856         u32 saveHTOTAL_B;
 857         u32 saveHBLANK_B;
 858         u32 saveHSYNC_B;
 859         u32 saveVTOTAL_B;
 860         u32 saveVBLANK_B;
 861         u32 saveVSYNC_B;
 862         u32 saveBCLRPAT_B;
 863         u32 saveTRANSBCONF;
 864         u32 saveTRANS_HTOTAL_B;
 865         u32 saveTRANS_HBLANK_B;
 866         u32 saveTRANS_HSYNC_B;
 867         u32 saveTRANS_VTOTAL_B;
 868         u32 saveTRANS_VBLANK_B;
 869         u32 saveTRANS_VSYNC_B;
 870         u32 savePIPEBSTAT;
 871         u32 saveDSPBSTRIDE;
 872         u32 saveDSPBSIZE;
 873         u32 saveDSPBPOS;
 874         u32 saveDSPBADDR;
 875         u32 saveDSPBSURF;
 876         u32 saveDSPBTILEOFF;
 877         u32 saveVGA0;
 878         u32 saveVGA1;
 879         u32 saveVGA_PD;
 880         u32 saveVGACNTRL;
 881         u32 saveADPA;
 882         u32 saveLVDS;
 883         u32 savePP_ON_DELAYS;
 884         u32 savePP_OFF_DELAYS;
 885         u32 saveDVOA;
 886         u32 saveDVOB;
 887         u32 saveDVOC;
 888         u32 savePP_ON;
 889         u32 savePP_OFF;
 890         u32 savePP_CONTROL;
 891         u32 savePP_DIVISOR;
 892         u32 savePFIT_CONTROL;
 893         u32 save_palette_a[256];
 894         u32 save_palette_b[256];
 895         u32 saveFBC_CONTROL;
 896         u32 saveIER;
 897         u32 saveIIR;
 898         u32 saveIMR;
 899         u32 saveDEIER;
 900         u32 saveDEIMR;
 901         u32 saveGTIER;
 902         u32 saveGTIMR;
 903         u32 saveFDI_RXA_IMR;
 904         u32 saveFDI_RXB_IMR;
 905         u32 saveCACHE_MODE_0;
 906         u32 saveMI_ARB_STATE;
 907         u32 saveSWF0[16];
 908         u32 saveSWF1[16];
 909         u32 saveSWF2[3];
 910         u8 saveMSR;
 911         u8 saveSR[8];
 912         u8 saveGR[25];
 913         u8 saveAR_INDEX;
 914         u8 saveAR[21];
 915         u8 saveDACMASK;
 916         u8 saveCR[37];
 917         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 918         u32 saveCURACNTR;
 919         u32 saveCURAPOS;
 920         u32 saveCURABASE;
 921         u32 saveCURBCNTR;
 922         u32 saveCURBPOS;
 923         u32 saveCURBBASE;
 924         u32 saveCURSIZE;
 925         u32 saveDP_B;
 926         u32 saveDP_C;
 927         u32 saveDP_D;
 928         u32 savePIPEA_GMCH_DATA_M;
 929         u32 savePIPEB_GMCH_DATA_M;
 930         u32 savePIPEA_GMCH_DATA_N;
 931         u32 savePIPEB_GMCH_DATA_N;
 932         u32 savePIPEA_DP_LINK_M;
 933         u32 savePIPEB_DP_LINK_M;
 934         u32 savePIPEA_DP_LINK_N;
 935         u32 savePIPEB_DP_LINK_N;
 936         u32 saveFDI_RXA_CTL;
 937         u32 saveFDI_TXA_CTL;
 938         u32 saveFDI_RXB_CTL;
 939         u32 saveFDI_TXB_CTL;
 940         u32 savePFA_CTL_1;
 941         u32 savePFB_CTL_1;
 942         u32 savePFA_WIN_SZ;
 943         u32 savePFB_WIN_SZ;
 944         u32 savePFA_WIN_POS;
 945         u32 savePFB_WIN_POS;
 946         u32 savePCH_DREF_CONTROL;
 947         u32 saveDISP_ARB_CTL;
 948         u32 savePIPEA_DATA_M1;
 949         u32 savePIPEA_DATA_N1;
 950         u32 savePIPEA_LINK_M1;
 951         u32 savePIPEA_LINK_N1;
 952         u32 savePIPEB_DATA_M1;
 953         u32 savePIPEB_DATA_N1;
 954         u32 savePIPEB_LINK_M1;
 955         u32 savePIPEB_LINK_N1;
 956         u32 saveMCHBAR_RENDER_STANDBY;
 957         u32 savePCH_PORT_HOTPLUG;
 958 };
 959
 960 struct intel_gen6_power_mgmt {
 961         /* work and pm_iir are protected by dev_priv->irq_lock */
 962         struct work_struct work;
 963         u32 pm_iir;
 964
 965         u8 cur_delay;
 966         u8 min_delay;
 967         u8 max_delay;
 968         u8 rpe_delay;
 969         u8 rp1_delay;
 970         u8 rp0_delay;
 971         u8 hw_max;
 972
 973         bool rp_up_masked;
 974         bool rp_down_masked;
 975
 976         int last_adj;
 977         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
 978
 979         bool enabled;
 980         struct delayed_work delayed_resume_work;
 981
 982         /*
 983          * Protects RPS/RC6 register access and PCU communication.
 984          * Must be taken after struct_mutex if nested.
 985          */
 986         struct mutex hw_lock;
 987 };
 988
 989 /* defined intel_pm.c */
 990 extern spinlock_t mchdev_lock;
 991
 992 struct intel_ilk_power_mgmt {
 993         u8 cur_delay;
 994         u8 min_delay;
 995         u8 max_delay;
 996         u8 fmax;
 997         u8 fstart;
 998
 999         u64 last_count1;
1000         unsigned long last_time1;
1001         unsigned long chipset_power;
1002         u64 last_count2;
1003         struct timespec last_time2;
1004         unsigned long gfx_power;
1005         u8 corr;
1006
1007         int c_m;
1008         int r_t;
1009
1010         struct drm_i915_gem_object *pwrctx;
1011         struct drm_i915_gem_object *renderctx;
1012 };
1013
1014 /* Power well structure for haswell */
1015 struct i915_power_well {
1016         const char *name;
1017         bool always_on;
1018         /* power well enable/disable usage count */
1019         int count;
1020         unsigned long domains;
1021         void *data;
1022         void (*set)(struct drm_device *dev, struct i915_power_well *power_well,
1023                     bool enable);
1024         bool (*is_enabled)(struct drm_device *dev,
1025                            struct i915_power_well *power_well);
1026 };
1027
1028 struct i915_power_domains {
1029         /*
1030          * Power wells needed for initialization at driver init and suspend
1031          * time are on. They are kept on until after the first modeset.
1032          */
1033         bool init_power_on;
1034         int power_well_count;
1035
1036         struct mutex lock;
1037         int domain_use_count[POWER_DOMAIN_NUM];
1038         struct i915_power_well *power_wells;
1039 };
1040
1041 struct i915_dri1_state {
1042         unsigned allow_batchbuffer : 1;
1043         u32 __iomem *gfx_hws_cpu_addr;
1044
1045         unsigned int cpp;
1046         int back_offset;
1047         int front_offset;
1048         int current_page;
1049         int page_flipping;
1050
1051         uint32_t counter;
1052 };
1053
1054 struct i915_ums_state {
1055         /**
1056          * Flag if the X Server, and thus DRM, is not currently in
1057          * control of the device.
1058          *
1059          * This is set between LeaveVT and EnterVT.  It needs to be
1060          * replaced with a semaphore.  It also needs to be
1061          * transitioned away from for kernel modesetting.
1062          */
1063         int mm_suspended;
1064 };
1065
1066 #define MAX_L3_SLICES 2
1067 struct intel_l3_parity {
1068         u32 *remap_info[MAX_L3_SLICES];
1069         struct work_struct error_work;
1070         int which_slice;
1071 };
1072
1073 struct i915_gem_mm {
1074         /** Memory allocator for GTT stolen memory */
1075         struct drm_mm stolen;
1076         /** List of all objects in gtt_space. Used to restore gtt
1077          * mappings on resume */
1078         struct list_head bound_list;
1079         /**
1080          * List of objects which are not bound to the GTT (thus
1081          * are idle and not used by the GPU) but still have
1082          * (presumably uncached) pages still attached.
1083          */
1084         struct list_head unbound_list;
1085
1086         /** Usable portion of the GTT for GEM */
1087         unsigned long stolen_base; /* limited to low memory (32-bit) */
1088
1089         /** PPGTT used for aliasing the PPGTT with the GTT */
1090         struct i915_hw_ppgtt *aliasing_ppgtt;
1091
1092         struct shrinker inactive_shrinker;
1093         bool shrinker_no_lock_stealing;
1094
1095         /** LRU list of objects with fence regs on them. */
1096         struct list_head fence_list;
1097
1098         /**
1099          * We leave the user IRQ off as much as possible,
1100          * but this means that requests will finish and never
1101          * be retired once the system goes idle. Set a timer to
1102          * fire periodically while the ring is running. When it
1103          * fires, go retire requests.
1104          */
1105         struct delayed_work retire_work;
1106
1107         /**
1108          * When we detect an idle GPU, we want to turn on
1109          * powersaving features. So once we see that there
1110          * are no more requests outstanding and no more
1111          * arrive within a small period of time, we fire
1112          * off the idle_work.
1113          */
1114         struct delayed_work idle_work;
1115
1116         /**
1117          * Are we in a non-interruptible section of code like
1118          * modesetting?
1119          */
1120         bool interruptible;
1121
1122         /** Bit 6 swizzling required for X tiling */
1123         uint32_t bit_6_swizzle_x;
1124         /** Bit 6 swizzling required for Y tiling */
1125         uint32_t bit_6_swizzle_y;
1126
1127         /* storage for physical objects */
1128         struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1129
1130         /* accounting, useful for userland debugging */
1131         spinlock_t object_stat_lock;
1132         size_t object_memory;
1133         u32 object_count;
1134 };
1135
1136 struct drm_i915_error_state_buf {
1137         unsigned bytes;
1138         unsigned size;
1139         int err;
1140         u8 *buf;
1141         loff_t start;
1142         loff_t pos;
1143 };
1144
1145 struct i915_error_state_file_priv {
1146         struct drm_device *dev;
1147         struct drm_i915_error_state *error;
1148 };
1149
1150 struct i915_gpu_error {
1151         /* For hangcheck timer */
1152 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1153 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1154         /* Hang gpu twice in this window and your context gets banned */
1155 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1156
1157         struct timer_list hangcheck_timer;
1158
1159         /* For reset and error_state handling. */
1160         spinlock_t lock;
1161         /* Protected by the above dev->gpu_error.lock. */
1162         struct drm_i915_error_state *first_error;
1163         struct work_struct work;
1164
1165
1166         unsigned long missed_irq_rings;
1167
1168         /**
1169          * State variable controlling the reset flow and count
1170          *
1171          * This is a counter which gets incremented when reset is triggered,
1172          * and again when reset has been handled. So odd values (lowest bit set)
1173          * means that reset is in progress and even values that
1174          * (reset_counter >> 1):th reset was successfully completed.
1175          *
1176          * If reset is not completed succesfully, the I915_WEDGE bit is
1177          * set meaning that hardware is terminally sour and there is no
1178          * recovery. All waiters on the reset_queue will be woken when
1179          * that happens.
1180          *
1181          * This counter is used by the wait_seqno code to notice that reset
1182          * event happened and it needs to restart the entire ioctl (since most
1183          * likely the seqno it waited for won't ever signal anytime soon).
1184          *
1185          * This is important for lock-free wait paths, where no contended lock
1186          * naturally enforces the correct ordering between the bail-out of the
1187          * waiter and the gpu reset work code.
1188          */
1189         atomic_t reset_counter;
1190
1191 #define I915_RESET_IN_PROGRESS_FLAG     1
1192 #define I915_WEDGED                     (1 << 31)
1193
1194         /**
1195          * Waitqueue to signal when the reset has completed. Used by clients
1196          * that wait for dev_priv->mm.wedged to settle.
1197          */
1198         wait_queue_head_t reset_queue;
1199
1200         /* For gpu hang simulation. */
1201         unsigned int stop_rings;
1202
1203         /* For missed irq/seqno simulation. */
1204         unsigned int test_irq_rings;
1205 };
1206
1207 enum modeset_restore {
1208         MODESET_ON_LID_OPEN,
1209         MODESET_DONE,
1210         MODESET_SUSPENDED,
1211 };
1212
1213 struct ddi_vbt_port_info {
1214         uint8_t hdmi_level_shift;
1215
1216         uint8_t supports_dvi:1;
1217         uint8_t supports_hdmi:1;
1218         uint8_t supports_dp:1;
1219 };
1220
1221 struct intel_vbt_data {
1222         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1223         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1224
1225         /* Feature bits */
1226         unsigned int int_tv_support:1;
1227         unsigned int lvds_dither:1;
1228         unsigned int lvds_vbt:1;
1229         unsigned int int_crt_support:1;
1230         unsigned int lvds_use_ssc:1;
1231         unsigned int display_clock_mode:1;
1232         unsigned int fdi_rx_polarity_inverted:1;
1233         int lvds_ssc_freq;
1234         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1235
1236         /* eDP */
1237         int edp_rate;
1238         int edp_lanes;
1239         int edp_preemphasis;
1240         int edp_vswing;
1241         bool edp_initialized;
1242         bool edp_support;
1243         int edp_bpp;
1244         struct edp_power_seq edp_pps;
1245
1246         struct {
1247                 u16 pwm_freq_hz;
1248                 bool active_low_pwm;
1249         } backlight;
1250
1251         /* MIPI DSI */
1252         struct {
1253                 u16 panel_id;
1254         } dsi;
1255
1256         int crt_ddc_pin;
1257
1258         int child_dev_num;
1259         union child_device_config *child_dev;
1260
1261         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1262 };
1263
1264 enum intel_ddb_partitioning {
1265         INTEL_DDB_PART_1_2,
1266         INTEL_DDB_PART_5_6, /* IVB+ */
1267 };
1268
1269 struct intel_wm_level {
1270         bool enable;
1271         uint32_t pri_val;
1272         uint32_t spr_val;
1273         uint32_t cur_val;
1274         uint32_t fbc_val;
1275 };
1276
1277 struct ilk_wm_values {
1278         uint32_t wm_pipe[3];
1279         uint32_t wm_lp[3];
1280         uint32_t wm_lp_spr[3];
1281         uint32_t wm_linetime[3];
1282         bool enable_fbc_wm;
1283         enum intel_ddb_partitioning partitioning;
1284 };
1285
1286 /*
1287  * This struct tracks the state needed for the Package C8+ feature.
1288  *
1289  * Package states C8 and deeper are really deep PC states that can only be
1290  * reached when all the devices on the system allow it, so even if the graphics
1291  * device allows PC8+, it doesn't mean the system will actually get to these
1292  * states.
1293  *
1294  * Our driver only allows PC8+ when all the outputs are disabled, the power well
1295  * is disabled and the GPU is idle. When these conditions are met, we manually
1296  * do the other conditions: disable the interrupts, clocks and switch LCPLL
1297  * refclk to Fclk.
1298  *
1299  * When we really reach PC8 or deeper states (not just when we allow it) we lose
1300  * the state of some registers, so when we come back from PC8+ we need to
1301  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1302  * need to take care of the registers kept by RC6.
1303  *
1304  * The interrupt disabling is part of the requirements. We can only leave the
1305  * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1306  * can lock the machine.
1307  *
1308  * Ideally every piece of our code that needs PC8+ disabled would call
1309  * hsw_disable_package_c8, which would increment disable_count and prevent the
1310  * system from reaching PC8+. But we don't have a symmetric way to do this for
1311  * everything, so we have the requirements_met and gpu_idle variables. When we
1312  * switch requirements_met or gpu_idle to true we decrease disable_count, and
1313  * increase it in the opposite case. The requirements_met variable is true when
1314  * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1315  * variable is true when the GPU is idle.
1316  *
1317  * In addition to everything, we only actually enable PC8+ if disable_count
1318  * stays at zero for at least some seconds. This is implemented with the
1319  * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1320  * consecutive times when all screens are disabled and some background app
1321  * queries the state of our connectors, or we have some application constantly
1322  * waking up to use the GPU. Only after the enable_work function actually
1323  * enables PC8+ the "enable" variable will become true, which means that it can
1324  * be false even if disable_count is 0.
1325  *
1326  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1327  * goes back to false exactly before we reenable the IRQs. We use this variable
1328  * to check if someone is trying to enable/disable IRQs while they're supposed
1329  * to be disabled. This shouldn't happen and we'll print some error messages in
1330  * case it happens, but if it actually happens we'll also update the variables
1331  * inside struct regsave so when we restore the IRQs they will contain the
1332  * latest expected values.
1333  *
1334  * For more, read "Display Sequences for Package C8" on our documentation.
1335  */
1336 struct i915_package_c8 {
1337         bool requirements_met;
1338         bool gpu_idle;
1339         bool irqs_disabled;
1340         /* Only true after the delayed work task actually enables it. */
1341         bool enabled;
1342         int disable_count;
1343         struct mutex lock;
1344         struct delayed_work enable_work;
1345
1346         struct {
1347                 uint32_t deimr;
1348                 uint32_t sdeimr;
1349                 uint32_t gtimr;
1350                 uint32_t gtier;
1351                 uint32_t gen6_pmimr;
1352         } regsave;
1353 };
1354
1355 struct i915_runtime_pm {
1356         bool suspended;
1357 };
1358
1359 enum intel_pipe_crc_source {
1360         INTEL_PIPE_CRC_SOURCE_NONE,
1361         INTEL_PIPE_CRC_SOURCE_PLANE1,
1362         INTEL_PIPE_CRC_SOURCE_PLANE2,
1363         INTEL_PIPE_CRC_SOURCE_PF,
1364         INTEL_PIPE_CRC_SOURCE_PIPE,
1365         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1366         INTEL_PIPE_CRC_SOURCE_TV,
1367         INTEL_PIPE_CRC_SOURCE_DP_B,
1368         INTEL_PIPE_CRC_SOURCE_DP_C,
1369         INTEL_PIPE_CRC_SOURCE_DP_D,
1370         INTEL_PIPE_CRC_SOURCE_AUTO,
1371         INTEL_PIPE_CRC_SOURCE_MAX,
1372 };
1373
1374 struct intel_pipe_crc_entry {
1375         uint32_t frame;
1376         uint32_t crc[5];
1377 };
1378
1379 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1380 struct intel_pipe_crc {
1381         spinlock_t lock;
1382         bool opened;            /* exclusive access to the result file */
1383         struct intel_pipe_crc_entry *entries;
1384         enum intel_pipe_crc_source source;
1385         int head, tail;
1386         wait_queue_head_t wq;
1387 };
1388
1389 typedef struct drm_i915_private {
1390         struct drm_device *dev;
1391         struct kmem_cache *slab;
1392
1393         const struct intel_device_info *info;
1394
1395         int relative_constants_mode;
1396
1397         void __iomem *regs;
1398
1399         struct intel_uncore uncore;
1400
1401         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1402
1403
1404         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1405          * controller on different i2c buses. */
1406         struct mutex gmbus_mutex;
1407
1408         /**
1409          * Base address of the gmbus and gpio block.
1410          */
1411         uint32_t gpio_mmio_base;
1412
1413         wait_queue_head_t gmbus_wait_queue;
1414
1415         struct pci_dev *bridge_dev;
1416         struct intel_ring_buffer ring[I915_NUM_RINGS];
1417         uint32_t last_seqno, next_seqno;
1418
1419         drm_dma_handle_t *status_page_dmah;
1420         struct resource mch_res;
1421
1422         /* protects the irq masks */
1423         spinlock_t irq_lock;
1424
1425         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1426         struct pm_qos_request pm_qos;
1427
1428         /* DPIO indirect register protection */
1429         struct mutex dpio_lock;
1430
1431         /** Cached value of IMR to avoid reads in updating the bitfield */
1432         union {
1433                 u32 irq_mask;
1434                 u32 de_irq_mask[I915_MAX_PIPES];
1435         };
1436         u32 gt_irq_mask;
1437         u32 pm_irq_mask;
1438
1439         struct work_struct hotplug_work;
1440         bool enable_hotplug_processing;
1441         struct {
1442                 unsigned long hpd_last_jiffies;
1443                 int hpd_cnt;
1444                 enum {
1445                         HPD_ENABLED = 0,
1446                         HPD_DISABLED = 1,
1447                         HPD_MARK_DISABLED = 2
1448                 } hpd_mark;
1449         } hpd_stats[HPD_NUM_PINS];
1450         u32 hpd_event_bits;
1451         struct timer_list hotplug_reenable_timer;
1452
1453         int num_plane;
1454
1455         struct i915_fbc fbc;
1456         struct intel_opregion opregion;
1457         struct intel_vbt_data vbt;
1458
1459         /* overlay */
1460         struct intel_overlay *overlay;
1461
1462         /* backlight registers and fields in struct intel_panel */
1463         spinlock_t backlight_lock;
1464
1465         /* LVDS info */
1466         bool no_aux_handshake;
1467
1468         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1469         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1470         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1471
1472         unsigned int fsb_freq, mem_freq, is_ddr3;
1473
1474         /**
1475          * wq - Driver workqueue for GEM.
1476          *
1477          * NOTE: Work items scheduled here are not allowed to grab any modeset
1478          * locks, for otherwise the flushing done in the pageflip code will
1479          * result in deadlocks.
1480          */
1481         struct workqueue_struct *wq;
1482
1483         /* Display functions */
1484         struct drm_i915_display_funcs display;
1485
1486         /* PCH chipset type */
1487         enum intel_pch pch_type;
1488         unsigned short pch_id;
1489
1490         unsigned long quirks;
1491
1492         enum modeset_restore modeset_restore;
1493         struct mutex modeset_restore_lock;
1494
1495         struct list_head vm_list; /* Global list of all address spaces */
1496         struct i915_gtt gtt; /* VMA representing the global address space */
1497
1498         struct i915_gem_mm mm;
1499
1500         /* Kernel Modesetting */
1501
1502         struct sdvo_device_mapping sdvo_mappings[2];
1503
1504         struct drm_crtc *plane_to_crtc_mapping[3];
1505         struct drm_crtc *pipe_to_crtc_mapping[3];
1506         wait_queue_head_t pending_flip_queue;
1507
1508 #ifdef CONFIG_DEBUG_FS
1509         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1510 #endif
1511
1512         int num_shared_dpll;
1513         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1514         struct intel_ddi_plls ddi_plls;
1515         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1516
1517         /* Reclocking support */
1518         bool render_reclock_avail;
1519         bool lvds_downclock_avail;
1520         /* indicates the reduced downclock for LVDS*/
1521         int lvds_downclock;
1522         u16 orig_clock;
1523
1524         bool mchbar_need_disable;
1525
1526         struct intel_l3_parity l3_parity;
1527
1528         /* Cannot be determined by PCIID. You must always read a register. */
1529         size_t ellc_size;
1530
1531         /* gen6+ rps state */
1532         struct intel_gen6_power_mgmt rps;
1533
1534         /* ilk-only ips/rps state. Everything in here is protected by the global
1535          * mchdev_lock in intel_pm.c */
1536         struct intel_ilk_power_mgmt ips;
1537
1538         struct i915_power_domains power_domains;
1539
1540         struct i915_psr psr;
1541
1542         struct i915_gpu_error gpu_error;
1543
1544         struct drm_i915_gem_object *vlv_pctx;
1545
1546 #ifdef CONFIG_DRM_I915_FBDEV
1547         /* list of fbdev register on this device */
1548         struct intel_fbdev *fbdev;
1549 #endif
1550
1551         /*
1552          * The console may be contended at resume, but we don't
1553          * want it to block on it.
1554          */
1555         struct work_struct console_resume_work;
1556
1557         struct drm_property *broadcast_rgb_property;
1558         struct drm_property *force_audio_property;
1559
1560         uint32_t hw_context_size;
1561         struct list_head context_list;
1562
1563         u32 fdi_rx_config;
1564
1565         struct i915_suspend_saved_registers regfile;
1566
1567         struct {
1568                 /*
1569                  * Raw watermark latency values:
1570                  * in 0.1us units for WM0,
1571                  * in 0.5us units for WM1+.
1572                  */
1573                 /* primary */
1574                 uint16_t pri_latency[5];
1575                 /* sprite */
1576                 uint16_t spr_latency[5];
1577                 /* cursor */
1578                 uint16_t cur_latency[5];
1579
1580                 /* current hardware state */
1581                 struct ilk_wm_values hw;
1582         } wm;
1583
1584         struct i915_package_c8 pc8;
1585
1586         struct i915_runtime_pm pm;
1587
1588         /* Old dri1 support infrastructure, beware the dragons ya fools entering
1589          * here! */
1590         struct i915_dri1_state dri1;
1591         /* Old ums support infrastructure, same warning applies. */
1592         struct i915_ums_state ums;
1593 } drm_i915_private_t;
1594
1595 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1596 {
1597         return dev->dev_private;
1598 }
1599
1600 /* Iterate over initialised rings */
1601 #define for_each_ring(ring__, dev_priv__, i__) \
1602         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1603                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1604
1605 enum hdmi_force_audio {
1606         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
1607         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
1608         HDMI_AUDIO_AUTO,                /* trust EDID */
1609         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
1610 };
1611
1612 #define I915_GTT_OFFSET_NONE ((u32)-1)
1613
1614 struct drm_i915_gem_object_ops {
1615         /* Interface between the GEM object and its backing storage.
1616          * get_pages() is called once prior to the use of the associated set
1617          * of pages before to binding them into the GTT, and put_pages() is
1618          * called after we no longer need them. As we expect there to be
1619          * associated cost with migrating pages between the backing storage
1620          * and making them available for the GPU (e.g. clflush), we may hold
1621          * onto the pages after they are no longer referenced by the GPU
1622          * in case they may be used again shortly (for example migrating the
1623          * pages to a different memory domain within the GTT). put_pages()
1624          * will therefore most likely be called when the object itself is
1625          * being released or under memory pressure (where we attempt to
1626          * reap pages for the shrinker).
1627          */
1628         int (*get_pages)(struct drm_i915_gem_object *);
1629         void (*put_pages)(struct drm_i915_gem_object *);
1630 };
1631
1632 struct drm_i915_gem_object {
1633         struct drm_gem_object base;
1634
1635         const struct drm_i915_gem_object_ops *ops;
1636
1637         /** List of VMAs backed by this object */
1638         struct list_head vma_list;
1639
1640         /** Stolen memory for this object, instead of being backed by shmem. */
1641         struct drm_mm_node *stolen;
1642         struct list_head global_list;
1643
1644         struct list_head ring_list;
1645         /** Used in execbuf to temporarily hold a ref */
1646         struct list_head obj_exec_link;
1647
1648         /**
1649          * This is set if the object is on the active lists (has pending
1650          * rendering and so a non-zero seqno), and is not set if it i s on
1651          * inactive (ready to be unbound) list.
1652          */
1653         unsigned int active:1;
1654
1655         /**
1656          * This is set if the object has been written to since last bound
1657          * to the GTT
1658          */
1659         unsigned int dirty:1;
1660
1661         /**
1662          * Fence register bits (if any) for this object.  Will be set
1663          * as needed when mapped into the GTT.
1664          * Protected by dev->struct_mutex.
1665          */
1666         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1667
1668         /**
1669          * Advice: are the backing pages purgeable?
1670          */
1671         unsigned int madv:2;
1672
1673         /**
1674          * Current tiling mode for the object.
1675          */
1676         unsigned int tiling_mode:2;
1677         /**
1678          * Whether the tiling parameters for the currently associated fence
1679          * register have changed. Note that for the purposes of tracking
1680          * tiling changes we also treat the unfenced register, the register
1681          * slot that the object occupies whilst it executes a fenced
1682          * command (such as BLT on gen2/3), as a "fence".
1683          */
1684         unsigned int fence_dirty:1;
1685
1686         /**
1687          * Is the object at the current location in the gtt mappable and
1688          * fenceable? Used to avoid costly recalculations.
1689          */
1690         unsigned int map_and_fenceable:1;
1691
1692         /**
1693          * Whether the current gtt mapping needs to be mappable (and isn't just
1694          * mappable by accident). Track pin and fault separate for a more
1695          * accurate mappable working set.
1696          */
1697         unsigned int fault_mappable:1;
1698         unsigned int pin_mappable:1;
1699         unsigned int pin_display:1;
1700
1701         /*
1702          * Is the GPU currently using a fence to access this buffer,
1703          */
1704         unsigned int pending_fenced_gpu_access:1;
1705         unsigned int fenced_gpu_access:1;
1706
1707         unsigned int cache_level:3;
1708
1709         unsigned int has_aliasing_ppgtt_mapping:1;
1710         unsigned int has_global_gtt_mapping:1;
1711         unsigned int has_dma_mapping:1;
1712
1713         struct sg_table *pages;
1714         int pages_pin_count;
1715
1716         /* prime dma-buf support */
1717         void *dma_buf_vmapping;
1718         int vmapping_count;
1719
1720         struct intel_ring_buffer *ring;
1721
1722         /** Breadcrumb of last rendering to the buffer. */
1723         uint32_t last_read_seqno;
1724         uint32_t last_write_seqno;
1725         /** Breadcrumb of last fenced GPU access to the buffer. */
1726         uint32_t last_fenced_seqno;
1727
1728         /** Current tiling stride for the object, if it's tiled. */
1729         uint32_t stride;
1730
1731         /** References from framebuffers, locks out tiling changes. */
1732         unsigned long framebuffer_references;
1733
1734         /** Record of address bit 17 of each page at last unbind. */
1735         unsigned long *bit_17;
1736
1737         /** User space pin count and filp owning the pin */
1738         unsigned long user_pin_count;
1739         struct drm_file *pin_filp;
1740
1741         /** for phy allocated objects */
1742         struct drm_i915_gem_phys_object *phys_obj;
1743 };
1744 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1745
1746 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1747
1748 /**
1749  * Request queue structure.
1750  *
1751  * The request queue allows us to note sequence numbers that have been emitted
1752  * and may be associated with active buffers to be retired.
1753  *
1754  * By keeping this list, we can avoid having to do questionable
1755  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1756  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1757  */
1758 struct drm_i915_gem_request {
1759         /** On Which ring this request was generated */
1760         struct intel_ring_buffer *ring;
1761
1762         /** GEM sequence number associated with this request. */
1763         uint32_t seqno;
1764
1765         /** Position in the ringbuffer of the start of the request */
1766         u32 head;
1767
1768         /** Position in the ringbuffer of the end of the request */
1769         u32 tail;
1770
1771         /** Context related to this request */
1772         struct i915_hw_context *ctx;
1773
1774         /** Batch buffer related to this request if any */
1775         struct drm_i915_gem_object *batch_obj;
1776
1777         /** Time at which this request was emitted, in jiffies. */
1778         unsigned long emitted_jiffies;
1779
1780         /** global list entry for this request */
1781         struct list_head list;
1782
1783         struct drm_i915_file_private *file_priv;
1784         /** file_priv list entry for this request */
1785         struct list_head client_list;
1786 };
1787
1788 struct drm_i915_file_private {
1789         struct drm_i915_private *dev_priv;
1790
1791         struct {
1792                 spinlock_t lock;
1793                 struct list_head request_list;
1794                 struct delayed_work idle_work;
1795         } mm;
1796         struct idr context_idr;
1797
1798         struct i915_hw_context *private_default_ctx;
1799         atomic_t rps_wait_boost;
1800 };
1801
1802 #define INTEL_INFO(dev) (to_i915(dev)->info)
1803
1804 #define IS_I830(dev)            ((dev)->pdev->device == 0x3577)
1805 #define IS_845G(dev)            ((dev)->pdev->device == 0x2562)
1806 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1807 #define IS_I865G(dev)           ((dev)->pdev->device == 0x2572)
1808 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1809 #define IS_I915GM(dev)          ((dev)->pdev->device == 0x2592)
1810 #define IS_I945G(dev)           ((dev)->pdev->device == 0x2772)
1811 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1812 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1813 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1814 #define IS_GM45(dev)            ((dev)->pdev->device == 0x2A42)
1815 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1816 #define IS_PINEVIEW_G(dev)      ((dev)->pdev->device == 0xa001)
1817 #define IS_PINEVIEW_M(dev)      ((dev)->pdev->device == 0xa011)
1818 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1819 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1820 #define IS_IRONLAKE_M(dev)      ((dev)->pdev->device == 0x0046)
1821 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1822 #define IS_IVB_GT1(dev)         ((dev)->pdev->device == 0x0156 || \
1823                                  (dev)->pdev->device == 0x0152 || \
1824                                  (dev)->pdev->device == 0x015a)
1825 #define IS_SNB_GT1(dev)         ((dev)->pdev->device == 0x0102 || \
1826                                  (dev)->pdev->device == 0x0106 || \
1827                                  (dev)->pdev->device == 0x010A)
1828 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1829 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1830 #define IS_BROADWELL(dev)       (INTEL_INFO(dev)->gen == 8)
1831 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1832 #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
1833                                  ((dev)->pdev->device & 0xFF00) == 0x0C00)
1834 #define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
1835                                  (((dev)->pdev->device & 0xf) == 0x2  || \
1836                                  ((dev)->pdev->device & 0xf) == 0x6 || \
1837                                  ((dev)->pdev->device & 0xf) == 0xe))
1838 #define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
1839                                  ((dev)->pdev->device & 0xFF00) == 0x0A00)
1840 #define IS_ULT(dev)             (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1841 #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
1842                                  ((dev)->pdev->device & 0x00F0) == 0x0020)
1843 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1844
1845 /*
1846  * The genX designation typically refers to the render engine, so render
1847  * capability related checks should use IS_GEN, while display and other checks
1848  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1849  * chips, etc.).
1850  */
1851 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1852 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1853 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1854 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1855 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1856 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1857 #define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
1858
1859 #define RENDER_RING             (1<<RCS)
1860 #define BSD_RING                (1<<VCS)
1861 #define BLT_RING                (1<<BCS)
1862 #define VEBOX_RING              (1<<VECS)
1863 #define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
1864 #define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
1865 #define HAS_VEBOX(dev)            (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1866 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1867 #define HAS_WT(dev)            (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1868 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1869
1870 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
1871 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
1872 #define HAS_PPGTT(dev)          (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
1873                                  && !IS_BROADWELL(dev))
1874 #define USES_PPGTT(dev)         intel_enable_ppgtt(dev, false)
1875 #define USES_FULL_PPGTT(dev)    intel_enable_ppgtt(dev, true)
1876
1877 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1878 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1879
1880 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1881 #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
1882 /*
1883  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1884  * even when in MSI mode. This results in spurious interrupt warnings if the
1885  * legacy irq no. is shared with another device. The kernel then disables that
1886  * interrupt source and so prevents the other device from working properly.
1887  */
1888 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1889 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1890
1891 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1892  * rows, which changed the alignment requirements and fence programming.
1893  */
1894 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1895                                                       IS_I915GM(dev)))
1896 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1897 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1898 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1899 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1900 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1901
1902 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1903 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1904 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1905
1906 #define HAS_IPS(dev)            (IS_ULT(dev) || IS_BROADWELL(dev))
1907
1908 #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
1909 #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
1910 #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev))
1911 #define HAS_PC8(dev)            (IS_HASWELL(dev)) /* XXX HSW:ULX */
1912 #define HAS_RUNTIME_PM(dev)     (IS_HASWELL(dev))
1913
1914 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
1915 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
1916 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
1917 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
1918 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
1919 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
1920
1921 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1922 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1923 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1924 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1925 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1926 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1927
1928 /* DPF == dynamic parity feature */
1929 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1930 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1931
1932 #define GT_FREQUENCY_MULTIPLIER 50
1933
1934 #include "i915_trace.h"
1935
1936 extern const struct drm_ioctl_desc i915_ioctls[];
1937 extern int i915_max_ioctl;
1938
1939 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1940 extern int i915_resume(struct drm_device *dev);
1941 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1942 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1943
1944 /* i915_params.c */
1945 struct i915_params {
1946         int modeset;
1947         int panel_ignore_lid;
1948         unsigned int powersave;
1949         int semaphores;
1950         unsigned int lvds_downclock;
1951         int lvds_channel_mode;
1952         int panel_use_ssc;
1953         int vbt_sdvo_panel_type;
1954         int enable_rc6;
1955         int enable_fbc;
1956         bool enable_hangcheck;
1957         int enable_ppgtt;
1958         int enable_psr;
1959         unsigned int preliminary_hw_support;
1960         int disable_power_well;
1961         int enable_ips;
1962         bool fastboot;
1963         int enable_pc8;
1964         int pc8_timeout;
1965         bool prefault_disable;
1966         bool reset;
1967         int invert_brightness;
1968 };
1969 extern struct i915_params i915 __read_mostly;
1970
1971                                 /* i915_dma.c */
1972 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1973 extern void i915_kernel_lost_context(struct drm_device * dev);
1974 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1975 extern int i915_driver_unload(struct drm_device *);
1976 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1977 extern void i915_driver_lastclose(struct drm_device * dev);
1978 extern void i915_driver_preclose(struct drm_device *dev,
1979                                  struct drm_file *file_priv);
1980 extern void i915_driver_postclose(struct drm_device *dev,
1981                                   struct drm_file *file_priv);
1982 extern int i915_driver_device_is_agp(struct drm_device * dev);
1983 #ifdef CONFIG_COMPAT
1984 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1985                               unsigned long arg);
1986 #endif
1987 extern int i915_emit_box(struct drm_device *dev,
1988                          struct drm_clip_rect *box,
1989                          int DR1, int DR4);
1990 extern int intel_gpu_reset(struct drm_device *dev);
1991 extern int i915_reset(struct drm_device *dev);
1992 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1993 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1994 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1995 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1996
1997 extern void intel_console_resume(struct work_struct *work);
1998
1999 /* i915_irq.c */
2000 void i915_queue_hangcheck(struct drm_device *dev);
2001 void i915_handle_error(struct drm_device *dev, bool wedged);
2002
2003 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2004                                                         int new_delay);
2005 extern void intel_irq_init(struct drm_device *dev);
2006 extern void intel_hpd_init(struct drm_device *dev);
2007
2008 extern void intel_uncore_sanitize(struct drm_device *dev);
2009 extern void intel_uncore_early_sanitize(struct drm_device *dev);
2010 extern void intel_uncore_init(struct drm_device *dev);
2011 extern void intel_uncore_check_errors(struct drm_device *dev);
2012 extern void intel_uncore_fini(struct drm_device *dev);
2013
2014 void
2015 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
2016
2017 void
2018 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
2019
2020 /* i915_gem.c */
2021 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2022                         struct drm_file *file_priv);
2023 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2024                           struct drm_file *file_priv);
2025 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2026                          struct drm_file *file_priv);
2027 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2028                           struct drm_file *file_priv);
2029 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2030                         struct drm_file *file_priv);
2031 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2032                         struct drm_file *file_priv);
2033 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2034                               struct drm_file *file_priv);
2035 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2036                              struct drm_file *file_priv);
2037 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2038                         struct drm_file *file_priv);
2039 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2040                          struct drm_file *file_priv);
2041 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2042                        struct drm_file *file_priv);
2043 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2044                          struct drm_file *file_priv);
2045 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2046                         struct drm_file *file_priv);
2047 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2048                                struct drm_file *file);
2049 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2050                                struct drm_file *file);
2051 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2052                             struct drm_file *file_priv);
2053 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2054                            struct drm_file *file_priv);
2055 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2056                            struct drm_file *file_priv);
2057 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2058                            struct drm_file *file_priv);
2059 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2060                         struct drm_file *file_priv);
2061 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2062                         struct drm_file *file_priv);
2063 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2064                                 struct drm_file *file_priv);
2065 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2066                         struct drm_file *file_priv);
2067 void i915_gem_load(struct drm_device *dev);
2068 void *i915_gem_object_alloc(struct drm_device *dev);
2069 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2070 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2071                          const struct drm_i915_gem_object_ops *ops);
2072 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2073                                                   size_t size);
2074 void i915_init_vm(struct drm_i915_private *dev_priv,
2075                   struct i915_address_space *vm);
2076 void i915_gem_free_object(struct drm_gem_object *obj);
2077 void i915_gem_vma_destroy(struct i915_vma *vma);
2078
2079 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2080                                      struct i915_address_space *vm,
2081                                      uint32_t alignment,
2082                                      bool map_and_fenceable,
2083                                      bool nonblocking);
2084 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2085 int __must_check i915_vma_unbind(struct i915_vma *vma);
2086 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
2087 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2088 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2089 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2090 void i915_gem_lastclose(struct drm_device *dev);
2091
2092 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2093 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2094 {
2095         struct sg_page_iter sg_iter;
2096
2097         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2098                 return sg_page_iter_page(&sg_iter);
2099
2100         return NULL;
2101 }
2102 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2103 {
2104         BUG_ON(obj->pages == NULL);
2105         obj->pages_pin_count++;
2106 }
2107 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2108 {
2109         BUG_ON(obj->pages_pin_count == 0);
2110         obj->pages_pin_count--;
2111 }
2112
2113 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2114 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2115                          struct intel_ring_buffer *to);
2116 void i915_vma_move_to_active(struct i915_vma *vma,
2117                              struct intel_ring_buffer *ring);
2118 int i915_gem_dumb_create(struct drm_file *file_priv,
2119                          struct drm_device *dev,
2120                          struct drm_mode_create_dumb *args);
2121 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2122                       uint32_t handle, uint64_t *offset);
2123 /**
2124  * Returns true if seq1 is later than seq2.
2125  */
2126 static inline bool
2127 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2128 {
2129         return (int32_t)(seq1 - seq2) >= 0;
2130 }
2131
2132 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2133 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2134 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2135 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2136
2137 static inline bool
2138 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2139 {
2140         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2141                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2142                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2143                 return true;
2144         } else
2145                 return false;
2146 }
2147
2148 static inline void
2149 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2150 {
2151         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2152                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2153                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2154                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2155         }
2156 }
2157
2158 bool i915_gem_retire_requests(struct drm_device *dev);
2159 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2160 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2161                                       bool interruptible);
2162 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2163 {
2164         return unlikely(atomic_read(&error->reset_counter)
2165                         & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2166 }
2167
2168 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2169 {
2170         return atomic_read(&error->reset_counter) & I915_WEDGED;
2171 }
2172
2173 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2174 {
2175         return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2176 }
2177
2178 void i915_gem_reset(struct drm_device *dev);
2179 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2180 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2181 int __must_check i915_gem_init(struct drm_device *dev);
2182 int __must_check i915_gem_init_hw(struct drm_device *dev);
2183 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2184 void i915_gem_init_swizzling(struct drm_device *dev);
2185 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2186 int __must_check i915_gpu_idle(struct drm_device *dev);
2187 int __must_check i915_gem_suspend(struct drm_device *dev);
2188 int __i915_add_request(struct intel_ring_buffer *ring,
2189                        struct drm_file *file,
2190                        struct drm_i915_gem_object *batch_obj,
2191                        u32 *seqno);
2192 #define i915_add_request(ring, seqno) \
2193         __i915_add_request(ring, NULL, NULL, seqno)
2194 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2195                                  uint32_t seqno);
2196 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2197 int __must_check
2198 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2199                                   bool write);
2200 int __must_check
2201 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2202 int __must_check
2203 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2204                                      u32 alignment,
2205                                      struct intel_ring_buffer *pipelined);
2206 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2207 int i915_gem_attach_phys_object(struct drm_device *dev,
2208                                 struct drm_i915_gem_object *obj,
2209                                 int id,
2210                                 int align);
2211 void i915_gem_detach_phys_object(struct drm_device *dev,
2212                                  struct drm_i915_gem_object *obj);
2213 void i915_gem_free_all_phys_object(struct drm_device *dev);
2214 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2215 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2216
2217 uint32_t
2218 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2219 uint32_t
2220 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2221                             int tiling_mode, bool fenced);
2222
2223 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2224                                     enum i915_cache_level cache_level);
2225
2226 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2227                                 struct dma_buf *dma_buf);
2228
2229 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2230                                 struct drm_gem_object *gem_obj, int flags);
2231
2232 void i915_gem_restore_fences(struct drm_device *dev);
2233
2234 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2235                                   struct i915_address_space *vm);
2236 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2237 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2238                         struct i915_address_space *vm);
2239 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2240                                 struct i915_address_space *vm);
2241 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2242                                      struct i915_address_space *vm);
2243 struct i915_vma *
2244 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2245                                   struct i915_address_space *vm);
2246
2247 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2248 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2249         struct i915_vma *vma;
2250         list_for_each_entry(vma, &obj->vma_list, vma_link)
2251                 if (vma->pin_count > 0)
2252                         return true;
2253         return false;
2254 }
2255
2256 /* Some GGTT VM helpers */
2257 #define obj_to_ggtt(obj) \
2258         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2259 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2260 {
2261         struct i915_address_space *ggtt =
2262                 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2263         return vm == ggtt;
2264 }
2265
2266 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2267 {
2268         return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2269 }
2270
2271 static inline unsigned long
2272 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2273 {
2274         return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2275 }
2276
2277 static inline unsigned long
2278 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2279 {
2280         return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2281 }
2282
2283 static inline int __must_check
2284 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2285                       uint32_t alignment,
2286                       bool map_and_fenceable,
2287                       bool nonblocking)
2288 {
2289         return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
2290                                    map_and_fenceable, nonblocking);
2291 }
2292
2293 /* i915_gem_context.c */
2294 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2295 int __must_check i915_gem_context_init(struct drm_device *dev);
2296 void i915_gem_context_fini(struct drm_device *dev);
2297 void i915_gem_context_reset(struct drm_device *dev);
2298 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2299 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2300 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2301 int i915_switch_context(struct intel_ring_buffer *ring,
2302                         struct drm_file *file, struct i915_hw_context *to);
2303 struct i915_hw_context *
2304 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2305 void i915_gem_context_free(struct kref *ctx_ref);
2306 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2307 {
2308         if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2309                 kref_get(&ctx->ref);
2310 }
2311
2312 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2313 {
2314         if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev))
2315                 kref_put(&ctx->ref, i915_gem_context_free);
2316 }
2317
2318 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2319 {
2320         return c->id == DEFAULT_CONTEXT_ID;
2321 }
2322
2323 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2324                                   struct drm_file *file);
2325 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2326                                    struct drm_file *file);
2327
2328 /* i915_gem_evict.c */
2329 int __must_check i915_gem_evict_something(struct drm_device *dev,
2330                                           struct i915_address_space *vm,
2331                                           int min_size,
2332                                           unsigned alignment,
2333                                           unsigned cache_level,
2334                                           bool mappable,
2335                                           bool nonblock);
2336 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2337 int i915_gem_evict_everything(struct drm_device *dev);
2338
2339 /* i915_gem_gtt.c */
2340 void i915_check_and_clear_faults(struct drm_device *dev);
2341 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2342 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2343 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2344 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2345 void i915_gem_init_global_gtt(struct drm_device *dev);
2346 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2347                                unsigned long mappable_end, unsigned long end);
2348 int i915_gem_gtt_init(struct drm_device *dev);
2349 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2350 {
2351         if (INTEL_INFO(dev)->gen < 6)
2352                 intel_gtt_chipset_flush();
2353 }
2354 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
2355 static inline bool intel_enable_ppgtt(struct drm_device *dev, bool full)
2356 {
2357         if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
2358                 return false;
2359
2360         if (i915.enable_ppgtt == 1 && full)
2361                 return false;
2362
2363 #ifdef CONFIG_INTEL_IOMMU
2364         /* Disable ppgtt on SNB if VT-d is on. */
2365         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
2366                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
2367                 return false;
2368         }
2369 #endif
2370
2371         if (full)
2372                 return HAS_PPGTT(dev);
2373         else
2374                 return HAS_ALIASING_PPGTT(dev);
2375 }
2376
2377 static inline void ppgtt_release(struct kref *kref)
2378 {
2379         struct i915_hw_ppgtt *ppgtt = container_of(kref, struct i915_hw_ppgtt, ref);
2380         struct drm_device *dev = ppgtt->base.dev;
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382         struct i915_address_space *vm = &ppgtt->base;
2383
2384         if (ppgtt == dev_priv->mm.aliasing_ppgtt ||
2385             (list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) {
2386                 ppgtt->base.cleanup(&ppgtt->base);
2387                 return;
2388         }
2389
2390         /*
2391          * Make sure vmas are unbound before we take down the drm_mm
2392          *
2393          * FIXME: Proper refcounting should take care of this, this shouldn't be
2394          * needed at all.
2395          */
2396         if (!list_empty(&vm->active_list)) {
2397                 struct i915_vma *vma;
2398
2399                 list_for_each_entry(vma, &vm->active_list, mm_list)
2400                         if (WARN_ON(list_empty(&vma->vma_link) ||
2401                                     list_is_singular(&vma->vma_link)))
2402                                 break;
2403
2404                 i915_gem_evict_vm(&ppgtt->base, true);
2405         } else {
2406                 i915_gem_retire_requests(dev);
2407                 i915_gem_evict_vm(&ppgtt->base, false);
2408         }
2409
2410         ppgtt->base.cleanup(&ppgtt->base);
2411 }
2412
2413 /* i915_gem_stolen.c */
2414 int i915_gem_init_stolen(struct drm_device *dev);
2415 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2416 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2417 void i915_gem_cleanup_stolen(struct drm_device *dev);
2418 struct drm_i915_gem_object *
2419 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2420 struct drm_i915_gem_object *
2421 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2422                                                u32 stolen_offset,
2423                                                u32 gtt_offset,
2424                                                u32 size);
2425 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2426
2427 /* i915_gem_tiling.c */
2428 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2429 {
2430         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2431
2432         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2433                 obj->tiling_mode != I915_TILING_NONE;
2434 }
2435
2436 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2437 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2438 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2439
2440 /* i915_gem_debug.c */
2441 #if WATCH_LISTS
2442 int i915_verify_lists(struct drm_device *dev);
2443 #else
2444 #define i915_verify_lists(dev) 0
2445 #endif
2446
2447 /* i915_debugfs.c */
2448 int i915_debugfs_init(struct drm_minor *minor);
2449 void i915_debugfs_cleanup(struct drm_minor *minor);
2450 #ifdef CONFIG_DEBUG_FS
2451 void intel_display_crc_init(struct drm_device *dev);
2452 #else
2453 static inline void intel_display_crc_init(struct drm_device *dev) {}
2454 #endif
2455
2456 /* i915_gpu_error.c */
2457 __printf(2, 3)
2458 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2459 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2460                             const struct i915_error_state_file_priv *error);
2461 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2462                               size_t count, loff_t pos);
2463 static inline void i915_error_state_buf_release(
2464         struct drm_i915_error_state_buf *eb)
2465 {
2466         kfree(eb->buf);
2467 }
2468 void i915_capture_error_state(struct drm_device *dev);
2469 void i915_error_state_get(struct drm_device *dev,
2470                           struct i915_error_state_file_priv *error_priv);
2471 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2472 void i915_destroy_error_state(struct drm_device *dev);
2473
2474 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2475 const char *i915_cache_level_str(int type);
2476
2477 /* i915_suspend.c */
2478 extern int i915_save_state(struct drm_device *dev);
2479 extern int i915_restore_state(struct drm_device *dev);
2480
2481 /* i915_ums.c */
2482 void i915_save_display_reg(struct drm_device *dev);
2483 void i915_restore_display_reg(struct drm_device *dev);
2484
2485 /* i915_sysfs.c */
2486 void i915_setup_sysfs(struct drm_device *dev_priv);
2487 void i915_teardown_sysfs(struct drm_device *dev_priv);
2488
2489 /* intel_i2c.c */
2490 extern int intel_setup_gmbus(struct drm_device *dev);
2491 extern void intel_teardown_gmbus(struct drm_device *dev);
2492 static inline bool intel_gmbus_is_port_valid(unsigned port)
2493 {
2494         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2495 }
2496
2497 extern struct i2c_adapter *intel_gmbus_get_adapter(
2498                 struct drm_i915_private *dev_priv, unsigned port);
2499 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2500 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2501 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2502 {
2503         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2504 }
2505 extern void intel_i2c_reset(struct drm_device *dev);
2506
2507 /* intel_opregion.c */
2508 struct intel_encoder;
2509 #ifdef CONFIG_ACPI
2510 extern int intel_opregion_setup(struct drm_device *dev);
2511 extern void intel_opregion_init(struct drm_device *dev);
2512 extern void intel_opregion_fini(struct drm_device *dev);
2513 extern void intel_opregion_asle_intr(struct drm_device *dev);
2514 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2515                                          bool enable);
2516 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2517                                          pci_power_t state);
2518 #else
2519 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2520 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2521 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2522 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2523 static inline int
2524 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2525 {
2526         return 0;
2527 }
2528 static inline int
2529 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2530 {
2531         return 0;
2532 }
2533 #endif
2534
2535 /* intel_acpi.c */
2536 #ifdef CONFIG_ACPI
2537 extern void intel_register_dsm_handler(void);
2538 extern void intel_unregister_dsm_handler(void);
2539 #else
2540 static inline void intel_register_dsm_handler(void) { return; }
2541 static inline void intel_unregister_dsm_handler(void) { return; }
2542 #endif /* CONFIG_ACPI */
2543
2544 /* modesetting */
2545 extern void intel_modeset_init_hw(struct drm_device *dev);
2546 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2547 extern void intel_modeset_init(struct drm_device *dev);
2548 extern void intel_modeset_gem_init(struct drm_device *dev);
2549 extern void intel_modeset_cleanup(struct drm_device *dev);
2550 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2551 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2552                                          bool force_restore);
2553 extern void i915_redisable_vga(struct drm_device *dev);
2554 extern bool intel_fbc_enabled(struct drm_device *dev);
2555 extern void intel_disable_fbc(struct drm_device *dev);
2556 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2557 extern void intel_init_pch_refclk(struct drm_device *dev);
2558 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2559 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2560 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2561 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2562 extern void intel_detect_pch(struct drm_device *dev);
2563 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2564 extern int intel_enable_rc6(const struct drm_device *dev);
2565
2566 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2567 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2568                         struct drm_file *file);
2569 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2570                                struct drm_file *file);
2571
2572 /* overlay */
2573 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2574 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2575                                             struct intel_overlay_error_state *error);
2576
2577 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2578 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2579                                             struct drm_device *dev,
2580                                             struct intel_display_error_state *error);
2581
2582 /* On SNB platform, before reading ring registers forcewake bit
2583  * must be set to prevent GT core from power down and stale values being
2584  * returned.
2585  */
2586 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2587 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2588
2589 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2590 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2591
2592 /* intel_sideband.c */
2593 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2594 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2595 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2596 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2597 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2598 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2599 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2600 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2601 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2602 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2603 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2604 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2605 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2606 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2607 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2608 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2609                    enum intel_sbi_destination destination);
2610 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2611                      enum intel_sbi_destination destination);
2612 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2613 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2614
2615 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2616 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2617
2618 void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2619 void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2620
2621 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2622         (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2623         ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2624         ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2625         ((reg) >= 0x2E000 && (reg) < 0x30000))
2626
2627 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2628         (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2629         ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2630         ((reg) >= 0x30000 && (reg) < 0x40000))
2631
2632 #define FORCEWAKE_RENDER        (1 << 0)
2633 #define FORCEWAKE_MEDIA         (1 << 1)
2634 #define FORCEWAKE_ALL           (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2635
2636
2637 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2638 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2639
2640 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2641 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2642 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2643 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2644
2645 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2646 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2647 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2648 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2649
2650 #define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2651 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2652
2653 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
2654 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
2655
2656 /* "Broadcast RGB" property */
2657 #define INTEL_BROADCAST_RGB_AUTO 0
2658 #define INTEL_BROADCAST_RGB_FULL 1
2659 #define INTEL_BROADCAST_RGB_LIMITED 2
2660
2661 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2662 {
2663         if (HAS_PCH_SPLIT(dev))
2664                 return CPU_VGACNTRL;
2665         else if (IS_VALLEYVIEW(dev))
2666                 return VLV_VGACNTRL;
2667         else
2668                 return VGACNTRL;
2669 }
2670
2671 static inline void __user *to_user_ptr(u64 address)
2672 {
2673         return (void __user *)(uintptr_t)address;
2674 }
2675
2676 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2677 {
2678         unsigned long j = msecs_to_jiffies(m);
2679
2680         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2681 }
2682
2683 static inline unsigned long
2684 timespec_to_jiffies_timeout(const struct timespec *value)
2685 {
2686         unsigned long j = timespec_to_jiffies(value);
2687
2688         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2689 }
2690
2691 /*
2692  * If you need to wait X milliseconds between events A and B, but event B
2693  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2694  * when event A happened, then just before event B you call this function and
2695  * pass the timestamp as the first argument, and X as the second argument.
2696  */
2697 static inline void
2698 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2699 {
2700         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2701
2702         /*
2703          * Don't re-read the value of "jiffies" every time since it may change
2704          * behind our back and break the math.
2705          */
2706         tmp_jiffies = jiffies;
2707         target_jiffies = timestamp_jiffies +
2708                          msecs_to_jiffies_timeout(to_wait_ms);
2709
2710         if (time_after(target_jiffies, tmp_jiffies)) {
2711                 remaining_jiffies = target_jiffies - tmp_jiffies;
2712                 while (remaining_jiffies)
2713                         remaining_jiffies =
2714                             schedule_timeout_uninterruptible(remaining_jiffies);
2715         }
2716 }
2717
2718 #endif