1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20170907"
84 #define DRIVER_TIMESTAMP 1504772900
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func
, int line
);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t
;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val
)
125 static inline uint_fixed_16_16_t
u32_to_fixed16(uint32_t val
)
127 uint_fixed_16_16_t fp
;
135 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp
)
137 return DIV_ROUND_UP(fp
.val
, 1 << 16);
140 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp
)
145 static inline uint_fixed_16_16_t
min_fixed16(uint_fixed_16_16_t min1
,
146 uint_fixed_16_16_t min2
)
148 uint_fixed_16_16_t min
;
150 min
.val
= min(min1
.val
, min2
.val
);
154 static inline uint_fixed_16_16_t
max_fixed16(uint_fixed_16_16_t max1
,
155 uint_fixed_16_16_t max2
)
157 uint_fixed_16_16_t max
;
159 max
.val
= max(max1
.val
, max2
.val
);
163 static inline uint_fixed_16_16_t
clamp_u64_to_fixed16(uint64_t val
)
165 uint_fixed_16_16_t fp
;
167 fp
.val
= clamp_t(uint32_t, val
, 0, ~0);
171 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val
,
172 uint_fixed_16_16_t d
)
174 return DIV_ROUND_UP(val
.val
, d
.val
);
177 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val
,
178 uint_fixed_16_16_t mul
)
180 uint64_t intermediate_val
;
182 intermediate_val
= (uint64_t) val
* mul
.val
;
183 intermediate_val
= DIV_ROUND_UP_ULL(intermediate_val
, 1 << 16);
184 WARN_ON(intermediate_val
>> 32);
185 return clamp_t(uint32_t, intermediate_val
, 0, ~0);
188 static inline uint_fixed_16_16_t
mul_fixed16(uint_fixed_16_16_t val
,
189 uint_fixed_16_16_t mul
)
191 uint64_t intermediate_val
;
193 intermediate_val
= (uint64_t) val
.val
* mul
.val
;
194 intermediate_val
= intermediate_val
>> 16;
195 return clamp_u64_to_fixed16(intermediate_val
);
198 static inline uint_fixed_16_16_t
div_fixed16(uint32_t val
, uint32_t d
)
202 interm_val
= (uint64_t)val
<< 16;
203 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
);
204 return clamp_u64_to_fixed16(interm_val
);
207 static inline uint32_t div_round_up_u32_fixed16(uint32_t val
,
208 uint_fixed_16_16_t d
)
212 interm_val
= (uint64_t)val
<< 16;
213 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
.val
);
214 WARN_ON(interm_val
>> 32);
215 return clamp_t(uint32_t, interm_val
, 0, ~0);
218 static inline uint_fixed_16_16_t
mul_u32_fixed16(uint32_t val
,
219 uint_fixed_16_16_t mul
)
221 uint64_t intermediate_val
;
223 intermediate_val
= (uint64_t) val
* mul
.val
;
224 return clamp_u64_to_fixed16(intermediate_val
);
227 static inline uint_fixed_16_16_t
add_fixed16(uint_fixed_16_16_t add1
,
228 uint_fixed_16_16_t add2
)
232 interm_sum
= (uint64_t) add1
.val
+ add2
.val
;
233 return clamp_u64_to_fixed16(interm_sum
);
236 static inline uint_fixed_16_16_t
add_fixed16_u32(uint_fixed_16_16_t add1
,
240 uint_fixed_16_16_t interm_add2
= u32_to_fixed16(add2
);
242 interm_sum
= (uint64_t) add1
.val
+ interm_add2
.val
;
243 return clamp_u64_to_fixed16(interm_sum
);
246 static inline const char *yesno(bool v
)
248 return v
? "yes" : "no";
251 static inline const char *onoff(bool v
)
253 return v
? "on" : "off";
256 static inline const char *enableddisabled(bool v
)
258 return v
? "enabled" : "disabled";
267 I915_MAX_PIPES
= _PIPE_EDP
269 #define pipe_name(p) ((p) + 'A')
281 static inline const char *transcoder_name(enum transcoder transcoder
)
283 switch (transcoder
) {
292 case TRANSCODER_DSI_A
:
294 case TRANSCODER_DSI_C
:
301 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
303 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
307 * Global legacy plane identifier. Valid only for primary/sprite
308 * planes on pre-g4x, and only for primary planes on g4x+.
315 #define plane_name(p) ((p) + 'A')
317 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
320 * Per-pipe plane identifier.
321 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
322 * number of planes per CRTC. Not all platforms really have this many planes,
323 * which means some arrays of size I915_MAX_PLANES may have unused entries
324 * between the topmost sprite plane and the cursor plane.
326 * This is expected to be passed to various register macros
327 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
338 #define for_each_plane_id_on_crtc(__crtc, __p) \
339 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
340 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
351 #define port_name(p) ((p) + 'A')
353 #define I915_NUM_PHYS_VLV 2
366 enum intel_display_power_domain
{
370 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
371 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
372 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
373 POWER_DOMAIN_TRANSCODER_A
,
374 POWER_DOMAIN_TRANSCODER_B
,
375 POWER_DOMAIN_TRANSCODER_C
,
376 POWER_DOMAIN_TRANSCODER_EDP
,
377 POWER_DOMAIN_TRANSCODER_DSI_A
,
378 POWER_DOMAIN_TRANSCODER_DSI_C
,
379 POWER_DOMAIN_PORT_DDI_A_LANES
,
380 POWER_DOMAIN_PORT_DDI_B_LANES
,
381 POWER_DOMAIN_PORT_DDI_C_LANES
,
382 POWER_DOMAIN_PORT_DDI_D_LANES
,
383 POWER_DOMAIN_PORT_DDI_E_LANES
,
384 POWER_DOMAIN_PORT_DDI_A_IO
,
385 POWER_DOMAIN_PORT_DDI_B_IO
,
386 POWER_DOMAIN_PORT_DDI_C_IO
,
387 POWER_DOMAIN_PORT_DDI_D_IO
,
388 POWER_DOMAIN_PORT_DDI_E_IO
,
389 POWER_DOMAIN_PORT_DSI
,
390 POWER_DOMAIN_PORT_CRT
,
391 POWER_DOMAIN_PORT_OTHER
,
400 POWER_DOMAIN_MODESET
,
406 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
407 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
408 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
409 #define POWER_DOMAIN_TRANSCODER(tran) \
410 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
411 (tran) + POWER_DOMAIN_TRANSCODER_A)
415 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
427 #define for_each_hpd_pin(__pin) \
428 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
430 #define HPD_STORM_DEFAULT_THRESHOLD 5
432 struct i915_hotplug
{
433 struct work_struct hotplug_work
;
436 unsigned long last_jiffies
;
441 HPD_MARK_DISABLED
= 2
443 } stats
[HPD_NUM_PINS
];
445 struct delayed_work reenable_work
;
447 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
450 struct work_struct dig_port_work
;
452 struct work_struct poll_init_work
;
455 unsigned int hpd_storm_threshold
;
458 * if we get a HPD irq from DP and a HPD irq from non-DP
459 * the non-DP HPD could block the workqueue on a mode config
460 * mutex getting, that userspace may have taken. However
461 * userspace is waiting on the DP workqueue to run which is
462 * blocked behind the non-DP one.
464 struct workqueue_struct
*dp_wq
;
467 #define I915_GEM_GPU_DOMAINS \
468 (I915_GEM_DOMAIN_RENDER | \
469 I915_GEM_DOMAIN_SAMPLER | \
470 I915_GEM_DOMAIN_COMMAND | \
471 I915_GEM_DOMAIN_INSTRUCTION | \
472 I915_GEM_DOMAIN_VERTEX)
474 #define for_each_pipe(__dev_priv, __p) \
475 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
476 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
477 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
478 for_each_if ((__mask) & (1 << (__p)))
479 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
481 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
483 #define for_each_sprite(__dev_priv, __p, __s) \
485 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
488 #define for_each_port_masked(__port, __ports_mask) \
489 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
490 for_each_if ((__ports_mask) & (1 << (__port)))
492 #define for_each_crtc(dev, crtc) \
493 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
495 #define for_each_intel_plane(dev, intel_plane) \
496 list_for_each_entry(intel_plane, \
497 &(dev)->mode_config.plane_list, \
500 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
501 list_for_each_entry(intel_plane, \
502 &(dev)->mode_config.plane_list, \
504 for_each_if ((plane_mask) & \
505 (1 << drm_plane_index(&intel_plane->base)))
507 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
508 list_for_each_entry(intel_plane, \
509 &(dev)->mode_config.plane_list, \
511 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
513 #define for_each_intel_crtc(dev, intel_crtc) \
514 list_for_each_entry(intel_crtc, \
515 &(dev)->mode_config.crtc_list, \
518 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
519 list_for_each_entry(intel_crtc, \
520 &(dev)->mode_config.crtc_list, \
522 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
524 #define for_each_intel_encoder(dev, intel_encoder) \
525 list_for_each_entry(intel_encoder, \
526 &(dev)->mode_config.encoder_list, \
529 #define for_each_intel_connector_iter(intel_connector, iter) \
530 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
532 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
533 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
534 for_each_if ((intel_encoder)->base.crtc == (__crtc))
536 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
537 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
538 for_each_if ((intel_connector)->base.encoder == (__encoder))
540 #define for_each_power_domain(domain, mask) \
541 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
542 for_each_if (BIT_ULL(domain) & (mask))
544 #define for_each_power_well(__dev_priv, __power_well) \
545 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
546 (__power_well) - (__dev_priv)->power_domains.power_wells < \
547 (__dev_priv)->power_domains.power_well_count; \
550 #define for_each_power_well_rev(__dev_priv, __power_well) \
551 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
552 (__dev_priv)->power_domains.power_well_count - 1; \
553 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
556 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
557 for_each_power_well(__dev_priv, __power_well) \
558 for_each_if ((__power_well)->domains & (__domain_mask))
560 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
561 for_each_power_well_rev(__dev_priv, __power_well) \
562 for_each_if ((__power_well)->domains & (__domain_mask))
564 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
566 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
567 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
568 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
570 for_each_if (plane_state)
572 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
574 (__i) < (__state)->base.dev->mode_config.num_crtc && \
575 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
576 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
581 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
583 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
584 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
585 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
586 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
590 struct drm_i915_private
;
591 struct i915_mm_struct
;
592 struct i915_mmu_object
;
594 struct drm_i915_file_private
{
595 struct drm_i915_private
*dev_priv
;
596 struct drm_file
*file
;
600 struct list_head request_list
;
601 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
602 * chosen to prevent the CPU getting more than a frame ahead of the GPU
603 * (when using lax throttling for the frontbuffer). We also use it to
604 * offer free GPU waitboosts for severely congested workloads.
606 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
608 struct idr context_idr
;
610 struct intel_rps_client
{
614 unsigned int bsd_engine
;
616 /* Client can have a maximum of 3 contexts banned before
617 * it is denied of creating new contexts. As one context
618 * ban needs 4 consecutive hangs, and more if there is
619 * progress in between, this is a last resort stop gap measure
620 * to limit the badly behaving clients access to gpu.
622 #define I915_MAX_CLIENT_CONTEXT_BANS 3
623 atomic_t context_bans
;
626 /* Used by dp and fdi links */
627 struct intel_link_m_n
{
635 void intel_link_compute_m_n(int bpp
, int nlanes
,
636 int pixel_clock
, int link_clock
,
637 struct intel_link_m_n
*m_n
,
640 /* Interface history:
643 * 1.2: Add Power Management
644 * 1.3: Add vblank support
645 * 1.4: Fix cmdbuffer path, add heap destroy
646 * 1.5: Add vblank pipe configuration
647 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
648 * - Support vertical blank on secondary display pipe
650 #define DRIVER_MAJOR 1
651 #define DRIVER_MINOR 6
652 #define DRIVER_PATCHLEVEL 0
654 struct opregion_header
;
655 struct opregion_acpi
;
656 struct opregion_swsci
;
657 struct opregion_asle
;
659 struct intel_opregion
{
660 struct opregion_header
*header
;
661 struct opregion_acpi
*acpi
;
662 struct opregion_swsci
*swsci
;
663 u32 swsci_gbda_sub_functions
;
664 u32 swsci_sbcb_sub_functions
;
665 struct opregion_asle
*asle
;
671 struct work_struct asle_work
;
673 #define OPREGION_SIZE (8*1024)
675 struct intel_overlay
;
676 struct intel_overlay_error_state
;
678 struct sdvo_device_mapping
{
687 struct intel_connector
;
688 struct intel_encoder
;
689 struct intel_atomic_state
;
690 struct intel_crtc_state
;
691 struct intel_initial_plane_config
;
695 struct intel_cdclk_state
;
697 struct drm_i915_display_funcs
{
698 void (*get_cdclk
)(struct drm_i915_private
*dev_priv
,
699 struct intel_cdclk_state
*cdclk_state
);
700 void (*set_cdclk
)(struct drm_i915_private
*dev_priv
,
701 const struct intel_cdclk_state
*cdclk_state
);
702 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
703 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
704 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
705 struct intel_crtc
*intel_crtc
,
706 struct intel_crtc_state
*newstate
);
707 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
708 struct intel_crtc_state
*cstate
);
709 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
710 struct intel_crtc_state
*cstate
);
711 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
712 struct intel_crtc_state
*cstate
);
713 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
714 void (*update_wm
)(struct intel_crtc
*crtc
);
715 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
716 /* Returns the active state of the crtc, and if the crtc is active,
717 * fills out the pipe-config with the hw state. */
718 bool (*get_pipe_config
)(struct intel_crtc
*,
719 struct intel_crtc_state
*);
720 void (*get_initial_plane_config
)(struct intel_crtc
*,
721 struct intel_initial_plane_config
*);
722 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
723 struct intel_crtc_state
*crtc_state
);
724 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
725 struct drm_atomic_state
*old_state
);
726 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
727 struct drm_atomic_state
*old_state
);
728 void (*update_crtcs
)(struct drm_atomic_state
*state
);
729 void (*audio_codec_enable
)(struct drm_connector
*connector
,
730 struct intel_encoder
*encoder
,
731 const struct drm_display_mode
*adjusted_mode
);
732 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
733 void (*fdi_link_train
)(struct intel_crtc
*crtc
,
734 const struct intel_crtc_state
*crtc_state
);
735 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
736 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
737 /* clock updates for mode set */
739 /* render clock increase/decrease */
740 /* display clock increase/decrease */
741 /* pll clock increase/decrease */
743 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
744 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
747 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
748 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
749 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
752 struct work_struct work
;
754 uint32_t *dmc_payload
;
755 uint32_t dmc_fw_size
;
758 i915_reg_t mmioaddr
[8];
759 uint32_t mmiodata
[8];
761 uint32_t allowed_dc_mask
;
764 #define DEV_INFO_FOR_EACH_FLAG(func) \
767 func(is_alpha_support); \
768 /* Keep has_* in alphabetical order */ \
769 func(has_64bit_reloc); \
770 func(has_aliasing_ppgtt); \
774 func(has_reset_engine); \
776 func(has_fpga_dbg); \
777 func(has_full_ppgtt); \
778 func(has_full_48bit_ppgtt); \
779 func(has_gmbus_irq); \
780 func(has_gmch_display); \
786 func(has_logical_ring_contexts); \
788 func(has_pipe_cxsr); \
789 func(has_pooled_eu); \
793 func(has_resource_streamer); \
794 func(has_runtime_pm); \
796 func(unfenced_needs_alignment); \
797 func(cursor_needs_physical); \
798 func(hws_needs_physical); \
799 func(overlay_needs_physical); \
802 struct sseu_dev_info
{
808 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
811 u8 has_subslice_pg
:1;
815 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
817 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
820 /* Keep in gen based order, and chronological order within a gen */
821 enum intel_platform
{
822 INTEL_PLATFORM_UNINITIALIZED
= 0,
853 struct intel_device_info
{
854 u32 display_mmio_offset
;
857 u8 num_sprites
[I915_MAX_PIPES
];
858 u8 num_scalers
[I915_MAX_PIPES
];
861 enum intel_platform platform
;
862 u8 gt
; /* GT number, 0 if undefined */
863 u8 ring_mask
; /* Rings supported by the HW */
865 #define DEFINE_FLAG(name) u8 name:1
866 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
868 u16 ddb_size
; /* in blocks */
869 /* Register offsets for the various display pipes and transcoders */
870 int pipe_offsets
[I915_MAX_TRANSCODERS
];
871 int trans_offsets
[I915_MAX_TRANSCODERS
];
872 int palette_offsets
[I915_MAX_PIPES
];
873 int cursor_offsets
[I915_MAX_PIPES
];
875 /* Slice/subslice/EU info */
876 struct sseu_dev_info sseu
;
879 u16 degamma_lut_size
;
884 struct intel_display_error_state
;
886 struct i915_gpu_state
{
889 struct timeval boottime
;
890 struct timeval uptime
;
892 struct drm_i915_private
*i915
;
902 struct intel_device_info device_info
;
903 struct i915_params params
;
905 /* Generic register state */
909 u32 gtier
[4], ngtier
;
913 u32 error
; /* gen6+ */
914 u32 err_int
; /* gen7 */
915 u32 fault_data0
; /* gen8, gen9 */
916 u32 fault_data1
; /* gen8, gen9 */
924 u64 fence
[I915_MAX_NUM_FENCES
];
925 struct intel_overlay_error_state
*overlay
;
926 struct intel_display_error_state
*display
;
927 struct drm_i915_error_object
*semaphore
;
928 struct drm_i915_error_object
*guc_log
;
930 struct drm_i915_error_engine
{
932 /* Software tracked state */
935 unsigned long hangcheck_timestamp
;
936 bool hangcheck_stalled
;
937 enum intel_engine_hangcheck_action hangcheck_action
;
938 struct i915_address_space
*vm
;
942 /* position of active request inside the ring */
943 u32 rq_head
, rq_post
, rq_tail
;
945 /* our own tracking of ring head and tail */
968 u32 rc_psmi
; /* sleep state */
969 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
970 struct intel_instdone instdone
;
972 struct drm_i915_error_context
{
973 char comm
[TASK_COMM_LEN
];
982 struct drm_i915_error_object
{
988 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
990 struct drm_i915_error_object
**user_bo
;
993 struct drm_i915_error_object
*wa_ctx
;
995 struct drm_i915_error_request
{
1003 } *requests
, execlist
[2];
1005 struct drm_i915_error_waiter
{
1006 char comm
[TASK_COMM_LEN
];
1018 } engine
[I915_NUM_ENGINES
];
1020 struct drm_i915_error_buffer
{
1023 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
1027 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1034 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
1035 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
1036 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
1039 enum i915_cache_level
{
1040 I915_CACHE_NONE
= 0,
1041 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
1042 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
1043 caches, eg sampler/render caches, and the
1044 large Last-Level-Cache. LLC is coherent with
1045 the CPU, but L3 is only visible to the GPU. */
1046 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
1049 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1060 /* This is always the inner lock when overlapping with struct_mutex and
1061 * it's the outer lock when overlapping with stolen_lock. */
1064 unsigned int possible_framebuffer_bits
;
1065 unsigned int busy_bits
;
1066 unsigned int visible_pipes_mask
;
1067 struct intel_crtc
*crtc
;
1069 struct drm_mm_node compressed_fb
;
1070 struct drm_mm_node
*compressed_llb
;
1077 bool underrun_detected
;
1078 struct work_struct underrun_work
;
1081 * Due to the atomic rules we can't access some structures without the
1082 * appropriate locking, so we cache information here in order to avoid
1085 struct intel_fbc_state_cache
{
1086 struct i915_vma
*vma
;
1089 unsigned int mode_flags
;
1090 uint32_t hsw_bdw_pixel_rate
;
1094 unsigned int rotation
;
1101 const struct drm_format_info
*format
;
1102 unsigned int stride
;
1107 * This structure contains everything that's relevant to program the
1108 * hardware registers. When we want to figure out if we need to disable
1109 * and re-enable FBC for a new configuration we just check if there's
1110 * something different in the struct. The genx_fbc_activate functions
1111 * are supposed to read from it in order to program the registers.
1113 struct intel_fbc_reg_params
{
1114 struct i915_vma
*vma
;
1119 unsigned int fence_y_offset
;
1123 const struct drm_format_info
*format
;
1124 unsigned int stride
;
1128 unsigned int gen9_wa_cfb_stride
;
1131 struct intel_fbc_work
{
1133 u32 scheduled_vblank
;
1134 struct work_struct work
;
1137 const char *no_fbc_reason
;
1141 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1142 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1143 * parsing for same resolution.
1145 enum drrs_refresh_rate_type
{
1148 DRRS_MAX_RR
, /* RR count */
1151 enum drrs_support_type
{
1152 DRRS_NOT_SUPPORTED
= 0,
1153 STATIC_DRRS_SUPPORT
= 1,
1154 SEAMLESS_DRRS_SUPPORT
= 2
1160 struct delayed_work work
;
1161 struct intel_dp
*dp
;
1162 unsigned busy_frontbuffer_bits
;
1163 enum drrs_refresh_rate_type refresh_rate_type
;
1164 enum drrs_support_type type
;
1171 struct intel_dp
*enabled
;
1173 struct delayed_work work
;
1174 unsigned busy_frontbuffer_bits
;
1176 bool aux_frame_sync
;
1178 bool y_cord_support
;
1179 bool colorimetry_support
;
1184 PCH_NONE
= 0, /* No PCH present */
1185 PCH_IBX
, /* Ibexpeak PCH */
1186 PCH_CPT
, /* Cougarpoint/Pantherpoint PCH */
1187 PCH_LPT
, /* Lynxpoint/Wildcatpoint PCH */
1188 PCH_SPT
, /* Sunrisepoint PCH */
1189 PCH_KBP
, /* Kaby Lake PCH */
1190 PCH_CNP
, /* Cannon Lake PCH */
1194 enum intel_sbi_destination
{
1199 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1200 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1201 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1202 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1203 #define QUIRK_INCREASE_T12_DELAY (1<<6)
1206 struct intel_fbc_work
;
1208 struct intel_gmbus
{
1209 struct i2c_adapter adapter
;
1210 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1213 i915_reg_t gpio_reg
;
1214 struct i2c_algo_bit_data bit_algo
;
1215 struct drm_i915_private
*dev_priv
;
1218 struct i915_suspend_saved_registers
{
1220 u32 saveFBC_CONTROL
;
1221 u32 saveCACHE_MODE_0
;
1222 u32 saveMI_ARB_STATE
;
1226 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1227 u32 savePCH_PORT_HOTPLUG
;
1231 struct vlv_s0ix_state
{
1238 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1239 u32 media_max_req_count
;
1240 u32 gfx_max_req_count
;
1266 u32 rp_down_timeout
;
1272 /* Display 1 CZ domain */
1277 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1279 /* GT SA CZ domain */
1286 /* Display 2 CZ domain */
1290 u32 clock_gate_dis2
;
1293 struct intel_rps_ei
{
1299 struct intel_gen6_power_mgmt
{
1301 * work, interrupts_enabled and pm_iir are protected by
1302 * dev_priv->irq_lock
1304 struct work_struct work
;
1305 bool interrupts_enabled
;
1308 /* PM interrupt bits that should never be masked */
1311 /* Frequencies are stored in potentially platform dependent multiples.
1312 * In other words, *_freq needs to be multiplied by X to be interesting.
1313 * Soft limits are those which are used for the dynamic reclocking done
1314 * by the driver (raise frequencies under heavy loads, and lower for
1315 * lighter loads). Hard limits are those imposed by the hardware.
1317 * A distinction is made for overclocking, which is never enabled by
1318 * default, and is considered to be above the hard limit if it's
1321 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1322 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1323 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1324 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1325 u8 min_freq
; /* AKA RPn. Minimum frequency */
1326 u8 boost_freq
; /* Frequency to request when wait boosting */
1327 u8 idle_freq
; /* Frequency to request when we are idle */
1328 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1329 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1330 u8 rp0_freq
; /* Non-overclocked max frequency. */
1331 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1333 u8 up_threshold
; /* Current %busy required to uplock */
1334 u8 down_threshold
; /* Current %busy required to downclock */
1337 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1340 struct delayed_work autoenable_work
;
1341 atomic_t num_waiters
;
1344 /* manual wa residency calculations */
1345 struct intel_rps_ei ei
;
1348 * Protects RPS/RC6 register access and PCU communication.
1349 * Must be taken after struct_mutex if nested. Note that
1350 * this lock may be held for long periods of time when
1351 * talking to hw - so only take it when talking to hw!
1353 struct mutex hw_lock
;
1356 /* defined intel_pm.c */
1357 extern spinlock_t mchdev_lock
;
1359 struct intel_ilk_power_mgmt
{
1367 unsigned long last_time1
;
1368 unsigned long chipset_power
;
1371 unsigned long gfx_power
;
1378 struct drm_i915_private
;
1379 struct i915_power_well
;
1381 struct i915_power_well_ops
{
1383 * Synchronize the well's hw state to match the current sw state, for
1384 * example enable/disable it based on the current refcount. Called
1385 * during driver init and resume time, possibly after first calling
1386 * the enable/disable handlers.
1388 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1389 struct i915_power_well
*power_well
);
1391 * Enable the well and resources that depend on it (for example
1392 * interrupts located on the well). Called after the 0->1 refcount
1395 void (*enable
)(struct drm_i915_private
*dev_priv
,
1396 struct i915_power_well
*power_well
);
1398 * Disable the well and resources that depend on it. Called after
1399 * the 1->0 refcount transition.
1401 void (*disable
)(struct drm_i915_private
*dev_priv
,
1402 struct i915_power_well
*power_well
);
1403 /* Returns the hw enabled state. */
1404 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1405 struct i915_power_well
*power_well
);
1408 /* Power well structure for haswell */
1409 struct i915_power_well
{
1412 /* power well enable/disable usage count */
1414 /* cached hw enabled state */
1417 /* unique identifier for this power well */
1418 enum i915_power_well_id id
;
1420 * Arbitraty data associated with this power well. Platform and power
1428 /* Mask of pipes whose IRQ logic is backed by the pw */
1430 /* The pw is backing the VGA functionality */
1435 const struct i915_power_well_ops
*ops
;
1438 struct i915_power_domains
{
1440 * Power wells needed for initialization at driver init and suspend
1441 * time are on. They are kept on until after the first modeset.
1445 int power_well_count
;
1448 int domain_use_count
[POWER_DOMAIN_NUM
];
1449 struct i915_power_well
*power_wells
;
1452 #define MAX_L3_SLICES 2
1453 struct intel_l3_parity
{
1454 u32
*remap_info
[MAX_L3_SLICES
];
1455 struct work_struct error_work
;
1459 struct i915_gem_mm
{
1460 /** Memory allocator for GTT stolen memory */
1461 struct drm_mm stolen
;
1462 /** Protects the usage of the GTT stolen memory allocator. This is
1463 * always the inner lock when overlapping with struct_mutex. */
1464 struct mutex stolen_lock
;
1466 /** List of all objects in gtt_space. Used to restore gtt
1467 * mappings on resume */
1468 struct list_head bound_list
;
1470 * List of objects which are not bound to the GTT (thus
1471 * are idle and not used by the GPU). These objects may or may
1472 * not actually have any pages attached.
1474 struct list_head unbound_list
;
1476 /** List of all objects in gtt_space, currently mmaped by userspace.
1477 * All objects within this list must also be on bound_list.
1479 struct list_head userfault_list
;
1482 * List of objects which are pending destruction.
1484 struct llist_head free_list
;
1485 struct work_struct free_work
;
1488 * Small stash of WC pages
1490 struct pagevec wc_stash
;
1492 /** Usable portion of the GTT for GEM */
1493 dma_addr_t stolen_base
; /* limited to low memory (32-bit) */
1495 /** PPGTT used for aliasing the PPGTT with the GTT */
1496 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1498 struct notifier_block oom_notifier
;
1499 struct notifier_block vmap_notifier
;
1500 struct shrinker shrinker
;
1502 /** LRU list of objects with fence regs on them. */
1503 struct list_head fence_list
;
1506 * Workqueue to fault in userptr pages, flushed by the execbuf
1507 * when required but otherwise left to userspace to try again
1510 struct workqueue_struct
*userptr_wq
;
1512 u64 unordered_timeline
;
1514 /* the indicator for dispatch video commands on two BSD rings */
1515 atomic_t bsd_engine_dispatch_index
;
1517 /** Bit 6 swizzling required for X tiling */
1518 uint32_t bit_6_swizzle_x
;
1519 /** Bit 6 swizzling required for Y tiling */
1520 uint32_t bit_6_swizzle_y
;
1522 /* accounting, useful for userland debugging */
1523 spinlock_t object_stat_lock
;
1528 struct drm_i915_error_state_buf
{
1529 struct drm_i915_private
*i915
;
1538 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1539 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1541 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1542 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1544 struct i915_gpu_error
{
1545 /* For hangcheck timer */
1546 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1547 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1549 struct delayed_work hangcheck_work
;
1551 /* For reset and error_state handling. */
1553 /* Protected by the above dev->gpu_error.lock. */
1554 struct i915_gpu_state
*first_error
;
1556 atomic_t pending_fb_pin
;
1558 unsigned long missed_irq_rings
;
1561 * State variable controlling the reset flow and count
1563 * This is a counter which gets incremented when reset is triggered,
1565 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1566 * meaning that any waiters holding onto the struct_mutex should
1567 * relinquish the lock immediately in order for the reset to start.
1569 * If reset is not completed succesfully, the I915_WEDGE bit is
1570 * set meaning that hardware is terminally sour and there is no
1571 * recovery. All waiters on the reset_queue will be woken when
1574 * This counter is used by the wait_seqno code to notice that reset
1575 * event happened and it needs to restart the entire ioctl (since most
1576 * likely the seqno it waited for won't ever signal anytime soon).
1578 * This is important for lock-free wait paths, where no contended lock
1579 * naturally enforces the correct ordering between the bail-out of the
1580 * waiter and the gpu reset work code.
1582 unsigned long reset_count
;
1585 * flags: Control various stages of the GPU reset
1587 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1588 * other users acquiring the struct_mutex. To do this we set the
1589 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1590 * and then check for that bit before acquiring the struct_mutex (in
1591 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1592 * secondary role in preventing two concurrent global reset attempts.
1594 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1595 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1596 * but it may be held by some long running waiter (that we cannot
1597 * interrupt without causing trouble). Once we are ready to do the GPU
1598 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1599 * they already hold the struct_mutex and want to participate they can
1600 * inspect the bit and do the reset directly, otherwise the worker
1601 * waits for the struct_mutex.
1603 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1604 * acquire the struct_mutex to reset an engine, we need an explicit
1605 * flag to prevent two concurrent reset attempts in the same engine.
1606 * As the number of engines continues to grow, allocate the flags from
1607 * the most significant bits.
1609 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1610 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1611 * i915_gem_request_alloc(), this bit is checked and the sequence
1612 * aborted (with -EIO reported to userspace) if set.
1614 unsigned long flags
;
1615 #define I915_RESET_BACKOFF 0
1616 #define I915_RESET_HANDOFF 1
1617 #define I915_RESET_MODESET 2
1618 #define I915_WEDGED (BITS_PER_LONG - 1)
1619 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1621 /** Number of times an engine has been reset */
1622 u32 reset_engine_count
[I915_NUM_ENGINES
];
1625 * Waitqueue to signal when a hang is detected. Used to for waiters
1626 * to release the struct_mutex for the reset to procede.
1628 wait_queue_head_t wait_queue
;
1631 * Waitqueue to signal when the reset has completed. Used by clients
1632 * that wait for dev_priv->mm.wedged to settle.
1634 wait_queue_head_t reset_queue
;
1636 /* For missed irq/seqno simulation. */
1637 unsigned long test_irq_rings
;
1640 enum modeset_restore
{
1641 MODESET_ON_LID_OPEN
,
1646 #define DP_AUX_A 0x40
1647 #define DP_AUX_B 0x10
1648 #define DP_AUX_C 0x20
1649 #define DP_AUX_D 0x30
1651 #define DDC_PIN_B 0x05
1652 #define DDC_PIN_C 0x04
1653 #define DDC_PIN_D 0x06
1655 struct ddi_vbt_port_info
{
1657 * This is an index in the HDMI/DVI DDI buffer translation table.
1658 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1659 * populate this field.
1661 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1662 uint8_t hdmi_level_shift
;
1664 uint8_t supports_dvi
:1;
1665 uint8_t supports_hdmi
:1;
1666 uint8_t supports_dp
:1;
1667 uint8_t supports_edp
:1;
1669 uint8_t alternate_aux_channel
;
1670 uint8_t alternate_ddc_pin
;
1672 uint8_t dp_boost_level
;
1673 uint8_t hdmi_boost_level
;
1676 enum psr_lines_to_wait
{
1677 PSR_0_LINES_TO_WAIT
= 0,
1679 PSR_4_LINES_TO_WAIT
,
1683 struct intel_vbt_data
{
1684 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1685 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1688 unsigned int int_tv_support
:1;
1689 unsigned int lvds_dither
:1;
1690 unsigned int lvds_vbt
:1;
1691 unsigned int int_crt_support
:1;
1692 unsigned int lvds_use_ssc
:1;
1693 unsigned int display_clock_mode
:1;
1694 unsigned int fdi_rx_polarity_inverted
:1;
1695 unsigned int panel_type
:4;
1697 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1699 enum drrs_support_type drrs_type
;
1710 struct edp_power_seq pps
;
1715 bool require_aux_wakeup
;
1717 enum psr_lines_to_wait lines_to_wait
;
1718 int tp1_wakeup_time
;
1719 int tp2_tp3_wakeup_time
;
1725 bool active_low_pwm
;
1726 u8 min_brightness
; /* min_brightness/255 of max */
1727 u8 controller
; /* brightness controller number */
1728 enum intel_backlight_type type
;
1734 struct mipi_config
*config
;
1735 struct mipi_pps_data
*pps
;
1739 const u8
*sequence
[MIPI_SEQ_MAX
];
1745 struct child_device_config
*child_dev
;
1747 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1748 struct sdvo_device_mapping sdvo_mappings
[2];
1751 enum intel_ddb_partitioning
{
1753 INTEL_DDB_PART_5_6
, /* IVB+ */
1756 struct intel_wm_level
{
1764 struct ilk_wm_values
{
1765 uint32_t wm_pipe
[3];
1767 uint32_t wm_lp_spr
[3];
1768 uint32_t wm_linetime
[3];
1770 enum intel_ddb_partitioning partitioning
;
1773 struct g4x_pipe_wm
{
1774 uint16_t plane
[I915_MAX_PLANES
];
1784 struct vlv_wm_ddl_values
{
1785 uint8_t plane
[I915_MAX_PLANES
];
1788 struct vlv_wm_values
{
1789 struct g4x_pipe_wm pipe
[3];
1790 struct g4x_sr_wm sr
;
1791 struct vlv_wm_ddl_values ddl
[3];
1796 struct g4x_wm_values
{
1797 struct g4x_pipe_wm pipe
[2];
1798 struct g4x_sr_wm sr
;
1799 struct g4x_sr_wm hpll
;
1805 struct skl_ddb_entry
{
1806 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1809 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1811 return entry
->end
- entry
->start
;
1814 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1815 const struct skl_ddb_entry
*e2
)
1817 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1823 struct skl_ddb_allocation
{
1824 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1825 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1828 struct skl_wm_values
{
1829 unsigned dirty_pipes
;
1830 struct skl_ddb_allocation ddb
;
1833 struct skl_wm_level
{
1835 uint16_t plane_res_b
;
1836 uint8_t plane_res_l
;
1840 * This struct helps tracking the state needed for runtime PM, which puts the
1841 * device in PCI D3 state. Notice that when this happens, nothing on the
1842 * graphics device works, even register access, so we don't get interrupts nor
1845 * Every piece of our code that needs to actually touch the hardware needs to
1846 * either call intel_runtime_pm_get or call intel_display_power_get with the
1847 * appropriate power domain.
1849 * Our driver uses the autosuspend delay feature, which means we'll only really
1850 * suspend if we stay with zero refcount for a certain amount of time. The
1851 * default value is currently very conservative (see intel_runtime_pm_enable), but
1852 * it can be changed with the standard runtime PM files from sysfs.
1854 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1855 * goes back to false exactly before we reenable the IRQs. We use this variable
1856 * to check if someone is trying to enable/disable IRQs while they're supposed
1857 * to be disabled. This shouldn't happen and we'll print some error messages in
1860 * For more, read the Documentation/power/runtime_pm.txt.
1862 struct i915_runtime_pm
{
1863 atomic_t wakeref_count
;
1868 enum intel_pipe_crc_source
{
1869 INTEL_PIPE_CRC_SOURCE_NONE
,
1870 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1871 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1872 INTEL_PIPE_CRC_SOURCE_PF
,
1873 INTEL_PIPE_CRC_SOURCE_PIPE
,
1874 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1875 INTEL_PIPE_CRC_SOURCE_TV
,
1876 INTEL_PIPE_CRC_SOURCE_DP_B
,
1877 INTEL_PIPE_CRC_SOURCE_DP_C
,
1878 INTEL_PIPE_CRC_SOURCE_DP_D
,
1879 INTEL_PIPE_CRC_SOURCE_AUTO
,
1880 INTEL_PIPE_CRC_SOURCE_MAX
,
1883 struct intel_pipe_crc_entry
{
1888 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1889 struct intel_pipe_crc
{
1891 bool opened
; /* exclusive access to the result file */
1892 struct intel_pipe_crc_entry
*entries
;
1893 enum intel_pipe_crc_source source
;
1895 wait_queue_head_t wq
;
1899 struct i915_frontbuffer_tracking
{
1903 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1910 struct i915_wa_reg
{
1913 /* bitmask representing WA bits */
1918 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1919 * allowing it for RCS as we don't foresee any requirement of having
1920 * a whitelist for other engines. When it is really required for
1921 * other engines then the limit need to be increased.
1923 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1925 struct i915_workarounds
{
1926 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1928 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1931 struct i915_virtual_gpu
{
1936 /* used in computing the new watermarks state */
1937 struct intel_wm_config
{
1938 unsigned int num_pipes_active
;
1939 bool sprites_enabled
;
1940 bool sprites_scaled
;
1943 struct i915_oa_format
{
1948 struct i915_oa_reg
{
1953 struct i915_oa_config
{
1954 char uuid
[UUID_STRING_LEN
+ 1];
1957 const struct i915_oa_reg
*mux_regs
;
1959 const struct i915_oa_reg
*b_counter_regs
;
1960 u32 b_counter_regs_len
;
1961 const struct i915_oa_reg
*flex_regs
;
1964 struct attribute_group sysfs_metric
;
1965 struct attribute
*attrs
[2];
1966 struct device_attribute sysfs_metric_id
;
1971 struct i915_perf_stream
;
1974 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1976 struct i915_perf_stream_ops
{
1978 * @enable: Enables the collection of HW samples, either in response to
1979 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1980 * without `I915_PERF_FLAG_DISABLED`.
1982 void (*enable
)(struct i915_perf_stream
*stream
);
1985 * @disable: Disables the collection of HW samples, either in response
1986 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1989 void (*disable
)(struct i915_perf_stream
*stream
);
1992 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1993 * once there is something ready to read() for the stream
1995 void (*poll_wait
)(struct i915_perf_stream
*stream
,
2000 * @wait_unlocked: For handling a blocking read, wait until there is
2001 * something to ready to read() for the stream. E.g. wait on the same
2002 * wait queue that would be passed to poll_wait().
2004 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
2007 * @read: Copy buffered metrics as records to userspace
2008 * **buf**: the userspace, destination buffer
2009 * **count**: the number of bytes to copy, requested by userspace
2010 * **offset**: zero at the start of the read, updated as the read
2011 * proceeds, it represents how many bytes have been copied so far and
2012 * the buffer offset for copying the next record.
2014 * Copy as many buffered i915 perf samples and records for this stream
2015 * to userspace as will fit in the given buffer.
2017 * Only write complete records; returning -%ENOSPC if there isn't room
2018 * for a complete record.
2020 * Return any error condition that results in a short read such as
2021 * -%ENOSPC or -%EFAULT, even though these may be squashed before
2022 * returning to userspace.
2024 int (*read
)(struct i915_perf_stream
*stream
,
2030 * @destroy: Cleanup any stream specific resources.
2032 * The stream will always be disabled before this is called.
2034 void (*destroy
)(struct i915_perf_stream
*stream
);
2038 * struct i915_perf_stream - state for a single open stream FD
2040 struct i915_perf_stream
{
2042 * @dev_priv: i915 drm device
2044 struct drm_i915_private
*dev_priv
;
2047 * @link: Links the stream into ``&drm_i915_private->streams``
2049 struct list_head link
;
2052 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2053 * properties given when opening a stream, representing the contents
2054 * of a single sample as read() by userspace.
2059 * @sample_size: Considering the configured contents of a sample
2060 * combined with the required header size, this is the total size
2061 * of a single sample record.
2066 * @ctx: %NULL if measuring system-wide across all contexts or a
2067 * specific context that is being monitored.
2069 struct i915_gem_context
*ctx
;
2072 * @enabled: Whether the stream is currently enabled, considering
2073 * whether the stream was opened in a disabled state and based
2074 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2079 * @ops: The callbacks providing the implementation of this specific
2080 * type of configured stream.
2082 const struct i915_perf_stream_ops
*ops
;
2085 * @oa_config: The OA configuration used by the stream.
2087 struct i915_oa_config
*oa_config
;
2091 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2093 struct i915_oa_ops
{
2095 * @is_valid_b_counter_reg: Validates register's address for
2096 * programming boolean counters for a particular platform.
2098 bool (*is_valid_b_counter_reg
)(struct drm_i915_private
*dev_priv
,
2102 * @is_valid_mux_reg: Validates register's address for programming mux
2103 * for a particular platform.
2105 bool (*is_valid_mux_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
2108 * @is_valid_flex_reg: Validates register's address for programming
2109 * flex EU filtering for a particular platform.
2111 bool (*is_valid_flex_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
2114 * @init_oa_buffer: Resets the head and tail pointers of the
2115 * circular buffer for periodic OA reports.
2117 * Called when first opening a stream for OA metrics, but also may be
2118 * called in response to an OA buffer overflow or other error
2121 * Note it may be necessary to clear the full OA buffer here as part of
2122 * maintaining the invariable that new reports must be written to
2123 * zeroed memory for us to be able to reliable detect if an expected
2124 * report has not yet landed in memory. (At least on Haswell the OA
2125 * buffer tail pointer is not synchronized with reports being visible
2128 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
2131 * @enable_metric_set: Selects and applies any MUX configuration to set
2132 * up the Boolean and Custom (B/C) counters that are part of the
2133 * counter reports being sampled. May apply system constraints such as
2134 * disabling EU clock gating as required.
2136 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
,
2137 const struct i915_oa_config
*oa_config
);
2140 * @disable_metric_set: Remove system constraints associated with using
2143 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
2146 * @oa_enable: Enable periodic sampling
2148 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
2151 * @oa_disable: Disable periodic sampling
2153 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
2156 * @read: Copy data from the circular OA buffer into a given userspace
2159 int (*read
)(struct i915_perf_stream
*stream
,
2165 * @oa_hw_tail_read: read the OA tail pointer register
2167 * In particular this enables us to share all the fiddly code for
2168 * handling the OA unit tail pointer race that affects multiple
2171 u32 (*oa_hw_tail_read
)(struct drm_i915_private
*dev_priv
);
2174 struct intel_cdclk_state
{
2175 unsigned int cdclk
, vco
, ref
;
2178 struct drm_i915_private
{
2179 struct drm_device drm
;
2181 struct kmem_cache
*objects
;
2182 struct kmem_cache
*vmas
;
2183 struct kmem_cache
*luts
;
2184 struct kmem_cache
*requests
;
2185 struct kmem_cache
*dependencies
;
2186 struct kmem_cache
*priorities
;
2188 const struct intel_device_info info
;
2192 struct intel_uncore uncore
;
2194 struct i915_virtual_gpu vgpu
;
2196 struct intel_gvt
*gvt
;
2198 struct intel_huc huc
;
2199 struct intel_guc guc
;
2201 struct intel_csr csr
;
2203 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
2205 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2206 * controller on different i2c buses. */
2207 struct mutex gmbus_mutex
;
2210 * Base address of the gmbus and gpio block.
2212 uint32_t gpio_mmio_base
;
2214 /* MMIO base address for MIPI regs */
2215 uint32_t mipi_mmio_base
;
2217 uint32_t psr_mmio_base
;
2219 uint32_t pps_mmio_base
;
2221 wait_queue_head_t gmbus_wait_queue
;
2223 struct pci_dev
*bridge_dev
;
2224 struct i915_gem_context
*kernel_context
;
2225 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
2226 struct i915_vma
*semaphore
;
2228 struct drm_dma_handle
*status_page_dmah
;
2229 struct resource mch_res
;
2231 /* protects the irq masks */
2232 spinlock_t irq_lock
;
2234 bool display_irqs_enabled
;
2236 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2237 struct pm_qos_request pm_qos
;
2239 /* Sideband mailbox protection */
2240 struct mutex sb_lock
;
2242 /** Cached value of IMR to avoid reads in updating the bitfield */
2245 u32 de_irq_mask
[I915_MAX_PIPES
];
2252 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
2254 struct i915_hotplug hotplug
;
2255 struct intel_fbc fbc
;
2256 struct i915_drrs drrs
;
2257 struct intel_opregion opregion
;
2258 struct intel_vbt_data vbt
;
2260 bool preserve_bios_swizzle
;
2263 struct intel_overlay
*overlay
;
2265 /* backlight registers and fields in struct intel_panel */
2266 struct mutex backlight_lock
;
2269 bool no_aux_handshake
;
2271 /* protects panel power sequencer state */
2272 struct mutex pps_mutex
;
2274 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2275 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2277 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2278 unsigned int skl_preferred_vco_freq
;
2279 unsigned int max_cdclk_freq
;
2281 unsigned int max_dotclk_freq
;
2282 unsigned int rawclk_freq
;
2283 unsigned int hpll_freq
;
2284 unsigned int czclk_freq
;
2288 * The current logical cdclk state.
2289 * See intel_atomic_state.cdclk.logical
2291 * For reading holding any crtc lock is sufficient,
2292 * for writing must hold all of them.
2294 struct intel_cdclk_state logical
;
2296 * The current actual cdclk state.
2297 * See intel_atomic_state.cdclk.actual
2299 struct intel_cdclk_state actual
;
2300 /* The current hardware cdclk state */
2301 struct intel_cdclk_state hw
;
2305 * wq - Driver workqueue for GEM.
2307 * NOTE: Work items scheduled here are not allowed to grab any modeset
2308 * locks, for otherwise the flushing done in the pageflip code will
2309 * result in deadlocks.
2311 struct workqueue_struct
*wq
;
2313 /* Display functions */
2314 struct drm_i915_display_funcs display
;
2316 /* PCH chipset type */
2317 enum intel_pch pch_type
;
2318 unsigned short pch_id
;
2320 unsigned long quirks
;
2322 enum modeset_restore modeset_restore
;
2323 struct mutex modeset_restore_lock
;
2324 struct drm_atomic_state
*modeset_restore_state
;
2325 struct drm_modeset_acquire_ctx reset_ctx
;
2327 struct list_head vm_list
; /* Global list of all address spaces */
2328 struct i915_ggtt ggtt
; /* VM representing the global address space */
2330 struct i915_gem_mm mm
;
2331 DECLARE_HASHTABLE(mm_structs
, 7);
2332 struct mutex mm_lock
;
2334 /* Kernel Modesetting */
2336 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2337 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2339 #ifdef CONFIG_DEBUG_FS
2340 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2343 /* dpll and cdclk state is protected by connection_mutex */
2344 int num_shared_dpll
;
2345 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2346 const struct intel_dpll_mgr
*dpll_mgr
;
2349 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2350 * Must be global rather than per dpll, because on some platforms
2351 * plls share registers.
2353 struct mutex dpll_lock
;
2355 unsigned int active_crtcs
;
2356 /* minimum acceptable cdclk for each pipe */
2357 int min_cdclk
[I915_MAX_PIPES
];
2359 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2361 struct i915_workarounds workarounds
;
2363 struct i915_frontbuffer_tracking fb_tracking
;
2365 struct intel_atomic_helper
{
2366 struct llist_head free_list
;
2367 struct work_struct free_work
;
2372 bool mchbar_need_disable
;
2374 struct intel_l3_parity l3_parity
;
2376 /* Cannot be determined by PCIID. You must always read a register. */
2379 /* gen6+ rps state */
2380 struct intel_gen6_power_mgmt rps
;
2382 /* ilk-only ips/rps state. Everything in here is protected by the global
2383 * mchdev_lock in intel_pm.c */
2384 struct intel_ilk_power_mgmt ips
;
2386 struct i915_power_domains power_domains
;
2388 struct i915_psr psr
;
2390 struct i915_gpu_error gpu_error
;
2392 struct drm_i915_gem_object
*vlv_pctx
;
2394 /* list of fbdev register on this device */
2395 struct intel_fbdev
*fbdev
;
2396 struct work_struct fbdev_suspend_work
;
2398 struct drm_property
*broadcast_rgb_property
;
2399 struct drm_property
*force_audio_property
;
2401 /* hda/i915 audio component */
2402 struct i915_audio_component
*audio_component
;
2403 bool audio_component_registered
;
2405 * av_mutex - mutex for audio/video sync
2408 struct mutex av_mutex
;
2411 struct list_head list
;
2412 struct llist_head free_list
;
2413 struct work_struct free_work
;
2415 /* The hw wants to have a stable context identifier for the
2416 * lifetime of the context (for OA, PASID, faults, etc).
2417 * This is limited in execlists to 21 bits.
2420 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2425 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2426 u32 chv_phy_control
;
2428 * Shadows for CHV DPLL_MD regs to keep the state
2429 * checker somewhat working in the presence hardware
2430 * crappiness (can't read out DPLL_MD for pipes B & C).
2432 u32 chv_dpll_md
[I915_MAX_PIPES
];
2436 bool suspended_to_idle
;
2437 struct i915_suspend_saved_registers regfile
;
2438 struct vlv_s0ix_state vlv_s0ix_state
;
2441 I915_SAGV_UNKNOWN
= 0,
2444 I915_SAGV_NOT_CONTROLLED
2449 * Raw watermark latency values:
2450 * in 0.1us units for WM0,
2451 * in 0.5us units for WM1+.
2454 uint16_t pri_latency
[5];
2456 uint16_t spr_latency
[5];
2458 uint16_t cur_latency
[5];
2460 * Raw watermark memory latency values
2461 * for SKL for all 8 levels
2464 uint16_t skl_latency
[8];
2466 /* current hardware state */
2468 struct ilk_wm_values hw
;
2469 struct skl_wm_values skl_hw
;
2470 struct vlv_wm_values vlv
;
2471 struct g4x_wm_values g4x
;
2477 * Should be held around atomic WM register writing; also
2478 * protects * intel_crtc->wm.active and
2479 * cstate->wm.need_postvbl_update.
2481 struct mutex wm_mutex
;
2484 * Set during HW readout of watermarks/DDB. Some platforms
2485 * need to know when we're still using BIOS-provided values
2486 * (which we don't fully trust).
2488 bool distrust_bios_wm
;
2491 struct i915_runtime_pm pm
;
2496 struct kobject
*metrics_kobj
;
2497 struct ctl_table_header
*sysctl_header
;
2500 * Lock associated with adding/modifying/removing OA configs
2501 * in dev_priv->perf.metrics_idr.
2503 struct mutex metrics_lock
;
2506 * List of dynamic configurations, you need to hold
2507 * dev_priv->perf.metrics_lock to access it.
2509 struct idr metrics_idr
;
2512 * Lock associated with anything below within this structure
2513 * except exclusive_stream.
2516 struct list_head streams
;
2520 * The stream currently using the OA unit. If accessed
2521 * outside a syscall associated to its file
2522 * descriptor, you need to hold
2523 * dev_priv->drm.struct_mutex.
2525 struct i915_perf_stream
*exclusive_stream
;
2527 u32 specific_ctx_id
;
2529 struct hrtimer poll_check_timer
;
2530 wait_queue_head_t poll_wq
;
2534 * For rate limiting any notifications of spurious
2535 * invalid OA reports
2537 struct ratelimit_state spurious_report_rs
;
2540 int period_exponent
;
2541 int timestamp_frequency
;
2543 struct i915_oa_config test_config
;
2546 struct i915_vma
*vma
;
2553 * Locks reads and writes to all head/tail state
2555 * Consider: the head and tail pointer state
2556 * needs to be read consistently from a hrtimer
2557 * callback (atomic context) and read() fop
2558 * (user context) with tail pointer updates
2559 * happening in atomic context and head updates
2560 * in user context and the (unlikely)
2561 * possibility of read() errors needing to
2562 * reset all head/tail state.
2564 * Note: Contention or performance aren't
2565 * currently a significant concern here
2566 * considering the relatively low frequency of
2567 * hrtimer callbacks (5ms period) and that
2568 * reads typically only happen in response to a
2569 * hrtimer event and likely complete before the
2572 * Note: This lock is not held *while* reading
2573 * and copying data to userspace so the value
2574 * of head observed in htrimer callbacks won't
2575 * represent any partial consumption of data.
2577 spinlock_t ptr_lock
;
2580 * One 'aging' tail pointer and one 'aged'
2581 * tail pointer ready to used for reading.
2583 * Initial values of 0xffffffff are invalid
2584 * and imply that an update is required
2585 * (and should be ignored by an attempted
2593 * Index for the aged tail ready to read()
2596 unsigned int aged_tail_idx
;
2599 * A monotonic timestamp for when the current
2600 * aging tail pointer was read; used to
2601 * determine when it is old enough to trust.
2603 u64 aging_timestamp
;
2606 * Although we can always read back the head
2607 * pointer register, we prefer to avoid
2608 * trusting the HW state, just to avoid any
2609 * risk that some hardware condition could
2610 * somehow bump the head pointer unpredictably
2611 * and cause us to forward the wrong OA buffer
2612 * data to userspace.
2617 u32 gen7_latched_oastatus1
;
2618 u32 ctx_oactxctrl_offset
;
2619 u32 ctx_flexeu0_offset
;
2622 * The RPT_ID/reason field for Gen8+ includes a bit
2623 * to determine if the CTX ID in the report is valid
2624 * but the specific bit differs between Gen 8 and 9
2626 u32 gen8_valid_ctx_bit
;
2628 struct i915_oa_ops ops
;
2629 const struct i915_oa_format
*oa_formats
;
2633 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2635 void (*resume
)(struct drm_i915_private
*);
2636 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2638 struct list_head timelines
;
2639 struct i915_gem_timeline global_timeline
;
2640 u32 active_requests
;
2643 * Is the GPU currently considered idle, or busy executing
2644 * userspace requests? Whilst idle, we allow runtime power
2645 * management to power down the hardware and display clocks.
2646 * In order to reduce the effect on performance, there
2647 * is a slight delay before we do so.
2652 * We leave the user IRQ off as much as possible,
2653 * but this means that requests will finish and never
2654 * be retired once the system goes idle. Set a timer to
2655 * fire periodically while the ring is running. When it
2656 * fires, go retire requests.
2658 struct delayed_work retire_work
;
2661 * When we detect an idle GPU, we want to turn on
2662 * powersaving features. So once we see that there
2663 * are no more requests outstanding and no more
2664 * arrive within a small period of time, we fire
2665 * off the idle_work.
2667 struct delayed_work idle_work
;
2669 ktime_t last_init_time
;
2672 /* perform PHY state sanity checks? */
2673 bool chv_phy_assert
[2];
2677 /* Used to save the pipe-to-encoder mapping for audio */
2678 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2680 /* necessary resource sharing with HDMI LPE audio driver. */
2682 struct platform_device
*platdev
;
2687 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2688 * will be rejected. Instead look for a better place.
2692 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2694 return container_of(dev
, struct drm_i915_private
, drm
);
2697 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2699 return to_i915(dev_get_drvdata(kdev
));
2702 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2704 return container_of(guc
, struct drm_i915_private
, guc
);
2707 static inline struct drm_i915_private
*huc_to_i915(struct intel_huc
*huc
)
2709 return container_of(huc
, struct drm_i915_private
, huc
);
2712 /* Simple iterator over all initialised engines */
2713 #define for_each_engine(engine__, dev_priv__, id__) \
2715 (id__) < I915_NUM_ENGINES; \
2717 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2719 /* Iterator over subset of engines selected by mask */
2720 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2721 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2722 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2724 enum hdmi_force_audio
{
2725 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2726 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2727 HDMI_AUDIO_AUTO
, /* trust EDID */
2728 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2731 #define I915_GTT_OFFSET_NONE ((u32)-1)
2734 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2735 * considered to be the frontbuffer for the given plane interface-wise. This
2736 * doesn't mean that the hw necessarily already scans it out, but that any
2737 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2739 * We have one bit per pipe and per scanout plane type.
2741 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2742 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2743 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2744 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2745 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2746 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2747 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2748 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2749 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2750 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2751 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2752 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2755 * Optimised SGL iterator for GEM objects
2757 static __always_inline
struct sgt_iter
{
2758 struct scatterlist
*sgp
;
2765 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2766 struct sgt_iter s
= { .sgp
= sgl
};
2769 s
.max
= s
.curr
= s
.sgp
->offset
;
2770 s
.max
+= s
.sgp
->length
;
2772 s
.dma
= sg_dma_address(s
.sgp
);
2774 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2780 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2783 if (unlikely(sg_is_chain(sg
)))
2784 sg
= sg_chain_ptr(sg
);
2789 * __sg_next - return the next scatterlist entry in a list
2790 * @sg: The current sg entry
2793 * If the entry is the last, return NULL; otherwise, step to the next
2794 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2795 * otherwise just return the pointer to the current element.
2797 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2799 #ifdef CONFIG_DEBUG_SG
2800 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2802 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2806 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2807 * @__dmap: DMA address (output)
2808 * @__iter: 'struct sgt_iter' (iterator state, internal)
2809 * @__sgt: sg_table to iterate over (input)
2811 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2812 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2813 ((__dmap) = (__iter).dma + (__iter).curr); \
2814 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2815 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2818 * for_each_sgt_page - iterate over the pages of the given sg_table
2819 * @__pp: page pointer (output)
2820 * @__iter: 'struct sgt_iter' (iterator state, internal)
2821 * @__sgt: sg_table to iterate over (input)
2823 #define for_each_sgt_page(__pp, __iter, __sgt) \
2824 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2825 ((__pp) = (__iter).pfn == 0 ? NULL : \
2826 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2827 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2828 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2830 static inline const struct intel_device_info
*
2831 intel_info(const struct drm_i915_private
*dev_priv
)
2833 return &dev_priv
->info
;
2836 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2838 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2839 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2841 #define REVID_FOREVER 0xff
2842 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2844 #define GEN_FOREVER (0)
2846 * Returns true if Gen is in inclusive range [Start, End].
2848 * Use GEN_FOREVER for unbound start and or end.
2850 #define IS_GEN(dev_priv, s, e) ({ \
2851 unsigned int __s = (s), __e = (e); \
2852 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2853 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2854 if ((__s) != GEN_FOREVER) \
2856 if ((__e) == GEN_FOREVER) \
2857 __e = BITS_PER_LONG - 1; \
2860 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2864 * Return true if revision is in range [since,until] inclusive.
2866 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2868 #define IS_REVID(p, since, until) \
2869 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2871 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2872 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2873 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2874 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2875 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2876 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2877 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2878 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2879 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2880 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2881 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2882 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2883 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2884 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2885 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2886 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2887 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2888 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2889 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2890 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2891 (dev_priv)->info.gt == 1)
2892 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2893 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2894 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2895 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2896 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2897 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2898 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2899 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2900 #define IS_COFFEELAKE(dev_priv) ((dev_priv)->info.platform == INTEL_COFFEELAKE)
2901 #define IS_CANNONLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_CANNONLAKE)
2902 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2903 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2904 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2905 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2906 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2907 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2908 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2909 /* ULX machines are also considered ULT. */
2910 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2911 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2912 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2913 (dev_priv)->info.gt == 3)
2914 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2915 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2916 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2917 (dev_priv)->info.gt == 3)
2918 /* ULX machines are also considered ULT. */
2919 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2920 INTEL_DEVID(dev_priv) == 0x0A1E)
2921 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2922 INTEL_DEVID(dev_priv) == 0x1913 || \
2923 INTEL_DEVID(dev_priv) == 0x1916 || \
2924 INTEL_DEVID(dev_priv) == 0x1921 || \
2925 INTEL_DEVID(dev_priv) == 0x1926)
2926 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2927 INTEL_DEVID(dev_priv) == 0x1915 || \
2928 INTEL_DEVID(dev_priv) == 0x191E)
2929 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2930 INTEL_DEVID(dev_priv) == 0x5913 || \
2931 INTEL_DEVID(dev_priv) == 0x5916 || \
2932 INTEL_DEVID(dev_priv) == 0x5921 || \
2933 INTEL_DEVID(dev_priv) == 0x5926)
2934 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2935 INTEL_DEVID(dev_priv) == 0x5915 || \
2936 INTEL_DEVID(dev_priv) == 0x591E)
2937 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2938 (dev_priv)->info.gt == 2)
2939 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2940 (dev_priv)->info.gt == 3)
2941 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2942 (dev_priv)->info.gt == 4)
2943 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2944 (dev_priv)->info.gt == 2)
2945 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2946 (dev_priv)->info.gt == 3)
2947 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2948 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2950 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2952 #define SKL_REVID_A0 0x0
2953 #define SKL_REVID_B0 0x1
2954 #define SKL_REVID_C0 0x2
2955 #define SKL_REVID_D0 0x3
2956 #define SKL_REVID_E0 0x4
2957 #define SKL_REVID_F0 0x5
2958 #define SKL_REVID_G0 0x6
2959 #define SKL_REVID_H0 0x7
2961 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2963 #define BXT_REVID_A0 0x0
2964 #define BXT_REVID_A1 0x1
2965 #define BXT_REVID_B0 0x3
2966 #define BXT_REVID_B_LAST 0x8
2967 #define BXT_REVID_C0 0x9
2969 #define IS_BXT_REVID(dev_priv, since, until) \
2970 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2972 #define KBL_REVID_A0 0x0
2973 #define KBL_REVID_B0 0x1
2974 #define KBL_REVID_C0 0x2
2975 #define KBL_REVID_D0 0x3
2976 #define KBL_REVID_E0 0x4
2978 #define IS_KBL_REVID(dev_priv, since, until) \
2979 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2981 #define GLK_REVID_A0 0x0
2982 #define GLK_REVID_A1 0x1
2984 #define IS_GLK_REVID(dev_priv, since, until) \
2985 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2987 #define CNL_REVID_A0 0x0
2988 #define CNL_REVID_B0 0x1
2990 #define IS_CNL_REVID(p, since, until) \
2991 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2994 * The genX designation typically refers to the render engine, so render
2995 * capability related checks should use IS_GEN, while display and other checks
2996 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2999 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
3000 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
3001 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
3002 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
3003 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
3004 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
3005 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
3006 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
3007 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
3009 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
3010 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
3011 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
3013 #define ENGINE_MASK(id) BIT(id)
3014 #define RENDER_RING ENGINE_MASK(RCS)
3015 #define BSD_RING ENGINE_MASK(VCS)
3016 #define BLT_RING ENGINE_MASK(BCS)
3017 #define VEBOX_RING ENGINE_MASK(VECS)
3018 #define BSD2_RING ENGINE_MASK(VCS2)
3019 #define ALL_ENGINES (~0)
3021 #define HAS_ENGINE(dev_priv, id) \
3022 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
3024 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
3025 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
3026 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
3027 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
3029 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
3030 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
3031 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
3032 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
3033 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
3035 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
3037 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
3038 ((dev_priv)->info.has_logical_ring_contexts)
3039 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
3040 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
3041 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
3043 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
3044 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
3045 ((dev_priv)->info.overlay_needs_physical)
3047 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
3048 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
3050 /* WaRsDisableCoarsePowerGating:skl,bxt */
3051 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
3052 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
3055 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
3056 * even when in MSI mode. This results in spurious interrupt warnings if the
3057 * legacy irq no. is shared with another device. The kernel then disables that
3058 * interrupt source and so prevents the other device from working properly.
3060 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
3061 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
3063 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
3064 * rows, which changed the alignment requirements and fence programming.
3066 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
3067 !(IS_I915G(dev_priv) || \
3068 IS_I915GM(dev_priv)))
3069 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
3070 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
3072 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
3073 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
3074 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
3075 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
3077 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
3079 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
3081 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
3082 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
3083 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
3084 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
3085 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
3087 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
3089 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
3090 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
3093 * For now, anything with a GuC requires uCode loading, and then supports
3094 * command submission once loaded. But these are logically independent
3095 * properties, so we have separate macros to test them.
3097 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
3098 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
3099 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3100 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
3101 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3103 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
3105 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
3107 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
3108 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3109 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
3110 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3111 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3112 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
3113 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
3114 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
3115 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
3116 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
3117 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
3118 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
3119 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
3120 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
3121 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
3122 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3124 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3125 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3126 #define HAS_PCH_CNP_LP(dev_priv) \
3127 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3128 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
3129 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
3130 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3131 #define HAS_PCH_LPT_LP(dev_priv) \
3132 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
3133 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
3134 #define HAS_PCH_LPT_H(dev_priv) \
3135 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
3136 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
3137 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3138 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3139 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3140 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3142 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3144 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3146 /* DPF == dynamic parity feature */
3147 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3148 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3149 2 : HAS_L3_DPF(dev_priv))
3151 #define GT_FREQUENCY_MULTIPLIER 50
3152 #define GEN9_FREQ_SCALER 3
3154 #include "i915_trace.h"
3156 static inline bool intel_vtd_active(void)
3158 #ifdef CONFIG_INTEL_IOMMU
3159 if (intel_iommu_gfx_mapped
)
3165 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3167 return INTEL_GEN(dev_priv
) >= 6 && intel_vtd_active();
3171 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3173 return IS_BROXTON(dev_priv
) && intel_vtd_active();
3176 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
3179 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
3183 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
3184 const char *fmt
, ...);
3186 #define i915_report_error(dev_priv, fmt, ...) \
3187 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3189 #ifdef CONFIG_COMPAT
3190 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
3193 #define i915_compat_ioctl NULL
3195 extern const struct dev_pm_ops i915_pm_ops
;
3197 extern int i915_driver_load(struct pci_dev
*pdev
,
3198 const struct pci_device_id
*ent
);
3199 extern void i915_driver_unload(struct drm_device
*dev
);
3200 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3201 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3203 #define I915_RESET_QUIET BIT(0)
3204 extern void i915_reset(struct drm_i915_private
*i915
, unsigned int flags
);
3205 extern int i915_reset_engine(struct intel_engine_cs
*engine
,
3206 unsigned int flags
);
3208 extern bool intel_has_reset_engine(struct drm_i915_private
*dev_priv
);
3209 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3210 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3211 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
3212 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3213 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3214 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3215 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3216 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3218 int intel_engines_init_mmio(struct drm_i915_private
*dev_priv
);
3219 int intel_engines_init(struct drm_i915_private
*dev_priv
);
3221 /* intel_hotplug.c */
3222 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3223 u32 pin_mask
, u32 long_mask
);
3224 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3225 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3226 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3227 enum port
intel_hpd_pin_to_port(enum hpd_pin pin
);
3228 enum hpd_pin
intel_hpd_pin(enum port port
);
3229 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3230 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3233 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3235 unsigned long delay
;
3237 if (unlikely(!i915
.enable_hangcheck
))
3240 /* Don't continually defer the hangcheck so that it is always run at
3241 * least once after work has been scheduled on any ring. Otherwise,
3242 * we will ignore a hung ring if a second ring is kept busy.
3245 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3246 queue_delayed_work(system_long_wq
,
3247 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3251 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3253 const char *fmt
, ...);
3255 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3256 extern void intel_irq_fini(struct drm_i915_private
*dev_priv
);
3257 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3258 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3260 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3262 return dev_priv
->gvt
;
3265 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3267 return dev_priv
->vgpu
.active
;
3271 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3275 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3278 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3279 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3280 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3283 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3284 uint32_t interrupt_mask
,
3285 uint32_t enabled_irq_mask
);
3287 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3289 ilk_update_display_irq(dev_priv
, bits
, bits
);
3292 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3294 ilk_update_display_irq(dev_priv
, bits
, 0);
3296 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3298 uint32_t interrupt_mask
,
3299 uint32_t enabled_irq_mask
);
3300 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3301 enum pipe pipe
, uint32_t bits
)
3303 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3305 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3306 enum pipe pipe
, uint32_t bits
)
3308 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3310 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3311 uint32_t interrupt_mask
,
3312 uint32_t enabled_irq_mask
);
3314 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3316 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3319 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3321 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3325 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3326 struct drm_file
*file_priv
);
3327 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3328 struct drm_file
*file_priv
);
3329 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3330 struct drm_file
*file_priv
);
3331 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3332 struct drm_file
*file_priv
);
3333 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3334 struct drm_file
*file_priv
);
3335 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3336 struct drm_file
*file_priv
);
3337 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3338 struct drm_file
*file_priv
);
3339 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3340 struct drm_file
*file_priv
);
3341 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3342 struct drm_file
*file_priv
);
3343 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3344 struct drm_file
*file_priv
);
3345 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3346 struct drm_file
*file
);
3347 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3348 struct drm_file
*file
);
3349 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3350 struct drm_file
*file_priv
);
3351 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3352 struct drm_file
*file_priv
);
3353 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
3354 struct drm_file
*file_priv
);
3355 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
3356 struct drm_file
*file_priv
);
3357 int i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3358 void i915_gem_cleanup_userptr(struct drm_i915_private
*dev_priv
);
3359 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3360 struct drm_file
*file
);
3361 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3362 struct drm_file
*file_priv
);
3363 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3364 struct drm_file
*file_priv
);
3365 void i915_gem_sanitize(struct drm_i915_private
*i915
);
3366 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
3367 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
3368 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3369 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3370 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3372 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
3373 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3374 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3375 const struct drm_i915_gem_object_ops
*ops
);
3376 struct drm_i915_gem_object
*
3377 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
3378 struct drm_i915_gem_object
*
3379 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
3380 const void *data
, size_t size
);
3381 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3382 void i915_gem_free_object(struct drm_gem_object
*obj
);
3384 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
3386 /* A single pass should suffice to release all the freed objects (along
3387 * most call paths) , but be a little more paranoid in that freeing
3388 * the objects does take a little amount of time, during which the rcu
3389 * callbacks could have added new objects into the freed list, and
3390 * armed the work again.
3394 } while (flush_work(&i915
->mm
.free_work
));
3397 static inline void i915_gem_drain_workqueue(struct drm_i915_private
*i915
)
3400 * Similar to objects above (see i915_gem_drain_freed-objects), in
3401 * general we have workers that are armed by RCU and then rearm
3402 * themselves in their callbacks. To be paranoid, we need to
3403 * drain the workqueue a second time after waiting for the RCU
3404 * grace period so that we catch work queued via RCU from the first
3405 * pass. As neither drain_workqueue() nor flush_workqueue() report
3406 * a result, we make an assumption that we only don't require more
3407 * than 2 passes to catch all recursive RCU delayed work.
3413 drain_workqueue(i915
->wq
);
3417 struct i915_vma
* __must_check
3418 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3419 const struct i915_ggtt_view
*view
,
3424 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3425 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3427 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3429 static inline int __sg_page_count(const struct scatterlist
*sg
)
3431 return sg
->length
>> PAGE_SHIFT
;
3434 struct scatterlist
*
3435 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3436 unsigned int n
, unsigned int *offset
);
3439 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3443 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3447 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3450 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3451 struct sg_table
*pages
);
3452 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3454 static inline int __must_check
3455 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3457 might_lock(&obj
->mm
.lock
);
3459 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3462 return __i915_gem_object_get_pages(obj
);
3466 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3468 GEM_BUG_ON(!obj
->mm
.pages
);
3470 atomic_inc(&obj
->mm
.pages_pin_count
);
3474 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3476 return atomic_read(&obj
->mm
.pages_pin_count
);
3480 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3482 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3483 GEM_BUG_ON(!obj
->mm
.pages
);
3485 atomic_dec(&obj
->mm
.pages_pin_count
);
3489 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3491 __i915_gem_object_unpin_pages(obj
);
3494 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3499 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3500 enum i915_mm_subclass subclass
);
3501 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3503 enum i915_map_type
{
3506 #define I915_MAP_OVERRIDE BIT(31)
3507 I915_MAP_FORCE_WB
= I915_MAP_WB
| I915_MAP_OVERRIDE
,
3508 I915_MAP_FORCE_WC
= I915_MAP_WC
| I915_MAP_OVERRIDE
,
3512 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3513 * @obj: the object to map into kernel address space
3514 * @type: the type of mapping, used to select pgprot_t
3516 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3517 * pages and then returns a contiguous mapping of the backing storage into
3518 * the kernel address space. Based on the @type of mapping, the PTE will be
3519 * set to either WriteBack or WriteCombine (via pgprot_t).
3521 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3522 * mapping is no longer required.
3524 * Returns the pointer through which to access the mapped object, or an
3525 * ERR_PTR() on error.
3527 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3528 enum i915_map_type type
);
3531 * i915_gem_object_unpin_map - releases an earlier mapping
3532 * @obj: the object to unmap
3534 * After pinning the object and mapping its pages, once you are finished
3535 * with your access, call i915_gem_object_unpin_map() to release the pin
3536 * upon the mapping. Once the pin count reaches zero, that mapping may be
3539 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3541 i915_gem_object_unpin_pages(obj
);
3544 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3545 unsigned int *needs_clflush
);
3546 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3547 unsigned int *needs_clflush
);
3548 #define CLFLUSH_BEFORE BIT(0)
3549 #define CLFLUSH_AFTER BIT(1)
3550 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3553 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3555 i915_gem_object_unpin_pages(obj
);
3558 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3559 void i915_vma_move_to_active(struct i915_vma
*vma
,
3560 struct drm_i915_gem_request
*req
,
3561 unsigned int flags
);
3562 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3563 struct drm_device
*dev
,
3564 struct drm_mode_create_dumb
*args
);
3565 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3566 uint32_t handle
, uint64_t *offset
);
3567 int i915_gem_mmap_gtt_version(void);
3569 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3570 struct drm_i915_gem_object
*new,
3571 unsigned frontbuffer_bits
);
3573 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3575 struct drm_i915_gem_request
*
3576 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3578 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3580 static inline bool i915_reset_backoff(struct i915_gpu_error
*error
)
3582 return unlikely(test_bit(I915_RESET_BACKOFF
, &error
->flags
));
3585 static inline bool i915_reset_handoff(struct i915_gpu_error
*error
)
3587 return unlikely(test_bit(I915_RESET_HANDOFF
, &error
->flags
));
3590 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3592 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3595 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error
*error
)
3597 return i915_reset_backoff(error
) | i915_terminally_wedged(error
);
3600 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3602 return READ_ONCE(error
->reset_count
);
3605 static inline u32
i915_reset_engine_count(struct i915_gpu_error
*error
,
3606 struct intel_engine_cs
*engine
)
3608 return READ_ONCE(error
->reset_engine_count
[engine
->id
]);
3611 struct drm_i915_gem_request
*
3612 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
);
3613 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3614 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3615 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
);
3616 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3617 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3618 bool i915_gem_unset_wedged(struct drm_i915_private
*dev_priv
);
3619 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
3620 struct drm_i915_gem_request
*request
);
3622 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3623 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3624 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3625 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3626 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3627 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3628 unsigned int flags
);
3629 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3630 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3631 int i915_gem_fault(struct vm_fault
*vmf
);
3632 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3635 struct intel_rps_client
*rps
);
3636 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3639 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3642 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
);
3644 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
);
3646 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3647 struct i915_vma
* __must_check
3648 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3650 const struct i915_ggtt_view
*view
);
3651 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3652 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3654 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
);
3655 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3657 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3658 enum i915_cache_level cache_level
);
3660 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3661 struct dma_buf
*dma_buf
);
3663 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3664 struct drm_gem_object
*gem_obj
, int flags
);
3666 static inline struct i915_hw_ppgtt
*
3667 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3669 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3672 /* i915_gem_fence_reg.c */
3673 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3674 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3675 struct drm_i915_fence_reg
*
3676 i915_reserve_fence(struct drm_i915_private
*dev_priv
);
3677 void i915_unreserve_fence(struct drm_i915_fence_reg
*fence
);
3679 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3680 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3682 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3683 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3684 struct sg_table
*pages
);
3685 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3686 struct sg_table
*pages
);
3688 static inline struct i915_gem_context
*
3689 __i915_gem_context_lookup_rcu(struct drm_i915_file_private
*file_priv
, u32 id
)
3691 return idr_find(&file_priv
->context_idr
, id
);
3694 static inline struct i915_gem_context
*
3695 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3697 struct i915_gem_context
*ctx
;
3700 ctx
= __i915_gem_context_lookup_rcu(file_priv
, id
);
3701 if (ctx
&& !kref_get_unless_zero(&ctx
->ref
))
3708 static inline struct intel_timeline
*
3709 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3710 struct intel_engine_cs
*engine
)
3712 struct i915_address_space
*vm
;
3714 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3715 return &vm
->timeline
.engine
[engine
->id
];
3718 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3719 struct drm_file
*file
);
3720 int i915_perf_add_config_ioctl(struct drm_device
*dev
, void *data
,
3721 struct drm_file
*file
);
3722 int i915_perf_remove_config_ioctl(struct drm_device
*dev
, void *data
,
3723 struct drm_file
*file
);
3724 void i915_oa_init_reg_state(struct intel_engine_cs
*engine
,
3725 struct i915_gem_context
*ctx
,
3726 uint32_t *reg_state
);
3728 /* i915_gem_evict.c */
3729 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3730 u64 min_size
, u64 alignment
,
3731 unsigned cache_level
,
3734 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3735 struct drm_mm_node
*node
,
3736 unsigned int flags
);
3737 int i915_gem_evict_vm(struct i915_address_space
*vm
);
3739 /* belongs in i915_gem_gtt.h */
3740 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3743 if (INTEL_GEN(dev_priv
) < 6)
3744 intel_gtt_chipset_flush();
3747 /* i915_gem_stolen.c */
3748 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3749 struct drm_mm_node
*node
, u64 size
,
3750 unsigned alignment
);
3751 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3752 struct drm_mm_node
*node
, u64 size
,
3753 unsigned alignment
, u64 start
,
3755 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3756 struct drm_mm_node
*node
);
3757 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3758 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3759 struct drm_i915_gem_object
*
3760 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3761 struct drm_i915_gem_object
*
3762 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3767 /* i915_gem_internal.c */
3768 struct drm_i915_gem_object
*
3769 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3772 /* i915_gem_shrinker.c */
3773 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3774 unsigned long target
,
3775 unsigned long *nr_scanned
,
3777 #define I915_SHRINK_PURGEABLE 0x1
3778 #define I915_SHRINK_UNBOUND 0x2
3779 #define I915_SHRINK_BOUND 0x4
3780 #define I915_SHRINK_ACTIVE 0x8
3781 #define I915_SHRINK_VMAPS 0x10
3782 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3783 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3784 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3787 /* i915_gem_tiling.c */
3788 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3790 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3792 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3793 i915_gem_object_is_tiled(obj
);
3796 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3797 unsigned int tiling
, unsigned int stride
);
3798 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3799 unsigned int tiling
, unsigned int stride
);
3801 /* i915_debugfs.c */
3802 #ifdef CONFIG_DEBUG_FS
3803 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3804 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3805 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3807 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3808 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3810 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3813 /* i915_gpu_error.c */
3814 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3817 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3818 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3819 const struct i915_gpu_state
*gpu
);
3820 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3821 struct drm_i915_private
*i915
,
3822 size_t count
, loff_t pos
);
3823 static inline void i915_error_state_buf_release(
3824 struct drm_i915_error_state_buf
*eb
)
3829 struct i915_gpu_state
*i915_capture_gpu_state(struct drm_i915_private
*i915
);
3830 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3832 const char *error_msg
);
3834 static inline struct i915_gpu_state
*
3835 i915_gpu_state_get(struct i915_gpu_state
*gpu
)
3837 kref_get(&gpu
->ref
);
3841 void __i915_gpu_state_free(struct kref
*kref
);
3842 static inline void i915_gpu_state_put(struct i915_gpu_state
*gpu
)
3845 kref_put(&gpu
->ref
, __i915_gpu_state_free
);
3848 struct i915_gpu_state
*i915_first_error_state(struct drm_i915_private
*i915
);
3849 void i915_reset_error_state(struct drm_i915_private
*i915
);
3853 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3855 const char *error_msg
)
3859 static inline struct i915_gpu_state
*
3860 i915_first_error_state(struct drm_i915_private
*i915
)
3865 static inline void i915_reset_error_state(struct drm_i915_private
*i915
)
3871 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3873 /* i915_cmd_parser.c */
3874 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3875 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3876 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3877 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3878 struct drm_i915_gem_object
*batch_obj
,
3879 struct drm_i915_gem_object
*shadow_batch_obj
,
3880 u32 batch_start_offset
,
3885 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3886 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3887 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3888 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3890 /* i915_suspend.c */
3891 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3892 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3895 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3896 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3898 /* intel_lpe_audio.c */
3899 int intel_lpe_audio_init(struct drm_i915_private
*dev_priv
);
3900 void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv
);
3901 void intel_lpe_audio_irq_handler(struct drm_i915_private
*dev_priv
);
3902 void intel_lpe_audio_notify(struct drm_i915_private
*dev_priv
,
3903 enum pipe pipe
, enum port port
,
3904 const void *eld
, int ls_clock
, bool dp_output
);
3907 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
3908 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
3909 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3912 extern struct i2c_adapter
*
3913 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3914 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3915 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3916 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3918 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3920 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
3923 void intel_bios_init(struct drm_i915_private
*dev_priv
);
3924 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3925 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3926 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3927 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3928 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3929 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3930 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3931 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3933 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3937 /* intel_opregion.c */
3939 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3940 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3941 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3942 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3943 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3945 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3947 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3949 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3950 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3951 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3952 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3956 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3961 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3965 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3973 extern void intel_register_dsm_handler(void);
3974 extern void intel_unregister_dsm_handler(void);
3976 static inline void intel_register_dsm_handler(void) { return; }
3977 static inline void intel_unregister_dsm_handler(void) { return; }
3978 #endif /* CONFIG_ACPI */
3980 /* intel_device_info.c */
3981 static inline struct intel_device_info
*
3982 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3984 return (struct intel_device_info
*)&dev_priv
->info
;
3987 const char *intel_platform_name(enum intel_platform platform
);
3988 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3989 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3992 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3993 extern int intel_modeset_init(struct drm_device
*dev
);
3994 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3995 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3996 extern int intel_connector_register(struct drm_connector
*);
3997 extern void intel_connector_unregister(struct drm_connector
*);
3998 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
4000 extern void intel_display_resume(struct drm_device
*dev
);
4001 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
4002 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
4003 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
4004 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
4005 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
4006 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
4009 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
4010 struct drm_file
*file
);
4013 extern struct intel_overlay_error_state
*
4014 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
4015 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
4016 struct intel_overlay_error_state
*error
);
4018 extern struct intel_display_error_state
*
4019 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
4020 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
4021 struct intel_display_error_state
*error
);
4023 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
4024 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
4025 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
4026 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
4028 /* intel_sideband.c */
4029 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
4030 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
4031 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
4032 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
4033 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
4034 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4035 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4036 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4037 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4038 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4039 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4040 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
4041 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
4042 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
4043 enum intel_sbi_destination destination
);
4044 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
4045 enum intel_sbi_destination destination
);
4046 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4047 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4049 /* intel_dpio_phy.c */
4050 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
4051 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
4052 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
4053 enum port port
, u32 margin
, u32 scale
,
4054 u32 enable
, u32 deemphasis
);
4055 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
4056 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
4057 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
4059 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
4061 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
4062 uint8_t lane_count
);
4063 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
4064 uint8_t lane_lat_optim_mask
);
4065 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
4067 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
4068 u32 deemph_reg_value
, u32 margin_reg_value
,
4069 bool uniq_trans_scale
);
4070 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
4072 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
4073 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
4074 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
4075 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
4077 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
4078 u32 demph_reg_value
, u32 preemph_reg_value
,
4079 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
4080 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
4081 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
4082 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
4084 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
4085 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
4086 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
4087 const i915_reg_t reg
);
4089 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
4090 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
4092 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
4093 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
4094 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
4095 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
4097 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
4098 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
4099 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
4100 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
4102 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
4103 * will be implemented using 2 32-bit writes in an arbitrary order with
4104 * an arbitrary delay between them. This can cause the hardware to
4105 * act upon the intermediate value, possibly leading to corruption and
4106 * machine death. For this reason we do not support I915_WRITE64, or
4107 * dev_priv->uncore.funcs.mmio_writeq.
4109 * When reading a 64-bit value as two 32-bit values, the delay may cause
4110 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
4111 * occasionally a 64-bit register does not actualy support a full readq
4112 * and must be read using two 32-bit reads.
4114 * You have been warned.
4116 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
4118 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
4119 u32 upper, lower, old_upper, loop = 0; \
4120 upper = I915_READ(upper_reg); \
4122 old_upper = upper; \
4123 lower = I915_READ(lower_reg); \
4124 upper = I915_READ(upper_reg); \
4125 } while (upper != old_upper && loop++ < 2); \
4126 (u64)upper << 32 | lower; })
4128 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
4129 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
4131 #define __raw_read(x, s) \
4132 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
4135 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
4138 #define __raw_write(x, s) \
4139 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
4140 i915_reg_t reg, uint##x##_t val) \
4142 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
4157 /* These are untraced mmio-accessors that are only valid to be used inside
4158 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4161 * Think twice, and think again, before using these.
4163 * As an example, these accessors can possibly be used between:
4165 * spin_lock_irq(&dev_priv->uncore.lock);
4166 * intel_uncore_forcewake_get__locked();
4170 * intel_uncore_forcewake_put__locked();
4171 * spin_unlock_irq(&dev_priv->uncore.lock);
4174 * Note: some registers may not need forcewake held, so
4175 * intel_uncore_forcewake_{get,put} can be omitted, see
4176 * intel_uncore_forcewake_for_reg().
4178 * Certain architectures will die if the same cacheline is concurrently accessed
4179 * by different clients (e.g. on Ivybridge). Access to registers should
4180 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4181 * a more localised lock guarding all access to that bank of registers.
4183 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4184 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4185 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4186 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4188 /* "Broadcast RGB" property */
4189 #define INTEL_BROADCAST_RGB_AUTO 0
4190 #define INTEL_BROADCAST_RGB_FULL 1
4191 #define INTEL_BROADCAST_RGB_LIMITED 2
4193 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
4195 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4196 return VLV_VGACNTRL
;
4197 else if (INTEL_GEN(dev_priv
) >= 5)
4198 return CPU_VGACNTRL
;
4203 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
4205 unsigned long j
= msecs_to_jiffies(m
);
4207 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4210 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4212 /* nsecs_to_jiffies64() does not guard against overflow */
4213 if (NSEC_PER_SEC
% HZ
&&
4214 div_u64(n
, NSEC_PER_SEC
) >= MAX_JIFFY_OFFSET
/ HZ
)
4215 return MAX_JIFFY_OFFSET
;
4217 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4220 static inline unsigned long
4221 timespec_to_jiffies_timeout(const struct timespec
*value
)
4223 unsigned long j
= timespec_to_jiffies(value
);
4225 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4229 * If you need to wait X milliseconds between events A and B, but event B
4230 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4231 * when event A happened, then just before event B you call this function and
4232 * pass the timestamp as the first argument, and X as the second argument.
4235 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4237 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4240 * Don't re-read the value of "jiffies" every time since it may change
4241 * behind our back and break the math.
4243 tmp_jiffies
= jiffies
;
4244 target_jiffies
= timestamp_jiffies
+
4245 msecs_to_jiffies_timeout(to_wait_ms
);
4247 if (time_after(target_jiffies
, tmp_jiffies
)) {
4248 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4249 while (remaining_jiffies
)
4251 schedule_timeout_uninterruptible(remaining_jiffies
);
4256 __i915_request_irq_complete(const struct drm_i915_gem_request
*req
)
4258 struct intel_engine_cs
*engine
= req
->engine
;
4261 /* Note that the engine may have wrapped around the seqno, and
4262 * so our request->global_seqno will be ahead of the hardware,
4263 * even though it completed the request before wrapping. We catch
4264 * this by kicking all the waiters before resetting the seqno
4265 * in hardware, and also signal the fence.
4267 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &req
->fence
.flags
))
4270 /* The request was dequeued before we were awoken. We check after
4271 * inspecting the hw to confirm that this was the same request
4272 * that generated the HWS update. The memory barriers within
4273 * the request execution are sufficient to ensure that a check
4274 * after reading the value from hw matches this request.
4276 seqno
= i915_gem_request_global_seqno(req
);
4280 /* Before we do the heavier coherent read of the seqno,
4281 * check the value (hopefully) in the CPU cacheline.
4283 if (__i915_gem_request_completed(req
, seqno
))
4286 /* Ensure our read of the seqno is coherent so that we
4287 * do not "miss an interrupt" (i.e. if this is the last
4288 * request and the seqno write from the GPU is not visible
4289 * by the time the interrupt fires, we will see that the
4290 * request is incomplete and go back to sleep awaiting
4291 * another interrupt that will never come.)
4293 * Strictly, we only need to do this once after an interrupt,
4294 * but it is easier and safer to do it every time the waiter
4297 if (engine
->irq_seqno_barrier
&&
4298 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
4299 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
4301 /* The ordering of irq_posted versus applying the barrier
4302 * is crucial. The clearing of the current irq_posted must
4303 * be visible before we perform the barrier operation,
4304 * such that if a subsequent interrupt arrives, irq_posted
4305 * is reasserted and our task rewoken (which causes us to
4306 * do another __i915_request_irq_complete() immediately
4307 * and reapply the barrier). Conversely, if the clear
4308 * occurs after the barrier, then an interrupt that arrived
4309 * whilst we waited on the barrier would not trigger a
4310 * barrier on the next pass, and the read may not see the
4313 engine
->irq_seqno_barrier(engine
);
4315 /* If we consume the irq, but we are no longer the bottom-half,
4316 * the real bottom-half may not have serialised their own
4317 * seqno check with the irq-barrier (i.e. may have inspected
4318 * the seqno before we believe it coherent since they see
4319 * irq_posted == false but we are still running).
4321 spin_lock_irq(&b
->irq_lock
);
4322 if (b
->irq_wait
&& b
->irq_wait
->tsk
!= current
)
4323 /* Note that if the bottom-half is changed as we
4324 * are sending the wake-up, the new bottom-half will
4325 * be woken by whomever made the change. We only have
4326 * to worry about when we steal the irq-posted for
4329 wake_up_process(b
->irq_wait
->tsk
);
4330 spin_unlock_irq(&b
->irq_lock
);
4332 if (__i915_gem_request_completed(req
, seqno
))
4339 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4340 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4342 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4343 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4344 * perform the operation. To check beforehand, pass in the parameters to
4345 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4346 * you only need to pass in the minor offsets, page-aligned pointers are
4349 * For just checking for SSE4.1, in the foreknowledge that the future use
4350 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4352 #define i915_can_memcpy_from_wc(dst, src, len) \
4353 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4355 #define i915_has_memcpy_from_wc() \
4356 i915_memcpy_from_wc(NULL, NULL, 0)
4359 int remap_io_mapping(struct vm_area_struct
*vma
,
4360 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4361 struct io_mapping
*iomap
);