1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain
{
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
98 POWER_DOMAIN_TRANSCODER_A
,
99 POWER_DOMAIN_TRANSCODER_B
,
100 POWER_DOMAIN_TRANSCODER_C
,
101 POWER_DOMAIN_TRANSCODER_EDP
= POWER_DOMAIN_TRANSCODER_A
+ 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
112 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct drm_i915_private
;
138 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
143 #define I915_NUM_PLLS 2
145 struct intel_dpll_hw_state
{
152 struct intel_shared_dpll
{
153 int refcount
; /* count of number of CRTCs sharing this PLL */
154 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
155 bool on
; /* is the PLL actually active? Disabled during modeset */
157 /* should match the index in the dev_priv->shared_dplls array */
158 enum intel_dpll_id id
;
159 struct intel_dpll_hw_state hw_state
;
160 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
161 struct intel_shared_dpll
*pll
);
162 void (*enable
)(struct drm_i915_private
*dev_priv
,
163 struct intel_shared_dpll
*pll
);
164 void (*disable
)(struct drm_i915_private
*dev_priv
,
165 struct intel_shared_dpll
*pll
);
166 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
167 struct intel_shared_dpll
*pll
,
168 struct intel_dpll_hw_state
*hw_state
);
171 /* Used by dp and fdi links */
172 struct intel_link_m_n
{
180 void intel_link_compute_m_n(int bpp
, int nlanes
,
181 int pixel_clock
, int link_clock
,
182 struct intel_link_m_n
*m_n
);
184 struct intel_ddi_plls
{
190 /* Interface history:
193 * 1.2: Add Power Management
194 * 1.3: Add vblank support
195 * 1.4: Fix cmdbuffer path, add heap destroy
196 * 1.5: Add vblank pipe configuration
197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
198 * - Support vertical blank on secondary display pipe
200 #define DRIVER_MAJOR 1
201 #define DRIVER_MINOR 6
202 #define DRIVER_PATCHLEVEL 0
204 #define WATCH_COHERENCY 0
205 #define WATCH_LISTS 0
208 #define I915_GEM_PHYS_CURSOR_0 1
209 #define I915_GEM_PHYS_CURSOR_1 2
210 #define I915_GEM_PHYS_OVERLAY_REGS 3
211 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
213 struct drm_i915_gem_phys_object
{
215 struct page
**page_list
;
216 drm_dma_handle_t
*handle
;
217 struct drm_i915_gem_object
*cur_obj
;
220 struct opregion_header
;
221 struct opregion_acpi
;
222 struct opregion_swsci
;
223 struct opregion_asle
;
225 struct intel_opregion
{
226 struct opregion_header __iomem
*header
;
227 struct opregion_acpi __iomem
*acpi
;
228 struct opregion_swsci __iomem
*swsci
;
229 struct opregion_asle __iomem
*asle
;
231 u32 __iomem
*lid_state
;
233 #define OPREGION_SIZE (8*1024)
235 struct intel_overlay
;
236 struct intel_overlay_error_state
;
238 struct drm_i915_master_private
{
239 drm_local_map_t
*sarea
;
240 struct _drm_i915_sarea
*sarea_priv
;
242 #define I915_FENCE_REG_NONE -1
243 #define I915_MAX_NUM_FENCES 32
244 /* 32 fences + sign bit for FENCE_REG_NONE */
245 #define I915_MAX_NUM_FENCE_BITS 6
247 struct drm_i915_fence_reg
{
248 struct list_head lru_list
;
249 struct drm_i915_gem_object
*obj
;
253 struct sdvo_device_mapping
{
262 struct intel_display_error_state
;
264 struct drm_i915_error_state
{
272 bool waiting
[I915_NUM_RINGS
];
273 u32 pipestat
[I915_MAX_PIPES
];
274 u32 tail
[I915_NUM_RINGS
];
275 u32 head
[I915_NUM_RINGS
];
276 u32 ctl
[I915_NUM_RINGS
];
277 u32 ipeir
[I915_NUM_RINGS
];
278 u32 ipehr
[I915_NUM_RINGS
];
279 u32 instdone
[I915_NUM_RINGS
];
280 u32 acthd
[I915_NUM_RINGS
];
281 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
282 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
283 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
284 /* our own tracking of ring head and tail */
285 u32 cpu_ring_head
[I915_NUM_RINGS
];
286 u32 cpu_ring_tail
[I915_NUM_RINGS
];
287 u32 error
; /* gen6+ */
288 u32 err_int
; /* gen7 */
289 u32 instpm
[I915_NUM_RINGS
];
290 u32 instps
[I915_NUM_RINGS
];
291 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
292 u32 seqno
[I915_NUM_RINGS
];
294 u32 fault_reg
[I915_NUM_RINGS
];
296 u32 faddr
[I915_NUM_RINGS
];
297 u64 fence
[I915_MAX_NUM_FENCES
];
299 struct drm_i915_error_ring
{
300 struct drm_i915_error_object
{
304 } *ringbuffer
, *batchbuffer
, *ctx
;
305 struct drm_i915_error_request
{
311 } ring
[I915_NUM_RINGS
];
312 struct drm_i915_error_buffer
{
319 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
326 } *active_bo
, *pinned_bo
;
327 u32 active_bo_count
, pinned_bo_count
;
328 struct intel_overlay_error_state
*overlay
;
329 struct intel_display_error_state
*display
;
332 struct intel_crtc_config
;
337 struct drm_i915_display_funcs
{
338 bool (*fbc_enabled
)(struct drm_device
*dev
);
339 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
340 void (*disable_fbc
)(struct drm_device
*dev
);
341 int (*get_display_clock_speed
)(struct drm_device
*dev
);
342 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
344 * find_dpll() - Find the best values for the PLL
345 * @limit: limits for the PLL
346 * @crtc: current CRTC
347 * @target: target frequency in kHz
348 * @refclk: reference clock frequency in kHz
349 * @match_clock: if provided, @best_clock P divider must
350 * match the P divider from @match_clock
351 * used for LVDS downclocking
352 * @best_clock: best PLL values found
354 * Returns true on success, false on failure.
356 bool (*find_dpll
)(const struct intel_limit
*limit
,
357 struct drm_crtc
*crtc
,
358 int target
, int refclk
,
359 struct dpll
*match_clock
,
360 struct dpll
*best_clock
);
361 void (*update_wm
)(struct drm_device
*dev
);
362 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
363 uint32_t sprite_width
, int pixel_size
,
365 void (*modeset_global_resources
)(struct drm_device
*dev
);
366 /* Returns the active state of the crtc, and if the crtc is active,
367 * fills out the pipe-config with the hw state. */
368 bool (*get_pipe_config
)(struct intel_crtc
*,
369 struct intel_crtc_config
*);
370 void (*get_clock
)(struct intel_crtc
*, struct intel_crtc_config
*);
371 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
373 struct drm_framebuffer
*old_fb
);
374 void (*crtc_enable
)(struct drm_crtc
*crtc
);
375 void (*crtc_disable
)(struct drm_crtc
*crtc
);
376 void (*off
)(struct drm_crtc
*crtc
);
377 void (*write_eld
)(struct drm_connector
*connector
,
378 struct drm_crtc
*crtc
);
379 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
380 void (*init_clock_gating
)(struct drm_device
*dev
);
381 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
382 struct drm_framebuffer
*fb
,
383 struct drm_i915_gem_object
*obj
);
384 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
386 void (*hpd_irq_setup
)(struct drm_device
*dev
);
387 /* clock updates for mode set */
389 /* render clock increase/decrease */
390 /* display clock increase/decrease */
391 /* pll clock increase/decrease */
394 struct drm_i915_gt_funcs
{
395 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
396 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
399 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
400 func(is_mobile) sep \
403 func(is_i945gm) sep \
405 func(need_gfx_hws) sep \
407 func(is_pineview) sep \
408 func(is_broadwater) sep \
409 func(is_crestline) sep \
410 func(is_ivybridge) sep \
411 func(is_valleyview) sep \
412 func(is_haswell) sep \
413 func(has_force_wake) sep \
415 func(has_pipe_cxsr) sep \
416 func(has_hotplug) sep \
417 func(cursor_needs_physical) sep \
418 func(has_overlay) sep \
419 func(overlay_needs_physical) sep \
420 func(supports_tv) sep \
421 func(has_bsd_ring) sep \
422 func(has_blt_ring) sep \
423 func(has_vebox_ring) sep \
428 #define DEFINE_FLAG(name) u8 name:1
429 #define SEP_SEMICOLON ;
431 struct intel_device_info
{
432 u32 display_mmio_offset
;
435 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
441 enum i915_cache_level
{
444 I915_CACHE_LLC_MLC
, /* gen6+, in docs at least! */
447 typedef uint32_t gen6_gtt_pte_t
;
449 struct i915_address_space
{
451 struct drm_device
*dev
;
452 struct list_head global_link
;
453 unsigned long start
; /* Start offset always 0 for dri2 */
454 size_t total
; /* size addr space maps (ex. 2GB for ggtt) */
462 * List of objects currently involved in rendering.
464 * Includes buffers having the contents of their GPU caches
465 * flushed, not necessarily primitives. last_rendering_seqno
466 * represents when the rendering involved will be completed.
468 * A reference is held on the buffer while on this list.
470 struct list_head active_list
;
473 * LRU list of objects which are not in the ringbuffer and
474 * are ready to unbind, but are still in the GTT.
476 * last_rendering_seqno is 0 while an object is in this list.
478 * A reference is not held on the buffer while on this list,
479 * as merely being GTT-bound shouldn't prevent its being
480 * freed, and we'll pull it off the list in the free path.
482 struct list_head inactive_list
;
484 /* FIXME: Need a more generic return type */
485 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
486 enum i915_cache_level level
);
487 void (*clear_range
)(struct i915_address_space
*vm
,
488 unsigned int first_entry
,
489 unsigned int num_entries
);
490 void (*insert_entries
)(struct i915_address_space
*vm
,
492 unsigned int first_entry
,
493 enum i915_cache_level cache_level
);
494 void (*cleanup
)(struct i915_address_space
*vm
);
497 /* The Graphics Translation Table is the way in which GEN hardware translates a
498 * Graphics Virtual Address into a Physical Address. In addition to the normal
499 * collateral associated with any va->pa translations GEN hardware also has a
500 * portion of the GTT which can be mapped by the CPU and remain both coherent
501 * and correct (in cases like swizzling). That region is referred to as GMADR in
505 struct i915_address_space base
;
506 size_t stolen_size
; /* Total size of stolen memory */
508 unsigned long mappable_end
; /* End offset that we can CPU map */
509 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
510 phys_addr_t mappable_base
; /* PA of our GMADR */
512 /** "Graphics Stolen Memory" holds the global PTEs */
520 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
521 size_t *stolen
, phys_addr_t
*mappable_base
,
522 unsigned long *mappable_end
);
524 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
526 struct i915_hw_ppgtt
{
527 struct i915_address_space base
;
528 unsigned num_pd_entries
;
529 struct page
**pt_pages
;
531 dma_addr_t
*pt_dma_addr
;
533 int (*enable
)(struct drm_device
*dev
);
536 /* To make things as simple as possible (ie. no refcounting), a VMA's lifetime
537 * will always be <= an objects lifetime. So object refcounting should cover us.
540 struct drm_mm_node node
;
541 struct drm_i915_gem_object
*obj
;
542 struct i915_address_space
*vm
;
544 struct list_head vma_link
; /* Link in the object's VMA list */
547 struct i915_ctx_hang_stats
{
548 /* This context had batch pending when hang was declared */
549 unsigned batch_pending
;
551 /* This context had batch active when hang was declared */
552 unsigned batch_active
;
555 /* This must match up with the value previously used for execbuf2.rsvd1. */
556 #define DEFAULT_CONTEXT_ID 0
557 struct i915_hw_context
{
561 struct drm_i915_file_private
*file_priv
;
562 struct intel_ring_buffer
*ring
;
563 struct drm_i915_gem_object
*obj
;
564 struct i915_ctx_hang_stats hang_stats
;
573 struct drm_mm_node
*compressed_fb
;
574 struct drm_mm_node
*compressed_llb
;
576 struct intel_fbc_work
{
577 struct delayed_work work
;
578 struct drm_crtc
*crtc
;
579 struct drm_framebuffer
*fb
;
584 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
585 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
586 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
587 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
588 FBC_BAD_PLANE
, /* fbc not supported on plane */
589 FBC_NOT_TILED
, /* buffer not tiled */
590 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
592 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
598 PCH_NONE
= 0, /* No PCH present */
599 PCH_IBX
, /* Ibexpeak PCH */
600 PCH_CPT
, /* Cougarpoint PCH */
601 PCH_LPT
, /* Lynxpoint PCH */
605 enum intel_sbi_destination
{
610 #define QUIRK_PIPEA_FORCE (1<<0)
611 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
612 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
615 struct intel_fbc_work
;
618 struct i2c_adapter adapter
;
622 struct i2c_algo_bit_data bit_algo
;
623 struct drm_i915_private
*dev_priv
;
626 struct i915_suspend_saved_registers
{
647 u32 saveTRANS_HTOTAL_A
;
648 u32 saveTRANS_HBLANK_A
;
649 u32 saveTRANS_HSYNC_A
;
650 u32 saveTRANS_VTOTAL_A
;
651 u32 saveTRANS_VBLANK_A
;
652 u32 saveTRANS_VSYNC_A
;
660 u32 savePFIT_PGM_RATIOS
;
661 u32 saveBLC_HIST_CTL
;
663 u32 saveBLC_PWM_CTL2
;
664 u32 saveBLC_CPU_PWM_CTL
;
665 u32 saveBLC_CPU_PWM_CTL2
;
678 u32 saveTRANS_HTOTAL_B
;
679 u32 saveTRANS_HBLANK_B
;
680 u32 saveTRANS_HSYNC_B
;
681 u32 saveTRANS_VTOTAL_B
;
682 u32 saveTRANS_VBLANK_B
;
683 u32 saveTRANS_VSYNC_B
;
697 u32 savePP_ON_DELAYS
;
698 u32 savePP_OFF_DELAYS
;
706 u32 savePFIT_CONTROL
;
707 u32 save_palette_a
[256];
708 u32 save_palette_b
[256];
709 u32 saveDPFC_CB_BASE
;
710 u32 saveFBC_CFB_BASE
;
713 u32 saveFBC_CONTROL2
;
723 u32 saveCACHE_MODE_0
;
724 u32 saveMI_ARB_STATE
;
735 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
746 u32 savePIPEA_GMCH_DATA_M
;
747 u32 savePIPEB_GMCH_DATA_M
;
748 u32 savePIPEA_GMCH_DATA_N
;
749 u32 savePIPEB_GMCH_DATA_N
;
750 u32 savePIPEA_DP_LINK_M
;
751 u32 savePIPEB_DP_LINK_M
;
752 u32 savePIPEA_DP_LINK_N
;
753 u32 savePIPEB_DP_LINK_N
;
764 u32 savePCH_DREF_CONTROL
;
765 u32 saveDISP_ARB_CTL
;
766 u32 savePIPEA_DATA_M1
;
767 u32 savePIPEA_DATA_N1
;
768 u32 savePIPEA_LINK_M1
;
769 u32 savePIPEA_LINK_N1
;
770 u32 savePIPEB_DATA_M1
;
771 u32 savePIPEB_DATA_N1
;
772 u32 savePIPEB_LINK_M1
;
773 u32 savePIPEB_LINK_N1
;
774 u32 saveMCHBAR_RENDER_STANDBY
;
775 u32 savePCH_PORT_HOTPLUG
;
778 struct intel_gen6_power_mgmt
{
779 /* work and pm_iir are protected by dev_priv->irq_lock */
780 struct work_struct work
;
783 /* On vlv we need to manually drop to Vmin with a delayed work. */
784 struct delayed_work vlv_work
;
786 /* The below variables an all the rps hw state are protected by
787 * dev->struct mutext. */
794 struct delayed_work delayed_resume_work
;
797 * Protects RPS/RC6 register access and PCU communication.
798 * Must be taken after struct_mutex if nested.
800 struct mutex hw_lock
;
803 /* defined intel_pm.c */
804 extern spinlock_t mchdev_lock
;
806 struct intel_ilk_power_mgmt
{
814 unsigned long last_time1
;
815 unsigned long chipset_power
;
817 struct timespec last_time2
;
818 unsigned long gfx_power
;
824 struct drm_i915_gem_object
*pwrctx
;
825 struct drm_i915_gem_object
*renderctx
;
828 /* Power well structure for haswell */
829 struct i915_power_well
{
830 struct drm_device
*device
;
832 /* power well enable/disable usage count */
837 struct i915_dri1_state
{
838 unsigned allow_batchbuffer
: 1;
839 u32 __iomem
*gfx_hws_cpu_addr
;
850 struct i915_ums_state
{
852 * Flag if the X Server, and thus DRM, is not currently in
853 * control of the device.
855 * This is set between LeaveVT and EnterVT. It needs to be
856 * replaced with a semaphore. It also needs to be
857 * transitioned away from for kernel modesetting.
862 struct intel_l3_parity
{
864 struct work_struct error_work
;
868 /** Memory allocator for GTT stolen memory */
869 struct drm_mm stolen
;
870 /** List of all objects in gtt_space. Used to restore gtt
871 * mappings on resume */
872 struct list_head bound_list
;
874 * List of objects which are not bound to the GTT (thus
875 * are idle and not used by the GPU) but still have
876 * (presumably uncached) pages still attached.
878 struct list_head unbound_list
;
880 /** Usable portion of the GTT for GEM */
881 unsigned long stolen_base
; /* limited to low memory (32-bit) */
883 /** PPGTT used for aliasing the PPGTT with the GTT */
884 struct i915_hw_ppgtt
*aliasing_ppgtt
;
886 struct shrinker inactive_shrinker
;
887 bool shrinker_no_lock_stealing
;
889 /** LRU list of objects with fence regs on them. */
890 struct list_head fence_list
;
893 * We leave the user IRQ off as much as possible,
894 * but this means that requests will finish and never
895 * be retired once the system goes idle. Set a timer to
896 * fire periodically while the ring is running. When it
897 * fires, go retire requests.
899 struct delayed_work retire_work
;
902 * Are we in a non-interruptible section of code like
907 /** Bit 6 swizzling required for X tiling */
908 uint32_t bit_6_swizzle_x
;
909 /** Bit 6 swizzling required for Y tiling */
910 uint32_t bit_6_swizzle_y
;
912 /* storage for physical objects */
913 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
915 /* accounting, useful for userland debugging */
916 size_t object_memory
;
920 struct drm_i915_error_state_buf
{
929 struct i915_error_state_file_priv
{
930 struct drm_device
*dev
;
931 struct drm_i915_error_state
*error
;
934 struct i915_gpu_error
{
935 /* For hangcheck timer */
936 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
937 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
938 struct timer_list hangcheck_timer
;
940 /* For reset and error_state handling. */
942 /* Protected by the above dev->gpu_error.lock. */
943 struct drm_i915_error_state
*first_error
;
944 struct work_struct work
;
946 unsigned long last_reset
;
949 * State variable and reset counter controlling the reset flow
951 * Upper bits are for the reset counter. This counter is used by the
952 * wait_seqno code to race-free noticed that a reset event happened and
953 * that it needs to restart the entire ioctl (since most likely the
954 * seqno it waited for won't ever signal anytime soon).
956 * This is important for lock-free wait paths, where no contended lock
957 * naturally enforces the correct ordering between the bail-out of the
958 * waiter and the gpu reset work code.
960 * Lowest bit controls the reset state machine: Set means a reset is in
961 * progress. This state will (presuming we don't have any bugs) decay
962 * into either unset (successful reset) or the special WEDGED value (hw
963 * terminally sour). All waiters on the reset_queue will be woken when
966 atomic_t reset_counter
;
969 * Special values/flags for reset_counter
971 * Note that the code relies on
972 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
975 #define I915_RESET_IN_PROGRESS_FLAG 1
976 #define I915_WEDGED 0xffffffff
979 * Waitqueue to signal when the reset has completed. Used by clients
980 * that wait for dev_priv->mm.wedged to settle.
982 wait_queue_head_t reset_queue
;
984 /* For gpu hang simulation. */
985 unsigned int stop_rings
;
988 enum modeset_restore
{
994 struct intel_vbt_data
{
995 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
996 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
999 unsigned int int_tv_support
:1;
1000 unsigned int lvds_dither
:1;
1001 unsigned int lvds_vbt
:1;
1002 unsigned int int_crt_support
:1;
1003 unsigned int lvds_use_ssc
:1;
1004 unsigned int display_clock_mode
:1;
1005 unsigned int fdi_rx_polarity_inverted
:1;
1007 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1012 int edp_preemphasis
;
1014 bool edp_initialized
;
1017 struct edp_power_seq edp_pps
;
1022 struct child_device_config
*child_dev
;
1025 typedef struct drm_i915_private
{
1026 struct drm_device
*dev
;
1027 struct kmem_cache
*slab
;
1029 const struct intel_device_info
*info
;
1031 int relative_constants_mode
;
1035 struct drm_i915_gt_funcs gt
;
1036 /** gt_fifo_count and the subsequent register write are synchronized
1037 * with dev->struct_mutex. */
1038 unsigned gt_fifo_count
;
1039 /** forcewake_count is protected by gt_lock */
1040 unsigned forcewake_count
;
1041 /** gt_lock is also taken in irq contexts. */
1044 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1047 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1048 * controller on different i2c buses. */
1049 struct mutex gmbus_mutex
;
1052 * Base address of the gmbus and gpio block.
1054 uint32_t gpio_mmio_base
;
1056 wait_queue_head_t gmbus_wait_queue
;
1058 struct pci_dev
*bridge_dev
;
1059 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1060 uint32_t last_seqno
, next_seqno
;
1062 drm_dma_handle_t
*status_page_dmah
;
1063 struct resource mch_res
;
1065 atomic_t irq_received
;
1067 /* protects the irq masks */
1068 spinlock_t irq_lock
;
1070 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1071 struct pm_qos_request pm_qos
;
1073 /* DPIO indirect register protection */
1074 struct mutex dpio_lock
;
1076 /** Cached value of IMR to avoid reads in updating the bitfield */
1080 struct work_struct hotplug_work
;
1081 bool enable_hotplug_processing
;
1083 unsigned long hpd_last_jiffies
;
1088 HPD_MARK_DISABLED
= 2
1090 } hpd_stats
[HPD_NUM_PINS
];
1092 struct timer_list hotplug_reenable_timer
;
1096 struct i915_fbc fbc
;
1097 struct intel_opregion opregion
;
1098 struct intel_vbt_data vbt
;
1101 struct intel_overlay
*overlay
;
1102 unsigned int sprite_scaling_enabled
;
1108 spinlock_t lock
; /* bl registers and the above bl fields */
1109 struct backlight_device
*device
;
1113 bool no_aux_handshake
;
1115 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1116 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1117 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1119 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1121 struct workqueue_struct
*wq
;
1123 /* Display functions */
1124 struct drm_i915_display_funcs display
;
1126 /* PCH chipset type */
1127 enum intel_pch pch_type
;
1128 unsigned short pch_id
;
1130 unsigned long quirks
;
1132 enum modeset_restore modeset_restore
;
1133 struct mutex modeset_restore_lock
;
1135 struct list_head vm_list
; /* Global list of all address spaces */
1136 struct i915_gtt gtt
; /* VMA representing the global address space */
1138 struct i915_gem_mm mm
;
1140 /* Kernel Modesetting */
1142 struct sdvo_device_mapping sdvo_mappings
[2];
1144 struct drm_crtc
*plane_to_crtc_mapping
[3];
1145 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1146 wait_queue_head_t pending_flip_queue
;
1148 int num_shared_dpll
;
1149 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1150 struct intel_ddi_plls ddi_plls
;
1152 /* Reclocking support */
1153 bool render_reclock_avail
;
1154 bool lvds_downclock_avail
;
1155 /* indicates the reduced downclock for LVDS*/
1159 bool mchbar_need_disable
;
1161 struct intel_l3_parity l3_parity
;
1163 /* Cannot be determined by PCIID. You must always read a register. */
1166 /* gen6+ rps state */
1167 struct intel_gen6_power_mgmt rps
;
1169 /* ilk-only ips/rps state. Everything in here is protected by the global
1170 * mchdev_lock in intel_pm.c */
1171 struct intel_ilk_power_mgmt ips
;
1173 /* Haswell power well */
1174 struct i915_power_well power_well
;
1176 struct i915_gpu_error gpu_error
;
1178 struct drm_i915_gem_object
*vlv_pctx
;
1180 /* list of fbdev register on this device */
1181 struct intel_fbdev
*fbdev
;
1184 * The console may be contended at resume, but we don't
1185 * want it to block on it.
1187 struct work_struct console_resume_work
;
1189 struct drm_property
*broadcast_rgb_property
;
1190 struct drm_property
*force_audio_property
;
1192 bool hw_contexts_disabled
;
1193 uint32_t hw_context_size
;
1197 struct i915_suspend_saved_registers regfile
;
1199 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1201 struct i915_dri1_state dri1
;
1202 /* Old ums support infrastructure, same warning applies. */
1203 struct i915_ums_state ums
;
1204 } drm_i915_private_t
;
1206 /* Iterate over initialised rings */
1207 #define for_each_ring(ring__, dev_priv__, i__) \
1208 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1209 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1211 enum hdmi_force_audio
{
1212 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1213 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1214 HDMI_AUDIO_AUTO
, /* trust EDID */
1215 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1218 #define I915_GTT_OFFSET_NONE ((u32)-1)
1220 struct drm_i915_gem_object_ops
{
1221 /* Interface between the GEM object and its backing storage.
1222 * get_pages() is called once prior to the use of the associated set
1223 * of pages before to binding them into the GTT, and put_pages() is
1224 * called after we no longer need them. As we expect there to be
1225 * associated cost with migrating pages between the backing storage
1226 * and making them available for the GPU (e.g. clflush), we may hold
1227 * onto the pages after they are no longer referenced by the GPU
1228 * in case they may be used again shortly (for example migrating the
1229 * pages to a different memory domain within the GTT). put_pages()
1230 * will therefore most likely be called when the object itself is
1231 * being released or under memory pressure (where we attempt to
1232 * reap pages for the shrinker).
1234 int (*get_pages
)(struct drm_i915_gem_object
*);
1235 void (*put_pages
)(struct drm_i915_gem_object
*);
1238 struct drm_i915_gem_object
{
1239 struct drm_gem_object base
;
1241 const struct drm_i915_gem_object_ops
*ops
;
1243 /** List of VMAs backed by this object */
1244 struct list_head vma_list
;
1246 /** Stolen memory for this object, instead of being backed by shmem. */
1247 struct drm_mm_node
*stolen
;
1248 struct list_head global_list
;
1250 /** This object's place on the active/inactive lists */
1251 struct list_head ring_list
;
1252 struct list_head mm_list
;
1253 /** This object's place in the batchbuffer or on the eviction list */
1254 struct list_head exec_list
;
1257 * This is set if the object is on the active lists (has pending
1258 * rendering and so a non-zero seqno), and is not set if it i s on
1259 * inactive (ready to be unbound) list.
1261 unsigned int active
:1;
1264 * This is set if the object has been written to since last bound
1267 unsigned int dirty
:1;
1270 * Fence register bits (if any) for this object. Will be set
1271 * as needed when mapped into the GTT.
1272 * Protected by dev->struct_mutex.
1274 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1277 * Advice: are the backing pages purgeable?
1279 unsigned int madv
:2;
1282 * Current tiling mode for the object.
1284 unsigned int tiling_mode
:2;
1286 * Whether the tiling parameters for the currently associated fence
1287 * register have changed. Note that for the purposes of tracking
1288 * tiling changes we also treat the unfenced register, the register
1289 * slot that the object occupies whilst it executes a fenced
1290 * command (such as BLT on gen2/3), as a "fence".
1292 unsigned int fence_dirty
:1;
1294 /** How many users have pinned this object in GTT space. The following
1295 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1296 * (via user_pin_count), execbuffer (objects are not allowed multiple
1297 * times for the same batchbuffer), and the framebuffer code. When
1298 * switching/pageflipping, the framebuffer code has at most two buffers
1301 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1302 * bits with absolutely no headroom. So use 4 bits. */
1303 unsigned int pin_count
:4;
1304 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1307 * Is the object at the current location in the gtt mappable and
1308 * fenceable? Used to avoid costly recalculations.
1310 unsigned int map_and_fenceable
:1;
1313 * Whether the current gtt mapping needs to be mappable (and isn't just
1314 * mappable by accident). Track pin and fault separate for a more
1315 * accurate mappable working set.
1317 unsigned int fault_mappable
:1;
1318 unsigned int pin_mappable
:1;
1321 * Is the GPU currently using a fence to access this buffer,
1323 unsigned int pending_fenced_gpu_access
:1;
1324 unsigned int fenced_gpu_access
:1;
1326 unsigned int cache_level
:2;
1328 unsigned int has_aliasing_ppgtt_mapping
:1;
1329 unsigned int has_global_gtt_mapping
:1;
1330 unsigned int has_dma_mapping
:1;
1332 struct sg_table
*pages
;
1333 int pages_pin_count
;
1335 /* prime dma-buf support */
1336 void *dma_buf_vmapping
;
1340 * Used for performing relocations during execbuffer insertion.
1342 struct hlist_node exec_node
;
1343 unsigned long exec_handle
;
1344 struct drm_i915_gem_exec_object2
*exec_entry
;
1346 struct intel_ring_buffer
*ring
;
1348 /** Breadcrumb of last rendering to the buffer. */
1349 uint32_t last_read_seqno
;
1350 uint32_t last_write_seqno
;
1351 /** Breadcrumb of last fenced GPU access to the buffer. */
1352 uint32_t last_fenced_seqno
;
1354 /** Current tiling stride for the object, if it's tiled. */
1357 /** Record of address bit 17 of each page at last unbind. */
1358 unsigned long *bit_17
;
1360 /** User space pin count and filp owning the pin */
1361 uint32_t user_pin_count
;
1362 struct drm_file
*pin_filp
;
1364 /** for phy allocated objects */
1365 struct drm_i915_gem_phys_object
*phys_obj
;
1367 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1369 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1371 /* This is a temporary define to help transition us to real VMAs. If you see
1372 * this, you're either reviewing code, or bisecting it. */
1373 static inline struct i915_vma
*
1374 __i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
)
1376 if (list_empty(&obj
->vma_list
))
1378 return list_first_entry(&obj
->vma_list
, struct i915_vma
, vma_link
);
1381 /* Whether or not this object is currently mapped by the translation tables */
1383 i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*o
)
1385 struct i915_vma
*vma
= __i915_gem_obj_to_vma(o
);
1388 return drm_mm_node_allocated(&vma
->node
);
1391 /* Offset of the first PTE pointing to this object */
1392 static inline unsigned long
1393 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
1395 BUG_ON(list_empty(&o
->vma_list
));
1396 return __i915_gem_obj_to_vma(o
)->node
.start
;
1399 /* The size used in the translation tables may be larger than the actual size of
1400 * the object on GEN2/GEN3 because of the way tiling is handled. See
1401 * i915_gem_get_gtt_size() for more details.
1403 static inline unsigned long
1404 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*o
)
1406 BUG_ON(list_empty(&o
->vma_list
));
1407 return __i915_gem_obj_to_vma(o
)->node
.size
;
1411 i915_gem_obj_ggtt_set_color(struct drm_i915_gem_object
*o
,
1412 enum i915_cache_level color
)
1414 __i915_gem_obj_to_vma(o
)->node
.color
= color
;
1418 * Request queue structure.
1420 * The request queue allows us to note sequence numbers that have been emitted
1421 * and may be associated with active buffers to be retired.
1423 * By keeping this list, we can avoid having to do questionable
1424 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1425 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1427 struct drm_i915_gem_request
{
1428 /** On Which ring this request was generated */
1429 struct intel_ring_buffer
*ring
;
1431 /** GEM sequence number associated with this request. */
1434 /** Position in the ringbuffer of the start of the request */
1437 /** Position in the ringbuffer of the end of the request */
1440 /** Context related to this request */
1441 struct i915_hw_context
*ctx
;
1443 /** Batch buffer related to this request if any */
1444 struct drm_i915_gem_object
*batch_obj
;
1446 /** Time at which this request was emitted, in jiffies. */
1447 unsigned long emitted_jiffies
;
1449 /** global list entry for this request */
1450 struct list_head list
;
1452 struct drm_i915_file_private
*file_priv
;
1453 /** file_priv list entry for this request */
1454 struct list_head client_list
;
1457 struct drm_i915_file_private
{
1460 struct list_head request_list
;
1462 struct idr context_idr
;
1464 struct i915_ctx_hang_stats hang_stats
;
1467 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1469 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1470 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1471 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1472 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1473 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1474 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1475 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1476 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1477 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1478 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1479 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1480 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1481 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1482 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1483 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1484 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1485 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1486 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1487 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1488 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1489 (dev)->pci_device == 0x0152 || \
1490 (dev)->pci_device == 0x015a)
1491 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1492 (dev)->pci_device == 0x0106 || \
1493 (dev)->pci_device == 0x010A)
1494 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1495 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1496 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1497 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1498 ((dev)->pci_device & 0xFF00) == 0x0A00)
1501 * The genX designation typically refers to the render engine, so render
1502 * capability related checks should use IS_GEN, while display and other checks
1503 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1506 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1507 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1508 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1509 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1510 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1511 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1513 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1514 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1515 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1516 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1517 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1519 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1520 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1522 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1523 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1525 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1526 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1528 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1529 * rows, which changed the alignment requirements and fence programming.
1531 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1533 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1534 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1535 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1536 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1537 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1538 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1539 /* dsparb controlled by hw only */
1540 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1542 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1543 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1544 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1546 #define HAS_IPS(dev) (IS_ULT(dev))
1548 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1550 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1551 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1552 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1554 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1555 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1556 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1557 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1558 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1559 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1561 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1562 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1563 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1564 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1565 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1566 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1568 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1570 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1572 #define GT_FREQUENCY_MULTIPLIER 50
1574 #include "i915_trace.h"
1577 * RC6 is a special power stage which allows the GPU to enter an very
1578 * low-voltage mode when idle, using down to 0V while at this stage. This
1579 * stage is entered automatically when the GPU is idle when RC6 support is
1580 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1582 * There are different RC6 modes available in Intel GPU, which differentiate
1583 * among each other with the latency required to enter and leave RC6 and
1584 * voltage consumed by the GPU in different states.
1586 * The combination of the following flags define which states GPU is allowed
1587 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1588 * RC6pp is deepest RC6. Their support by hardware varies according to the
1589 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1590 * which brings the most power savings; deeper states save more power, but
1591 * require higher latency to switch to and wake up.
1593 #define INTEL_RC6_ENABLE (1<<0)
1594 #define INTEL_RC6p_ENABLE (1<<1)
1595 #define INTEL_RC6pp_ENABLE (1<<2)
1597 extern struct drm_ioctl_desc i915_ioctls
[];
1598 extern int i915_max_ioctl
;
1599 extern unsigned int i915_fbpercrtc __always_unused
;
1600 extern int i915_panel_ignore_lid __read_mostly
;
1601 extern unsigned int i915_powersave __read_mostly
;
1602 extern int i915_semaphores __read_mostly
;
1603 extern unsigned int i915_lvds_downclock __read_mostly
;
1604 extern int i915_lvds_channel_mode __read_mostly
;
1605 extern int i915_panel_use_ssc __read_mostly
;
1606 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1607 extern int i915_enable_rc6 __read_mostly
;
1608 extern int i915_enable_fbc __read_mostly
;
1609 extern bool i915_enable_hangcheck __read_mostly
;
1610 extern int i915_enable_ppgtt __read_mostly
;
1611 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1612 extern int i915_disable_power_well __read_mostly
;
1613 extern int i915_enable_ips __read_mostly
;
1614 extern bool i915_fastboot __read_mostly
;
1616 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1617 extern int i915_resume(struct drm_device
*dev
);
1618 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1619 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1622 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1623 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1624 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1625 extern int i915_driver_unload(struct drm_device
*);
1626 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1627 extern void i915_driver_lastclose(struct drm_device
* dev
);
1628 extern void i915_driver_preclose(struct drm_device
*dev
,
1629 struct drm_file
*file_priv
);
1630 extern void i915_driver_postclose(struct drm_device
*dev
,
1631 struct drm_file
*file_priv
);
1632 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1633 #ifdef CONFIG_COMPAT
1634 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1637 extern int i915_emit_box(struct drm_device
*dev
,
1638 struct drm_clip_rect
*box
,
1640 extern int intel_gpu_reset(struct drm_device
*dev
);
1641 extern int i915_reset(struct drm_device
*dev
);
1642 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1643 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1644 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1645 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1647 extern void intel_console_resume(struct work_struct
*work
);
1650 void i915_queue_hangcheck(struct drm_device
*dev
);
1651 void i915_hangcheck_elapsed(unsigned long data
);
1652 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1654 extern void intel_irq_init(struct drm_device
*dev
);
1655 extern void intel_hpd_init(struct drm_device
*dev
);
1656 extern void intel_gt_init(struct drm_device
*dev
);
1657 extern void intel_gt_reset(struct drm_device
*dev
);
1660 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1663 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1666 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1667 struct drm_file
*file_priv
);
1668 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1669 struct drm_file
*file_priv
);
1670 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1671 struct drm_file
*file_priv
);
1672 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1673 struct drm_file
*file_priv
);
1674 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1675 struct drm_file
*file_priv
);
1676 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1677 struct drm_file
*file_priv
);
1678 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1679 struct drm_file
*file_priv
);
1680 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1681 struct drm_file
*file_priv
);
1682 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1683 struct drm_file
*file_priv
);
1684 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1685 struct drm_file
*file_priv
);
1686 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1687 struct drm_file
*file_priv
);
1688 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1689 struct drm_file
*file_priv
);
1690 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1691 struct drm_file
*file_priv
);
1692 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1693 struct drm_file
*file
);
1694 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1695 struct drm_file
*file
);
1696 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1697 struct drm_file
*file_priv
);
1698 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1699 struct drm_file
*file_priv
);
1700 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1701 struct drm_file
*file_priv
);
1702 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1703 struct drm_file
*file_priv
);
1704 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1705 struct drm_file
*file_priv
);
1706 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1707 struct drm_file
*file_priv
);
1708 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1709 struct drm_file
*file_priv
);
1710 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1711 struct drm_file
*file_priv
);
1712 void i915_gem_load(struct drm_device
*dev
);
1713 void *i915_gem_object_alloc(struct drm_device
*dev
);
1714 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1715 int i915_gem_init_object(struct drm_gem_object
*obj
);
1716 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1717 const struct drm_i915_gem_object_ops
*ops
);
1718 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1720 void i915_gem_free_object(struct drm_gem_object
*obj
);
1721 struct i915_vma
*i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
1722 struct i915_address_space
*vm
);
1723 void i915_gem_vma_destroy(struct i915_vma
*vma
);
1725 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1727 bool map_and_fenceable
,
1729 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1730 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1731 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1732 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1733 void i915_gem_lastclose(struct drm_device
*dev
);
1735 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1736 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1738 struct sg_page_iter sg_iter
;
1740 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1741 return sg_page_iter_page(&sg_iter
);
1745 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1747 BUG_ON(obj
->pages
== NULL
);
1748 obj
->pages_pin_count
++;
1750 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1752 BUG_ON(obj
->pages_pin_count
== 0);
1753 obj
->pages_pin_count
--;
1756 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1757 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1758 struct intel_ring_buffer
*to
);
1759 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1760 struct intel_ring_buffer
*ring
);
1762 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1763 struct drm_device
*dev
,
1764 struct drm_mode_create_dumb
*args
);
1765 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1766 uint32_t handle
, uint64_t *offset
);
1767 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1770 * Returns true if seq1 is later than seq2.
1773 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1775 return (int32_t)(seq1
- seq2
) >= 0;
1778 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1779 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1780 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1781 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1784 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1786 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1787 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1788 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1795 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1797 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1798 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1799 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
1800 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1804 void i915_gem_retire_requests(struct drm_device
*dev
);
1805 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1806 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1807 bool interruptible
);
1808 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1810 return unlikely(atomic_read(&error
->reset_counter
)
1811 & I915_RESET_IN_PROGRESS_FLAG
);
1814 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1816 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1819 void i915_gem_reset(struct drm_device
*dev
);
1820 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1821 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1822 uint32_t read_domains
,
1823 uint32_t write_domain
);
1824 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1825 int __must_check
i915_gem_init(struct drm_device
*dev
);
1826 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1827 void i915_gem_l3_remap(struct drm_device
*dev
);
1828 void i915_gem_init_swizzling(struct drm_device
*dev
);
1829 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1830 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1831 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1832 int __i915_add_request(struct intel_ring_buffer
*ring
,
1833 struct drm_file
*file
,
1834 struct drm_i915_gem_object
*batch_obj
,
1836 #define i915_add_request(ring, seqno) \
1837 __i915_add_request(ring, NULL, NULL, seqno)
1838 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1840 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1842 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1845 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1847 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1849 struct intel_ring_buffer
*pipelined
);
1850 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1851 struct drm_i915_gem_object
*obj
,
1854 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1855 struct drm_i915_gem_object
*obj
);
1856 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1857 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1860 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
1862 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1863 int tiling_mode
, bool fenced
);
1865 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1866 enum i915_cache_level cache_level
);
1868 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1869 struct dma_buf
*dma_buf
);
1871 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1872 struct drm_gem_object
*gem_obj
, int flags
);
1874 /* i915_gem_context.c */
1875 void i915_gem_context_init(struct drm_device
*dev
);
1876 void i915_gem_context_fini(struct drm_device
*dev
);
1877 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1878 int i915_switch_context(struct intel_ring_buffer
*ring
,
1879 struct drm_file
*file
, int to_id
);
1880 void i915_gem_context_free(struct kref
*ctx_ref
);
1881 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
1883 kref_get(&ctx
->ref
);
1886 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
1888 kref_put(&ctx
->ref
, i915_gem_context_free
);
1891 struct i915_ctx_hang_stats
* __must_check
1892 i915_gem_context_get_hang_stats(struct drm_device
*dev
,
1893 struct drm_file
*file
,
1895 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1896 struct drm_file
*file
);
1897 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1898 struct drm_file
*file
);
1900 /* i915_gem_gtt.c */
1901 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1902 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1903 struct drm_i915_gem_object
*obj
,
1904 enum i915_cache_level cache_level
);
1905 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1906 struct drm_i915_gem_object
*obj
);
1908 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1909 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1910 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1911 enum i915_cache_level cache_level
);
1912 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1913 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1914 void i915_gem_init_global_gtt(struct drm_device
*dev
);
1915 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
1916 unsigned long mappable_end
, unsigned long end
);
1917 int i915_gem_gtt_init(struct drm_device
*dev
);
1918 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
1920 if (INTEL_INFO(dev
)->gen
< 6)
1921 intel_gtt_chipset_flush();
1925 /* i915_gem_evict.c */
1926 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1928 unsigned cache_level
,
1931 int i915_gem_evict_everything(struct drm_device
*dev
);
1933 /* i915_gem_stolen.c */
1934 int i915_gem_init_stolen(struct drm_device
*dev
);
1935 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
1936 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
1937 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1938 struct drm_i915_gem_object
*
1939 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
1940 struct drm_i915_gem_object
*
1941 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
1945 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
1947 /* i915_gem_tiling.c */
1948 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
1950 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
1952 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
1953 obj
->tiling_mode
!= I915_TILING_NONE
;
1956 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1957 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1958 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1960 /* i915_gem_debug.c */
1961 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1962 const char *where
, uint32_t mark
);
1964 int i915_verify_lists(struct drm_device
*dev
);
1966 #define i915_verify_lists(dev) 0
1968 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1970 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1971 const char *where
, uint32_t mark
);
1973 /* i915_debugfs.c */
1974 int i915_debugfs_init(struct drm_minor
*minor
);
1975 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1977 /* i915_gpu_error.c */
1979 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
1980 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
1981 const struct i915_error_state_file_priv
*error
);
1982 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
1983 size_t count
, loff_t pos
);
1984 static inline void i915_error_state_buf_release(
1985 struct drm_i915_error_state_buf
*eb
)
1989 void i915_capture_error_state(struct drm_device
*dev
);
1990 void i915_error_state_get(struct drm_device
*dev
,
1991 struct i915_error_state_file_priv
*error_priv
);
1992 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
1993 void i915_destroy_error_state(struct drm_device
*dev
);
1995 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
1996 const char *i915_cache_level_str(int type
);
1998 /* i915_suspend.c */
1999 extern int i915_save_state(struct drm_device
*dev
);
2000 extern int i915_restore_state(struct drm_device
*dev
);
2003 void i915_save_display_reg(struct drm_device
*dev
);
2004 void i915_restore_display_reg(struct drm_device
*dev
);
2007 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2008 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2011 extern int intel_setup_gmbus(struct drm_device
*dev
);
2012 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2013 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2015 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2018 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2019 struct drm_i915_private
*dev_priv
, unsigned port
);
2020 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2021 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2022 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2024 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2026 extern void intel_i2c_reset(struct drm_device
*dev
);
2028 /* intel_opregion.c */
2029 extern int intel_opregion_setup(struct drm_device
*dev
);
2031 extern void intel_opregion_init(struct drm_device
*dev
);
2032 extern void intel_opregion_fini(struct drm_device
*dev
);
2033 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2035 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2036 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2037 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2042 extern void intel_register_dsm_handler(void);
2043 extern void intel_unregister_dsm_handler(void);
2045 static inline void intel_register_dsm_handler(void) { return; }
2046 static inline void intel_unregister_dsm_handler(void) { return; }
2047 #endif /* CONFIG_ACPI */
2050 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2051 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2052 extern void intel_modeset_init(struct drm_device
*dev
);
2053 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2054 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2055 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2056 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2057 bool force_restore
);
2058 extern void i915_redisable_vga(struct drm_device
*dev
);
2059 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2060 extern void intel_disable_fbc(struct drm_device
*dev
);
2061 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2062 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2063 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2064 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2065 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2066 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2067 extern void intel_detect_pch(struct drm_device
*dev
);
2068 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2069 extern int intel_enable_rc6(const struct drm_device
*dev
);
2071 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2072 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2073 struct drm_file
*file
);
2076 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2077 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2078 struct intel_overlay_error_state
*error
);
2080 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2081 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2082 struct drm_device
*dev
,
2083 struct intel_display_error_state
*error
);
2085 /* On SNB platform, before reading ring registers forcewake bit
2086 * must be set to prevent GT core from power down and stale values being
2089 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
2090 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
2091 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
2093 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2094 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2096 /* intel_sideband.c */
2097 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2098 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2099 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2100 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, int reg
);
2101 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, int reg
, u32 val
);
2102 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2103 enum intel_sbi_destination destination
);
2104 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2105 enum intel_sbi_destination destination
);
2107 int vlv_gpu_freq(int ddr_freq
, int val
);
2108 int vlv_freq_opcode(int ddr_freq
, int val
);
2110 #define __i915_read(x, y) \
2111 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
2119 #define __i915_write(x, y) \
2120 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
2128 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
2129 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
2131 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
2132 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
2133 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
2134 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
2136 #define I915_READ(reg) i915_read32(dev_priv, (reg))
2137 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
2138 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
2139 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
2141 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
2142 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
2144 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2145 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2147 /* "Broadcast RGB" property */
2148 #define INTEL_BROADCAST_RGB_AUTO 0
2149 #define INTEL_BROADCAST_RGB_FULL 1
2150 #define INTEL_BROADCAST_RGB_LIMITED 2
2152 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2154 if (HAS_PCH_SPLIT(dev
))
2155 return CPU_VGACNTRL
;
2156 else if (IS_VALLEYVIEW(dev
))
2157 return VLV_VGACNTRL
;
2162 static inline void __user
*to_user_ptr(u64 address
)
2164 return (void __user
*)(uintptr_t)address
;
2167 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2169 unsigned long j
= msecs_to_jiffies(m
);
2171 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2174 static inline unsigned long
2175 timespec_to_jiffies_timeout(const struct timespec
*value
)
2177 unsigned long j
= timespec_to_jiffies(value
);
2179 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);