1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20170619"
84 #define DRIVER_TIMESTAMP 1497857498
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func
, int line
);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t
;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val
)
125 static inline uint_fixed_16_16_t
u32_to_fixed_16_16(uint32_t val
)
127 uint_fixed_16_16_t fp
;
135 static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp
)
137 return DIV_ROUND_UP(fp
.val
, 1 << 16);
140 static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp
)
145 static inline uint_fixed_16_16_t
min_fixed_16_16(uint_fixed_16_16_t min1
,
146 uint_fixed_16_16_t min2
)
148 uint_fixed_16_16_t min
;
150 min
.val
= min(min1
.val
, min2
.val
);
154 static inline uint_fixed_16_16_t
max_fixed_16_16(uint_fixed_16_16_t max1
,
155 uint_fixed_16_16_t max2
)
157 uint_fixed_16_16_t max
;
159 max
.val
= max(max1
.val
, max2
.val
);
163 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val
,
164 uint_fixed_16_16_t d
)
166 return DIV_ROUND_UP(val
.val
, d
.val
);
169 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val
,
170 uint_fixed_16_16_t mul
)
172 uint64_t intermediate_val
;
175 intermediate_val
= (uint64_t) val
* mul
.val
;
176 intermediate_val
= DIV_ROUND_UP_ULL(intermediate_val
, 1 << 16);
177 WARN_ON(intermediate_val
>> 32);
178 result
= clamp_t(uint32_t, intermediate_val
, 0, ~0);
182 static inline uint_fixed_16_16_t
mul_fixed16(uint_fixed_16_16_t val
,
183 uint_fixed_16_16_t mul
)
185 uint64_t intermediate_val
;
186 uint_fixed_16_16_t fp
;
188 intermediate_val
= (uint64_t) val
.val
* mul
.val
;
189 intermediate_val
= intermediate_val
>> 16;
190 WARN_ON(intermediate_val
>> 32);
191 fp
.val
= clamp_t(uint32_t, intermediate_val
, 0, ~0);
195 static inline uint_fixed_16_16_t
fixed_16_16_div(uint32_t val
, uint32_t d
)
197 uint_fixed_16_16_t fp
, res
;
199 fp
= u32_to_fixed_16_16(val
);
200 res
.val
= DIV_ROUND_UP(fp
.val
, d
);
204 static inline uint_fixed_16_16_t
fixed_16_16_div_u64(uint32_t val
, uint32_t d
)
206 uint_fixed_16_16_t res
;
209 interm_val
= (uint64_t)val
<< 16;
210 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
);
211 WARN_ON(interm_val
>> 32);
212 res
.val
= (uint32_t) interm_val
;
217 static inline uint32_t div_round_up_u32_fixed16(uint32_t val
,
218 uint_fixed_16_16_t d
)
222 interm_val
= (uint64_t)val
<< 16;
223 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
.val
);
224 WARN_ON(interm_val
>> 32);
225 return clamp_t(uint32_t, interm_val
, 0, ~0);
228 static inline uint_fixed_16_16_t
mul_u32_fixed_16_16(uint32_t val
,
229 uint_fixed_16_16_t mul
)
231 uint64_t intermediate_val
;
232 uint_fixed_16_16_t fp
;
234 intermediate_val
= (uint64_t) val
* mul
.val
;
235 WARN_ON(intermediate_val
>> 32);
236 fp
.val
= (uint32_t) intermediate_val
;
240 static inline const char *yesno(bool v
)
242 return v
? "yes" : "no";
245 static inline const char *onoff(bool v
)
247 return v
? "on" : "off";
250 static inline const char *enableddisabled(bool v
)
252 return v
? "enabled" : "disabled";
261 I915_MAX_PIPES
= _PIPE_EDP
263 #define pipe_name(p) ((p) + 'A')
275 static inline const char *transcoder_name(enum transcoder transcoder
)
277 switch (transcoder
) {
286 case TRANSCODER_DSI_A
:
288 case TRANSCODER_DSI_C
:
295 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
297 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
301 * Global legacy plane identifier. Valid only for primary/sprite
302 * planes on pre-g4x, and only for primary planes on g4x+.
309 #define plane_name(p) ((p) + 'A')
311 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
314 * Per-pipe plane identifier.
315 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
316 * number of planes per CRTC. Not all platforms really have this many planes,
317 * which means some arrays of size I915_MAX_PLANES may have unused entries
318 * between the topmost sprite plane and the cursor plane.
320 * This is expected to be passed to various register macros
321 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
332 #define for_each_plane_id_on_crtc(__crtc, __p) \
333 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
334 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
345 #define port_name(p) ((p) + 'A')
347 #define I915_NUM_PHYS_VLV 2
360 enum intel_display_power_domain
{
364 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
365 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
366 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
367 POWER_DOMAIN_TRANSCODER_A
,
368 POWER_DOMAIN_TRANSCODER_B
,
369 POWER_DOMAIN_TRANSCODER_C
,
370 POWER_DOMAIN_TRANSCODER_EDP
,
371 POWER_DOMAIN_TRANSCODER_DSI_A
,
372 POWER_DOMAIN_TRANSCODER_DSI_C
,
373 POWER_DOMAIN_PORT_DDI_A_LANES
,
374 POWER_DOMAIN_PORT_DDI_B_LANES
,
375 POWER_DOMAIN_PORT_DDI_C_LANES
,
376 POWER_DOMAIN_PORT_DDI_D_LANES
,
377 POWER_DOMAIN_PORT_DDI_E_LANES
,
378 POWER_DOMAIN_PORT_DDI_A_IO
,
379 POWER_DOMAIN_PORT_DDI_B_IO
,
380 POWER_DOMAIN_PORT_DDI_C_IO
,
381 POWER_DOMAIN_PORT_DDI_D_IO
,
382 POWER_DOMAIN_PORT_DDI_E_IO
,
383 POWER_DOMAIN_PORT_DSI
,
384 POWER_DOMAIN_PORT_CRT
,
385 POWER_DOMAIN_PORT_OTHER
,
394 POWER_DOMAIN_MODESET
,
400 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
401 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
402 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
403 #define POWER_DOMAIN_TRANSCODER(tran) \
404 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
405 (tran) + POWER_DOMAIN_TRANSCODER_A)
409 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
421 #define for_each_hpd_pin(__pin) \
422 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
424 #define HPD_STORM_DEFAULT_THRESHOLD 5
426 struct i915_hotplug
{
427 struct work_struct hotplug_work
;
430 unsigned long last_jiffies
;
435 HPD_MARK_DISABLED
= 2
437 } stats
[HPD_NUM_PINS
];
439 struct delayed_work reenable_work
;
441 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
444 struct work_struct dig_port_work
;
446 struct work_struct poll_init_work
;
449 unsigned int hpd_storm_threshold
;
452 * if we get a HPD irq from DP and a HPD irq from non-DP
453 * the non-DP HPD could block the workqueue on a mode config
454 * mutex getting, that userspace may have taken. However
455 * userspace is waiting on the DP workqueue to run which is
456 * blocked behind the non-DP one.
458 struct workqueue_struct
*dp_wq
;
461 #define I915_GEM_GPU_DOMAINS \
462 (I915_GEM_DOMAIN_RENDER | \
463 I915_GEM_DOMAIN_SAMPLER | \
464 I915_GEM_DOMAIN_COMMAND | \
465 I915_GEM_DOMAIN_INSTRUCTION | \
466 I915_GEM_DOMAIN_VERTEX)
468 #define for_each_pipe(__dev_priv, __p) \
469 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
470 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
471 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
472 for_each_if ((__mask) & (1 << (__p)))
473 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
475 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
477 #define for_each_sprite(__dev_priv, __p, __s) \
479 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
482 #define for_each_port_masked(__port, __ports_mask) \
483 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
484 for_each_if ((__ports_mask) & (1 << (__port)))
486 #define for_each_crtc(dev, crtc) \
487 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
489 #define for_each_intel_plane(dev, intel_plane) \
490 list_for_each_entry(intel_plane, \
491 &(dev)->mode_config.plane_list, \
494 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
495 list_for_each_entry(intel_plane, \
496 &(dev)->mode_config.plane_list, \
498 for_each_if ((plane_mask) & \
499 (1 << drm_plane_index(&intel_plane->base)))
501 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
502 list_for_each_entry(intel_plane, \
503 &(dev)->mode_config.plane_list, \
505 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
507 #define for_each_intel_crtc(dev, intel_crtc) \
508 list_for_each_entry(intel_crtc, \
509 &(dev)->mode_config.crtc_list, \
512 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
513 list_for_each_entry(intel_crtc, \
514 &(dev)->mode_config.crtc_list, \
516 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
518 #define for_each_intel_encoder(dev, intel_encoder) \
519 list_for_each_entry(intel_encoder, \
520 &(dev)->mode_config.encoder_list, \
523 #define for_each_intel_connector_iter(intel_connector, iter) \
524 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
526 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
527 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
528 for_each_if ((intel_encoder)->base.crtc == (__crtc))
530 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
531 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
532 for_each_if ((intel_connector)->base.encoder == (__encoder))
534 #define for_each_power_domain(domain, mask) \
535 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
536 for_each_if (BIT_ULL(domain) & (mask))
538 #define for_each_power_well(__dev_priv, __power_well) \
539 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
540 (__power_well) - (__dev_priv)->power_domains.power_wells < \
541 (__dev_priv)->power_domains.power_well_count; \
544 #define for_each_power_well_rev(__dev_priv, __power_well) \
545 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
546 (__dev_priv)->power_domains.power_well_count - 1; \
547 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
550 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
551 for_each_power_well(__dev_priv, __power_well) \
552 for_each_if ((__power_well)->domains & (__domain_mask))
554 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
555 for_each_power_well_rev(__dev_priv, __power_well) \
556 for_each_if ((__power_well)->domains & (__domain_mask))
558 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
560 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
561 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
562 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
564 for_each_if (plane_state)
566 struct drm_i915_private
;
567 struct i915_mm_struct
;
568 struct i915_mmu_object
;
570 struct drm_i915_file_private
{
571 struct drm_i915_private
*dev_priv
;
572 struct drm_file
*file
;
576 struct list_head request_list
;
577 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
578 * chosen to prevent the CPU getting more than a frame ahead of the GPU
579 * (when using lax throttling for the frontbuffer). We also use it to
580 * offer free GPU waitboosts for severely congested workloads.
582 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
584 struct idr context_idr
;
586 struct intel_rps_client
{
590 unsigned int bsd_engine
;
592 /* Client can have a maximum of 3 contexts banned before
593 * it is denied of creating new contexts. As one context
594 * ban needs 4 consecutive hangs, and more if there is
595 * progress in between, this is a last resort stop gap measure
596 * to limit the badly behaving clients access to gpu.
598 #define I915_MAX_CLIENT_CONTEXT_BANS 3
602 /* Used by dp and fdi links */
603 struct intel_link_m_n
{
611 void intel_link_compute_m_n(int bpp
, int nlanes
,
612 int pixel_clock
, int link_clock
,
613 struct intel_link_m_n
*m_n
);
615 /* Interface history:
618 * 1.2: Add Power Management
619 * 1.3: Add vblank support
620 * 1.4: Fix cmdbuffer path, add heap destroy
621 * 1.5: Add vblank pipe configuration
622 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
623 * - Support vertical blank on secondary display pipe
625 #define DRIVER_MAJOR 1
626 #define DRIVER_MINOR 6
627 #define DRIVER_PATCHLEVEL 0
629 struct opregion_header
;
630 struct opregion_acpi
;
631 struct opregion_swsci
;
632 struct opregion_asle
;
634 struct intel_opregion
{
635 struct opregion_header
*header
;
636 struct opregion_acpi
*acpi
;
637 struct opregion_swsci
*swsci
;
638 u32 swsci_gbda_sub_functions
;
639 u32 swsci_sbcb_sub_functions
;
640 struct opregion_asle
*asle
;
645 struct work_struct asle_work
;
647 #define OPREGION_SIZE (8*1024)
649 struct intel_overlay
;
650 struct intel_overlay_error_state
;
652 struct sdvo_device_mapping
{
661 struct intel_connector
;
662 struct intel_encoder
;
663 struct intel_atomic_state
;
664 struct intel_crtc_state
;
665 struct intel_initial_plane_config
;
669 struct intel_cdclk_state
;
671 struct drm_i915_display_funcs
{
672 void (*get_cdclk
)(struct drm_i915_private
*dev_priv
,
673 struct intel_cdclk_state
*cdclk_state
);
674 void (*set_cdclk
)(struct drm_i915_private
*dev_priv
,
675 const struct intel_cdclk_state
*cdclk_state
);
676 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
677 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
678 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
679 struct intel_crtc
*intel_crtc
,
680 struct intel_crtc_state
*newstate
);
681 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
682 struct intel_crtc_state
*cstate
);
683 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
684 struct intel_crtc_state
*cstate
);
685 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
686 struct intel_crtc_state
*cstate
);
687 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
688 void (*update_wm
)(struct intel_crtc
*crtc
);
689 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
690 /* Returns the active state of the crtc, and if the crtc is active,
691 * fills out the pipe-config with the hw state. */
692 bool (*get_pipe_config
)(struct intel_crtc
*,
693 struct intel_crtc_state
*);
694 void (*get_initial_plane_config
)(struct intel_crtc
*,
695 struct intel_initial_plane_config
*);
696 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
697 struct intel_crtc_state
*crtc_state
);
698 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
699 struct drm_atomic_state
*old_state
);
700 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
701 struct drm_atomic_state
*old_state
);
702 void (*update_crtcs
)(struct drm_atomic_state
*state
,
703 unsigned int *crtc_vblank_mask
);
704 void (*audio_codec_enable
)(struct drm_connector
*connector
,
705 struct intel_encoder
*encoder
,
706 const struct drm_display_mode
*adjusted_mode
);
707 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
708 void (*fdi_link_train
)(struct intel_crtc
*crtc
,
709 const struct intel_crtc_state
*crtc_state
);
710 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
711 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
712 struct drm_framebuffer
*fb
,
713 struct drm_i915_gem_object
*obj
,
714 struct drm_i915_gem_request
*req
,
716 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
717 /* clock updates for mode set */
719 /* render clock increase/decrease */
720 /* display clock increase/decrease */
721 /* pll clock increase/decrease */
723 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
724 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
727 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
728 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
729 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
732 struct work_struct work
;
734 uint32_t *dmc_payload
;
735 uint32_t dmc_fw_size
;
738 i915_reg_t mmioaddr
[8];
739 uint32_t mmiodata
[8];
741 uint32_t allowed_dc_mask
;
744 #define DEV_INFO_FOR_EACH_FLAG(func) \
747 func(is_alpha_support); \
748 /* Keep has_* in alphabetical order */ \
749 func(has_64bit_reloc); \
750 func(has_aliasing_ppgtt); \
754 func(has_reset_engine); \
756 func(has_fpga_dbg); \
757 func(has_full_ppgtt); \
758 func(has_full_48bit_ppgtt); \
759 func(has_gmbus_irq); \
760 func(has_gmch_display); \
766 func(has_logical_ring_contexts); \
768 func(has_pipe_cxsr); \
769 func(has_pooled_eu); \
773 func(has_resource_streamer); \
774 func(has_runtime_pm); \
776 func(unfenced_needs_alignment); \
777 func(cursor_needs_physical); \
778 func(hws_needs_physical); \
779 func(overlay_needs_physical); \
782 struct sseu_dev_info
{
788 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
791 u8 has_subslice_pg
:1;
795 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
797 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
800 /* Keep in gen based order, and chronological order within a gen */
801 enum intel_platform
{
802 INTEL_PLATFORM_UNINITIALIZED
= 0,
833 struct intel_device_info
{
834 u32 display_mmio_offset
;
837 u8 num_sprites
[I915_MAX_PIPES
];
838 u8 num_scalers
[I915_MAX_PIPES
];
841 enum intel_platform platform
;
842 u8 ring_mask
; /* Rings supported by the HW */
844 #define DEFINE_FLAG(name) u8 name:1
845 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
847 u16 ddb_size
; /* in blocks */
848 /* Register offsets for the various display pipes and transcoders */
849 int pipe_offsets
[I915_MAX_TRANSCODERS
];
850 int trans_offsets
[I915_MAX_TRANSCODERS
];
851 int palette_offsets
[I915_MAX_PIPES
];
852 int cursor_offsets
[I915_MAX_PIPES
];
854 /* Slice/subslice/EU info */
855 struct sseu_dev_info sseu
;
858 u16 degamma_lut_size
;
863 struct intel_display_error_state
;
865 struct i915_gpu_state
{
868 struct timeval boottime
;
869 struct timeval uptime
;
871 struct drm_i915_private
*i915
;
881 struct intel_device_info device_info
;
882 struct i915_params params
;
884 /* Generic register state */
888 u32 gtier
[4], ngtier
;
892 u32 error
; /* gen6+ */
893 u32 err_int
; /* gen7 */
894 u32 fault_data0
; /* gen8, gen9 */
895 u32 fault_data1
; /* gen8, gen9 */
903 u64 fence
[I915_MAX_NUM_FENCES
];
904 struct intel_overlay_error_state
*overlay
;
905 struct intel_display_error_state
*display
;
906 struct drm_i915_error_object
*semaphore
;
907 struct drm_i915_error_object
*guc_log
;
909 struct drm_i915_error_engine
{
911 /* Software tracked state */
914 unsigned long hangcheck_timestamp
;
915 bool hangcheck_stalled
;
916 enum intel_engine_hangcheck_action hangcheck_action
;
917 struct i915_address_space
*vm
;
921 /* position of active request inside the ring */
922 u32 rq_head
, rq_post
, rq_tail
;
924 /* our own tracking of ring head and tail */
947 u32 rc_psmi
; /* sleep state */
948 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
949 struct intel_instdone instdone
;
951 struct drm_i915_error_context
{
952 char comm
[TASK_COMM_LEN
];
961 struct drm_i915_error_object
{
967 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
969 struct drm_i915_error_object
**user_bo
;
972 struct drm_i915_error_object
*wa_ctx
;
974 struct drm_i915_error_request
{
982 } *requests
, execlist
[2];
984 struct drm_i915_error_waiter
{
985 char comm
[TASK_COMM_LEN
];
997 } engine
[I915_NUM_ENGINES
];
999 struct drm_i915_error_buffer
{
1002 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
1006 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1013 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
1014 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
1015 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
1018 enum i915_cache_level
{
1019 I915_CACHE_NONE
= 0,
1020 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
1021 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
1022 caches, eg sampler/render caches, and the
1023 large Last-Level-Cache. LLC is coherent with
1024 the CPU, but L3 is only visible to the GPU. */
1025 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
1028 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1039 /* This is always the inner lock when overlapping with struct_mutex and
1040 * it's the outer lock when overlapping with stolen_lock. */
1043 unsigned int possible_framebuffer_bits
;
1044 unsigned int busy_bits
;
1045 unsigned int visible_pipes_mask
;
1046 struct intel_crtc
*crtc
;
1048 struct drm_mm_node compressed_fb
;
1049 struct drm_mm_node
*compressed_llb
;
1056 bool underrun_detected
;
1057 struct work_struct underrun_work
;
1059 struct intel_fbc_state_cache
{
1060 struct i915_vma
*vma
;
1063 unsigned int mode_flags
;
1064 uint32_t hsw_bdw_pixel_rate
;
1068 unsigned int rotation
;
1075 const struct drm_format_info
*format
;
1076 unsigned int stride
;
1080 struct intel_fbc_reg_params
{
1081 struct i915_vma
*vma
;
1086 unsigned int fence_y_offset
;
1090 const struct drm_format_info
*format
;
1091 unsigned int stride
;
1097 struct intel_fbc_work
{
1099 u32 scheduled_vblank
;
1100 struct work_struct work
;
1103 const char *no_fbc_reason
;
1107 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1108 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1109 * parsing for same resolution.
1111 enum drrs_refresh_rate_type
{
1114 DRRS_MAX_RR
, /* RR count */
1117 enum drrs_support_type
{
1118 DRRS_NOT_SUPPORTED
= 0,
1119 STATIC_DRRS_SUPPORT
= 1,
1120 SEAMLESS_DRRS_SUPPORT
= 2
1126 struct delayed_work work
;
1127 struct intel_dp
*dp
;
1128 unsigned busy_frontbuffer_bits
;
1129 enum drrs_refresh_rate_type refresh_rate_type
;
1130 enum drrs_support_type type
;
1137 struct intel_dp
*enabled
;
1139 struct delayed_work work
;
1140 unsigned busy_frontbuffer_bits
;
1142 bool aux_frame_sync
;
1144 bool y_cord_support
;
1145 bool colorimetry_support
;
1150 PCH_NONE
= 0, /* No PCH present */
1151 PCH_IBX
, /* Ibexpeak PCH */
1152 PCH_CPT
, /* Cougarpoint/Pantherpoint PCH */
1153 PCH_LPT
, /* Lynxpoint/Wildcatpoint PCH */
1154 PCH_SPT
, /* Sunrisepoint PCH */
1155 PCH_KBP
, /* Kabypoint PCH */
1156 PCH_CNP
, /* Cannonpoint PCH */
1160 enum intel_sbi_destination
{
1165 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1166 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1167 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1168 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1171 struct intel_fbc_work
;
1173 struct intel_gmbus
{
1174 struct i2c_adapter adapter
;
1175 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1178 i915_reg_t gpio_reg
;
1179 struct i2c_algo_bit_data bit_algo
;
1180 struct drm_i915_private
*dev_priv
;
1183 struct i915_suspend_saved_registers
{
1185 u32 saveFBC_CONTROL
;
1186 u32 saveCACHE_MODE_0
;
1187 u32 saveMI_ARB_STATE
;
1191 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1192 u32 savePCH_PORT_HOTPLUG
;
1196 struct vlv_s0ix_state
{
1203 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1204 u32 media_max_req_count
;
1205 u32 gfx_max_req_count
;
1231 u32 rp_down_timeout
;
1237 /* Display 1 CZ domain */
1242 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1244 /* GT SA CZ domain */
1251 /* Display 2 CZ domain */
1255 u32 clock_gate_dis2
;
1258 struct intel_rps_ei
{
1264 struct intel_gen6_power_mgmt
{
1266 * work, interrupts_enabled and pm_iir are protected by
1267 * dev_priv->irq_lock
1269 struct work_struct work
;
1270 bool interrupts_enabled
;
1273 /* PM interrupt bits that should never be masked */
1276 /* Frequencies are stored in potentially platform dependent multiples.
1277 * In other words, *_freq needs to be multiplied by X to be interesting.
1278 * Soft limits are those which are used for the dynamic reclocking done
1279 * by the driver (raise frequencies under heavy loads, and lower for
1280 * lighter loads). Hard limits are those imposed by the hardware.
1282 * A distinction is made for overclocking, which is never enabled by
1283 * default, and is considered to be above the hard limit if it's
1286 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1287 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1288 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1289 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1290 u8 min_freq
; /* AKA RPn. Minimum frequency */
1291 u8 boost_freq
; /* Frequency to request when wait boosting */
1292 u8 idle_freq
; /* Frequency to request when we are idle */
1293 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1294 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1295 u8 rp0_freq
; /* Non-overclocked max frequency. */
1296 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1298 u8 up_threshold
; /* Current %busy required to uplock */
1299 u8 down_threshold
; /* Current %busy required to downclock */
1302 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1305 struct delayed_work autoenable_work
;
1306 atomic_t num_waiters
;
1309 /* manual wa residency calculations */
1310 struct intel_rps_ei ei
;
1313 * Protects RPS/RC6 register access and PCU communication.
1314 * Must be taken after struct_mutex if nested. Note that
1315 * this lock may be held for long periods of time when
1316 * talking to hw - so only take it when talking to hw!
1318 struct mutex hw_lock
;
1321 /* defined intel_pm.c */
1322 extern spinlock_t mchdev_lock
;
1324 struct intel_ilk_power_mgmt
{
1332 unsigned long last_time1
;
1333 unsigned long chipset_power
;
1336 unsigned long gfx_power
;
1343 struct drm_i915_private
;
1344 struct i915_power_well
;
1346 struct i915_power_well_ops
{
1348 * Synchronize the well's hw state to match the current sw state, for
1349 * example enable/disable it based on the current refcount. Called
1350 * during driver init and resume time, possibly after first calling
1351 * the enable/disable handlers.
1353 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1354 struct i915_power_well
*power_well
);
1356 * Enable the well and resources that depend on it (for example
1357 * interrupts located on the well). Called after the 0->1 refcount
1360 void (*enable
)(struct drm_i915_private
*dev_priv
,
1361 struct i915_power_well
*power_well
);
1363 * Disable the well and resources that depend on it. Called after
1364 * the 1->0 refcount transition.
1366 void (*disable
)(struct drm_i915_private
*dev_priv
,
1367 struct i915_power_well
*power_well
);
1368 /* Returns the hw enabled state. */
1369 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1370 struct i915_power_well
*power_well
);
1373 /* Power well structure for haswell */
1374 struct i915_power_well
{
1377 /* power well enable/disable usage count */
1379 /* cached hw enabled state */
1382 /* unique identifier for this power well */
1385 * Arbitraty data associated with this power well. Platform and power
1389 const struct i915_power_well_ops
*ops
;
1392 struct i915_power_domains
{
1394 * Power wells needed for initialization at driver init and suspend
1395 * time are on. They are kept on until after the first modeset.
1399 int power_well_count
;
1402 int domain_use_count
[POWER_DOMAIN_NUM
];
1403 struct i915_power_well
*power_wells
;
1406 #define MAX_L3_SLICES 2
1407 struct intel_l3_parity
{
1408 u32
*remap_info
[MAX_L3_SLICES
];
1409 struct work_struct error_work
;
1413 struct i915_gem_mm
{
1414 /** Memory allocator for GTT stolen memory */
1415 struct drm_mm stolen
;
1416 /** Protects the usage of the GTT stolen memory allocator. This is
1417 * always the inner lock when overlapping with struct_mutex. */
1418 struct mutex stolen_lock
;
1420 /** List of all objects in gtt_space. Used to restore gtt
1421 * mappings on resume */
1422 struct list_head bound_list
;
1424 * List of objects which are not bound to the GTT (thus
1425 * are idle and not used by the GPU). These objects may or may
1426 * not actually have any pages attached.
1428 struct list_head unbound_list
;
1430 /** List of all objects in gtt_space, currently mmaped by userspace.
1431 * All objects within this list must also be on bound_list.
1433 struct list_head userfault_list
;
1436 * List of objects which are pending destruction.
1438 struct llist_head free_list
;
1439 struct work_struct free_work
;
1441 /** Usable portion of the GTT for GEM */
1442 dma_addr_t stolen_base
; /* limited to low memory (32-bit) */
1444 /** PPGTT used for aliasing the PPGTT with the GTT */
1445 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1447 struct notifier_block oom_notifier
;
1448 struct notifier_block vmap_notifier
;
1449 struct shrinker shrinker
;
1451 /** LRU list of objects with fence regs on them. */
1452 struct list_head fence_list
;
1455 * Workqueue to fault in userptr pages, flushed by the execbuf
1456 * when required but otherwise left to userspace to try again
1459 struct workqueue_struct
*userptr_wq
;
1461 u64 unordered_timeline
;
1463 /* the indicator for dispatch video commands on two BSD rings */
1464 atomic_t bsd_engine_dispatch_index
;
1466 /** Bit 6 swizzling required for X tiling */
1467 uint32_t bit_6_swizzle_x
;
1468 /** Bit 6 swizzling required for Y tiling */
1469 uint32_t bit_6_swizzle_y
;
1471 /* accounting, useful for userland debugging */
1472 spinlock_t object_stat_lock
;
1477 struct drm_i915_error_state_buf
{
1478 struct drm_i915_private
*i915
;
1487 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1488 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1490 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1491 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1493 struct i915_gpu_error
{
1494 /* For hangcheck timer */
1495 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1496 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1498 struct delayed_work hangcheck_work
;
1500 /* For reset and error_state handling. */
1502 /* Protected by the above dev->gpu_error.lock. */
1503 struct i915_gpu_state
*first_error
;
1505 unsigned long missed_irq_rings
;
1508 * State variable controlling the reset flow and count
1510 * This is a counter which gets incremented when reset is triggered,
1512 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1513 * meaning that any waiters holding onto the struct_mutex should
1514 * relinquish the lock immediately in order for the reset to start.
1516 * If reset is not completed succesfully, the I915_WEDGE bit is
1517 * set meaning that hardware is terminally sour and there is no
1518 * recovery. All waiters on the reset_queue will be woken when
1521 * This counter is used by the wait_seqno code to notice that reset
1522 * event happened and it needs to restart the entire ioctl (since most
1523 * likely the seqno it waited for won't ever signal anytime soon).
1525 * This is important for lock-free wait paths, where no contended lock
1526 * naturally enforces the correct ordering between the bail-out of the
1527 * waiter and the gpu reset work code.
1529 unsigned long reset_count
;
1532 * flags: Control various stages of the GPU reset
1534 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1535 * other users acquiring the struct_mutex. To do this we set the
1536 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1537 * and then check for that bit before acquiring the struct_mutex (in
1538 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1539 * secondary role in preventing two concurrent global reset attempts.
1541 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1542 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1543 * but it may be held by some long running waiter (that we cannot
1544 * interrupt without causing trouble). Once we are ready to do the GPU
1545 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1546 * they already hold the struct_mutex and want to participate they can
1547 * inspect the bit and do the reset directly, otherwise the worker
1548 * waits for the struct_mutex.
1550 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1551 * acquire the struct_mutex to reset an engine, we need an explicit
1552 * flag to prevent two concurrent reset attempts in the same engine.
1553 * As the number of engines continues to grow, allocate the flags from
1554 * the most significant bits.
1556 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1557 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1558 * i915_gem_request_alloc(), this bit is checked and the sequence
1559 * aborted (with -EIO reported to userspace) if set.
1561 unsigned long flags
;
1562 #define I915_RESET_BACKOFF 0
1563 #define I915_RESET_HANDOFF 1
1564 #define I915_WEDGED (BITS_PER_LONG - 1)
1565 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1567 /** Number of times an engine has been reset */
1568 u32 reset_engine_count
[I915_NUM_ENGINES
];
1571 * Waitqueue to signal when a hang is detected. Used to for waiters
1572 * to release the struct_mutex for the reset to procede.
1574 wait_queue_head_t wait_queue
;
1577 * Waitqueue to signal when the reset has completed. Used by clients
1578 * that wait for dev_priv->mm.wedged to settle.
1580 wait_queue_head_t reset_queue
;
1582 /* For missed irq/seqno simulation. */
1583 unsigned long test_irq_rings
;
1586 enum modeset_restore
{
1587 MODESET_ON_LID_OPEN
,
1592 #define DP_AUX_A 0x40
1593 #define DP_AUX_B 0x10
1594 #define DP_AUX_C 0x20
1595 #define DP_AUX_D 0x30
1597 #define DDC_PIN_B 0x05
1598 #define DDC_PIN_C 0x04
1599 #define DDC_PIN_D 0x06
1601 struct ddi_vbt_port_info
{
1603 * This is an index in the HDMI/DVI DDI buffer translation table.
1604 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1605 * populate this field.
1607 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1608 uint8_t hdmi_level_shift
;
1610 uint8_t supports_dvi
:1;
1611 uint8_t supports_hdmi
:1;
1612 uint8_t supports_dp
:1;
1613 uint8_t supports_edp
:1;
1615 uint8_t alternate_aux_channel
;
1616 uint8_t alternate_ddc_pin
;
1618 uint8_t dp_boost_level
;
1619 uint8_t hdmi_boost_level
;
1622 enum psr_lines_to_wait
{
1623 PSR_0_LINES_TO_WAIT
= 0,
1625 PSR_4_LINES_TO_WAIT
,
1629 struct intel_vbt_data
{
1630 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1631 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1634 unsigned int int_tv_support
:1;
1635 unsigned int lvds_dither
:1;
1636 unsigned int lvds_vbt
:1;
1637 unsigned int int_crt_support
:1;
1638 unsigned int lvds_use_ssc
:1;
1639 unsigned int display_clock_mode
:1;
1640 unsigned int fdi_rx_polarity_inverted
:1;
1641 unsigned int panel_type
:4;
1643 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1645 enum drrs_support_type drrs_type
;
1656 struct edp_power_seq pps
;
1661 bool require_aux_wakeup
;
1663 enum psr_lines_to_wait lines_to_wait
;
1664 int tp1_wakeup_time
;
1665 int tp2_tp3_wakeup_time
;
1671 bool active_low_pwm
;
1672 u8 min_brightness
; /* min_brightness/255 of max */
1673 u8 controller
; /* brightness controller number */
1674 enum intel_backlight_type type
;
1680 struct mipi_config
*config
;
1681 struct mipi_pps_data
*pps
;
1685 const u8
*sequence
[MIPI_SEQ_MAX
];
1691 union child_device_config
*child_dev
;
1693 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1694 struct sdvo_device_mapping sdvo_mappings
[2];
1697 enum intel_ddb_partitioning
{
1699 INTEL_DDB_PART_5_6
, /* IVB+ */
1702 struct intel_wm_level
{
1710 struct ilk_wm_values
{
1711 uint32_t wm_pipe
[3];
1713 uint32_t wm_lp_spr
[3];
1714 uint32_t wm_linetime
[3];
1716 enum intel_ddb_partitioning partitioning
;
1719 struct g4x_pipe_wm
{
1720 uint16_t plane
[I915_MAX_PLANES
];
1730 struct vlv_wm_ddl_values
{
1731 uint8_t plane
[I915_MAX_PLANES
];
1734 struct vlv_wm_values
{
1735 struct g4x_pipe_wm pipe
[3];
1736 struct g4x_sr_wm sr
;
1737 struct vlv_wm_ddl_values ddl
[3];
1742 struct g4x_wm_values
{
1743 struct g4x_pipe_wm pipe
[2];
1744 struct g4x_sr_wm sr
;
1745 struct g4x_sr_wm hpll
;
1751 struct skl_ddb_entry
{
1752 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1755 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1757 return entry
->end
- entry
->start
;
1760 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1761 const struct skl_ddb_entry
*e2
)
1763 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1769 struct skl_ddb_allocation
{
1770 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1771 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1774 struct skl_wm_values
{
1775 unsigned dirty_pipes
;
1776 struct skl_ddb_allocation ddb
;
1779 struct skl_wm_level
{
1781 uint16_t plane_res_b
;
1782 uint8_t plane_res_l
;
1786 * This struct helps tracking the state needed for runtime PM, which puts the
1787 * device in PCI D3 state. Notice that when this happens, nothing on the
1788 * graphics device works, even register access, so we don't get interrupts nor
1791 * Every piece of our code that needs to actually touch the hardware needs to
1792 * either call intel_runtime_pm_get or call intel_display_power_get with the
1793 * appropriate power domain.
1795 * Our driver uses the autosuspend delay feature, which means we'll only really
1796 * suspend if we stay with zero refcount for a certain amount of time. The
1797 * default value is currently very conservative (see intel_runtime_pm_enable), but
1798 * it can be changed with the standard runtime PM files from sysfs.
1800 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1801 * goes back to false exactly before we reenable the IRQs. We use this variable
1802 * to check if someone is trying to enable/disable IRQs while they're supposed
1803 * to be disabled. This shouldn't happen and we'll print some error messages in
1806 * For more, read the Documentation/power/runtime_pm.txt.
1808 struct i915_runtime_pm
{
1809 atomic_t wakeref_count
;
1814 enum intel_pipe_crc_source
{
1815 INTEL_PIPE_CRC_SOURCE_NONE
,
1816 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1817 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1818 INTEL_PIPE_CRC_SOURCE_PF
,
1819 INTEL_PIPE_CRC_SOURCE_PIPE
,
1820 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1821 INTEL_PIPE_CRC_SOURCE_TV
,
1822 INTEL_PIPE_CRC_SOURCE_DP_B
,
1823 INTEL_PIPE_CRC_SOURCE_DP_C
,
1824 INTEL_PIPE_CRC_SOURCE_DP_D
,
1825 INTEL_PIPE_CRC_SOURCE_AUTO
,
1826 INTEL_PIPE_CRC_SOURCE_MAX
,
1829 struct intel_pipe_crc_entry
{
1834 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1835 struct intel_pipe_crc
{
1837 bool opened
; /* exclusive access to the result file */
1838 struct intel_pipe_crc_entry
*entries
;
1839 enum intel_pipe_crc_source source
;
1841 wait_queue_head_t wq
;
1845 struct i915_frontbuffer_tracking
{
1849 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1856 struct i915_wa_reg
{
1859 /* bitmask representing WA bits */
1864 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1865 * allowing it for RCS as we don't foresee any requirement of having
1866 * a whitelist for other engines. When it is really required for
1867 * other engines then the limit need to be increased.
1869 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1871 struct i915_workarounds
{
1872 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1874 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1877 struct i915_virtual_gpu
{
1881 /* used in computing the new watermarks state */
1882 struct intel_wm_config
{
1883 unsigned int num_pipes_active
;
1884 bool sprites_enabled
;
1885 bool sprites_scaled
;
1888 struct i915_oa_format
{
1893 struct i915_oa_reg
{
1898 struct i915_perf_stream
;
1901 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1903 struct i915_perf_stream_ops
{
1905 * @enable: Enables the collection of HW samples, either in response to
1906 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1907 * without `I915_PERF_FLAG_DISABLED`.
1909 void (*enable
)(struct i915_perf_stream
*stream
);
1912 * @disable: Disables the collection of HW samples, either in response
1913 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1916 void (*disable
)(struct i915_perf_stream
*stream
);
1919 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1920 * once there is something ready to read() for the stream
1922 void (*poll_wait
)(struct i915_perf_stream
*stream
,
1927 * @wait_unlocked: For handling a blocking read, wait until there is
1928 * something to ready to read() for the stream. E.g. wait on the same
1929 * wait queue that would be passed to poll_wait().
1931 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
1934 * @read: Copy buffered metrics as records to userspace
1935 * **buf**: the userspace, destination buffer
1936 * **count**: the number of bytes to copy, requested by userspace
1937 * **offset**: zero at the start of the read, updated as the read
1938 * proceeds, it represents how many bytes have been copied so far and
1939 * the buffer offset for copying the next record.
1941 * Copy as many buffered i915 perf samples and records for this stream
1942 * to userspace as will fit in the given buffer.
1944 * Only write complete records; returning -%ENOSPC if there isn't room
1945 * for a complete record.
1947 * Return any error condition that results in a short read such as
1948 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1949 * returning to userspace.
1951 int (*read
)(struct i915_perf_stream
*stream
,
1957 * @destroy: Cleanup any stream specific resources.
1959 * The stream will always be disabled before this is called.
1961 void (*destroy
)(struct i915_perf_stream
*stream
);
1965 * struct i915_perf_stream - state for a single open stream FD
1967 struct i915_perf_stream
{
1969 * @dev_priv: i915 drm device
1971 struct drm_i915_private
*dev_priv
;
1974 * @link: Links the stream into ``&drm_i915_private->streams``
1976 struct list_head link
;
1979 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1980 * properties given when opening a stream, representing the contents
1981 * of a single sample as read() by userspace.
1986 * @sample_size: Considering the configured contents of a sample
1987 * combined with the required header size, this is the total size
1988 * of a single sample record.
1993 * @ctx: %NULL if measuring system-wide across all contexts or a
1994 * specific context that is being monitored.
1996 struct i915_gem_context
*ctx
;
1999 * @enabled: Whether the stream is currently enabled, considering
2000 * whether the stream was opened in a disabled state and based
2001 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2006 * @ops: The callbacks providing the implementation of this specific
2007 * type of configured stream.
2009 const struct i915_perf_stream_ops
*ops
;
2013 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2015 struct i915_oa_ops
{
2017 * @init_oa_buffer: Resets the head and tail pointers of the
2018 * circular buffer for periodic OA reports.
2020 * Called when first opening a stream for OA metrics, but also may be
2021 * called in response to an OA buffer overflow or other error
2024 * Note it may be necessary to clear the full OA buffer here as part of
2025 * maintaining the invariable that new reports must be written to
2026 * zeroed memory for us to be able to reliable detect if an expected
2027 * report has not yet landed in memory. (At least on Haswell the OA
2028 * buffer tail pointer is not synchronized with reports being visible
2031 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
2034 * @select_metric_set: The auto generated code that checks whether a
2035 * requested OA config is applicable to the system and if so sets up
2036 * the mux, oa and flex eu register config pointers according to the
2037 * current dev_priv->perf.oa.metrics_set.
2039 int (*select_metric_set
)(struct drm_i915_private
*dev_priv
);
2042 * @enable_metric_set: Selects and applies any MUX configuration to set
2043 * up the Boolean and Custom (B/C) counters that are part of the
2044 * counter reports being sampled. May apply system constraints such as
2045 * disabling EU clock gating as required.
2047 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
);
2050 * @disable_metric_set: Remove system constraints associated with using
2053 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
2056 * @oa_enable: Enable periodic sampling
2058 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
2061 * @oa_disable: Disable periodic sampling
2063 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
2066 * @read: Copy data from the circular OA buffer into a given userspace
2069 int (*read
)(struct i915_perf_stream
*stream
,
2075 * @oa_hw_tail_read: read the OA tail pointer register
2077 * In particular this enables us to share all the fiddly code for
2078 * handling the OA unit tail pointer race that affects multiple
2081 u32 (*oa_hw_tail_read
)(struct drm_i915_private
*dev_priv
);
2084 struct intel_cdclk_state
{
2085 unsigned int cdclk
, vco
, ref
;
2088 struct drm_i915_private
{
2089 struct drm_device drm
;
2091 struct kmem_cache
*objects
;
2092 struct kmem_cache
*vmas
;
2093 struct kmem_cache
*requests
;
2094 struct kmem_cache
*dependencies
;
2095 struct kmem_cache
*priorities
;
2097 const struct intel_device_info info
;
2101 struct intel_uncore uncore
;
2103 struct i915_virtual_gpu vgpu
;
2105 struct intel_gvt
*gvt
;
2107 struct intel_huc huc
;
2108 struct intel_guc guc
;
2110 struct intel_csr csr
;
2112 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
2114 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2115 * controller on different i2c buses. */
2116 struct mutex gmbus_mutex
;
2119 * Base address of the gmbus and gpio block.
2121 uint32_t gpio_mmio_base
;
2123 /* MMIO base address for MIPI regs */
2124 uint32_t mipi_mmio_base
;
2126 uint32_t psr_mmio_base
;
2128 uint32_t pps_mmio_base
;
2130 wait_queue_head_t gmbus_wait_queue
;
2132 struct pci_dev
*bridge_dev
;
2133 struct i915_gem_context
*kernel_context
;
2134 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
2135 struct i915_vma
*semaphore
;
2137 struct drm_dma_handle
*status_page_dmah
;
2138 struct resource mch_res
;
2140 /* protects the irq masks */
2141 spinlock_t irq_lock
;
2143 /* protects the mmio flip data */
2144 spinlock_t mmio_flip_lock
;
2146 bool display_irqs_enabled
;
2148 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2149 struct pm_qos_request pm_qos
;
2151 /* Sideband mailbox protection */
2152 struct mutex sb_lock
;
2154 /** Cached value of IMR to avoid reads in updating the bitfield */
2157 u32 de_irq_mask
[I915_MAX_PIPES
];
2164 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
2166 struct i915_hotplug hotplug
;
2167 struct intel_fbc fbc
;
2168 struct i915_drrs drrs
;
2169 struct intel_opregion opregion
;
2170 struct intel_vbt_data vbt
;
2172 bool preserve_bios_swizzle
;
2175 struct intel_overlay
*overlay
;
2177 /* backlight registers and fields in struct intel_panel */
2178 struct mutex backlight_lock
;
2181 bool no_aux_handshake
;
2183 /* protects panel power sequencer state */
2184 struct mutex pps_mutex
;
2186 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2187 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2189 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2190 unsigned int skl_preferred_vco_freq
;
2191 unsigned int max_cdclk_freq
;
2193 unsigned int max_dotclk_freq
;
2194 unsigned int rawclk_freq
;
2195 unsigned int hpll_freq
;
2196 unsigned int czclk_freq
;
2200 * The current logical cdclk state.
2201 * See intel_atomic_state.cdclk.logical
2203 * For reading holding any crtc lock is sufficient,
2204 * for writing must hold all of them.
2206 struct intel_cdclk_state logical
;
2208 * The current actual cdclk state.
2209 * See intel_atomic_state.cdclk.actual
2211 struct intel_cdclk_state actual
;
2212 /* The current hardware cdclk state */
2213 struct intel_cdclk_state hw
;
2217 * wq - Driver workqueue for GEM.
2219 * NOTE: Work items scheduled here are not allowed to grab any modeset
2220 * locks, for otherwise the flushing done in the pageflip code will
2221 * result in deadlocks.
2223 struct workqueue_struct
*wq
;
2225 /* Display functions */
2226 struct drm_i915_display_funcs display
;
2228 /* PCH chipset type */
2229 enum intel_pch pch_type
;
2230 unsigned short pch_id
;
2232 unsigned long quirks
;
2234 enum modeset_restore modeset_restore
;
2235 struct mutex modeset_restore_lock
;
2236 struct drm_atomic_state
*modeset_restore_state
;
2237 struct drm_modeset_acquire_ctx reset_ctx
;
2239 struct list_head vm_list
; /* Global list of all address spaces */
2240 struct i915_ggtt ggtt
; /* VM representing the global address space */
2242 struct i915_gem_mm mm
;
2243 DECLARE_HASHTABLE(mm_structs
, 7);
2244 struct mutex mm_lock
;
2246 /* Kernel Modesetting */
2248 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2249 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2250 wait_queue_head_t pending_flip_queue
;
2252 #ifdef CONFIG_DEBUG_FS
2253 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2256 /* dpll and cdclk state is protected by connection_mutex */
2257 int num_shared_dpll
;
2258 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2259 const struct intel_dpll_mgr
*dpll_mgr
;
2262 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2263 * Must be global rather than per dpll, because on some platforms
2264 * plls share registers.
2266 struct mutex dpll_lock
;
2268 unsigned int active_crtcs
;
2269 unsigned int min_pixclk
[I915_MAX_PIPES
];
2271 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2273 struct i915_workarounds workarounds
;
2275 struct i915_frontbuffer_tracking fb_tracking
;
2277 struct intel_atomic_helper
{
2278 struct llist_head free_list
;
2279 struct work_struct free_work
;
2284 bool mchbar_need_disable
;
2286 struct intel_l3_parity l3_parity
;
2288 /* Cannot be determined by PCIID. You must always read a register. */
2291 /* gen6+ rps state */
2292 struct intel_gen6_power_mgmt rps
;
2294 /* ilk-only ips/rps state. Everything in here is protected by the global
2295 * mchdev_lock in intel_pm.c */
2296 struct intel_ilk_power_mgmt ips
;
2298 struct i915_power_domains power_domains
;
2300 struct i915_psr psr
;
2302 struct i915_gpu_error gpu_error
;
2304 struct drm_i915_gem_object
*vlv_pctx
;
2306 #ifdef CONFIG_DRM_FBDEV_EMULATION
2307 /* list of fbdev register on this device */
2308 struct intel_fbdev
*fbdev
;
2309 struct work_struct fbdev_suspend_work
;
2312 struct drm_property
*broadcast_rgb_property
;
2313 struct drm_property
*force_audio_property
;
2315 /* hda/i915 audio component */
2316 struct i915_audio_component
*audio_component
;
2317 bool audio_component_registered
;
2319 * av_mutex - mutex for audio/video sync
2322 struct mutex av_mutex
;
2325 struct list_head list
;
2326 struct llist_head free_list
;
2327 struct work_struct free_work
;
2329 /* The hw wants to have a stable context identifier for the
2330 * lifetime of the context (for OA, PASID, faults, etc).
2331 * This is limited in execlists to 21 bits.
2334 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2339 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2340 u32 chv_phy_control
;
2342 * Shadows for CHV DPLL_MD regs to keep the state
2343 * checker somewhat working in the presence hardware
2344 * crappiness (can't read out DPLL_MD for pipes B & C).
2346 u32 chv_dpll_md
[I915_MAX_PIPES
];
2350 bool suspended_to_idle
;
2351 struct i915_suspend_saved_registers regfile
;
2352 struct vlv_s0ix_state vlv_s0ix_state
;
2355 I915_SAGV_UNKNOWN
= 0,
2358 I915_SAGV_NOT_CONTROLLED
2363 * Raw watermark latency values:
2364 * in 0.1us units for WM0,
2365 * in 0.5us units for WM1+.
2368 uint16_t pri_latency
[5];
2370 uint16_t spr_latency
[5];
2372 uint16_t cur_latency
[5];
2374 * Raw watermark memory latency values
2375 * for SKL for all 8 levels
2378 uint16_t skl_latency
[8];
2380 /* current hardware state */
2382 struct ilk_wm_values hw
;
2383 struct skl_wm_values skl_hw
;
2384 struct vlv_wm_values vlv
;
2385 struct g4x_wm_values g4x
;
2391 * Should be held around atomic WM register writing; also
2392 * protects * intel_crtc->wm.active and
2393 * cstate->wm.need_postvbl_update.
2395 struct mutex wm_mutex
;
2398 * Set during HW readout of watermarks/DDB. Some platforms
2399 * need to know when we're still using BIOS-provided values
2400 * (which we don't fully trust).
2402 bool distrust_bios_wm
;
2405 struct i915_runtime_pm pm
;
2410 struct kobject
*metrics_kobj
;
2411 struct ctl_table_header
*sysctl_header
;
2414 struct list_head streams
;
2417 struct i915_perf_stream
*exclusive_stream
;
2419 u32 specific_ctx_id
;
2421 struct hrtimer poll_check_timer
;
2422 wait_queue_head_t poll_wq
;
2426 * For rate limiting any notifications of spurious
2427 * invalid OA reports
2429 struct ratelimit_state spurious_report_rs
;
2432 int period_exponent
;
2433 int timestamp_frequency
;
2437 const struct i915_oa_reg
*mux_regs
[6];
2438 int mux_regs_lens
[6];
2441 const struct i915_oa_reg
*b_counter_regs
;
2442 int b_counter_regs_len
;
2443 const struct i915_oa_reg
*flex_regs
;
2447 struct i915_vma
*vma
;
2454 * Locks reads and writes to all head/tail state
2456 * Consider: the head and tail pointer state
2457 * needs to be read consistently from a hrtimer
2458 * callback (atomic context) and read() fop
2459 * (user context) with tail pointer updates
2460 * happening in atomic context and head updates
2461 * in user context and the (unlikely)
2462 * possibility of read() errors needing to
2463 * reset all head/tail state.
2465 * Note: Contention or performance aren't
2466 * currently a significant concern here
2467 * considering the relatively low frequency of
2468 * hrtimer callbacks (5ms period) and that
2469 * reads typically only happen in response to a
2470 * hrtimer event and likely complete before the
2473 * Note: This lock is not held *while* reading
2474 * and copying data to userspace so the value
2475 * of head observed in htrimer callbacks won't
2476 * represent any partial consumption of data.
2478 spinlock_t ptr_lock
;
2481 * One 'aging' tail pointer and one 'aged'
2482 * tail pointer ready to used for reading.
2484 * Initial values of 0xffffffff are invalid
2485 * and imply that an update is required
2486 * (and should be ignored by an attempted
2494 * Index for the aged tail ready to read()
2497 unsigned int aged_tail_idx
;
2500 * A monotonic timestamp for when the current
2501 * aging tail pointer was read; used to
2502 * determine when it is old enough to trust.
2504 u64 aging_timestamp
;
2507 * Although we can always read back the head
2508 * pointer register, we prefer to avoid
2509 * trusting the HW state, just to avoid any
2510 * risk that some hardware condition could
2511 * somehow bump the head pointer unpredictably
2512 * and cause us to forward the wrong OA buffer
2513 * data to userspace.
2518 u32 gen7_latched_oastatus1
;
2519 u32 ctx_oactxctrl_offset
;
2520 u32 ctx_flexeu0_offset
;
2523 * The RPT_ID/reason field for Gen8+ includes a bit
2524 * to determine if the CTX ID in the report is valid
2525 * but the specific bit differs between Gen 8 and 9
2527 u32 gen8_valid_ctx_bit
;
2529 struct i915_oa_ops ops
;
2530 const struct i915_oa_format
*oa_formats
;
2535 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2537 void (*resume
)(struct drm_i915_private
*);
2538 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2540 struct list_head timelines
;
2541 struct i915_gem_timeline global_timeline
;
2542 u32 active_requests
;
2545 * Is the GPU currently considered idle, or busy executing
2546 * userspace requests? Whilst idle, we allow runtime power
2547 * management to power down the hardware and display clocks.
2548 * In order to reduce the effect on performance, there
2549 * is a slight delay before we do so.
2554 * We leave the user IRQ off as much as possible,
2555 * but this means that requests will finish and never
2556 * be retired once the system goes idle. Set a timer to
2557 * fire periodically while the ring is running. When it
2558 * fires, go retire requests.
2560 struct delayed_work retire_work
;
2563 * When we detect an idle GPU, we want to turn on
2564 * powersaving features. So once we see that there
2565 * are no more requests outstanding and no more
2566 * arrive within a small period of time, we fire
2567 * off the idle_work.
2569 struct delayed_work idle_work
;
2571 ktime_t last_init_time
;
2574 /* perform PHY state sanity checks? */
2575 bool chv_phy_assert
[2];
2579 /* Used to save the pipe-to-encoder mapping for audio */
2580 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2582 /* necessary resource sharing with HDMI LPE audio driver. */
2584 struct platform_device
*platdev
;
2589 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2590 * will be rejected. Instead look for a better place.
2594 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2596 return container_of(dev
, struct drm_i915_private
, drm
);
2599 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2601 return to_i915(dev_get_drvdata(kdev
));
2604 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2606 return container_of(guc
, struct drm_i915_private
, guc
);
2609 static inline struct drm_i915_private
*huc_to_i915(struct intel_huc
*huc
)
2611 return container_of(huc
, struct drm_i915_private
, huc
);
2614 /* Simple iterator over all initialised engines */
2615 #define for_each_engine(engine__, dev_priv__, id__) \
2617 (id__) < I915_NUM_ENGINES; \
2619 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2621 /* Iterator over subset of engines selected by mask */
2622 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2623 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2624 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2626 enum hdmi_force_audio
{
2627 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2628 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2629 HDMI_AUDIO_AUTO
, /* trust EDID */
2630 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2633 #define I915_GTT_OFFSET_NONE ((u32)-1)
2636 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2637 * considered to be the frontbuffer for the given plane interface-wise. This
2638 * doesn't mean that the hw necessarily already scans it out, but that any
2639 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2641 * We have one bit per pipe and per scanout plane type.
2643 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2644 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2645 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2646 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2647 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2648 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2649 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2650 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2651 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2652 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2653 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2654 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2657 * Optimised SGL iterator for GEM objects
2659 static __always_inline
struct sgt_iter
{
2660 struct scatterlist
*sgp
;
2667 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2668 struct sgt_iter s
= { .sgp
= sgl
};
2671 s
.max
= s
.curr
= s
.sgp
->offset
;
2672 s
.max
+= s
.sgp
->length
;
2674 s
.dma
= sg_dma_address(s
.sgp
);
2676 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2682 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2685 if (unlikely(sg_is_chain(sg
)))
2686 sg
= sg_chain_ptr(sg
);
2691 * __sg_next - return the next scatterlist entry in a list
2692 * @sg: The current sg entry
2695 * If the entry is the last, return NULL; otherwise, step to the next
2696 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2697 * otherwise just return the pointer to the current element.
2699 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2701 #ifdef CONFIG_DEBUG_SG
2702 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2704 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2708 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2709 * @__dmap: DMA address (output)
2710 * @__iter: 'struct sgt_iter' (iterator state, internal)
2711 * @__sgt: sg_table to iterate over (input)
2713 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2714 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2715 ((__dmap) = (__iter).dma + (__iter).curr); \
2716 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2717 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2720 * for_each_sgt_page - iterate over the pages of the given sg_table
2721 * @__pp: page pointer (output)
2722 * @__iter: 'struct sgt_iter' (iterator state, internal)
2723 * @__sgt: sg_table to iterate over (input)
2725 #define for_each_sgt_page(__pp, __iter, __sgt) \
2726 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2727 ((__pp) = (__iter).pfn == 0 ? NULL : \
2728 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2729 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2730 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2732 static inline const struct intel_device_info
*
2733 intel_info(const struct drm_i915_private
*dev_priv
)
2735 return &dev_priv
->info
;
2738 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2740 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2741 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2743 #define REVID_FOREVER 0xff
2744 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2746 #define GEN_FOREVER (0)
2748 * Returns true if Gen is in inclusive range [Start, End].
2750 * Use GEN_FOREVER for unbound start and or end.
2752 #define IS_GEN(dev_priv, s, e) ({ \
2753 unsigned int __s = (s), __e = (e); \
2754 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2755 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2756 if ((__s) != GEN_FOREVER) \
2758 if ((__e) == GEN_FOREVER) \
2759 __e = BITS_PER_LONG - 1; \
2762 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2766 * Return true if revision is in range [since,until] inclusive.
2768 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2770 #define IS_REVID(p, since, until) \
2771 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2773 #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830)
2774 #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G)
2775 #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
2776 #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G)
2777 #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
2778 #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM)
2779 #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G)
2780 #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
2781 #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G)
2782 #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM)
2783 #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45)
2784 #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45)
2785 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2786 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2787 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2788 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW)
2789 #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
2790 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2791 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2792 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2793 INTEL_DEVID(dev_priv) == 0x0152 || \
2794 INTEL_DEVID(dev_priv) == 0x015a)
2795 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
2796 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
2797 #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
2798 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
2799 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
2800 #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
2801 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
2802 #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
2803 #define IS_COFFEELAKE(dev_priv) ((dev_priv)->info.platform == INTEL_COFFEELAKE)
2804 #define IS_CANNONLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_CANNONLAKE)
2805 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2806 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2807 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2808 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2809 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2810 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2811 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2812 /* ULX machines are also considered ULT. */
2813 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2814 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2815 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2816 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2817 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2818 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2819 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2820 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2821 /* ULX machines are also considered ULT. */
2822 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2823 INTEL_DEVID(dev_priv) == 0x0A1E)
2824 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2825 INTEL_DEVID(dev_priv) == 0x1913 || \
2826 INTEL_DEVID(dev_priv) == 0x1916 || \
2827 INTEL_DEVID(dev_priv) == 0x1921 || \
2828 INTEL_DEVID(dev_priv) == 0x1926)
2829 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2830 INTEL_DEVID(dev_priv) == 0x1915 || \
2831 INTEL_DEVID(dev_priv) == 0x191E)
2832 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2833 INTEL_DEVID(dev_priv) == 0x5913 || \
2834 INTEL_DEVID(dev_priv) == 0x5916 || \
2835 INTEL_DEVID(dev_priv) == 0x5921 || \
2836 INTEL_DEVID(dev_priv) == 0x5926)
2837 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2838 INTEL_DEVID(dev_priv) == 0x5915 || \
2839 INTEL_DEVID(dev_priv) == 0x591E)
2840 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2841 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
2842 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2843 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2844 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2845 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2846 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2847 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
2848 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2849 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2850 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2851 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2853 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2855 #define SKL_REVID_A0 0x0
2856 #define SKL_REVID_B0 0x1
2857 #define SKL_REVID_C0 0x2
2858 #define SKL_REVID_D0 0x3
2859 #define SKL_REVID_E0 0x4
2860 #define SKL_REVID_F0 0x5
2861 #define SKL_REVID_G0 0x6
2862 #define SKL_REVID_H0 0x7
2864 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2866 #define BXT_REVID_A0 0x0
2867 #define BXT_REVID_A1 0x1
2868 #define BXT_REVID_B0 0x3
2869 #define BXT_REVID_B_LAST 0x8
2870 #define BXT_REVID_C0 0x9
2872 #define IS_BXT_REVID(dev_priv, since, until) \
2873 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2875 #define KBL_REVID_A0 0x0
2876 #define KBL_REVID_B0 0x1
2877 #define KBL_REVID_C0 0x2
2878 #define KBL_REVID_D0 0x3
2879 #define KBL_REVID_E0 0x4
2881 #define IS_KBL_REVID(dev_priv, since, until) \
2882 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2884 #define GLK_REVID_A0 0x0
2885 #define GLK_REVID_A1 0x1
2887 #define IS_GLK_REVID(dev_priv, since, until) \
2888 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2890 #define CNL_REVID_A0 0x0
2891 #define CNL_REVID_B0 0x1
2893 #define IS_CNL_REVID(p, since, until) \
2894 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2897 * The genX designation typically refers to the render engine, so render
2898 * capability related checks should use IS_GEN, while display and other checks
2899 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2902 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2903 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2904 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2905 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2906 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2907 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2908 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2909 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2910 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2912 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2913 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2914 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2916 #define ENGINE_MASK(id) BIT(id)
2917 #define RENDER_RING ENGINE_MASK(RCS)
2918 #define BSD_RING ENGINE_MASK(VCS)
2919 #define BLT_RING ENGINE_MASK(BCS)
2920 #define VEBOX_RING ENGINE_MASK(VECS)
2921 #define BSD2_RING ENGINE_MASK(VCS2)
2922 #define ALL_ENGINES (~0)
2924 #define HAS_ENGINE(dev_priv, id) \
2925 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2927 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2928 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2929 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2930 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2932 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2933 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2934 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2935 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2936 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2938 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2940 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2941 ((dev_priv)->info.has_logical_ring_contexts)
2942 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2943 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2944 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2946 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2947 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2948 ((dev_priv)->info.overlay_needs_physical)
2950 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2951 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2953 /* WaRsDisableCoarsePowerGating:skl,bxt */
2954 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2955 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2958 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2959 * even when in MSI mode. This results in spurious interrupt warnings if the
2960 * legacy irq no. is shared with another device. The kernel then disables that
2961 * interrupt source and so prevents the other device from working properly.
2963 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2964 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2966 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2967 * rows, which changed the alignment requirements and fence programming.
2969 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2970 !(IS_I915G(dev_priv) || \
2971 IS_I915GM(dev_priv)))
2972 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2973 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2975 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2976 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2977 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2978 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2980 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2982 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2984 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2985 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2986 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2987 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2988 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2990 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2992 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2993 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2996 * For now, anything with a GuC requires uCode loading, and then supports
2997 * command submission once loaded. But these are logically independent
2998 * properties, so we have separate macros to test them.
3000 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
3001 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
3002 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3003 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
3004 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3006 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
3008 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
3010 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
3011 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3012 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
3013 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3014 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3015 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
3016 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
3017 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
3018 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
3019 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
3020 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
3021 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
3022 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
3023 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
3024 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
3025 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3027 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3028 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3029 #define HAS_PCH_CNP_LP(dev_priv) \
3030 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3031 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
3032 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
3033 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3034 #define HAS_PCH_LPT_LP(dev_priv) \
3035 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
3036 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
3037 #define HAS_PCH_LPT_H(dev_priv) \
3038 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
3039 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
3040 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3041 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3042 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3043 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3045 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3047 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3049 /* DPF == dynamic parity feature */
3050 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3051 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3052 2 : HAS_L3_DPF(dev_priv))
3054 #define GT_FREQUENCY_MULTIPLIER 50
3055 #define GEN9_FREQ_SCALER 3
3057 #include "i915_trace.h"
3059 static inline bool intel_vtd_active(void)
3061 #ifdef CONFIG_INTEL_IOMMU
3062 if (intel_iommu_gfx_mapped
)
3068 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3070 return INTEL_GEN(dev_priv
) >= 6 && intel_vtd_active();
3074 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3076 return IS_BROXTON(dev_priv
) && intel_vtd_active();
3079 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
3082 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
3086 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
3087 const char *fmt
, ...);
3089 #define i915_report_error(dev_priv, fmt, ...) \
3090 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3092 #ifdef CONFIG_COMPAT
3093 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
3096 #define i915_compat_ioctl NULL
3098 extern const struct dev_pm_ops i915_pm_ops
;
3100 extern int i915_driver_load(struct pci_dev
*pdev
,
3101 const struct pci_device_id
*ent
);
3102 extern void i915_driver_unload(struct drm_device
*dev
);
3103 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3104 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3105 extern void i915_reset(struct drm_i915_private
*dev_priv
);
3106 extern int i915_reset_engine(struct intel_engine_cs
*engine
);
3107 extern bool intel_has_reset_engine(struct drm_i915_private
*dev_priv
);
3108 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3109 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3110 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
3111 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3112 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3113 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3114 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3115 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3117 int intel_engines_init_mmio(struct drm_i915_private
*dev_priv
);
3118 int intel_engines_init(struct drm_i915_private
*dev_priv
);
3120 /* intel_hotplug.c */
3121 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3122 u32 pin_mask
, u32 long_mask
);
3123 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3124 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3125 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3126 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
3127 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3128 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3131 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3133 unsigned long delay
;
3135 if (unlikely(!i915
.enable_hangcheck
))
3138 /* Don't continually defer the hangcheck so that it is always run at
3139 * least once after work has been scheduled on any ring. Otherwise,
3140 * we will ignore a hung ring if a second ring is kept busy.
3143 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3144 queue_delayed_work(system_long_wq
,
3145 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3149 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3151 const char *fmt
, ...);
3153 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3154 extern void intel_irq_fini(struct drm_i915_private
*dev_priv
);
3155 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3156 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3158 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3160 return dev_priv
->gvt
;
3163 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3165 return dev_priv
->vgpu
.active
;
3169 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3173 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3176 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3177 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3178 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3181 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3182 uint32_t interrupt_mask
,
3183 uint32_t enabled_irq_mask
);
3185 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3187 ilk_update_display_irq(dev_priv
, bits
, bits
);
3190 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3192 ilk_update_display_irq(dev_priv
, bits
, 0);
3194 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3196 uint32_t interrupt_mask
,
3197 uint32_t enabled_irq_mask
);
3198 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3199 enum pipe pipe
, uint32_t bits
)
3201 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3203 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3204 enum pipe pipe
, uint32_t bits
)
3206 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3208 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3209 uint32_t interrupt_mask
,
3210 uint32_t enabled_irq_mask
);
3212 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3214 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3217 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3219 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3223 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3224 struct drm_file
*file_priv
);
3225 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3226 struct drm_file
*file_priv
);
3227 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3228 struct drm_file
*file_priv
);
3229 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3230 struct drm_file
*file_priv
);
3231 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3232 struct drm_file
*file_priv
);
3233 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3234 struct drm_file
*file_priv
);
3235 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3236 struct drm_file
*file_priv
);
3237 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3238 struct drm_file
*file_priv
);
3239 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3240 struct drm_file
*file_priv
);
3241 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3242 struct drm_file
*file_priv
);
3243 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3244 struct drm_file
*file
);
3245 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3246 struct drm_file
*file
);
3247 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3248 struct drm_file
*file_priv
);
3249 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3250 struct drm_file
*file_priv
);
3251 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
3252 struct drm_file
*file_priv
);
3253 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
3254 struct drm_file
*file_priv
);
3255 int i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3256 void i915_gem_cleanup_userptr(struct drm_i915_private
*dev_priv
);
3257 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3258 struct drm_file
*file
);
3259 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3260 struct drm_file
*file_priv
);
3261 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3262 struct drm_file
*file_priv
);
3263 void i915_gem_sanitize(struct drm_i915_private
*i915
);
3264 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
3265 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
3266 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3267 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3268 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3270 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
3271 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3272 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3273 const struct drm_i915_gem_object_ops
*ops
);
3274 struct drm_i915_gem_object
*
3275 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
3276 struct drm_i915_gem_object
*
3277 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
3278 const void *data
, size_t size
);
3279 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3280 void i915_gem_free_object(struct drm_gem_object
*obj
);
3282 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
3284 /* A single pass should suffice to release all the freed objects (along
3285 * most call paths) , but be a little more paranoid in that freeing
3286 * the objects does take a little amount of time, during which the rcu
3287 * callbacks could have added new objects into the freed list, and
3288 * armed the work again.
3292 } while (flush_work(&i915
->mm
.free_work
));
3295 struct i915_vma
* __must_check
3296 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3297 const struct i915_ggtt_view
*view
,
3302 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3303 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3305 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3307 static inline int __sg_page_count(const struct scatterlist
*sg
)
3309 return sg
->length
>> PAGE_SHIFT
;
3312 struct scatterlist
*
3313 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3314 unsigned int n
, unsigned int *offset
);
3317 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3321 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3325 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3328 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3329 struct sg_table
*pages
);
3330 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3332 static inline int __must_check
3333 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3335 might_lock(&obj
->mm
.lock
);
3337 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3340 return __i915_gem_object_get_pages(obj
);
3344 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3346 GEM_BUG_ON(!obj
->mm
.pages
);
3348 atomic_inc(&obj
->mm
.pages_pin_count
);
3352 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3354 return atomic_read(&obj
->mm
.pages_pin_count
);
3358 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3360 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3361 GEM_BUG_ON(!obj
->mm
.pages
);
3363 atomic_dec(&obj
->mm
.pages_pin_count
);
3367 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3369 __i915_gem_object_unpin_pages(obj
);
3372 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3377 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3378 enum i915_mm_subclass subclass
);
3379 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3381 enum i915_map_type
{
3387 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3388 * @obj: the object to map into kernel address space
3389 * @type: the type of mapping, used to select pgprot_t
3391 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3392 * pages and then returns a contiguous mapping of the backing storage into
3393 * the kernel address space. Based on the @type of mapping, the PTE will be
3394 * set to either WriteBack or WriteCombine (via pgprot_t).
3396 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3397 * mapping is no longer required.
3399 * Returns the pointer through which to access the mapped object, or an
3400 * ERR_PTR() on error.
3402 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3403 enum i915_map_type type
);
3406 * i915_gem_object_unpin_map - releases an earlier mapping
3407 * @obj: the object to unmap
3409 * After pinning the object and mapping its pages, once you are finished
3410 * with your access, call i915_gem_object_unpin_map() to release the pin
3411 * upon the mapping. Once the pin count reaches zero, that mapping may be
3414 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3416 i915_gem_object_unpin_pages(obj
);
3419 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3420 unsigned int *needs_clflush
);
3421 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3422 unsigned int *needs_clflush
);
3423 #define CLFLUSH_BEFORE BIT(0)
3424 #define CLFLUSH_AFTER BIT(1)
3425 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3428 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3430 i915_gem_object_unpin_pages(obj
);
3433 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3434 void i915_vma_move_to_active(struct i915_vma
*vma
,
3435 struct drm_i915_gem_request
*req
,
3436 unsigned int flags
);
3437 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3438 struct drm_device
*dev
,
3439 struct drm_mode_create_dumb
*args
);
3440 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3441 uint32_t handle
, uint64_t *offset
);
3442 int i915_gem_mmap_gtt_version(void);
3444 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3445 struct drm_i915_gem_object
*new,
3446 unsigned frontbuffer_bits
);
3448 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3450 struct drm_i915_gem_request
*
3451 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3453 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3455 static inline bool i915_reset_backoff(struct i915_gpu_error
*error
)
3457 return unlikely(test_bit(I915_RESET_BACKOFF
, &error
->flags
));
3460 static inline bool i915_reset_handoff(struct i915_gpu_error
*error
)
3462 return unlikely(test_bit(I915_RESET_HANDOFF
, &error
->flags
));
3465 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3467 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3470 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error
*error
)
3472 return i915_reset_backoff(error
) | i915_terminally_wedged(error
);
3475 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3477 return READ_ONCE(error
->reset_count
);
3480 static inline u32
i915_reset_engine_count(struct i915_gpu_error
*error
,
3481 struct intel_engine_cs
*engine
)
3483 return READ_ONCE(error
->reset_engine_count
[engine
->id
]);
3486 struct drm_i915_gem_request
*
3487 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
);
3488 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3489 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3490 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
);
3491 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3492 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3493 bool i915_gem_unset_wedged(struct drm_i915_private
*dev_priv
);
3494 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
3495 struct drm_i915_gem_request
*request
);
3497 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3498 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3499 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3500 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3501 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3502 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3503 unsigned int flags
);
3504 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3505 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3506 int i915_gem_fault(struct vm_fault
*vmf
);
3507 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3510 struct intel_rps_client
*rps
);
3511 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3514 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3517 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
);
3519 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
);
3521 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3522 struct i915_vma
* __must_check
3523 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3525 const struct i915_ggtt_view
*view
);
3526 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3527 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3529 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
);
3530 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3532 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3533 enum i915_cache_level cache_level
);
3535 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3536 struct dma_buf
*dma_buf
);
3538 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3539 struct drm_gem_object
*gem_obj
, int flags
);
3541 static inline struct i915_hw_ppgtt
*
3542 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3544 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3547 /* i915_gem_fence_reg.c */
3548 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3549 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3551 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3552 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3554 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3555 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3556 struct sg_table
*pages
);
3557 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3558 struct sg_table
*pages
);
3560 static inline struct i915_gem_context
*
3561 __i915_gem_context_lookup_rcu(struct drm_i915_file_private
*file_priv
, u32 id
)
3563 return idr_find(&file_priv
->context_idr
, id
);
3566 static inline struct i915_gem_context
*
3567 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3569 struct i915_gem_context
*ctx
;
3572 ctx
= __i915_gem_context_lookup_rcu(file_priv
, id
);
3573 if (ctx
&& !kref_get_unless_zero(&ctx
->ref
))
3580 static inline struct intel_timeline
*
3581 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3582 struct intel_engine_cs
*engine
)
3584 struct i915_address_space
*vm
;
3586 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3587 return &vm
->timeline
.engine
[engine
->id
];
3590 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3591 struct drm_file
*file
);
3592 void i915_oa_init_reg_state(struct intel_engine_cs
*engine
,
3593 struct i915_gem_context
*ctx
,
3594 uint32_t *reg_state
);
3596 /* i915_gem_evict.c */
3597 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3598 u64 min_size
, u64 alignment
,
3599 unsigned cache_level
,
3602 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3603 struct drm_mm_node
*node
,
3604 unsigned int flags
);
3605 int i915_gem_evict_vm(struct i915_address_space
*vm
);
3607 /* belongs in i915_gem_gtt.h */
3608 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3611 if (INTEL_GEN(dev_priv
) < 6)
3612 intel_gtt_chipset_flush();
3615 /* i915_gem_stolen.c */
3616 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3617 struct drm_mm_node
*node
, u64 size
,
3618 unsigned alignment
);
3619 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3620 struct drm_mm_node
*node
, u64 size
,
3621 unsigned alignment
, u64 start
,
3623 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3624 struct drm_mm_node
*node
);
3625 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3626 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3627 struct drm_i915_gem_object
*
3628 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3629 struct drm_i915_gem_object
*
3630 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3635 /* i915_gem_internal.c */
3636 struct drm_i915_gem_object
*
3637 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3640 /* i915_gem_shrinker.c */
3641 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3642 unsigned long target
,
3644 #define I915_SHRINK_PURGEABLE 0x1
3645 #define I915_SHRINK_UNBOUND 0x2
3646 #define I915_SHRINK_BOUND 0x4
3647 #define I915_SHRINK_ACTIVE 0x8
3648 #define I915_SHRINK_VMAPS 0x10
3649 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3650 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3651 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3654 /* i915_gem_tiling.c */
3655 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3657 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3659 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3660 i915_gem_object_is_tiled(obj
);
3663 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3664 unsigned int tiling
, unsigned int stride
);
3665 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3666 unsigned int tiling
, unsigned int stride
);
3668 /* i915_debugfs.c */
3669 #ifdef CONFIG_DEBUG_FS
3670 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3671 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3672 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3674 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3675 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3677 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3680 /* i915_gpu_error.c */
3681 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3684 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3685 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3686 const struct i915_gpu_state
*gpu
);
3687 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3688 struct drm_i915_private
*i915
,
3689 size_t count
, loff_t pos
);
3690 static inline void i915_error_state_buf_release(
3691 struct drm_i915_error_state_buf
*eb
)
3696 struct i915_gpu_state
*i915_capture_gpu_state(struct drm_i915_private
*i915
);
3697 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3699 const char *error_msg
);
3701 static inline struct i915_gpu_state
*
3702 i915_gpu_state_get(struct i915_gpu_state
*gpu
)
3704 kref_get(&gpu
->ref
);
3708 void __i915_gpu_state_free(struct kref
*kref
);
3709 static inline void i915_gpu_state_put(struct i915_gpu_state
*gpu
)
3712 kref_put(&gpu
->ref
, __i915_gpu_state_free
);
3715 struct i915_gpu_state
*i915_first_error_state(struct drm_i915_private
*i915
);
3716 void i915_reset_error_state(struct drm_i915_private
*i915
);
3720 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3722 const char *error_msg
)
3726 static inline struct i915_gpu_state
*
3727 i915_first_error_state(struct drm_i915_private
*i915
)
3732 static inline void i915_reset_error_state(struct drm_i915_private
*i915
)
3738 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3740 /* i915_cmd_parser.c */
3741 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3742 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3743 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3744 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3745 struct drm_i915_gem_object
*batch_obj
,
3746 struct drm_i915_gem_object
*shadow_batch_obj
,
3747 u32 batch_start_offset
,
3752 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3753 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3754 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3755 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3757 /* i915_suspend.c */
3758 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3759 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3762 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3763 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3765 /* intel_lpe_audio.c */
3766 int intel_lpe_audio_init(struct drm_i915_private
*dev_priv
);
3767 void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv
);
3768 void intel_lpe_audio_irq_handler(struct drm_i915_private
*dev_priv
);
3769 void intel_lpe_audio_notify(struct drm_i915_private
*dev_priv
,
3770 enum pipe pipe
, enum port port
,
3771 const void *eld
, int ls_clock
, bool dp_output
);
3774 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
3775 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
3776 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3779 extern struct i2c_adapter
*
3780 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3781 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3782 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3783 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3785 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3787 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
3790 void intel_bios_init(struct drm_i915_private
*dev_priv
);
3791 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3792 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3793 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3794 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3795 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3796 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3797 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3798 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3800 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3804 /* intel_opregion.c */
3806 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3807 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3808 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3809 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3810 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3812 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3814 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3816 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3817 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3818 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3819 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3823 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3828 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3832 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3840 extern void intel_register_dsm_handler(void);
3841 extern void intel_unregister_dsm_handler(void);
3843 static inline void intel_register_dsm_handler(void) { return; }
3844 static inline void intel_unregister_dsm_handler(void) { return; }
3845 #endif /* CONFIG_ACPI */
3847 /* intel_device_info.c */
3848 static inline struct intel_device_info
*
3849 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3851 return (struct intel_device_info
*)&dev_priv
->info
;
3854 const char *intel_platform_name(enum intel_platform platform
);
3855 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3856 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3859 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3860 extern int intel_modeset_init(struct drm_device
*dev
);
3861 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3862 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3863 extern int intel_connector_register(struct drm_connector
*);
3864 extern void intel_connector_unregister(struct drm_connector
*);
3865 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
3867 extern void intel_display_resume(struct drm_device
*dev
);
3868 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
3869 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
3870 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3871 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
3872 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3873 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3876 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3877 struct drm_file
*file
);
3880 extern struct intel_overlay_error_state
*
3881 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3882 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3883 struct intel_overlay_error_state
*error
);
3885 extern struct intel_display_error_state
*
3886 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3887 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3888 struct intel_display_error_state
*error
);
3890 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3891 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3892 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
3893 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
3895 /* intel_sideband.c */
3896 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3897 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3898 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3899 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3900 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3901 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3902 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3903 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3904 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3905 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3906 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3907 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3908 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3909 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3910 enum intel_sbi_destination destination
);
3911 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3912 enum intel_sbi_destination destination
);
3913 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3914 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3916 /* intel_dpio_phy.c */
3917 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
3918 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3919 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3920 enum port port
, u32 margin
, u32 scale
,
3921 u32 enable
, u32 deemphasis
);
3922 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3923 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3924 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3926 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3928 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3929 uint8_t lane_count
);
3930 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3931 uint8_t lane_lat_optim_mask
);
3932 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3934 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3935 u32 deemph_reg_value
, u32 margin_reg_value
,
3936 bool uniq_trans_scale
);
3937 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3939 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3940 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3941 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3942 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3944 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3945 u32 demph_reg_value
, u32 preemph_reg_value
,
3946 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3947 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3948 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3949 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3951 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3952 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3953 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
3954 const i915_reg_t reg
);
3956 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3957 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3959 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3960 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3961 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3962 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3964 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3965 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3966 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3967 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3969 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3970 * will be implemented using 2 32-bit writes in an arbitrary order with
3971 * an arbitrary delay between them. This can cause the hardware to
3972 * act upon the intermediate value, possibly leading to corruption and
3973 * machine death. For this reason we do not support I915_WRITE64, or
3974 * dev_priv->uncore.funcs.mmio_writeq.
3976 * When reading a 64-bit value as two 32-bit values, the delay may cause
3977 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3978 * occasionally a 64-bit register does not actualy support a full readq
3979 * and must be read using two 32-bit reads.
3981 * You have been warned.
3983 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3985 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3986 u32 upper, lower, old_upper, loop = 0; \
3987 upper = I915_READ(upper_reg); \
3989 old_upper = upper; \
3990 lower = I915_READ(lower_reg); \
3991 upper = I915_READ(upper_reg); \
3992 } while (upper != old_upper && loop++ < 2); \
3993 (u64)upper << 32 | lower; })
3995 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3996 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3998 #define __raw_read(x, s) \
3999 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
4002 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
4005 #define __raw_write(x, s) \
4006 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
4007 i915_reg_t reg, uint##x##_t val) \
4009 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
4024 /* These are untraced mmio-accessors that are only valid to be used inside
4025 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4028 * Think twice, and think again, before using these.
4030 * As an example, these accessors can possibly be used between:
4032 * spin_lock_irq(&dev_priv->uncore.lock);
4033 * intel_uncore_forcewake_get__locked();
4037 * intel_uncore_forcewake_put__locked();
4038 * spin_unlock_irq(&dev_priv->uncore.lock);
4041 * Note: some registers may not need forcewake held, so
4042 * intel_uncore_forcewake_{get,put} can be omitted, see
4043 * intel_uncore_forcewake_for_reg().
4045 * Certain architectures will die if the same cacheline is concurrently accessed
4046 * by different clients (e.g. on Ivybridge). Access to registers should
4047 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4048 * a more localised lock guarding all access to that bank of registers.
4050 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4051 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4052 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4053 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4055 /* "Broadcast RGB" property */
4056 #define INTEL_BROADCAST_RGB_AUTO 0
4057 #define INTEL_BROADCAST_RGB_FULL 1
4058 #define INTEL_BROADCAST_RGB_LIMITED 2
4060 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
4062 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4063 return VLV_VGACNTRL
;
4064 else if (INTEL_GEN(dev_priv
) >= 5)
4065 return CPU_VGACNTRL
;
4070 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
4072 unsigned long j
= msecs_to_jiffies(m
);
4074 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4077 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4079 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4082 static inline unsigned long
4083 timespec_to_jiffies_timeout(const struct timespec
*value
)
4085 unsigned long j
= timespec_to_jiffies(value
);
4087 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4091 * If you need to wait X milliseconds between events A and B, but event B
4092 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4093 * when event A happened, then just before event B you call this function and
4094 * pass the timestamp as the first argument, and X as the second argument.
4097 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4099 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4102 * Don't re-read the value of "jiffies" every time since it may change
4103 * behind our back and break the math.
4105 tmp_jiffies
= jiffies
;
4106 target_jiffies
= timestamp_jiffies
+
4107 msecs_to_jiffies_timeout(to_wait_ms
);
4109 if (time_after(target_jiffies
, tmp_jiffies
)) {
4110 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4111 while (remaining_jiffies
)
4113 schedule_timeout_uninterruptible(remaining_jiffies
);
4118 __i915_request_irq_complete(const struct drm_i915_gem_request
*req
)
4120 struct intel_engine_cs
*engine
= req
->engine
;
4123 /* Note that the engine may have wrapped around the seqno, and
4124 * so our request->global_seqno will be ahead of the hardware,
4125 * even though it completed the request before wrapping. We catch
4126 * this by kicking all the waiters before resetting the seqno
4127 * in hardware, and also signal the fence.
4129 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &req
->fence
.flags
))
4132 /* The request was dequeued before we were awoken. We check after
4133 * inspecting the hw to confirm that this was the same request
4134 * that generated the HWS update. The memory barriers within
4135 * the request execution are sufficient to ensure that a check
4136 * after reading the value from hw matches this request.
4138 seqno
= i915_gem_request_global_seqno(req
);
4142 /* Before we do the heavier coherent read of the seqno,
4143 * check the value (hopefully) in the CPU cacheline.
4145 if (__i915_gem_request_completed(req
, seqno
))
4148 /* Ensure our read of the seqno is coherent so that we
4149 * do not "miss an interrupt" (i.e. if this is the last
4150 * request and the seqno write from the GPU is not visible
4151 * by the time the interrupt fires, we will see that the
4152 * request is incomplete and go back to sleep awaiting
4153 * another interrupt that will never come.)
4155 * Strictly, we only need to do this once after an interrupt,
4156 * but it is easier and safer to do it every time the waiter
4159 if (engine
->irq_seqno_barrier
&&
4160 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
4161 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
4163 /* The ordering of irq_posted versus applying the barrier
4164 * is crucial. The clearing of the current irq_posted must
4165 * be visible before we perform the barrier operation,
4166 * such that if a subsequent interrupt arrives, irq_posted
4167 * is reasserted and our task rewoken (which causes us to
4168 * do another __i915_request_irq_complete() immediately
4169 * and reapply the barrier). Conversely, if the clear
4170 * occurs after the barrier, then an interrupt that arrived
4171 * whilst we waited on the barrier would not trigger a
4172 * barrier on the next pass, and the read may not see the
4175 engine
->irq_seqno_barrier(engine
);
4177 /* If we consume the irq, but we are no longer the bottom-half,
4178 * the real bottom-half may not have serialised their own
4179 * seqno check with the irq-barrier (i.e. may have inspected
4180 * the seqno before we believe it coherent since they see
4181 * irq_posted == false but we are still running).
4183 spin_lock_irq(&b
->irq_lock
);
4184 if (b
->irq_wait
&& b
->irq_wait
->tsk
!= current
)
4185 /* Note that if the bottom-half is changed as we
4186 * are sending the wake-up, the new bottom-half will
4187 * be woken by whomever made the change. We only have
4188 * to worry about when we steal the irq-posted for
4191 wake_up_process(b
->irq_wait
->tsk
);
4192 spin_unlock_irq(&b
->irq_lock
);
4194 if (__i915_gem_request_completed(req
, seqno
))
4201 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4202 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4204 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4205 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4206 * perform the operation. To check beforehand, pass in the parameters to
4207 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4208 * you only need to pass in the minor offsets, page-aligned pointers are
4211 * For just checking for SSE4.1, in the foreknowledge that the future use
4212 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4214 #define i915_can_memcpy_from_wc(dst, src, len) \
4215 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4217 #define i915_has_memcpy_from_wc() \
4218 i915_memcpy_from_wc(NULL, NULL, 0)
4221 int remap_io_mapping(struct vm_area_struct
*vma
,
4222 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4223 struct io_mapping
*iomap
);
4225 static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object
*obj
)
4227 return (obj
->cache_level
!= I915_CACHE_NONE
||
4228 HAS_LLC(to_i915(obj
->base
.dev
)));