drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <drm/intel-gtt.h>
  40 #include <linux/backlight.h>
  41
  42 /* General customization:
  43  */
  44
  45 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  46
  47 #define DRIVER_NAME             "i915"
  48 #define DRIVER_DESC             "Intel Graphics"
  49 #define DRIVER_DATE             "20080730"
  50
  51 enum pipe {
  52         PIPE_A = 0,
  53         PIPE_B,
  54         PIPE_C,
  55         I915_MAX_PIPES
  56 };
  57 #define pipe_name(p) ((p) + 'A')
  58
  59 enum plane {
  60         PLANE_A = 0,
  61         PLANE_B,
  62         PLANE_C,
  63 };
  64 #define plane_name(p) ((p) + 'A')
  65
  66 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  67
  68 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  69
  70 /* Interface history:
  71  *
  72  * 1.1: Original.
  73  * 1.2: Add Power Management
  74  * 1.3: Add vblank support
  75  * 1.4: Fix cmdbuffer path, add heap destroy
  76  * 1.5: Add vblank pipe configuration
  77  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  78  *      - Support vertical blank on secondary display pipe
  79  */
  80 #define DRIVER_MAJOR            1
  81 #define DRIVER_MINOR            6
  82 #define DRIVER_PATCHLEVEL       0
  83
  84 #define WATCH_COHERENCY 0
  85 #define WATCH_LISTS     0
  86
  87 #define I915_GEM_PHYS_CURSOR_0 1
  88 #define I915_GEM_PHYS_CURSOR_1 2
  89 #define I915_GEM_PHYS_OVERLAY_REGS 3
  90 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  91
  92 struct drm_i915_gem_phys_object {
  93         int id;
  94         struct page **page_list;
  95         drm_dma_handle_t *handle;
  96         struct drm_i915_gem_object *cur_obj;
  97 };
  98
  99 struct mem_block {
 100         struct mem_block *next;
 101         struct mem_block *prev;
 102         int start;
 103         int size;
 104         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 105 };
 106
 107 struct opregion_header;
 108 struct opregion_acpi;
 109 struct opregion_swsci;
 110 struct opregion_asle;
 111 struct drm_i915_private;
 112
 113 struct intel_opregion {
 114         struct opregion_header *header;
 115         struct opregion_acpi *acpi;
 116         struct opregion_swsci *swsci;
 117         struct opregion_asle *asle;
 118         void *vbt;
 119         u32 __iomem *lid_state;
 120 };
 121 #define OPREGION_SIZE            (8*1024)
 122
 123 struct intel_overlay;
 124 struct intel_overlay_error_state;
 125
 126 struct drm_i915_master_private {
 127         drm_local_map_t *sarea;
 128         struct _drm_i915_sarea *sarea_priv;
 129 };
 130 #define I915_FENCE_REG_NONE -1
 131 #define I915_MAX_NUM_FENCES 16
 132 /* 16 fences + sign bit for FENCE_REG_NONE */
 133 #define I915_MAX_NUM_FENCE_BITS 5
 134
 135 struct drm_i915_fence_reg {
 136         struct list_head lru_list;
 137         struct drm_i915_gem_object *obj;
 138         uint32_t setup_seqno;
 139         int pin_count;
 140 };
 141
 142 struct sdvo_device_mapping {
 143         u8 initialized;
 144         u8 dvo_port;
 145         u8 slave_addr;
 146         u8 dvo_wiring;
 147         u8 i2c_pin;
 148         u8 ddc_pin;
 149 };
 150
 151 struct intel_display_error_state;
 152
 153 struct drm_i915_error_state {
 154         u32 eir;
 155         u32 pgtbl_er;
 156         u32 pipestat[I915_MAX_PIPES];
 157         u32 tail[I915_NUM_RINGS];
 158         u32 head[I915_NUM_RINGS];
 159         u32 ipeir[I915_NUM_RINGS];
 160         u32 ipehr[I915_NUM_RINGS];
 161         u32 instdone[I915_NUM_RINGS];
 162         u32 acthd[I915_NUM_RINGS];
 163         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 164         /* our own tracking of ring head and tail */
 165         u32 cpu_ring_head[I915_NUM_RINGS];
 166         u32 cpu_ring_tail[I915_NUM_RINGS];
 167         u32 error; /* gen6+ */
 168         u32 instpm[I915_NUM_RINGS];
 169         u32 instps[I915_NUM_RINGS];
 170         u32 instdone1;
 171         u32 seqno[I915_NUM_RINGS];
 172         u64 bbaddr;
 173         u32 fault_reg[I915_NUM_RINGS];
 174         u32 done_reg;
 175         u32 faddr[I915_NUM_RINGS];
 176         u64 fence[I915_MAX_NUM_FENCES];
 177         struct timeval time;
 178         struct drm_i915_error_ring {
 179                 struct drm_i915_error_object {
 180                         int page_count;
 181                         u32 gtt_offset;
 182                         u32 *pages[0];
 183                 } *ringbuffer, *batchbuffer;
 184                 struct drm_i915_error_request {
 185                         long jiffies;
 186                         u32 seqno;
 187                         u32 tail;
 188                 } *requests;
 189                 int num_requests;
 190         } ring[I915_NUM_RINGS];
 191         struct drm_i915_error_buffer {
 192                 u32 size;
 193                 u32 name;
 194                 u32 seqno;
 195                 u32 gtt_offset;
 196                 u32 read_domains;
 197                 u32 write_domain;
 198                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 199                 s32 pinned:2;
 200                 u32 tiling:2;
 201                 u32 dirty:1;
 202                 u32 purgeable:1;
 203                 s32 ring:4;
 204                 u32 cache_level:2;
 205         } *active_bo, *pinned_bo;
 206         u32 active_bo_count, pinned_bo_count;
 207         struct intel_overlay_error_state *overlay;
 208         struct intel_display_error_state *display;
 209 };
 210
 211 struct drm_i915_display_funcs {
 212         void (*dpms)(struct drm_crtc *crtc, int mode);
 213         bool (*fbc_enabled)(struct drm_device *dev);
 214         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 215         void (*disable_fbc)(struct drm_device *dev);
 216         int (*get_display_clock_speed)(struct drm_device *dev);
 217         int (*get_fifo_size)(struct drm_device *dev, int plane);
 218         void (*update_wm)(struct drm_device *dev);
 219         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
 220                                  uint32_t sprite_width, int pixel_size);
 221         int (*crtc_mode_set)(struct drm_crtc *crtc,
 222                              struct drm_display_mode *mode,
 223                              struct drm_display_mode *adjusted_mode,
 224                              int x, int y,
 225                              struct drm_framebuffer *old_fb);
 226         void (*write_eld)(struct drm_connector *connector,
 227                           struct drm_crtc *crtc);
 228         void (*fdi_link_train)(struct drm_crtc *crtc);
 229         void (*init_clock_gating)(struct drm_device *dev);
 230         void (*init_pch_clock_gating)(struct drm_device *dev);
 231         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 232                           struct drm_framebuffer *fb,
 233                           struct drm_i915_gem_object *obj);
 234         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 235                             int x, int y);
 236         void (*force_wake_get)(struct drm_i915_private *dev_priv);
 237         void (*force_wake_put)(struct drm_i915_private *dev_priv);
 238         /* clock updates for mode set */
 239         /* cursor updates */
 240         /* render clock increase/decrease */
 241         /* display clock increase/decrease */
 242         /* pll clock increase/decrease */
 243 };
 244
 245 struct intel_device_info {
 246         u8 gen;
 247         u8 is_mobile:1;
 248         u8 is_i85x:1;
 249         u8 is_i915g:1;
 250         u8 is_i945gm:1;
 251         u8 is_g33:1;
 252         u8 need_gfx_hws:1;
 253         u8 is_g4x:1;
 254         u8 is_pineview:1;
 255         u8 is_broadwater:1;
 256         u8 is_crestline:1;
 257         u8 is_ivybridge:1;
 258         u8 has_fbc:1;
 259         u8 has_pipe_cxsr:1;
 260         u8 has_hotplug:1;
 261         u8 cursor_needs_physical:1;
 262         u8 has_overlay:1;
 263         u8 overlay_needs_physical:1;
 264         u8 supports_tv:1;
 265         u8 has_bsd_ring:1;
 266         u8 has_blt_ring:1;
 267         u8 has_llc:1;
 268 };
 269
 270 #define I915_PPGTT_PD_ENTRIES 512
 271 #define I915_PPGTT_PT_ENTRIES 1024
 272 struct i915_hw_ppgtt {
 273         unsigned num_pd_entries;
 274         struct page **pt_pages;
 275         uint32_t pd_offset;
 276         dma_addr_t *pt_dma_addr;
 277         dma_addr_t scratch_page_dma_addr;
 278 };
 279
 280 enum no_fbc_reason {
 281         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 282         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 283         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 284         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 285         FBC_BAD_PLANE, /* fbc not supported on plane */
 286         FBC_NOT_TILED, /* buffer not tiled */
 287         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 288         FBC_MODULE_PARAM,
 289 };
 290
 291 enum intel_pch {
 292         PCH_IBX,        /* Ibexpeak PCH */
 293         PCH_CPT,        /* Cougarpoint PCH */
 294 };
 295
 296 #define QUIRK_PIPEA_FORCE (1<<0)
 297 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 298 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 299
 300 struct intel_fbdev;
 301 struct intel_fbc_work;
 302
 303 struct intel_gmbus {
 304         struct i2c_adapter adapter;
 305         bool force_bit;
 306         bool has_gpio;
 307         u32 reg0;
 308         u32 gpio_reg;
 309         struct i2c_algo_bit_data bit_algo;
 310         struct drm_i915_private *dev_priv;
 311 };
 312
 313 typedef struct drm_i915_private {
 314         struct drm_device *dev;
 315
 316         const struct intel_device_info *info;
 317
 318         int has_gem;
 319         int relative_constants_mode;
 320
 321         void __iomem *regs;
 322         /** gt_fifo_count and the subsequent register write are synchronized
 323          * with dev->struct_mutex. */
 324         unsigned gt_fifo_count;
 325         /** forcewake_count is protected by gt_lock */
 326         unsigned forcewake_count;
 327         /** gt_lock is also taken in irq contexts. */
 328         struct spinlock gt_lock;
 329
 330         struct intel_gmbus *gmbus;
 331
 332         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 333          * controller on different i2c buses. */
 334         struct mutex gmbus_mutex;
 335
 336         struct pci_dev *bridge_dev;
 337         struct intel_ring_buffer ring[I915_NUM_RINGS];
 338         uint32_t next_seqno;
 339
 340         drm_dma_handle_t *status_page_dmah;
 341         uint32_t counter;
 342         drm_local_map_t hws_map;
 343         struct drm_i915_gem_object *pwrctx;
 344         struct drm_i915_gem_object *renderctx;
 345
 346         struct resource mch_res;
 347
 348         unsigned int cpp;
 349         int back_offset;
 350         int front_offset;
 351         int current_page;
 352         int page_flipping;
 353
 354         atomic_t irq_received;
 355
 356         /* protects the irq masks */
 357         spinlock_t irq_lock;
 358         /** Cached value of IMR to avoid reads in updating the bitfield */
 359         u32 pipestat[2];
 360         u32 irq_mask;
 361         u32 gt_irq_mask;
 362         u32 pch_irq_mask;
 363
 364         u32 hotplug_supported_mask;
 365         struct work_struct hotplug_work;
 366
 367         int tex_lru_log_granularity;
 368         int allow_batchbuffer;
 369         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 370         int vblank_pipe;
 371         int num_pipe;
 372
 373         /* For hangcheck timer */
 374 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 375         struct timer_list hangcheck_timer;
 376         int hangcheck_count;
 377         uint32_t last_acthd;
 378         uint32_t last_acthd_bsd;
 379         uint32_t last_acthd_blt;
 380         uint32_t last_instdone;
 381         uint32_t last_instdone1;
 382
 383         unsigned long cfb_size;
 384         unsigned int cfb_fb;
 385         enum plane cfb_plane;
 386         int cfb_y;
 387         struct intel_fbc_work *fbc_work;
 388
 389         struct intel_opregion opregion;
 390
 391         /* overlay */
 392         struct intel_overlay *overlay;
 393         bool sprite_scaling_enabled;
 394
 395         /* LVDS info */
 396         int backlight_level;  /* restore backlight to this value */
 397         bool backlight_enabled;
 398         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 399         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 400
 401         /* Feature bits from the VBIOS */
 402         unsigned int int_tv_support:1;
 403         unsigned int lvds_dither:1;
 404         unsigned int lvds_vbt:1;
 405         unsigned int int_crt_support:1;
 406         unsigned int lvds_use_ssc:1;
 407         unsigned int display_clock_mode:1;
 408         int lvds_ssc_freq;
 409         struct {
 410                 int rate;
 411                 int lanes;
 412                 int preemphasis;
 413                 int vswing;
 414
 415                 bool initialized;
 416                 bool support;
 417                 int bpp;
 418                 struct edp_power_seq pps;
 419         } edp;
 420         bool no_aux_handshake;
 421
 422         struct notifier_block lid_notifier;
 423
 424         int crt_ddc_pin;
 425         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
 426         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 427         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 428
 429         unsigned int fsb_freq, mem_freq, is_ddr3;
 430
 431         spinlock_t error_lock;
 432         struct drm_i915_error_state *first_error;
 433         struct work_struct error_work;
 434         struct completion error_completion;
 435         struct workqueue_struct *wq;
 436
 437         /* Display functions */
 438         struct drm_i915_display_funcs display;
 439
 440         /* PCH chipset type */
 441         enum intel_pch pch_type;
 442
 443         unsigned long quirks;
 444
 445         /* Register state */
 446         bool modeset_on_lid;
 447         u8 saveLBB;
 448         u32 saveDSPACNTR;
 449         u32 saveDSPBCNTR;
 450         u32 saveDSPARB;
 451         u32 saveHWS;
 452         u32 savePIPEACONF;
 453         u32 savePIPEBCONF;
 454         u32 savePIPEASRC;
 455         u32 savePIPEBSRC;
 456         u32 saveFPA0;
 457         u32 saveFPA1;
 458         u32 saveDPLL_A;
 459         u32 saveDPLL_A_MD;
 460         u32 saveHTOTAL_A;
 461         u32 saveHBLANK_A;
 462         u32 saveHSYNC_A;
 463         u32 saveVTOTAL_A;
 464         u32 saveVBLANK_A;
 465         u32 saveVSYNC_A;
 466         u32 saveBCLRPAT_A;
 467         u32 saveTRANSACONF;
 468         u32 saveTRANS_HTOTAL_A;
 469         u32 saveTRANS_HBLANK_A;
 470         u32 saveTRANS_HSYNC_A;
 471         u32 saveTRANS_VTOTAL_A;
 472         u32 saveTRANS_VBLANK_A;
 473         u32 saveTRANS_VSYNC_A;
 474         u32 savePIPEASTAT;
 475         u32 saveDSPASTRIDE;
 476         u32 saveDSPASIZE;
 477         u32 saveDSPAPOS;
 478         u32 saveDSPAADDR;
 479         u32 saveDSPASURF;
 480         u32 saveDSPATILEOFF;
 481         u32 savePFIT_PGM_RATIOS;
 482         u32 saveBLC_HIST_CTL;
 483         u32 saveBLC_PWM_CTL;
 484         u32 saveBLC_PWM_CTL2;
 485         u32 saveBLC_CPU_PWM_CTL;
 486         u32 saveBLC_CPU_PWM_CTL2;
 487         u32 saveFPB0;
 488         u32 saveFPB1;
 489         u32 saveDPLL_B;
 490         u32 saveDPLL_B_MD;
 491         u32 saveHTOTAL_B;
 492         u32 saveHBLANK_B;
 493         u32 saveHSYNC_B;
 494         u32 saveVTOTAL_B;
 495         u32 saveVBLANK_B;
 496         u32 saveVSYNC_B;
 497         u32 saveBCLRPAT_B;
 498         u32 saveTRANSBCONF;
 499         u32 saveTRANS_HTOTAL_B;
 500         u32 saveTRANS_HBLANK_B;
 501         u32 saveTRANS_HSYNC_B;
 502         u32 saveTRANS_VTOTAL_B;
 503         u32 saveTRANS_VBLANK_B;
 504         u32 saveTRANS_VSYNC_B;
 505         u32 savePIPEBSTAT;
 506         u32 saveDSPBSTRIDE;
 507         u32 saveDSPBSIZE;
 508         u32 saveDSPBPOS;
 509         u32 saveDSPBADDR;
 510         u32 saveDSPBSURF;
 511         u32 saveDSPBTILEOFF;
 512         u32 saveVGA0;
 513         u32 saveVGA1;
 514         u32 saveVGA_PD;
 515         u32 saveVGACNTRL;
 516         u32 saveADPA;
 517         u32 saveLVDS;
 518         u32 savePP_ON_DELAYS;
 519         u32 savePP_OFF_DELAYS;
 520         u32 saveDVOA;
 521         u32 saveDVOB;
 522         u32 saveDVOC;
 523         u32 savePP_ON;
 524         u32 savePP_OFF;
 525         u32 savePP_CONTROL;
 526         u32 savePP_DIVISOR;
 527         u32 savePFIT_CONTROL;
 528         u32 save_palette_a[256];
 529         u32 save_palette_b[256];
 530         u32 saveDPFC_CB_BASE;
 531         u32 saveFBC_CFB_BASE;
 532         u32 saveFBC_LL_BASE;
 533         u32 saveFBC_CONTROL;
 534         u32 saveFBC_CONTROL2;
 535         u32 saveIER;
 536         u32 saveIIR;
 537         u32 saveIMR;
 538         u32 saveDEIER;
 539         u32 saveDEIMR;
 540         u32 saveGTIER;
 541         u32 saveGTIMR;
 542         u32 saveFDI_RXA_IMR;
 543         u32 saveFDI_RXB_IMR;
 544         u32 saveCACHE_MODE_0;
 545         u32 saveMI_ARB_STATE;
 546         u32 saveSWF0[16];
 547         u32 saveSWF1[16];
 548         u32 saveSWF2[3];
 549         u8 saveMSR;
 550         u8 saveSR[8];
 551         u8 saveGR[25];
 552         u8 saveAR_INDEX;
 553         u8 saveAR[21];
 554         u8 saveDACMASK;
 555         u8 saveCR[37];
 556         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 557         u32 saveCURACNTR;
 558         u32 saveCURAPOS;
 559         u32 saveCURABASE;
 560         u32 saveCURBCNTR;
 561         u32 saveCURBPOS;
 562         u32 saveCURBBASE;
 563         u32 saveCURSIZE;
 564         u32 saveDP_B;
 565         u32 saveDP_C;
 566         u32 saveDP_D;
 567         u32 savePIPEA_GMCH_DATA_M;
 568         u32 savePIPEB_GMCH_DATA_M;
 569         u32 savePIPEA_GMCH_DATA_N;
 570         u32 savePIPEB_GMCH_DATA_N;
 571         u32 savePIPEA_DP_LINK_M;
 572         u32 savePIPEB_DP_LINK_M;
 573         u32 savePIPEA_DP_LINK_N;
 574         u32 savePIPEB_DP_LINK_N;
 575         u32 saveFDI_RXA_CTL;
 576         u32 saveFDI_TXA_CTL;
 577         u32 saveFDI_RXB_CTL;
 578         u32 saveFDI_TXB_CTL;
 579         u32 savePFA_CTL_1;
 580         u32 savePFB_CTL_1;
 581         u32 savePFA_WIN_SZ;
 582         u32 savePFB_WIN_SZ;
 583         u32 savePFA_WIN_POS;
 584         u32 savePFB_WIN_POS;
 585         u32 savePCH_DREF_CONTROL;
 586         u32 saveDISP_ARB_CTL;
 587         u32 savePIPEA_DATA_M1;
 588         u32 savePIPEA_DATA_N1;
 589         u32 savePIPEA_LINK_M1;
 590         u32 savePIPEA_LINK_N1;
 591         u32 savePIPEB_DATA_M1;
 592         u32 savePIPEB_DATA_N1;
 593         u32 savePIPEB_LINK_M1;
 594         u32 savePIPEB_LINK_N1;
 595         u32 saveMCHBAR_RENDER_STANDBY;
 596         u32 savePCH_PORT_HOTPLUG;
 597
 598         struct {
 599                 /** Bridge to intel-gtt-ko */
 600                 const struct intel_gtt *gtt;
 601                 /** Memory allocator for GTT stolen memory */
 602                 struct drm_mm stolen;
 603                 /** Memory allocator for GTT */
 604                 struct drm_mm gtt_space;
 605                 /** List of all objects in gtt_space. Used to restore gtt
 606                  * mappings on resume */
 607                 struct list_head gtt_list;
 608
 609                 /** Usable portion of the GTT for GEM */
 610                 unsigned long gtt_start;
 611                 unsigned long gtt_mappable_end;
 612                 unsigned long gtt_end;
 613
 614                 struct io_mapping *gtt_mapping;
 615                 int gtt_mtrr;
 616
 617                 /** PPGTT used for aliasing the PPGTT with the GTT */
 618                 struct i915_hw_ppgtt *aliasing_ppgtt;
 619
 620                 struct shrinker inactive_shrinker;
 621
 622                 /**
 623                  * List of objects currently involved in rendering.
 624                  *
 625                  * Includes buffers having the contents of their GPU caches
 626                  * flushed, not necessarily primitives.  last_rendering_seqno
 627                  * represents when the rendering involved will be completed.
 628                  *
 629                  * A reference is held on the buffer while on this list.
 630                  */
 631                 struct list_head active_list;
 632
 633                 /**
 634                  * List of objects which are not in the ringbuffer but which
 635                  * still have a write_domain which needs to be flushed before
 636                  * unbinding.
 637                  *
 638                  * last_rendering_seqno is 0 while an object is in this list.
 639                  *
 640                  * A reference is held on the buffer while on this list.
 641                  */
 642                 struct list_head flushing_list;
 643
 644                 /**
 645                  * LRU list of objects which are not in the ringbuffer and
 646                  * are ready to unbind, but are still in the GTT.
 647                  *
 648                  * last_rendering_seqno is 0 while an object is in this list.
 649                  *
 650                  * A reference is not held on the buffer while on this list,
 651                  * as merely being GTT-bound shouldn't prevent its being
 652                  * freed, and we'll pull it off the list in the free path.
 653                  */
 654                 struct list_head inactive_list;
 655
 656                 /**
 657                  * LRU list of objects which are not in the ringbuffer but
 658                  * are still pinned in the GTT.
 659                  */
 660                 struct list_head pinned_list;
 661
 662                 /** LRU list of objects with fence regs on them. */
 663                 struct list_head fence_list;
 664
 665                 /**
 666                  * List of objects currently pending being freed.
 667                  *
 668                  * These objects are no longer in use, but due to a signal
 669                  * we were prevented from freeing them at the appointed time.
 670                  */
 671                 struct list_head deferred_free_list;
 672
 673                 /**
 674                  * We leave the user IRQ off as much as possible,
 675                  * but this means that requests will finish and never
 676                  * be retired once the system goes idle. Set a timer to
 677                  * fire periodically while the ring is running. When it
 678                  * fires, go retire requests.
 679                  */
 680                 struct delayed_work retire_work;
 681
 682                 /**
 683                  * Are we in a non-interruptible section of code like
 684                  * modesetting?
 685                  */
 686                 bool interruptible;
 687
 688                 /**
 689                  * Flag if the X Server, and thus DRM, is not currently in
 690                  * control of the device.
 691                  *
 692                  * This is set between LeaveVT and EnterVT.  It needs to be
 693                  * replaced with a semaphore.  It also needs to be
 694                  * transitioned away from for kernel modesetting.
 695                  */
 696                 int suspended;
 697
 698                 /**
 699                  * Flag if the hardware appears to be wedged.
 700                  *
 701                  * This is set when attempts to idle the device timeout.
 702                  * It prevents command submission from occurring and makes
 703                  * every pending request fail
 704                  */
 705                 atomic_t wedged;
 706
 707                 /** Bit 6 swizzling required for X tiling */
 708                 uint32_t bit_6_swizzle_x;
 709                 /** Bit 6 swizzling required for Y tiling */
 710                 uint32_t bit_6_swizzle_y;
 711
 712                 /* storage for physical objects */
 713                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 714
 715                 /* accounting, useful for userland debugging */
 716                 size_t gtt_total;
 717                 size_t mappable_gtt_total;
 718                 size_t object_memory;
 719                 u32 object_count;
 720         } mm;
 721         struct sdvo_device_mapping sdvo_mappings[2];
 722         /* indicate whether the LVDS_BORDER should be enabled or not */
 723         unsigned int lvds_border_bits;
 724         /* Panel fitter placement and size for Ironlake+ */
 725         u32 pch_pf_pos, pch_pf_size;
 726
 727         struct drm_crtc *plane_to_crtc_mapping[3];
 728         struct drm_crtc *pipe_to_crtc_mapping[3];
 729         wait_queue_head_t pending_flip_queue;
 730         bool flip_pending_is_done;
 731
 732         /* Reclocking support */
 733         bool render_reclock_avail;
 734         bool lvds_downclock_avail;
 735         /* indicates the reduced downclock for LVDS*/
 736         int lvds_downclock;
 737         struct work_struct idle_work;
 738         struct timer_list idle_timer;
 739         bool busy;
 740         u16 orig_clock;
 741         int child_dev_num;
 742         struct child_device_config *child_dev;
 743         struct drm_connector *int_lvds_connector;
 744         struct drm_connector *int_edp_connector;
 745
 746         bool mchbar_need_disable;
 747
 748         struct work_struct rps_work;
 749         spinlock_t rps_lock;
 750         u32 pm_iir;
 751
 752         u8 cur_delay;
 753         u8 min_delay;
 754         u8 max_delay;
 755         u8 fmax;
 756         u8 fstart;
 757
 758         u64 last_count1;
 759         unsigned long last_time1;
 760         unsigned long chipset_power;
 761         u64 last_count2;
 762         struct timespec last_time2;
 763         unsigned long gfx_power;
 764         int c_m;
 765         int r_t;
 766         u8 corr;
 767         spinlock_t *mchdev_lock;
 768
 769         enum no_fbc_reason no_fbc_reason;
 770
 771         struct drm_mm_node *compressed_fb;
 772         struct drm_mm_node *compressed_llb;
 773
 774         unsigned long last_gpu_reset;
 775
 776         /* list of fbdev register on this device */
 777         struct intel_fbdev *fbdev;
 778
 779         struct backlight_device *backlight;
 780
 781         struct drm_property *broadcast_rgb_property;
 782         struct drm_property *force_audio_property;
 783 } drm_i915_private_t;
 784
 785 enum hdmi_force_audio {
 786         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
 787         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
 788         HDMI_AUDIO_AUTO,                /* trust EDID */
 789         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 790 };
 791
 792 enum i915_cache_level {
 793         I915_CACHE_NONE,
 794         I915_CACHE_LLC,
 795         I915_CACHE_LLC_MLC, /* gen6+ */
 796 };
 797
 798 struct drm_i915_gem_object {
 799         struct drm_gem_object base;
 800
 801         /** Current space allocated to this object in the GTT, if any. */
 802         struct drm_mm_node *gtt_space;
 803         struct list_head gtt_list;
 804
 805         /** This object's place on the active/flushing/inactive lists */
 806         struct list_head ring_list;
 807         struct list_head mm_list;
 808         /** This object's place on GPU write list */
 809         struct list_head gpu_write_list;
 810         /** This object's place in the batchbuffer or on the eviction list */
 811         struct list_head exec_list;
 812
 813         /**
 814          * This is set if the object is on the active or flushing lists
 815          * (has pending rendering), and is not set if it's on inactive (ready
 816          * to be unbound).
 817          */
 818         unsigned int active:1;
 819
 820         /**
 821          * This is set if the object has been written to since last bound
 822          * to the GTT
 823          */
 824         unsigned int dirty:1;
 825
 826         /**
 827          * This is set if the object has been written to since the last
 828          * GPU flush.
 829          */
 830         unsigned int pending_gpu_write:1;
 831
 832         /**
 833          * Fence register bits (if any) for this object.  Will be set
 834          * as needed when mapped into the GTT.
 835          * Protected by dev->struct_mutex.
 836          */
 837         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
 838
 839         /**
 840          * Advice: are the backing pages purgeable?
 841          */
 842         unsigned int madv:2;
 843
 844         /**
 845          * Current tiling mode for the object.
 846          */
 847         unsigned int tiling_mode:2;
 848         unsigned int tiling_changed:1;
 849
 850         /** How many users have pinned this object in GTT space. The following
 851          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 852          * (via user_pin_count), execbuffer (objects are not allowed multiple
 853          * times for the same batchbuffer), and the framebuffer code. When
 854          * switching/pageflipping, the framebuffer code has at most two buffers
 855          * pinned per crtc.
 856          *
 857          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 858          * bits with absolutely no headroom. So use 4 bits. */
 859         unsigned int pin_count:4;
 860 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 861
 862         /**
 863          * Is the object at the current location in the gtt mappable and
 864          * fenceable? Used to avoid costly recalculations.
 865          */
 866         unsigned int map_and_fenceable:1;
 867
 868         /**
 869          * Whether the current gtt mapping needs to be mappable (and isn't just
 870          * mappable by accident). Track pin and fault separate for a more
 871          * accurate mappable working set.
 872          */
 873         unsigned int fault_mappable:1;
 874         unsigned int pin_mappable:1;
 875
 876         /*
 877          * Is the GPU currently using a fence to access this buffer,
 878          */
 879         unsigned int pending_fenced_gpu_access:1;
 880         unsigned int fenced_gpu_access:1;
 881
 882         unsigned int cache_level:2;
 883
 884         unsigned int has_aliasing_ppgtt_mapping:1;
 885
 886         struct page **pages;
 887
 888         /**
 889          * DMAR support
 890          */
 891         struct scatterlist *sg_list;
 892         int num_sg;
 893
 894         /**
 895          * Used for performing relocations during execbuffer insertion.
 896          */
 897         struct hlist_node exec_node;
 898         unsigned long exec_handle;
 899         struct drm_i915_gem_exec_object2 *exec_entry;
 900
 901         /**
 902          * Current offset of the object in GTT space.
 903          *
 904          * This is the same as gtt_space->start
 905          */
 906         uint32_t gtt_offset;
 907
 908         /** Breadcrumb of last rendering to the buffer. */
 909         uint32_t last_rendering_seqno;
 910         struct intel_ring_buffer *ring;
 911
 912         /** Breadcrumb of last fenced GPU access to the buffer. */
 913         uint32_t last_fenced_seqno;
 914         struct intel_ring_buffer *last_fenced_ring;
 915
 916         /** Current tiling stride for the object, if it's tiled. */
 917         uint32_t stride;
 918
 919         /** Record of address bit 17 of each page at last unbind. */
 920         unsigned long *bit_17;
 921
 922
 923         /**
 924          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 925          * flags which individual pages are valid.
 926          */
 927         uint8_t *page_cpu_valid;
 928
 929         /** User space pin count and filp owning the pin */
 930         uint32_t user_pin_count;
 931         struct drm_file *pin_filp;
 932
 933         /** for phy allocated objects */
 934         struct drm_i915_gem_phys_object *phys_obj;
 935
 936         /**
 937          * Number of crtcs where this object is currently the fb, but
 938          * will be page flipped away on the next vblank.  When it
 939          * reaches 0, dev_priv->pending_flip_queue will be woken up.
 940          */
 941         atomic_t pending_flip;
 942 };
 943
 944 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 945
 946 /**
 947  * Request queue structure.
 948  *
 949  * The request queue allows us to note sequence numbers that have been emitted
 950  * and may be associated with active buffers to be retired.
 951  *
 952  * By keeping this list, we can avoid having to do questionable
 953  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 954  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 955  */
 956 struct drm_i915_gem_request {
 957         /** On Which ring this request was generated */
 958         struct intel_ring_buffer *ring;
 959
 960         /** GEM sequence number associated with this request. */
 961         uint32_t seqno;
 962
 963         /** Postion in the ringbuffer of the end of the request */
 964         u32 tail;
 965
 966         /** Time at which this request was emitted, in jiffies. */
 967         unsigned long emitted_jiffies;
 968
 969         /** global list entry for this request */
 970         struct list_head list;
 971
 972         struct drm_i915_file_private *file_priv;
 973         /** file_priv list entry for this request */
 974         struct list_head client_list;
 975 };
 976
 977 struct drm_i915_file_private {
 978         struct {
 979                 struct spinlock lock;
 980                 struct list_head request_list;
 981         } mm;
 982 };
 983
 984 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
 985
 986 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
 987 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
 988 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
 989 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
 990 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
 991 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
 992 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
 993 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
 994 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
 995 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
 996 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
 997 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
 998 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
 999 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1000 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1001 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1002 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1003 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1004 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1005 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1006
1007 /*
1008  * The genX designation typically refers to the render engine, so render
1009  * capability related checks should use IS_GEN, while display and other checks
1010  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1011  * chips, etc.).
1012  */
1013 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1014 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1015 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1016 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1017 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1018 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1019
1020 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1021 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1022 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1023 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1024
1025 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1026
1027 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1028 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1029
1030 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1031  * rows, which changed the alignment requirements and fence programming.
1032  */
1033 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1034                                                       IS_I915GM(dev)))
1035 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1036 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1037 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1038 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1039 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1040 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1041 /* dsparb controlled by hw only */
1042 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1043
1044 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1045 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1046 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1047
1048 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1049 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1050
1051 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1052 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1053 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1054
1055 #include "i915_trace.h"
1056
1057 extern struct drm_ioctl_desc i915_ioctls[];
1058 extern int i915_max_ioctl;
1059 extern unsigned int i915_fbpercrtc __always_unused;
1060 extern int i915_panel_ignore_lid __read_mostly;
1061 extern unsigned int i915_powersave __read_mostly;
1062 extern int i915_semaphores __read_mostly;
1063 extern unsigned int i915_lvds_downclock __read_mostly;
1064 extern int i915_panel_use_ssc __read_mostly;
1065 extern int i915_vbt_sdvo_panel_type __read_mostly;
1066 extern int i915_enable_rc6 __read_mostly;
1067 extern int i915_enable_fbc __read_mostly;
1068 extern bool i915_enable_hangcheck __read_mostly;
1069 extern bool i915_enable_ppgtt __read_mostly;
1070
1071 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1072 extern int i915_resume(struct drm_device *dev);
1073 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1074 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1075
1076                                 /* i915_dma.c */
1077 extern void i915_kernel_lost_context(struct drm_device * dev);
1078 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1079 extern int i915_driver_unload(struct drm_device *);
1080 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1081 extern void i915_driver_lastclose(struct drm_device * dev);
1082 extern void i915_driver_preclose(struct drm_device *dev,
1083                                  struct drm_file *file_priv);
1084 extern void i915_driver_postclose(struct drm_device *dev,
1085                                   struct drm_file *file_priv);
1086 extern int i915_driver_device_is_agp(struct drm_device * dev);
1087 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1088                               unsigned long arg);
1089 extern int i915_emit_box(struct drm_device *dev,
1090                          struct drm_clip_rect *box,
1091                          int DR1, int DR4);
1092 extern int i915_reset(struct drm_device *dev, u8 flags);
1093 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1094 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1095 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1096 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1097
1098
1099 /* i915_irq.c */
1100 void i915_hangcheck_elapsed(unsigned long data);
1101 void i915_handle_error(struct drm_device *dev, bool wedged);
1102 extern int i915_irq_emit(struct drm_device *dev, void *data,
1103                          struct drm_file *file_priv);
1104 extern int i915_irq_wait(struct drm_device *dev, void *data,
1105                          struct drm_file *file_priv);
1106
1107 extern void intel_irq_init(struct drm_device *dev);
1108
1109 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1110                                 struct drm_file *file_priv);
1111 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1112                                 struct drm_file *file_priv);
1113 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1114                             struct drm_file *file_priv);
1115
1116 void
1117 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1118
1119 void
1120 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1121
1122 void intel_enable_asle(struct drm_device *dev);
1123
1124 #ifdef CONFIG_DEBUG_FS
1125 extern void i915_destroy_error_state(struct drm_device *dev);
1126 #else
1127 #define i915_destroy_error_state(x)
1128 #endif
1129
1130
1131 /* i915_gem.c */
1132 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1133                         struct drm_file *file_priv);
1134 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1135                           struct drm_file *file_priv);
1136 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1137                          struct drm_file *file_priv);
1138 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1139                           struct drm_file *file_priv);
1140 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1141                         struct drm_file *file_priv);
1142 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1143                         struct drm_file *file_priv);
1144 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1145                               struct drm_file *file_priv);
1146 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1147                              struct drm_file *file_priv);
1148 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1149                         struct drm_file *file_priv);
1150 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1151                          struct drm_file *file_priv);
1152 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1153                        struct drm_file *file_priv);
1154 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1155                          struct drm_file *file_priv);
1156 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1157                         struct drm_file *file_priv);
1158 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1159                             struct drm_file *file_priv);
1160 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1161                            struct drm_file *file_priv);
1162 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1163                            struct drm_file *file_priv);
1164 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1165                            struct drm_file *file_priv);
1166 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1167                         struct drm_file *file_priv);
1168 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1169                         struct drm_file *file_priv);
1170 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1171                                 struct drm_file *file_priv);
1172 void i915_gem_load(struct drm_device *dev);
1173 int i915_gem_init_object(struct drm_gem_object *obj);
1174 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1175                                      uint32_t invalidate_domains,
1176                                      uint32_t flush_domains);
1177 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1178                                                   size_t size);
1179 void i915_gem_free_object(struct drm_gem_object *obj);
1180 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1181                                      uint32_t alignment,
1182                                      bool map_and_fenceable);
1183 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1184 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1185 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1186 void i915_gem_lastclose(struct drm_device *dev);
1187
1188 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1189 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1190 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1191                                     struct intel_ring_buffer *ring,
1192                                     u32 seqno);
1193
1194 int i915_gem_dumb_create(struct drm_file *file_priv,
1195                          struct drm_device *dev,
1196                          struct drm_mode_create_dumb *args);
1197 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1198                       uint32_t handle, uint64_t *offset);
1199 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1200                           uint32_t handle);
1201 /**
1202  * Returns true if seq1 is later than seq2.
1203  */
1204 static inline bool
1205 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1206 {
1207         return (int32_t)(seq1 - seq2) >= 0;
1208 }
1209
1210 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1211
1212 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1213                                            struct intel_ring_buffer *pipelined);
1214 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1215
1216 static inline void
1217 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1218 {
1219         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1220                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1221                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1222         }
1223 }
1224
1225 static inline void
1226 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1227 {
1228         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1229                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1230                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1231         }
1232 }
1233
1234 void i915_gem_retire_requests(struct drm_device *dev);
1235 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1236
1237 void i915_gem_reset(struct drm_device *dev);
1238 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1239 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1240                                             uint32_t read_domains,
1241                                             uint32_t write_domain);
1242 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1243 int __must_check i915_gem_init_hw(struct drm_device *dev);
1244 void i915_gem_init_swizzling(struct drm_device *dev);
1245 void i915_gem_init_ppgtt(struct drm_device *dev);
1246 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1247 void i915_gem_do_init(struct drm_device *dev,
1248                       unsigned long start,
1249                       unsigned long mappable_end,
1250                       unsigned long end);
1251 int __must_check i915_gpu_idle(struct drm_device *dev, bool do_retire);
1252 int __must_check i915_gem_idle(struct drm_device *dev);
1253 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1254                                   struct drm_file *file,
1255                                   struct drm_i915_gem_request *request);
1256 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1257                                    uint32_t seqno,
1258                                    bool do_retire);
1259 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1260 int __must_check
1261 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1262                                   bool write);
1263 int __must_check
1264 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1265                                      u32 alignment,
1266                                      struct intel_ring_buffer *pipelined);
1267 int i915_gem_attach_phys_object(struct drm_device *dev,
1268                                 struct drm_i915_gem_object *obj,
1269                                 int id,
1270                                 int align);
1271 void i915_gem_detach_phys_object(struct drm_device *dev,
1272                                  struct drm_i915_gem_object *obj);
1273 void i915_gem_free_all_phys_object(struct drm_device *dev);
1274 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1275
1276 uint32_t
1277 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1278                                     uint32_t size,
1279                                     int tiling_mode);
1280
1281 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1282                                     enum i915_cache_level cache_level);
1283
1284 /* i915_gem_gtt.c */
1285 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1286 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1287 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1288                             struct drm_i915_gem_object *obj,
1289                             enum i915_cache_level cache_level);
1290 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1291                               struct drm_i915_gem_object *obj);
1292
1293 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1294 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1295 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1296                                 enum i915_cache_level cache_level);
1297 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1298
1299 /* i915_gem_evict.c */
1300 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1301                                           unsigned alignment, bool mappable);
1302 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1303                                            bool purgeable_only);
1304 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1305                                          bool purgeable_only);
1306
1307 /* i915_gem_tiling.c */
1308 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1309 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1310 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1311
1312 /* i915_gem_debug.c */
1313 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1314                           const char *where, uint32_t mark);
1315 #if WATCH_LISTS
1316 int i915_verify_lists(struct drm_device *dev);
1317 #else
1318 #define i915_verify_lists(dev) 0
1319 #endif
1320 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1321                                      int handle);
1322 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1323                           const char *where, uint32_t mark);
1324
1325 /* i915_debugfs.c */
1326 int i915_debugfs_init(struct drm_minor *minor);
1327 void i915_debugfs_cleanup(struct drm_minor *minor);
1328
1329 /* i915_suspend.c */
1330 extern int i915_save_state(struct drm_device *dev);
1331 extern int i915_restore_state(struct drm_device *dev);
1332
1333 /* i915_suspend.c */
1334 extern int i915_save_state(struct drm_device *dev);
1335 extern int i915_restore_state(struct drm_device *dev);
1336
1337 /* intel_i2c.c */
1338 extern int intel_setup_gmbus(struct drm_device *dev);
1339 extern void intel_teardown_gmbus(struct drm_device *dev);
1340 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1341 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1342 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1343 {
1344         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1345 }
1346 extern void intel_i2c_reset(struct drm_device *dev);
1347
1348 /* intel_opregion.c */
1349 extern int intel_opregion_setup(struct drm_device *dev);
1350 #ifdef CONFIG_ACPI
1351 extern void intel_opregion_init(struct drm_device *dev);
1352 extern void intel_opregion_fini(struct drm_device *dev);
1353 extern void intel_opregion_asle_intr(struct drm_device *dev);
1354 extern void intel_opregion_gse_intr(struct drm_device *dev);
1355 extern void intel_opregion_enable_asle(struct drm_device *dev);
1356 #else
1357 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1358 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1359 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1360 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1361 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1362 #endif
1363
1364 /* intel_acpi.c */
1365 #ifdef CONFIG_ACPI
1366 extern void intel_register_dsm_handler(void);
1367 extern void intel_unregister_dsm_handler(void);
1368 #else
1369 static inline void intel_register_dsm_handler(void) { return; }
1370 static inline void intel_unregister_dsm_handler(void) { return; }
1371 #endif /* CONFIG_ACPI */
1372
1373 /* modesetting */
1374 extern void intel_modeset_init(struct drm_device *dev);
1375 extern void intel_modeset_gem_init(struct drm_device *dev);
1376 extern void intel_modeset_cleanup(struct drm_device *dev);
1377 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1378 extern bool intel_fbc_enabled(struct drm_device *dev);
1379 extern void intel_disable_fbc(struct drm_device *dev);
1380 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1381 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1382 extern void ironlake_enable_rc6(struct drm_device *dev);
1383 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1384 extern void intel_detect_pch(struct drm_device *dev);
1385 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1386
1387 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1388 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1389 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1390 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1391
1392 /* overlay */
1393 #ifdef CONFIG_DEBUG_FS
1394 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1395 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1396
1397 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1398 extern void intel_display_print_error_state(struct seq_file *m,
1399                                             struct drm_device *dev,
1400                                             struct intel_display_error_state *error);
1401 #endif
1402
1403 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1404
1405 #define BEGIN_LP_RING(n) \
1406         intel_ring_begin(LP_RING(dev_priv), (n))
1407
1408 #define OUT_RING(x) \
1409         intel_ring_emit(LP_RING(dev_priv), x)
1410
1411 #define ADVANCE_LP_RING() \
1412         intel_ring_advance(LP_RING(dev_priv))
1413
1414 /**
1415  * Lock test for when it's just for synchronization of ring access.
1416  *
1417  * In that case, we don't need to do it when GEM is initialized as nobody else
1418  * has access to the ring.
1419  */
1420 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
1421         if (LP_RING(dev->dev_private)->obj == NULL)                     \
1422                 LOCK_TEST_WITH_RETURN(dev, file);                       \
1423 } while (0)
1424
1425 /* On SNB platform, before reading ring registers forcewake bit
1426  * must be set to prevent GT core from power down and stale values being
1427  * returned.
1428  */
1429 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1430 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1431 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1432
1433 /* We give fast paths for the really cool registers */
1434 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1435         (((dev_priv)->info->gen >= 6) && \
1436          ((reg) < 0x40000) &&            \
1437          ((reg) != FORCEWAKE))
1438
1439 #define __i915_read(x, y) \
1440         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1441
1442 __i915_read(8, b)
1443 __i915_read(16, w)
1444 __i915_read(32, l)
1445 __i915_read(64, q)
1446 #undef __i915_read
1447
1448 #define __i915_write(x, y) \
1449         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1450
1451 __i915_write(8, b)
1452 __i915_write(16, w)
1453 __i915_write(32, l)
1454 __i915_write(64, q)
1455 #undef __i915_write
1456
1457 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1458 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1459
1460 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1461 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1462 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1463 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1464
1465 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1466 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1467 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1468 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1469
1470 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1471 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1472
1473 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1474 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1475
1476
1477 #endif