1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
44 /* General customization:
47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
49 #define DRIVER_NAME "i915"
50 #define DRIVER_DESC "Intel Graphics"
51 #define DRIVER_DATE "20080730"
59 #define pipe_name(p) ((p) + 'A')
67 #define transcoder_name(t) ((t) + 'A')
74 #define plane_name(p) ((p) + 'A')
84 #define port_name(p) ((p) + 'A')
86 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
88 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
90 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
91 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
92 if ((intel_encoder)->base.crtc == (__crtc))
94 struct intel_pch_pll
{
95 int refcount
; /* count of number of CRTCs sharing this PLL */
96 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
97 bool on
; /* is the PLL actually active? Disabled during modeset */
102 #define I915_NUM_PLLS 2
104 struct intel_ddi_plls
{
110 /* Interface history:
113 * 1.2: Add Power Management
114 * 1.3: Add vblank support
115 * 1.4: Fix cmdbuffer path, add heap destroy
116 * 1.5: Add vblank pipe configuration
117 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
118 * - Support vertical blank on secondary display pipe
120 #define DRIVER_MAJOR 1
121 #define DRIVER_MINOR 6
122 #define DRIVER_PATCHLEVEL 0
124 #define WATCH_COHERENCY 0
125 #define WATCH_LISTS 0
128 #define I915_GEM_PHYS_CURSOR_0 1
129 #define I915_GEM_PHYS_CURSOR_1 2
130 #define I915_GEM_PHYS_OVERLAY_REGS 3
131 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
133 struct drm_i915_gem_phys_object
{
135 struct page
**page_list
;
136 drm_dma_handle_t
*handle
;
137 struct drm_i915_gem_object
*cur_obj
;
140 struct opregion_header
;
141 struct opregion_acpi
;
142 struct opregion_swsci
;
143 struct opregion_asle
;
144 struct drm_i915_private
;
146 struct intel_opregion
{
147 struct opregion_header __iomem
*header
;
148 struct opregion_acpi __iomem
*acpi
;
149 struct opregion_swsci __iomem
*swsci
;
150 struct opregion_asle __iomem
*asle
;
152 u32 __iomem
*lid_state
;
154 #define OPREGION_SIZE (8*1024)
156 struct intel_overlay
;
157 struct intel_overlay_error_state
;
159 struct drm_i915_master_private
{
160 drm_local_map_t
*sarea
;
161 struct _drm_i915_sarea
*sarea_priv
;
163 #define I915_FENCE_REG_NONE -1
164 #define I915_MAX_NUM_FENCES 16
165 /* 16 fences + sign bit for FENCE_REG_NONE */
166 #define I915_MAX_NUM_FENCE_BITS 5
168 struct drm_i915_fence_reg
{
169 struct list_head lru_list
;
170 struct drm_i915_gem_object
*obj
;
174 struct sdvo_device_mapping
{
183 struct intel_display_error_state
;
185 struct drm_i915_error_state
{
191 bool waiting
[I915_NUM_RINGS
];
192 u32 pipestat
[I915_MAX_PIPES
];
193 u32 tail
[I915_NUM_RINGS
];
194 u32 head
[I915_NUM_RINGS
];
195 u32 ipeir
[I915_NUM_RINGS
];
196 u32 ipehr
[I915_NUM_RINGS
];
197 u32 instdone
[I915_NUM_RINGS
];
198 u32 acthd
[I915_NUM_RINGS
];
199 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
200 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
201 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
202 /* our own tracking of ring head and tail */
203 u32 cpu_ring_head
[I915_NUM_RINGS
];
204 u32 cpu_ring_tail
[I915_NUM_RINGS
];
205 u32 error
; /* gen6+ */
206 u32 err_int
; /* gen7 */
207 u32 instpm
[I915_NUM_RINGS
];
208 u32 instps
[I915_NUM_RINGS
];
209 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
210 u32 seqno
[I915_NUM_RINGS
];
212 u32 fault_reg
[I915_NUM_RINGS
];
214 u32 faddr
[I915_NUM_RINGS
];
215 u64 fence
[I915_MAX_NUM_FENCES
];
217 struct drm_i915_error_ring
{
218 struct drm_i915_error_object
{
222 } *ringbuffer
, *batchbuffer
;
223 struct drm_i915_error_request
{
229 } ring
[I915_NUM_RINGS
];
230 struct drm_i915_error_buffer
{
237 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
244 } *active_bo
, *pinned_bo
;
245 u32 active_bo_count
, pinned_bo_count
;
246 struct intel_overlay_error_state
*overlay
;
247 struct intel_display_error_state
*display
;
250 struct drm_i915_display_funcs
{
251 bool (*fbc_enabled
)(struct drm_device
*dev
);
252 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
253 void (*disable_fbc
)(struct drm_device
*dev
);
254 int (*get_display_clock_speed
)(struct drm_device
*dev
);
255 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
256 void (*update_wm
)(struct drm_device
*dev
);
257 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
258 uint32_t sprite_width
, int pixel_size
);
259 void (*update_linetime_wm
)(struct drm_device
*dev
, int pipe
,
260 struct drm_display_mode
*mode
);
261 void (*modeset_global_resources
)(struct drm_device
*dev
);
262 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
263 struct drm_display_mode
*mode
,
264 struct drm_display_mode
*adjusted_mode
,
266 struct drm_framebuffer
*old_fb
);
267 void (*crtc_enable
)(struct drm_crtc
*crtc
);
268 void (*crtc_disable
)(struct drm_crtc
*crtc
);
269 void (*off
)(struct drm_crtc
*crtc
);
270 void (*write_eld
)(struct drm_connector
*connector
,
271 struct drm_crtc
*crtc
);
272 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
273 void (*init_clock_gating
)(struct drm_device
*dev
);
274 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
275 struct drm_framebuffer
*fb
,
276 struct drm_i915_gem_object
*obj
);
277 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
279 /* clock updates for mode set */
281 /* render clock increase/decrease */
282 /* display clock increase/decrease */
283 /* pll clock increase/decrease */
286 struct drm_i915_gt_funcs
{
287 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
288 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
291 #define DEV_INFO_FLAGS \
292 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
293 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
294 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
295 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
296 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
297 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
298 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
299 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
300 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
301 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
302 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
303 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
304 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
305 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
306 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
307 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
308 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
309 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
310 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
311 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
312 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
313 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
314 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
315 DEV_INFO_FLAG(has_llc)
317 struct intel_device_info
{
336 u8 cursor_needs_physical
:1;
338 u8 overlay_needs_physical
:1;
345 #define I915_PPGTT_PD_ENTRIES 512
346 #define I915_PPGTT_PT_ENTRIES 1024
347 struct i915_hw_ppgtt
{
348 struct drm_device
*dev
;
349 unsigned num_pd_entries
;
350 struct page
**pt_pages
;
352 dma_addr_t
*pt_dma_addr
;
353 dma_addr_t scratch_page_dma_addr
;
357 /* This must match up with the value previously used for execbuf2.rsvd1. */
358 #define DEFAULT_CONTEXT_ID 0
359 struct i915_hw_context
{
362 struct drm_i915_file_private
*file_priv
;
363 struct intel_ring_buffer
*ring
;
364 struct drm_i915_gem_object
*obj
;
368 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
369 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
370 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
371 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
372 FBC_BAD_PLANE
, /* fbc not supported on plane */
373 FBC_NOT_TILED
, /* buffer not tiled */
374 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
379 PCH_NONE
= 0, /* No PCH present */
380 PCH_IBX
, /* Ibexpeak PCH */
381 PCH_CPT
, /* Cougarpoint PCH */
382 PCH_LPT
, /* Lynxpoint PCH */
385 #define QUIRK_PIPEA_FORCE (1<<0)
386 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
387 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
390 struct intel_fbc_work
;
393 struct i2c_adapter adapter
;
397 struct i2c_algo_bit_data bit_algo
;
398 struct drm_i915_private
*dev_priv
;
401 struct i915_suspend_saved_registers
{
422 u32 saveTRANS_HTOTAL_A
;
423 u32 saveTRANS_HBLANK_A
;
424 u32 saveTRANS_HSYNC_A
;
425 u32 saveTRANS_VTOTAL_A
;
426 u32 saveTRANS_VBLANK_A
;
427 u32 saveTRANS_VSYNC_A
;
435 u32 savePFIT_PGM_RATIOS
;
436 u32 saveBLC_HIST_CTL
;
438 u32 saveBLC_PWM_CTL2
;
439 u32 saveBLC_CPU_PWM_CTL
;
440 u32 saveBLC_CPU_PWM_CTL2
;
453 u32 saveTRANS_HTOTAL_B
;
454 u32 saveTRANS_HBLANK_B
;
455 u32 saveTRANS_HSYNC_B
;
456 u32 saveTRANS_VTOTAL_B
;
457 u32 saveTRANS_VBLANK_B
;
458 u32 saveTRANS_VSYNC_B
;
472 u32 savePP_ON_DELAYS
;
473 u32 savePP_OFF_DELAYS
;
481 u32 savePFIT_CONTROL
;
482 u32 save_palette_a
[256];
483 u32 save_palette_b
[256];
484 u32 saveDPFC_CB_BASE
;
485 u32 saveFBC_CFB_BASE
;
488 u32 saveFBC_CONTROL2
;
498 u32 saveCACHE_MODE_0
;
499 u32 saveMI_ARB_STATE
;
510 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
521 u32 savePIPEA_GMCH_DATA_M
;
522 u32 savePIPEB_GMCH_DATA_M
;
523 u32 savePIPEA_GMCH_DATA_N
;
524 u32 savePIPEB_GMCH_DATA_N
;
525 u32 savePIPEA_DP_LINK_M
;
526 u32 savePIPEB_DP_LINK_M
;
527 u32 savePIPEA_DP_LINK_N
;
528 u32 savePIPEB_DP_LINK_N
;
539 u32 savePCH_DREF_CONTROL
;
540 u32 saveDISP_ARB_CTL
;
541 u32 savePIPEA_DATA_M1
;
542 u32 savePIPEA_DATA_N1
;
543 u32 savePIPEA_LINK_M1
;
544 u32 savePIPEA_LINK_N1
;
545 u32 savePIPEB_DATA_M1
;
546 u32 savePIPEB_DATA_N1
;
547 u32 savePIPEB_LINK_M1
;
548 u32 savePIPEB_LINK_N1
;
549 u32 saveMCHBAR_RENDER_STANDBY
;
550 u32 savePCH_PORT_HOTPLUG
;
553 struct intel_gen6_power_mgmt
{
554 struct work_struct work
;
556 /* lock - irqsave spinlock that protectects the work_struct and
560 /* The below variables an all the rps hw state are protected by
561 * dev->struct mutext. */
566 struct delayed_work delayed_resume_work
;
569 * Protects RPS/RC6 register access and PCU communication.
570 * Must be taken after struct_mutex if nested.
572 struct mutex hw_lock
;
575 struct intel_ilk_power_mgmt
{
583 unsigned long last_time1
;
584 unsigned long chipset_power
;
586 struct timespec last_time2
;
587 unsigned long gfx_power
;
593 struct drm_i915_gem_object
*pwrctx
;
594 struct drm_i915_gem_object
*renderctx
;
597 struct i915_dri1_state
{
598 unsigned allow_batchbuffer
: 1;
599 u32 __iomem
*gfx_hws_cpu_addr
;
610 struct intel_l3_parity
{
612 struct work_struct error_work
;
615 typedef struct drm_i915_private
{
616 struct drm_device
*dev
;
618 const struct intel_device_info
*info
;
620 int relative_constants_mode
;
624 struct drm_i915_gt_funcs gt
;
625 /** gt_fifo_count and the subsequent register write are synchronized
626 * with dev->struct_mutex. */
627 unsigned gt_fifo_count
;
628 /** forcewake_count is protected by gt_lock */
629 unsigned forcewake_count
;
630 /** gt_lock is also taken in irq contexts. */
631 struct spinlock gt_lock
;
633 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
635 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
636 * controller on different i2c buses. */
637 struct mutex gmbus_mutex
;
640 * Base address of the gmbus and gpio block.
642 uint32_t gpio_mmio_base
;
644 struct pci_dev
*bridge_dev
;
645 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
648 drm_dma_handle_t
*status_page_dmah
;
649 struct resource mch_res
;
651 atomic_t irq_received
;
653 /* protects the irq masks */
656 /* DPIO indirect register protection */
657 spinlock_t dpio_lock
;
659 /** Cached value of IMR to avoid reads in updating the bitfield */
665 u32 hotplug_supported_mask
;
666 struct work_struct hotplug_work
;
671 /* For hangcheck timer */
672 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
673 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
674 struct timer_list hangcheck_timer
;
676 uint32_t last_acthd
[I915_NUM_RINGS
];
677 uint32_t prev_instdone
[I915_NUM_INSTDONE_REG
];
679 unsigned int stop_rings
;
681 unsigned long cfb_size
;
683 enum plane cfb_plane
;
685 struct intel_fbc_work
*fbc_work
;
687 struct intel_opregion opregion
;
690 struct intel_overlay
*overlay
;
691 bool sprite_scaling_enabled
;
694 int backlight_level
; /* restore backlight to this value */
695 bool backlight_enabled
;
696 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
697 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
699 /* Feature bits from the VBIOS */
700 unsigned int int_tv_support
:1;
701 unsigned int lvds_dither
:1;
702 unsigned int lvds_vbt
:1;
703 unsigned int int_crt_support
:1;
704 unsigned int lvds_use_ssc
:1;
705 unsigned int display_clock_mode
:1;
707 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
717 struct edp_power_seq pps
;
719 bool no_aux_handshake
;
722 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
723 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
724 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
726 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
728 spinlock_t error_lock
;
729 /* Protected by dev->error_lock. */
730 struct drm_i915_error_state
*first_error
;
731 struct work_struct error_work
;
732 struct completion error_completion
;
733 struct workqueue_struct
*wq
;
735 /* Display functions */
736 struct drm_i915_display_funcs display
;
738 /* PCH chipset type */
739 enum intel_pch pch_type
;
740 unsigned short pch_id
;
742 unsigned long quirks
;
748 /** Bridge to intel-gtt-ko */
749 struct intel_gtt
*gtt
;
750 /** Memory allocator for GTT stolen memory */
751 struct drm_mm stolen
;
752 /** Memory allocator for GTT */
753 struct drm_mm gtt_space
;
754 /** List of all objects in gtt_space. Used to restore gtt
755 * mappings on resume */
756 struct list_head bound_list
;
758 * List of objects which are not bound to the GTT (thus
759 * are idle and not used by the GPU) but still have
760 * (presumably uncached) pages still attached.
762 struct list_head unbound_list
;
764 /** Usable portion of the GTT for GEM */
765 unsigned long gtt_start
;
766 unsigned long gtt_mappable_end
;
767 unsigned long gtt_end
;
769 struct io_mapping
*gtt_mapping
;
770 phys_addr_t gtt_base_addr
;
773 /** PPGTT used for aliasing the PPGTT with the GTT */
774 struct i915_hw_ppgtt
*aliasing_ppgtt
;
776 struct shrinker inactive_shrinker
;
779 * List of objects currently involved in rendering.
781 * Includes buffers having the contents of their GPU caches
782 * flushed, not necessarily primitives. last_rendering_seqno
783 * represents when the rendering involved will be completed.
785 * A reference is held on the buffer while on this list.
787 struct list_head active_list
;
790 * LRU list of objects which are not in the ringbuffer and
791 * are ready to unbind, but are still in the GTT.
793 * last_rendering_seqno is 0 while an object is in this list.
795 * A reference is not held on the buffer while on this list,
796 * as merely being GTT-bound shouldn't prevent its being
797 * freed, and we'll pull it off the list in the free path.
799 struct list_head inactive_list
;
801 /** LRU list of objects with fence regs on them. */
802 struct list_head fence_list
;
805 * We leave the user IRQ off as much as possible,
806 * but this means that requests will finish and never
807 * be retired once the system goes idle. Set a timer to
808 * fire periodically while the ring is running. When it
809 * fires, go retire requests.
811 struct delayed_work retire_work
;
814 * Are we in a non-interruptible section of code like
820 * Flag if the X Server, and thus DRM, is not currently in
821 * control of the device.
823 * This is set between LeaveVT and EnterVT. It needs to be
824 * replaced with a semaphore. It also needs to be
825 * transitioned away from for kernel modesetting.
830 * Flag if the hardware appears to be wedged.
832 * This is set when attempts to idle the device timeout.
833 * It prevents command submission from occurring and makes
834 * every pending request fail
838 /** Bit 6 swizzling required for X tiling */
839 uint32_t bit_6_swizzle_x
;
840 /** Bit 6 swizzling required for Y tiling */
841 uint32_t bit_6_swizzle_y
;
843 /* storage for physical objects */
844 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
846 /* accounting, useful for userland debugging */
848 size_t mappable_gtt_total
;
849 size_t object_memory
;
853 /* Kernel Modesetting */
855 struct sdvo_device_mapping sdvo_mappings
[2];
856 /* indicate whether the LVDS_BORDER should be enabled or not */
857 unsigned int lvds_border_bits
;
858 /* Panel fitter placement and size for Ironlake+ */
859 u32 pch_pf_pos
, pch_pf_size
;
861 struct drm_crtc
*plane_to_crtc_mapping
[3];
862 struct drm_crtc
*pipe_to_crtc_mapping
[3];
863 wait_queue_head_t pending_flip_queue
;
865 struct intel_pch_pll pch_plls
[I915_NUM_PLLS
];
866 struct intel_ddi_plls ddi_plls
;
868 /* Reclocking support */
869 bool render_reclock_avail
;
870 bool lvds_downclock_avail
;
871 /* indicates the reduced downclock for LVDS*/
875 struct child_device_config
*child_dev
;
877 bool mchbar_need_disable
;
879 struct intel_l3_parity l3_parity
;
881 /* gen6+ rps state */
882 struct intel_gen6_power_mgmt rps
;
884 /* ilk-only ips/rps state. Everything in here is protected by the global
885 * mchdev_lock in intel_pm.c */
886 struct intel_ilk_power_mgmt ips
;
888 enum no_fbc_reason no_fbc_reason
;
890 struct drm_mm_node
*compressed_fb
;
891 struct drm_mm_node
*compressed_llb
;
893 unsigned long last_gpu_reset
;
895 /* list of fbdev register on this device */
896 struct intel_fbdev
*fbdev
;
899 * The console may be contended at resume, but we don't
900 * want it to block on it.
902 struct work_struct console_resume_work
;
904 struct backlight_device
*backlight
;
906 struct drm_property
*broadcast_rgb_property
;
907 struct drm_property
*force_audio_property
;
909 bool hw_contexts_disabled
;
910 uint32_t hw_context_size
;
912 struct i915_suspend_saved_registers regfile
;
914 /* Old dri1 support infrastructure, beware the dragons ya fools entering
916 struct i915_dri1_state dri1
;
917 } drm_i915_private_t
;
919 /* Iterate over initialised rings */
920 #define for_each_ring(ring__, dev_priv__, i__) \
921 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
922 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
924 enum hdmi_force_audio
{
925 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
926 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
927 HDMI_AUDIO_AUTO
, /* trust EDID */
928 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
931 enum i915_cache_level
{
934 I915_CACHE_LLC_MLC
, /* gen6+, in docs at least! */
937 struct drm_i915_gem_object_ops
{
938 /* Interface between the GEM object and its backing storage.
939 * get_pages() is called once prior to the use of the associated set
940 * of pages before to binding them into the GTT, and put_pages() is
941 * called after we no longer need them. As we expect there to be
942 * associated cost with migrating pages between the backing storage
943 * and making them available for the GPU (e.g. clflush), we may hold
944 * onto the pages after they are no longer referenced by the GPU
945 * in case they may be used again shortly (for example migrating the
946 * pages to a different memory domain within the GTT). put_pages()
947 * will therefore most likely be called when the object itself is
948 * being released or under memory pressure (where we attempt to
949 * reap pages for the shrinker).
951 int (*get_pages
)(struct drm_i915_gem_object
*);
952 void (*put_pages
)(struct drm_i915_gem_object
*);
955 struct drm_i915_gem_object
{
956 struct drm_gem_object base
;
958 const struct drm_i915_gem_object_ops
*ops
;
960 /** Current space allocated to this object in the GTT, if any. */
961 struct drm_mm_node
*gtt_space
;
962 struct list_head gtt_list
;
964 /** This object's place on the active/inactive lists */
965 struct list_head ring_list
;
966 struct list_head mm_list
;
967 /** This object's place in the batchbuffer or on the eviction list */
968 struct list_head exec_list
;
971 * This is set if the object is on the active lists (has pending
972 * rendering and so a non-zero seqno), and is not set if it i s on
973 * inactive (ready to be unbound) list.
975 unsigned int active
:1;
978 * This is set if the object has been written to since last bound
981 unsigned int dirty
:1;
984 * Fence register bits (if any) for this object. Will be set
985 * as needed when mapped into the GTT.
986 * Protected by dev->struct_mutex.
988 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
991 * Advice: are the backing pages purgeable?
996 * Current tiling mode for the object.
998 unsigned int tiling_mode
:2;
1000 * Whether the tiling parameters for the currently associated fence
1001 * register have changed. Note that for the purposes of tracking
1002 * tiling changes we also treat the unfenced register, the register
1003 * slot that the object occupies whilst it executes a fenced
1004 * command (such as BLT on gen2/3), as a "fence".
1006 unsigned int fence_dirty
:1;
1008 /** How many users have pinned this object in GTT space. The following
1009 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1010 * (via user_pin_count), execbuffer (objects are not allowed multiple
1011 * times for the same batchbuffer), and the framebuffer code. When
1012 * switching/pageflipping, the framebuffer code has at most two buffers
1015 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1016 * bits with absolutely no headroom. So use 4 bits. */
1017 unsigned int pin_count
:4;
1018 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1021 * Is the object at the current location in the gtt mappable and
1022 * fenceable? Used to avoid costly recalculations.
1024 unsigned int map_and_fenceable
:1;
1027 * Whether the current gtt mapping needs to be mappable (and isn't just
1028 * mappable by accident). Track pin and fault separate for a more
1029 * accurate mappable working set.
1031 unsigned int fault_mappable
:1;
1032 unsigned int pin_mappable
:1;
1035 * Is the GPU currently using a fence to access this buffer,
1037 unsigned int pending_fenced_gpu_access
:1;
1038 unsigned int fenced_gpu_access
:1;
1040 unsigned int cache_level
:2;
1042 unsigned int has_aliasing_ppgtt_mapping
:1;
1043 unsigned int has_global_gtt_mapping
:1;
1044 unsigned int has_dma_mapping
:1;
1046 struct sg_table
*pages
;
1047 int pages_pin_count
;
1049 /* prime dma-buf support */
1050 void *dma_buf_vmapping
;
1054 * Used for performing relocations during execbuffer insertion.
1056 struct hlist_node exec_node
;
1057 unsigned long exec_handle
;
1058 struct drm_i915_gem_exec_object2
*exec_entry
;
1061 * Current offset of the object in GTT space.
1063 * This is the same as gtt_space->start
1065 uint32_t gtt_offset
;
1067 struct intel_ring_buffer
*ring
;
1069 /** Breadcrumb of last rendering to the buffer. */
1070 uint32_t last_read_seqno
;
1071 uint32_t last_write_seqno
;
1072 /** Breadcrumb of last fenced GPU access to the buffer. */
1073 uint32_t last_fenced_seqno
;
1075 /** Current tiling stride for the object, if it's tiled. */
1078 /** Record of address bit 17 of each page at last unbind. */
1079 unsigned long *bit_17
;
1081 /** User space pin count and filp owning the pin */
1082 uint32_t user_pin_count
;
1083 struct drm_file
*pin_filp
;
1085 /** for phy allocated objects */
1086 struct drm_i915_gem_phys_object
*phys_obj
;
1089 * Number of crtcs where this object is currently the fb, but
1090 * will be page flipped away on the next vblank. When it
1091 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1093 atomic_t pending_flip
;
1096 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1099 * Request queue structure.
1101 * The request queue allows us to note sequence numbers that have been emitted
1102 * and may be associated with active buffers to be retired.
1104 * By keeping this list, we can avoid having to do questionable
1105 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1106 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1108 struct drm_i915_gem_request
{
1109 /** On Which ring this request was generated */
1110 struct intel_ring_buffer
*ring
;
1112 /** GEM sequence number associated with this request. */
1115 /** Postion in the ringbuffer of the end of the request */
1118 /** Time at which this request was emitted, in jiffies. */
1119 unsigned long emitted_jiffies
;
1121 /** global list entry for this request */
1122 struct list_head list
;
1124 struct drm_i915_file_private
*file_priv
;
1125 /** file_priv list entry for this request */
1126 struct list_head client_list
;
1129 struct drm_i915_file_private
{
1131 struct spinlock lock
;
1132 struct list_head request_list
;
1134 struct idr context_idr
;
1137 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1139 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1140 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1141 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1142 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1143 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1144 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1145 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1146 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1147 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1148 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1149 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1150 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1151 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1152 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1153 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1154 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1155 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1156 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1157 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1158 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1159 (dev)->pci_device == 0x0152 || \
1160 (dev)->pci_device == 0x015a)
1161 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1162 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1163 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1164 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1165 ((dev)->pci_device & 0xFF00) == 0x0A00)
1168 * The genX designation typically refers to the render engine, so render
1169 * capability related checks should use IS_GEN, while display and other checks
1170 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1173 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1174 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1175 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1176 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1177 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1178 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1180 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1181 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1182 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1183 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1185 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1186 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1188 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1189 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1191 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1192 * rows, which changed the alignment requirements and fence programming.
1194 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1196 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1197 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1198 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1199 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1200 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1201 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1202 /* dsparb controlled by hw only */
1203 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1205 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1206 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1207 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1209 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1211 #define HAS_DDI(dev) (IS_HASWELL(dev))
1213 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1214 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1215 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1216 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1217 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1218 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1220 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1221 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1222 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1223 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1224 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1226 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1228 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1230 #define GT_FREQUENCY_MULTIPLIER 50
1232 #include "i915_trace.h"
1235 * RC6 is a special power stage which allows the GPU to enter an very
1236 * low-voltage mode when idle, using down to 0V while at this stage. This
1237 * stage is entered automatically when the GPU is idle when RC6 support is
1238 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1240 * There are different RC6 modes available in Intel GPU, which differentiate
1241 * among each other with the latency required to enter and leave RC6 and
1242 * voltage consumed by the GPU in different states.
1244 * The combination of the following flags define which states GPU is allowed
1245 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1246 * RC6pp is deepest RC6. Their support by hardware varies according to the
1247 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1248 * which brings the most power savings; deeper states save more power, but
1249 * require higher latency to switch to and wake up.
1251 #define INTEL_RC6_ENABLE (1<<0)
1252 #define INTEL_RC6p_ENABLE (1<<1)
1253 #define INTEL_RC6pp_ENABLE (1<<2)
1255 extern struct drm_ioctl_desc i915_ioctls
[];
1256 extern int i915_max_ioctl
;
1257 extern unsigned int i915_fbpercrtc __always_unused
;
1258 extern int i915_panel_ignore_lid __read_mostly
;
1259 extern unsigned int i915_powersave __read_mostly
;
1260 extern int i915_semaphores __read_mostly
;
1261 extern unsigned int i915_lvds_downclock __read_mostly
;
1262 extern int i915_lvds_channel_mode __read_mostly
;
1263 extern int i915_panel_use_ssc __read_mostly
;
1264 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1265 extern int i915_enable_rc6 __read_mostly
;
1266 extern int i915_enable_fbc __read_mostly
;
1267 extern bool i915_enable_hangcheck __read_mostly
;
1268 extern int i915_enable_ppgtt __read_mostly
;
1269 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1271 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1272 extern int i915_resume(struct drm_device
*dev
);
1273 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1274 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1277 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1278 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1279 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1280 extern int i915_driver_unload(struct drm_device
*);
1281 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1282 extern void i915_driver_lastclose(struct drm_device
* dev
);
1283 extern void i915_driver_preclose(struct drm_device
*dev
,
1284 struct drm_file
*file_priv
);
1285 extern void i915_driver_postclose(struct drm_device
*dev
,
1286 struct drm_file
*file_priv
);
1287 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1288 #ifdef CONFIG_COMPAT
1289 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1292 extern int i915_emit_box(struct drm_device
*dev
,
1293 struct drm_clip_rect
*box
,
1295 extern int intel_gpu_reset(struct drm_device
*dev
);
1296 extern int i915_reset(struct drm_device
*dev
);
1297 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1298 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1299 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1300 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1302 extern void intel_console_resume(struct work_struct
*work
);
1305 void i915_hangcheck_elapsed(unsigned long data
);
1306 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1308 extern void intel_irq_init(struct drm_device
*dev
);
1309 extern void intel_gt_init(struct drm_device
*dev
);
1310 extern void intel_gt_reset(struct drm_device
*dev
);
1312 void i915_error_state_free(struct kref
*error_ref
);
1315 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1318 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1320 void intel_enable_asle(struct drm_device
*dev
);
1322 #ifdef CONFIG_DEBUG_FS
1323 extern void i915_destroy_error_state(struct drm_device
*dev
);
1325 #define i915_destroy_error_state(x)
1330 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1331 struct drm_file
*file_priv
);
1332 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1333 struct drm_file
*file_priv
);
1334 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1335 struct drm_file
*file_priv
);
1336 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1337 struct drm_file
*file_priv
);
1338 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1339 struct drm_file
*file_priv
);
1340 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1341 struct drm_file
*file_priv
);
1342 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1343 struct drm_file
*file_priv
);
1344 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1345 struct drm_file
*file_priv
);
1346 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1347 struct drm_file
*file_priv
);
1348 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1349 struct drm_file
*file_priv
);
1350 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1351 struct drm_file
*file_priv
);
1352 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1353 struct drm_file
*file_priv
);
1354 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1355 struct drm_file
*file_priv
);
1356 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1357 struct drm_file
*file
);
1358 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1359 struct drm_file
*file
);
1360 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1361 struct drm_file
*file_priv
);
1362 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1363 struct drm_file
*file_priv
);
1364 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1365 struct drm_file
*file_priv
);
1366 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1367 struct drm_file
*file_priv
);
1368 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1369 struct drm_file
*file_priv
);
1370 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1371 struct drm_file
*file_priv
);
1372 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1373 struct drm_file
*file_priv
);
1374 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1375 struct drm_file
*file_priv
);
1376 void i915_gem_load(struct drm_device
*dev
);
1377 int i915_gem_init_object(struct drm_gem_object
*obj
);
1378 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1379 const struct drm_i915_gem_object_ops
*ops
);
1380 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1382 void i915_gem_free_object(struct drm_gem_object
*obj
);
1383 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1385 bool map_and_fenceable
,
1387 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1388 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1389 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1390 void i915_gem_lastclose(struct drm_device
*dev
);
1392 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1393 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1395 struct scatterlist
*sg
= obj
->pages
->sgl
;
1396 int nents
= obj
->pages
->nents
;
1397 while (nents
> SG_MAX_SINGLE_ALLOC
) {
1398 if (n
< SG_MAX_SINGLE_ALLOC
- 1)
1401 sg
= sg_chain_ptr(sg
+ SG_MAX_SINGLE_ALLOC
- 1);
1402 n
-= SG_MAX_SINGLE_ALLOC
- 1;
1403 nents
-= SG_MAX_SINGLE_ALLOC
- 1;
1405 return sg_page(sg
+n
);
1407 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1409 BUG_ON(obj
->pages
== NULL
);
1410 obj
->pages_pin_count
++;
1412 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1414 BUG_ON(obj
->pages_pin_count
== 0);
1415 obj
->pages_pin_count
--;
1418 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1419 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1420 struct intel_ring_buffer
*to
);
1421 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1422 struct intel_ring_buffer
*ring
);
1424 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1425 struct drm_device
*dev
,
1426 struct drm_mode_create_dumb
*args
);
1427 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1428 uint32_t handle
, uint64_t *offset
);
1429 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1432 * Returns true if seq1 is later than seq2.
1435 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1437 return (int32_t)(seq1
- seq2
) >= 0;
1440 extern int i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1442 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1443 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1446 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1448 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1449 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1450 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1457 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1459 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1460 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1461 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1465 void i915_gem_retire_requests(struct drm_device
*dev
);
1466 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1467 int __must_check
i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
1468 bool interruptible
);
1470 void i915_gem_reset(struct drm_device
*dev
);
1471 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1472 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1473 uint32_t read_domains
,
1474 uint32_t write_domain
);
1475 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1476 int __must_check
i915_gem_init(struct drm_device
*dev
);
1477 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1478 void i915_gem_l3_remap(struct drm_device
*dev
);
1479 void i915_gem_init_swizzling(struct drm_device
*dev
);
1480 void i915_gem_init_ppgtt(struct drm_device
*dev
);
1481 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1482 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1483 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1484 int i915_add_request(struct intel_ring_buffer
*ring
,
1485 struct drm_file
*file
,
1487 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1489 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1491 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1494 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1496 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1498 struct intel_ring_buffer
*pipelined
);
1499 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1500 struct drm_i915_gem_object
*obj
,
1503 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1504 struct drm_i915_gem_object
*obj
);
1505 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1506 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1509 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1513 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1514 enum i915_cache_level cache_level
);
1516 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1517 struct dma_buf
*dma_buf
);
1519 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1520 struct drm_gem_object
*gem_obj
, int flags
);
1522 /* i915_gem_context.c */
1523 void i915_gem_context_init(struct drm_device
*dev
);
1524 void i915_gem_context_fini(struct drm_device
*dev
);
1525 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1526 int i915_switch_context(struct intel_ring_buffer
*ring
,
1527 struct drm_file
*file
, int to_id
);
1528 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1529 struct drm_file
*file
);
1530 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1531 struct drm_file
*file
);
1533 /* i915_gem_gtt.c */
1534 int __must_check
i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
);
1535 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1536 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1537 struct drm_i915_gem_object
*obj
,
1538 enum i915_cache_level cache_level
);
1539 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1540 struct drm_i915_gem_object
*obj
);
1542 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1543 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1544 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1545 enum i915_cache_level cache_level
);
1546 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1547 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1548 void i915_gem_init_global_gtt(struct drm_device
*dev
,
1549 unsigned long start
,
1550 unsigned long mappable_end
,
1552 int i915_gem_gtt_init(struct drm_device
*dev
);
1553 void i915_gem_gtt_fini(struct drm_device
*dev
);
1554 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
1556 if (INTEL_INFO(dev
)->gen
< 6)
1557 intel_gtt_chipset_flush();
1561 /* i915_gem_evict.c */
1562 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1564 unsigned cache_level
,
1567 int i915_gem_evict_everything(struct drm_device
*dev
);
1569 /* i915_gem_stolen.c */
1570 int i915_gem_init_stolen(struct drm_device
*dev
);
1571 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1573 /* i915_gem_tiling.c */
1574 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1575 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1576 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1578 /* i915_gem_debug.c */
1579 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1580 const char *where
, uint32_t mark
);
1582 int i915_verify_lists(struct drm_device
*dev
);
1584 #define i915_verify_lists(dev) 0
1586 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1588 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1589 const char *where
, uint32_t mark
);
1591 /* i915_debugfs.c */
1592 int i915_debugfs_init(struct drm_minor
*minor
);
1593 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1595 /* i915_suspend.c */
1596 extern int i915_save_state(struct drm_device
*dev
);
1597 extern int i915_restore_state(struct drm_device
*dev
);
1599 /* i915_suspend.c */
1600 extern int i915_save_state(struct drm_device
*dev
);
1601 extern int i915_restore_state(struct drm_device
*dev
);
1604 void i915_setup_sysfs(struct drm_device
*dev_priv
);
1605 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
1608 extern int intel_setup_gmbus(struct drm_device
*dev
);
1609 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1610 extern inline bool intel_gmbus_is_port_valid(unsigned port
)
1612 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
1615 extern struct i2c_adapter
*intel_gmbus_get_adapter(
1616 struct drm_i915_private
*dev_priv
, unsigned port
);
1617 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1618 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1619 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1621 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1623 extern void intel_i2c_reset(struct drm_device
*dev
);
1625 /* intel_opregion.c */
1626 extern int intel_opregion_setup(struct drm_device
*dev
);
1628 extern void intel_opregion_init(struct drm_device
*dev
);
1629 extern void intel_opregion_fini(struct drm_device
*dev
);
1630 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1631 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1632 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1634 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1635 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1636 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1637 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1638 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1643 extern void intel_register_dsm_handler(void);
1644 extern void intel_unregister_dsm_handler(void);
1646 static inline void intel_register_dsm_handler(void) { return; }
1647 static inline void intel_unregister_dsm_handler(void) { return; }
1648 #endif /* CONFIG_ACPI */
1651 extern void intel_modeset_init_hw(struct drm_device
*dev
);
1652 extern void intel_modeset_init(struct drm_device
*dev
);
1653 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1654 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1655 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1656 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
1657 bool force_restore
);
1658 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1659 extern void intel_disable_fbc(struct drm_device
*dev
);
1660 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1661 extern void ironlake_init_pch_refclk(struct drm_device
*dev
);
1662 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1663 extern void intel_detect_pch(struct drm_device
*dev
);
1664 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1665 extern int intel_enable_rc6(const struct drm_device
*dev
);
1667 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
1668 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
1669 struct drm_file
*file
);
1672 #ifdef CONFIG_DEBUG_FS
1673 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1674 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1676 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1677 extern void intel_display_print_error_state(struct seq_file
*m
,
1678 struct drm_device
*dev
,
1679 struct intel_display_error_state
*error
);
1682 /* On SNB platform, before reading ring registers forcewake bit
1683 * must be set to prevent GT core from power down and stale values being
1686 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1687 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1688 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1690 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
1691 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
1693 #define __i915_read(x, y) \
1694 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1702 #define __i915_write(x, y) \
1703 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1711 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1712 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1714 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1715 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1716 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1717 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1719 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1720 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1721 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1722 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1724 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1725 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1727 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1728 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)