1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
56 #include "intel_bios.h"
57 #include "intel_dpll_mgr.h"
58 #include "intel_guc.h"
59 #include "intel_lrc.h"
60 #include "intel_ringbuffer.h"
63 #include "i915_gem_gtt.h"
64 #include "i915_gem_render_state.h"
65 #include "i915_gem_request.h"
66 #include "i915_gem_timeline.h"
68 #include "intel_gvt.h"
70 /* General customization:
73 #define DRIVER_NAME "i915"
74 #define DRIVER_DESC "Intel Graphics"
75 #define DRIVER_DATE "20161024"
76 #define DRIVER_TIMESTAMP 1477290335
79 /* Many gcc seem to no see through this and fall over :( */
81 #define WARN_ON(x) ({ \
82 bool __i915_warn_cond = (x); \
83 if (__builtin_constant_p(__i915_warn_cond)) \
84 BUILD_BUG_ON(__i915_warn_cond); \
85 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
87 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
91 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
93 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
94 (long) (x), __func__);
96 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
97 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
98 * which may not necessarily be a user visible problem. This will either
99 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
100 * enable distros and users to tailor their preferred amount of i915 abrt
103 #define I915_STATE_WARN(condition, format...) ({ \
104 int __ret_warn_on = !!(condition); \
105 if (unlikely(__ret_warn_on)) \
106 if (!WARN(i915.verbose_state_checks, format)) \
108 unlikely(__ret_warn_on); \
111 #define I915_STATE_WARN_ON(x) \
112 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
114 bool __i915_inject_load_failure(const char *func
, int line
);
115 #define i915_inject_load_failure() \
116 __i915_inject_load_failure(__func__, __LINE__)
118 static inline const char *yesno(bool v
)
120 return v
? "yes" : "no";
123 static inline const char *onoff(bool v
)
125 return v
? "on" : "off";
134 I915_MAX_PIPES
= _PIPE_EDP
136 #define pipe_name(p) ((p) + 'A')
148 static inline const char *transcoder_name(enum transcoder transcoder
)
150 switch (transcoder
) {
159 case TRANSCODER_DSI_A
:
161 case TRANSCODER_DSI_C
:
168 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
170 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
174 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
175 * number of planes per CRTC. Not all platforms really have this many planes,
176 * which means some arrays of size I915_MAX_PLANES may have unused entries
177 * between the topmost sprite plane and the cursor plane.
186 #define plane_name(p) ((p) + 'A')
188 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
199 #define port_name(p) ((p) + 'A')
201 #define I915_NUM_PHYS_VLV 2
213 enum intel_display_power_domain
{
217 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
218 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
219 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
220 POWER_DOMAIN_TRANSCODER_A
,
221 POWER_DOMAIN_TRANSCODER_B
,
222 POWER_DOMAIN_TRANSCODER_C
,
223 POWER_DOMAIN_TRANSCODER_EDP
,
224 POWER_DOMAIN_TRANSCODER_DSI_A
,
225 POWER_DOMAIN_TRANSCODER_DSI_C
,
226 POWER_DOMAIN_PORT_DDI_A_LANES
,
227 POWER_DOMAIN_PORT_DDI_B_LANES
,
228 POWER_DOMAIN_PORT_DDI_C_LANES
,
229 POWER_DOMAIN_PORT_DDI_D_LANES
,
230 POWER_DOMAIN_PORT_DDI_E_LANES
,
231 POWER_DOMAIN_PORT_DSI
,
232 POWER_DOMAIN_PORT_CRT
,
233 POWER_DOMAIN_PORT_OTHER
,
242 POWER_DOMAIN_MODESET
,
248 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
249 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
250 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
251 #define POWER_DOMAIN_TRANSCODER(tran) \
252 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
253 (tran) + POWER_DOMAIN_TRANSCODER_A)
257 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
269 #define for_each_hpd_pin(__pin) \
270 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
272 struct i915_hotplug
{
273 struct work_struct hotplug_work
;
276 unsigned long last_jiffies
;
281 HPD_MARK_DISABLED
= 2
283 } stats
[HPD_NUM_PINS
];
285 struct delayed_work reenable_work
;
287 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
290 struct work_struct dig_port_work
;
292 struct work_struct poll_init_work
;
296 * if we get a HPD irq from DP and a HPD irq from non-DP
297 * the non-DP HPD could block the workqueue on a mode config
298 * mutex getting, that userspace may have taken. However
299 * userspace is waiting on the DP workqueue to run which is
300 * blocked behind the non-DP one.
302 struct workqueue_struct
*dp_wq
;
305 #define I915_GEM_GPU_DOMAINS \
306 (I915_GEM_DOMAIN_RENDER | \
307 I915_GEM_DOMAIN_SAMPLER | \
308 I915_GEM_DOMAIN_COMMAND | \
309 I915_GEM_DOMAIN_INSTRUCTION | \
310 I915_GEM_DOMAIN_VERTEX)
312 #define for_each_pipe(__dev_priv, __p) \
313 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
314 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
315 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
316 for_each_if ((__mask) & (1 << (__p)))
317 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
319 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
321 #define for_each_sprite(__dev_priv, __p, __s) \
323 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
326 #define for_each_port_masked(__port, __ports_mask) \
327 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
328 for_each_if ((__ports_mask) & (1 << (__port)))
330 #define for_each_crtc(dev, crtc) \
331 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
333 #define for_each_intel_plane(dev, intel_plane) \
334 list_for_each_entry(intel_plane, \
335 &(dev)->mode_config.plane_list, \
338 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
339 list_for_each_entry(intel_plane, \
340 &(dev)->mode_config.plane_list, \
342 for_each_if ((plane_mask) & \
343 (1 << drm_plane_index(&intel_plane->base)))
345 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
346 list_for_each_entry(intel_plane, \
347 &(dev)->mode_config.plane_list, \
349 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
351 #define for_each_intel_crtc(dev, intel_crtc) \
352 list_for_each_entry(intel_crtc, \
353 &(dev)->mode_config.crtc_list, \
356 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
357 list_for_each_entry(intel_crtc, \
358 &(dev)->mode_config.crtc_list, \
360 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
362 #define for_each_intel_encoder(dev, intel_encoder) \
363 list_for_each_entry(intel_encoder, \
364 &(dev)->mode_config.encoder_list, \
367 #define for_each_intel_connector(dev, intel_connector) \
368 list_for_each_entry(intel_connector, \
369 &(dev)->mode_config.connector_list, \
372 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
373 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
374 for_each_if ((intel_encoder)->base.crtc == (__crtc))
376 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
377 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
378 for_each_if ((intel_connector)->base.encoder == (__encoder))
380 #define for_each_power_domain(domain, mask) \
381 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
382 for_each_if ((1 << (domain)) & (mask))
384 struct drm_i915_private
;
385 struct i915_mm_struct
;
386 struct i915_mmu_object
;
388 struct drm_i915_file_private
{
389 struct drm_i915_private
*dev_priv
;
390 struct drm_file
*file
;
394 struct list_head request_list
;
395 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
396 * chosen to prevent the CPU getting more than a frame ahead of the GPU
397 * (when using lax throttling for the frontbuffer). We also use it to
398 * offer free GPU waitboosts for severely congested workloads.
400 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
402 struct idr context_idr
;
404 struct intel_rps_client
{
405 struct list_head link
;
409 unsigned int bsd_engine
;
412 /* Used by dp and fdi links */
413 struct intel_link_m_n
{
421 void intel_link_compute_m_n(int bpp
, int nlanes
,
422 int pixel_clock
, int link_clock
,
423 struct intel_link_m_n
*m_n
);
425 /* Interface history:
428 * 1.2: Add Power Management
429 * 1.3: Add vblank support
430 * 1.4: Fix cmdbuffer path, add heap destroy
431 * 1.5: Add vblank pipe configuration
432 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
433 * - Support vertical blank on secondary display pipe
435 #define DRIVER_MAJOR 1
436 #define DRIVER_MINOR 6
437 #define DRIVER_PATCHLEVEL 0
439 struct opregion_header
;
440 struct opregion_acpi
;
441 struct opregion_swsci
;
442 struct opregion_asle
;
444 struct intel_opregion
{
445 struct opregion_header
*header
;
446 struct opregion_acpi
*acpi
;
447 struct opregion_swsci
*swsci
;
448 u32 swsci_gbda_sub_functions
;
449 u32 swsci_sbcb_sub_functions
;
450 struct opregion_asle
*asle
;
455 struct work_struct asle_work
;
457 #define OPREGION_SIZE (8*1024)
459 struct intel_overlay
;
460 struct intel_overlay_error_state
;
462 struct drm_i915_fence_reg
{
463 struct list_head link
;
464 struct drm_i915_private
*i915
;
465 struct i915_vma
*vma
;
469 * Whether the tiling parameters for the currently
470 * associated fence register have changed. Note that
471 * for the purposes of tracking tiling changes we also
472 * treat the unfenced register, the register slot that
473 * the object occupies whilst it executes a fenced
474 * command (such as BLT on gen2/3), as a "fence".
479 struct sdvo_device_mapping
{
488 struct intel_connector
;
489 struct intel_encoder
;
490 struct intel_crtc_state
;
491 struct intel_initial_plane_config
;
496 struct drm_i915_display_funcs
{
497 int (*get_display_clock_speed
)(struct drm_i915_private
*dev_priv
);
498 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
499 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
500 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
501 struct intel_crtc
*intel_crtc
,
502 struct intel_crtc_state
*newstate
);
503 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
504 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
505 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
506 void (*update_wm
)(struct intel_crtc
*crtc
);
507 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
508 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
509 /* Returns the active state of the crtc, and if the crtc is active,
510 * fills out the pipe-config with the hw state. */
511 bool (*get_pipe_config
)(struct intel_crtc
*,
512 struct intel_crtc_state
*);
513 void (*get_initial_plane_config
)(struct intel_crtc
*,
514 struct intel_initial_plane_config
*);
515 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
516 struct intel_crtc_state
*crtc_state
);
517 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
518 struct drm_atomic_state
*old_state
);
519 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
520 struct drm_atomic_state
*old_state
);
521 void (*update_crtcs
)(struct drm_atomic_state
*state
,
522 unsigned int *crtc_vblank_mask
);
523 void (*audio_codec_enable
)(struct drm_connector
*connector
,
524 struct intel_encoder
*encoder
,
525 const struct drm_display_mode
*adjusted_mode
);
526 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
527 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
528 void (*init_clock_gating
)(struct drm_device
*dev
);
529 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
530 struct drm_framebuffer
*fb
,
531 struct drm_i915_gem_object
*obj
,
532 struct drm_i915_gem_request
*req
,
534 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
535 /* clock updates for mode set */
537 /* render clock increase/decrease */
538 /* display clock increase/decrease */
539 /* pll clock increase/decrease */
541 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
542 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
545 enum forcewake_domain_id
{
546 FW_DOMAIN_ID_RENDER
= 0,
547 FW_DOMAIN_ID_BLITTER
,
553 enum forcewake_domains
{
554 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
555 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
556 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
557 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
562 #define FW_REG_READ (1)
563 #define FW_REG_WRITE (2)
565 enum forcewake_domains
566 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
567 i915_reg_t reg
, unsigned int op
);
569 struct intel_uncore_funcs
{
570 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
571 enum forcewake_domains domains
);
572 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
573 enum forcewake_domains domains
);
575 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
576 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
577 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
578 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
580 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
581 uint8_t val
, bool trace
);
582 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
583 uint16_t val
, bool trace
);
584 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
585 uint32_t val
, bool trace
);
588 struct intel_forcewake_range
{
592 enum forcewake_domains domains
;
595 struct intel_uncore
{
596 spinlock_t lock
; /** lock is also taken in irq contexts. */
598 const struct intel_forcewake_range
*fw_domains_table
;
599 unsigned int fw_domains_table_entries
;
601 struct intel_uncore_funcs funcs
;
605 enum forcewake_domains fw_domains
;
606 enum forcewake_domains fw_domains_active
;
608 struct intel_uncore_forcewake_domain
{
609 struct drm_i915_private
*i915
;
610 enum forcewake_domain_id id
;
611 enum forcewake_domains mask
;
613 struct hrtimer timer
;
620 } fw_domain
[FW_DOMAIN_ID_COUNT
];
622 int unclaimed_mmio_check
;
625 /* Iterate over initialised fw domains */
626 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
627 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
628 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
630 for_each_if ((mask__) & (domain__)->mask)
632 #define for_each_fw_domain(domain__, dev_priv__) \
633 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
635 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
636 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
637 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
640 struct work_struct work
;
642 uint32_t *dmc_payload
;
643 uint32_t dmc_fw_size
;
646 i915_reg_t mmioaddr
[8];
647 uint32_t mmiodata
[8];
649 uint32_t allowed_dc_mask
;
652 #define DEV_INFO_FOR_EACH_FLAG(func) \
653 /* Keep is_* in chronological order */ \
661 func(is_broadwater); \
662 func(is_crestline); \
663 func(is_ivybridge); \
664 func(is_valleyview); \
665 func(is_cherryview); \
667 func(is_broadwell); \
671 func(is_preliminary); \
672 /* Keep has_* in alphabetical order */ \
677 func(has_fpga_dbg); \
678 func(has_gmbus_irq); \
679 func(has_gmch_display); \
682 func(has_hw_contexts); \
685 func(has_logical_ring_contexts); \
687 func(has_pipe_cxsr); \
688 func(has_pooled_eu); \
692 func(has_resource_streamer); \
693 func(has_runtime_pm); \
695 func(cursor_needs_physical); \
696 func(hws_needs_physical); \
697 func(overlay_needs_physical); \
700 struct sseu_dev_info
{
706 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
709 u8 has_subslice_pg
:1;
713 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
715 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
718 struct intel_device_info
{
719 u32 display_mmio_offset
;
722 u8 num_sprites
[I915_MAX_PIPES
];
725 u8 ring_mask
; /* Rings supported by the HW */
727 #define DEFINE_FLAG(name) u8 name:1
728 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
730 u16 ddb_size
; /* in blocks */
731 /* Register offsets for the various display pipes and transcoders */
732 int pipe_offsets
[I915_MAX_TRANSCODERS
];
733 int trans_offsets
[I915_MAX_TRANSCODERS
];
734 int palette_offsets
[I915_MAX_PIPES
];
735 int cursor_offsets
[I915_MAX_PIPES
];
737 /* Slice/subslice/EU info */
738 struct sseu_dev_info sseu
;
741 u16 degamma_lut_size
;
746 struct intel_display_error_state
;
748 struct drm_i915_error_state
{
751 struct timeval boottime
;
752 struct timeval uptime
;
754 struct drm_i915_private
*i915
;
761 struct intel_device_info device_info
;
763 /* Generic register state */
771 u32 error
; /* gen6+ */
772 u32 err_int
; /* gen7 */
773 u32 fault_data0
; /* gen8, gen9 */
774 u32 fault_data1
; /* gen8, gen9 */
781 u64 fence
[I915_MAX_NUM_FENCES
];
782 struct intel_overlay_error_state
*overlay
;
783 struct intel_display_error_state
*display
;
784 struct drm_i915_error_object
*semaphore
;
785 struct drm_i915_error_object
*guc_log
;
787 struct drm_i915_error_engine
{
789 /* Software tracked state */
793 enum intel_engine_hangcheck_action hangcheck_action
;
794 struct i915_address_space
*vm
;
797 /* position of active request inside the ring */
798 u32 rq_head
, rq_post
, rq_tail
;
800 /* our own tracking of ring head and tail */
823 u32 rc_psmi
; /* sleep state */
824 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
825 struct intel_instdone instdone
;
827 struct drm_i915_error_object
{
833 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
835 struct drm_i915_error_object
*wa_ctx
;
837 struct drm_i915_error_request
{
844 } *requests
, execlist
[2];
846 struct drm_i915_error_waiter
{
847 char comm
[TASK_COMM_LEN
];
861 char comm
[TASK_COMM_LEN
];
862 } engine
[I915_NUM_ENGINES
];
864 struct drm_i915_error_buffer
{
867 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
871 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
878 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
879 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
880 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
883 enum i915_cache_level
{
885 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
886 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
887 caches, eg sampler/render caches, and the
888 large Last-Level-Cache. LLC is coherent with
889 the CPU, but L3 is only visible to the GPU. */
890 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
893 struct i915_ctx_hang_stats
{
894 /* This context had batch pending when hang was declared */
895 unsigned batch_pending
;
897 /* This context had batch active when hang was declared */
898 unsigned batch_active
;
900 /* Time when this context was last blamed for a GPU reset */
901 unsigned long guilty_ts
;
903 /* If the contexts causes a second GPU hang within this time,
904 * it is permanently banned from submitting any more work.
906 unsigned long ban_period_seconds
;
908 /* This context is banned to submit more work */
912 /* This must match up with the value previously used for execbuf2.rsvd1. */
913 #define DEFAULT_CONTEXT_HANDLE 0
916 * struct i915_gem_context - as the name implies, represents a context.
917 * @ref: reference count.
918 * @user_handle: userspace tracking identity for this context.
919 * @remap_slice: l3 row remapping information.
920 * @flags: context specific flags:
921 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
922 * @file_priv: filp associated with this context (NULL for global default
924 * @hang_stats: information about the role of this context in possible GPU
926 * @ppgtt: virtual memory space used by this context.
927 * @legacy_hw_ctx: render context backing object and whether it is correctly
928 * initialized (legacy ring submission mechanism only).
929 * @link: link in the global list of contexts.
931 * Contexts are memory images used by the hardware to store copies of their
934 struct i915_gem_context
{
936 struct drm_i915_private
*i915
;
937 struct drm_i915_file_private
*file_priv
;
938 struct i915_hw_ppgtt
*ppgtt
;
942 struct i915_ctx_hang_stats hang_stats
;
945 #define CONTEXT_NO_ZEROMAP BIT(0)
946 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
948 /* Unique identifier for this context, used by the hw for tracking */
954 struct intel_context
{
955 struct i915_vma
*state
;
956 struct intel_ring
*ring
;
957 uint32_t *lrc_reg_state
;
961 } engine
[I915_NUM_ENGINES
];
964 struct atomic_notifier_head status_notifier
;
965 bool execlists_force_single_submission
;
967 struct list_head link
;
982 /* This is always the inner lock when overlapping with struct_mutex and
983 * it's the outer lock when overlapping with stolen_lock. */
986 unsigned int possible_framebuffer_bits
;
987 unsigned int busy_bits
;
988 unsigned int visible_pipes_mask
;
989 struct intel_crtc
*crtc
;
991 struct drm_mm_node compressed_fb
;
992 struct drm_mm_node
*compressed_llb
;
999 bool underrun_detected
;
1000 struct work_struct underrun_work
;
1002 struct intel_fbc_state_cache
{
1004 unsigned int mode_flags
;
1005 uint32_t hsw_bdw_pixel_rate
;
1009 unsigned int rotation
;
1016 u64 ilk_ggtt_offset
;
1017 uint32_t pixel_format
;
1018 unsigned int stride
;
1020 unsigned int tiling_mode
;
1024 struct intel_fbc_reg_params
{
1028 unsigned int fence_y_offset
;
1033 uint32_t pixel_format
;
1034 unsigned int stride
;
1041 struct intel_fbc_work
{
1043 u32 scheduled_vblank
;
1044 struct work_struct work
;
1047 const char *no_fbc_reason
;
1051 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1052 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1053 * parsing for same resolution.
1055 enum drrs_refresh_rate_type
{
1058 DRRS_MAX_RR
, /* RR count */
1061 enum drrs_support_type
{
1062 DRRS_NOT_SUPPORTED
= 0,
1063 STATIC_DRRS_SUPPORT
= 1,
1064 SEAMLESS_DRRS_SUPPORT
= 2
1070 struct delayed_work work
;
1071 struct intel_dp
*dp
;
1072 unsigned busy_frontbuffer_bits
;
1073 enum drrs_refresh_rate_type refresh_rate_type
;
1074 enum drrs_support_type type
;
1081 struct intel_dp
*enabled
;
1083 struct delayed_work work
;
1084 unsigned busy_frontbuffer_bits
;
1086 bool aux_frame_sync
;
1091 PCH_NONE
= 0, /* No PCH present */
1092 PCH_IBX
, /* Ibexpeak PCH */
1093 PCH_CPT
, /* Cougarpoint PCH */
1094 PCH_LPT
, /* Lynxpoint PCH */
1095 PCH_SPT
, /* Sunrisepoint PCH */
1096 PCH_KBP
, /* Kabypoint PCH */
1100 enum intel_sbi_destination
{
1105 #define QUIRK_PIPEA_FORCE (1<<0)
1106 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1107 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1108 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1109 #define QUIRK_PIPEB_FORCE (1<<4)
1110 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1113 struct intel_fbc_work
;
1115 struct intel_gmbus
{
1116 struct i2c_adapter adapter
;
1117 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1120 i915_reg_t gpio_reg
;
1121 struct i2c_algo_bit_data bit_algo
;
1122 struct drm_i915_private
*dev_priv
;
1125 struct i915_suspend_saved_registers
{
1127 u32 saveFBC_CONTROL
;
1128 u32 saveCACHE_MODE_0
;
1129 u32 saveMI_ARB_STATE
;
1133 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1134 u32 savePCH_PORT_HOTPLUG
;
1138 struct vlv_s0ix_state
{
1145 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1146 u32 media_max_req_count
;
1147 u32 gfx_max_req_count
;
1173 u32 rp_down_timeout
;
1179 /* Display 1 CZ domain */
1184 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1186 /* GT SA CZ domain */
1193 /* Display 2 CZ domain */
1197 u32 clock_gate_dis2
;
1200 struct intel_rps_ei
{
1206 struct intel_gen6_power_mgmt
{
1208 * work, interrupts_enabled and pm_iir are protected by
1209 * dev_priv->irq_lock
1211 struct work_struct work
;
1212 bool interrupts_enabled
;
1215 /* PM interrupt bits that should never be masked */
1218 /* Frequencies are stored in potentially platform dependent multiples.
1219 * In other words, *_freq needs to be multiplied by X to be interesting.
1220 * Soft limits are those which are used for the dynamic reclocking done
1221 * by the driver (raise frequencies under heavy loads, and lower for
1222 * lighter loads). Hard limits are those imposed by the hardware.
1224 * A distinction is made for overclocking, which is never enabled by
1225 * default, and is considered to be above the hard limit if it's
1228 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1229 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1230 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1231 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1232 u8 min_freq
; /* AKA RPn. Minimum frequency */
1233 u8 boost_freq
; /* Frequency to request when wait boosting */
1234 u8 idle_freq
; /* Frequency to request when we are idle */
1235 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1236 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1237 u8 rp0_freq
; /* Non-overclocked max frequency. */
1238 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1240 u8 up_threshold
; /* Current %busy required to uplock */
1241 u8 down_threshold
; /* Current %busy required to downclock */
1244 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1246 spinlock_t client_lock
;
1247 struct list_head clients
;
1251 struct delayed_work autoenable_work
;
1254 /* manual wa residency calculations */
1255 struct intel_rps_ei up_ei
, down_ei
;
1258 * Protects RPS/RC6 register access and PCU communication.
1259 * Must be taken after struct_mutex if nested. Note that
1260 * this lock may be held for long periods of time when
1261 * talking to hw - so only take it when talking to hw!
1263 struct mutex hw_lock
;
1266 /* defined intel_pm.c */
1267 extern spinlock_t mchdev_lock
;
1269 struct intel_ilk_power_mgmt
{
1277 unsigned long last_time1
;
1278 unsigned long chipset_power
;
1281 unsigned long gfx_power
;
1288 struct drm_i915_private
;
1289 struct i915_power_well
;
1291 struct i915_power_well_ops
{
1293 * Synchronize the well's hw state to match the current sw state, for
1294 * example enable/disable it based on the current refcount. Called
1295 * during driver init and resume time, possibly after first calling
1296 * the enable/disable handlers.
1298 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1299 struct i915_power_well
*power_well
);
1301 * Enable the well and resources that depend on it (for example
1302 * interrupts located on the well). Called after the 0->1 refcount
1305 void (*enable
)(struct drm_i915_private
*dev_priv
,
1306 struct i915_power_well
*power_well
);
1308 * Disable the well and resources that depend on it. Called after
1309 * the 1->0 refcount transition.
1311 void (*disable
)(struct drm_i915_private
*dev_priv
,
1312 struct i915_power_well
*power_well
);
1313 /* Returns the hw enabled state. */
1314 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1315 struct i915_power_well
*power_well
);
1318 /* Power well structure for haswell */
1319 struct i915_power_well
{
1322 /* power well enable/disable usage count */
1324 /* cached hw enabled state */
1326 unsigned long domains
;
1327 /* unique identifier for this power well */
1330 * Arbitraty data associated with this power well. Platform and power
1334 const struct i915_power_well_ops
*ops
;
1337 struct i915_power_domains
{
1339 * Power wells needed for initialization at driver init and suspend
1340 * time are on. They are kept on until after the first modeset.
1344 int power_well_count
;
1347 int domain_use_count
[POWER_DOMAIN_NUM
];
1348 struct i915_power_well
*power_wells
;
1351 #define MAX_L3_SLICES 2
1352 struct intel_l3_parity
{
1353 u32
*remap_info
[MAX_L3_SLICES
];
1354 struct work_struct error_work
;
1358 struct i915_gem_mm
{
1359 /** Memory allocator for GTT stolen memory */
1360 struct drm_mm stolen
;
1361 /** Protects the usage of the GTT stolen memory allocator. This is
1362 * always the inner lock when overlapping with struct_mutex. */
1363 struct mutex stolen_lock
;
1365 /** List of all objects in gtt_space. Used to restore gtt
1366 * mappings on resume */
1367 struct list_head bound_list
;
1369 * List of objects which are not bound to the GTT (thus
1370 * are idle and not used by the GPU). These objects may or may
1371 * not actually have any pages attached.
1373 struct list_head unbound_list
;
1375 /** List of all objects in gtt_space, currently mmaped by userspace.
1376 * All objects within this list must also be on bound_list.
1378 struct list_head userfault_list
;
1381 * List of objects which are pending destruction.
1383 struct llist_head free_list
;
1384 struct work_struct free_work
;
1386 /** Usable portion of the GTT for GEM */
1387 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1389 /** PPGTT used for aliasing the PPGTT with the GTT */
1390 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1392 struct notifier_block oom_notifier
;
1393 struct notifier_block vmap_notifier
;
1394 struct shrinker shrinker
;
1396 /** LRU list of objects with fence regs on them. */
1397 struct list_head fence_list
;
1400 * Are we in a non-interruptible section of code like
1405 /* the indicator for dispatch video commands on two BSD rings */
1406 atomic_t bsd_engine_dispatch_index
;
1408 /** Bit 6 swizzling required for X tiling */
1409 uint32_t bit_6_swizzle_x
;
1410 /** Bit 6 swizzling required for Y tiling */
1411 uint32_t bit_6_swizzle_y
;
1413 /* accounting, useful for userland debugging */
1414 spinlock_t object_stat_lock
;
1419 struct drm_i915_error_state_buf
{
1420 struct drm_i915_private
*i915
;
1429 struct i915_error_state_file_priv
{
1430 struct drm_device
*dev
;
1431 struct drm_i915_error_state
*error
;
1434 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1435 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1437 struct i915_gpu_error
{
1438 /* For hangcheck timer */
1439 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1440 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1441 /* Hang gpu twice in this window and your context gets banned */
1442 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1444 struct delayed_work hangcheck_work
;
1446 /* For reset and error_state handling. */
1448 /* Protected by the above dev->gpu_error.lock. */
1449 struct drm_i915_error_state
*first_error
;
1451 unsigned long missed_irq_rings
;
1454 * State variable controlling the reset flow and count
1456 * This is a counter which gets incremented when reset is triggered,
1458 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1459 * meaning that any waiters holding onto the struct_mutex should
1460 * relinquish the lock immediately in order for the reset to start.
1462 * If reset is not completed succesfully, the I915_WEDGE bit is
1463 * set meaning that hardware is terminally sour and there is no
1464 * recovery. All waiters on the reset_queue will be woken when
1467 * This counter is used by the wait_seqno code to notice that reset
1468 * event happened and it needs to restart the entire ioctl (since most
1469 * likely the seqno it waited for won't ever signal anytime soon).
1471 * This is important for lock-free wait paths, where no contended lock
1472 * naturally enforces the correct ordering between the bail-out of the
1473 * waiter and the gpu reset work code.
1475 unsigned long reset_count
;
1477 unsigned long flags
;
1478 #define I915_RESET_IN_PROGRESS 0
1479 #define I915_WEDGED (BITS_PER_LONG - 1)
1482 * Waitqueue to signal when a hang is detected. Used to for waiters
1483 * to release the struct_mutex for the reset to procede.
1485 wait_queue_head_t wait_queue
;
1488 * Waitqueue to signal when the reset has completed. Used by clients
1489 * that wait for dev_priv->mm.wedged to settle.
1491 wait_queue_head_t reset_queue
;
1493 /* For missed irq/seqno simulation. */
1494 unsigned long test_irq_rings
;
1497 enum modeset_restore
{
1498 MODESET_ON_LID_OPEN
,
1503 #define DP_AUX_A 0x40
1504 #define DP_AUX_B 0x10
1505 #define DP_AUX_C 0x20
1506 #define DP_AUX_D 0x30
1508 #define DDC_PIN_B 0x05
1509 #define DDC_PIN_C 0x04
1510 #define DDC_PIN_D 0x06
1512 struct ddi_vbt_port_info
{
1514 * This is an index in the HDMI/DVI DDI buffer translation table.
1515 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1516 * populate this field.
1518 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1519 uint8_t hdmi_level_shift
;
1521 uint8_t supports_dvi
:1;
1522 uint8_t supports_hdmi
:1;
1523 uint8_t supports_dp
:1;
1525 uint8_t alternate_aux_channel
;
1526 uint8_t alternate_ddc_pin
;
1528 uint8_t dp_boost_level
;
1529 uint8_t hdmi_boost_level
;
1532 enum psr_lines_to_wait
{
1533 PSR_0_LINES_TO_WAIT
= 0,
1535 PSR_4_LINES_TO_WAIT
,
1539 struct intel_vbt_data
{
1540 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1541 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1544 unsigned int int_tv_support
:1;
1545 unsigned int lvds_dither
:1;
1546 unsigned int lvds_vbt
:1;
1547 unsigned int int_crt_support
:1;
1548 unsigned int lvds_use_ssc
:1;
1549 unsigned int display_clock_mode
:1;
1550 unsigned int fdi_rx_polarity_inverted
:1;
1551 unsigned int panel_type
:4;
1553 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1555 enum drrs_support_type drrs_type
;
1566 struct edp_power_seq pps
;
1571 bool require_aux_wakeup
;
1573 enum psr_lines_to_wait lines_to_wait
;
1574 int tp1_wakeup_time
;
1575 int tp2_tp3_wakeup_time
;
1581 bool active_low_pwm
;
1582 u8 min_brightness
; /* min_brightness/255 of max */
1583 enum intel_backlight_type type
;
1589 struct mipi_config
*config
;
1590 struct mipi_pps_data
*pps
;
1594 const u8
*sequence
[MIPI_SEQ_MAX
];
1600 union child_device_config
*child_dev
;
1602 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1603 struct sdvo_device_mapping sdvo_mappings
[2];
1606 enum intel_ddb_partitioning
{
1608 INTEL_DDB_PART_5_6
, /* IVB+ */
1611 struct intel_wm_level
{
1619 struct ilk_wm_values
{
1620 uint32_t wm_pipe
[3];
1622 uint32_t wm_lp_spr
[3];
1623 uint32_t wm_linetime
[3];
1625 enum intel_ddb_partitioning partitioning
;
1628 struct vlv_pipe_wm
{
1639 struct vlv_wm_values
{
1640 struct vlv_pipe_wm pipe
[3];
1641 struct vlv_sr_wm sr
;
1651 struct skl_ddb_entry
{
1652 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1655 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1657 return entry
->end
- entry
->start
;
1660 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1661 const struct skl_ddb_entry
*e2
)
1663 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1669 struct skl_ddb_allocation
{
1670 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1671 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1674 struct skl_wm_values
{
1675 unsigned dirty_pipes
;
1676 struct skl_ddb_allocation ddb
;
1679 struct skl_wm_level
{
1681 uint16_t plane_res_b
;
1682 uint8_t plane_res_l
;
1686 * This struct helps tracking the state needed for runtime PM, which puts the
1687 * device in PCI D3 state. Notice that when this happens, nothing on the
1688 * graphics device works, even register access, so we don't get interrupts nor
1691 * Every piece of our code that needs to actually touch the hardware needs to
1692 * either call intel_runtime_pm_get or call intel_display_power_get with the
1693 * appropriate power domain.
1695 * Our driver uses the autosuspend delay feature, which means we'll only really
1696 * suspend if we stay with zero refcount for a certain amount of time. The
1697 * default value is currently very conservative (see intel_runtime_pm_enable), but
1698 * it can be changed with the standard runtime PM files from sysfs.
1700 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1701 * goes back to false exactly before we reenable the IRQs. We use this variable
1702 * to check if someone is trying to enable/disable IRQs while they're supposed
1703 * to be disabled. This shouldn't happen and we'll print some error messages in
1706 * For more, read the Documentation/power/runtime_pm.txt.
1708 struct i915_runtime_pm
{
1709 atomic_t wakeref_count
;
1714 enum intel_pipe_crc_source
{
1715 INTEL_PIPE_CRC_SOURCE_NONE
,
1716 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1717 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1718 INTEL_PIPE_CRC_SOURCE_PF
,
1719 INTEL_PIPE_CRC_SOURCE_PIPE
,
1720 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1721 INTEL_PIPE_CRC_SOURCE_TV
,
1722 INTEL_PIPE_CRC_SOURCE_DP_B
,
1723 INTEL_PIPE_CRC_SOURCE_DP_C
,
1724 INTEL_PIPE_CRC_SOURCE_DP_D
,
1725 INTEL_PIPE_CRC_SOURCE_AUTO
,
1726 INTEL_PIPE_CRC_SOURCE_MAX
,
1729 struct intel_pipe_crc_entry
{
1734 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1735 struct intel_pipe_crc
{
1737 bool opened
; /* exclusive access to the result file */
1738 struct intel_pipe_crc_entry
*entries
;
1739 enum intel_pipe_crc_source source
;
1741 wait_queue_head_t wq
;
1744 struct i915_frontbuffer_tracking
{
1748 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1755 struct i915_wa_reg
{
1758 /* bitmask representing WA bits */
1763 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1764 * allowing it for RCS as we don't foresee any requirement of having
1765 * a whitelist for other engines. When it is really required for
1766 * other engines then the limit need to be increased.
1768 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1770 struct i915_workarounds
{
1771 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1773 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1776 struct i915_virtual_gpu
{
1780 /* used in computing the new watermarks state */
1781 struct intel_wm_config
{
1782 unsigned int num_pipes_active
;
1783 bool sprites_enabled
;
1784 bool sprites_scaled
;
1787 struct drm_i915_private
{
1788 struct drm_device drm
;
1790 struct kmem_cache
*objects
;
1791 struct kmem_cache
*vmas
;
1792 struct kmem_cache
*requests
;
1794 const struct intel_device_info info
;
1796 int relative_constants_mode
;
1800 struct intel_uncore uncore
;
1802 struct i915_virtual_gpu vgpu
;
1804 struct intel_gvt
*gvt
;
1806 struct intel_guc guc
;
1808 struct intel_csr csr
;
1810 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1812 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1813 * controller on different i2c buses. */
1814 struct mutex gmbus_mutex
;
1817 * Base address of the gmbus and gpio block.
1819 uint32_t gpio_mmio_base
;
1821 /* MMIO base address for MIPI regs */
1822 uint32_t mipi_mmio_base
;
1824 uint32_t psr_mmio_base
;
1826 uint32_t pps_mmio_base
;
1828 wait_queue_head_t gmbus_wait_queue
;
1830 struct pci_dev
*bridge_dev
;
1831 struct i915_gem_context
*kernel_context
;
1832 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
1833 struct i915_vma
*semaphore
;
1835 struct drm_dma_handle
*status_page_dmah
;
1836 struct resource mch_res
;
1838 /* protects the irq masks */
1839 spinlock_t irq_lock
;
1841 /* protects the mmio flip data */
1842 spinlock_t mmio_flip_lock
;
1844 bool display_irqs_enabled
;
1846 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1847 struct pm_qos_request pm_qos
;
1849 /* Sideband mailbox protection */
1850 struct mutex sb_lock
;
1852 /** Cached value of IMR to avoid reads in updating the bitfield */
1855 u32 de_irq_mask
[I915_MAX_PIPES
];
1862 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1864 struct i915_hotplug hotplug
;
1865 struct intel_fbc fbc
;
1866 struct i915_drrs drrs
;
1867 struct intel_opregion opregion
;
1868 struct intel_vbt_data vbt
;
1870 bool preserve_bios_swizzle
;
1873 struct intel_overlay
*overlay
;
1875 /* backlight registers and fields in struct intel_panel */
1876 struct mutex backlight_lock
;
1879 bool no_aux_handshake
;
1881 /* protects panel power sequencer state */
1882 struct mutex pps_mutex
;
1884 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1885 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1887 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1888 unsigned int skl_preferred_vco_freq
;
1889 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1890 unsigned int max_dotclk_freq
;
1891 unsigned int rawclk_freq
;
1892 unsigned int hpll_freq
;
1893 unsigned int czclk_freq
;
1896 unsigned int vco
, ref
;
1900 * wq - Driver workqueue for GEM.
1902 * NOTE: Work items scheduled here are not allowed to grab any modeset
1903 * locks, for otherwise the flushing done in the pageflip code will
1904 * result in deadlocks.
1906 struct workqueue_struct
*wq
;
1908 /* Display functions */
1909 struct drm_i915_display_funcs display
;
1911 /* PCH chipset type */
1912 enum intel_pch pch_type
;
1913 unsigned short pch_id
;
1915 unsigned long quirks
;
1917 enum modeset_restore modeset_restore
;
1918 struct mutex modeset_restore_lock
;
1919 struct drm_atomic_state
*modeset_restore_state
;
1920 struct drm_modeset_acquire_ctx reset_ctx
;
1922 struct list_head vm_list
; /* Global list of all address spaces */
1923 struct i915_ggtt ggtt
; /* VM representing the global address space */
1925 struct i915_gem_mm mm
;
1926 DECLARE_HASHTABLE(mm_structs
, 7);
1927 struct mutex mm_lock
;
1929 /* The hw wants to have a stable context identifier for the lifetime
1930 * of the context (for OA, PASID, faults, etc). This is limited
1931 * in execlists to 21 bits.
1933 struct ida context_hw_ida
;
1934 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1936 /* Kernel Modesetting */
1938 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1939 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1940 wait_queue_head_t pending_flip_queue
;
1942 #ifdef CONFIG_DEBUG_FS
1943 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1946 /* dpll and cdclk state is protected by connection_mutex */
1947 int num_shared_dpll
;
1948 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1949 const struct intel_dpll_mgr
*dpll_mgr
;
1952 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1953 * Must be global rather than per dpll, because on some platforms
1954 * plls share registers.
1956 struct mutex dpll_lock
;
1958 unsigned int active_crtcs
;
1959 unsigned int min_pixclk
[I915_MAX_PIPES
];
1961 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1963 struct i915_workarounds workarounds
;
1965 struct i915_frontbuffer_tracking fb_tracking
;
1969 bool mchbar_need_disable
;
1971 struct intel_l3_parity l3_parity
;
1973 /* Cannot be determined by PCIID. You must always read a register. */
1976 /* gen6+ rps state */
1977 struct intel_gen6_power_mgmt rps
;
1979 /* ilk-only ips/rps state. Everything in here is protected by the global
1980 * mchdev_lock in intel_pm.c */
1981 struct intel_ilk_power_mgmt ips
;
1983 struct i915_power_domains power_domains
;
1985 struct i915_psr psr
;
1987 struct i915_gpu_error gpu_error
;
1989 struct drm_i915_gem_object
*vlv_pctx
;
1991 #ifdef CONFIG_DRM_FBDEV_EMULATION
1992 /* list of fbdev register on this device */
1993 struct intel_fbdev
*fbdev
;
1994 struct work_struct fbdev_suspend_work
;
1997 struct drm_property
*broadcast_rgb_property
;
1998 struct drm_property
*force_audio_property
;
2000 /* hda/i915 audio component */
2001 struct i915_audio_component
*audio_component
;
2002 bool audio_component_registered
;
2004 * av_mutex - mutex for audio/video sync
2007 struct mutex av_mutex
;
2009 uint32_t hw_context_size
;
2010 struct list_head context_list
;
2014 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2015 u32 chv_phy_control
;
2017 * Shadows for CHV DPLL_MD regs to keep the state
2018 * checker somewhat working in the presence hardware
2019 * crappiness (can't read out DPLL_MD for pipes B & C).
2021 u32 chv_dpll_md
[I915_MAX_PIPES
];
2025 bool suspended_to_idle
;
2026 struct i915_suspend_saved_registers regfile
;
2027 struct vlv_s0ix_state vlv_s0ix_state
;
2030 I915_SAGV_UNKNOWN
= 0,
2033 I915_SAGV_NOT_CONTROLLED
2038 * Raw watermark latency values:
2039 * in 0.1us units for WM0,
2040 * in 0.5us units for WM1+.
2043 uint16_t pri_latency
[5];
2045 uint16_t spr_latency
[5];
2047 uint16_t cur_latency
[5];
2049 * Raw watermark memory latency values
2050 * for SKL for all 8 levels
2053 uint16_t skl_latency
[8];
2056 * The skl_wm_values structure is a bit too big for stack
2057 * allocation, so we keep the staging struct where we store
2058 * intermediate results here instead.
2060 struct skl_wm_values skl_results
;
2062 /* current hardware state */
2064 struct ilk_wm_values hw
;
2065 struct skl_wm_values skl_hw
;
2066 struct vlv_wm_values vlv
;
2072 * Should be held around atomic WM register writing; also
2073 * protects * intel_crtc->wm.active and
2074 * cstate->wm.need_postvbl_update.
2076 struct mutex wm_mutex
;
2079 * Set during HW readout of watermarks/DDB. Some platforms
2080 * need to know when we're still using BIOS-provided values
2081 * (which we don't fully trust).
2083 bool distrust_bios_wm
;
2086 struct i915_runtime_pm pm
;
2088 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2090 void (*resume
)(struct drm_i915_private
*);
2091 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2093 struct list_head timelines
;
2094 struct i915_gem_timeline global_timeline
;
2095 u32 active_requests
;
2098 * Is the GPU currently considered idle, or busy executing
2099 * userspace requests? Whilst idle, we allow runtime power
2100 * management to power down the hardware and display clocks.
2101 * In order to reduce the effect on performance, there
2102 * is a slight delay before we do so.
2107 * We leave the user IRQ off as much as possible,
2108 * but this means that requests will finish and never
2109 * be retired once the system goes idle. Set a timer to
2110 * fire periodically while the ring is running. When it
2111 * fires, go retire requests.
2113 struct delayed_work retire_work
;
2116 * When we detect an idle GPU, we want to turn on
2117 * powersaving features. So once we see that there
2118 * are no more requests outstanding and no more
2119 * arrive within a small period of time, we fire
2120 * off the idle_work.
2122 struct delayed_work idle_work
;
2124 ktime_t last_init_time
;
2127 /* perform PHY state sanity checks? */
2128 bool chv_phy_assert
[2];
2130 /* Used to save the pipe-to-encoder mapping for audio */
2131 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2134 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2135 * will be rejected. Instead look for a better place.
2139 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2141 return container_of(dev
, struct drm_i915_private
, drm
);
2144 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2146 return to_i915(dev_get_drvdata(kdev
));
2149 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2151 return container_of(guc
, struct drm_i915_private
, guc
);
2154 /* Simple iterator over all initialised engines */
2155 #define for_each_engine(engine__, dev_priv__, id__) \
2157 (id__) < I915_NUM_ENGINES; \
2159 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2161 #define __mask_next_bit(mask) ({ \
2162 int __idx = ffs(mask) - 1; \
2163 mask &= ~BIT(__idx); \
2167 /* Iterator over subset of engines selected by mask */
2168 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2169 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2170 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2172 enum hdmi_force_audio
{
2173 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2174 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2175 HDMI_AUDIO_AUTO
, /* trust EDID */
2176 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2179 #define I915_GTT_OFFSET_NONE ((u32)-1)
2181 struct drm_i915_gem_object_ops
{
2183 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2185 /* Interface between the GEM object and its backing storage.
2186 * get_pages() is called once prior to the use of the associated set
2187 * of pages before to binding them into the GTT, and put_pages() is
2188 * called after we no longer need them. As we expect there to be
2189 * associated cost with migrating pages between the backing storage
2190 * and making them available for the GPU (e.g. clflush), we may hold
2191 * onto the pages after they are no longer referenced by the GPU
2192 * in case they may be used again shortly (for example migrating the
2193 * pages to a different memory domain within the GTT). put_pages()
2194 * will therefore most likely be called when the object itself is
2195 * being released or under memory pressure (where we attempt to
2196 * reap pages for the shrinker).
2198 struct sg_table
*(*get_pages
)(struct drm_i915_gem_object
*);
2199 void (*put_pages
)(struct drm_i915_gem_object
*, struct sg_table
*);
2201 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2202 void (*release
)(struct drm_i915_gem_object
*);
2206 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2207 * considered to be the frontbuffer for the given plane interface-wise. This
2208 * doesn't mean that the hw necessarily already scans it out, but that any
2209 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2211 * We have one bit per pipe and per scanout plane type.
2213 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2214 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2215 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2216 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2217 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2218 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2219 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2220 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2221 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2222 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2223 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2224 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2226 struct drm_i915_gem_object
{
2227 struct drm_gem_object base
;
2229 const struct drm_i915_gem_object_ops
*ops
;
2231 /** List of VMAs backed by this object */
2232 struct list_head vma_list
;
2233 struct rb_root vma_tree
;
2235 /** Stolen memory for this object, instead of being backed by shmem. */
2236 struct drm_mm_node
*stolen
;
2237 struct list_head global_list
;
2239 struct rcu_head rcu
;
2240 struct llist_node freed
;
2244 * Whether the object is currently in the GGTT mmap.
2246 struct list_head userfault_link
;
2248 /** Used in execbuf to temporarily hold a ref */
2249 struct list_head obj_exec_link
;
2251 struct list_head batch_pool_link
;
2253 unsigned long flags
;
2256 * Have we taken a reference for the object for incomplete GPU
2259 #define I915_BO_ACTIVE_REF 0
2262 * Is the object to be mapped as read-only to the GPU
2263 * Only honoured if hardware has relevant pte bit
2265 unsigned long gt_ro
:1;
2266 unsigned int cache_level
:3;
2267 unsigned int cache_dirty
:1;
2269 atomic_t frontbuffer_bits
;
2270 unsigned int frontbuffer_ggtt_origin
; /* write once */
2272 /** Current tiling stride for the object, if it's tiled. */
2273 unsigned int tiling_and_stride
;
2274 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2275 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2276 #define STRIDE_MASK (~TILING_MASK)
2278 /** Count of VMA actually bound by this object */
2279 unsigned int bind_count
;
2280 unsigned int active_count
;
2281 unsigned int pin_display
;
2284 struct mutex lock
; /* protects the pages and their use */
2285 atomic_t pages_pin_count
;
2287 struct sg_table
*pages
;
2290 struct i915_gem_object_page_iter
{
2291 struct scatterlist
*sg_pos
;
2292 unsigned int sg_idx
; /* in pages, but 32bit eek! */
2294 struct radix_tree_root radix
;
2295 struct mutex lock
; /* protects this cache */
2299 * Advice: are the backing pages purgeable?
2301 unsigned int madv
:2;
2304 * This is set if the object has been written to since the
2305 * pages were last acquired.
2310 * This is set if the object has been pinned due to unknown
2316 /** Breadcrumb of last rendering to the buffer.
2317 * There can only be one writer, but we allow for multiple readers.
2318 * If there is a writer that necessarily implies that all other
2319 * read requests are complete - but we may only be lazily clearing
2320 * the read requests. A read request is naturally the most recent
2321 * request on a ring, so we may have two different write and read
2322 * requests on one ring where the write request is older than the
2323 * read request. This allows for the CPU to read from an active
2324 * buffer by only waiting for the write to complete.
2326 struct reservation_object
*resv
;
2328 /** References from framebuffers, locks out tiling changes. */
2329 unsigned long framebuffer_references
;
2331 /** Record of address bit 17 of each page at last unbind. */
2332 unsigned long *bit_17
;
2334 struct i915_gem_userptr
{
2336 unsigned read_only
:1;
2338 struct i915_mm_struct
*mm
;
2339 struct i915_mmu_object
*mmu_object
;
2340 struct work_struct
*work
;
2343 /** for phys allocated objects */
2344 struct drm_dma_handle
*phys_handle
;
2346 struct reservation_object __builtin_resv
;
2349 static inline struct drm_i915_gem_object
*
2350 to_intel_bo(struct drm_gem_object
*gem
)
2352 /* Assert that to_intel_bo(NULL) == NULL */
2353 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object
, base
));
2355 return container_of(gem
, struct drm_i915_gem_object
, base
);
2359 * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
2360 * @filp: DRM file private date
2361 * @handle: userspace handle
2365 * A pointer to the object named by the handle if such exists on @filp, NULL
2366 * otherwise. This object is only valid whilst under the RCU read lock, and
2367 * note carefully the object may be in the process of being destroyed.
2369 static inline struct drm_i915_gem_object
*
2370 i915_gem_object_lookup_rcu(struct drm_file
*file
, u32 handle
)
2372 #ifdef CONFIG_LOCKDEP
2373 WARN_ON(debug_locks
&& !lock_is_held(&rcu_lock_map
));
2375 return idr_find(&file
->object_idr
, handle
);
2378 static inline struct drm_i915_gem_object
*
2379 i915_gem_object_lookup(struct drm_file
*file
, u32 handle
)
2381 struct drm_i915_gem_object
*obj
;
2384 obj
= i915_gem_object_lookup_rcu(file
, handle
);
2385 if (obj
&& !kref_get_unless_zero(&obj
->base
.refcount
))
2393 extern struct drm_gem_object
*
2394 drm_gem_object_lookup(struct drm_file
*file
, u32 handle
);
2396 __attribute__((nonnull
))
2397 static inline struct drm_i915_gem_object
*
2398 i915_gem_object_get(struct drm_i915_gem_object
*obj
)
2400 drm_gem_object_reference(&obj
->base
);
2405 extern void drm_gem_object_reference(struct drm_gem_object
*);
2407 __attribute__((nonnull
))
2409 i915_gem_object_put(struct drm_i915_gem_object
*obj
)
2411 __drm_gem_object_unreference(&obj
->base
);
2415 extern void drm_gem_object_unreference(struct drm_gem_object
*);
2418 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object
*);
2421 i915_gem_object_is_dead(const struct drm_i915_gem_object
*obj
)
2423 return atomic_read(&obj
->base
.refcount
.refcount
) == 0;
2427 i915_gem_object_has_struct_page(const struct drm_i915_gem_object
*obj
)
2429 return obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
;
2433 i915_gem_object_is_active(const struct drm_i915_gem_object
*obj
)
2435 return obj
->active_count
;
2439 i915_gem_object_has_active_reference(const struct drm_i915_gem_object
*obj
)
2441 return test_bit(I915_BO_ACTIVE_REF
, &obj
->flags
);
2445 i915_gem_object_set_active_reference(struct drm_i915_gem_object
*obj
)
2447 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2448 __set_bit(I915_BO_ACTIVE_REF
, &obj
->flags
);
2452 i915_gem_object_clear_active_reference(struct drm_i915_gem_object
*obj
)
2454 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2455 __clear_bit(I915_BO_ACTIVE_REF
, &obj
->flags
);
2458 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object
*obj
);
2460 static inline unsigned int
2461 i915_gem_object_get_tiling(struct drm_i915_gem_object
*obj
)
2463 return obj
->tiling_and_stride
& TILING_MASK
;
2467 i915_gem_object_is_tiled(struct drm_i915_gem_object
*obj
)
2469 return i915_gem_object_get_tiling(obj
) != I915_TILING_NONE
;
2472 static inline unsigned int
2473 i915_gem_object_get_stride(struct drm_i915_gem_object
*obj
)
2475 return obj
->tiling_and_stride
& STRIDE_MASK
;
2478 static inline struct intel_engine_cs
*
2479 i915_gem_object_last_write_engine(struct drm_i915_gem_object
*obj
)
2481 struct intel_engine_cs
*engine
= NULL
;
2482 struct dma_fence
*fence
;
2485 fence
= reservation_object_get_excl_rcu(obj
->resv
);
2488 if (fence
&& dma_fence_is_i915(fence
) && !dma_fence_is_signaled(fence
))
2489 engine
= to_request(fence
)->engine
;
2490 dma_fence_put(fence
);
2495 static inline struct i915_vma
*i915_vma_get(struct i915_vma
*vma
)
2497 i915_gem_object_get(vma
->obj
);
2501 static inline void i915_vma_put(struct i915_vma
*vma
)
2503 i915_gem_object_put(vma
->obj
);
2507 * Optimised SGL iterator for GEM objects
2509 static __always_inline
struct sgt_iter
{
2510 struct scatterlist
*sgp
;
2517 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2518 struct sgt_iter s
= { .sgp
= sgl
};
2521 s
.max
= s
.curr
= s
.sgp
->offset
;
2522 s
.max
+= s
.sgp
->length
;
2524 s
.dma
= sg_dma_address(s
.sgp
);
2526 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2532 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2535 if (unlikely(sg_is_chain(sg
)))
2536 sg
= sg_chain_ptr(sg
);
2541 * __sg_next - return the next scatterlist entry in a list
2542 * @sg: The current sg entry
2545 * If the entry is the last, return NULL; otherwise, step to the next
2546 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2547 * otherwise just return the pointer to the current element.
2549 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2551 #ifdef CONFIG_DEBUG_SG
2552 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2554 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2558 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2559 * @__dmap: DMA address (output)
2560 * @__iter: 'struct sgt_iter' (iterator state, internal)
2561 * @__sgt: sg_table to iterate over (input)
2563 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2564 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2565 ((__dmap) = (__iter).dma + (__iter).curr); \
2566 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2567 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2570 * for_each_sgt_page - iterate over the pages of the given sg_table
2571 * @__pp: page pointer (output)
2572 * @__iter: 'struct sgt_iter' (iterator state, internal)
2573 * @__sgt: sg_table to iterate over (input)
2575 #define for_each_sgt_page(__pp, __iter, __sgt) \
2576 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2577 ((__pp) = (__iter).pfn == 0 ? NULL : \
2578 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2579 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2580 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2583 * A command that requires special handling by the command parser.
2585 struct drm_i915_cmd_descriptor
{
2587 * Flags describing how the command parser processes the command.
2589 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2590 * a length mask if not set
2591 * CMD_DESC_SKIP: The command is allowed but does not follow the
2592 * standard length encoding for the opcode range in
2594 * CMD_DESC_REJECT: The command is never allowed
2595 * CMD_DESC_REGISTER: The command should be checked against the
2596 * register whitelist for the appropriate ring
2597 * CMD_DESC_MASTER: The command is allowed if the submitting process
2601 #define CMD_DESC_FIXED (1<<0)
2602 #define CMD_DESC_SKIP (1<<1)
2603 #define CMD_DESC_REJECT (1<<2)
2604 #define CMD_DESC_REGISTER (1<<3)
2605 #define CMD_DESC_BITMASK (1<<4)
2606 #define CMD_DESC_MASTER (1<<5)
2609 * The command's unique identification bits and the bitmask to get them.
2610 * This isn't strictly the opcode field as defined in the spec and may
2611 * also include type, subtype, and/or subop fields.
2619 * The command's length. The command is either fixed length (i.e. does
2620 * not include a length field) or has a length field mask. The flag
2621 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2622 * a length mask. All command entries in a command table must include
2623 * length information.
2631 * Describes where to find a register address in the command to check
2632 * against the ring's register whitelist. Only valid if flags has the
2633 * CMD_DESC_REGISTER bit set.
2635 * A non-zero step value implies that the command may access multiple
2636 * registers in sequence (e.g. LRI), in that case step gives the
2637 * distance in dwords between individual offset fields.
2645 #define MAX_CMD_DESC_BITMASKS 3
2647 * Describes command checks where a particular dword is masked and
2648 * compared against an expected value. If the command does not match
2649 * the expected value, the parser rejects it. Only valid if flags has
2650 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2653 * If the check specifies a non-zero condition_mask then the parser
2654 * only performs the check when the bits specified by condition_mask
2661 u32 condition_offset
;
2663 } bits
[MAX_CMD_DESC_BITMASKS
];
2667 * A table of commands requiring special handling by the command parser.
2669 * Each engine has an array of tables. Each table consists of an array of
2670 * command descriptors, which must be sorted with command opcodes in
2673 struct drm_i915_cmd_table
{
2674 const struct drm_i915_cmd_descriptor
*table
;
2678 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2679 #define __I915__(p) ({ \
2680 struct drm_i915_private *__p; \
2681 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2682 __p = (struct drm_i915_private *)p; \
2683 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2684 __p = to_i915((struct drm_device *)p); \
2689 #define INTEL_INFO(p) (&__I915__(p)->info)
2691 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2692 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2694 #define REVID_FOREVER 0xff
2695 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2697 #define GEN_FOREVER (0)
2699 * Returns true if Gen is in inclusive range [Start, End].
2701 * Use GEN_FOREVER for unbound start and or end.
2703 #define IS_GEN(dev_priv, s, e) ({ \
2704 unsigned int __s = (s), __e = (e); \
2705 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2706 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2707 if ((__s) != GEN_FOREVER) \
2709 if ((__e) == GEN_FOREVER) \
2710 __e = BITS_PER_LONG - 1; \
2713 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2717 * Return true if revision is in range [since,until] inclusive.
2719 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2721 #define IS_REVID(p, since, until) \
2722 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2724 #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
2725 #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
2726 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2727 #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
2728 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2729 #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
2730 #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
2731 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2732 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2733 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2734 #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
2735 #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
2736 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2737 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2738 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2739 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2740 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2741 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
2742 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2743 INTEL_DEVID(dev_priv) == 0x0152 || \
2744 INTEL_DEVID(dev_priv) == 0x015a)
2745 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
2746 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
2747 #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
2748 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
2749 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
2750 #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
2751 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
2752 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2753 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2754 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2755 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2756 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2757 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2758 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2759 /* ULX machines are also considered ULT. */
2760 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2761 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2762 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2763 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2764 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2765 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2766 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2767 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2768 /* ULX machines are also considered ULT. */
2769 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2770 INTEL_DEVID(dev_priv) == 0x0A1E)
2771 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2772 INTEL_DEVID(dev_priv) == 0x1913 || \
2773 INTEL_DEVID(dev_priv) == 0x1916 || \
2774 INTEL_DEVID(dev_priv) == 0x1921 || \
2775 INTEL_DEVID(dev_priv) == 0x1926)
2776 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2777 INTEL_DEVID(dev_priv) == 0x1915 || \
2778 INTEL_DEVID(dev_priv) == 0x191E)
2779 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2780 INTEL_DEVID(dev_priv) == 0x5913 || \
2781 INTEL_DEVID(dev_priv) == 0x5916 || \
2782 INTEL_DEVID(dev_priv) == 0x5921 || \
2783 INTEL_DEVID(dev_priv) == 0x5926)
2784 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2785 INTEL_DEVID(dev_priv) == 0x5915 || \
2786 INTEL_DEVID(dev_priv) == 0x591E)
2787 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2788 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2789 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2790 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2792 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2794 #define SKL_REVID_A0 0x0
2795 #define SKL_REVID_B0 0x1
2796 #define SKL_REVID_C0 0x2
2797 #define SKL_REVID_D0 0x3
2798 #define SKL_REVID_E0 0x4
2799 #define SKL_REVID_F0 0x5
2800 #define SKL_REVID_G0 0x6
2801 #define SKL_REVID_H0 0x7
2803 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2805 #define BXT_REVID_A0 0x0
2806 #define BXT_REVID_A1 0x1
2807 #define BXT_REVID_B0 0x3
2808 #define BXT_REVID_C0 0x9
2810 #define IS_BXT_REVID(dev_priv, since, until) \
2811 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2813 #define KBL_REVID_A0 0x0
2814 #define KBL_REVID_B0 0x1
2815 #define KBL_REVID_C0 0x2
2816 #define KBL_REVID_D0 0x3
2817 #define KBL_REVID_E0 0x4
2819 #define IS_KBL_REVID(dev_priv, since, until) \
2820 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2823 * The genX designation typically refers to the render engine, so render
2824 * capability related checks should use IS_GEN, while display and other checks
2825 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2828 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2829 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2830 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2831 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2832 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2833 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2834 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2835 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2837 #define ENGINE_MASK(id) BIT(id)
2838 #define RENDER_RING ENGINE_MASK(RCS)
2839 #define BSD_RING ENGINE_MASK(VCS)
2840 #define BLT_RING ENGINE_MASK(BCS)
2841 #define VEBOX_RING ENGINE_MASK(VECS)
2842 #define BSD2_RING ENGINE_MASK(VCS2)
2843 #define ALL_ENGINES (~0)
2845 #define HAS_ENGINE(dev_priv, id) \
2846 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2848 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2849 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2850 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2851 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2853 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2854 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2855 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2856 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2857 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2858 #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
2860 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
2861 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts)
2862 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2863 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2864 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2866 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2867 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2869 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2870 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
2872 /* WaRsDisableCoarsePowerGating:skl,bxt */
2873 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2874 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2875 IS_SKL_GT3(dev_priv) || \
2876 IS_SKL_GT4(dev_priv))
2879 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2880 * even when in MSI mode. This results in spurious interrupt warnings if the
2881 * legacy irq no. is shared with another device. The kernel then disables that
2882 * interrupt source and so prevents the other device from working properly.
2884 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2885 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
2887 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2888 * rows, which changed the alignment requirements and fence programming.
2890 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2891 !(IS_I915G(dev_priv) || \
2892 IS_I915GM(dev_priv)))
2893 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2894 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2896 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2897 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2898 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2900 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2902 #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
2904 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2905 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2906 #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
2907 #define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
2908 #define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p)
2910 #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
2912 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2914 * For now, anything with a GuC requires uCode loading, and then supports
2915 * command submission once loaded. But these are logically independent
2916 * properties, so we have separate macros to test them.
2918 #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
2919 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2920 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2922 #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
2924 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2926 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2927 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2928 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2929 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2930 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2931 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2932 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2933 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2934 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2935 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2936 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2937 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2939 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2940 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2941 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2942 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2943 #define HAS_PCH_LPT_LP(dev_priv) \
2944 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2945 #define HAS_PCH_LPT_H(dev_priv) \
2946 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2947 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2948 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2949 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2950 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2952 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2954 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2956 /* DPF == dynamic parity feature */
2957 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2958 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2959 2 : HAS_L3_DPF(dev_priv))
2961 #define GT_FREQUENCY_MULTIPLIER 50
2962 #define GEN9_FREQ_SCALER 3
2964 #include "i915_trace.h"
2966 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2968 #ifdef CONFIG_INTEL_IOMMU
2969 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2975 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2976 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2978 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2981 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2985 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2986 const char *fmt
, ...);
2988 #define i915_report_error(dev_priv, fmt, ...) \
2989 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2991 #ifdef CONFIG_COMPAT
2992 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2995 extern const struct dev_pm_ops i915_pm_ops
;
2997 extern int i915_driver_load(struct pci_dev
*pdev
,
2998 const struct pci_device_id
*ent
);
2999 extern void i915_driver_unload(struct drm_device
*dev
);
3000 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3001 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3002 extern void i915_reset(struct drm_i915_private
*dev_priv
);
3003 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3004 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3005 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3006 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3007 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3008 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3009 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3011 /* intel_hotplug.c */
3012 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3013 u32 pin_mask
, u32 long_mask
);
3014 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3015 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3016 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3017 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
3018 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3019 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3022 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3024 unsigned long delay
;
3026 if (unlikely(!i915
.enable_hangcheck
))
3029 /* Don't continually defer the hangcheck so that it is always run at
3030 * least once after work has been scheduled on any ring. Otherwise,
3031 * we will ignore a hung ring if a second ring is kept busy.
3034 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3035 queue_delayed_work(system_long_wq
,
3036 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3040 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3042 const char *fmt
, ...);
3044 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3045 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3046 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3048 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
3049 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
3050 bool restore_forcewake
);
3051 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
3052 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
3053 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
3054 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
3055 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
3057 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
3058 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
3059 enum forcewake_domains domains
);
3060 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
3061 enum forcewake_domains domains
);
3062 /* Like above but the caller must manage the uncore.lock itself.
3063 * Must be used with I915_READ_FW and friends.
3065 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
3066 enum forcewake_domains domains
);
3067 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
3068 enum forcewake_domains domains
);
3069 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
3071 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
3073 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
3077 const unsigned long timeout_ms
);
3078 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
3082 const unsigned long timeout_ms
);
3084 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3086 return dev_priv
->gvt
;
3089 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3091 return dev_priv
->vgpu
.active
;
3095 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3099 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3102 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3103 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3104 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3107 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3108 uint32_t interrupt_mask
,
3109 uint32_t enabled_irq_mask
);
3111 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3113 ilk_update_display_irq(dev_priv
, bits
, bits
);
3116 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3118 ilk_update_display_irq(dev_priv
, bits
, 0);
3120 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3122 uint32_t interrupt_mask
,
3123 uint32_t enabled_irq_mask
);
3124 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3125 enum pipe pipe
, uint32_t bits
)
3127 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3129 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3130 enum pipe pipe
, uint32_t bits
)
3132 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3134 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3135 uint32_t interrupt_mask
,
3136 uint32_t enabled_irq_mask
);
3138 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3140 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3143 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3145 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3149 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3150 struct drm_file
*file_priv
);
3151 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3152 struct drm_file
*file_priv
);
3153 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3154 struct drm_file
*file_priv
);
3155 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3156 struct drm_file
*file_priv
);
3157 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3158 struct drm_file
*file_priv
);
3159 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3160 struct drm_file
*file_priv
);
3161 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3162 struct drm_file
*file_priv
);
3163 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3164 struct drm_file
*file_priv
);
3165 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3166 struct drm_file
*file_priv
);
3167 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3168 struct drm_file
*file_priv
);
3169 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3170 struct drm_file
*file
);
3171 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3172 struct drm_file
*file
);
3173 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3174 struct drm_file
*file_priv
);
3175 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3176 struct drm_file
*file_priv
);
3177 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
3178 struct drm_file
*file_priv
);
3179 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
3180 struct drm_file
*file_priv
);
3181 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3182 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3183 struct drm_file
*file
);
3184 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3185 struct drm_file
*file_priv
);
3186 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3187 struct drm_file
*file_priv
);
3188 int i915_gem_load_init(struct drm_device
*dev
);
3189 void i915_gem_load_cleanup(struct drm_device
*dev
);
3190 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3191 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3192 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3194 void *i915_gem_object_alloc(struct drm_device
*dev
);
3195 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3196 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3197 const struct drm_i915_gem_object_ops
*ops
);
3198 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3200 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3201 struct drm_device
*dev
, const void *data
, size_t size
);
3202 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3203 void i915_gem_free_object(struct drm_gem_object
*obj
);
3205 struct i915_vma
* __must_check
3206 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3207 const struct i915_ggtt_view
*view
,
3212 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3214 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3215 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3216 void i915_vma_close(struct i915_vma
*vma
);
3217 void i915_vma_destroy(struct i915_vma
*vma
);
3219 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3220 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3222 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3224 static inline int __sg_page_count(const struct scatterlist
*sg
)
3226 return sg
->length
>> PAGE_SHIFT
;
3229 struct scatterlist
*
3230 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3231 unsigned int n
, unsigned int *offset
);
3234 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3238 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3242 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3245 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3246 struct sg_table
*pages
);
3247 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3249 static inline int __must_check
3250 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3252 might_lock(&obj
->mm
.lock
);
3254 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3257 return __i915_gem_object_get_pages(obj
);
3261 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3263 GEM_BUG_ON(!obj
->mm
.pages
);
3265 atomic_inc(&obj
->mm
.pages_pin_count
);
3269 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3271 return atomic_read(&obj
->mm
.pages_pin_count
);
3275 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3277 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3278 GEM_BUG_ON(!obj
->mm
.pages
);
3280 atomic_dec(&obj
->mm
.pages_pin_count
);
3281 GEM_BUG_ON(atomic_read(&obj
->mm
.pages_pin_count
) < obj
->bind_count
);
3285 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3287 __i915_gem_object_unpin_pages(obj
);
3290 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3295 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3296 enum i915_mm_subclass subclass
);
3297 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3299 enum i915_map_type
{
3305 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3306 * @obj - the object to map into kernel address space
3307 * @type - the type of mapping, used to select pgprot_t
3309 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3310 * pages and then returns a contiguous mapping of the backing storage into
3311 * the kernel address space. Based on the @type of mapping, the PTE will be
3312 * set to either WriteBack or WriteCombine (via pgprot_t).
3314 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3315 * mapping is no longer required.
3317 * Returns the pointer through which to access the mapped object, or an
3318 * ERR_PTR() on error.
3320 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3321 enum i915_map_type type
);
3324 * i915_gem_object_unpin_map - releases an earlier mapping
3325 * @obj - the object to unmap
3327 * After pinning the object and mapping its pages, once you are finished
3328 * with your access, call i915_gem_object_unpin_map() to release the pin
3329 * upon the mapping. Once the pin count reaches zero, that mapping may be
3332 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3334 i915_gem_object_unpin_pages(obj
);
3337 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3338 unsigned int *needs_clflush
);
3339 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3340 unsigned int *needs_clflush
);
3341 #define CLFLUSH_BEFORE 0x1
3342 #define CLFLUSH_AFTER 0x2
3343 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3346 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3348 i915_gem_object_unpin_pages(obj
);
3351 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3352 void i915_vma_move_to_active(struct i915_vma
*vma
,
3353 struct drm_i915_gem_request
*req
,
3354 unsigned int flags
);
3355 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3356 struct drm_device
*dev
,
3357 struct drm_mode_create_dumb
*args
);
3358 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3359 uint32_t handle
, uint64_t *offset
);
3360 int i915_gem_mmap_gtt_version(void);
3362 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3363 struct drm_i915_gem_object
*new,
3364 unsigned frontbuffer_bits
);
3366 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3368 struct drm_i915_gem_request
*
3369 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3371 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3373 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3375 return unlikely(test_bit(I915_RESET_IN_PROGRESS
, &error
->flags
));
3378 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3380 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3383 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3385 return i915_reset_in_progress(error
) | i915_terminally_wedged(error
);
3388 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3390 return READ_ONCE(error
->reset_count
);
3393 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3394 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3395 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3396 int __must_check
i915_gem_init(struct drm_device
*dev
);
3397 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3398 void i915_gem_init_swizzling(struct drm_device
*dev
);
3399 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3400 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3401 unsigned int flags
);
3402 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3403 void i915_gem_resume(struct drm_device
*dev
);
3404 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3405 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3408 struct intel_rps_client
*rps
);
3410 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3413 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3414 struct i915_vma
* __must_check
3415 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3417 const struct i915_ggtt_view
*view
);
3418 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3419 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3421 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3422 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3424 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
, u64 size
,
3426 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
3427 int tiling_mode
, bool fenced
);
3429 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3430 enum i915_cache_level cache_level
);
3432 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3433 struct dma_buf
*dma_buf
);
3435 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3436 struct drm_gem_object
*gem_obj
, int flags
);
3439 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3440 struct i915_address_space
*vm
,
3441 const struct i915_ggtt_view
*view
);
3444 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3445 struct i915_address_space
*vm
,
3446 const struct i915_ggtt_view
*view
);
3448 static inline struct i915_hw_ppgtt
*
3449 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3451 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3454 static inline struct i915_vma
*
3455 i915_gem_object_to_ggtt(struct drm_i915_gem_object
*obj
,
3456 const struct i915_ggtt_view
*view
)
3458 return i915_gem_obj_to_vma(obj
, &to_i915(obj
->base
.dev
)->ggtt
.base
, view
);
3461 static inline unsigned long
3462 i915_gem_object_ggtt_offset(struct drm_i915_gem_object
*o
,
3463 const struct i915_ggtt_view
*view
)
3465 return i915_ggtt_offset(i915_gem_object_to_ggtt(o
, view
));
3468 /* i915_gem_fence.c */
3469 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3470 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3473 * i915_vma_pin_fence - pin fencing state
3474 * @vma: vma to pin fencing for
3476 * This pins the fencing state (whether tiled or untiled) to make sure the
3477 * vma (and its object) is ready to be used as a scanout target. Fencing
3478 * status must be synchronize first by calling i915_vma_get_fence():
3480 * The resulting fence pin reference must be released again with
3481 * i915_vma_unpin_fence().
3485 * True if the vma has a fence, false otherwise.
3488 i915_vma_pin_fence(struct i915_vma
*vma
)
3490 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3492 vma
->fence
->pin_count
++;
3499 * i915_vma_unpin_fence - unpin fencing state
3500 * @vma: vma to unpin fencing for
3502 * This releases the fence pin reference acquired through
3503 * i915_vma_pin_fence. It will handle both objects with and without an
3504 * attached fence correctly, callers do not need to distinguish this.
3507 i915_vma_unpin_fence(struct i915_vma
*vma
)
3509 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3511 GEM_BUG_ON(vma
->fence
->pin_count
<= 0);
3512 vma
->fence
->pin_count
--;
3516 void i915_gem_restore_fences(struct drm_device
*dev
);
3518 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3519 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3520 struct sg_table
*pages
);
3521 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3522 struct sg_table
*pages
);
3524 /* i915_gem_context.c */
3525 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3526 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3527 void i915_gem_context_fini(struct drm_device
*dev
);
3528 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3529 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3530 int i915_switch_context(struct drm_i915_gem_request
*req
);
3531 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
);
3533 i915_gem_context_pin_legacy(struct i915_gem_context
*ctx
,
3534 unsigned int flags
);
3535 void i915_gem_context_free(struct kref
*ctx_ref
);
3536 struct drm_i915_gem_object
*
3537 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3538 struct i915_gem_context
*
3539 i915_gem_context_create_gvt(struct drm_device
*dev
);
3541 static inline struct i915_gem_context
*
3542 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3544 struct i915_gem_context
*ctx
;
3546 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3548 ctx
= idr_find(&file_priv
->context_idr
, id
);
3550 return ERR_PTR(-ENOENT
);
3555 static inline struct i915_gem_context
*
3556 i915_gem_context_get(struct i915_gem_context
*ctx
)
3558 kref_get(&ctx
->ref
);
3562 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3564 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3565 kref_put(&ctx
->ref
, i915_gem_context_free
);
3568 static inline struct intel_timeline
*
3569 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3570 struct intel_engine_cs
*engine
)
3572 struct i915_address_space
*vm
;
3574 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3575 return &vm
->timeline
.engine
[engine
->id
];
3578 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3580 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3583 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3584 struct drm_file
*file
);
3585 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3586 struct drm_file
*file
);
3587 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3588 struct drm_file
*file_priv
);
3589 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3590 struct drm_file
*file_priv
);
3591 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3592 struct drm_file
*file
);
3594 /* i915_gem_evict.c */
3595 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3596 u64 min_size
, u64 alignment
,
3597 unsigned cache_level
,
3600 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3601 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3603 /* belongs in i915_gem_gtt.h */
3604 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3607 if (INTEL_GEN(dev_priv
) < 6)
3608 intel_gtt_chipset_flush();
3611 /* i915_gem_stolen.c */
3612 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3613 struct drm_mm_node
*node
, u64 size
,
3614 unsigned alignment
);
3615 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3616 struct drm_mm_node
*node
, u64 size
,
3617 unsigned alignment
, u64 start
,
3619 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3620 struct drm_mm_node
*node
);
3621 int i915_gem_init_stolen(struct drm_device
*dev
);
3622 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3623 struct drm_i915_gem_object
*
3624 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3625 struct drm_i915_gem_object
*
3626 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3631 /* i915_gem_internal.c */
3632 struct drm_i915_gem_object
*
3633 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3636 /* i915_gem_shrinker.c */
3637 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3638 unsigned long target
,
3640 #define I915_SHRINK_PURGEABLE 0x1
3641 #define I915_SHRINK_UNBOUND 0x2
3642 #define I915_SHRINK_BOUND 0x4
3643 #define I915_SHRINK_ACTIVE 0x8
3644 #define I915_SHRINK_VMAPS 0x10
3645 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3646 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3647 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3650 /* i915_gem_tiling.c */
3651 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3653 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3655 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3656 i915_gem_object_is_tiled(obj
);
3659 /* i915_debugfs.c */
3660 #ifdef CONFIG_DEBUG_FS
3661 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3662 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3663 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3664 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3666 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3667 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3668 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3670 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3673 /* i915_gpu_error.c */
3674 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3677 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3678 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3679 const struct i915_error_state_file_priv
*error
);
3680 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3681 struct drm_i915_private
*i915
,
3682 size_t count
, loff_t pos
);
3683 static inline void i915_error_state_buf_release(
3684 struct drm_i915_error_state_buf
*eb
)
3688 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3690 const char *error_msg
);
3691 void i915_error_state_get(struct drm_device
*dev
,
3692 struct i915_error_state_file_priv
*error_priv
);
3693 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3694 void i915_destroy_error_state(struct drm_device
*dev
);
3698 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3700 const char *error_msg
)
3704 static inline void i915_destroy_error_state(struct drm_device
*dev
)
3710 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3712 /* i915_cmd_parser.c */
3713 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3714 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3715 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3716 bool intel_engine_needs_cmd_parser(struct intel_engine_cs
*engine
);
3717 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3718 struct drm_i915_gem_object
*batch_obj
,
3719 struct drm_i915_gem_object
*shadow_batch_obj
,
3720 u32 batch_start_offset
,
3724 /* i915_suspend.c */
3725 extern int i915_save_state(struct drm_device
*dev
);
3726 extern int i915_restore_state(struct drm_device
*dev
);
3729 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3730 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3733 extern int intel_setup_gmbus(struct drm_device
*dev
);
3734 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3735 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3738 extern struct i2c_adapter
*
3739 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3740 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3741 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3742 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3744 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3746 extern void intel_i2c_reset(struct drm_device
*dev
);
3749 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3750 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3751 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3752 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3753 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3754 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3755 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3756 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3757 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3759 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3763 /* intel_opregion.c */
3765 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3766 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3767 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3768 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3769 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3771 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3773 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3775 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3776 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3777 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3778 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3782 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3787 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3791 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3799 extern void intel_register_dsm_handler(void);
3800 extern void intel_unregister_dsm_handler(void);
3802 static inline void intel_register_dsm_handler(void) { return; }
3803 static inline void intel_unregister_dsm_handler(void) { return; }
3804 #endif /* CONFIG_ACPI */
3806 /* intel_device_info.c */
3807 static inline struct intel_device_info
*
3808 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3810 return (struct intel_device_info
*)&dev_priv
->info
;
3813 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3814 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3817 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3818 extern int intel_modeset_init(struct drm_device
*dev
);
3819 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3820 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3821 extern int intel_connector_register(struct drm_connector
*);
3822 extern void intel_connector_unregister(struct drm_connector
*);
3823 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3824 extern void intel_display_resume(struct drm_device
*dev
);
3825 extern void i915_redisable_vga(struct drm_device
*dev
);
3826 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3827 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3828 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3829 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3830 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3833 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3834 struct drm_file
*file
);
3837 extern struct intel_overlay_error_state
*
3838 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3839 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3840 struct intel_overlay_error_state
*error
);
3842 extern struct intel_display_error_state
*
3843 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3844 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3845 struct drm_device
*dev
,
3846 struct intel_display_error_state
*error
);
3848 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3849 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3851 /* intel_sideband.c */
3852 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3853 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3854 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3855 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3856 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3857 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3858 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3859 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3860 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3861 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3862 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3863 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3864 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3865 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3866 enum intel_sbi_destination destination
);
3867 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3868 enum intel_sbi_destination destination
);
3869 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3870 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3872 /* intel_dpio_phy.c */
3873 void bxt_port_to_phy_channel(enum port port
,
3874 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3875 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3876 enum port port
, u32 margin
, u32 scale
,
3877 u32 enable
, u32 deemphasis
);
3878 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3879 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3880 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3882 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3884 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3885 uint8_t lane_count
);
3886 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3887 uint8_t lane_lat_optim_mask
);
3888 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3890 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3891 u32 deemph_reg_value
, u32 margin_reg_value
,
3892 bool uniq_trans_scale
);
3893 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3895 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3896 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3897 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3898 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3900 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3901 u32 demph_reg_value
, u32 preemph_reg_value
,
3902 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3903 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3904 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3905 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3907 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3908 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3910 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3911 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3913 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3914 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3915 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3916 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3918 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3919 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3920 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3921 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3923 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3924 * will be implemented using 2 32-bit writes in an arbitrary order with
3925 * an arbitrary delay between them. This can cause the hardware to
3926 * act upon the intermediate value, possibly leading to corruption and
3927 * machine death. For this reason we do not support I915_WRITE64, or
3928 * dev_priv->uncore.funcs.mmio_writeq.
3930 * When reading a 64-bit value as two 32-bit values, the delay may cause
3931 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3932 * occasionally a 64-bit register does not actualy support a full readq
3933 * and must be read using two 32-bit reads.
3935 * You have been warned.
3937 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3939 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3940 u32 upper, lower, old_upper, loop = 0; \
3941 upper = I915_READ(upper_reg); \
3943 old_upper = upper; \
3944 lower = I915_READ(lower_reg); \
3945 upper = I915_READ(upper_reg); \
3946 } while (upper != old_upper && loop++ < 2); \
3947 (u64)upper << 32 | lower; })
3949 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3950 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3952 #define __raw_read(x, s) \
3953 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3956 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3959 #define __raw_write(x, s) \
3960 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3961 i915_reg_t reg, uint##x##_t val) \
3963 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3978 /* These are untraced mmio-accessors that are only valid to be used inside
3979 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3982 * Think twice, and think again, before using these.
3984 * As an example, these accessors can possibly be used between:
3986 * spin_lock_irq(&dev_priv->uncore.lock);
3987 * intel_uncore_forcewake_get__locked();
3991 * intel_uncore_forcewake_put__locked();
3992 * spin_unlock_irq(&dev_priv->uncore.lock);
3995 * Note: some registers may not need forcewake held, so
3996 * intel_uncore_forcewake_{get,put} can be omitted, see
3997 * intel_uncore_forcewake_for_reg().
3999 * Certain architectures will die if the same cacheline is concurrently accessed
4000 * by different clients (e.g. on Ivybridge). Access to registers should
4001 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4002 * a more localised lock guarding all access to that bank of registers.
4004 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4005 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4006 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4007 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4009 /* "Broadcast RGB" property */
4010 #define INTEL_BROADCAST_RGB_AUTO 0
4011 #define INTEL_BROADCAST_RGB_FULL 1
4012 #define INTEL_BROADCAST_RGB_LIMITED 2
4014 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
4016 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4017 return VLV_VGACNTRL
;
4018 else if (INTEL_GEN(dev_priv
) >= 5)
4019 return CPU_VGACNTRL
;
4024 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
4026 unsigned long j
= msecs_to_jiffies(m
);
4028 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4031 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4033 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4036 static inline unsigned long
4037 timespec_to_jiffies_timeout(const struct timespec
*value
)
4039 unsigned long j
= timespec_to_jiffies(value
);
4041 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4045 * If you need to wait X milliseconds between events A and B, but event B
4046 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4047 * when event A happened, then just before event B you call this function and
4048 * pass the timestamp as the first argument, and X as the second argument.
4051 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4053 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4056 * Don't re-read the value of "jiffies" every time since it may change
4057 * behind our back and break the math.
4059 tmp_jiffies
= jiffies
;
4060 target_jiffies
= timestamp_jiffies
+
4061 msecs_to_jiffies_timeout(to_wait_ms
);
4063 if (time_after(target_jiffies
, tmp_jiffies
)) {
4064 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4065 while (remaining_jiffies
)
4067 schedule_timeout_uninterruptible(remaining_jiffies
);
4072 __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
4074 struct intel_engine_cs
*engine
= req
->engine
;
4076 /* Before we do the heavier coherent read of the seqno,
4077 * check the value (hopefully) in the CPU cacheline.
4079 if (__i915_gem_request_completed(req
))
4082 /* Ensure our read of the seqno is coherent so that we
4083 * do not "miss an interrupt" (i.e. if this is the last
4084 * request and the seqno write from the GPU is not visible
4085 * by the time the interrupt fires, we will see that the
4086 * request is incomplete and go back to sleep awaiting
4087 * another interrupt that will never come.)
4089 * Strictly, we only need to do this once after an interrupt,
4090 * but it is easier and safer to do it every time the waiter
4093 if (engine
->irq_seqno_barrier
&&
4094 rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
4095 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
4096 struct task_struct
*tsk
;
4098 /* The ordering of irq_posted versus applying the barrier
4099 * is crucial. The clearing of the current irq_posted must
4100 * be visible before we perform the barrier operation,
4101 * such that if a subsequent interrupt arrives, irq_posted
4102 * is reasserted and our task rewoken (which causes us to
4103 * do another __i915_request_irq_complete() immediately
4104 * and reapply the barrier). Conversely, if the clear
4105 * occurs after the barrier, then an interrupt that arrived
4106 * whilst we waited on the barrier would not trigger a
4107 * barrier on the next pass, and the read may not see the
4110 engine
->irq_seqno_barrier(engine
);
4112 /* If we consume the irq, but we are no longer the bottom-half,
4113 * the real bottom-half may not have serialised their own
4114 * seqno check with the irq-barrier (i.e. may have inspected
4115 * the seqno before we believe it coherent since they see
4116 * irq_posted == false but we are still running).
4119 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
4120 if (tsk
&& tsk
!= current
)
4121 /* Note that if the bottom-half is changed as we
4122 * are sending the wake-up, the new bottom-half will
4123 * be woken by whomever made the change. We only have
4124 * to worry about when we steal the irq-posted for
4127 wake_up_process(tsk
);
4130 if (__i915_gem_request_completed(req
))
4137 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4138 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4141 int remap_io_mapping(struct vm_area_struct
*vma
,
4142 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4143 struct io_mapping
*iomap
);
4145 #define ptr_mask_bits(ptr) ({ \
4146 unsigned long __v = (unsigned long)(ptr); \
4147 (typeof(ptr))(__v & PAGE_MASK); \
4150 #define ptr_unpack_bits(ptr, bits) ({ \
4151 unsigned long __v = (unsigned long)(ptr); \
4152 (bits) = __v & ~PAGE_MASK; \
4153 (typeof(ptr))(__v & PAGE_MASK); \
4156 #define ptr_pack_bits(ptr, bits) \
4157 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
4159 #define fetch_and_zero(ptr) ({ \
4160 typeof(*ptr) __T = *(ptr); \
4161 *(ptr) = (typeof(*ptr))0; \