drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include <linux/io-mapping.h>
  35
  36 /* General customization:
  37  */
  38
  39 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  40
  41 #define DRIVER_NAME             "i915"
  42 #define DRIVER_DESC             "Intel Graphics"
  43 #define DRIVER_DATE             "20080730"
  44
  45 enum pipe {
  46         PIPE_A = 0,
  47         PIPE_B,
  48 };
  49
  50 #define I915_NUM_PIPE   2
  51
  52 /* Interface history:
  53  *
  54  * 1.1: Original.
  55  * 1.2: Add Power Management
  56  * 1.3: Add vblank support
  57  * 1.4: Fix cmdbuffer path, add heap destroy
  58  * 1.5: Add vblank pipe configuration
  59  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  60  *      - Support vertical blank on secondary display pipe
  61  */
  62 #define DRIVER_MAJOR            1
  63 #define DRIVER_MINOR            6
  64 #define DRIVER_PATCHLEVEL       0
  65
  66 #define WATCH_COHERENCY 0
  67 #define WATCH_BUF       0
  68 #define WATCH_EXEC      0
  69 #define WATCH_LRU       0
  70 #define WATCH_RELOC     0
  71 #define WATCH_INACTIVE  0
  72 #define WATCH_PWRITE    0
  73
  74 typedef struct _drm_i915_ring_buffer {
  75         int tail_mask;
  76         unsigned long Size;
  77         u8 *virtual_start;
  78         int head;
  79         int tail;
  80         int space;
  81         drm_local_map_t map;
  82         struct drm_gem_object *ring_obj;
  83 } drm_i915_ring_buffer_t;
  84
  85 struct mem_block {
  86         struct mem_block *next;
  87         struct mem_block *prev;
  88         int start;
  89         int size;
  90         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  91 };
  92
  93 struct opregion_header;
  94 struct opregion_acpi;
  95 struct opregion_swsci;
  96 struct opregion_asle;
  97
  98 struct intel_opregion {
  99         struct opregion_header *header;
 100         struct opregion_acpi *acpi;
 101         struct opregion_swsci *swsci;
 102         struct opregion_asle *asle;
 103         int enabled;
 104 };
 105
 106 typedef struct drm_i915_private {
 107         struct drm_device *dev;
 108
 109         void __iomem *regs;
 110         drm_local_map_t *sarea;
 111
 112         drm_i915_sarea_t *sarea_priv;
 113         drm_i915_ring_buffer_t ring;
 114
 115         drm_dma_handle_t *status_page_dmah;
 116         void *hw_status_page;
 117         dma_addr_t dma_status_page;
 118         uint32_t counter;
 119         unsigned int status_gfx_addr;
 120         drm_local_map_t hws_map;
 121         struct drm_gem_object *hws_obj;
 122
 123         unsigned int cpp;
 124         int back_offset;
 125         int front_offset;
 126         int current_page;
 127         int page_flipping;
 128
 129         wait_queue_head_t irq_queue;
 130         atomic_t irq_received;
 131         /** Protects user_irq_refcount and irq_mask_reg */
 132         spinlock_t user_irq_lock;
 133         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 134         int user_irq_refcount;
 135         /** Cached value of IMR to avoid reads in updating the bitfield */
 136         u32 irq_mask_reg;
 137         u32 pipestat[2];
 138
 139         int tex_lru_log_granularity;
 140         int allow_batchbuffer;
 141         struct mem_block *agp_heap;
 142         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 143         int vblank_pipe;
 144
 145         struct intel_opregion opregion;
 146
 147         /* Register state */
 148         u8 saveLBB;
 149         u32 saveDSPACNTR;
 150         u32 saveDSPBCNTR;
 151         u32 saveDSPARB;
 152         u32 saveRENDERSTANDBY;
 153         u32 saveHWS;
 154         u32 savePIPEACONF;
 155         u32 savePIPEBCONF;
 156         u32 savePIPEASRC;
 157         u32 savePIPEBSRC;
 158         u32 saveFPA0;
 159         u32 saveFPA1;
 160         u32 saveDPLL_A;
 161         u32 saveDPLL_A_MD;
 162         u32 saveHTOTAL_A;
 163         u32 saveHBLANK_A;
 164         u32 saveHSYNC_A;
 165         u32 saveVTOTAL_A;
 166         u32 saveVBLANK_A;
 167         u32 saveVSYNC_A;
 168         u32 saveBCLRPAT_A;
 169         u32 savePIPEASTAT;
 170         u32 saveDSPASTRIDE;
 171         u32 saveDSPASIZE;
 172         u32 saveDSPAPOS;
 173         u32 saveDSPAADDR;
 174         u32 saveDSPASURF;
 175         u32 saveDSPATILEOFF;
 176         u32 savePFIT_PGM_RATIOS;
 177         u32 saveBLC_PWM_CTL;
 178         u32 saveBLC_PWM_CTL2;
 179         u32 saveFPB0;
 180         u32 saveFPB1;
 181         u32 saveDPLL_B;
 182         u32 saveDPLL_B_MD;
 183         u32 saveHTOTAL_B;
 184         u32 saveHBLANK_B;
 185         u32 saveHSYNC_B;
 186         u32 saveVTOTAL_B;
 187         u32 saveVBLANK_B;
 188         u32 saveVSYNC_B;
 189         u32 saveBCLRPAT_B;
 190         u32 savePIPEBSTAT;
 191         u32 saveDSPBSTRIDE;
 192         u32 saveDSPBSIZE;
 193         u32 saveDSPBPOS;
 194         u32 saveDSPBADDR;
 195         u32 saveDSPBSURF;
 196         u32 saveDSPBTILEOFF;
 197         u32 saveVGA0;
 198         u32 saveVGA1;
 199         u32 saveVGA_PD;
 200         u32 saveVGACNTRL;
 201         u32 saveADPA;
 202         u32 saveLVDS;
 203         u32 savePP_ON_DELAYS;
 204         u32 savePP_OFF_DELAYS;
 205         u32 saveDVOA;
 206         u32 saveDVOB;
 207         u32 saveDVOC;
 208         u32 savePP_ON;
 209         u32 savePP_OFF;
 210         u32 savePP_CONTROL;
 211         u32 savePP_DIVISOR;
 212         u32 savePFIT_CONTROL;
 213         u32 save_palette_a[256];
 214         u32 save_palette_b[256];
 215         u32 saveFBC_CFB_BASE;
 216         u32 saveFBC_LL_BASE;
 217         u32 saveFBC_CONTROL;
 218         u32 saveFBC_CONTROL2;
 219         u32 saveIER;
 220         u32 saveIIR;
 221         u32 saveIMR;
 222         u32 saveCACHE_MODE_0;
 223         u32 saveD_STATE;
 224         u32 saveCG_2D_DIS;
 225         u32 saveMI_ARB_STATE;
 226         u32 saveSWF0[16];
 227         u32 saveSWF1[16];
 228         u32 saveSWF2[3];
 229         u8 saveMSR;
 230         u8 saveSR[8];
 231         u8 saveGR[25];
 232         u8 saveAR_INDEX;
 233         u8 saveAR[21];
 234         u8 saveDACMASK;
 235         u8 saveDACDATA[256*3]; /* 256 3-byte colors */
 236         u8 saveCR[37];
 237
 238         struct {
 239                 struct drm_mm gtt_space;
 240
 241                 struct io_mapping *gtt_mapping;
 242
 243                 /**
 244                  * List of objects currently involved in rendering from the
 245                  * ringbuffer.
 246                  *
 247                  * Includes buffers having the contents of their GPU caches
 248                  * flushed, not necessarily primitives.  last_rendering_seqno
 249                  * represents when the rendering involved will be completed.
 250                  *
 251                  * A reference is held on the buffer while on this list.
 252                  */
 253                 struct list_head active_list;
 254
 255                 /**
 256                  * List of objects which are not in the ringbuffer but which
 257                  * still have a write_domain which needs to be flushed before
 258                  * unbinding.
 259                  *
 260                  * last_rendering_seqno is 0 while an object is in this list.
 261                  *
 262                  * A reference is held on the buffer while on this list.
 263                  */
 264                 struct list_head flushing_list;
 265
 266                 /**
 267                  * LRU list of objects which are not in the ringbuffer and
 268                  * are ready to unbind, but are still in the GTT.
 269                  *
 270                  * last_rendering_seqno is 0 while an object is in this list.
 271                  *
 272                  * A reference is not held on the buffer while on this list,
 273                  * as merely being GTT-bound shouldn't prevent its being
 274                  * freed, and we'll pull it off the list in the free path.
 275                  */
 276                 struct list_head inactive_list;
 277
 278                 /**
 279                  * List of breadcrumbs associated with GPU requests currently
 280                  * outstanding.
 281                  */
 282                 struct list_head request_list;
 283
 284                 /**
 285                  * We leave the user IRQ off as much as possible,
 286                  * but this means that requests will finish and never
 287                  * be retired once the system goes idle. Set a timer to
 288                  * fire periodically while the ring is running. When it
 289                  * fires, go retire requests.
 290                  */
 291                 struct delayed_work retire_work;
 292
 293                 uint32_t next_gem_seqno;
 294
 295                 /**
 296                  * Waiting sequence number, if any
 297                  */
 298                 uint32_t waiting_gem_seqno;
 299
 300                 /**
 301                  * Last seq seen at irq time
 302                  */
 303                 uint32_t irq_gem_seqno;
 304
 305                 /**
 306                  * Flag if the X Server, and thus DRM, is not currently in
 307                  * control of the device.
 308                  *
 309                  * This is set between LeaveVT and EnterVT.  It needs to be
 310                  * replaced with a semaphore.  It also needs to be
 311                  * transitioned away from for kernel modesetting.
 312                  */
 313                 int suspended;
 314
 315                 /**
 316                  * Flag if the hardware appears to be wedged.
 317                  *
 318                  * This is set when attempts to idle the device timeout.
 319                  * It prevents command submission from occuring and makes
 320                  * every pending request fail
 321                  */
 322                 int wedged;
 323
 324                 /** Bit 6 swizzling required for X tiling */
 325                 uint32_t bit_6_swizzle_x;
 326                 /** Bit 6 swizzling required for Y tiling */
 327                 uint32_t bit_6_swizzle_y;
 328         } mm;
 329 } drm_i915_private_t;
 330
 331 /** driver private structure attached to each drm_gem_object */
 332 struct drm_i915_gem_object {
 333         struct drm_gem_object *obj;
 334
 335         /** Current space allocated to this object in the GTT, if any. */
 336         struct drm_mm_node *gtt_space;
 337
 338         /** This object's place on the active/flushing/inactive lists */
 339         struct list_head list;
 340
 341         /**
 342          * This is set if the object is on the active or flushing lists
 343          * (has pending rendering), and is not set if it's on inactive (ready
 344          * to be unbound).
 345          */
 346         int active;
 347
 348         /**
 349          * This is set if the object has been written to since last bound
 350          * to the GTT
 351          */
 352         int dirty;
 353
 354         /** AGP memory structure for our GTT binding. */
 355         DRM_AGP_MEM *agp_mem;
 356
 357         struct page **page_list;
 358
 359         /**
 360          * Current offset of the object in GTT space.
 361          *
 362          * This is the same as gtt_space->start
 363          */
 364         uint32_t gtt_offset;
 365
 366         /** Boolean whether this object has a valid gtt offset. */
 367         int gtt_bound;
 368
 369         /** How many users have pinned this object in GTT space */
 370         int pin_count;
 371
 372         /** Breadcrumb of last rendering to the buffer. */
 373         uint32_t last_rendering_seqno;
 374
 375         /** Current tiling mode for the object. */
 376         uint32_t tiling_mode;
 377
 378         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 379         uint32_t agp_type;
 380
 381         /**
 382          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 383          * flags which individual pages are valid.
 384          */
 385         uint8_t *page_cpu_valid;
 386 };
 387
 388 /**
 389  * Request queue structure.
 390  *
 391  * The request queue allows us to note sequence numbers that have been emitted
 392  * and may be associated with active buffers to be retired.
 393  *
 394  * By keeping this list, we can avoid having to do questionable
 395  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 396  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 397  */
 398 struct drm_i915_gem_request {
 399         /** GEM sequence number associated with this request. */
 400         uint32_t seqno;
 401
 402         /** Time at which this request was emitted, in jiffies. */
 403         unsigned long emitted_jiffies;
 404
 405         struct list_head list;
 406 };
 407
 408 struct drm_i915_file_private {
 409         struct {
 410                 uint32_t last_gem_seqno;
 411                 uint32_t last_gem_throttle_seqno;
 412         } mm;
 413 };
 414
 415 extern struct drm_ioctl_desc i915_ioctls[];
 416 extern int i915_max_ioctl;
 417
 418                                 /* i915_dma.c */
 419 extern void i915_kernel_lost_context(struct drm_device * dev);
 420 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 421 extern int i915_driver_unload(struct drm_device *);
 422 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 423 extern void i915_driver_lastclose(struct drm_device * dev);
 424 extern void i915_driver_preclose(struct drm_device *dev,
 425                                  struct drm_file *file_priv);
 426 extern void i915_driver_postclose(struct drm_device *dev,
 427                                   struct drm_file *file_priv);
 428 extern int i915_driver_device_is_agp(struct drm_device * dev);
 429 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 430                               unsigned long arg);
 431 extern int i915_emit_box(struct drm_device *dev,
 432                          struct drm_clip_rect __user *boxes,
 433                          int i, int DR1, int DR4);
 434
 435 /* i915_irq.c */
 436 extern int i915_irq_emit(struct drm_device *dev, void *data,
 437                          struct drm_file *file_priv);
 438 extern int i915_irq_wait(struct drm_device *dev, void *data,
 439                          struct drm_file *file_priv);
 440 void i915_user_irq_get(struct drm_device *dev);
 441 void i915_user_irq_put(struct drm_device *dev);
 442
 443 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 444 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 445 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 446 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 447 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 448                                 struct drm_file *file_priv);
 449 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 450                                 struct drm_file *file_priv);
 451 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 452 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 453 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 454 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 455                             struct drm_file *file_priv);
 456 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 457
 458 void
 459 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 460
 461 void
 462 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 463
 464
 465 /* i915_mem.c */
 466 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 467                           struct drm_file *file_priv);
 468 extern int i915_mem_free(struct drm_device *dev, void *data,
 469                          struct drm_file *file_priv);
 470 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 471                               struct drm_file *file_priv);
 472 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 473                                  struct drm_file *file_priv);
 474 extern void i915_mem_takedown(struct mem_block **heap);
 475 extern void i915_mem_release(struct drm_device * dev,
 476                              struct drm_file *file_priv, struct mem_block *heap);
 477 /* i915_gem.c */
 478 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 479                         struct drm_file *file_priv);
 480 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 481                           struct drm_file *file_priv);
 482 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 483                          struct drm_file *file_priv);
 484 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 485                           struct drm_file *file_priv);
 486 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 487                         struct drm_file *file_priv);
 488 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 489                               struct drm_file *file_priv);
 490 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 491                              struct drm_file *file_priv);
 492 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 493                         struct drm_file *file_priv);
 494 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 495                        struct drm_file *file_priv);
 496 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 497                          struct drm_file *file_priv);
 498 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 499                         struct drm_file *file_priv);
 500 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 501                             struct drm_file *file_priv);
 502 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 503                            struct drm_file *file_priv);
 504 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 505                            struct drm_file *file_priv);
 506 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 507                         struct drm_file *file_priv);
 508 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 509                         struct drm_file *file_priv);
 510 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 511                                 struct drm_file *file_priv);
 512 void i915_gem_load(struct drm_device *dev);
 513 int i915_gem_proc_init(struct drm_minor *minor);
 514 void i915_gem_proc_cleanup(struct drm_minor *minor);
 515 int i915_gem_init_object(struct drm_gem_object *obj);
 516 void i915_gem_free_object(struct drm_gem_object *obj);
 517 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 518 void i915_gem_object_unpin(struct drm_gem_object *obj);
 519 void i915_gem_lastclose(struct drm_device *dev);
 520 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 521 void i915_gem_retire_requests(struct drm_device *dev);
 522 void i915_gem_retire_work_handler(struct work_struct *work);
 523 void i915_gem_clflush_object(struct drm_gem_object *obj);
 524
 525 /* i915_gem_tiling.c */
 526 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 527
 528 /* i915_gem_debug.c */
 529 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 530                           const char *where, uint32_t mark);
 531 #if WATCH_INACTIVE
 532 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 533 #else
 534 #define i915_verify_inactive(dev, file, line)
 535 #endif
 536 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 537 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 538                           const char *where, uint32_t mark);
 539 void i915_dump_lru(struct drm_device *dev, const char *where);
 540
 541 /* i915_suspend.c */
 542 extern int i915_save_state(struct drm_device *dev);
 543 extern int i915_restore_state(struct drm_device *dev);
 544
 545 /* i915_suspend.c */
 546 extern int i915_save_state(struct drm_device *dev);
 547 extern int i915_restore_state(struct drm_device *dev);
 548
 549 #ifdef CONFIG_ACPI
 550 /* i915_opregion.c */
 551 extern int intel_opregion_init(struct drm_device *dev);
 552 extern void intel_opregion_free(struct drm_device *dev);
 553 extern void opregion_asle_intr(struct drm_device *dev);
 554 extern void opregion_enable_asle(struct drm_device *dev);
 555 #else
 556 static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
 557 static inline void intel_opregion_free(struct drm_device *dev) { return; }
 558 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 559 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 560 #endif
 561
 562 /**
 563  * Lock test for when it's just for synchronization of ring access.
 564  *
 565  * In that case, we don't need to do it when GEM is initialized as nobody else
 566  * has access to the ring.
 567  */
 568 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 569         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 570                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 571 } while (0)
 572
 573 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 574 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 575 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 576 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 577 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 578 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 579
 580 #define I915_VERBOSE 0
 581
 582 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 583                         volatile char *virt;
 584
 585 #define BEGIN_LP_RING(n) do {                           \
 586         if (I915_VERBOSE)                               \
 587                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));  \
 588         if (dev_priv->ring.space < (n)*4)               \
 589                 i915_wait_ring(dev, (n)*4, __func__);           \
 590         outcount = 0;                                   \
 591         outring = dev_priv->ring.tail;                  \
 592         ringmask = dev_priv->ring.tail_mask;            \
 593         virt = dev_priv->ring.virtual_start;            \
 594 } while (0)
 595
 596 #define OUT_RING(n) do {                                        \
 597         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 598         *(volatile unsigned int *)(virt + outring) = (n);       \
 599         outcount++;                                             \
 600         outring += 4;                                           \
 601         outring &= ringmask;                                    \
 602 } while (0)
 603
 604 #define ADVANCE_LP_RING() do {                                          \
 605         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 606         dev_priv->ring.tail = outring;                                  \
 607         dev_priv->ring.space -= outcount * 4;                           \
 608         I915_WRITE(PRB0_TAIL, outring);                 \
 609 } while(0)
 610
 611 /**
 612  * Reads a dword out of the status page, which is written to from the command
 613  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 614  * MI_STORE_DATA_IMM.
 615  *
 616  * The following dwords have a reserved meaning:
 617  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 618  * 0x04: ring 0 head pointer
 619  * 0x05: ring 1 head pointer (915-class)
 620  * 0x06: ring 2 head pointer (915-class)
 621  * 0x10-0x1b: Context status DWords (GM45)
 622  * 0x1f: Last written status offset. (GM45)
 623  *
 624  * The area from dword 0x20 to 0x3ff is available for driver usage.
 625  */
 626 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 627 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 628 #define I915_GEM_HWS_INDEX              0x20
 629 #define I915_BREADCRUMB_INDEX           0x21
 630
 631 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 632
 633 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 634 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 635 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 636 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 637 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 638
 639 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 640 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 641 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 642 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 643                         (dev)->pci_device == 0x27AE)
 644 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 645                        (dev)->pci_device == 0x2982 || \
 646                        (dev)->pci_device == 0x2992 || \
 647                        (dev)->pci_device == 0x29A2 || \
 648                        (dev)->pci_device == 0x2A02 || \
 649                        (dev)->pci_device == 0x2A12 || \
 650                        (dev)->pci_device == 0x2A42 || \
 651                        (dev)->pci_device == 0x2E02 || \
 652                        (dev)->pci_device == 0x2E12 || \
 653                        (dev)->pci_device == 0x2E22)
 654
 655 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 656
 657 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
 658
 659 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 660                      (dev)->pci_device == 0x2E12 || \
 661                      (dev)->pci_device == 0x2E22)
 662
 663 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 664                         (dev)->pci_device == 0x29B2 ||  \
 665                         (dev)->pci_device == 0x29D2)
 666
 667 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 668                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
 669
 670 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 671                         IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
 672
 673 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
 674
 675 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 676
 677 #endif