1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
44 /* General customization:
47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
49 #define DRIVER_NAME "i915"
50 #define DRIVER_DESC "Intel Graphics"
51 #define DRIVER_DATE "20080730"
59 #define pipe_name(p) ((p) + 'A')
66 #define plane_name(p) ((p) + 'A')
76 #define port_name(p) ((p) + 'A')
78 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
80 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
82 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
83 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
84 if ((intel_encoder)->base.crtc == (__crtc))
86 struct intel_pch_pll
{
87 int refcount
; /* count of number of CRTCs sharing this PLL */
88 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
89 bool on
; /* is the PLL actually active? Disabled during modeset */
94 #define I915_NUM_PLLS 2
99 * 1.2: Add Power Management
100 * 1.3: Add vblank support
101 * 1.4: Fix cmdbuffer path, add heap destroy
102 * 1.5: Add vblank pipe configuration
103 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
104 * - Support vertical blank on secondary display pipe
106 #define DRIVER_MAJOR 1
107 #define DRIVER_MINOR 6
108 #define DRIVER_PATCHLEVEL 0
110 #define WATCH_COHERENCY 0
111 #define WATCH_LISTS 0
114 #define I915_GEM_PHYS_CURSOR_0 1
115 #define I915_GEM_PHYS_CURSOR_1 2
116 #define I915_GEM_PHYS_OVERLAY_REGS 3
117 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
119 struct drm_i915_gem_phys_object
{
121 struct page
**page_list
;
122 drm_dma_handle_t
*handle
;
123 struct drm_i915_gem_object
*cur_obj
;
127 struct mem_block
*next
;
128 struct mem_block
*prev
;
131 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
134 struct opregion_header
;
135 struct opregion_acpi
;
136 struct opregion_swsci
;
137 struct opregion_asle
;
138 struct drm_i915_private
;
140 struct intel_opregion
{
141 struct opregion_header __iomem
*header
;
142 struct opregion_acpi __iomem
*acpi
;
143 struct opregion_swsci __iomem
*swsci
;
144 struct opregion_asle __iomem
*asle
;
146 u32 __iomem
*lid_state
;
148 #define OPREGION_SIZE (8*1024)
150 struct intel_overlay
;
151 struct intel_overlay_error_state
;
153 struct drm_i915_master_private
{
154 drm_local_map_t
*sarea
;
155 struct _drm_i915_sarea
*sarea_priv
;
157 #define I915_FENCE_REG_NONE -1
158 #define I915_MAX_NUM_FENCES 16
159 /* 16 fences + sign bit for FENCE_REG_NONE */
160 #define I915_MAX_NUM_FENCE_BITS 5
162 struct drm_i915_fence_reg
{
163 struct list_head lru_list
;
164 struct drm_i915_gem_object
*obj
;
168 struct sdvo_device_mapping
{
177 struct intel_display_error_state
;
179 struct drm_i915_error_state
{
185 bool waiting
[I915_NUM_RINGS
];
186 u32 pipestat
[I915_MAX_PIPES
];
187 u32 tail
[I915_NUM_RINGS
];
188 u32 head
[I915_NUM_RINGS
];
189 u32 ipeir
[I915_NUM_RINGS
];
190 u32 ipehr
[I915_NUM_RINGS
];
191 u32 instdone
[I915_NUM_RINGS
];
192 u32 acthd
[I915_NUM_RINGS
];
193 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
194 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
195 /* our own tracking of ring head and tail */
196 u32 cpu_ring_head
[I915_NUM_RINGS
];
197 u32 cpu_ring_tail
[I915_NUM_RINGS
];
198 u32 error
; /* gen6+ */
199 u32 instpm
[I915_NUM_RINGS
];
200 u32 instps
[I915_NUM_RINGS
];
202 u32 seqno
[I915_NUM_RINGS
];
204 u32 fault_reg
[I915_NUM_RINGS
];
206 u32 faddr
[I915_NUM_RINGS
];
207 u64 fence
[I915_MAX_NUM_FENCES
];
209 struct drm_i915_error_ring
{
210 struct drm_i915_error_object
{
214 } *ringbuffer
, *batchbuffer
;
215 struct drm_i915_error_request
{
221 } ring
[I915_NUM_RINGS
];
222 struct drm_i915_error_buffer
{
229 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
236 } *active_bo
, *pinned_bo
;
237 u32 active_bo_count
, pinned_bo_count
;
238 struct intel_overlay_error_state
*overlay
;
239 struct intel_display_error_state
*display
;
242 struct drm_i915_display_funcs
{
243 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
244 bool (*fbc_enabled
)(struct drm_device
*dev
);
245 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
246 void (*disable_fbc
)(struct drm_device
*dev
);
247 int (*get_display_clock_speed
)(struct drm_device
*dev
);
248 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
249 void (*update_wm
)(struct drm_device
*dev
);
250 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
251 uint32_t sprite_width
, int pixel_size
);
252 void (*update_linetime_wm
)(struct drm_device
*dev
, int pipe
,
253 struct drm_display_mode
*mode
);
254 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
255 struct drm_display_mode
*mode
,
256 struct drm_display_mode
*adjusted_mode
,
258 struct drm_framebuffer
*old_fb
);
259 void (*off
)(struct drm_crtc
*crtc
);
260 void (*write_eld
)(struct drm_connector
*connector
,
261 struct drm_crtc
*crtc
);
262 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
263 void (*init_clock_gating
)(struct drm_device
*dev
);
264 void (*init_pch_clock_gating
)(struct drm_device
*dev
);
265 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
266 struct drm_framebuffer
*fb
,
267 struct drm_i915_gem_object
*obj
);
268 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
270 /* clock updates for mode set */
272 /* render clock increase/decrease */
273 /* display clock increase/decrease */
274 /* pll clock increase/decrease */
277 struct drm_i915_gt_funcs
{
278 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
279 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
282 #define DEV_INFO_FLAGS \
283 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
284 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
285 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
286 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
287 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
288 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
289 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
290 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
291 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
292 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
293 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
294 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
295 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
296 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
297 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
298 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
299 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
300 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
301 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
302 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
303 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
304 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
305 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
306 DEV_INFO_FLAG(has_llc)
308 struct intel_device_info
{
327 u8 cursor_needs_physical
:1;
329 u8 overlay_needs_physical
:1;
336 #define I915_PPGTT_PD_ENTRIES 512
337 #define I915_PPGTT_PT_ENTRIES 1024
338 struct i915_hw_ppgtt
{
339 unsigned num_pd_entries
;
340 struct page
**pt_pages
;
342 dma_addr_t
*pt_dma_addr
;
343 dma_addr_t scratch_page_dma_addr
;
347 /* This must match up with the value previously used for execbuf2.rsvd1. */
348 #define DEFAULT_CONTEXT_ID 0
349 struct i915_hw_context
{
352 struct drm_i915_file_private
*file_priv
;
353 struct intel_ring_buffer
*ring
;
354 struct drm_i915_gem_object
*obj
;
358 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
359 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
360 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
361 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
362 FBC_BAD_PLANE
, /* fbc not supported on plane */
363 FBC_NOT_TILED
, /* buffer not tiled */
364 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
369 PCH_NONE
= 0, /* No PCH present */
370 PCH_IBX
, /* Ibexpeak PCH */
371 PCH_CPT
, /* Cougarpoint PCH */
372 PCH_LPT
, /* Lynxpoint PCH */
375 #define QUIRK_PIPEA_FORCE (1<<0)
376 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
377 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
380 struct intel_fbc_work
;
383 struct i2c_adapter adapter
;
387 struct i2c_algo_bit_data bit_algo
;
388 struct drm_i915_private
*dev_priv
;
391 typedef struct drm_i915_private
{
392 struct drm_device
*dev
;
394 const struct intel_device_info
*info
;
396 int relative_constants_mode
;
400 struct drm_i915_gt_funcs gt
;
401 /** gt_fifo_count and the subsequent register write are synchronized
402 * with dev->struct_mutex. */
403 unsigned gt_fifo_count
;
404 /** forcewake_count is protected by gt_lock */
405 unsigned forcewake_count
;
406 /** gt_lock is also taken in irq contexts. */
407 struct spinlock gt_lock
;
409 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
411 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
412 * controller on different i2c buses. */
413 struct mutex gmbus_mutex
;
416 * Base address of the gmbus and gpio block.
418 uint32_t gpio_mmio_base
;
420 struct pci_dev
*bridge_dev
;
421 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
424 drm_dma_handle_t
*status_page_dmah
;
426 struct drm_i915_gem_object
*pwrctx
;
427 struct drm_i915_gem_object
*renderctx
;
429 struct resource mch_res
;
431 atomic_t irq_received
;
433 /* protects the irq masks */
436 /* DPIO indirect register protection */
437 spinlock_t dpio_lock
;
439 /** Cached value of IMR to avoid reads in updating the bitfield */
445 u32 hotplug_supported_mask
;
446 struct work_struct hotplug_work
;
451 /* For hangcheck timer */
452 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
453 struct timer_list hangcheck_timer
;
455 uint32_t last_acthd
[I915_NUM_RINGS
];
456 uint32_t last_instdone
;
457 uint32_t last_instdone1
;
459 unsigned int stop_rings
;
461 unsigned long cfb_size
;
463 enum plane cfb_plane
;
465 struct intel_fbc_work
*fbc_work
;
467 struct intel_opregion opregion
;
470 struct intel_overlay
*overlay
;
471 bool sprite_scaling_enabled
;
474 int backlight_level
; /* restore backlight to this value */
475 bool backlight_enabled
;
476 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
477 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
479 /* Feature bits from the VBIOS */
480 unsigned int int_tv_support
:1;
481 unsigned int lvds_dither
:1;
482 unsigned int lvds_vbt
:1;
483 unsigned int int_crt_support
:1;
484 unsigned int lvds_use_ssc
:1;
485 unsigned int display_clock_mode
:1;
487 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
488 unsigned int lvds_val
; /* used for checking LVDS channel mode */
498 struct edp_power_seq pps
;
500 bool no_aux_handshake
;
502 struct notifier_block lid_notifier
;
505 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
506 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
507 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
509 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
511 spinlock_t error_lock
;
512 /* Protected by dev->error_lock. */
513 struct drm_i915_error_state
*first_error
;
514 struct work_struct error_work
;
515 struct completion error_completion
;
516 struct workqueue_struct
*wq
;
518 /* Display functions */
519 struct drm_i915_display_funcs display
;
521 /* PCH chipset type */
522 enum intel_pch pch_type
;
524 unsigned long quirks
;
549 u32 saveTRANS_HTOTAL_A
;
550 u32 saveTRANS_HBLANK_A
;
551 u32 saveTRANS_HSYNC_A
;
552 u32 saveTRANS_VTOTAL_A
;
553 u32 saveTRANS_VBLANK_A
;
554 u32 saveTRANS_VSYNC_A
;
562 u32 savePFIT_PGM_RATIOS
;
563 u32 saveBLC_HIST_CTL
;
565 u32 saveBLC_PWM_CTL2
;
566 u32 saveBLC_CPU_PWM_CTL
;
567 u32 saveBLC_CPU_PWM_CTL2
;
580 u32 saveTRANS_HTOTAL_B
;
581 u32 saveTRANS_HBLANK_B
;
582 u32 saveTRANS_HSYNC_B
;
583 u32 saveTRANS_VTOTAL_B
;
584 u32 saveTRANS_VBLANK_B
;
585 u32 saveTRANS_VSYNC_B
;
599 u32 savePP_ON_DELAYS
;
600 u32 savePP_OFF_DELAYS
;
608 u32 savePFIT_CONTROL
;
609 u32 save_palette_a
[256];
610 u32 save_palette_b
[256];
611 u32 saveDPFC_CB_BASE
;
612 u32 saveFBC_CFB_BASE
;
615 u32 saveFBC_CONTROL2
;
625 u32 saveCACHE_MODE_0
;
626 u32 saveMI_ARB_STATE
;
637 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
648 u32 savePIPEA_GMCH_DATA_M
;
649 u32 savePIPEB_GMCH_DATA_M
;
650 u32 savePIPEA_GMCH_DATA_N
;
651 u32 savePIPEB_GMCH_DATA_N
;
652 u32 savePIPEA_DP_LINK_M
;
653 u32 savePIPEB_DP_LINK_M
;
654 u32 savePIPEA_DP_LINK_N
;
655 u32 savePIPEB_DP_LINK_N
;
666 u32 savePCH_DREF_CONTROL
;
667 u32 saveDISP_ARB_CTL
;
668 u32 savePIPEA_DATA_M1
;
669 u32 savePIPEA_DATA_N1
;
670 u32 savePIPEA_LINK_M1
;
671 u32 savePIPEA_LINK_N1
;
672 u32 savePIPEB_DATA_M1
;
673 u32 savePIPEB_DATA_N1
;
674 u32 savePIPEB_LINK_M1
;
675 u32 savePIPEB_LINK_N1
;
676 u32 saveMCHBAR_RENDER_STANDBY
;
677 u32 savePCH_PORT_HOTPLUG
;
680 /** Bridge to intel-gtt-ko */
681 const struct intel_gtt
*gtt
;
682 /** Memory allocator for GTT stolen memory */
683 struct drm_mm stolen
;
684 /** Memory allocator for GTT */
685 struct drm_mm gtt_space
;
686 /** List of all objects in gtt_space. Used to restore gtt
687 * mappings on resume */
688 struct list_head bound_list
;
690 * List of objects which are not bound to the GTT (thus
691 * are idle and not used by the GPU) but still have
692 * (presumably uncached) pages still attached.
694 struct list_head unbound_list
;
696 /** Usable portion of the GTT for GEM */
697 unsigned long gtt_start
;
698 unsigned long gtt_mappable_end
;
699 unsigned long gtt_end
;
701 struct io_mapping
*gtt_mapping
;
702 phys_addr_t gtt_base_addr
;
705 /** PPGTT used for aliasing the PPGTT with the GTT */
706 struct i915_hw_ppgtt
*aliasing_ppgtt
;
710 struct shrinker inactive_shrinker
;
713 * List of objects currently involved in rendering.
715 * Includes buffers having the contents of their GPU caches
716 * flushed, not necessarily primitives. last_rendering_seqno
717 * represents when the rendering involved will be completed.
719 * A reference is held on the buffer while on this list.
721 struct list_head active_list
;
724 * LRU list of objects which are not in the ringbuffer and
725 * are ready to unbind, but are still in the GTT.
727 * last_rendering_seqno is 0 while an object is in this list.
729 * A reference is not held on the buffer while on this list,
730 * as merely being GTT-bound shouldn't prevent its being
731 * freed, and we'll pull it off the list in the free path.
733 struct list_head inactive_list
;
735 /** LRU list of objects with fence regs on them. */
736 struct list_head fence_list
;
739 * We leave the user IRQ off as much as possible,
740 * but this means that requests will finish and never
741 * be retired once the system goes idle. Set a timer to
742 * fire periodically while the ring is running. When it
743 * fires, go retire requests.
745 struct delayed_work retire_work
;
748 * Are we in a non-interruptible section of code like
754 * Flag if the X Server, and thus DRM, is not currently in
755 * control of the device.
757 * This is set between LeaveVT and EnterVT. It needs to be
758 * replaced with a semaphore. It also needs to be
759 * transitioned away from for kernel modesetting.
764 * Flag if the hardware appears to be wedged.
766 * This is set when attempts to idle the device timeout.
767 * It prevents command submission from occurring and makes
768 * every pending request fail
772 /** Bit 6 swizzling required for X tiling */
773 uint32_t bit_6_swizzle_x
;
774 /** Bit 6 swizzling required for Y tiling */
775 uint32_t bit_6_swizzle_y
;
777 /* storage for physical objects */
778 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
780 /* accounting, useful for userland debugging */
782 size_t mappable_gtt_total
;
783 size_t object_memory
;
787 /* Old dri1 support infrastructure, beware the dragons ya fools entering
790 unsigned allow_batchbuffer
: 1;
791 u32 __iomem
*gfx_hws_cpu_addr
;
800 /* Kernel Modesetting */
802 struct sdvo_device_mapping sdvo_mappings
[2];
803 /* indicate whether the LVDS_BORDER should be enabled or not */
804 unsigned int lvds_border_bits
;
805 /* Panel fitter placement and size for Ironlake+ */
806 u32 pch_pf_pos
, pch_pf_size
;
808 struct drm_crtc
*plane_to_crtc_mapping
[3];
809 struct drm_crtc
*pipe_to_crtc_mapping
[3];
810 wait_queue_head_t pending_flip_queue
;
812 struct intel_pch_pll pch_plls
[I915_NUM_PLLS
];
814 /* Reclocking support */
815 bool render_reclock_avail
;
816 bool lvds_downclock_avail
;
817 /* indicates the reduced downclock for LVDS*/
821 struct child_device_config
*child_dev
;
822 struct drm_connector
*int_lvds_connector
;
823 struct drm_connector
*int_edp_connector
;
825 bool mchbar_need_disable
;
827 /* gen6+ rps state */
829 struct work_struct work
;
831 /* lock - irqsave spinlock that protectects the work_struct and
835 /* The below variables an all the rps hw state are protected by
836 * dev->struct mutext. */
850 unsigned long last_time1
;
851 unsigned long chipset_power
;
853 struct timespec last_time2
;
854 unsigned long gfx_power
;
859 enum no_fbc_reason no_fbc_reason
;
861 struct drm_mm_node
*compressed_fb
;
862 struct drm_mm_node
*compressed_llb
;
864 unsigned long last_gpu_reset
;
866 /* list of fbdev register on this device */
867 struct intel_fbdev
*fbdev
;
869 struct backlight_device
*backlight
;
871 struct drm_property
*broadcast_rgb_property
;
872 struct drm_property
*force_audio_property
;
874 struct work_struct parity_error_work
;
875 bool hw_contexts_disabled
;
876 uint32_t hw_context_size
;
877 } drm_i915_private_t
;
879 /* Iterate over initialised rings */
880 #define for_each_ring(ring__, dev_priv__, i__) \
881 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
882 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
884 enum hdmi_force_audio
{
885 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
886 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
887 HDMI_AUDIO_AUTO
, /* trust EDID */
888 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
891 enum i915_cache_level
{
894 I915_CACHE_LLC_MLC
, /* gen6+, in docs at least! */
897 struct drm_i915_gem_object
{
898 struct drm_gem_object base
;
900 /** Current space allocated to this object in the GTT, if any. */
901 struct drm_mm_node
*gtt_space
;
902 struct list_head gtt_list
;
904 /** This object's place on the active/inactive lists */
905 struct list_head ring_list
;
906 struct list_head mm_list
;
907 /** This object's place in the batchbuffer or on the eviction list */
908 struct list_head exec_list
;
911 * This is set if the object is on the active lists (has pending
912 * rendering and so a non-zero seqno), and is not set if it i s on
913 * inactive (ready to be unbound) list.
915 unsigned int active
:1;
918 * This is set if the object has been written to since last bound
921 unsigned int dirty
:1;
924 * Fence register bits (if any) for this object. Will be set
925 * as needed when mapped into the GTT.
926 * Protected by dev->struct_mutex.
928 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
931 * Advice: are the backing pages purgeable?
936 * Current tiling mode for the object.
938 unsigned int tiling_mode
:2;
940 * Whether the tiling parameters for the currently associated fence
941 * register have changed. Note that for the purposes of tracking
942 * tiling changes we also treat the unfenced register, the register
943 * slot that the object occupies whilst it executes a fenced
944 * command (such as BLT on gen2/3), as a "fence".
946 unsigned int fence_dirty
:1;
948 /** How many users have pinned this object in GTT space. The following
949 * users can each hold at most one reference: pwrite/pread, pin_ioctl
950 * (via user_pin_count), execbuffer (objects are not allowed multiple
951 * times for the same batchbuffer), and the framebuffer code. When
952 * switching/pageflipping, the framebuffer code has at most two buffers
955 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
956 * bits with absolutely no headroom. So use 4 bits. */
957 unsigned int pin_count
:4;
958 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
961 * Is the object at the current location in the gtt mappable and
962 * fenceable? Used to avoid costly recalculations.
964 unsigned int map_and_fenceable
:1;
967 * Whether the current gtt mapping needs to be mappable (and isn't just
968 * mappable by accident). Track pin and fault separate for a more
969 * accurate mappable working set.
971 unsigned int fault_mappable
:1;
972 unsigned int pin_mappable
:1;
975 * Is the GPU currently using a fence to access this buffer,
977 unsigned int pending_fenced_gpu_access
:1;
978 unsigned int fenced_gpu_access
:1;
980 unsigned int cache_level
:2;
982 unsigned int has_aliasing_ppgtt_mapping
:1;
983 unsigned int has_global_gtt_mapping
:1;
990 struct scatterlist
*sg_list
;
993 /* prime dma-buf support */
994 struct sg_table
*sg_table
;
995 void *dma_buf_vmapping
;
999 * Used for performing relocations during execbuffer insertion.
1001 struct hlist_node exec_node
;
1002 unsigned long exec_handle
;
1003 struct drm_i915_gem_exec_object2
*exec_entry
;
1006 * Current offset of the object in GTT space.
1008 * This is the same as gtt_space->start
1010 uint32_t gtt_offset
;
1012 struct intel_ring_buffer
*ring
;
1014 /** Breadcrumb of last rendering to the buffer. */
1015 uint32_t last_read_seqno
;
1016 uint32_t last_write_seqno
;
1017 /** Breadcrumb of last fenced GPU access to the buffer. */
1018 uint32_t last_fenced_seqno
;
1020 /** Current tiling stride for the object, if it's tiled. */
1023 /** Record of address bit 17 of each page at last unbind. */
1024 unsigned long *bit_17
;
1026 /** User space pin count and filp owning the pin */
1027 uint32_t user_pin_count
;
1028 struct drm_file
*pin_filp
;
1030 /** for phy allocated objects */
1031 struct drm_i915_gem_phys_object
*phys_obj
;
1034 * Number of crtcs where this object is currently the fb, but
1035 * will be page flipped away on the next vblank. When it
1036 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1038 atomic_t pending_flip
;
1041 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1044 * Request queue structure.
1046 * The request queue allows us to note sequence numbers that have been emitted
1047 * and may be associated with active buffers to be retired.
1049 * By keeping this list, we can avoid having to do questionable
1050 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1051 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1053 struct drm_i915_gem_request
{
1054 /** On Which ring this request was generated */
1055 struct intel_ring_buffer
*ring
;
1057 /** GEM sequence number associated with this request. */
1060 /** Postion in the ringbuffer of the end of the request */
1063 /** Time at which this request was emitted, in jiffies. */
1064 unsigned long emitted_jiffies
;
1066 /** global list entry for this request */
1067 struct list_head list
;
1069 struct drm_i915_file_private
*file_priv
;
1070 /** file_priv list entry for this request */
1071 struct list_head client_list
;
1074 struct drm_i915_file_private
{
1076 struct spinlock lock
;
1077 struct list_head request_list
;
1079 struct idr context_idr
;
1082 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1084 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1085 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1086 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1087 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1088 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1089 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1090 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1091 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1092 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1093 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1094 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1095 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1096 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1097 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1098 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1099 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1100 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1101 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1102 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1103 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1104 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1105 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1108 * The genX designation typically refers to the render engine, so render
1109 * capability related checks should use IS_GEN, while display and other checks
1110 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1113 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1114 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1115 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1116 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1117 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1118 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1120 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1121 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1122 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1123 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1125 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1126 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1128 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1129 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1131 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1132 * rows, which changed the alignment requirements and fence programming.
1134 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1136 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1137 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1138 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1139 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1140 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1141 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1142 /* dsparb controlled by hw only */
1143 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1145 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1146 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1147 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1149 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1151 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1152 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1153 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1154 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1155 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1157 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1159 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1161 #include "i915_trace.h"
1164 * RC6 is a special power stage which allows the GPU to enter an very
1165 * low-voltage mode when idle, using down to 0V while at this stage. This
1166 * stage is entered automatically when the GPU is idle when RC6 support is
1167 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1169 * There are different RC6 modes available in Intel GPU, which differentiate
1170 * among each other with the latency required to enter and leave RC6 and
1171 * voltage consumed by the GPU in different states.
1173 * The combination of the following flags define which states GPU is allowed
1174 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1175 * RC6pp is deepest RC6. Their support by hardware varies according to the
1176 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1177 * which brings the most power savings; deeper states save more power, but
1178 * require higher latency to switch to and wake up.
1180 #define INTEL_RC6_ENABLE (1<<0)
1181 #define INTEL_RC6p_ENABLE (1<<1)
1182 #define INTEL_RC6pp_ENABLE (1<<2)
1184 extern struct drm_ioctl_desc i915_ioctls
[];
1185 extern int i915_max_ioctl
;
1186 extern unsigned int i915_fbpercrtc __always_unused
;
1187 extern int i915_panel_ignore_lid __read_mostly
;
1188 extern unsigned int i915_powersave __read_mostly
;
1189 extern int i915_semaphores __read_mostly
;
1190 extern unsigned int i915_lvds_downclock __read_mostly
;
1191 extern int i915_lvds_channel_mode __read_mostly
;
1192 extern int i915_panel_use_ssc __read_mostly
;
1193 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1194 extern int i915_enable_rc6 __read_mostly
;
1195 extern int i915_enable_fbc __read_mostly
;
1196 extern bool i915_enable_hangcheck __read_mostly
;
1197 extern int i915_enable_ppgtt __read_mostly
;
1199 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1200 extern int i915_resume(struct drm_device
*dev
);
1201 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1202 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1205 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1206 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1207 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1208 extern int i915_driver_unload(struct drm_device
*);
1209 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1210 extern void i915_driver_lastclose(struct drm_device
* dev
);
1211 extern void i915_driver_preclose(struct drm_device
*dev
,
1212 struct drm_file
*file_priv
);
1213 extern void i915_driver_postclose(struct drm_device
*dev
,
1214 struct drm_file
*file_priv
);
1215 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1216 #ifdef CONFIG_COMPAT
1217 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1220 extern int i915_emit_box(struct drm_device
*dev
,
1221 struct drm_clip_rect
*box
,
1223 extern int intel_gpu_reset(struct drm_device
*dev
);
1224 extern int i915_reset(struct drm_device
*dev
);
1225 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1226 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1227 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1228 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1232 void i915_hangcheck_elapsed(unsigned long data
);
1233 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1235 extern void intel_irq_init(struct drm_device
*dev
);
1236 extern void intel_gt_init(struct drm_device
*dev
);
1238 void i915_error_state_free(struct kref
*error_ref
);
1241 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1244 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1246 void intel_enable_asle(struct drm_device
*dev
);
1248 #ifdef CONFIG_DEBUG_FS
1249 extern void i915_destroy_error_state(struct drm_device
*dev
);
1251 #define i915_destroy_error_state(x)
1256 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1257 struct drm_file
*file_priv
);
1258 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1259 struct drm_file
*file_priv
);
1260 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1261 struct drm_file
*file_priv
);
1262 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1263 struct drm_file
*file_priv
);
1264 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1265 struct drm_file
*file_priv
);
1266 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1267 struct drm_file
*file_priv
);
1268 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1269 struct drm_file
*file_priv
);
1270 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1271 struct drm_file
*file_priv
);
1272 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1273 struct drm_file
*file_priv
);
1274 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1275 struct drm_file
*file_priv
);
1276 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1277 struct drm_file
*file_priv
);
1278 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1279 struct drm_file
*file_priv
);
1280 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1281 struct drm_file
*file_priv
);
1282 int i915_gem_get_cacheing_ioctl(struct drm_device
*dev
, void *data
,
1283 struct drm_file
*file
);
1284 int i915_gem_set_cacheing_ioctl(struct drm_device
*dev
, void *data
,
1285 struct drm_file
*file
);
1286 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1287 struct drm_file
*file_priv
);
1288 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1289 struct drm_file
*file_priv
);
1290 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1291 struct drm_file
*file_priv
);
1292 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1293 struct drm_file
*file_priv
);
1294 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1295 struct drm_file
*file_priv
);
1296 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1297 struct drm_file
*file_priv
);
1298 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1299 struct drm_file
*file_priv
);
1300 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1301 struct drm_file
*file_priv
);
1302 void i915_gem_load(struct drm_device
*dev
);
1303 int i915_gem_init_object(struct drm_gem_object
*obj
);
1304 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1306 void i915_gem_free_object(struct drm_gem_object
*obj
);
1307 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1309 bool map_and_fenceable
);
1310 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1311 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1312 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1313 void i915_gem_lastclose(struct drm_device
*dev
);
1315 int __must_check
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
);
1316 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1317 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1318 struct intel_ring_buffer
*to
);
1319 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1320 struct intel_ring_buffer
*ring
,
1323 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1324 struct drm_device
*dev
,
1325 struct drm_mode_create_dumb
*args
);
1326 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1327 uint32_t handle
, uint64_t *offset
);
1328 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1331 * Returns true if seq1 is later than seq2.
1334 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1336 return (int32_t)(seq1
- seq2
) >= 0;
1339 u32
i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
);
1341 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1342 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1345 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1347 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1348 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1349 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1356 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1358 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1359 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1360 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1364 void i915_gem_retire_requests(struct drm_device
*dev
);
1365 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1366 int __must_check
i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
1367 bool interruptible
);
1369 void i915_gem_reset(struct drm_device
*dev
);
1370 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1371 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1372 uint32_t read_domains
,
1373 uint32_t write_domain
);
1374 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1375 int __must_check
i915_gem_init(struct drm_device
*dev
);
1376 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1377 void i915_gem_l3_remap(struct drm_device
*dev
);
1378 void i915_gem_init_swizzling(struct drm_device
*dev
);
1379 void i915_gem_init_ppgtt(struct drm_device
*dev
);
1380 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1381 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1382 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1383 int i915_add_request(struct intel_ring_buffer
*ring
,
1384 struct drm_file
*file
,
1385 struct drm_i915_gem_request
*request
);
1386 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1388 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1390 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1393 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1395 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1397 struct intel_ring_buffer
*pipelined
);
1398 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1399 struct drm_i915_gem_object
*obj
,
1402 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1403 struct drm_i915_gem_object
*obj
);
1404 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1405 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1408 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1412 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1413 enum i915_cache_level cache_level
);
1415 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1416 struct dma_buf
*dma_buf
);
1418 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1419 struct drm_gem_object
*gem_obj
, int flags
);
1421 /* i915_gem_context.c */
1422 void i915_gem_context_init(struct drm_device
*dev
);
1423 void i915_gem_context_fini(struct drm_device
*dev
);
1424 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1425 int i915_switch_context(struct intel_ring_buffer
*ring
,
1426 struct drm_file
*file
, int to_id
);
1427 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1428 struct drm_file
*file
);
1429 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1430 struct drm_file
*file
);
1432 /* i915_gem_gtt.c */
1433 int __must_check
i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
);
1434 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1435 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1436 struct drm_i915_gem_object
*obj
,
1437 enum i915_cache_level cache_level
);
1438 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1439 struct drm_i915_gem_object
*obj
);
1441 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1442 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1443 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1444 enum i915_cache_level cache_level
);
1445 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1446 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1447 void i915_gem_init_global_gtt(struct drm_device
*dev
,
1448 unsigned long start
,
1449 unsigned long mappable_end
,
1452 /* i915_gem_evict.c */
1453 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1455 unsigned cache_level
,
1457 int i915_gem_evict_everything(struct drm_device
*dev
);
1459 /* i915_gem_stolen.c */
1460 int i915_gem_init_stolen(struct drm_device
*dev
);
1461 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1463 /* i915_gem_tiling.c */
1464 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1465 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1466 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1468 /* i915_gem_debug.c */
1469 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1470 const char *where
, uint32_t mark
);
1472 int i915_verify_lists(struct drm_device
*dev
);
1474 #define i915_verify_lists(dev) 0
1476 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1478 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1479 const char *where
, uint32_t mark
);
1481 /* i915_debugfs.c */
1482 int i915_debugfs_init(struct drm_minor
*minor
);
1483 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1485 /* i915_suspend.c */
1486 extern int i915_save_state(struct drm_device
*dev
);
1487 extern int i915_restore_state(struct drm_device
*dev
);
1489 /* i915_suspend.c */
1490 extern int i915_save_state(struct drm_device
*dev
);
1491 extern int i915_restore_state(struct drm_device
*dev
);
1494 void i915_setup_sysfs(struct drm_device
*dev_priv
);
1495 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
1498 extern int intel_setup_gmbus(struct drm_device
*dev
);
1499 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1500 extern inline bool intel_gmbus_is_port_valid(unsigned port
)
1502 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
1505 extern struct i2c_adapter
*intel_gmbus_get_adapter(
1506 struct drm_i915_private
*dev_priv
, unsigned port
);
1507 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1508 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1509 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1511 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1513 extern void intel_i2c_reset(struct drm_device
*dev
);
1515 /* intel_opregion.c */
1516 extern int intel_opregion_setup(struct drm_device
*dev
);
1518 extern void intel_opregion_init(struct drm_device
*dev
);
1519 extern void intel_opregion_fini(struct drm_device
*dev
);
1520 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1521 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1522 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1524 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1525 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1526 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1527 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1528 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1533 extern void intel_register_dsm_handler(void);
1534 extern void intel_unregister_dsm_handler(void);
1536 static inline void intel_register_dsm_handler(void) { return; }
1537 static inline void intel_unregister_dsm_handler(void) { return; }
1538 #endif /* CONFIG_ACPI */
1541 extern void intel_modeset_init_hw(struct drm_device
*dev
);
1542 extern void intel_modeset_init(struct drm_device
*dev
);
1543 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1544 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1545 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1546 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1547 extern void intel_disable_fbc(struct drm_device
*dev
);
1548 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1549 extern void ironlake_init_pch_refclk(struct drm_device
*dev
);
1550 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1551 extern void intel_detect_pch(struct drm_device
*dev
);
1552 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1553 extern int intel_enable_rc6(const struct drm_device
*dev
);
1555 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
1556 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
1557 struct drm_file
*file
);
1560 #ifdef CONFIG_DEBUG_FS
1561 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1562 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1564 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1565 extern void intel_display_print_error_state(struct seq_file
*m
,
1566 struct drm_device
*dev
,
1567 struct intel_display_error_state
*error
);
1570 /* On SNB platform, before reading ring registers forcewake bit
1571 * must be set to prevent GT core from power down and stale values being
1574 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1575 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1576 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1578 #define __i915_read(x, y) \
1579 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1587 #define __i915_write(x, y) \
1588 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1596 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1597 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1599 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1600 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1601 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1602 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1604 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1605 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1606 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1607 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1609 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1610 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1612 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1613 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)