1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
56 #include "intel_bios.h"
57 #include "intel_dpll_mgr.h"
58 #include "intel_guc.h"
59 #include "intel_lrc.h"
60 #include "intel_ringbuffer.h"
63 #include "i915_gem_gtt.h"
64 #include "i915_gem_render_state.h"
65 #include "i915_gem_request.h"
66 #include "i915_gem_timeline.h"
68 #include "intel_gvt.h"
70 /* General customization:
73 #define DRIVER_NAME "i915"
74 #define DRIVER_DESC "Intel Graphics"
75 #define DRIVER_DATE "20161108"
76 #define DRIVER_TIMESTAMP 1478587895
79 /* Many gcc seem to no see through this and fall over :( */
81 #define WARN_ON(x) ({ \
82 bool __i915_warn_cond = (x); \
83 if (__builtin_constant_p(__i915_warn_cond)) \
84 BUILD_BUG_ON(__i915_warn_cond); \
85 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
87 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
91 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
93 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
94 (long) (x), __func__);
96 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
97 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
98 * which may not necessarily be a user visible problem. This will either
99 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
100 * enable distros and users to tailor their preferred amount of i915 abrt
103 #define I915_STATE_WARN(condition, format...) ({ \
104 int __ret_warn_on = !!(condition); \
105 if (unlikely(__ret_warn_on)) \
106 if (!WARN(i915.verbose_state_checks, format)) \
108 unlikely(__ret_warn_on); \
111 #define I915_STATE_WARN_ON(x) \
112 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
114 bool __i915_inject_load_failure(const char *func
, int line
);
115 #define i915_inject_load_failure() \
116 __i915_inject_load_failure(__func__, __LINE__)
118 static inline const char *yesno(bool v
)
120 return v
? "yes" : "no";
123 static inline const char *onoff(bool v
)
125 return v
? "on" : "off";
134 I915_MAX_PIPES
= _PIPE_EDP
136 #define pipe_name(p) ((p) + 'A')
148 static inline const char *transcoder_name(enum transcoder transcoder
)
150 switch (transcoder
) {
159 case TRANSCODER_DSI_A
:
161 case TRANSCODER_DSI_C
:
168 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
170 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
174 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
175 * number of planes per CRTC. Not all platforms really have this many planes,
176 * which means some arrays of size I915_MAX_PLANES may have unused entries
177 * between the topmost sprite plane and the cursor plane.
186 #define plane_name(p) ((p) + 'A')
188 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
199 #define port_name(p) ((p) + 'A')
201 #define I915_NUM_PHYS_VLV 2
213 enum intel_display_power_domain
{
217 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
218 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
219 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
220 POWER_DOMAIN_TRANSCODER_A
,
221 POWER_DOMAIN_TRANSCODER_B
,
222 POWER_DOMAIN_TRANSCODER_C
,
223 POWER_DOMAIN_TRANSCODER_EDP
,
224 POWER_DOMAIN_TRANSCODER_DSI_A
,
225 POWER_DOMAIN_TRANSCODER_DSI_C
,
226 POWER_DOMAIN_PORT_DDI_A_LANES
,
227 POWER_DOMAIN_PORT_DDI_B_LANES
,
228 POWER_DOMAIN_PORT_DDI_C_LANES
,
229 POWER_DOMAIN_PORT_DDI_D_LANES
,
230 POWER_DOMAIN_PORT_DDI_E_LANES
,
231 POWER_DOMAIN_PORT_DSI
,
232 POWER_DOMAIN_PORT_CRT
,
233 POWER_DOMAIN_PORT_OTHER
,
242 POWER_DOMAIN_MODESET
,
248 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
249 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
250 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
251 #define POWER_DOMAIN_TRANSCODER(tran) \
252 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
253 (tran) + POWER_DOMAIN_TRANSCODER_A)
257 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
269 #define for_each_hpd_pin(__pin) \
270 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
272 struct i915_hotplug
{
273 struct work_struct hotplug_work
;
276 unsigned long last_jiffies
;
281 HPD_MARK_DISABLED
= 2
283 } stats
[HPD_NUM_PINS
];
285 struct delayed_work reenable_work
;
287 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
290 struct work_struct dig_port_work
;
292 struct work_struct poll_init_work
;
296 * if we get a HPD irq from DP and a HPD irq from non-DP
297 * the non-DP HPD could block the workqueue on a mode config
298 * mutex getting, that userspace may have taken. However
299 * userspace is waiting on the DP workqueue to run which is
300 * blocked behind the non-DP one.
302 struct workqueue_struct
*dp_wq
;
305 #define I915_GEM_GPU_DOMAINS \
306 (I915_GEM_DOMAIN_RENDER | \
307 I915_GEM_DOMAIN_SAMPLER | \
308 I915_GEM_DOMAIN_COMMAND | \
309 I915_GEM_DOMAIN_INSTRUCTION | \
310 I915_GEM_DOMAIN_VERTEX)
312 #define for_each_pipe(__dev_priv, __p) \
313 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
314 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
315 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
316 for_each_if ((__mask) & (1 << (__p)))
317 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
319 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
321 #define for_each_sprite(__dev_priv, __p, __s) \
323 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
326 #define for_each_port_masked(__port, __ports_mask) \
327 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
328 for_each_if ((__ports_mask) & (1 << (__port)))
330 #define for_each_crtc(dev, crtc) \
331 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
333 #define for_each_intel_plane(dev, intel_plane) \
334 list_for_each_entry(intel_plane, \
335 &(dev)->mode_config.plane_list, \
338 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
339 list_for_each_entry(intel_plane, \
340 &(dev)->mode_config.plane_list, \
342 for_each_if ((plane_mask) & \
343 (1 << drm_plane_index(&intel_plane->base)))
345 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
346 list_for_each_entry(intel_plane, \
347 &(dev)->mode_config.plane_list, \
349 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
351 #define for_each_intel_crtc(dev, intel_crtc) \
352 list_for_each_entry(intel_crtc, \
353 &(dev)->mode_config.crtc_list, \
356 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
357 list_for_each_entry(intel_crtc, \
358 &(dev)->mode_config.crtc_list, \
360 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
362 #define for_each_intel_encoder(dev, intel_encoder) \
363 list_for_each_entry(intel_encoder, \
364 &(dev)->mode_config.encoder_list, \
367 #define for_each_intel_connector(dev, intel_connector) \
368 list_for_each_entry(intel_connector, \
369 &(dev)->mode_config.connector_list, \
372 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
373 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
374 for_each_if ((intel_encoder)->base.crtc == (__crtc))
376 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
377 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
378 for_each_if ((intel_connector)->base.encoder == (__encoder))
380 #define for_each_power_domain(domain, mask) \
381 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
382 for_each_if ((1 << (domain)) & (mask))
384 struct drm_i915_private
;
385 struct i915_mm_struct
;
386 struct i915_mmu_object
;
388 struct drm_i915_file_private
{
389 struct drm_i915_private
*dev_priv
;
390 struct drm_file
*file
;
394 struct list_head request_list
;
395 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
396 * chosen to prevent the CPU getting more than a frame ahead of the GPU
397 * (when using lax throttling for the frontbuffer). We also use it to
398 * offer free GPU waitboosts for severely congested workloads.
400 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
402 struct idr context_idr
;
404 struct intel_rps_client
{
405 struct list_head link
;
409 unsigned int bsd_engine
;
412 /* Used by dp and fdi links */
413 struct intel_link_m_n
{
421 void intel_link_compute_m_n(int bpp
, int nlanes
,
422 int pixel_clock
, int link_clock
,
423 struct intel_link_m_n
*m_n
);
425 /* Interface history:
428 * 1.2: Add Power Management
429 * 1.3: Add vblank support
430 * 1.4: Fix cmdbuffer path, add heap destroy
431 * 1.5: Add vblank pipe configuration
432 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
433 * - Support vertical blank on secondary display pipe
435 #define DRIVER_MAJOR 1
436 #define DRIVER_MINOR 6
437 #define DRIVER_PATCHLEVEL 0
439 struct opregion_header
;
440 struct opregion_acpi
;
441 struct opregion_swsci
;
442 struct opregion_asle
;
444 struct intel_opregion
{
445 struct opregion_header
*header
;
446 struct opregion_acpi
*acpi
;
447 struct opregion_swsci
*swsci
;
448 u32 swsci_gbda_sub_functions
;
449 u32 swsci_sbcb_sub_functions
;
450 struct opregion_asle
*asle
;
455 struct work_struct asle_work
;
457 #define OPREGION_SIZE (8*1024)
459 struct intel_overlay
;
460 struct intel_overlay_error_state
;
462 struct drm_i915_fence_reg
{
463 struct list_head link
;
464 struct drm_i915_private
*i915
;
465 struct i915_vma
*vma
;
469 * Whether the tiling parameters for the currently
470 * associated fence register have changed. Note that
471 * for the purposes of tracking tiling changes we also
472 * treat the unfenced register, the register slot that
473 * the object occupies whilst it executes a fenced
474 * command (such as BLT on gen2/3), as a "fence".
479 struct sdvo_device_mapping
{
488 struct intel_connector
;
489 struct intel_encoder
;
490 struct intel_crtc_state
;
491 struct intel_initial_plane_config
;
496 struct drm_i915_display_funcs
{
497 int (*get_display_clock_speed
)(struct drm_i915_private
*dev_priv
);
498 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
499 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
500 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
501 struct intel_crtc
*intel_crtc
,
502 struct intel_crtc_state
*newstate
);
503 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
504 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
505 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
506 void (*update_wm
)(struct intel_crtc
*crtc
);
507 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
508 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
509 /* Returns the active state of the crtc, and if the crtc is active,
510 * fills out the pipe-config with the hw state. */
511 bool (*get_pipe_config
)(struct intel_crtc
*,
512 struct intel_crtc_state
*);
513 void (*get_initial_plane_config
)(struct intel_crtc
*,
514 struct intel_initial_plane_config
*);
515 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
516 struct intel_crtc_state
*crtc_state
);
517 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
518 struct drm_atomic_state
*old_state
);
519 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
520 struct drm_atomic_state
*old_state
);
521 void (*update_crtcs
)(struct drm_atomic_state
*state
,
522 unsigned int *crtc_vblank_mask
);
523 void (*audio_codec_enable
)(struct drm_connector
*connector
,
524 struct intel_encoder
*encoder
,
525 const struct drm_display_mode
*adjusted_mode
);
526 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
527 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
528 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
529 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
530 struct drm_framebuffer
*fb
,
531 struct drm_i915_gem_object
*obj
,
532 struct drm_i915_gem_request
*req
,
534 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
535 /* clock updates for mode set */
537 /* render clock increase/decrease */
538 /* display clock increase/decrease */
539 /* pll clock increase/decrease */
541 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
542 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
545 enum forcewake_domain_id
{
546 FW_DOMAIN_ID_RENDER
= 0,
547 FW_DOMAIN_ID_BLITTER
,
553 enum forcewake_domains
{
554 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
555 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
556 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
557 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
562 #define FW_REG_READ (1)
563 #define FW_REG_WRITE (2)
565 enum forcewake_domains
566 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
567 i915_reg_t reg
, unsigned int op
);
569 struct intel_uncore_funcs
{
570 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
571 enum forcewake_domains domains
);
572 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
573 enum forcewake_domains domains
);
575 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
576 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
577 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
578 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
580 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
581 uint8_t val
, bool trace
);
582 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
583 uint16_t val
, bool trace
);
584 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
585 uint32_t val
, bool trace
);
588 struct intel_forcewake_range
{
592 enum forcewake_domains domains
;
595 struct intel_uncore
{
596 spinlock_t lock
; /** lock is also taken in irq contexts. */
598 const struct intel_forcewake_range
*fw_domains_table
;
599 unsigned int fw_domains_table_entries
;
601 struct intel_uncore_funcs funcs
;
605 enum forcewake_domains fw_domains
;
606 enum forcewake_domains fw_domains_active
;
608 struct intel_uncore_forcewake_domain
{
609 struct drm_i915_private
*i915
;
610 enum forcewake_domain_id id
;
611 enum forcewake_domains mask
;
613 struct hrtimer timer
;
620 } fw_domain
[FW_DOMAIN_ID_COUNT
];
622 int unclaimed_mmio_check
;
625 /* Iterate over initialised fw domains */
626 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
627 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
628 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
630 for_each_if ((mask__) & (domain__)->mask)
632 #define for_each_fw_domain(domain__, dev_priv__) \
633 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
635 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
636 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
637 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
640 struct work_struct work
;
642 uint32_t *dmc_payload
;
643 uint32_t dmc_fw_size
;
646 i915_reg_t mmioaddr
[8];
647 uint32_t mmiodata
[8];
649 uint32_t allowed_dc_mask
;
652 #define DEV_INFO_FOR_EACH_FLAG(func) \
653 /* Keep is_* in chronological order */ \
661 func(is_broadwater); \
662 func(is_crestline); \
663 func(is_ivybridge); \
664 func(is_valleyview); \
665 func(is_cherryview); \
667 func(is_broadwell); \
671 func(is_preliminary); \
672 /* Keep has_* in alphabetical order */ \
673 func(has_64bit_reloc); \
678 func(has_fpga_dbg); \
679 func(has_gmbus_irq); \
680 func(has_gmch_display); \
683 func(has_hw_contexts); \
686 func(has_logical_ring_contexts); \
688 func(has_pipe_cxsr); \
689 func(has_pooled_eu); \
693 func(has_resource_streamer); \
694 func(has_runtime_pm); \
696 func(cursor_needs_physical); \
697 func(hws_needs_physical); \
698 func(overlay_needs_physical); \
701 struct sseu_dev_info
{
707 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
710 u8 has_subslice_pg
:1;
714 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
716 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
719 struct intel_device_info
{
720 u32 display_mmio_offset
;
723 u8 num_sprites
[I915_MAX_PIPES
];
726 u8 ring_mask
; /* Rings supported by the HW */
728 #define DEFINE_FLAG(name) u8 name:1
729 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
731 u16 ddb_size
; /* in blocks */
732 /* Register offsets for the various display pipes and transcoders */
733 int pipe_offsets
[I915_MAX_TRANSCODERS
];
734 int trans_offsets
[I915_MAX_TRANSCODERS
];
735 int palette_offsets
[I915_MAX_PIPES
];
736 int cursor_offsets
[I915_MAX_PIPES
];
738 /* Slice/subslice/EU info */
739 struct sseu_dev_info sseu
;
742 u16 degamma_lut_size
;
747 struct intel_display_error_state
;
749 struct drm_i915_error_state
{
752 struct timeval boottime
;
753 struct timeval uptime
;
755 struct drm_i915_private
*i915
;
762 struct intel_device_info device_info
;
764 /* Generic register state */
772 u32 error
; /* gen6+ */
773 u32 err_int
; /* gen7 */
774 u32 fault_data0
; /* gen8, gen9 */
775 u32 fault_data1
; /* gen8, gen9 */
782 u64 fence
[I915_MAX_NUM_FENCES
];
783 struct intel_overlay_error_state
*overlay
;
784 struct intel_display_error_state
*display
;
785 struct drm_i915_error_object
*semaphore
;
786 struct drm_i915_error_object
*guc_log
;
788 struct drm_i915_error_engine
{
790 /* Software tracked state */
794 enum intel_engine_hangcheck_action hangcheck_action
;
795 struct i915_address_space
*vm
;
798 /* position of active request inside the ring */
799 u32 rq_head
, rq_post
, rq_tail
;
801 /* our own tracking of ring head and tail */
824 u32 rc_psmi
; /* sleep state */
825 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
826 struct intel_instdone instdone
;
828 struct drm_i915_error_object
{
834 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
836 struct drm_i915_error_object
*wa_ctx
;
838 struct drm_i915_error_request
{
845 } *requests
, execlist
[2];
847 struct drm_i915_error_waiter
{
848 char comm
[TASK_COMM_LEN
];
862 char comm
[TASK_COMM_LEN
];
863 } engine
[I915_NUM_ENGINES
];
865 struct drm_i915_error_buffer
{
868 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
872 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
879 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
880 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
881 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
884 enum i915_cache_level
{
886 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
887 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
888 caches, eg sampler/render caches, and the
889 large Last-Level-Cache. LLC is coherent with
890 the CPU, but L3 is only visible to the GPU. */
891 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
894 struct i915_ctx_hang_stats
{
895 /* This context had batch pending when hang was declared */
896 unsigned batch_pending
;
898 /* This context had batch active when hang was declared */
899 unsigned batch_active
;
901 /* Time when this context was last blamed for a GPU reset */
902 unsigned long guilty_ts
;
904 /* If the contexts causes a second GPU hang within this time,
905 * it is permanently banned from submitting any more work.
907 unsigned long ban_period_seconds
;
909 /* This context is banned to submit more work */
913 /* This must match up with the value previously used for execbuf2.rsvd1. */
914 #define DEFAULT_CONTEXT_HANDLE 0
917 * struct i915_gem_context - as the name implies, represents a context.
918 * @ref: reference count.
919 * @user_handle: userspace tracking identity for this context.
920 * @remap_slice: l3 row remapping information.
921 * @flags: context specific flags:
922 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
923 * @file_priv: filp associated with this context (NULL for global default
925 * @hang_stats: information about the role of this context in possible GPU
927 * @ppgtt: virtual memory space used by this context.
928 * @legacy_hw_ctx: render context backing object and whether it is correctly
929 * initialized (legacy ring submission mechanism only).
930 * @link: link in the global list of contexts.
932 * Contexts are memory images used by the hardware to store copies of their
935 struct i915_gem_context
{
937 struct drm_i915_private
*i915
;
938 struct drm_i915_file_private
*file_priv
;
939 struct i915_hw_ppgtt
*ppgtt
;
943 struct i915_ctx_hang_stats hang_stats
;
946 #define CONTEXT_NO_ZEROMAP BIT(0)
947 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
949 /* Unique identifier for this context, used by the hw for tracking */
955 struct intel_context
{
956 struct i915_vma
*state
;
957 struct intel_ring
*ring
;
958 uint32_t *lrc_reg_state
;
962 } engine
[I915_NUM_ENGINES
];
965 struct atomic_notifier_head status_notifier
;
966 bool execlists_force_single_submission
;
968 struct list_head link
;
983 /* This is always the inner lock when overlapping with struct_mutex and
984 * it's the outer lock when overlapping with stolen_lock. */
987 unsigned int possible_framebuffer_bits
;
988 unsigned int busy_bits
;
989 unsigned int visible_pipes_mask
;
990 struct intel_crtc
*crtc
;
992 struct drm_mm_node compressed_fb
;
993 struct drm_mm_node
*compressed_llb
;
1000 bool underrun_detected
;
1001 struct work_struct underrun_work
;
1003 struct intel_fbc_state_cache
{
1005 unsigned int mode_flags
;
1006 uint32_t hsw_bdw_pixel_rate
;
1010 unsigned int rotation
;
1017 u64 ilk_ggtt_offset
;
1018 uint32_t pixel_format
;
1019 unsigned int stride
;
1021 unsigned int tiling_mode
;
1025 struct intel_fbc_reg_params
{
1029 unsigned int fence_y_offset
;
1034 uint32_t pixel_format
;
1035 unsigned int stride
;
1042 struct intel_fbc_work
{
1044 u32 scheduled_vblank
;
1045 struct work_struct work
;
1048 const char *no_fbc_reason
;
1052 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1053 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1054 * parsing for same resolution.
1056 enum drrs_refresh_rate_type
{
1059 DRRS_MAX_RR
, /* RR count */
1062 enum drrs_support_type
{
1063 DRRS_NOT_SUPPORTED
= 0,
1064 STATIC_DRRS_SUPPORT
= 1,
1065 SEAMLESS_DRRS_SUPPORT
= 2
1071 struct delayed_work work
;
1072 struct intel_dp
*dp
;
1073 unsigned busy_frontbuffer_bits
;
1074 enum drrs_refresh_rate_type refresh_rate_type
;
1075 enum drrs_support_type type
;
1082 struct intel_dp
*enabled
;
1084 struct delayed_work work
;
1085 unsigned busy_frontbuffer_bits
;
1087 bool aux_frame_sync
;
1092 PCH_NONE
= 0, /* No PCH present */
1093 PCH_IBX
, /* Ibexpeak PCH */
1094 PCH_CPT
, /* Cougarpoint PCH */
1095 PCH_LPT
, /* Lynxpoint PCH */
1096 PCH_SPT
, /* Sunrisepoint PCH */
1097 PCH_KBP
, /* Kabypoint PCH */
1101 enum intel_sbi_destination
{
1106 #define QUIRK_PIPEA_FORCE (1<<0)
1107 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1108 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1109 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1110 #define QUIRK_PIPEB_FORCE (1<<4)
1111 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1114 struct intel_fbc_work
;
1116 struct intel_gmbus
{
1117 struct i2c_adapter adapter
;
1118 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1121 i915_reg_t gpio_reg
;
1122 struct i2c_algo_bit_data bit_algo
;
1123 struct drm_i915_private
*dev_priv
;
1126 struct i915_suspend_saved_registers
{
1128 u32 saveFBC_CONTROL
;
1129 u32 saveCACHE_MODE_0
;
1130 u32 saveMI_ARB_STATE
;
1134 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1135 u32 savePCH_PORT_HOTPLUG
;
1139 struct vlv_s0ix_state
{
1146 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1147 u32 media_max_req_count
;
1148 u32 gfx_max_req_count
;
1174 u32 rp_down_timeout
;
1180 /* Display 1 CZ domain */
1185 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1187 /* GT SA CZ domain */
1194 /* Display 2 CZ domain */
1198 u32 clock_gate_dis2
;
1201 struct intel_rps_ei
{
1207 struct intel_gen6_power_mgmt
{
1209 * work, interrupts_enabled and pm_iir are protected by
1210 * dev_priv->irq_lock
1212 struct work_struct work
;
1213 bool interrupts_enabled
;
1216 /* PM interrupt bits that should never be masked */
1219 /* Frequencies are stored in potentially platform dependent multiples.
1220 * In other words, *_freq needs to be multiplied by X to be interesting.
1221 * Soft limits are those which are used for the dynamic reclocking done
1222 * by the driver (raise frequencies under heavy loads, and lower for
1223 * lighter loads). Hard limits are those imposed by the hardware.
1225 * A distinction is made for overclocking, which is never enabled by
1226 * default, and is considered to be above the hard limit if it's
1229 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1230 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1231 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1232 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1233 u8 min_freq
; /* AKA RPn. Minimum frequency */
1234 u8 boost_freq
; /* Frequency to request when wait boosting */
1235 u8 idle_freq
; /* Frequency to request when we are idle */
1236 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1237 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1238 u8 rp0_freq
; /* Non-overclocked max frequency. */
1239 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1241 u8 up_threshold
; /* Current %busy required to uplock */
1242 u8 down_threshold
; /* Current %busy required to downclock */
1245 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1247 spinlock_t client_lock
;
1248 struct list_head clients
;
1252 struct delayed_work autoenable_work
;
1255 /* manual wa residency calculations */
1256 struct intel_rps_ei up_ei
, down_ei
;
1259 * Protects RPS/RC6 register access and PCU communication.
1260 * Must be taken after struct_mutex if nested. Note that
1261 * this lock may be held for long periods of time when
1262 * talking to hw - so only take it when talking to hw!
1264 struct mutex hw_lock
;
1267 /* defined intel_pm.c */
1268 extern spinlock_t mchdev_lock
;
1270 struct intel_ilk_power_mgmt
{
1278 unsigned long last_time1
;
1279 unsigned long chipset_power
;
1282 unsigned long gfx_power
;
1289 struct drm_i915_private
;
1290 struct i915_power_well
;
1292 struct i915_power_well_ops
{
1294 * Synchronize the well's hw state to match the current sw state, for
1295 * example enable/disable it based on the current refcount. Called
1296 * during driver init and resume time, possibly after first calling
1297 * the enable/disable handlers.
1299 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1300 struct i915_power_well
*power_well
);
1302 * Enable the well and resources that depend on it (for example
1303 * interrupts located on the well). Called after the 0->1 refcount
1306 void (*enable
)(struct drm_i915_private
*dev_priv
,
1307 struct i915_power_well
*power_well
);
1309 * Disable the well and resources that depend on it. Called after
1310 * the 1->0 refcount transition.
1312 void (*disable
)(struct drm_i915_private
*dev_priv
,
1313 struct i915_power_well
*power_well
);
1314 /* Returns the hw enabled state. */
1315 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1316 struct i915_power_well
*power_well
);
1319 /* Power well structure for haswell */
1320 struct i915_power_well
{
1323 /* power well enable/disable usage count */
1325 /* cached hw enabled state */
1327 unsigned long domains
;
1328 /* unique identifier for this power well */
1331 * Arbitraty data associated with this power well. Platform and power
1335 const struct i915_power_well_ops
*ops
;
1338 struct i915_power_domains
{
1340 * Power wells needed for initialization at driver init and suspend
1341 * time are on. They are kept on until after the first modeset.
1345 int power_well_count
;
1348 int domain_use_count
[POWER_DOMAIN_NUM
];
1349 struct i915_power_well
*power_wells
;
1352 #define MAX_L3_SLICES 2
1353 struct intel_l3_parity
{
1354 u32
*remap_info
[MAX_L3_SLICES
];
1355 struct work_struct error_work
;
1359 struct i915_gem_mm
{
1360 /** Memory allocator for GTT stolen memory */
1361 struct drm_mm stolen
;
1362 /** Protects the usage of the GTT stolen memory allocator. This is
1363 * always the inner lock when overlapping with struct_mutex. */
1364 struct mutex stolen_lock
;
1366 /** List of all objects in gtt_space. Used to restore gtt
1367 * mappings on resume */
1368 struct list_head bound_list
;
1370 * List of objects which are not bound to the GTT (thus
1371 * are idle and not used by the GPU). These objects may or may
1372 * not actually have any pages attached.
1374 struct list_head unbound_list
;
1376 /** List of all objects in gtt_space, currently mmaped by userspace.
1377 * All objects within this list must also be on bound_list.
1379 struct list_head userfault_list
;
1382 * List of objects which are pending destruction.
1384 struct llist_head free_list
;
1385 struct work_struct free_work
;
1387 /** Usable portion of the GTT for GEM */
1388 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1390 /** PPGTT used for aliasing the PPGTT with the GTT */
1391 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1393 struct notifier_block oom_notifier
;
1394 struct notifier_block vmap_notifier
;
1395 struct shrinker shrinker
;
1397 /** LRU list of objects with fence regs on them. */
1398 struct list_head fence_list
;
1401 * Are we in a non-interruptible section of code like
1406 /* the indicator for dispatch video commands on two BSD rings */
1407 atomic_t bsd_engine_dispatch_index
;
1409 /** Bit 6 swizzling required for X tiling */
1410 uint32_t bit_6_swizzle_x
;
1411 /** Bit 6 swizzling required for Y tiling */
1412 uint32_t bit_6_swizzle_y
;
1414 /* accounting, useful for userland debugging */
1415 spinlock_t object_stat_lock
;
1420 struct drm_i915_error_state_buf
{
1421 struct drm_i915_private
*i915
;
1430 struct i915_error_state_file_priv
{
1431 struct drm_device
*dev
;
1432 struct drm_i915_error_state
*error
;
1435 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1436 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1438 struct i915_gpu_error
{
1439 /* For hangcheck timer */
1440 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1441 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1442 /* Hang gpu twice in this window and your context gets banned */
1443 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1445 struct delayed_work hangcheck_work
;
1447 /* For reset and error_state handling. */
1449 /* Protected by the above dev->gpu_error.lock. */
1450 struct drm_i915_error_state
*first_error
;
1452 unsigned long missed_irq_rings
;
1455 * State variable controlling the reset flow and count
1457 * This is a counter which gets incremented when reset is triggered,
1459 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1460 * meaning that any waiters holding onto the struct_mutex should
1461 * relinquish the lock immediately in order for the reset to start.
1463 * If reset is not completed succesfully, the I915_WEDGE bit is
1464 * set meaning that hardware is terminally sour and there is no
1465 * recovery. All waiters on the reset_queue will be woken when
1468 * This counter is used by the wait_seqno code to notice that reset
1469 * event happened and it needs to restart the entire ioctl (since most
1470 * likely the seqno it waited for won't ever signal anytime soon).
1472 * This is important for lock-free wait paths, where no contended lock
1473 * naturally enforces the correct ordering between the bail-out of the
1474 * waiter and the gpu reset work code.
1476 unsigned long reset_count
;
1478 unsigned long flags
;
1479 #define I915_RESET_IN_PROGRESS 0
1480 #define I915_WEDGED (BITS_PER_LONG - 1)
1483 * Waitqueue to signal when a hang is detected. Used to for waiters
1484 * to release the struct_mutex for the reset to procede.
1486 wait_queue_head_t wait_queue
;
1489 * Waitqueue to signal when the reset has completed. Used by clients
1490 * that wait for dev_priv->mm.wedged to settle.
1492 wait_queue_head_t reset_queue
;
1494 /* For missed irq/seqno simulation. */
1495 unsigned long test_irq_rings
;
1498 enum modeset_restore
{
1499 MODESET_ON_LID_OPEN
,
1504 #define DP_AUX_A 0x40
1505 #define DP_AUX_B 0x10
1506 #define DP_AUX_C 0x20
1507 #define DP_AUX_D 0x30
1509 #define DDC_PIN_B 0x05
1510 #define DDC_PIN_C 0x04
1511 #define DDC_PIN_D 0x06
1513 struct ddi_vbt_port_info
{
1515 * This is an index in the HDMI/DVI DDI buffer translation table.
1516 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1517 * populate this field.
1519 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1520 uint8_t hdmi_level_shift
;
1522 uint8_t supports_dvi
:1;
1523 uint8_t supports_hdmi
:1;
1524 uint8_t supports_dp
:1;
1526 uint8_t alternate_aux_channel
;
1527 uint8_t alternate_ddc_pin
;
1529 uint8_t dp_boost_level
;
1530 uint8_t hdmi_boost_level
;
1533 enum psr_lines_to_wait
{
1534 PSR_0_LINES_TO_WAIT
= 0,
1536 PSR_4_LINES_TO_WAIT
,
1540 struct intel_vbt_data
{
1541 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1542 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1545 unsigned int int_tv_support
:1;
1546 unsigned int lvds_dither
:1;
1547 unsigned int lvds_vbt
:1;
1548 unsigned int int_crt_support
:1;
1549 unsigned int lvds_use_ssc
:1;
1550 unsigned int display_clock_mode
:1;
1551 unsigned int fdi_rx_polarity_inverted
:1;
1552 unsigned int panel_type
:4;
1554 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1556 enum drrs_support_type drrs_type
;
1567 struct edp_power_seq pps
;
1572 bool require_aux_wakeup
;
1574 enum psr_lines_to_wait lines_to_wait
;
1575 int tp1_wakeup_time
;
1576 int tp2_tp3_wakeup_time
;
1582 bool active_low_pwm
;
1583 u8 min_brightness
; /* min_brightness/255 of max */
1584 enum intel_backlight_type type
;
1590 struct mipi_config
*config
;
1591 struct mipi_pps_data
*pps
;
1595 const u8
*sequence
[MIPI_SEQ_MAX
];
1601 union child_device_config
*child_dev
;
1603 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1604 struct sdvo_device_mapping sdvo_mappings
[2];
1607 enum intel_ddb_partitioning
{
1609 INTEL_DDB_PART_5_6
, /* IVB+ */
1612 struct intel_wm_level
{
1620 struct ilk_wm_values
{
1621 uint32_t wm_pipe
[3];
1623 uint32_t wm_lp_spr
[3];
1624 uint32_t wm_linetime
[3];
1626 enum intel_ddb_partitioning partitioning
;
1629 struct vlv_pipe_wm
{
1640 struct vlv_wm_values
{
1641 struct vlv_pipe_wm pipe
[3];
1642 struct vlv_sr_wm sr
;
1652 struct skl_ddb_entry
{
1653 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1656 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1658 return entry
->end
- entry
->start
;
1661 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1662 const struct skl_ddb_entry
*e2
)
1664 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1670 struct skl_ddb_allocation
{
1671 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1672 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1675 struct skl_wm_values
{
1676 unsigned dirty_pipes
;
1677 struct skl_ddb_allocation ddb
;
1680 struct skl_wm_level
{
1682 uint16_t plane_res_b
;
1683 uint8_t plane_res_l
;
1687 * This struct helps tracking the state needed for runtime PM, which puts the
1688 * device in PCI D3 state. Notice that when this happens, nothing on the
1689 * graphics device works, even register access, so we don't get interrupts nor
1692 * Every piece of our code that needs to actually touch the hardware needs to
1693 * either call intel_runtime_pm_get or call intel_display_power_get with the
1694 * appropriate power domain.
1696 * Our driver uses the autosuspend delay feature, which means we'll only really
1697 * suspend if we stay with zero refcount for a certain amount of time. The
1698 * default value is currently very conservative (see intel_runtime_pm_enable), but
1699 * it can be changed with the standard runtime PM files from sysfs.
1701 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1702 * goes back to false exactly before we reenable the IRQs. We use this variable
1703 * to check if someone is trying to enable/disable IRQs while they're supposed
1704 * to be disabled. This shouldn't happen and we'll print some error messages in
1707 * For more, read the Documentation/power/runtime_pm.txt.
1709 struct i915_runtime_pm
{
1710 atomic_t wakeref_count
;
1715 enum intel_pipe_crc_source
{
1716 INTEL_PIPE_CRC_SOURCE_NONE
,
1717 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1718 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1719 INTEL_PIPE_CRC_SOURCE_PF
,
1720 INTEL_PIPE_CRC_SOURCE_PIPE
,
1721 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1722 INTEL_PIPE_CRC_SOURCE_TV
,
1723 INTEL_PIPE_CRC_SOURCE_DP_B
,
1724 INTEL_PIPE_CRC_SOURCE_DP_C
,
1725 INTEL_PIPE_CRC_SOURCE_DP_D
,
1726 INTEL_PIPE_CRC_SOURCE_AUTO
,
1727 INTEL_PIPE_CRC_SOURCE_MAX
,
1730 struct intel_pipe_crc_entry
{
1735 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1736 struct intel_pipe_crc
{
1738 bool opened
; /* exclusive access to the result file */
1739 struct intel_pipe_crc_entry
*entries
;
1740 enum intel_pipe_crc_source source
;
1742 wait_queue_head_t wq
;
1745 struct i915_frontbuffer_tracking
{
1749 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1756 struct i915_wa_reg
{
1759 /* bitmask representing WA bits */
1764 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1765 * allowing it for RCS as we don't foresee any requirement of having
1766 * a whitelist for other engines. When it is really required for
1767 * other engines then the limit need to be increased.
1769 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1771 struct i915_workarounds
{
1772 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1774 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1777 struct i915_virtual_gpu
{
1781 /* used in computing the new watermarks state */
1782 struct intel_wm_config
{
1783 unsigned int num_pipes_active
;
1784 bool sprites_enabled
;
1785 bool sprites_scaled
;
1788 struct drm_i915_private
{
1789 struct drm_device drm
;
1791 struct kmem_cache
*objects
;
1792 struct kmem_cache
*vmas
;
1793 struct kmem_cache
*requests
;
1795 const struct intel_device_info info
;
1797 int relative_constants_mode
;
1801 struct intel_uncore uncore
;
1803 struct i915_virtual_gpu vgpu
;
1805 struct intel_gvt
*gvt
;
1807 struct intel_guc guc
;
1809 struct intel_csr csr
;
1811 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1813 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1814 * controller on different i2c buses. */
1815 struct mutex gmbus_mutex
;
1818 * Base address of the gmbus and gpio block.
1820 uint32_t gpio_mmio_base
;
1822 /* MMIO base address for MIPI regs */
1823 uint32_t mipi_mmio_base
;
1825 uint32_t psr_mmio_base
;
1827 uint32_t pps_mmio_base
;
1829 wait_queue_head_t gmbus_wait_queue
;
1831 struct pci_dev
*bridge_dev
;
1832 struct i915_gem_context
*kernel_context
;
1833 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
1834 struct i915_vma
*semaphore
;
1836 struct drm_dma_handle
*status_page_dmah
;
1837 struct resource mch_res
;
1839 /* protects the irq masks */
1840 spinlock_t irq_lock
;
1842 /* protects the mmio flip data */
1843 spinlock_t mmio_flip_lock
;
1845 bool display_irqs_enabled
;
1847 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1848 struct pm_qos_request pm_qos
;
1850 /* Sideband mailbox protection */
1851 struct mutex sb_lock
;
1853 /** Cached value of IMR to avoid reads in updating the bitfield */
1856 u32 de_irq_mask
[I915_MAX_PIPES
];
1863 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1865 struct i915_hotplug hotplug
;
1866 struct intel_fbc fbc
;
1867 struct i915_drrs drrs
;
1868 struct intel_opregion opregion
;
1869 struct intel_vbt_data vbt
;
1871 bool preserve_bios_swizzle
;
1874 struct intel_overlay
*overlay
;
1876 /* backlight registers and fields in struct intel_panel */
1877 struct mutex backlight_lock
;
1880 bool no_aux_handshake
;
1882 /* protects panel power sequencer state */
1883 struct mutex pps_mutex
;
1885 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1886 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1888 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1889 unsigned int skl_preferred_vco_freq
;
1890 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1891 unsigned int max_dotclk_freq
;
1892 unsigned int rawclk_freq
;
1893 unsigned int hpll_freq
;
1894 unsigned int czclk_freq
;
1897 unsigned int vco
, ref
;
1901 * wq - Driver workqueue for GEM.
1903 * NOTE: Work items scheduled here are not allowed to grab any modeset
1904 * locks, for otherwise the flushing done in the pageflip code will
1905 * result in deadlocks.
1907 struct workqueue_struct
*wq
;
1909 /* Display functions */
1910 struct drm_i915_display_funcs display
;
1912 /* PCH chipset type */
1913 enum intel_pch pch_type
;
1914 unsigned short pch_id
;
1916 unsigned long quirks
;
1918 enum modeset_restore modeset_restore
;
1919 struct mutex modeset_restore_lock
;
1920 struct drm_atomic_state
*modeset_restore_state
;
1921 struct drm_modeset_acquire_ctx reset_ctx
;
1923 struct list_head vm_list
; /* Global list of all address spaces */
1924 struct i915_ggtt ggtt
; /* VM representing the global address space */
1926 struct i915_gem_mm mm
;
1927 DECLARE_HASHTABLE(mm_structs
, 7);
1928 struct mutex mm_lock
;
1930 /* The hw wants to have a stable context identifier for the lifetime
1931 * of the context (for OA, PASID, faults, etc). This is limited
1932 * in execlists to 21 bits.
1934 struct ida context_hw_ida
;
1935 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1937 /* Kernel Modesetting */
1939 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1940 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1941 wait_queue_head_t pending_flip_queue
;
1943 #ifdef CONFIG_DEBUG_FS
1944 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1947 /* dpll and cdclk state is protected by connection_mutex */
1948 int num_shared_dpll
;
1949 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1950 const struct intel_dpll_mgr
*dpll_mgr
;
1953 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1954 * Must be global rather than per dpll, because on some platforms
1955 * plls share registers.
1957 struct mutex dpll_lock
;
1959 unsigned int active_crtcs
;
1960 unsigned int min_pixclk
[I915_MAX_PIPES
];
1962 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1964 struct i915_workarounds workarounds
;
1966 struct i915_frontbuffer_tracking fb_tracking
;
1970 bool mchbar_need_disable
;
1972 struct intel_l3_parity l3_parity
;
1974 /* Cannot be determined by PCIID. You must always read a register. */
1977 /* gen6+ rps state */
1978 struct intel_gen6_power_mgmt rps
;
1980 /* ilk-only ips/rps state. Everything in here is protected by the global
1981 * mchdev_lock in intel_pm.c */
1982 struct intel_ilk_power_mgmt ips
;
1984 struct i915_power_domains power_domains
;
1986 struct i915_psr psr
;
1988 struct i915_gpu_error gpu_error
;
1990 struct drm_i915_gem_object
*vlv_pctx
;
1992 #ifdef CONFIG_DRM_FBDEV_EMULATION
1993 /* list of fbdev register on this device */
1994 struct intel_fbdev
*fbdev
;
1995 struct work_struct fbdev_suspend_work
;
1998 struct drm_property
*broadcast_rgb_property
;
1999 struct drm_property
*force_audio_property
;
2001 /* hda/i915 audio component */
2002 struct i915_audio_component
*audio_component
;
2003 bool audio_component_registered
;
2005 * av_mutex - mutex for audio/video sync
2008 struct mutex av_mutex
;
2010 uint32_t hw_context_size
;
2011 struct list_head context_list
;
2015 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2016 u32 chv_phy_control
;
2018 * Shadows for CHV DPLL_MD regs to keep the state
2019 * checker somewhat working in the presence hardware
2020 * crappiness (can't read out DPLL_MD for pipes B & C).
2022 u32 chv_dpll_md
[I915_MAX_PIPES
];
2026 bool suspended_to_idle
;
2027 struct i915_suspend_saved_registers regfile
;
2028 struct vlv_s0ix_state vlv_s0ix_state
;
2031 I915_SAGV_UNKNOWN
= 0,
2034 I915_SAGV_NOT_CONTROLLED
2039 * Raw watermark latency values:
2040 * in 0.1us units for WM0,
2041 * in 0.5us units for WM1+.
2044 uint16_t pri_latency
[5];
2046 uint16_t spr_latency
[5];
2048 uint16_t cur_latency
[5];
2050 * Raw watermark memory latency values
2051 * for SKL for all 8 levels
2054 uint16_t skl_latency
[8];
2057 * The skl_wm_values structure is a bit too big for stack
2058 * allocation, so we keep the staging struct where we store
2059 * intermediate results here instead.
2061 struct skl_wm_values skl_results
;
2063 /* current hardware state */
2065 struct ilk_wm_values hw
;
2066 struct skl_wm_values skl_hw
;
2067 struct vlv_wm_values vlv
;
2073 * Should be held around atomic WM register writing; also
2074 * protects * intel_crtc->wm.active and
2075 * cstate->wm.need_postvbl_update.
2077 struct mutex wm_mutex
;
2080 * Set during HW readout of watermarks/DDB. Some platforms
2081 * need to know when we're still using BIOS-provided values
2082 * (which we don't fully trust).
2084 bool distrust_bios_wm
;
2087 struct i915_runtime_pm pm
;
2089 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2091 void (*resume
)(struct drm_i915_private
*);
2092 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2094 struct list_head timelines
;
2095 struct i915_gem_timeline global_timeline
;
2096 u32 active_requests
;
2099 * Is the GPU currently considered idle, or busy executing
2100 * userspace requests? Whilst idle, we allow runtime power
2101 * management to power down the hardware and display clocks.
2102 * In order to reduce the effect on performance, there
2103 * is a slight delay before we do so.
2108 * We leave the user IRQ off as much as possible,
2109 * but this means that requests will finish and never
2110 * be retired once the system goes idle. Set a timer to
2111 * fire periodically while the ring is running. When it
2112 * fires, go retire requests.
2114 struct delayed_work retire_work
;
2117 * When we detect an idle GPU, we want to turn on
2118 * powersaving features. So once we see that there
2119 * are no more requests outstanding and no more
2120 * arrive within a small period of time, we fire
2121 * off the idle_work.
2123 struct delayed_work idle_work
;
2125 ktime_t last_init_time
;
2128 /* perform PHY state sanity checks? */
2129 bool chv_phy_assert
[2];
2131 /* Used to save the pipe-to-encoder mapping for audio */
2132 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2135 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2136 * will be rejected. Instead look for a better place.
2140 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2142 return container_of(dev
, struct drm_i915_private
, drm
);
2145 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2147 return to_i915(dev_get_drvdata(kdev
));
2150 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2152 return container_of(guc
, struct drm_i915_private
, guc
);
2155 /* Simple iterator over all initialised engines */
2156 #define for_each_engine(engine__, dev_priv__, id__) \
2158 (id__) < I915_NUM_ENGINES; \
2160 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2162 #define __mask_next_bit(mask) ({ \
2163 int __idx = ffs(mask) - 1; \
2164 mask &= ~BIT(__idx); \
2168 /* Iterator over subset of engines selected by mask */
2169 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2170 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2171 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2173 enum hdmi_force_audio
{
2174 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2175 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2176 HDMI_AUDIO_AUTO
, /* trust EDID */
2177 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2180 #define I915_GTT_OFFSET_NONE ((u32)-1)
2182 struct drm_i915_gem_object_ops
{
2184 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2185 #define I915_GEM_OBJECT_IS_SHRINKABLE 0x2
2187 /* Interface between the GEM object and its backing storage.
2188 * get_pages() is called once prior to the use of the associated set
2189 * of pages before to binding them into the GTT, and put_pages() is
2190 * called after we no longer need them. As we expect there to be
2191 * associated cost with migrating pages between the backing storage
2192 * and making them available for the GPU (e.g. clflush), we may hold
2193 * onto the pages after they are no longer referenced by the GPU
2194 * in case they may be used again shortly (for example migrating the
2195 * pages to a different memory domain within the GTT). put_pages()
2196 * will therefore most likely be called when the object itself is
2197 * being released or under memory pressure (where we attempt to
2198 * reap pages for the shrinker).
2200 struct sg_table
*(*get_pages
)(struct drm_i915_gem_object
*);
2201 void (*put_pages
)(struct drm_i915_gem_object
*, struct sg_table
*);
2203 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2204 void (*release
)(struct drm_i915_gem_object
*);
2208 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2209 * considered to be the frontbuffer for the given plane interface-wise. This
2210 * doesn't mean that the hw necessarily already scans it out, but that any
2211 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2213 * We have one bit per pipe and per scanout plane type.
2215 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2216 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2217 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2218 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2219 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2220 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2221 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2222 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2223 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2224 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2225 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2226 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2228 struct drm_i915_gem_object
{
2229 struct drm_gem_object base
;
2231 const struct drm_i915_gem_object_ops
*ops
;
2233 /** List of VMAs backed by this object */
2234 struct list_head vma_list
;
2235 struct rb_root vma_tree
;
2237 /** Stolen memory for this object, instead of being backed by shmem. */
2238 struct drm_mm_node
*stolen
;
2239 struct list_head global_link
;
2241 struct rcu_head rcu
;
2242 struct llist_node freed
;
2246 * Whether the object is currently in the GGTT mmap.
2248 struct list_head userfault_link
;
2250 /** Used in execbuf to temporarily hold a ref */
2251 struct list_head obj_exec_link
;
2253 struct list_head batch_pool_link
;
2255 unsigned long flags
;
2258 * Have we taken a reference for the object for incomplete GPU
2261 #define I915_BO_ACTIVE_REF 0
2264 * Is the object to be mapped as read-only to the GPU
2265 * Only honoured if hardware has relevant pte bit
2267 unsigned long gt_ro
:1;
2268 unsigned int cache_level
:3;
2269 unsigned int cache_dirty
:1;
2271 atomic_t frontbuffer_bits
;
2272 unsigned int frontbuffer_ggtt_origin
; /* write once */
2274 /** Current tiling stride for the object, if it's tiled. */
2275 unsigned int tiling_and_stride
;
2276 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2277 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2278 #define STRIDE_MASK (~TILING_MASK)
2280 /** Count of VMA actually bound by this object */
2281 unsigned int bind_count
;
2282 unsigned int active_count
;
2283 unsigned int pin_display
;
2286 struct mutex lock
; /* protects the pages and their use */
2287 atomic_t pages_pin_count
;
2289 struct sg_table
*pages
;
2292 struct i915_gem_object_page_iter
{
2293 struct scatterlist
*sg_pos
;
2294 unsigned int sg_idx
; /* in pages, but 32bit eek! */
2296 struct radix_tree_root radix
;
2297 struct mutex lock
; /* protects this cache */
2301 * Advice: are the backing pages purgeable?
2303 unsigned int madv
:2;
2306 * This is set if the object has been written to since the
2307 * pages were last acquired.
2312 * This is set if the object has been pinned due to unknown
2318 /** Breadcrumb of last rendering to the buffer.
2319 * There can only be one writer, but we allow for multiple readers.
2320 * If there is a writer that necessarily implies that all other
2321 * read requests are complete - but we may only be lazily clearing
2322 * the read requests. A read request is naturally the most recent
2323 * request on a ring, so we may have two different write and read
2324 * requests on one ring where the write request is older than the
2325 * read request. This allows for the CPU to read from an active
2326 * buffer by only waiting for the write to complete.
2328 struct reservation_object
*resv
;
2330 /** References from framebuffers, locks out tiling changes. */
2331 unsigned long framebuffer_references
;
2333 /** Record of address bit 17 of each page at last unbind. */
2334 unsigned long *bit_17
;
2336 struct i915_gem_userptr
{
2338 unsigned read_only
:1;
2340 struct i915_mm_struct
*mm
;
2341 struct i915_mmu_object
*mmu_object
;
2342 struct work_struct
*work
;
2345 /** for phys allocated objects */
2346 struct drm_dma_handle
*phys_handle
;
2348 struct reservation_object __builtin_resv
;
2351 static inline struct drm_i915_gem_object
*
2352 to_intel_bo(struct drm_gem_object
*gem
)
2354 /* Assert that to_intel_bo(NULL) == NULL */
2355 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object
, base
));
2357 return container_of(gem
, struct drm_i915_gem_object
, base
);
2361 * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
2362 * @filp: DRM file private date
2363 * @handle: userspace handle
2367 * A pointer to the object named by the handle if such exists on @filp, NULL
2368 * otherwise. This object is only valid whilst under the RCU read lock, and
2369 * note carefully the object may be in the process of being destroyed.
2371 static inline struct drm_i915_gem_object
*
2372 i915_gem_object_lookup_rcu(struct drm_file
*file
, u32 handle
)
2374 #ifdef CONFIG_LOCKDEP
2375 WARN_ON(debug_locks
&& !lock_is_held(&rcu_lock_map
));
2377 return idr_find(&file
->object_idr
, handle
);
2380 static inline struct drm_i915_gem_object
*
2381 i915_gem_object_lookup(struct drm_file
*file
, u32 handle
)
2383 struct drm_i915_gem_object
*obj
;
2386 obj
= i915_gem_object_lookup_rcu(file
, handle
);
2387 if (obj
&& !kref_get_unless_zero(&obj
->base
.refcount
))
2395 extern struct drm_gem_object
*
2396 drm_gem_object_lookup(struct drm_file
*file
, u32 handle
);
2398 __attribute__((nonnull
))
2399 static inline struct drm_i915_gem_object
*
2400 i915_gem_object_get(struct drm_i915_gem_object
*obj
)
2402 drm_gem_object_reference(&obj
->base
);
2407 extern void drm_gem_object_reference(struct drm_gem_object
*);
2409 __attribute__((nonnull
))
2411 i915_gem_object_put(struct drm_i915_gem_object
*obj
)
2413 __drm_gem_object_unreference(&obj
->base
);
2417 extern void drm_gem_object_unreference(struct drm_gem_object
*);
2420 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object
*);
2423 i915_gem_object_is_dead(const struct drm_i915_gem_object
*obj
)
2425 return atomic_read(&obj
->base
.refcount
.refcount
) == 0;
2429 i915_gem_object_has_struct_page(const struct drm_i915_gem_object
*obj
)
2431 return obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
;
2435 i915_gem_object_is_shrinkable(const struct drm_i915_gem_object
*obj
)
2437 return obj
->ops
->flags
& I915_GEM_OBJECT_IS_SHRINKABLE
;
2441 i915_gem_object_is_active(const struct drm_i915_gem_object
*obj
)
2443 return obj
->active_count
;
2447 i915_gem_object_has_active_reference(const struct drm_i915_gem_object
*obj
)
2449 return test_bit(I915_BO_ACTIVE_REF
, &obj
->flags
);
2453 i915_gem_object_set_active_reference(struct drm_i915_gem_object
*obj
)
2455 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2456 __set_bit(I915_BO_ACTIVE_REF
, &obj
->flags
);
2460 i915_gem_object_clear_active_reference(struct drm_i915_gem_object
*obj
)
2462 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2463 __clear_bit(I915_BO_ACTIVE_REF
, &obj
->flags
);
2466 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object
*obj
);
2468 static inline unsigned int
2469 i915_gem_object_get_tiling(struct drm_i915_gem_object
*obj
)
2471 return obj
->tiling_and_stride
& TILING_MASK
;
2475 i915_gem_object_is_tiled(struct drm_i915_gem_object
*obj
)
2477 return i915_gem_object_get_tiling(obj
) != I915_TILING_NONE
;
2480 static inline unsigned int
2481 i915_gem_object_get_stride(struct drm_i915_gem_object
*obj
)
2483 return obj
->tiling_and_stride
& STRIDE_MASK
;
2486 static inline struct intel_engine_cs
*
2487 i915_gem_object_last_write_engine(struct drm_i915_gem_object
*obj
)
2489 struct intel_engine_cs
*engine
= NULL
;
2490 struct dma_fence
*fence
;
2493 fence
= reservation_object_get_excl_rcu(obj
->resv
);
2496 if (fence
&& dma_fence_is_i915(fence
) && !dma_fence_is_signaled(fence
))
2497 engine
= to_request(fence
)->engine
;
2498 dma_fence_put(fence
);
2503 static inline struct i915_vma
*i915_vma_get(struct i915_vma
*vma
)
2505 i915_gem_object_get(vma
->obj
);
2509 static inline void i915_vma_put(struct i915_vma
*vma
)
2511 i915_gem_object_put(vma
->obj
);
2515 * Optimised SGL iterator for GEM objects
2517 static __always_inline
struct sgt_iter
{
2518 struct scatterlist
*sgp
;
2525 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2526 struct sgt_iter s
= { .sgp
= sgl
};
2529 s
.max
= s
.curr
= s
.sgp
->offset
;
2530 s
.max
+= s
.sgp
->length
;
2532 s
.dma
= sg_dma_address(s
.sgp
);
2534 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2540 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2543 if (unlikely(sg_is_chain(sg
)))
2544 sg
= sg_chain_ptr(sg
);
2549 * __sg_next - return the next scatterlist entry in a list
2550 * @sg: The current sg entry
2553 * If the entry is the last, return NULL; otherwise, step to the next
2554 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2555 * otherwise just return the pointer to the current element.
2557 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2559 #ifdef CONFIG_DEBUG_SG
2560 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2562 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2566 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2567 * @__dmap: DMA address (output)
2568 * @__iter: 'struct sgt_iter' (iterator state, internal)
2569 * @__sgt: sg_table to iterate over (input)
2571 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2572 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2573 ((__dmap) = (__iter).dma + (__iter).curr); \
2574 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2575 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2578 * for_each_sgt_page - iterate over the pages of the given sg_table
2579 * @__pp: page pointer (output)
2580 * @__iter: 'struct sgt_iter' (iterator state, internal)
2581 * @__sgt: sg_table to iterate over (input)
2583 #define for_each_sgt_page(__pp, __iter, __sgt) \
2584 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2585 ((__pp) = (__iter).pfn == 0 ? NULL : \
2586 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2587 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2588 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2591 * A command that requires special handling by the command parser.
2593 struct drm_i915_cmd_descriptor
{
2595 * Flags describing how the command parser processes the command.
2597 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2598 * a length mask if not set
2599 * CMD_DESC_SKIP: The command is allowed but does not follow the
2600 * standard length encoding for the opcode range in
2602 * CMD_DESC_REJECT: The command is never allowed
2603 * CMD_DESC_REGISTER: The command should be checked against the
2604 * register whitelist for the appropriate ring
2605 * CMD_DESC_MASTER: The command is allowed if the submitting process
2609 #define CMD_DESC_FIXED (1<<0)
2610 #define CMD_DESC_SKIP (1<<1)
2611 #define CMD_DESC_REJECT (1<<2)
2612 #define CMD_DESC_REGISTER (1<<3)
2613 #define CMD_DESC_BITMASK (1<<4)
2614 #define CMD_DESC_MASTER (1<<5)
2617 * The command's unique identification bits and the bitmask to get them.
2618 * This isn't strictly the opcode field as defined in the spec and may
2619 * also include type, subtype, and/or subop fields.
2627 * The command's length. The command is either fixed length (i.e. does
2628 * not include a length field) or has a length field mask. The flag
2629 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2630 * a length mask. All command entries in a command table must include
2631 * length information.
2639 * Describes where to find a register address in the command to check
2640 * against the ring's register whitelist. Only valid if flags has the
2641 * CMD_DESC_REGISTER bit set.
2643 * A non-zero step value implies that the command may access multiple
2644 * registers in sequence (e.g. LRI), in that case step gives the
2645 * distance in dwords between individual offset fields.
2653 #define MAX_CMD_DESC_BITMASKS 3
2655 * Describes command checks where a particular dword is masked and
2656 * compared against an expected value. If the command does not match
2657 * the expected value, the parser rejects it. Only valid if flags has
2658 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2661 * If the check specifies a non-zero condition_mask then the parser
2662 * only performs the check when the bits specified by condition_mask
2669 u32 condition_offset
;
2671 } bits
[MAX_CMD_DESC_BITMASKS
];
2675 * A table of commands requiring special handling by the command parser.
2677 * Each engine has an array of tables. Each table consists of an array of
2678 * command descriptors, which must be sorted with command opcodes in
2681 struct drm_i915_cmd_table
{
2682 const struct drm_i915_cmd_descriptor
*table
;
2686 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2687 #define __I915__(p) ({ \
2688 struct drm_i915_private *__p; \
2689 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2690 __p = (struct drm_i915_private *)p; \
2691 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2692 __p = to_i915((struct drm_device *)p); \
2697 #define INTEL_INFO(p) (&__I915__(p)->info)
2699 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2700 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2702 #define REVID_FOREVER 0xff
2703 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2705 #define GEN_FOREVER (0)
2707 * Returns true if Gen is in inclusive range [Start, End].
2709 * Use GEN_FOREVER for unbound start and or end.
2711 #define IS_GEN(dev_priv, s, e) ({ \
2712 unsigned int __s = (s), __e = (e); \
2713 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2714 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2715 if ((__s) != GEN_FOREVER) \
2717 if ((__e) == GEN_FOREVER) \
2718 __e = BITS_PER_LONG - 1; \
2721 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2725 * Return true if revision is in range [since,until] inclusive.
2727 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2729 #define IS_REVID(p, since, until) \
2730 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2732 #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
2733 #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
2734 #define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x)
2735 #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
2736 #define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g)
2737 #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
2738 #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
2739 #define IS_I945GM(dev_priv) ((dev_priv)->info.is_i945gm)
2740 #define IS_BROADWATER(dev_priv) ((dev_priv)->info.is_broadwater)
2741 #define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
2742 #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
2743 #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
2744 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2745 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2746 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
2747 #define IS_G33(dev_priv) ((dev_priv)->info.is_g33)
2748 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2749 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
2750 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2751 INTEL_DEVID(dev_priv) == 0x0152 || \
2752 INTEL_DEVID(dev_priv) == 0x015a)
2753 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
2754 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
2755 #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
2756 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
2757 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
2758 #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
2759 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
2760 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2761 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2762 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2763 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2764 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2765 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2766 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2767 /* ULX machines are also considered ULT. */
2768 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2769 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2770 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2771 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2772 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2773 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2774 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2775 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2776 /* ULX machines are also considered ULT. */
2777 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2778 INTEL_DEVID(dev_priv) == 0x0A1E)
2779 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2780 INTEL_DEVID(dev_priv) == 0x1913 || \
2781 INTEL_DEVID(dev_priv) == 0x1916 || \
2782 INTEL_DEVID(dev_priv) == 0x1921 || \
2783 INTEL_DEVID(dev_priv) == 0x1926)
2784 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2785 INTEL_DEVID(dev_priv) == 0x1915 || \
2786 INTEL_DEVID(dev_priv) == 0x191E)
2787 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2788 INTEL_DEVID(dev_priv) == 0x5913 || \
2789 INTEL_DEVID(dev_priv) == 0x5916 || \
2790 INTEL_DEVID(dev_priv) == 0x5921 || \
2791 INTEL_DEVID(dev_priv) == 0x5926)
2792 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2793 INTEL_DEVID(dev_priv) == 0x5915 || \
2794 INTEL_DEVID(dev_priv) == 0x591E)
2795 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2796 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2797 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2798 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2800 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2802 #define SKL_REVID_A0 0x0
2803 #define SKL_REVID_B0 0x1
2804 #define SKL_REVID_C0 0x2
2805 #define SKL_REVID_D0 0x3
2806 #define SKL_REVID_E0 0x4
2807 #define SKL_REVID_F0 0x5
2808 #define SKL_REVID_G0 0x6
2809 #define SKL_REVID_H0 0x7
2811 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2813 #define BXT_REVID_A0 0x0
2814 #define BXT_REVID_A1 0x1
2815 #define BXT_REVID_B0 0x3
2816 #define BXT_REVID_C0 0x9
2818 #define IS_BXT_REVID(dev_priv, since, until) \
2819 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2821 #define KBL_REVID_A0 0x0
2822 #define KBL_REVID_B0 0x1
2823 #define KBL_REVID_C0 0x2
2824 #define KBL_REVID_D0 0x3
2825 #define KBL_REVID_E0 0x4
2827 #define IS_KBL_REVID(dev_priv, since, until) \
2828 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2831 * The genX designation typically refers to the render engine, so render
2832 * capability related checks should use IS_GEN, while display and other checks
2833 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2836 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2837 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2838 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2839 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2840 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2841 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2842 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2843 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2845 #define ENGINE_MASK(id) BIT(id)
2846 #define RENDER_RING ENGINE_MASK(RCS)
2847 #define BSD_RING ENGINE_MASK(VCS)
2848 #define BLT_RING ENGINE_MASK(BCS)
2849 #define VEBOX_RING ENGINE_MASK(VECS)
2850 #define BSD2_RING ENGINE_MASK(VCS2)
2851 #define ALL_ENGINES (~0)
2853 #define HAS_ENGINE(dev_priv, id) \
2854 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2856 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2857 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2858 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2859 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2861 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2862 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2863 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2864 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2865 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2866 #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
2868 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
2869 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts)
2870 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2871 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2872 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2874 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2875 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2877 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2878 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
2880 /* WaRsDisableCoarsePowerGating:skl,bxt */
2881 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2882 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2883 IS_SKL_GT3(dev_priv) || \
2884 IS_SKL_GT4(dev_priv))
2887 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2888 * even when in MSI mode. This results in spurious interrupt warnings if the
2889 * legacy irq no. is shared with another device. The kernel then disables that
2890 * interrupt source and so prevents the other device from working properly.
2892 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2893 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
2895 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2896 * rows, which changed the alignment requirements and fence programming.
2898 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2899 !(IS_I915G(dev_priv) || \
2900 IS_I915GM(dev_priv)))
2901 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2902 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2904 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2905 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2906 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2908 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2910 #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
2912 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2913 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2914 #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
2915 #define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
2916 #define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p)
2918 #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
2920 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2921 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2924 * For now, anything with a GuC requires uCode loading, and then supports
2925 * command submission once loaded. But these are logically independent
2926 * properties, so we have separate macros to test them.
2928 #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
2929 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2930 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2932 #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
2934 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2936 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2937 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2938 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2939 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2940 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2941 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2942 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2943 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2944 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2945 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2946 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2947 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2949 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2950 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2951 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2952 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2953 #define HAS_PCH_LPT_LP(dev_priv) \
2954 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2955 #define HAS_PCH_LPT_H(dev_priv) \
2956 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2957 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2958 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2959 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2960 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2962 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2964 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2966 /* DPF == dynamic parity feature */
2967 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2968 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2969 2 : HAS_L3_DPF(dev_priv))
2971 #define GT_FREQUENCY_MULTIPLIER 50
2972 #define GEN9_FREQ_SCALER 3
2974 #include "i915_trace.h"
2976 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2978 #ifdef CONFIG_INTEL_IOMMU
2979 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2985 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2986 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2988 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2991 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2995 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2996 const char *fmt
, ...);
2998 #define i915_report_error(dev_priv, fmt, ...) \
2999 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3001 #ifdef CONFIG_COMPAT
3002 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
3005 #define i915_compat_ioctl NULL
3007 extern const struct dev_pm_ops i915_pm_ops
;
3009 extern int i915_driver_load(struct pci_dev
*pdev
,
3010 const struct pci_device_id
*ent
);
3011 extern void i915_driver_unload(struct drm_device
*dev
);
3012 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3013 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3014 extern void i915_reset(struct drm_i915_private
*dev_priv
);
3015 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3016 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3017 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
3018 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3019 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3020 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3021 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3022 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3024 /* intel_hotplug.c */
3025 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3026 u32 pin_mask
, u32 long_mask
);
3027 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3028 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3029 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3030 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
3031 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3032 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3035 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3037 unsigned long delay
;
3039 if (unlikely(!i915
.enable_hangcheck
))
3042 /* Don't continually defer the hangcheck so that it is always run at
3043 * least once after work has been scheduled on any ring. Otherwise,
3044 * we will ignore a hung ring if a second ring is kept busy.
3047 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3048 queue_delayed_work(system_long_wq
,
3049 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3053 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3055 const char *fmt
, ...);
3057 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3058 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3059 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3061 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
3062 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
3063 bool restore_forcewake
);
3064 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
3065 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
3066 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
3067 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
3068 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
3070 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
3071 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
3072 enum forcewake_domains domains
);
3073 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
3074 enum forcewake_domains domains
);
3075 /* Like above but the caller must manage the uncore.lock itself.
3076 * Must be used with I915_READ_FW and friends.
3078 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
3079 enum forcewake_domains domains
);
3080 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
3081 enum forcewake_domains domains
);
3082 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
3084 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
3086 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
3090 const unsigned long timeout_ms
);
3091 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
3095 const unsigned long timeout_ms
);
3097 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3099 return dev_priv
->gvt
;
3102 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3104 return dev_priv
->vgpu
.active
;
3108 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3112 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3115 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3116 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3117 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3120 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3121 uint32_t interrupt_mask
,
3122 uint32_t enabled_irq_mask
);
3124 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3126 ilk_update_display_irq(dev_priv
, bits
, bits
);
3129 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3131 ilk_update_display_irq(dev_priv
, bits
, 0);
3133 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3135 uint32_t interrupt_mask
,
3136 uint32_t enabled_irq_mask
);
3137 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3138 enum pipe pipe
, uint32_t bits
)
3140 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3142 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3143 enum pipe pipe
, uint32_t bits
)
3145 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3147 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3148 uint32_t interrupt_mask
,
3149 uint32_t enabled_irq_mask
);
3151 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3153 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3156 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3158 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3162 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3163 struct drm_file
*file_priv
);
3164 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3165 struct drm_file
*file_priv
);
3166 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3167 struct drm_file
*file_priv
);
3168 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3169 struct drm_file
*file_priv
);
3170 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3171 struct drm_file
*file_priv
);
3172 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3173 struct drm_file
*file_priv
);
3174 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3175 struct drm_file
*file_priv
);
3176 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3177 struct drm_file
*file_priv
);
3178 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3179 struct drm_file
*file_priv
);
3180 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3181 struct drm_file
*file_priv
);
3182 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3183 struct drm_file
*file
);
3184 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3185 struct drm_file
*file
);
3186 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3187 struct drm_file
*file_priv
);
3188 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3189 struct drm_file
*file_priv
);
3190 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
3191 struct drm_file
*file_priv
);
3192 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
3193 struct drm_file
*file_priv
);
3194 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3195 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3196 struct drm_file
*file
);
3197 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3198 struct drm_file
*file_priv
);
3199 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3200 struct drm_file
*file_priv
);
3201 int i915_gem_load_init(struct drm_device
*dev
);
3202 void i915_gem_load_cleanup(struct drm_device
*dev
);
3203 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3204 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3205 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3207 void *i915_gem_object_alloc(struct drm_device
*dev
);
3208 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3209 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3210 const struct drm_i915_gem_object_ops
*ops
);
3211 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3213 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3214 struct drm_device
*dev
, const void *data
, size_t size
);
3215 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3216 void i915_gem_free_object(struct drm_gem_object
*obj
);
3218 struct i915_vma
* __must_check
3219 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3220 const struct i915_ggtt_view
*view
,
3225 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3227 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3228 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3229 void i915_vma_close(struct i915_vma
*vma
);
3230 void i915_vma_destroy(struct i915_vma
*vma
);
3232 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3233 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3235 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3237 static inline int __sg_page_count(const struct scatterlist
*sg
)
3239 return sg
->length
>> PAGE_SHIFT
;
3242 struct scatterlist
*
3243 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3244 unsigned int n
, unsigned int *offset
);
3247 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3251 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3255 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3258 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3259 struct sg_table
*pages
);
3260 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3262 static inline int __must_check
3263 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3265 might_lock(&obj
->mm
.lock
);
3267 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3270 return __i915_gem_object_get_pages(obj
);
3274 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3276 GEM_BUG_ON(!obj
->mm
.pages
);
3278 atomic_inc(&obj
->mm
.pages_pin_count
);
3282 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3284 return atomic_read(&obj
->mm
.pages_pin_count
);
3288 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3290 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3291 GEM_BUG_ON(!obj
->mm
.pages
);
3293 atomic_dec(&obj
->mm
.pages_pin_count
);
3294 GEM_BUG_ON(atomic_read(&obj
->mm
.pages_pin_count
) < obj
->bind_count
);
3298 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3300 __i915_gem_object_unpin_pages(obj
);
3303 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3308 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3309 enum i915_mm_subclass subclass
);
3310 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3312 enum i915_map_type
{
3318 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3319 * @obj - the object to map into kernel address space
3320 * @type - the type of mapping, used to select pgprot_t
3322 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3323 * pages and then returns a contiguous mapping of the backing storage into
3324 * the kernel address space. Based on the @type of mapping, the PTE will be
3325 * set to either WriteBack or WriteCombine (via pgprot_t).
3327 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3328 * mapping is no longer required.
3330 * Returns the pointer through which to access the mapped object, or an
3331 * ERR_PTR() on error.
3333 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3334 enum i915_map_type type
);
3337 * i915_gem_object_unpin_map - releases an earlier mapping
3338 * @obj - the object to unmap
3340 * After pinning the object and mapping its pages, once you are finished
3341 * with your access, call i915_gem_object_unpin_map() to release the pin
3342 * upon the mapping. Once the pin count reaches zero, that mapping may be
3345 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3347 i915_gem_object_unpin_pages(obj
);
3350 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3351 unsigned int *needs_clflush
);
3352 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3353 unsigned int *needs_clflush
);
3354 #define CLFLUSH_BEFORE 0x1
3355 #define CLFLUSH_AFTER 0x2
3356 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3359 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3361 i915_gem_object_unpin_pages(obj
);
3364 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3365 void i915_vma_move_to_active(struct i915_vma
*vma
,
3366 struct drm_i915_gem_request
*req
,
3367 unsigned int flags
);
3368 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3369 struct drm_device
*dev
,
3370 struct drm_mode_create_dumb
*args
);
3371 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3372 uint32_t handle
, uint64_t *offset
);
3373 int i915_gem_mmap_gtt_version(void);
3375 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3376 struct drm_i915_gem_object
*new,
3377 unsigned frontbuffer_bits
);
3379 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3381 struct drm_i915_gem_request
*
3382 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3384 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3386 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3388 return unlikely(test_bit(I915_RESET_IN_PROGRESS
, &error
->flags
));
3391 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3393 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3396 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3398 return i915_reset_in_progress(error
) | i915_terminally_wedged(error
);
3401 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3403 return READ_ONCE(error
->reset_count
);
3406 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3407 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3408 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3409 int __must_check
i915_gem_init(struct drm_device
*dev
);
3410 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3411 void i915_gem_init_swizzling(struct drm_device
*dev
);
3412 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3413 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3414 unsigned int flags
);
3415 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3416 void i915_gem_resume(struct drm_device
*dev
);
3417 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3418 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3421 struct intel_rps_client
*rps
);
3423 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3426 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3427 struct i915_vma
* __must_check
3428 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3430 const struct i915_ggtt_view
*view
);
3431 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3432 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3434 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3435 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3437 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
, u64 size
,
3439 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
3440 int tiling_mode
, bool fenced
);
3442 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3443 enum i915_cache_level cache_level
);
3445 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3446 struct dma_buf
*dma_buf
);
3448 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3449 struct drm_gem_object
*gem_obj
, int flags
);
3452 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3453 struct i915_address_space
*vm
,
3454 const struct i915_ggtt_view
*view
);
3457 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3458 struct i915_address_space
*vm
,
3459 const struct i915_ggtt_view
*view
);
3461 static inline struct i915_hw_ppgtt
*
3462 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3464 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3467 static inline struct i915_vma
*
3468 i915_gem_object_to_ggtt(struct drm_i915_gem_object
*obj
,
3469 const struct i915_ggtt_view
*view
)
3471 return i915_gem_obj_to_vma(obj
, &to_i915(obj
->base
.dev
)->ggtt
.base
, view
);
3474 static inline unsigned long
3475 i915_gem_object_ggtt_offset(struct drm_i915_gem_object
*o
,
3476 const struct i915_ggtt_view
*view
)
3478 return i915_ggtt_offset(i915_gem_object_to_ggtt(o
, view
));
3481 /* i915_gem_fence.c */
3482 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3483 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3486 * i915_vma_pin_fence - pin fencing state
3487 * @vma: vma to pin fencing for
3489 * This pins the fencing state (whether tiled or untiled) to make sure the
3490 * vma (and its object) is ready to be used as a scanout target. Fencing
3491 * status must be synchronize first by calling i915_vma_get_fence():
3493 * The resulting fence pin reference must be released again with
3494 * i915_vma_unpin_fence().
3498 * True if the vma has a fence, false otherwise.
3501 i915_vma_pin_fence(struct i915_vma
*vma
)
3503 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3505 vma
->fence
->pin_count
++;
3512 * i915_vma_unpin_fence - unpin fencing state
3513 * @vma: vma to unpin fencing for
3515 * This releases the fence pin reference acquired through
3516 * i915_vma_pin_fence. It will handle both objects with and without an
3517 * attached fence correctly, callers do not need to distinguish this.
3520 i915_vma_unpin_fence(struct i915_vma
*vma
)
3522 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3524 GEM_BUG_ON(vma
->fence
->pin_count
<= 0);
3525 vma
->fence
->pin_count
--;
3529 void i915_gem_restore_fences(struct drm_device
*dev
);
3531 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3532 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3533 struct sg_table
*pages
);
3534 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3535 struct sg_table
*pages
);
3537 /* i915_gem_context.c */
3538 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3539 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3540 void i915_gem_context_fini(struct drm_device
*dev
);
3541 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3542 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3543 int i915_switch_context(struct drm_i915_gem_request
*req
);
3544 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
);
3546 i915_gem_context_pin_legacy(struct i915_gem_context
*ctx
,
3547 unsigned int flags
);
3548 void i915_gem_context_free(struct kref
*ctx_ref
);
3549 struct drm_i915_gem_object
*
3550 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3551 struct i915_gem_context
*
3552 i915_gem_context_create_gvt(struct drm_device
*dev
);
3554 static inline struct i915_gem_context
*
3555 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3557 struct i915_gem_context
*ctx
;
3559 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3561 ctx
= idr_find(&file_priv
->context_idr
, id
);
3563 return ERR_PTR(-ENOENT
);
3568 static inline struct i915_gem_context
*
3569 i915_gem_context_get(struct i915_gem_context
*ctx
)
3571 kref_get(&ctx
->ref
);
3575 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3577 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3578 kref_put(&ctx
->ref
, i915_gem_context_free
);
3581 static inline struct intel_timeline
*
3582 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3583 struct intel_engine_cs
*engine
)
3585 struct i915_address_space
*vm
;
3587 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3588 return &vm
->timeline
.engine
[engine
->id
];
3591 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3593 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3596 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3597 struct drm_file
*file
);
3598 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3599 struct drm_file
*file
);
3600 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3601 struct drm_file
*file_priv
);
3602 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3603 struct drm_file
*file_priv
);
3604 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3605 struct drm_file
*file
);
3607 /* i915_gem_evict.c */
3608 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3609 u64 min_size
, u64 alignment
,
3610 unsigned cache_level
,
3613 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3614 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3616 /* belongs in i915_gem_gtt.h */
3617 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3620 if (INTEL_GEN(dev_priv
) < 6)
3621 intel_gtt_chipset_flush();
3624 /* i915_gem_stolen.c */
3625 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3626 struct drm_mm_node
*node
, u64 size
,
3627 unsigned alignment
);
3628 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3629 struct drm_mm_node
*node
, u64 size
,
3630 unsigned alignment
, u64 start
,
3632 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3633 struct drm_mm_node
*node
);
3634 int i915_gem_init_stolen(struct drm_device
*dev
);
3635 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3636 struct drm_i915_gem_object
*
3637 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3638 struct drm_i915_gem_object
*
3639 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3644 /* i915_gem_internal.c */
3645 struct drm_i915_gem_object
*
3646 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3649 /* i915_gem_shrinker.c */
3650 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3651 unsigned long target
,
3653 #define I915_SHRINK_PURGEABLE 0x1
3654 #define I915_SHRINK_UNBOUND 0x2
3655 #define I915_SHRINK_BOUND 0x4
3656 #define I915_SHRINK_ACTIVE 0x8
3657 #define I915_SHRINK_VMAPS 0x10
3658 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3659 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3660 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3663 /* i915_gem_tiling.c */
3664 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3666 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3668 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3669 i915_gem_object_is_tiled(obj
);
3672 /* i915_debugfs.c */
3673 #ifdef CONFIG_DEBUG_FS
3674 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3675 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3676 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3677 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3679 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3680 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3681 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3683 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3686 /* i915_gpu_error.c */
3687 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3690 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3691 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3692 const struct i915_error_state_file_priv
*error
);
3693 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3694 struct drm_i915_private
*i915
,
3695 size_t count
, loff_t pos
);
3696 static inline void i915_error_state_buf_release(
3697 struct drm_i915_error_state_buf
*eb
)
3701 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3703 const char *error_msg
);
3704 void i915_error_state_get(struct drm_device
*dev
,
3705 struct i915_error_state_file_priv
*error_priv
);
3706 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3707 void i915_destroy_error_state(struct drm_device
*dev
);
3711 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3713 const char *error_msg
)
3717 static inline void i915_destroy_error_state(struct drm_device
*dev
)
3723 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3725 /* i915_cmd_parser.c */
3726 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3727 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3728 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3729 bool intel_engine_needs_cmd_parser(struct intel_engine_cs
*engine
);
3730 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3731 struct drm_i915_gem_object
*batch_obj
,
3732 struct drm_i915_gem_object
*shadow_batch_obj
,
3733 u32 batch_start_offset
,
3737 /* i915_suspend.c */
3738 extern int i915_save_state(struct drm_device
*dev
);
3739 extern int i915_restore_state(struct drm_device
*dev
);
3742 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3743 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3746 extern int intel_setup_gmbus(struct drm_device
*dev
);
3747 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3748 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3751 extern struct i2c_adapter
*
3752 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3753 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3754 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3755 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3757 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3759 extern void intel_i2c_reset(struct drm_device
*dev
);
3762 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3763 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3764 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3765 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3766 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3767 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3768 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3769 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3770 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3772 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3776 /* intel_opregion.c */
3778 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3779 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3780 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3781 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3782 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3784 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3786 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3788 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3789 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3790 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3791 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3795 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3800 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3804 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3812 extern void intel_register_dsm_handler(void);
3813 extern void intel_unregister_dsm_handler(void);
3815 static inline void intel_register_dsm_handler(void) { return; }
3816 static inline void intel_unregister_dsm_handler(void) { return; }
3817 #endif /* CONFIG_ACPI */
3819 /* intel_device_info.c */
3820 static inline struct intel_device_info
*
3821 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3823 return (struct intel_device_info
*)&dev_priv
->info
;
3826 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3827 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3830 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3831 extern int intel_modeset_init(struct drm_device
*dev
);
3832 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3833 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3834 extern int intel_connector_register(struct drm_connector
*);
3835 extern void intel_connector_unregister(struct drm_connector
*);
3836 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3837 extern void intel_display_resume(struct drm_device
*dev
);
3838 extern void i915_redisable_vga(struct drm_device
*dev
);
3839 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3840 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3841 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3842 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3843 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3846 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3847 struct drm_file
*file
);
3850 extern struct intel_overlay_error_state
*
3851 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3852 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3853 struct intel_overlay_error_state
*error
);
3855 extern struct intel_display_error_state
*
3856 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3857 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3858 struct drm_device
*dev
,
3859 struct intel_display_error_state
*error
);
3861 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3862 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3864 /* intel_sideband.c */
3865 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3866 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3867 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3868 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3869 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3870 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3871 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3872 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3873 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3874 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3875 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3876 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3877 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3878 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3879 enum intel_sbi_destination destination
);
3880 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3881 enum intel_sbi_destination destination
);
3882 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3883 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3885 /* intel_dpio_phy.c */
3886 void bxt_port_to_phy_channel(enum port port
,
3887 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3888 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3889 enum port port
, u32 margin
, u32 scale
,
3890 u32 enable
, u32 deemphasis
);
3891 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3892 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3893 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3895 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3897 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3898 uint8_t lane_count
);
3899 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3900 uint8_t lane_lat_optim_mask
);
3901 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3903 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3904 u32 deemph_reg_value
, u32 margin_reg_value
,
3905 bool uniq_trans_scale
);
3906 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3908 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3909 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3910 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3911 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3913 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3914 u32 demph_reg_value
, u32 preemph_reg_value
,
3915 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3916 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3917 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3918 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3920 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3921 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3923 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3924 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3926 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3927 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3928 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3929 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3931 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3932 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3933 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3934 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3936 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3937 * will be implemented using 2 32-bit writes in an arbitrary order with
3938 * an arbitrary delay between them. This can cause the hardware to
3939 * act upon the intermediate value, possibly leading to corruption and
3940 * machine death. For this reason we do not support I915_WRITE64, or
3941 * dev_priv->uncore.funcs.mmio_writeq.
3943 * When reading a 64-bit value as two 32-bit values, the delay may cause
3944 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3945 * occasionally a 64-bit register does not actualy support a full readq
3946 * and must be read using two 32-bit reads.
3948 * You have been warned.
3950 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3952 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3953 u32 upper, lower, old_upper, loop = 0; \
3954 upper = I915_READ(upper_reg); \
3956 old_upper = upper; \
3957 lower = I915_READ(lower_reg); \
3958 upper = I915_READ(upper_reg); \
3959 } while (upper != old_upper && loop++ < 2); \
3960 (u64)upper << 32 | lower; })
3962 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3963 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3965 #define __raw_read(x, s) \
3966 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3969 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3972 #define __raw_write(x, s) \
3973 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3974 i915_reg_t reg, uint##x##_t val) \
3976 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3991 /* These are untraced mmio-accessors that are only valid to be used inside
3992 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3995 * Think twice, and think again, before using these.
3997 * As an example, these accessors can possibly be used between:
3999 * spin_lock_irq(&dev_priv->uncore.lock);
4000 * intel_uncore_forcewake_get__locked();
4004 * intel_uncore_forcewake_put__locked();
4005 * spin_unlock_irq(&dev_priv->uncore.lock);
4008 * Note: some registers may not need forcewake held, so
4009 * intel_uncore_forcewake_{get,put} can be omitted, see
4010 * intel_uncore_forcewake_for_reg().
4012 * Certain architectures will die if the same cacheline is concurrently accessed
4013 * by different clients (e.g. on Ivybridge). Access to registers should
4014 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4015 * a more localised lock guarding all access to that bank of registers.
4017 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4018 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4019 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4020 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4022 /* "Broadcast RGB" property */
4023 #define INTEL_BROADCAST_RGB_AUTO 0
4024 #define INTEL_BROADCAST_RGB_FULL 1
4025 #define INTEL_BROADCAST_RGB_LIMITED 2
4027 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
4029 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4030 return VLV_VGACNTRL
;
4031 else if (INTEL_GEN(dev_priv
) >= 5)
4032 return CPU_VGACNTRL
;
4037 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
4039 unsigned long j
= msecs_to_jiffies(m
);
4041 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4044 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4046 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4049 static inline unsigned long
4050 timespec_to_jiffies_timeout(const struct timespec
*value
)
4052 unsigned long j
= timespec_to_jiffies(value
);
4054 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4058 * If you need to wait X milliseconds between events A and B, but event B
4059 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4060 * when event A happened, then just before event B you call this function and
4061 * pass the timestamp as the first argument, and X as the second argument.
4064 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4066 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4069 * Don't re-read the value of "jiffies" every time since it may change
4070 * behind our back and break the math.
4072 tmp_jiffies
= jiffies
;
4073 target_jiffies
= timestamp_jiffies
+
4074 msecs_to_jiffies_timeout(to_wait_ms
);
4076 if (time_after(target_jiffies
, tmp_jiffies
)) {
4077 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4078 while (remaining_jiffies
)
4080 schedule_timeout_uninterruptible(remaining_jiffies
);
4085 __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
4087 struct intel_engine_cs
*engine
= req
->engine
;
4089 /* Before we do the heavier coherent read of the seqno,
4090 * check the value (hopefully) in the CPU cacheline.
4092 if (__i915_gem_request_completed(req
))
4095 /* Ensure our read of the seqno is coherent so that we
4096 * do not "miss an interrupt" (i.e. if this is the last
4097 * request and the seqno write from the GPU is not visible
4098 * by the time the interrupt fires, we will see that the
4099 * request is incomplete and go back to sleep awaiting
4100 * another interrupt that will never come.)
4102 * Strictly, we only need to do this once after an interrupt,
4103 * but it is easier and safer to do it every time the waiter
4106 if (engine
->irq_seqno_barrier
&&
4107 rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
4108 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
4109 struct task_struct
*tsk
;
4111 /* The ordering of irq_posted versus applying the barrier
4112 * is crucial. The clearing of the current irq_posted must
4113 * be visible before we perform the barrier operation,
4114 * such that if a subsequent interrupt arrives, irq_posted
4115 * is reasserted and our task rewoken (which causes us to
4116 * do another __i915_request_irq_complete() immediately
4117 * and reapply the barrier). Conversely, if the clear
4118 * occurs after the barrier, then an interrupt that arrived
4119 * whilst we waited on the barrier would not trigger a
4120 * barrier on the next pass, and the read may not see the
4123 engine
->irq_seqno_barrier(engine
);
4125 /* If we consume the irq, but we are no longer the bottom-half,
4126 * the real bottom-half may not have serialised their own
4127 * seqno check with the irq-barrier (i.e. may have inspected
4128 * the seqno before we believe it coherent since they see
4129 * irq_posted == false but we are still running).
4132 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
4133 if (tsk
&& tsk
!= current
)
4134 /* Note that if the bottom-half is changed as we
4135 * are sending the wake-up, the new bottom-half will
4136 * be woken by whomever made the change. We only have
4137 * to worry about when we steal the irq-posted for
4140 wake_up_process(tsk
);
4143 if (__i915_gem_request_completed(req
))
4150 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4151 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4154 int remap_io_mapping(struct vm_area_struct
*vma
,
4155 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4156 struct io_mapping
*iomap
);
4158 #define ptr_mask_bits(ptr) ({ \
4159 unsigned long __v = (unsigned long)(ptr); \
4160 (typeof(ptr))(__v & PAGE_MASK); \
4163 #define ptr_unpack_bits(ptr, bits) ({ \
4164 unsigned long __v = (unsigned long)(ptr); \
4165 (bits) = __v & ~PAGE_MASK; \
4166 (typeof(ptr))(__v & PAGE_MASK); \
4169 #define ptr_pack_bits(ptr, bits) \
4170 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
4172 #define fetch_and_zero(ptr) ({ \
4173 typeof(*ptr) __T = *(ptr); \
4174 *(ptr) = (typeof(*ptr))0; \