1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150731"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES
= _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain
{
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
173 POWER_DOMAIN_TRANSCODER_A
,
174 POWER_DOMAIN_TRANSCODER_B
,
175 POWER_DOMAIN_TRANSCODER_C
,
176 POWER_DOMAIN_TRANSCODER_EDP
,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
185 POWER_DOMAIN_PORT_DDI_E_2_LANES
,
186 POWER_DOMAIN_PORT_DSI
,
187 POWER_DOMAIN_PORT_CRT
,
188 POWER_DOMAIN_PORT_OTHER
,
201 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
202 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
203 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
204 #define POWER_DOMAIN_TRANSCODER(tran) \
205 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
206 (tran) + POWER_DOMAIN_TRANSCODER_A)
210 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
222 #define for_each_hpd_pin(__pin) \
223 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
225 struct i915_hotplug
{
226 struct work_struct hotplug_work
;
229 unsigned long last_jiffies
;
234 HPD_MARK_DISABLED
= 2
236 } stats
[HPD_NUM_PINS
];
238 struct delayed_work reenable_work
;
240 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
243 struct work_struct dig_port_work
;
246 * if we get a HPD irq from DP and a HPD irq from non-DP
247 * the non-DP HPD could block the workqueue on a mode config
248 * mutex getting, that userspace may have taken. However
249 * userspace is waiting on the DP workqueue to run which is
250 * blocked behind the non-DP one.
252 struct workqueue_struct
*dp_wq
;
255 #define I915_GEM_GPU_DOMAINS \
256 (I915_GEM_DOMAIN_RENDER | \
257 I915_GEM_DOMAIN_SAMPLER | \
258 I915_GEM_DOMAIN_COMMAND | \
259 I915_GEM_DOMAIN_INSTRUCTION | \
260 I915_GEM_DOMAIN_VERTEX)
262 #define for_each_pipe(__dev_priv, __p) \
263 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
264 #define for_each_plane(__dev_priv, __pipe, __p) \
266 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
268 #define for_each_sprite(__dev_priv, __p, __s) \
270 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
273 #define for_each_crtc(dev, crtc) \
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
276 #define for_each_intel_plane(dev, intel_plane) \
277 list_for_each_entry(intel_plane, \
278 &dev->mode_config.plane_list, \
281 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
282 list_for_each_entry(intel_plane, \
283 &(dev)->mode_config.plane_list, \
285 if ((intel_plane)->pipe == (intel_crtc)->pipe)
287 #define for_each_intel_crtc(dev, intel_crtc) \
288 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
290 #define for_each_intel_encoder(dev, intel_encoder) \
291 list_for_each_entry(intel_encoder, \
292 &(dev)->mode_config.encoder_list, \
295 #define for_each_intel_connector(dev, intel_connector) \
296 list_for_each_entry(intel_connector, \
297 &dev->mode_config.connector_list, \
300 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
301 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
302 if ((intel_encoder)->base.crtc == (__crtc))
304 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
305 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
306 if ((intel_connector)->base.encoder == (__encoder))
308 #define for_each_power_domain(domain, mask) \
309 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
310 if ((1 << (domain)) & (mask))
312 struct drm_i915_private
;
313 struct i915_mm_struct
;
314 struct i915_mmu_object
;
316 struct drm_i915_file_private
{
317 struct drm_i915_private
*dev_priv
;
318 struct drm_file
*file
;
322 struct list_head request_list
;
323 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
324 * chosen to prevent the CPU getting more than a frame ahead of the GPU
325 * (when using lax throttling for the frontbuffer). We also use it to
326 * offer free GPU waitboosts for severely congested workloads.
328 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
330 struct idr context_idr
;
332 struct intel_rps_client
{
333 struct list_head link
;
337 struct intel_engine_cs
*bsd_ring
;
341 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
342 /* real shared dpll ids must be >= 0 */
343 DPLL_ID_PCH_PLL_A
= 0,
344 DPLL_ID_PCH_PLL_B
= 1,
349 DPLL_ID_SKL_DPLL1
= 0,
350 DPLL_ID_SKL_DPLL2
= 1,
351 DPLL_ID_SKL_DPLL3
= 2,
353 #define I915_NUM_PLLS 3
355 struct intel_dpll_hw_state
{
367 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
368 * lower part of ctrl1 and they get shifted into position when writing
369 * the register. This allows us to easily compare the state to share
373 /* HDMI only, 0 when used for DP */
374 uint32_t cfgcr1
, cfgcr2
;
377 uint32_t ebb0
, ebb4
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pll9
, pll10
,
381 struct intel_shared_dpll_config
{
382 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
383 struct intel_dpll_hw_state hw_state
;
386 struct intel_shared_dpll
{
387 struct intel_shared_dpll_config config
;
389 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
390 bool on
; /* is the PLL actually active? Disabled during modeset */
392 /* should match the index in the dev_priv->shared_dplls array */
393 enum intel_dpll_id id
;
394 /* The mode_set hook is optional and should be used together with the
395 * intel_prepare_shared_dpll function. */
396 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
397 struct intel_shared_dpll
*pll
);
398 void (*enable
)(struct drm_i915_private
*dev_priv
,
399 struct intel_shared_dpll
*pll
);
400 void (*disable
)(struct drm_i915_private
*dev_priv
,
401 struct intel_shared_dpll
*pll
);
402 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
403 struct intel_shared_dpll
*pll
,
404 struct intel_dpll_hw_state
*hw_state
);
412 /* Used by dp and fdi links */
413 struct intel_link_m_n
{
421 void intel_link_compute_m_n(int bpp
, int nlanes
,
422 int pixel_clock
, int link_clock
,
423 struct intel_link_m_n
*m_n
);
425 /* Interface history:
428 * 1.2: Add Power Management
429 * 1.3: Add vblank support
430 * 1.4: Fix cmdbuffer path, add heap destroy
431 * 1.5: Add vblank pipe configuration
432 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
433 * - Support vertical blank on secondary display pipe
435 #define DRIVER_MAJOR 1
436 #define DRIVER_MINOR 6
437 #define DRIVER_PATCHLEVEL 0
439 #define WATCH_LISTS 0
441 struct opregion_header
;
442 struct opregion_acpi
;
443 struct opregion_swsci
;
444 struct opregion_asle
;
446 struct intel_opregion
{
447 struct opregion_header __iomem
*header
;
448 struct opregion_acpi __iomem
*acpi
;
449 struct opregion_swsci __iomem
*swsci
;
450 u32 swsci_gbda_sub_functions
;
451 u32 swsci_sbcb_sub_functions
;
452 struct opregion_asle __iomem
*asle
;
454 u32 __iomem
*lid_state
;
455 struct work_struct asle_work
;
457 #define OPREGION_SIZE (8*1024)
459 struct intel_overlay
;
460 struct intel_overlay_error_state
;
462 #define I915_FENCE_REG_NONE -1
463 #define I915_MAX_NUM_FENCES 32
464 /* 32 fences + sign bit for FENCE_REG_NONE */
465 #define I915_MAX_NUM_FENCE_BITS 6
467 struct drm_i915_fence_reg
{
468 struct list_head lru_list
;
469 struct drm_i915_gem_object
*obj
;
473 struct sdvo_device_mapping
{
482 struct intel_display_error_state
;
484 struct drm_i915_error_state
{
493 /* Generic register state */
501 u32 error
; /* gen6+ */
502 u32 err_int
; /* gen7 */
503 u32 fault_data0
; /* gen8, gen9 */
504 u32 fault_data1
; /* gen8, gen9 */
510 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
511 u64 fence
[I915_MAX_NUM_FENCES
];
512 struct intel_overlay_error_state
*overlay
;
513 struct intel_display_error_state
*display
;
514 struct drm_i915_error_object
*semaphore_obj
;
516 struct drm_i915_error_ring
{
518 /* Software tracked state */
521 enum intel_ring_hangcheck_action hangcheck_action
;
524 /* our own tracking of ring head and tail */
528 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
547 u32 rc_psmi
; /* sleep state */
548 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
550 struct drm_i915_error_object
{
554 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
556 struct drm_i915_error_request
{
571 char comm
[TASK_COMM_LEN
];
572 } ring
[I915_NUM_RINGS
];
574 struct drm_i915_error_buffer
{
577 u32 rseqno
[I915_NUM_RINGS
], wseqno
;
581 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
589 } **active_bo
, **pinned_bo
;
591 u32
*active_bo_count
, *pinned_bo_count
;
595 struct intel_connector
;
596 struct intel_encoder
;
597 struct intel_crtc_state
;
598 struct intel_initial_plane_config
;
603 struct drm_i915_display_funcs
{
604 int (*get_display_clock_speed
)(struct drm_device
*dev
);
605 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
607 * find_dpll() - Find the best values for the PLL
608 * @limit: limits for the PLL
609 * @crtc: current CRTC
610 * @target: target frequency in kHz
611 * @refclk: reference clock frequency in kHz
612 * @match_clock: if provided, @best_clock P divider must
613 * match the P divider from @match_clock
614 * used for LVDS downclocking
615 * @best_clock: best PLL values found
617 * Returns true on success, false on failure.
619 bool (*find_dpll
)(const struct intel_limit
*limit
,
620 struct intel_crtc_state
*crtc_state
,
621 int target
, int refclk
,
622 struct dpll
*match_clock
,
623 struct dpll
*best_clock
);
624 void (*update_wm
)(struct drm_crtc
*crtc
);
625 void (*update_sprite_wm
)(struct drm_plane
*plane
,
626 struct drm_crtc
*crtc
,
627 uint32_t sprite_width
, uint32_t sprite_height
,
628 int pixel_size
, bool enable
, bool scaled
);
629 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
630 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
631 /* Returns the active state of the crtc, and if the crtc is active,
632 * fills out the pipe-config with the hw state. */
633 bool (*get_pipe_config
)(struct intel_crtc
*,
634 struct intel_crtc_state
*);
635 void (*get_initial_plane_config
)(struct intel_crtc
*,
636 struct intel_initial_plane_config
*);
637 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
638 struct intel_crtc_state
*crtc_state
);
639 void (*crtc_enable
)(struct drm_crtc
*crtc
);
640 void (*crtc_disable
)(struct drm_crtc
*crtc
);
641 void (*audio_codec_enable
)(struct drm_connector
*connector
,
642 struct intel_encoder
*encoder
,
643 struct drm_display_mode
*mode
);
644 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
645 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
646 void (*init_clock_gating
)(struct drm_device
*dev
);
647 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
648 struct drm_framebuffer
*fb
,
649 struct drm_i915_gem_object
*obj
,
650 struct drm_i915_gem_request
*req
,
652 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
653 struct drm_framebuffer
*fb
,
655 void (*hpd_irq_setup
)(struct drm_device
*dev
);
656 /* clock updates for mode set */
658 /* render clock increase/decrease */
659 /* display clock increase/decrease */
660 /* pll clock increase/decrease */
662 int (*setup_backlight
)(struct intel_connector
*connector
, enum pipe pipe
);
663 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
664 void (*set_backlight
)(struct intel_connector
*connector
,
666 void (*disable_backlight
)(struct intel_connector
*connector
);
667 void (*enable_backlight
)(struct intel_connector
*connector
);
670 enum forcewake_domain_id
{
671 FW_DOMAIN_ID_RENDER
= 0,
672 FW_DOMAIN_ID_BLITTER
,
678 enum forcewake_domains
{
679 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
680 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
681 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
682 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
687 struct intel_uncore_funcs
{
688 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
689 enum forcewake_domains domains
);
690 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
691 enum forcewake_domains domains
);
693 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
694 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
695 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
696 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
698 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
699 uint8_t val
, bool trace
);
700 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
701 uint16_t val
, bool trace
);
702 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
703 uint32_t val
, bool trace
);
704 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
705 uint64_t val
, bool trace
);
708 struct intel_uncore
{
709 spinlock_t lock
; /** lock is also taken in irq contexts. */
711 struct intel_uncore_funcs funcs
;
714 enum forcewake_domains fw_domains
;
716 struct intel_uncore_forcewake_domain
{
717 struct drm_i915_private
*i915
;
718 enum forcewake_domain_id id
;
720 struct timer_list timer
;
727 } fw_domain
[FW_DOMAIN_ID_COUNT
];
730 /* Iterate over initialised fw domains */
731 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
732 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
733 (i__) < FW_DOMAIN_ID_COUNT; \
734 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
735 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
737 #define for_each_fw_domain(domain__, dev_priv__, i__) \
738 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
741 FW_UNINITIALIZED
= 0,
748 uint32_t *dmc_payload
;
749 uint32_t dmc_fw_size
;
751 uint32_t mmioaddr
[8];
752 uint32_t mmiodata
[8];
753 enum csr_state state
;
756 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
757 func(is_mobile) sep \
760 func(is_i945gm) sep \
762 func(need_gfx_hws) sep \
764 func(is_pineview) sep \
765 func(is_broadwater) sep \
766 func(is_crestline) sep \
767 func(is_ivybridge) sep \
768 func(is_valleyview) sep \
769 func(is_haswell) sep \
770 func(is_skylake) sep \
771 func(is_preliminary) sep \
773 func(has_pipe_cxsr) sep \
774 func(has_hotplug) sep \
775 func(cursor_needs_physical) sep \
776 func(has_overlay) sep \
777 func(overlay_needs_physical) sep \
778 func(supports_tv) sep \
783 #define DEFINE_FLAG(name) u8 name:1
784 #define SEP_SEMICOLON ;
786 struct intel_device_info
{
787 u32 display_mmio_offset
;
790 u8 num_sprites
[I915_MAX_PIPES
];
792 u8 ring_mask
; /* Rings supported by the HW */
793 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
794 /* Register offsets for the various display pipes and transcoders */
795 int pipe_offsets
[I915_MAX_TRANSCODERS
];
796 int trans_offsets
[I915_MAX_TRANSCODERS
];
797 int palette_offsets
[I915_MAX_PIPES
];
798 int cursor_offsets
[I915_MAX_PIPES
];
800 /* Slice/subslice/EU info */
803 u8 subslice_per_slice
;
806 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
809 u8 has_subslice_pg
:1;
816 enum i915_cache_level
{
818 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
819 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
820 caches, eg sampler/render caches, and the
821 large Last-Level-Cache. LLC is coherent with
822 the CPU, but L3 is only visible to the GPU. */
823 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
826 struct i915_ctx_hang_stats
{
827 /* This context had batch pending when hang was declared */
828 unsigned batch_pending
;
830 /* This context had batch active when hang was declared */
831 unsigned batch_active
;
833 /* Time when this context was last blamed for a GPU reset */
834 unsigned long guilty_ts
;
836 /* If the contexts causes a second GPU hang within this time,
837 * it is permanently banned from submitting any more work.
839 unsigned long ban_period_seconds
;
841 /* This context is banned to submit more work */
845 /* This must match up with the value previously used for execbuf2.rsvd1. */
846 #define DEFAULT_CONTEXT_HANDLE 0
848 #define CONTEXT_NO_ZEROMAP (1<<0)
850 * struct intel_context - as the name implies, represents a context.
851 * @ref: reference count.
852 * @user_handle: userspace tracking identity for this context.
853 * @remap_slice: l3 row remapping information.
854 * @flags: context specific flags:
855 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
856 * @file_priv: filp associated with this context (NULL for global default
858 * @hang_stats: information about the role of this context in possible GPU
860 * @ppgtt: virtual memory space used by this context.
861 * @legacy_hw_ctx: render context backing object and whether it is correctly
862 * initialized (legacy ring submission mechanism only).
863 * @link: link in the global list of contexts.
865 * Contexts are memory images used by the hardware to store copies of their
868 struct intel_context
{
872 struct drm_i915_private
*i915
;
874 struct drm_i915_file_private
*file_priv
;
875 struct i915_ctx_hang_stats hang_stats
;
876 struct i915_hw_ppgtt
*ppgtt
;
878 /* Legacy ring buffer submission */
880 struct drm_i915_gem_object
*rcs_state
;
885 bool rcs_initialized
;
887 struct drm_i915_gem_object
*state
;
888 struct intel_ringbuffer
*ringbuf
;
890 } engine
[I915_NUM_RINGS
];
892 struct list_head link
;
904 /* This is always the inner lock when overlapping with struct_mutex and
905 * it's the outer lock when overlapping with stolen_lock. */
907 unsigned long uncompressed_size
;
910 unsigned int possible_framebuffer_bits
;
911 unsigned int busy_bits
;
912 struct intel_crtc
*crtc
;
915 struct drm_mm_node compressed_fb
;
916 struct drm_mm_node
*compressed_llb
;
920 /* Tracks whether the HW is actually enabled, not whether the feature is
924 struct intel_fbc_work
{
925 struct delayed_work work
;
926 struct intel_crtc
*crtc
;
927 struct drm_framebuffer
*fb
;
931 FBC_OK
, /* FBC is enabled */
932 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
933 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
934 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
935 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
936 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
937 FBC_BAD_PLANE
, /* fbc not supported on plane */
938 FBC_NOT_TILED
, /* buffer not tiled */
939 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
941 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
942 FBC_ROTATION
, /* rotation is not supported */
943 FBC_IN_DBG_MASTER
, /* kernel debugger is active */
946 bool (*fbc_enabled
)(struct drm_i915_private
*dev_priv
);
947 void (*enable_fbc
)(struct intel_crtc
*crtc
);
948 void (*disable_fbc
)(struct drm_i915_private
*dev_priv
);
952 * HIGH_RR is the highest eDP panel refresh rate read from EDID
953 * LOW_RR is the lowest eDP panel refresh rate found from EDID
954 * parsing for same resolution.
956 enum drrs_refresh_rate_type
{
959 DRRS_MAX_RR
, /* RR count */
962 enum drrs_support_type
{
963 DRRS_NOT_SUPPORTED
= 0,
964 STATIC_DRRS_SUPPORT
= 1,
965 SEAMLESS_DRRS_SUPPORT
= 2
971 struct delayed_work work
;
973 unsigned busy_frontbuffer_bits
;
974 enum drrs_refresh_rate_type refresh_rate_type
;
975 enum drrs_support_type type
;
982 struct intel_dp
*enabled
;
984 struct delayed_work work
;
985 unsigned busy_frontbuffer_bits
;
991 PCH_NONE
= 0, /* No PCH present */
992 PCH_IBX
, /* Ibexpeak PCH */
993 PCH_CPT
, /* Cougarpoint PCH */
994 PCH_LPT
, /* Lynxpoint PCH */
995 PCH_SPT
, /* Sunrisepoint PCH */
999 enum intel_sbi_destination
{
1004 #define QUIRK_PIPEA_FORCE (1<<0)
1005 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1006 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1007 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1008 #define QUIRK_PIPEB_FORCE (1<<4)
1009 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1012 struct intel_fbc_work
;
1014 struct intel_gmbus
{
1015 struct i2c_adapter adapter
;
1019 struct i2c_algo_bit_data bit_algo
;
1020 struct drm_i915_private
*dev_priv
;
1023 struct i915_suspend_saved_registers
{
1026 u32 savePP_ON_DELAYS
;
1027 u32 savePP_OFF_DELAYS
;
1032 u32 saveFBC_CONTROL
;
1033 u32 saveCACHE_MODE_0
;
1034 u32 saveMI_ARB_STATE
;
1038 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1039 u32 savePCH_PORT_HOTPLUG
;
1043 struct vlv_s0ix_state
{
1050 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1051 u32 media_max_req_count
;
1052 u32 gfx_max_req_count
;
1078 u32 rp_down_timeout
;
1084 /* Display 1 CZ domain */
1089 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1091 /* GT SA CZ domain */
1098 /* Display 2 CZ domain */
1102 u32 clock_gate_dis2
;
1105 struct intel_rps_ei
{
1111 struct intel_gen6_power_mgmt
{
1113 * work, interrupts_enabled and pm_iir are protected by
1114 * dev_priv->irq_lock
1116 struct work_struct work
;
1117 bool interrupts_enabled
;
1120 /* Frequencies are stored in potentially platform dependent multiples.
1121 * In other words, *_freq needs to be multiplied by X to be interesting.
1122 * Soft limits are those which are used for the dynamic reclocking done
1123 * by the driver (raise frequencies under heavy loads, and lower for
1124 * lighter loads). Hard limits are those imposed by the hardware.
1126 * A distinction is made for overclocking, which is never enabled by
1127 * default, and is considered to be above the hard limit if it's
1130 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1131 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1132 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1133 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1134 u8 min_freq
; /* AKA RPn. Minimum frequency */
1135 u8 idle_freq
; /* Frequency to request when we are idle */
1136 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1137 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1138 u8 rp0_freq
; /* Non-overclocked max frequency. */
1141 u8 up_threshold
; /* Current %busy required to uplock */
1142 u8 down_threshold
; /* Current %busy required to downclock */
1145 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1147 spinlock_t client_lock
;
1148 struct list_head clients
;
1152 struct delayed_work delayed_resume_work
;
1155 struct intel_rps_client semaphores
, mmioflips
;
1157 /* manual wa residency calculations */
1158 struct intel_rps_ei up_ei
, down_ei
;
1161 * Protects RPS/RC6 register access and PCU communication.
1162 * Must be taken after struct_mutex if nested. Note that
1163 * this lock may be held for long periods of time when
1164 * talking to hw - so only take it when talking to hw!
1166 struct mutex hw_lock
;
1169 /* defined intel_pm.c */
1170 extern spinlock_t mchdev_lock
;
1172 struct intel_ilk_power_mgmt
{
1180 unsigned long last_time1
;
1181 unsigned long chipset_power
;
1184 unsigned long gfx_power
;
1191 struct drm_i915_private
;
1192 struct i915_power_well
;
1194 struct i915_power_well_ops
{
1196 * Synchronize the well's hw state to match the current sw state, for
1197 * example enable/disable it based on the current refcount. Called
1198 * during driver init and resume time, possibly after first calling
1199 * the enable/disable handlers.
1201 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1202 struct i915_power_well
*power_well
);
1204 * Enable the well and resources that depend on it (for example
1205 * interrupts located on the well). Called after the 0->1 refcount
1208 void (*enable
)(struct drm_i915_private
*dev_priv
,
1209 struct i915_power_well
*power_well
);
1211 * Disable the well and resources that depend on it. Called after
1212 * the 1->0 refcount transition.
1214 void (*disable
)(struct drm_i915_private
*dev_priv
,
1215 struct i915_power_well
*power_well
);
1216 /* Returns the hw enabled state. */
1217 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1218 struct i915_power_well
*power_well
);
1221 /* Power well structure for haswell */
1222 struct i915_power_well
{
1225 /* power well enable/disable usage count */
1227 /* cached hw enabled state */
1229 unsigned long domains
;
1231 const struct i915_power_well_ops
*ops
;
1234 struct i915_power_domains
{
1236 * Power wells needed for initialization at driver init and suspend
1237 * time are on. They are kept on until after the first modeset.
1241 int power_well_count
;
1244 int domain_use_count
[POWER_DOMAIN_NUM
];
1245 struct i915_power_well
*power_wells
;
1248 #define MAX_L3_SLICES 2
1249 struct intel_l3_parity
{
1250 u32
*remap_info
[MAX_L3_SLICES
];
1251 struct work_struct error_work
;
1255 struct i915_gem_mm
{
1256 /** Memory allocator for GTT stolen memory */
1257 struct drm_mm stolen
;
1258 /** Protects the usage of the GTT stolen memory allocator. This is
1259 * always the inner lock when overlapping with struct_mutex. */
1260 struct mutex stolen_lock
;
1262 /** List of all objects in gtt_space. Used to restore gtt
1263 * mappings on resume */
1264 struct list_head bound_list
;
1266 * List of objects which are not bound to the GTT (thus
1267 * are idle and not used by the GPU) but still have
1268 * (presumably uncached) pages still attached.
1270 struct list_head unbound_list
;
1272 /** Usable portion of the GTT for GEM */
1273 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1275 /** PPGTT used for aliasing the PPGTT with the GTT */
1276 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1278 struct notifier_block oom_notifier
;
1279 struct shrinker shrinker
;
1280 bool shrinker_no_lock_stealing
;
1282 /** LRU list of objects with fence regs on them. */
1283 struct list_head fence_list
;
1286 * We leave the user IRQ off as much as possible,
1287 * but this means that requests will finish and never
1288 * be retired once the system goes idle. Set a timer to
1289 * fire periodically while the ring is running. When it
1290 * fires, go retire requests.
1292 struct delayed_work retire_work
;
1295 * When we detect an idle GPU, we want to turn on
1296 * powersaving features. So once we see that there
1297 * are no more requests outstanding and no more
1298 * arrive within a small period of time, we fire
1299 * off the idle_work.
1301 struct delayed_work idle_work
;
1304 * Are we in a non-interruptible section of code like
1310 * Is the GPU currently considered idle, or busy executing userspace
1311 * requests? Whilst idle, we attempt to power down the hardware and
1312 * display clocks. In order to reduce the effect on performance, there
1313 * is a slight delay before we do so.
1317 /* the indicator for dispatch video commands on two BSD rings */
1318 int bsd_ring_dispatch_index
;
1320 /** Bit 6 swizzling required for X tiling */
1321 uint32_t bit_6_swizzle_x
;
1322 /** Bit 6 swizzling required for Y tiling */
1323 uint32_t bit_6_swizzle_y
;
1325 /* accounting, useful for userland debugging */
1326 spinlock_t object_stat_lock
;
1327 size_t object_memory
;
1331 struct drm_i915_error_state_buf
{
1332 struct drm_i915_private
*i915
;
1341 struct i915_error_state_file_priv
{
1342 struct drm_device
*dev
;
1343 struct drm_i915_error_state
*error
;
1346 struct i915_gpu_error
{
1347 /* For hangcheck timer */
1348 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1349 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1350 /* Hang gpu twice in this window and your context gets banned */
1351 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1353 struct workqueue_struct
*hangcheck_wq
;
1354 struct delayed_work hangcheck_work
;
1356 /* For reset and error_state handling. */
1358 /* Protected by the above dev->gpu_error.lock. */
1359 struct drm_i915_error_state
*first_error
;
1361 unsigned long missed_irq_rings
;
1364 * State variable controlling the reset flow and count
1366 * This is a counter which gets incremented when reset is triggered,
1367 * and again when reset has been handled. So odd values (lowest bit set)
1368 * means that reset is in progress and even values that
1369 * (reset_counter >> 1):th reset was successfully completed.
1371 * If reset is not completed succesfully, the I915_WEDGE bit is
1372 * set meaning that hardware is terminally sour and there is no
1373 * recovery. All waiters on the reset_queue will be woken when
1376 * This counter is used by the wait_seqno code to notice that reset
1377 * event happened and it needs to restart the entire ioctl (since most
1378 * likely the seqno it waited for won't ever signal anytime soon).
1380 * This is important for lock-free wait paths, where no contended lock
1381 * naturally enforces the correct ordering between the bail-out of the
1382 * waiter and the gpu reset work code.
1384 atomic_t reset_counter
;
1386 #define I915_RESET_IN_PROGRESS_FLAG 1
1387 #define I915_WEDGED (1 << 31)
1390 * Waitqueue to signal when the reset has completed. Used by clients
1391 * that wait for dev_priv->mm.wedged to settle.
1393 wait_queue_head_t reset_queue
;
1395 /* Userspace knobs for gpu hang simulation;
1396 * combines both a ring mask, and extra flags
1399 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1400 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1402 /* For missed irq/seqno simulation. */
1403 unsigned int test_irq_rings
;
1405 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1406 bool reload_in_reset
;
1409 enum modeset_restore
{
1410 MODESET_ON_LID_OPEN
,
1415 #define DP_AUX_A 0x40
1416 #define DP_AUX_B 0x10
1417 #define DP_AUX_C 0x20
1418 #define DP_AUX_D 0x30
1420 #define DDC_PIN_B 0x05
1421 #define DDC_PIN_C 0x04
1422 #define DDC_PIN_D 0x06
1424 struct ddi_vbt_port_info
{
1426 * This is an index in the HDMI/DVI DDI buffer translation table.
1427 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1428 * populate this field.
1430 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1431 uint8_t hdmi_level_shift
;
1433 uint8_t supports_dvi
:1;
1434 uint8_t supports_hdmi
:1;
1435 uint8_t supports_dp
:1;
1437 uint8_t alternate_aux_channel
;
1438 uint8_t alternate_ddc_pin
;
1440 uint8_t dp_boost_level
;
1441 uint8_t hdmi_boost_level
;
1444 enum psr_lines_to_wait
{
1445 PSR_0_LINES_TO_WAIT
= 0,
1447 PSR_4_LINES_TO_WAIT
,
1451 struct intel_vbt_data
{
1452 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1453 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1456 unsigned int int_tv_support
:1;
1457 unsigned int lvds_dither
:1;
1458 unsigned int lvds_vbt
:1;
1459 unsigned int int_crt_support
:1;
1460 unsigned int lvds_use_ssc
:1;
1461 unsigned int display_clock_mode
:1;
1462 unsigned int fdi_rx_polarity_inverted
:1;
1463 unsigned int has_mipi
:1;
1465 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1467 enum drrs_support_type drrs_type
;
1472 int edp_preemphasis
;
1474 bool edp_initialized
;
1477 struct edp_power_seq edp_pps
;
1481 bool require_aux_wakeup
;
1483 enum psr_lines_to_wait lines_to_wait
;
1484 int tp1_wakeup_time
;
1485 int tp2_tp3_wakeup_time
;
1491 bool active_low_pwm
;
1492 u8 min_brightness
; /* min_brightness/255 of max */
1499 struct mipi_config
*config
;
1500 struct mipi_pps_data
*pps
;
1504 u8
*sequence
[MIPI_SEQ_MAX
];
1510 union child_device_config
*child_dev
;
1512 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1515 enum intel_ddb_partitioning
{
1517 INTEL_DDB_PART_5_6
, /* IVB+ */
1520 struct intel_wm_level
{
1528 struct ilk_wm_values
{
1529 uint32_t wm_pipe
[3];
1531 uint32_t wm_lp_spr
[3];
1532 uint32_t wm_linetime
[3];
1534 enum intel_ddb_partitioning partitioning
;
1537 struct vlv_pipe_wm
{
1548 struct vlv_wm_values
{
1549 struct vlv_pipe_wm pipe
[3];
1550 struct vlv_sr_wm sr
;
1560 struct skl_ddb_entry
{
1561 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1564 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1566 return entry
->end
- entry
->start
;
1569 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1570 const struct skl_ddb_entry
*e2
)
1572 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1578 struct skl_ddb_allocation
{
1579 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1580 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1581 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* y-plane */
1582 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1585 struct skl_wm_values
{
1586 bool dirty
[I915_MAX_PIPES
];
1587 struct skl_ddb_allocation ddb
;
1588 uint32_t wm_linetime
[I915_MAX_PIPES
];
1589 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1590 uint32_t cursor
[I915_MAX_PIPES
][8];
1591 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1592 uint32_t cursor_trans
[I915_MAX_PIPES
];
1595 struct skl_wm_level
{
1596 bool plane_en
[I915_MAX_PLANES
];
1598 uint16_t plane_res_b
[I915_MAX_PLANES
];
1599 uint8_t plane_res_l
[I915_MAX_PLANES
];
1600 uint16_t cursor_res_b
;
1601 uint8_t cursor_res_l
;
1605 * This struct helps tracking the state needed for runtime PM, which puts the
1606 * device in PCI D3 state. Notice that when this happens, nothing on the
1607 * graphics device works, even register access, so we don't get interrupts nor
1610 * Every piece of our code that needs to actually touch the hardware needs to
1611 * either call intel_runtime_pm_get or call intel_display_power_get with the
1612 * appropriate power domain.
1614 * Our driver uses the autosuspend delay feature, which means we'll only really
1615 * suspend if we stay with zero refcount for a certain amount of time. The
1616 * default value is currently very conservative (see intel_runtime_pm_enable), but
1617 * it can be changed with the standard runtime PM files from sysfs.
1619 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1620 * goes back to false exactly before we reenable the IRQs. We use this variable
1621 * to check if someone is trying to enable/disable IRQs while they're supposed
1622 * to be disabled. This shouldn't happen and we'll print some error messages in
1625 * For more, read the Documentation/power/runtime_pm.txt.
1627 struct i915_runtime_pm
{
1632 enum intel_pipe_crc_source
{
1633 INTEL_PIPE_CRC_SOURCE_NONE
,
1634 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1635 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1636 INTEL_PIPE_CRC_SOURCE_PF
,
1637 INTEL_PIPE_CRC_SOURCE_PIPE
,
1638 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1639 INTEL_PIPE_CRC_SOURCE_TV
,
1640 INTEL_PIPE_CRC_SOURCE_DP_B
,
1641 INTEL_PIPE_CRC_SOURCE_DP_C
,
1642 INTEL_PIPE_CRC_SOURCE_DP_D
,
1643 INTEL_PIPE_CRC_SOURCE_AUTO
,
1644 INTEL_PIPE_CRC_SOURCE_MAX
,
1647 struct intel_pipe_crc_entry
{
1652 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1653 struct intel_pipe_crc
{
1655 bool opened
; /* exclusive access to the result file */
1656 struct intel_pipe_crc_entry
*entries
;
1657 enum intel_pipe_crc_source source
;
1659 wait_queue_head_t wq
;
1662 struct i915_frontbuffer_tracking
{
1666 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1673 struct i915_wa_reg
{
1676 /* bitmask representing WA bits */
1680 #define I915_MAX_WA_REGS 16
1682 struct i915_workarounds
{
1683 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1687 struct i915_virtual_gpu
{
1691 struct i915_execbuffer_params
{
1692 struct drm_device
*dev
;
1693 struct drm_file
*file
;
1694 uint32_t dispatch_flags
;
1695 uint32_t args_batch_start_offset
;
1696 uint32_t batch_obj_vm_offset
;
1697 struct intel_engine_cs
*ring
;
1698 struct drm_i915_gem_object
*batch_obj
;
1699 struct intel_context
*ctx
;
1700 struct drm_i915_gem_request
*request
;
1703 struct drm_i915_private
{
1704 struct drm_device
*dev
;
1705 struct kmem_cache
*objects
;
1706 struct kmem_cache
*vmas
;
1707 struct kmem_cache
*requests
;
1709 const struct intel_device_info info
;
1711 int relative_constants_mode
;
1715 struct intel_uncore uncore
;
1717 struct i915_virtual_gpu vgpu
;
1719 struct intel_csr csr
;
1721 /* Display CSR-related protection */
1722 struct mutex csr_lock
;
1724 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1726 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1727 * controller on different i2c buses. */
1728 struct mutex gmbus_mutex
;
1731 * Base address of the gmbus and gpio block.
1733 uint32_t gpio_mmio_base
;
1735 /* MMIO base address for MIPI regs */
1736 uint32_t mipi_mmio_base
;
1738 wait_queue_head_t gmbus_wait_queue
;
1740 struct pci_dev
*bridge_dev
;
1741 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1742 struct drm_i915_gem_object
*semaphore_obj
;
1743 uint32_t last_seqno
, next_seqno
;
1745 struct drm_dma_handle
*status_page_dmah
;
1746 struct resource mch_res
;
1748 /* protects the irq masks */
1749 spinlock_t irq_lock
;
1751 /* protects the mmio flip data */
1752 spinlock_t mmio_flip_lock
;
1754 bool display_irqs_enabled
;
1756 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1757 struct pm_qos_request pm_qos
;
1759 /* Sideband mailbox protection */
1760 struct mutex sb_lock
;
1762 /** Cached value of IMR to avoid reads in updating the bitfield */
1765 u32 de_irq_mask
[I915_MAX_PIPES
];
1770 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1772 struct i915_hotplug hotplug
;
1773 struct i915_fbc fbc
;
1774 struct i915_drrs drrs
;
1775 struct intel_opregion opregion
;
1776 struct intel_vbt_data vbt
;
1778 bool preserve_bios_swizzle
;
1781 struct intel_overlay
*overlay
;
1783 /* backlight registers and fields in struct intel_panel */
1784 struct mutex backlight_lock
;
1787 bool no_aux_handshake
;
1789 /* protects panel power sequencer state */
1790 struct mutex pps_mutex
;
1792 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1793 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1794 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1796 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1797 unsigned int skl_boot_cdclk
;
1798 unsigned int cdclk_freq
, max_cdclk_freq
;
1799 unsigned int hpll_freq
;
1802 * wq - Driver workqueue for GEM.
1804 * NOTE: Work items scheduled here are not allowed to grab any modeset
1805 * locks, for otherwise the flushing done in the pageflip code will
1806 * result in deadlocks.
1808 struct workqueue_struct
*wq
;
1810 /* Display functions */
1811 struct drm_i915_display_funcs display
;
1813 /* PCH chipset type */
1814 enum intel_pch pch_type
;
1815 unsigned short pch_id
;
1817 unsigned long quirks
;
1819 enum modeset_restore modeset_restore
;
1820 struct mutex modeset_restore_lock
;
1822 struct list_head vm_list
; /* Global list of all address spaces */
1823 struct i915_gtt gtt
; /* VM representing the global address space */
1825 struct i915_gem_mm mm
;
1826 DECLARE_HASHTABLE(mm_structs
, 7);
1827 struct mutex mm_lock
;
1829 /* Kernel Modesetting */
1831 struct sdvo_device_mapping sdvo_mappings
[2];
1833 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1834 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1835 wait_queue_head_t pending_flip_queue
;
1837 #ifdef CONFIG_DEBUG_FS
1838 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1841 int num_shared_dpll
;
1842 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1843 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1845 struct i915_workarounds workarounds
;
1847 /* Reclocking support */
1848 bool render_reclock_avail
;
1850 struct i915_frontbuffer_tracking fb_tracking
;
1854 bool mchbar_need_disable
;
1856 struct intel_l3_parity l3_parity
;
1858 /* Cannot be determined by PCIID. You must always read a register. */
1861 /* gen6+ rps state */
1862 struct intel_gen6_power_mgmt rps
;
1864 /* ilk-only ips/rps state. Everything in here is protected by the global
1865 * mchdev_lock in intel_pm.c */
1866 struct intel_ilk_power_mgmt ips
;
1868 struct i915_power_domains power_domains
;
1870 struct i915_psr psr
;
1872 struct i915_gpu_error gpu_error
;
1874 struct drm_i915_gem_object
*vlv_pctx
;
1876 #ifdef CONFIG_DRM_FBDEV_EMULATION
1877 /* list of fbdev register on this device */
1878 struct intel_fbdev
*fbdev
;
1879 struct work_struct fbdev_suspend_work
;
1882 struct drm_property
*broadcast_rgb_property
;
1883 struct drm_property
*force_audio_property
;
1885 /* hda/i915 audio component */
1886 bool audio_component_registered
;
1888 uint32_t hw_context_size
;
1889 struct list_head context_list
;
1893 u32 chv_phy_control
;
1896 struct i915_suspend_saved_registers regfile
;
1897 struct vlv_s0ix_state vlv_s0ix_state
;
1901 * Raw watermark latency values:
1902 * in 0.1us units for WM0,
1903 * in 0.5us units for WM1+.
1906 uint16_t pri_latency
[5];
1908 uint16_t spr_latency
[5];
1910 uint16_t cur_latency
[5];
1912 * Raw watermark memory latency values
1913 * for SKL for all 8 levels
1916 uint16_t skl_latency
[8];
1919 * The skl_wm_values structure is a bit too big for stack
1920 * allocation, so we keep the staging struct where we store
1921 * intermediate results here instead.
1923 struct skl_wm_values skl_results
;
1925 /* current hardware state */
1927 struct ilk_wm_values hw
;
1928 struct skl_wm_values skl_hw
;
1929 struct vlv_wm_values vlv
;
1935 struct i915_runtime_pm pm
;
1937 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1939 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
1940 struct drm_i915_gem_execbuffer2
*args
,
1941 struct list_head
*vmas
);
1942 int (*init_rings
)(struct drm_device
*dev
);
1943 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1944 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1947 bool edp_low_vswing
;
1950 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1951 * will be rejected. Instead look for a better place.
1955 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1957 return dev
->dev_private
;
1960 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1962 return to_i915(dev_get_drvdata(dev
));
1965 /* Iterate over initialised rings */
1966 #define for_each_ring(ring__, dev_priv__, i__) \
1967 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1968 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1970 enum hdmi_force_audio
{
1971 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1972 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1973 HDMI_AUDIO_AUTO
, /* trust EDID */
1974 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1977 #define I915_GTT_OFFSET_NONE ((u32)-1)
1979 struct drm_i915_gem_object_ops
{
1980 /* Interface between the GEM object and its backing storage.
1981 * get_pages() is called once prior to the use of the associated set
1982 * of pages before to binding them into the GTT, and put_pages() is
1983 * called after we no longer need them. As we expect there to be
1984 * associated cost with migrating pages between the backing storage
1985 * and making them available for the GPU (e.g. clflush), we may hold
1986 * onto the pages after they are no longer referenced by the GPU
1987 * in case they may be used again shortly (for example migrating the
1988 * pages to a different memory domain within the GTT). put_pages()
1989 * will therefore most likely be called when the object itself is
1990 * being released or under memory pressure (where we attempt to
1991 * reap pages for the shrinker).
1993 int (*get_pages
)(struct drm_i915_gem_object
*);
1994 void (*put_pages
)(struct drm_i915_gem_object
*);
1995 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1996 void (*release
)(struct drm_i915_gem_object
*);
2000 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2001 * considered to be the frontbuffer for the given plane interface-vise. This
2002 * doesn't mean that the hw necessarily already scans it out, but that any
2003 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2005 * We have one bit per pipe and per scanout plane type.
2007 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
2008 #define INTEL_FRONTBUFFER_BITS \
2009 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2010 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2011 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2012 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2013 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2014 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
2015 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2016 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2017 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2018 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2019 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2021 struct drm_i915_gem_object
{
2022 struct drm_gem_object base
;
2024 const struct drm_i915_gem_object_ops
*ops
;
2026 /** List of VMAs backed by this object */
2027 struct list_head vma_list
;
2029 /** Stolen memory for this object, instead of being backed by shmem. */
2030 struct drm_mm_node
*stolen
;
2031 struct list_head global_list
;
2033 struct list_head ring_list
[I915_NUM_RINGS
];
2034 /** Used in execbuf to temporarily hold a ref */
2035 struct list_head obj_exec_link
;
2037 struct list_head batch_pool_link
;
2040 * This is set if the object is on the active lists (has pending
2041 * rendering and so a non-zero seqno), and is not set if it i s on
2042 * inactive (ready to be unbound) list.
2044 unsigned int active
:I915_NUM_RINGS
;
2047 * This is set if the object has been written to since last bound
2050 unsigned int dirty
:1;
2053 * Fence register bits (if any) for this object. Will be set
2054 * as needed when mapped into the GTT.
2055 * Protected by dev->struct_mutex.
2057 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2060 * Advice: are the backing pages purgeable?
2062 unsigned int madv
:2;
2065 * Current tiling mode for the object.
2067 unsigned int tiling_mode
:2;
2069 * Whether the tiling parameters for the currently associated fence
2070 * register have changed. Note that for the purposes of tracking
2071 * tiling changes we also treat the unfenced register, the register
2072 * slot that the object occupies whilst it executes a fenced
2073 * command (such as BLT on gen2/3), as a "fence".
2075 unsigned int fence_dirty
:1;
2078 * Is the object at the current location in the gtt mappable and
2079 * fenceable? Used to avoid costly recalculations.
2081 unsigned int map_and_fenceable
:1;
2084 * Whether the current gtt mapping needs to be mappable (and isn't just
2085 * mappable by accident). Track pin and fault separate for a more
2086 * accurate mappable working set.
2088 unsigned int fault_mappable
:1;
2091 * Is the object to be mapped as read-only to the GPU
2092 * Only honoured if hardware has relevant pte bit
2094 unsigned long gt_ro
:1;
2095 unsigned int cache_level
:3;
2096 unsigned int cache_dirty
:1;
2098 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2100 unsigned int pin_display
;
2102 struct sg_table
*pages
;
2103 int pages_pin_count
;
2105 struct scatterlist
*sg
;
2109 /* prime dma-buf support */
2110 void *dma_buf_vmapping
;
2113 /** Breadcrumb of last rendering to the buffer.
2114 * There can only be one writer, but we allow for multiple readers.
2115 * If there is a writer that necessarily implies that all other
2116 * read requests are complete - but we may only be lazily clearing
2117 * the read requests. A read request is naturally the most recent
2118 * request on a ring, so we may have two different write and read
2119 * requests on one ring where the write request is older than the
2120 * read request. This allows for the CPU to read from an active
2121 * buffer by only waiting for the write to complete.
2123 struct drm_i915_gem_request
*last_read_req
[I915_NUM_RINGS
];
2124 struct drm_i915_gem_request
*last_write_req
;
2125 /** Breadcrumb of last fenced GPU access to the buffer. */
2126 struct drm_i915_gem_request
*last_fenced_req
;
2128 /** Current tiling stride for the object, if it's tiled. */
2131 /** References from framebuffers, locks out tiling changes. */
2132 unsigned long framebuffer_references
;
2134 /** Record of address bit 17 of each page at last unbind. */
2135 unsigned long *bit_17
;
2138 /** for phy allocated objects */
2139 struct drm_dma_handle
*phys_handle
;
2141 struct i915_gem_userptr
{
2143 unsigned read_only
:1;
2144 unsigned workers
:4;
2145 #define I915_GEM_USERPTR_MAX_WORKERS 15
2147 struct i915_mm_struct
*mm
;
2148 struct i915_mmu_object
*mmu_object
;
2149 struct work_struct
*work
;
2153 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2155 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2156 struct drm_i915_gem_object
*new,
2157 unsigned frontbuffer_bits
);
2160 * Request queue structure.
2162 * The request queue allows us to note sequence numbers that have been emitted
2163 * and may be associated with active buffers to be retired.
2165 * By keeping this list, we can avoid having to do questionable sequence
2166 * number comparisons on buffer last_read|write_seqno. It also allows an
2167 * emission time to be associated with the request for tracking how far ahead
2168 * of the GPU the submission is.
2170 * The requests are reference counted, so upon creation they should have an
2171 * initial reference taken using kref_init
2173 struct drm_i915_gem_request
{
2176 /** On Which ring this request was generated */
2177 struct drm_i915_private
*i915
;
2178 struct intel_engine_cs
*ring
;
2180 /** GEM sequence number associated with this request. */
2183 /** Position in the ringbuffer of the start of the request */
2187 * Position in the ringbuffer of the start of the postfix.
2188 * This is required to calculate the maximum available ringbuffer
2189 * space without overwriting the postfix.
2193 /** Position in the ringbuffer of the end of the whole request */
2197 * Context and ring buffer related to this request
2198 * Contexts are refcounted, so when this request is associated with a
2199 * context, we must increment the context's refcount, to guarantee that
2200 * it persists while any request is linked to it. Requests themselves
2201 * are also refcounted, so the request will only be freed when the last
2202 * reference to it is dismissed, and the code in
2203 * i915_gem_request_free() will then decrement the refcount on the
2206 struct intel_context
*ctx
;
2207 struct intel_ringbuffer
*ringbuf
;
2209 /** Batch buffer related to this request if any (used for
2210 error state dump only) */
2211 struct drm_i915_gem_object
*batch_obj
;
2213 /** Time at which this request was emitted, in jiffies. */
2214 unsigned long emitted_jiffies
;
2216 /** global list entry for this request */
2217 struct list_head list
;
2219 struct drm_i915_file_private
*file_priv
;
2220 /** file_priv list entry for this request */
2221 struct list_head client_list
;
2223 /** process identifier submitting this request */
2227 * The ELSP only accepts two elements at a time, so we queue
2228 * context/tail pairs on a given queue (ring->execlist_queue) until the
2229 * hardware is available. The queue serves a double purpose: we also use
2230 * it to keep track of the up to 2 contexts currently in the hardware
2231 * (usually one in execution and the other queued up by the GPU): We
2232 * only remove elements from the head of the queue when the hardware
2233 * informs us that an element has been completed.
2235 * All accesses to the queue are mediated by a spinlock
2236 * (ring->execlist_lock).
2239 /** Execlist link in the submission queue.*/
2240 struct list_head execlist_link
;
2242 /** Execlists no. of times this request has been sent to the ELSP */
2247 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2248 struct intel_context
*ctx
,
2249 struct drm_i915_gem_request
**req_out
);
2250 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
);
2251 void i915_gem_request_free(struct kref
*req_ref
);
2252 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2253 struct drm_file
*file
);
2255 static inline uint32_t
2256 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2258 return req
? req
->seqno
: 0;
2261 static inline struct intel_engine_cs
*
2262 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2264 return req
? req
->ring
: NULL
;
2267 static inline struct drm_i915_gem_request
*
2268 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2271 kref_get(&req
->ref
);
2276 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2278 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2279 kref_put(&req
->ref
, i915_gem_request_free
);
2283 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2285 struct drm_device
*dev
;
2290 dev
= req
->ring
->dev
;
2291 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2292 mutex_unlock(&dev
->struct_mutex
);
2295 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2296 struct drm_i915_gem_request
*src
)
2299 i915_gem_request_reference(src
);
2302 i915_gem_request_unreference(*pdst
);
2308 * XXX: i915_gem_request_completed should be here but currently needs the
2309 * definition of i915_seqno_passed() which is below. It will be moved in
2310 * a later patch when the call to i915_seqno_passed() is obsoleted...
2314 * A command that requires special handling by the command parser.
2316 struct drm_i915_cmd_descriptor
{
2318 * Flags describing how the command parser processes the command.
2320 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2321 * a length mask if not set
2322 * CMD_DESC_SKIP: The command is allowed but does not follow the
2323 * standard length encoding for the opcode range in
2325 * CMD_DESC_REJECT: The command is never allowed
2326 * CMD_DESC_REGISTER: The command should be checked against the
2327 * register whitelist for the appropriate ring
2328 * CMD_DESC_MASTER: The command is allowed if the submitting process
2332 #define CMD_DESC_FIXED (1<<0)
2333 #define CMD_DESC_SKIP (1<<1)
2334 #define CMD_DESC_REJECT (1<<2)
2335 #define CMD_DESC_REGISTER (1<<3)
2336 #define CMD_DESC_BITMASK (1<<4)
2337 #define CMD_DESC_MASTER (1<<5)
2340 * The command's unique identification bits and the bitmask to get them.
2341 * This isn't strictly the opcode field as defined in the spec and may
2342 * also include type, subtype, and/or subop fields.
2350 * The command's length. The command is either fixed length (i.e. does
2351 * not include a length field) or has a length field mask. The flag
2352 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2353 * a length mask. All command entries in a command table must include
2354 * length information.
2362 * Describes where to find a register address in the command to check
2363 * against the ring's register whitelist. Only valid if flags has the
2364 * CMD_DESC_REGISTER bit set.
2366 * A non-zero step value implies that the command may access multiple
2367 * registers in sequence (e.g. LRI), in that case step gives the
2368 * distance in dwords between individual offset fields.
2376 #define MAX_CMD_DESC_BITMASKS 3
2378 * Describes command checks where a particular dword is masked and
2379 * compared against an expected value. If the command does not match
2380 * the expected value, the parser rejects it. Only valid if flags has
2381 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2384 * If the check specifies a non-zero condition_mask then the parser
2385 * only performs the check when the bits specified by condition_mask
2392 u32 condition_offset
;
2394 } bits
[MAX_CMD_DESC_BITMASKS
];
2398 * A table of commands requiring special handling by the command parser.
2400 * Each ring has an array of tables. Each table consists of an array of command
2401 * descriptors, which must be sorted with command opcodes in ascending order.
2403 struct drm_i915_cmd_table
{
2404 const struct drm_i915_cmd_descriptor
*table
;
2408 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2409 #define __I915__(p) ({ \
2410 struct drm_i915_private *__p; \
2411 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2412 __p = (struct drm_i915_private *)p; \
2413 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2414 __p = to_i915((struct drm_device *)p); \
2419 #define INTEL_INFO(p) (&__I915__(p)->info)
2420 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2421 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2423 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2424 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2425 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2426 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2427 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2428 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2429 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2430 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2431 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2432 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2433 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2434 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2435 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2436 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2437 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2438 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2439 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2440 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2441 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2442 INTEL_DEVID(dev) == 0x0152 || \
2443 INTEL_DEVID(dev) == 0x015a)
2444 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2445 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2446 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2447 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2448 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2449 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2450 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2451 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2452 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2453 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2454 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2455 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2456 (INTEL_DEVID(dev) & 0xf) == 0xe))
2457 /* ULX machines are also considered ULT. */
2458 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2459 (INTEL_DEVID(dev) & 0xf) == 0xe)
2460 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2461 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2462 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2463 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2464 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2465 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2466 /* ULX machines are also considered ULT. */
2467 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2468 INTEL_DEVID(dev) == 0x0A1E)
2469 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2470 INTEL_DEVID(dev) == 0x1913 || \
2471 INTEL_DEVID(dev) == 0x1916 || \
2472 INTEL_DEVID(dev) == 0x1921 || \
2473 INTEL_DEVID(dev) == 0x1926)
2474 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2475 INTEL_DEVID(dev) == 0x1915 || \
2476 INTEL_DEVID(dev) == 0x191E)
2477 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2479 #define SKL_REVID_A0 (0x0)
2480 #define SKL_REVID_B0 (0x1)
2481 #define SKL_REVID_C0 (0x2)
2482 #define SKL_REVID_D0 (0x3)
2483 #define SKL_REVID_E0 (0x4)
2484 #define SKL_REVID_F0 (0x5)
2486 #define BXT_REVID_A0 (0x0)
2487 #define BXT_REVID_B0 (0x3)
2488 #define BXT_REVID_C0 (0x6)
2491 * The genX designation typically refers to the render engine, so render
2492 * capability related checks should use IS_GEN, while display and other checks
2493 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2496 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2497 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2498 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2499 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2500 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2501 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2502 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2503 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2505 #define RENDER_RING (1<<RCS)
2506 #define BSD_RING (1<<VCS)
2507 #define BLT_RING (1<<BCS)
2508 #define VEBOX_RING (1<<VECS)
2509 #define BSD2_RING (1<<VCS2)
2510 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2511 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2512 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2513 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2514 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2515 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2516 __I915__(dev)->ellc_size)
2517 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2519 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2520 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2521 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2522 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2524 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2525 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2527 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2528 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2530 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2531 * even when in MSI mode. This results in spurious interrupt warnings if the
2532 * legacy irq no. is shared with another device. The kernel then disables that
2533 * interrupt source and so prevents the other device from working properly.
2535 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2536 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2538 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2539 * rows, which changed the alignment requirements and fence programming.
2541 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2543 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2544 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2546 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2547 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2548 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2550 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2552 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2553 INTEL_INFO(dev)->gen >= 9)
2555 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2556 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2557 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2558 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2560 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2561 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2563 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2564 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2566 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2568 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2569 INTEL_INFO(dev)->gen >= 8)
2571 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2572 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2574 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2575 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2576 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2577 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2578 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2579 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2580 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2581 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2583 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2584 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2585 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2586 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2587 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2588 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2589 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2591 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2593 /* DPF == dynamic parity feature */
2594 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2595 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2597 #define GT_FREQUENCY_MULTIPLIER 50
2598 #define GEN9_FREQ_SCALER 3
2600 #include "i915_trace.h"
2602 extern const struct drm_ioctl_desc i915_ioctls
[];
2603 extern int i915_max_ioctl
;
2605 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2606 extern int i915_resume_legacy(struct drm_device
*dev
);
2609 struct i915_params
{
2611 int panel_ignore_lid
;
2613 int lvds_channel_mode
;
2615 int vbt_sdvo_panel_type
;
2619 int enable_execlists
;
2621 unsigned int preliminary_hw_support
;
2622 int disable_power_well
;
2624 int invert_brightness
;
2625 int enable_cmd_parser
;
2626 /* leave bools at the end to not create holes */
2627 bool enable_hangcheck
;
2629 bool prefault_disable
;
2630 bool load_detect_test
;
2632 bool disable_display
;
2633 bool disable_vtd_wa
;
2634 bool enable_guc_submission
;
2638 bool verbose_state_checks
;
2641 extern struct i915_params i915 __read_mostly
;
2644 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2645 extern int i915_driver_unload(struct drm_device
*);
2646 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2647 extern void i915_driver_lastclose(struct drm_device
* dev
);
2648 extern void i915_driver_preclose(struct drm_device
*dev
,
2649 struct drm_file
*file
);
2650 extern void i915_driver_postclose(struct drm_device
*dev
,
2651 struct drm_file
*file
);
2652 #ifdef CONFIG_COMPAT
2653 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2656 extern int intel_gpu_reset(struct drm_device
*dev
);
2657 extern bool intel_has_gpu_reset(struct drm_device
*dev
);
2658 extern int i915_reset(struct drm_device
*dev
);
2659 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2660 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2661 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2662 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2663 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2664 void i915_firmware_load_error_print(const char *fw_path
, int err
);
2666 /* intel_hotplug.c */
2667 void intel_hpd_irq_handler(struct drm_device
*dev
, u32 pin_mask
, u32 long_mask
);
2668 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2669 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2670 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2671 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2674 void i915_queue_hangcheck(struct drm_device
*dev
);
2676 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2677 const char *fmt
, ...);
2679 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2680 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2681 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2683 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2684 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2685 bool restore_forcewake
);
2686 extern void intel_uncore_init(struct drm_device
*dev
);
2687 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2688 extern void intel_uncore_fini(struct drm_device
*dev
);
2689 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2690 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2691 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2692 enum forcewake_domains domains
);
2693 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2694 enum forcewake_domains domains
);
2695 /* Like above but the caller must manage the uncore.lock itself.
2696 * Must be used with I915_READ_FW and friends.
2698 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2699 enum forcewake_domains domains
);
2700 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2701 enum forcewake_domains domains
);
2702 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2703 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2705 return to_i915(dev
)->vgpu
.active
;
2709 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2713 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2716 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2717 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2719 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2721 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2722 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2723 uint32_t interrupt_mask
,
2724 uint32_t enabled_irq_mask
);
2725 #define ibx_enable_display_interrupt(dev_priv, bits) \
2726 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2727 #define ibx_disable_display_interrupt(dev_priv, bits) \
2728 ibx_display_interrupt_update((dev_priv), (bits), 0)
2731 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2732 struct drm_file
*file_priv
);
2733 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2734 struct drm_file
*file_priv
);
2735 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2736 struct drm_file
*file_priv
);
2737 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2738 struct drm_file
*file_priv
);
2739 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2740 struct drm_file
*file_priv
);
2741 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2742 struct drm_file
*file_priv
);
2743 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2744 struct drm_file
*file_priv
);
2745 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2746 struct drm_i915_gem_request
*req
);
2747 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
);
2748 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
2749 struct drm_i915_gem_execbuffer2
*args
,
2750 struct list_head
*vmas
);
2751 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2752 struct drm_file
*file_priv
);
2753 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2754 struct drm_file
*file_priv
);
2755 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2756 struct drm_file
*file_priv
);
2757 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2758 struct drm_file
*file
);
2759 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2760 struct drm_file
*file
);
2761 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2762 struct drm_file
*file_priv
);
2763 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2764 struct drm_file
*file_priv
);
2765 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2766 struct drm_file
*file_priv
);
2767 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2768 struct drm_file
*file_priv
);
2769 int i915_gem_init_userptr(struct drm_device
*dev
);
2770 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2771 struct drm_file
*file
);
2772 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2773 struct drm_file
*file_priv
);
2774 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2775 struct drm_file
*file_priv
);
2776 void i915_gem_load(struct drm_device
*dev
);
2777 void *i915_gem_object_alloc(struct drm_device
*dev
);
2778 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2779 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2780 const struct drm_i915_gem_object_ops
*ops
);
2781 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2783 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2784 struct drm_device
*dev
, const void *data
, size_t size
);
2785 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2786 struct i915_address_space
*vm
);
2787 void i915_gem_free_object(struct drm_gem_object
*obj
);
2788 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2790 /* Flags used by pin/bind&friends. */
2791 #define PIN_MAPPABLE (1<<0)
2792 #define PIN_NONBLOCK (1<<1)
2793 #define PIN_GLOBAL (1<<2)
2794 #define PIN_OFFSET_BIAS (1<<3)
2795 #define PIN_USER (1<<4)
2796 #define PIN_UPDATE (1<<5)
2797 #define PIN_OFFSET_MASK (~4095)
2799 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2800 struct i915_address_space
*vm
,
2804 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2805 const struct i915_ggtt_view
*view
,
2809 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2811 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2812 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2813 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2814 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2816 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2817 int *needs_clflush
);
2819 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2821 static inline int __sg_page_count(struct scatterlist
*sg
)
2823 return sg
->length
>> PAGE_SHIFT
;
2826 static inline struct page
*
2827 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2829 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2832 if (n
< obj
->get_page
.last
) {
2833 obj
->get_page
.sg
= obj
->pages
->sgl
;
2834 obj
->get_page
.last
= 0;
2837 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2838 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2839 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2840 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2843 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2846 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2848 BUG_ON(obj
->pages
== NULL
);
2849 obj
->pages_pin_count
++;
2851 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2853 BUG_ON(obj
->pages_pin_count
== 0);
2854 obj
->pages_pin_count
--;
2857 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2858 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2859 struct intel_engine_cs
*to
,
2860 struct drm_i915_gem_request
**to_req
);
2861 void i915_vma_move_to_active(struct i915_vma
*vma
,
2862 struct drm_i915_gem_request
*req
);
2863 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2864 struct drm_device
*dev
,
2865 struct drm_mode_create_dumb
*args
);
2866 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2867 uint32_t handle
, uint64_t *offset
);
2869 * Returns true if seq1 is later than seq2.
2872 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2874 return (int32_t)(seq1
- seq2
) >= 0;
2877 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2878 bool lazy_coherency
)
2882 BUG_ON(req
== NULL
);
2884 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2886 return i915_seqno_passed(seqno
, req
->seqno
);
2889 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2890 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2892 struct drm_i915_gem_request
*
2893 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2895 bool i915_gem_retire_requests(struct drm_device
*dev
);
2896 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2897 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2898 bool interruptible
);
2900 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2902 return unlikely(atomic_read(&error
->reset_counter
)
2903 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2906 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2908 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2911 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2913 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2916 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2918 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2919 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2922 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2924 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2925 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2928 void i915_gem_reset(struct drm_device
*dev
);
2929 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2930 int __must_check
i915_gem_init(struct drm_device
*dev
);
2931 int i915_gem_init_rings(struct drm_device
*dev
);
2932 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2933 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
);
2934 void i915_gem_init_swizzling(struct drm_device
*dev
);
2935 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2936 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2937 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2938 void __i915_add_request(struct drm_i915_gem_request
*req
,
2939 struct drm_i915_gem_object
*batch_obj
,
2941 #define i915_add_request(req) \
2942 __i915_add_request(req, NULL, true)
2943 #define i915_add_request_no_flush(req) \
2944 __i915_add_request(req, NULL, false)
2945 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2946 unsigned reset_counter
,
2949 struct intel_rps_client
*rps
);
2950 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2951 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2953 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
2956 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2959 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2961 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2963 struct intel_engine_cs
*pipelined
,
2964 struct drm_i915_gem_request
**pipelined_request
,
2965 const struct i915_ggtt_view
*view
);
2966 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
2967 const struct i915_ggtt_view
*view
);
2968 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2970 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2971 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2974 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2976 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2977 int tiling_mode
, bool fenced
);
2979 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2980 enum i915_cache_level cache_level
);
2982 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2983 struct dma_buf
*dma_buf
);
2985 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2986 struct drm_gem_object
*gem_obj
, int flags
);
2989 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
2990 const struct i915_ggtt_view
*view
);
2992 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2993 struct i915_address_space
*vm
);
2994 static inline unsigned long
2995 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
2997 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3000 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3001 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3002 const struct i915_ggtt_view
*view
);
3003 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3004 struct i915_address_space
*vm
);
3006 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
3007 struct i915_address_space
*vm
);
3009 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3010 struct i915_address_space
*vm
);
3012 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3013 const struct i915_ggtt_view
*view
);
3016 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3017 struct i915_address_space
*vm
);
3019 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3020 const struct i915_ggtt_view
*view
);
3022 static inline struct i915_vma
*
3023 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3025 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3027 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3029 /* Some GGTT VM helpers */
3030 #define i915_obj_to_ggtt(obj) \
3031 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3032 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
3034 struct i915_address_space
*ggtt
=
3035 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
3039 static inline struct i915_hw_ppgtt
*
3040 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3042 WARN_ON(i915_is_ggtt(vm
));
3044 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3048 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3050 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3053 static inline unsigned long
3054 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3056 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
3059 static inline int __must_check
3060 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3064 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
3065 alignment
, flags
| PIN_GLOBAL
);
3069 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3071 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3074 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3075 const struct i915_ggtt_view
*view
);
3077 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3079 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3082 /* i915_gem_fence.c */
3083 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3084 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3086 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3087 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3089 void i915_gem_restore_fences(struct drm_device
*dev
);
3091 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3092 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3093 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3095 /* i915_gem_context.c */
3096 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3097 void i915_gem_context_fini(struct drm_device
*dev
);
3098 void i915_gem_context_reset(struct drm_device
*dev
);
3099 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3100 int i915_gem_context_enable(struct drm_i915_gem_request
*req
);
3101 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3102 int i915_switch_context(struct drm_i915_gem_request
*req
);
3103 struct intel_context
*
3104 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3105 void i915_gem_context_free(struct kref
*ctx_ref
);
3106 struct drm_i915_gem_object
*
3107 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3108 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3110 kref_get(&ctx
->ref
);
3113 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3115 kref_put(&ctx
->ref
, i915_gem_context_free
);
3118 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3120 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3123 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3124 struct drm_file
*file
);
3125 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3126 struct drm_file
*file
);
3127 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3128 struct drm_file
*file_priv
);
3129 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3130 struct drm_file
*file_priv
);
3132 /* i915_gem_evict.c */
3133 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3134 struct i915_address_space
*vm
,
3137 unsigned cache_level
,
3138 unsigned long start
,
3141 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3142 int i915_gem_evict_everything(struct drm_device
*dev
);
3144 /* belongs in i915_gem_gtt.h */
3145 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3147 if (INTEL_INFO(dev
)->gen
< 6)
3148 intel_gtt_chipset_flush();
3151 /* i915_gem_stolen.c */
3152 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3153 struct drm_mm_node
*node
, u64 size
,
3154 unsigned alignment
);
3155 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3156 struct drm_mm_node
*node
);
3157 int i915_gem_init_stolen(struct drm_device
*dev
);
3158 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3159 struct drm_i915_gem_object
*
3160 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3161 struct drm_i915_gem_object
*
3162 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3167 /* i915_gem_shrinker.c */
3168 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3171 #define I915_SHRINK_PURGEABLE 0x1
3172 #define I915_SHRINK_UNBOUND 0x2
3173 #define I915_SHRINK_BOUND 0x4
3174 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3175 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3178 /* i915_gem_tiling.c */
3179 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3181 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3183 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3184 obj
->tiling_mode
!= I915_TILING_NONE
;
3187 /* i915_gem_debug.c */
3189 int i915_verify_lists(struct drm_device
*dev
);
3191 #define i915_verify_lists(dev) 0
3194 /* i915_debugfs.c */
3195 int i915_debugfs_init(struct drm_minor
*minor
);
3196 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3197 #ifdef CONFIG_DEBUG_FS
3198 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3199 void intel_display_crc_init(struct drm_device
*dev
);
3201 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3203 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3206 /* i915_gpu_error.c */
3208 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3209 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3210 const struct i915_error_state_file_priv
*error
);
3211 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3212 struct drm_i915_private
*i915
,
3213 size_t count
, loff_t pos
);
3214 static inline void i915_error_state_buf_release(
3215 struct drm_i915_error_state_buf
*eb
)
3219 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3220 const char *error_msg
);
3221 void i915_error_state_get(struct drm_device
*dev
,
3222 struct i915_error_state_file_priv
*error_priv
);
3223 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3224 void i915_destroy_error_state(struct drm_device
*dev
);
3226 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3227 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3229 /* i915_cmd_parser.c */
3230 int i915_cmd_parser_get_version(void);
3231 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3232 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3233 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3234 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3235 struct drm_i915_gem_object
*batch_obj
,
3236 struct drm_i915_gem_object
*shadow_batch_obj
,
3237 u32 batch_start_offset
,
3241 /* i915_suspend.c */
3242 extern int i915_save_state(struct drm_device
*dev
);
3243 extern int i915_restore_state(struct drm_device
*dev
);
3246 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3247 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3250 extern int intel_setup_gmbus(struct drm_device
*dev
);
3251 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3252 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3255 extern struct i2c_adapter
*
3256 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3257 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3258 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3259 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3261 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3263 extern void intel_i2c_reset(struct drm_device
*dev
);
3265 /* intel_opregion.c */
3267 extern int intel_opregion_setup(struct drm_device
*dev
);
3268 extern void intel_opregion_init(struct drm_device
*dev
);
3269 extern void intel_opregion_fini(struct drm_device
*dev
);
3270 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3271 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3273 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3276 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3277 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3278 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3279 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3281 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3286 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3294 extern void intel_register_dsm_handler(void);
3295 extern void intel_unregister_dsm_handler(void);
3297 static inline void intel_register_dsm_handler(void) { return; }
3298 static inline void intel_unregister_dsm_handler(void) { return; }
3299 #endif /* CONFIG_ACPI */
3302 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3303 extern void intel_modeset_init(struct drm_device
*dev
);
3304 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3305 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3306 extern void intel_connector_unregister(struct intel_connector
*);
3307 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3308 extern void intel_display_resume(struct drm_device
*dev
);
3309 extern void i915_redisable_vga(struct drm_device
*dev
);
3310 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3311 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3312 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3313 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3314 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3316 extern void intel_detect_pch(struct drm_device
*dev
);
3317 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3318 extern int intel_enable_rc6(const struct drm_device
*dev
);
3320 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3321 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3322 struct drm_file
*file
);
3323 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3324 struct drm_file
*file
);
3327 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3328 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3329 struct intel_overlay_error_state
*error
);
3331 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3332 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3333 struct drm_device
*dev
,
3334 struct intel_display_error_state
*error
);
3336 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3337 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3339 /* intel_sideband.c */
3340 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3341 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3342 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3343 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3344 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3345 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3346 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3347 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3348 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3349 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3350 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3351 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3352 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3353 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3354 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3355 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3356 enum intel_sbi_destination destination
);
3357 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3358 enum intel_sbi_destination destination
);
3359 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3360 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3362 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3363 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3365 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3366 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3368 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3369 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3370 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3371 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3373 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3374 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3375 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3376 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3378 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3379 * will be implemented using 2 32-bit writes in an arbitrary order with
3380 * an arbitrary delay between them. This can cause the hardware to
3381 * act upon the intermediate value, possibly leading to corruption and
3382 * machine death. You have been warned.
3384 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3385 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3387 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3388 u32 upper, lower, old_upper, loop = 0; \
3389 upper = I915_READ(upper_reg); \
3391 old_upper = upper; \
3392 lower = I915_READ(lower_reg); \
3393 upper = I915_READ(upper_reg); \
3394 } while (upper != old_upper && loop++ < 2); \
3395 (u64)upper << 32 | lower; })
3397 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3398 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3400 /* These are untraced mmio-accessors that are only valid to be used inside
3401 * criticial sections inside IRQ handlers where forcewake is explicitly
3403 * Think twice, and think again, before using these.
3404 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3405 * intel_uncore_forcewake_irqunlock().
3407 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3408 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3409 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3411 /* "Broadcast RGB" property */
3412 #define INTEL_BROADCAST_RGB_AUTO 0
3413 #define INTEL_BROADCAST_RGB_FULL 1
3414 #define INTEL_BROADCAST_RGB_LIMITED 2
3416 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3418 if (IS_VALLEYVIEW(dev
))
3419 return VLV_VGACNTRL
;
3420 else if (INTEL_INFO(dev
)->gen
>= 5)
3421 return CPU_VGACNTRL
;
3426 static inline void __user
*to_user_ptr(u64 address
)
3428 return (void __user
*)(uintptr_t)address
;
3431 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3433 unsigned long j
= msecs_to_jiffies(m
);
3435 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3438 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3440 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3443 static inline unsigned long
3444 timespec_to_jiffies_timeout(const struct timespec
*value
)
3446 unsigned long j
= timespec_to_jiffies(value
);
3448 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3452 * If you need to wait X milliseconds between events A and B, but event B
3453 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3454 * when event A happened, then just before event B you call this function and
3455 * pass the timestamp as the first argument, and X as the second argument.
3458 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3460 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3463 * Don't re-read the value of "jiffies" every time since it may change
3464 * behind our back and break the math.
3466 tmp_jiffies
= jiffies
;
3467 target_jiffies
= timestamp_jiffies
+
3468 msecs_to_jiffies_timeout(to_wait_ms
);
3470 if (time_after(target_jiffies
, tmp_jiffies
)) {
3471 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3472 while (remaining_jiffies
)
3474 schedule_timeout_uninterruptible(remaining_jiffies
);
3478 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3479 struct drm_i915_gem_request
*req
)
3481 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3482 i915_gem_request_assign(&ring
->trace_irq_req
, req
);