1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
53 #include "i915_params.h"
56 #include "intel_bios.h"
57 #include "intel_dpll_mgr.h"
58 #include "intel_guc.h"
59 #include "intel_lrc.h"
60 #include "intel_ringbuffer.h"
63 #include "i915_gem_fence_reg.h"
64 #include "i915_gem_object.h"
65 #include "i915_gem_gtt.h"
66 #include "i915_gem_render_state.h"
67 #include "i915_gem_request.h"
68 #include "i915_gem_timeline.h"
72 #include "intel_gvt.h"
74 /* General customization:
77 #define DRIVER_NAME "i915"
78 #define DRIVER_DESC "Intel Graphics"
79 #define DRIVER_DATE "20161121"
80 #define DRIVER_TIMESTAMP 1479717903
83 /* Many gcc seem to no see through this and fall over :( */
85 #define WARN_ON(x) ({ \
86 bool __i915_warn_cond = (x); \
87 if (__builtin_constant_p(__i915_warn_cond)) \
88 BUILD_BUG_ON(__i915_warn_cond); \
89 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
91 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
95 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
97 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
98 (long) (x), __func__);
100 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
101 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
102 * which may not necessarily be a user visible problem. This will either
103 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
104 * enable distros and users to tailor their preferred amount of i915 abrt
107 #define I915_STATE_WARN(condition, format...) ({ \
108 int __ret_warn_on = !!(condition); \
109 if (unlikely(__ret_warn_on)) \
110 if (!WARN(i915.verbose_state_checks, format)) \
112 unlikely(__ret_warn_on); \
115 #define I915_STATE_WARN_ON(x) \
116 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
118 bool __i915_inject_load_failure(const char *func
, int line
);
119 #define i915_inject_load_failure() \
120 __i915_inject_load_failure(__func__, __LINE__)
122 static inline const char *yesno(bool v
)
124 return v
? "yes" : "no";
127 static inline const char *onoff(bool v
)
129 return v
? "on" : "off";
132 static inline const char *enableddisabled(bool v
)
134 return v
? "enabled" : "disabled";
143 I915_MAX_PIPES
= _PIPE_EDP
145 #define pipe_name(p) ((p) + 'A')
157 static inline const char *transcoder_name(enum transcoder transcoder
)
159 switch (transcoder
) {
168 case TRANSCODER_DSI_A
:
170 case TRANSCODER_DSI_C
:
177 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
179 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
183 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
184 * number of planes per CRTC. Not all platforms really have this many planes,
185 * which means some arrays of size I915_MAX_PLANES may have unused entries
186 * between the topmost sprite plane and the cursor plane.
195 #define plane_name(p) ((p) + 'A')
197 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
208 #define port_name(p) ((p) + 'A')
210 #define I915_NUM_PHYS_VLV 2
222 enum intel_display_power_domain
{
226 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
227 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
228 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
229 POWER_DOMAIN_TRANSCODER_A
,
230 POWER_DOMAIN_TRANSCODER_B
,
231 POWER_DOMAIN_TRANSCODER_C
,
232 POWER_DOMAIN_TRANSCODER_EDP
,
233 POWER_DOMAIN_TRANSCODER_DSI_A
,
234 POWER_DOMAIN_TRANSCODER_DSI_C
,
235 POWER_DOMAIN_PORT_DDI_A_LANES
,
236 POWER_DOMAIN_PORT_DDI_B_LANES
,
237 POWER_DOMAIN_PORT_DDI_C_LANES
,
238 POWER_DOMAIN_PORT_DDI_D_LANES
,
239 POWER_DOMAIN_PORT_DDI_E_LANES
,
240 POWER_DOMAIN_PORT_DSI
,
241 POWER_DOMAIN_PORT_CRT
,
242 POWER_DOMAIN_PORT_OTHER
,
251 POWER_DOMAIN_MODESET
,
257 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
258 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
259 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
260 #define POWER_DOMAIN_TRANSCODER(tran) \
261 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
262 (tran) + POWER_DOMAIN_TRANSCODER_A)
266 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
278 #define for_each_hpd_pin(__pin) \
279 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
281 struct i915_hotplug
{
282 struct work_struct hotplug_work
;
285 unsigned long last_jiffies
;
290 HPD_MARK_DISABLED
= 2
292 } stats
[HPD_NUM_PINS
];
294 struct delayed_work reenable_work
;
296 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
299 struct work_struct dig_port_work
;
301 struct work_struct poll_init_work
;
305 * if we get a HPD irq from DP and a HPD irq from non-DP
306 * the non-DP HPD could block the workqueue on a mode config
307 * mutex getting, that userspace may have taken. However
308 * userspace is waiting on the DP workqueue to run which is
309 * blocked behind the non-DP one.
311 struct workqueue_struct
*dp_wq
;
314 #define I915_GEM_GPU_DOMAINS \
315 (I915_GEM_DOMAIN_RENDER | \
316 I915_GEM_DOMAIN_SAMPLER | \
317 I915_GEM_DOMAIN_COMMAND | \
318 I915_GEM_DOMAIN_INSTRUCTION | \
319 I915_GEM_DOMAIN_VERTEX)
321 #define for_each_pipe(__dev_priv, __p) \
322 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
323 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
324 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
325 for_each_if ((__mask) & (1 << (__p)))
326 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
328 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
330 #define for_each_sprite(__dev_priv, __p, __s) \
332 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
335 #define for_each_port_masked(__port, __ports_mask) \
336 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
337 for_each_if ((__ports_mask) & (1 << (__port)))
339 #define for_each_crtc(dev, crtc) \
340 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
342 #define for_each_intel_plane(dev, intel_plane) \
343 list_for_each_entry(intel_plane, \
344 &(dev)->mode_config.plane_list, \
347 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
348 list_for_each_entry(intel_plane, \
349 &(dev)->mode_config.plane_list, \
351 for_each_if ((plane_mask) & \
352 (1 << drm_plane_index(&intel_plane->base)))
354 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
355 list_for_each_entry(intel_plane, \
356 &(dev)->mode_config.plane_list, \
358 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
360 #define for_each_intel_crtc(dev, intel_crtc) \
361 list_for_each_entry(intel_crtc, \
362 &(dev)->mode_config.crtc_list, \
365 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
366 list_for_each_entry(intel_crtc, \
367 &(dev)->mode_config.crtc_list, \
369 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
371 #define for_each_intel_encoder(dev, intel_encoder) \
372 list_for_each_entry(intel_encoder, \
373 &(dev)->mode_config.encoder_list, \
376 #define for_each_intel_connector(dev, intel_connector) \
377 list_for_each_entry(intel_connector, \
378 &(dev)->mode_config.connector_list, \
381 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
382 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
383 for_each_if ((intel_encoder)->base.crtc == (__crtc))
385 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
386 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
387 for_each_if ((intel_connector)->base.encoder == (__encoder))
389 #define for_each_power_domain(domain, mask) \
390 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
391 for_each_if ((1 << (domain)) & (mask))
393 struct drm_i915_private
;
394 struct i915_mm_struct
;
395 struct i915_mmu_object
;
397 struct drm_i915_file_private
{
398 struct drm_i915_private
*dev_priv
;
399 struct drm_file
*file
;
403 struct list_head request_list
;
404 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
405 * chosen to prevent the CPU getting more than a frame ahead of the GPU
406 * (when using lax throttling for the frontbuffer). We also use it to
407 * offer free GPU waitboosts for severely congested workloads.
409 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
411 struct idr context_idr
;
413 struct intel_rps_client
{
414 struct list_head link
;
418 unsigned int bsd_engine
;
420 /* Client can have a maximum of 3 contexts banned before
421 * it is denied of creating new contexts. As one context
422 * ban needs 4 consecutive hangs, and more if there is
423 * progress in between, this is a last resort stop gap measure
424 * to limit the badly behaving clients access to gpu.
426 #define I915_MAX_CLIENT_CONTEXT_BANS 3
430 /* Used by dp and fdi links */
431 struct intel_link_m_n
{
439 void intel_link_compute_m_n(int bpp
, int nlanes
,
440 int pixel_clock
, int link_clock
,
441 struct intel_link_m_n
*m_n
);
443 /* Interface history:
446 * 1.2: Add Power Management
447 * 1.3: Add vblank support
448 * 1.4: Fix cmdbuffer path, add heap destroy
449 * 1.5: Add vblank pipe configuration
450 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
451 * - Support vertical blank on secondary display pipe
453 #define DRIVER_MAJOR 1
454 #define DRIVER_MINOR 6
455 #define DRIVER_PATCHLEVEL 0
457 struct opregion_header
;
458 struct opregion_acpi
;
459 struct opregion_swsci
;
460 struct opregion_asle
;
462 struct intel_opregion
{
463 struct opregion_header
*header
;
464 struct opregion_acpi
*acpi
;
465 struct opregion_swsci
*swsci
;
466 u32 swsci_gbda_sub_functions
;
467 u32 swsci_sbcb_sub_functions
;
468 struct opregion_asle
*asle
;
473 struct work_struct asle_work
;
475 #define OPREGION_SIZE (8*1024)
477 struct intel_overlay
;
478 struct intel_overlay_error_state
;
480 struct sdvo_device_mapping
{
489 struct intel_connector
;
490 struct intel_encoder
;
491 struct intel_atomic_state
;
492 struct intel_crtc_state
;
493 struct intel_initial_plane_config
;
498 struct drm_i915_display_funcs
{
499 int (*get_display_clock_speed
)(struct drm_i915_private
*dev_priv
);
500 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
501 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
502 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
503 struct intel_crtc
*intel_crtc
,
504 struct intel_crtc_state
*newstate
);
505 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
506 struct intel_crtc_state
*cstate
);
507 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
508 struct intel_crtc_state
*cstate
);
509 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
510 struct intel_crtc_state
*cstate
);
511 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
512 void (*update_wm
)(struct intel_crtc
*crtc
);
513 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
514 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
515 /* Returns the active state of the crtc, and if the crtc is active,
516 * fills out the pipe-config with the hw state. */
517 bool (*get_pipe_config
)(struct intel_crtc
*,
518 struct intel_crtc_state
*);
519 void (*get_initial_plane_config
)(struct intel_crtc
*,
520 struct intel_initial_plane_config
*);
521 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
522 struct intel_crtc_state
*crtc_state
);
523 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
524 struct drm_atomic_state
*old_state
);
525 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
526 struct drm_atomic_state
*old_state
);
527 void (*update_crtcs
)(struct drm_atomic_state
*state
,
528 unsigned int *crtc_vblank_mask
);
529 void (*audio_codec_enable
)(struct drm_connector
*connector
,
530 struct intel_encoder
*encoder
,
531 const struct drm_display_mode
*adjusted_mode
);
532 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
533 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
534 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
535 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
536 struct drm_framebuffer
*fb
,
537 struct drm_i915_gem_object
*obj
,
538 struct drm_i915_gem_request
*req
,
540 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
541 /* clock updates for mode set */
543 /* render clock increase/decrease */
544 /* display clock increase/decrease */
545 /* pll clock increase/decrease */
547 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
548 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
551 enum forcewake_domain_id
{
552 FW_DOMAIN_ID_RENDER
= 0,
553 FW_DOMAIN_ID_BLITTER
,
559 enum forcewake_domains
{
560 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
561 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
562 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
563 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
568 #define FW_REG_READ (1)
569 #define FW_REG_WRITE (2)
571 enum decoupled_power_domain
{
572 GEN9_DECOUPLED_PD_BLITTER
= 0,
573 GEN9_DECOUPLED_PD_RENDER
,
574 GEN9_DECOUPLED_PD_MEDIA
,
575 GEN9_DECOUPLED_PD_ALL
579 GEN9_DECOUPLED_OP_WRITE
= 0,
580 GEN9_DECOUPLED_OP_READ
583 enum forcewake_domains
584 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
585 i915_reg_t reg
, unsigned int op
);
587 struct intel_uncore_funcs
{
588 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
589 enum forcewake_domains domains
);
590 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
591 enum forcewake_domains domains
);
593 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
594 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
595 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
596 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
598 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
599 uint8_t val
, bool trace
);
600 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
601 uint16_t val
, bool trace
);
602 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
603 uint32_t val
, bool trace
);
606 struct intel_forcewake_range
{
610 enum forcewake_domains domains
;
613 struct intel_uncore
{
614 spinlock_t lock
; /** lock is also taken in irq contexts. */
616 const struct intel_forcewake_range
*fw_domains_table
;
617 unsigned int fw_domains_table_entries
;
619 struct intel_uncore_funcs funcs
;
623 enum forcewake_domains fw_domains
;
624 enum forcewake_domains fw_domains_active
;
626 struct intel_uncore_forcewake_domain
{
627 struct drm_i915_private
*i915
;
628 enum forcewake_domain_id id
;
629 enum forcewake_domains mask
;
631 struct hrtimer timer
;
638 } fw_domain
[FW_DOMAIN_ID_COUNT
];
640 int unclaimed_mmio_check
;
643 /* Iterate over initialised fw domains */
644 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
645 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
646 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
648 for_each_if ((mask__) & (domain__)->mask)
650 #define for_each_fw_domain(domain__, dev_priv__) \
651 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
653 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
654 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
655 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
658 struct work_struct work
;
660 uint32_t *dmc_payload
;
661 uint32_t dmc_fw_size
;
664 i915_reg_t mmioaddr
[8];
665 uint32_t mmiodata
[8];
667 uint32_t allowed_dc_mask
;
670 #define DEV_INFO_FOR_EACH_FLAG(func) \
671 /* Keep is_* in chronological order */ \
679 func(is_broadwater); \
680 func(is_crestline); \
681 func(is_ivybridge); \
682 func(is_valleyview); \
683 func(is_cherryview); \
685 func(is_broadwell); \
689 func(is_alpha_support); \
690 /* Keep has_* in alphabetical order */ \
691 func(has_64bit_reloc); \
696 func(has_fpga_dbg); \
697 func(has_gmbus_irq); \
698 func(has_gmch_display); \
701 func(has_hw_contexts); \
704 func(has_logical_ring_contexts); \
706 func(has_pipe_cxsr); \
707 func(has_pooled_eu); \
711 func(has_resource_streamer); \
712 func(has_runtime_pm); \
714 func(cursor_needs_physical); \
715 func(hws_needs_physical); \
716 func(overlay_needs_physical); \
718 func(has_decoupled_mmio)
720 struct sseu_dev_info
{
726 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
729 u8 has_subslice_pg
:1;
733 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
735 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
738 struct intel_device_info
{
739 u32 display_mmio_offset
;
742 u8 num_sprites
[I915_MAX_PIPES
];
745 u8 ring_mask
; /* Rings supported by the HW */
747 #define DEFINE_FLAG(name) u8 name:1
748 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
750 u16 ddb_size
; /* in blocks */
751 /* Register offsets for the various display pipes and transcoders */
752 int pipe_offsets
[I915_MAX_TRANSCODERS
];
753 int trans_offsets
[I915_MAX_TRANSCODERS
];
754 int palette_offsets
[I915_MAX_PIPES
];
755 int cursor_offsets
[I915_MAX_PIPES
];
757 /* Slice/subslice/EU info */
758 struct sseu_dev_info sseu
;
761 u16 degamma_lut_size
;
766 struct intel_display_error_state
;
768 struct drm_i915_error_state
{
771 struct timeval boottime
;
772 struct timeval uptime
;
774 struct drm_i915_private
*i915
;
781 struct intel_device_info device_info
;
783 /* Generic register state */
791 u32 error
; /* gen6+ */
792 u32 err_int
; /* gen7 */
793 u32 fault_data0
; /* gen8, gen9 */
794 u32 fault_data1
; /* gen8, gen9 */
801 u64 fence
[I915_MAX_NUM_FENCES
];
802 struct intel_overlay_error_state
*overlay
;
803 struct intel_display_error_state
*display
;
804 struct drm_i915_error_object
*semaphore
;
805 struct drm_i915_error_object
*guc_log
;
807 struct drm_i915_error_engine
{
809 /* Software tracked state */
812 unsigned long hangcheck_timestamp
;
813 bool hangcheck_stalled
;
814 enum intel_engine_hangcheck_action hangcheck_action
;
815 struct i915_address_space
*vm
;
818 /* position of active request inside the ring */
819 u32 rq_head
, rq_post
, rq_tail
;
821 /* our own tracking of ring head and tail */
844 u32 rc_psmi
; /* sleep state */
845 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
846 struct intel_instdone instdone
;
848 struct drm_i915_error_object
{
854 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
856 struct drm_i915_error_object
*wa_ctx
;
858 struct drm_i915_error_request
{
866 } *requests
, execlist
[2];
868 struct drm_i915_error_waiter
{
869 char comm
[TASK_COMM_LEN
];
883 char comm
[TASK_COMM_LEN
];
885 } engine
[I915_NUM_ENGINES
];
887 struct drm_i915_error_buffer
{
890 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
894 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
901 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
902 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
903 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
906 enum i915_cache_level
{
908 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
909 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
910 caches, eg sampler/render caches, and the
911 large Last-Level-Cache. LLC is coherent with
912 the CPU, but L3 is only visible to the GPU. */
913 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
916 struct i915_ctx_hang_stats
{
917 /* This context had batch pending when hang was declared */
918 unsigned batch_pending
;
920 /* This context had batch active when hang was declared */
921 unsigned batch_active
;
925 /* This context is banned to submit more work */
928 #define CONTEXT_SCORE_GUILTY 10
929 #define CONTEXT_SCORE_BAN_THRESHOLD 40
930 /* Accumulated score of hangs caused by this context */
934 /* This must match up with the value previously used for execbuf2.rsvd1. */
935 #define DEFAULT_CONTEXT_HANDLE 0
938 * struct i915_gem_context - as the name implies, represents a context.
939 * @ref: reference count.
940 * @user_handle: userspace tracking identity for this context.
941 * @remap_slice: l3 row remapping information.
942 * @flags: context specific flags:
943 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
944 * @file_priv: filp associated with this context (NULL for global default
946 * @hang_stats: information about the role of this context in possible GPU
948 * @ppgtt: virtual memory space used by this context.
949 * @legacy_hw_ctx: render context backing object and whether it is correctly
950 * initialized (legacy ring submission mechanism only).
951 * @link: link in the global list of contexts.
953 * Contexts are memory images used by the hardware to store copies of their
956 struct i915_gem_context
{
958 struct drm_i915_private
*i915
;
959 struct drm_i915_file_private
*file_priv
;
960 struct i915_hw_ppgtt
*ppgtt
;
964 struct i915_ctx_hang_stats hang_stats
;
967 #define CONTEXT_NO_ZEROMAP BIT(0)
968 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
970 /* Unique identifier for this context, used by the hw for tracking */
973 int priority
; /* greater priorities are serviced first */
977 struct intel_context
{
978 struct i915_vma
*state
;
979 struct intel_ring
*ring
;
980 uint32_t *lrc_reg_state
;
984 } engine
[I915_NUM_ENGINES
];
987 struct atomic_notifier_head status_notifier
;
988 bool execlists_force_single_submission
;
990 struct list_head link
;
1005 /* This is always the inner lock when overlapping with struct_mutex and
1006 * it's the outer lock when overlapping with stolen_lock. */
1009 unsigned int possible_framebuffer_bits
;
1010 unsigned int busy_bits
;
1011 unsigned int visible_pipes_mask
;
1012 struct intel_crtc
*crtc
;
1014 struct drm_mm_node compressed_fb
;
1015 struct drm_mm_node
*compressed_llb
;
1022 bool underrun_detected
;
1023 struct work_struct underrun_work
;
1025 struct intel_fbc_state_cache
{
1027 unsigned int mode_flags
;
1028 uint32_t hsw_bdw_pixel_rate
;
1032 unsigned int rotation
;
1039 u64 ilk_ggtt_offset
;
1040 uint32_t pixel_format
;
1041 unsigned int stride
;
1043 unsigned int tiling_mode
;
1047 struct intel_fbc_reg_params
{
1051 unsigned int fence_y_offset
;
1056 uint32_t pixel_format
;
1057 unsigned int stride
;
1064 struct intel_fbc_work
{
1066 u32 scheduled_vblank
;
1067 struct work_struct work
;
1070 const char *no_fbc_reason
;
1074 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1075 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1076 * parsing for same resolution.
1078 enum drrs_refresh_rate_type
{
1081 DRRS_MAX_RR
, /* RR count */
1084 enum drrs_support_type
{
1085 DRRS_NOT_SUPPORTED
= 0,
1086 STATIC_DRRS_SUPPORT
= 1,
1087 SEAMLESS_DRRS_SUPPORT
= 2
1093 struct delayed_work work
;
1094 struct intel_dp
*dp
;
1095 unsigned busy_frontbuffer_bits
;
1096 enum drrs_refresh_rate_type refresh_rate_type
;
1097 enum drrs_support_type type
;
1104 struct intel_dp
*enabled
;
1106 struct delayed_work work
;
1107 unsigned busy_frontbuffer_bits
;
1109 bool aux_frame_sync
;
1114 PCH_NONE
= 0, /* No PCH present */
1115 PCH_IBX
, /* Ibexpeak PCH */
1116 PCH_CPT
, /* Cougarpoint PCH */
1117 PCH_LPT
, /* Lynxpoint PCH */
1118 PCH_SPT
, /* Sunrisepoint PCH */
1119 PCH_KBP
, /* Kabypoint PCH */
1123 enum intel_sbi_destination
{
1128 #define QUIRK_PIPEA_FORCE (1<<0)
1129 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1130 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1131 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1132 #define QUIRK_PIPEB_FORCE (1<<4)
1133 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1136 struct intel_fbc_work
;
1138 struct intel_gmbus
{
1139 struct i2c_adapter adapter
;
1140 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1143 i915_reg_t gpio_reg
;
1144 struct i2c_algo_bit_data bit_algo
;
1145 struct drm_i915_private
*dev_priv
;
1148 struct i915_suspend_saved_registers
{
1150 u32 saveFBC_CONTROL
;
1151 u32 saveCACHE_MODE_0
;
1152 u32 saveMI_ARB_STATE
;
1156 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1157 u32 savePCH_PORT_HOTPLUG
;
1161 struct vlv_s0ix_state
{
1168 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1169 u32 media_max_req_count
;
1170 u32 gfx_max_req_count
;
1196 u32 rp_down_timeout
;
1202 /* Display 1 CZ domain */
1207 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1209 /* GT SA CZ domain */
1216 /* Display 2 CZ domain */
1220 u32 clock_gate_dis2
;
1223 struct intel_rps_ei
{
1229 struct intel_gen6_power_mgmt
{
1231 * work, interrupts_enabled and pm_iir are protected by
1232 * dev_priv->irq_lock
1234 struct work_struct work
;
1235 bool interrupts_enabled
;
1238 /* PM interrupt bits that should never be masked */
1241 /* Frequencies are stored in potentially platform dependent multiples.
1242 * In other words, *_freq needs to be multiplied by X to be interesting.
1243 * Soft limits are those which are used for the dynamic reclocking done
1244 * by the driver (raise frequencies under heavy loads, and lower for
1245 * lighter loads). Hard limits are those imposed by the hardware.
1247 * A distinction is made for overclocking, which is never enabled by
1248 * default, and is considered to be above the hard limit if it's
1251 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1252 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1253 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1254 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1255 u8 min_freq
; /* AKA RPn. Minimum frequency */
1256 u8 boost_freq
; /* Frequency to request when wait boosting */
1257 u8 idle_freq
; /* Frequency to request when we are idle */
1258 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1259 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1260 u8 rp0_freq
; /* Non-overclocked max frequency. */
1261 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1263 u8 up_threshold
; /* Current %busy required to uplock */
1264 u8 down_threshold
; /* Current %busy required to downclock */
1267 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1269 spinlock_t client_lock
;
1270 struct list_head clients
;
1274 struct delayed_work autoenable_work
;
1277 /* manual wa residency calculations */
1278 struct intel_rps_ei up_ei
, down_ei
;
1281 * Protects RPS/RC6 register access and PCU communication.
1282 * Must be taken after struct_mutex if nested. Note that
1283 * this lock may be held for long periods of time when
1284 * talking to hw - so only take it when talking to hw!
1286 struct mutex hw_lock
;
1289 /* defined intel_pm.c */
1290 extern spinlock_t mchdev_lock
;
1292 struct intel_ilk_power_mgmt
{
1300 unsigned long last_time1
;
1301 unsigned long chipset_power
;
1304 unsigned long gfx_power
;
1311 struct drm_i915_private
;
1312 struct i915_power_well
;
1314 struct i915_power_well_ops
{
1316 * Synchronize the well's hw state to match the current sw state, for
1317 * example enable/disable it based on the current refcount. Called
1318 * during driver init and resume time, possibly after first calling
1319 * the enable/disable handlers.
1321 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1322 struct i915_power_well
*power_well
);
1324 * Enable the well and resources that depend on it (for example
1325 * interrupts located on the well). Called after the 0->1 refcount
1328 void (*enable
)(struct drm_i915_private
*dev_priv
,
1329 struct i915_power_well
*power_well
);
1331 * Disable the well and resources that depend on it. Called after
1332 * the 1->0 refcount transition.
1334 void (*disable
)(struct drm_i915_private
*dev_priv
,
1335 struct i915_power_well
*power_well
);
1336 /* Returns the hw enabled state. */
1337 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1338 struct i915_power_well
*power_well
);
1341 /* Power well structure for haswell */
1342 struct i915_power_well
{
1345 /* power well enable/disable usage count */
1347 /* cached hw enabled state */
1349 unsigned long domains
;
1350 /* unique identifier for this power well */
1353 * Arbitraty data associated with this power well. Platform and power
1357 const struct i915_power_well_ops
*ops
;
1360 struct i915_power_domains
{
1362 * Power wells needed for initialization at driver init and suspend
1363 * time are on. They are kept on until after the first modeset.
1367 int power_well_count
;
1370 int domain_use_count
[POWER_DOMAIN_NUM
];
1371 struct i915_power_well
*power_wells
;
1374 #define MAX_L3_SLICES 2
1375 struct intel_l3_parity
{
1376 u32
*remap_info
[MAX_L3_SLICES
];
1377 struct work_struct error_work
;
1381 struct i915_gem_mm
{
1382 /** Memory allocator for GTT stolen memory */
1383 struct drm_mm stolen
;
1384 /** Protects the usage of the GTT stolen memory allocator. This is
1385 * always the inner lock when overlapping with struct_mutex. */
1386 struct mutex stolen_lock
;
1388 /** List of all objects in gtt_space. Used to restore gtt
1389 * mappings on resume */
1390 struct list_head bound_list
;
1392 * List of objects which are not bound to the GTT (thus
1393 * are idle and not used by the GPU). These objects may or may
1394 * not actually have any pages attached.
1396 struct list_head unbound_list
;
1398 /** List of all objects in gtt_space, currently mmaped by userspace.
1399 * All objects within this list must also be on bound_list.
1401 struct list_head userfault_list
;
1404 * List of objects which are pending destruction.
1406 struct llist_head free_list
;
1407 struct work_struct free_work
;
1409 /** Usable portion of the GTT for GEM */
1410 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1412 /** PPGTT used for aliasing the PPGTT with the GTT */
1413 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1415 struct notifier_block oom_notifier
;
1416 struct notifier_block vmap_notifier
;
1417 struct shrinker shrinker
;
1419 /** LRU list of objects with fence regs on them. */
1420 struct list_head fence_list
;
1423 * Are we in a non-interruptible section of code like
1428 /* the indicator for dispatch video commands on two BSD rings */
1429 atomic_t bsd_engine_dispatch_index
;
1431 /** Bit 6 swizzling required for X tiling */
1432 uint32_t bit_6_swizzle_x
;
1433 /** Bit 6 swizzling required for Y tiling */
1434 uint32_t bit_6_swizzle_y
;
1436 /* accounting, useful for userland debugging */
1437 spinlock_t object_stat_lock
;
1442 struct drm_i915_error_state_buf
{
1443 struct drm_i915_private
*i915
;
1452 struct i915_error_state_file_priv
{
1453 struct drm_device
*dev
;
1454 struct drm_i915_error_state
*error
;
1457 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1458 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1460 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1461 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1463 struct i915_gpu_error
{
1464 /* For hangcheck timer */
1465 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1466 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1468 struct delayed_work hangcheck_work
;
1470 /* For reset and error_state handling. */
1472 /* Protected by the above dev->gpu_error.lock. */
1473 struct drm_i915_error_state
*first_error
;
1475 unsigned long missed_irq_rings
;
1478 * State variable controlling the reset flow and count
1480 * This is a counter which gets incremented when reset is triggered,
1482 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
1483 * meaning that any waiters holding onto the struct_mutex should
1484 * relinquish the lock immediately in order for the reset to start.
1486 * If reset is not completed succesfully, the I915_WEDGE bit is
1487 * set meaning that hardware is terminally sour and there is no
1488 * recovery. All waiters on the reset_queue will be woken when
1491 * This counter is used by the wait_seqno code to notice that reset
1492 * event happened and it needs to restart the entire ioctl (since most
1493 * likely the seqno it waited for won't ever signal anytime soon).
1495 * This is important for lock-free wait paths, where no contended lock
1496 * naturally enforces the correct ordering between the bail-out of the
1497 * waiter and the gpu reset work code.
1499 unsigned long reset_count
;
1501 unsigned long flags
;
1502 #define I915_RESET_IN_PROGRESS 0
1503 #define I915_WEDGED (BITS_PER_LONG - 1)
1506 * Waitqueue to signal when a hang is detected. Used to for waiters
1507 * to release the struct_mutex for the reset to procede.
1509 wait_queue_head_t wait_queue
;
1512 * Waitqueue to signal when the reset has completed. Used by clients
1513 * that wait for dev_priv->mm.wedged to settle.
1515 wait_queue_head_t reset_queue
;
1517 /* For missed irq/seqno simulation. */
1518 unsigned long test_irq_rings
;
1521 enum modeset_restore
{
1522 MODESET_ON_LID_OPEN
,
1527 #define DP_AUX_A 0x40
1528 #define DP_AUX_B 0x10
1529 #define DP_AUX_C 0x20
1530 #define DP_AUX_D 0x30
1532 #define DDC_PIN_B 0x05
1533 #define DDC_PIN_C 0x04
1534 #define DDC_PIN_D 0x06
1536 struct ddi_vbt_port_info
{
1538 * This is an index in the HDMI/DVI DDI buffer translation table.
1539 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1540 * populate this field.
1542 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1543 uint8_t hdmi_level_shift
;
1545 uint8_t supports_dvi
:1;
1546 uint8_t supports_hdmi
:1;
1547 uint8_t supports_dp
:1;
1549 uint8_t alternate_aux_channel
;
1550 uint8_t alternate_ddc_pin
;
1552 uint8_t dp_boost_level
;
1553 uint8_t hdmi_boost_level
;
1556 enum psr_lines_to_wait
{
1557 PSR_0_LINES_TO_WAIT
= 0,
1559 PSR_4_LINES_TO_WAIT
,
1563 struct intel_vbt_data
{
1564 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1565 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1568 unsigned int int_tv_support
:1;
1569 unsigned int lvds_dither
:1;
1570 unsigned int lvds_vbt
:1;
1571 unsigned int int_crt_support
:1;
1572 unsigned int lvds_use_ssc
:1;
1573 unsigned int display_clock_mode
:1;
1574 unsigned int fdi_rx_polarity_inverted
:1;
1575 unsigned int panel_type
:4;
1577 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1579 enum drrs_support_type drrs_type
;
1590 struct edp_power_seq pps
;
1595 bool require_aux_wakeup
;
1597 enum psr_lines_to_wait lines_to_wait
;
1598 int tp1_wakeup_time
;
1599 int tp2_tp3_wakeup_time
;
1605 bool active_low_pwm
;
1606 u8 min_brightness
; /* min_brightness/255 of max */
1607 enum intel_backlight_type type
;
1613 struct mipi_config
*config
;
1614 struct mipi_pps_data
*pps
;
1618 const u8
*sequence
[MIPI_SEQ_MAX
];
1624 union child_device_config
*child_dev
;
1626 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1627 struct sdvo_device_mapping sdvo_mappings
[2];
1630 enum intel_ddb_partitioning
{
1632 INTEL_DDB_PART_5_6
, /* IVB+ */
1635 struct intel_wm_level
{
1643 struct ilk_wm_values
{
1644 uint32_t wm_pipe
[3];
1646 uint32_t wm_lp_spr
[3];
1647 uint32_t wm_linetime
[3];
1649 enum intel_ddb_partitioning partitioning
;
1652 struct vlv_pipe_wm
{
1663 struct vlv_wm_values
{
1664 struct vlv_pipe_wm pipe
[3];
1665 struct vlv_sr_wm sr
;
1675 struct skl_ddb_entry
{
1676 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1679 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1681 return entry
->end
- entry
->start
;
1684 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1685 const struct skl_ddb_entry
*e2
)
1687 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1693 struct skl_ddb_allocation
{
1694 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1695 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1698 struct skl_wm_values
{
1699 unsigned dirty_pipes
;
1700 struct skl_ddb_allocation ddb
;
1703 struct skl_wm_level
{
1705 uint16_t plane_res_b
;
1706 uint8_t plane_res_l
;
1710 * This struct helps tracking the state needed for runtime PM, which puts the
1711 * device in PCI D3 state. Notice that when this happens, nothing on the
1712 * graphics device works, even register access, so we don't get interrupts nor
1715 * Every piece of our code that needs to actually touch the hardware needs to
1716 * either call intel_runtime_pm_get or call intel_display_power_get with the
1717 * appropriate power domain.
1719 * Our driver uses the autosuspend delay feature, which means we'll only really
1720 * suspend if we stay with zero refcount for a certain amount of time. The
1721 * default value is currently very conservative (see intel_runtime_pm_enable), but
1722 * it can be changed with the standard runtime PM files from sysfs.
1724 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1725 * goes back to false exactly before we reenable the IRQs. We use this variable
1726 * to check if someone is trying to enable/disable IRQs while they're supposed
1727 * to be disabled. This shouldn't happen and we'll print some error messages in
1730 * For more, read the Documentation/power/runtime_pm.txt.
1732 struct i915_runtime_pm
{
1733 atomic_t wakeref_count
;
1738 enum intel_pipe_crc_source
{
1739 INTEL_PIPE_CRC_SOURCE_NONE
,
1740 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1741 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1742 INTEL_PIPE_CRC_SOURCE_PF
,
1743 INTEL_PIPE_CRC_SOURCE_PIPE
,
1744 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1745 INTEL_PIPE_CRC_SOURCE_TV
,
1746 INTEL_PIPE_CRC_SOURCE_DP_B
,
1747 INTEL_PIPE_CRC_SOURCE_DP_C
,
1748 INTEL_PIPE_CRC_SOURCE_DP_D
,
1749 INTEL_PIPE_CRC_SOURCE_AUTO
,
1750 INTEL_PIPE_CRC_SOURCE_MAX
,
1753 struct intel_pipe_crc_entry
{
1758 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1759 struct intel_pipe_crc
{
1761 bool opened
; /* exclusive access to the result file */
1762 struct intel_pipe_crc_entry
*entries
;
1763 enum intel_pipe_crc_source source
;
1765 wait_queue_head_t wq
;
1768 struct i915_frontbuffer_tracking
{
1772 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1779 struct i915_wa_reg
{
1782 /* bitmask representing WA bits */
1787 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1788 * allowing it for RCS as we don't foresee any requirement of having
1789 * a whitelist for other engines. When it is really required for
1790 * other engines then the limit need to be increased.
1792 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1794 struct i915_workarounds
{
1795 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1797 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1800 struct i915_virtual_gpu
{
1804 /* used in computing the new watermarks state */
1805 struct intel_wm_config
{
1806 unsigned int num_pipes_active
;
1807 bool sprites_enabled
;
1808 bool sprites_scaled
;
1811 struct drm_i915_private
{
1812 struct drm_device drm
;
1814 struct kmem_cache
*objects
;
1815 struct kmem_cache
*vmas
;
1816 struct kmem_cache
*requests
;
1817 struct kmem_cache
*dependencies
;
1819 const struct intel_device_info info
;
1821 int relative_constants_mode
;
1825 struct intel_uncore uncore
;
1827 struct i915_virtual_gpu vgpu
;
1829 struct intel_gvt
*gvt
;
1831 struct intel_guc guc
;
1833 struct intel_csr csr
;
1835 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1837 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1838 * controller on different i2c buses. */
1839 struct mutex gmbus_mutex
;
1842 * Base address of the gmbus and gpio block.
1844 uint32_t gpio_mmio_base
;
1846 /* MMIO base address for MIPI regs */
1847 uint32_t mipi_mmio_base
;
1849 uint32_t psr_mmio_base
;
1851 uint32_t pps_mmio_base
;
1853 wait_queue_head_t gmbus_wait_queue
;
1855 struct pci_dev
*bridge_dev
;
1856 struct i915_gem_context
*kernel_context
;
1857 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
1858 struct i915_vma
*semaphore
;
1860 struct drm_dma_handle
*status_page_dmah
;
1861 struct resource mch_res
;
1863 /* protects the irq masks */
1864 spinlock_t irq_lock
;
1866 /* protects the mmio flip data */
1867 spinlock_t mmio_flip_lock
;
1869 bool display_irqs_enabled
;
1871 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1872 struct pm_qos_request pm_qos
;
1874 /* Sideband mailbox protection */
1875 struct mutex sb_lock
;
1877 /** Cached value of IMR to avoid reads in updating the bitfield */
1880 u32 de_irq_mask
[I915_MAX_PIPES
];
1887 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1889 struct i915_hotplug hotplug
;
1890 struct intel_fbc fbc
;
1891 struct i915_drrs drrs
;
1892 struct intel_opregion opregion
;
1893 struct intel_vbt_data vbt
;
1895 bool preserve_bios_swizzle
;
1898 struct intel_overlay
*overlay
;
1900 /* backlight registers and fields in struct intel_panel */
1901 struct mutex backlight_lock
;
1904 bool no_aux_handshake
;
1906 /* protects panel power sequencer state */
1907 struct mutex pps_mutex
;
1909 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1910 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1912 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1913 unsigned int skl_preferred_vco_freq
;
1914 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1915 unsigned int max_dotclk_freq
;
1916 unsigned int rawclk_freq
;
1917 unsigned int hpll_freq
;
1918 unsigned int czclk_freq
;
1921 unsigned int vco
, ref
;
1925 * wq - Driver workqueue for GEM.
1927 * NOTE: Work items scheduled here are not allowed to grab any modeset
1928 * locks, for otherwise the flushing done in the pageflip code will
1929 * result in deadlocks.
1931 struct workqueue_struct
*wq
;
1933 /* Display functions */
1934 struct drm_i915_display_funcs display
;
1936 /* PCH chipset type */
1937 enum intel_pch pch_type
;
1938 unsigned short pch_id
;
1940 unsigned long quirks
;
1942 enum modeset_restore modeset_restore
;
1943 struct mutex modeset_restore_lock
;
1944 struct drm_atomic_state
*modeset_restore_state
;
1945 struct drm_modeset_acquire_ctx reset_ctx
;
1947 struct list_head vm_list
; /* Global list of all address spaces */
1948 struct i915_ggtt ggtt
; /* VM representing the global address space */
1950 struct i915_gem_mm mm
;
1951 DECLARE_HASHTABLE(mm_structs
, 7);
1952 struct mutex mm_lock
;
1954 /* The hw wants to have a stable context identifier for the lifetime
1955 * of the context (for OA, PASID, faults, etc). This is limited
1956 * in execlists to 21 bits.
1958 struct ida context_hw_ida
;
1959 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1961 /* Kernel Modesetting */
1963 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1964 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1965 wait_queue_head_t pending_flip_queue
;
1967 #ifdef CONFIG_DEBUG_FS
1968 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1971 /* dpll and cdclk state is protected by connection_mutex */
1972 int num_shared_dpll
;
1973 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1974 const struct intel_dpll_mgr
*dpll_mgr
;
1977 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1978 * Must be global rather than per dpll, because on some platforms
1979 * plls share registers.
1981 struct mutex dpll_lock
;
1983 unsigned int active_crtcs
;
1984 unsigned int min_pixclk
[I915_MAX_PIPES
];
1986 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1988 struct i915_workarounds workarounds
;
1990 struct i915_frontbuffer_tracking fb_tracking
;
1994 bool mchbar_need_disable
;
1996 struct intel_l3_parity l3_parity
;
1998 /* Cannot be determined by PCIID. You must always read a register. */
2001 /* gen6+ rps state */
2002 struct intel_gen6_power_mgmt rps
;
2004 /* ilk-only ips/rps state. Everything in here is protected by the global
2005 * mchdev_lock in intel_pm.c */
2006 struct intel_ilk_power_mgmt ips
;
2008 struct i915_power_domains power_domains
;
2010 struct i915_psr psr
;
2012 struct i915_gpu_error gpu_error
;
2014 struct drm_i915_gem_object
*vlv_pctx
;
2016 #ifdef CONFIG_DRM_FBDEV_EMULATION
2017 /* list of fbdev register on this device */
2018 struct intel_fbdev
*fbdev
;
2019 struct work_struct fbdev_suspend_work
;
2022 struct drm_property
*broadcast_rgb_property
;
2023 struct drm_property
*force_audio_property
;
2025 /* hda/i915 audio component */
2026 struct i915_audio_component
*audio_component
;
2027 bool audio_component_registered
;
2029 * av_mutex - mutex for audio/video sync
2032 struct mutex av_mutex
;
2034 uint32_t hw_context_size
;
2035 struct list_head context_list
;
2039 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2040 u32 chv_phy_control
;
2042 * Shadows for CHV DPLL_MD regs to keep the state
2043 * checker somewhat working in the presence hardware
2044 * crappiness (can't read out DPLL_MD for pipes B & C).
2046 u32 chv_dpll_md
[I915_MAX_PIPES
];
2050 bool suspended_to_idle
;
2051 struct i915_suspend_saved_registers regfile
;
2052 struct vlv_s0ix_state vlv_s0ix_state
;
2055 I915_SAGV_UNKNOWN
= 0,
2058 I915_SAGV_NOT_CONTROLLED
2063 * Raw watermark latency values:
2064 * in 0.1us units for WM0,
2065 * in 0.5us units for WM1+.
2068 uint16_t pri_latency
[5];
2070 uint16_t spr_latency
[5];
2072 uint16_t cur_latency
[5];
2074 * Raw watermark memory latency values
2075 * for SKL for all 8 levels
2078 uint16_t skl_latency
[8];
2080 /* current hardware state */
2082 struct ilk_wm_values hw
;
2083 struct skl_wm_values skl_hw
;
2084 struct vlv_wm_values vlv
;
2090 * Should be held around atomic WM register writing; also
2091 * protects * intel_crtc->wm.active and
2092 * cstate->wm.need_postvbl_update.
2094 struct mutex wm_mutex
;
2097 * Set during HW readout of watermarks/DDB. Some platforms
2098 * need to know when we're still using BIOS-provided values
2099 * (which we don't fully trust).
2101 bool distrust_bios_wm
;
2104 struct i915_runtime_pm pm
;
2106 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2108 void (*resume
)(struct drm_i915_private
*);
2109 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2111 struct list_head timelines
;
2112 struct i915_gem_timeline global_timeline
;
2113 u32 active_requests
;
2116 * Is the GPU currently considered idle, or busy executing
2117 * userspace requests? Whilst idle, we allow runtime power
2118 * management to power down the hardware and display clocks.
2119 * In order to reduce the effect on performance, there
2120 * is a slight delay before we do so.
2125 * We leave the user IRQ off as much as possible,
2126 * but this means that requests will finish and never
2127 * be retired once the system goes idle. Set a timer to
2128 * fire periodically while the ring is running. When it
2129 * fires, go retire requests.
2131 struct delayed_work retire_work
;
2134 * When we detect an idle GPU, we want to turn on
2135 * powersaving features. So once we see that there
2136 * are no more requests outstanding and no more
2137 * arrive within a small period of time, we fire
2138 * off the idle_work.
2140 struct delayed_work idle_work
;
2142 ktime_t last_init_time
;
2145 /* perform PHY state sanity checks? */
2146 bool chv_phy_assert
[2];
2148 /* Used to save the pipe-to-encoder mapping for audio */
2149 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2152 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2153 * will be rejected. Instead look for a better place.
2157 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2159 return container_of(dev
, struct drm_i915_private
, drm
);
2162 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2164 return to_i915(dev_get_drvdata(kdev
));
2167 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2169 return container_of(guc
, struct drm_i915_private
, guc
);
2172 /* Simple iterator over all initialised engines */
2173 #define for_each_engine(engine__, dev_priv__, id__) \
2175 (id__) < I915_NUM_ENGINES; \
2177 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2179 #define __mask_next_bit(mask) ({ \
2180 int __idx = ffs(mask) - 1; \
2181 mask &= ~BIT(__idx); \
2185 /* Iterator over subset of engines selected by mask */
2186 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2187 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2188 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2190 enum hdmi_force_audio
{
2191 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2192 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2193 HDMI_AUDIO_AUTO
, /* trust EDID */
2194 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2197 #define I915_GTT_OFFSET_NONE ((u32)-1)
2200 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2201 * considered to be the frontbuffer for the given plane interface-wise. This
2202 * doesn't mean that the hw necessarily already scans it out, but that any
2203 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2205 * We have one bit per pipe and per scanout plane type.
2207 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2208 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2209 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2210 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2211 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2212 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2213 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2214 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2215 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2216 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2217 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2218 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2221 * Optimised SGL iterator for GEM objects
2223 static __always_inline
struct sgt_iter
{
2224 struct scatterlist
*sgp
;
2231 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2232 struct sgt_iter s
= { .sgp
= sgl
};
2235 s
.max
= s
.curr
= s
.sgp
->offset
;
2236 s
.max
+= s
.sgp
->length
;
2238 s
.dma
= sg_dma_address(s
.sgp
);
2240 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2246 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2249 if (unlikely(sg_is_chain(sg
)))
2250 sg
= sg_chain_ptr(sg
);
2255 * __sg_next - return the next scatterlist entry in a list
2256 * @sg: The current sg entry
2259 * If the entry is the last, return NULL; otherwise, step to the next
2260 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2261 * otherwise just return the pointer to the current element.
2263 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2265 #ifdef CONFIG_DEBUG_SG
2266 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2268 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2272 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2273 * @__dmap: DMA address (output)
2274 * @__iter: 'struct sgt_iter' (iterator state, internal)
2275 * @__sgt: sg_table to iterate over (input)
2277 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2278 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2279 ((__dmap) = (__iter).dma + (__iter).curr); \
2280 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2281 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2284 * for_each_sgt_page - iterate over the pages of the given sg_table
2285 * @__pp: page pointer (output)
2286 * @__iter: 'struct sgt_iter' (iterator state, internal)
2287 * @__sgt: sg_table to iterate over (input)
2289 #define for_each_sgt_page(__pp, __iter, __sgt) \
2290 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2291 ((__pp) = (__iter).pfn == 0 ? NULL : \
2292 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2293 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2294 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2297 * A command that requires special handling by the command parser.
2299 struct drm_i915_cmd_descriptor
{
2301 * Flags describing how the command parser processes the command.
2303 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2304 * a length mask if not set
2305 * CMD_DESC_SKIP: The command is allowed but does not follow the
2306 * standard length encoding for the opcode range in
2308 * CMD_DESC_REJECT: The command is never allowed
2309 * CMD_DESC_REGISTER: The command should be checked against the
2310 * register whitelist for the appropriate ring
2311 * CMD_DESC_MASTER: The command is allowed if the submitting process
2315 #define CMD_DESC_FIXED (1<<0)
2316 #define CMD_DESC_SKIP (1<<1)
2317 #define CMD_DESC_REJECT (1<<2)
2318 #define CMD_DESC_REGISTER (1<<3)
2319 #define CMD_DESC_BITMASK (1<<4)
2320 #define CMD_DESC_MASTER (1<<5)
2323 * The command's unique identification bits and the bitmask to get them.
2324 * This isn't strictly the opcode field as defined in the spec and may
2325 * also include type, subtype, and/or subop fields.
2333 * The command's length. The command is either fixed length (i.e. does
2334 * not include a length field) or has a length field mask. The flag
2335 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2336 * a length mask. All command entries in a command table must include
2337 * length information.
2345 * Describes where to find a register address in the command to check
2346 * against the ring's register whitelist. Only valid if flags has the
2347 * CMD_DESC_REGISTER bit set.
2349 * A non-zero step value implies that the command may access multiple
2350 * registers in sequence (e.g. LRI), in that case step gives the
2351 * distance in dwords between individual offset fields.
2359 #define MAX_CMD_DESC_BITMASKS 3
2361 * Describes command checks where a particular dword is masked and
2362 * compared against an expected value. If the command does not match
2363 * the expected value, the parser rejects it. Only valid if flags has
2364 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2367 * If the check specifies a non-zero condition_mask then the parser
2368 * only performs the check when the bits specified by condition_mask
2375 u32 condition_offset
;
2377 } bits
[MAX_CMD_DESC_BITMASKS
];
2381 * A table of commands requiring special handling by the command parser.
2383 * Each engine has an array of tables. Each table consists of an array of
2384 * command descriptors, which must be sorted with command opcodes in
2387 struct drm_i915_cmd_table
{
2388 const struct drm_i915_cmd_descriptor
*table
;
2392 static inline const struct intel_device_info
*
2393 intel_info(const struct drm_i915_private
*dev_priv
)
2395 return &dev_priv
->info
;
2398 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2400 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2401 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2403 #define REVID_FOREVER 0xff
2404 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2406 #define GEN_FOREVER (0)
2408 * Returns true if Gen is in inclusive range [Start, End].
2410 * Use GEN_FOREVER for unbound start and or end.
2412 #define IS_GEN(dev_priv, s, e) ({ \
2413 unsigned int __s = (s), __e = (e); \
2414 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2415 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2416 if ((__s) != GEN_FOREVER) \
2418 if ((__e) == GEN_FOREVER) \
2419 __e = BITS_PER_LONG - 1; \
2422 !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2426 * Return true if revision is in range [since,until] inclusive.
2428 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2430 #define IS_REVID(p, since, until) \
2431 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2433 #define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
2434 #define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
2435 #define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x)
2436 #define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
2437 #define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g)
2438 #define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
2439 #define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
2440 #define IS_I945GM(dev_priv) ((dev_priv)->info.is_i945gm)
2441 #define IS_BROADWATER(dev_priv) ((dev_priv)->info.is_broadwater)
2442 #define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
2443 #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
2444 #define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
2445 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2446 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2447 #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
2448 #define IS_G33(dev_priv) ((dev_priv)->info.is_g33)
2449 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2450 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
2451 #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
2452 INTEL_DEVID(dev_priv) == 0x0152 || \
2453 INTEL_DEVID(dev_priv) == 0x015a)
2454 #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
2455 #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
2456 #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
2457 #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
2458 #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
2459 #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
2460 #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
2461 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2462 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2463 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2464 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2465 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2466 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2467 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2468 /* ULX machines are also considered ULT. */
2469 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2470 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2471 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2472 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2473 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2474 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2475 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2476 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2477 /* ULX machines are also considered ULT. */
2478 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2479 INTEL_DEVID(dev_priv) == 0x0A1E)
2480 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2481 INTEL_DEVID(dev_priv) == 0x1913 || \
2482 INTEL_DEVID(dev_priv) == 0x1916 || \
2483 INTEL_DEVID(dev_priv) == 0x1921 || \
2484 INTEL_DEVID(dev_priv) == 0x1926)
2485 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2486 INTEL_DEVID(dev_priv) == 0x1915 || \
2487 INTEL_DEVID(dev_priv) == 0x191E)
2488 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2489 INTEL_DEVID(dev_priv) == 0x5913 || \
2490 INTEL_DEVID(dev_priv) == 0x5916 || \
2491 INTEL_DEVID(dev_priv) == 0x5921 || \
2492 INTEL_DEVID(dev_priv) == 0x5926)
2493 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2494 INTEL_DEVID(dev_priv) == 0x5915 || \
2495 INTEL_DEVID(dev_priv) == 0x591E)
2496 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2497 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2498 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2499 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2501 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2503 #define SKL_REVID_A0 0x0
2504 #define SKL_REVID_B0 0x1
2505 #define SKL_REVID_C0 0x2
2506 #define SKL_REVID_D0 0x3
2507 #define SKL_REVID_E0 0x4
2508 #define SKL_REVID_F0 0x5
2509 #define SKL_REVID_G0 0x6
2510 #define SKL_REVID_H0 0x7
2512 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2514 #define BXT_REVID_A0 0x0
2515 #define BXT_REVID_A1 0x1
2516 #define BXT_REVID_B0 0x3
2517 #define BXT_REVID_C0 0x9
2519 #define IS_BXT_REVID(dev_priv, since, until) \
2520 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2522 #define KBL_REVID_A0 0x0
2523 #define KBL_REVID_B0 0x1
2524 #define KBL_REVID_C0 0x2
2525 #define KBL_REVID_D0 0x3
2526 #define KBL_REVID_E0 0x4
2528 #define IS_KBL_REVID(dev_priv, since, until) \
2529 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2532 * The genX designation typically refers to the render engine, so render
2533 * capability related checks should use IS_GEN, while display and other checks
2534 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2537 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2538 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2539 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2540 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2541 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2542 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2543 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2544 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2546 #define ENGINE_MASK(id) BIT(id)
2547 #define RENDER_RING ENGINE_MASK(RCS)
2548 #define BSD_RING ENGINE_MASK(VCS)
2549 #define BLT_RING ENGINE_MASK(BCS)
2550 #define VEBOX_RING ENGINE_MASK(VECS)
2551 #define BSD2_RING ENGINE_MASK(VCS2)
2552 #define ALL_ENGINES (~0)
2554 #define HAS_ENGINE(dev_priv, id) \
2555 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2557 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2558 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2559 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2560 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2562 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2563 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2564 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2565 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2566 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2568 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2570 #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
2571 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2572 ((dev_priv)->info.has_logical_ring_contexts)
2573 #define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
2574 #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
2575 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
2577 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2578 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2579 ((dev_priv)->info.overlay_needs_physical)
2581 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2582 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
2584 /* WaRsDisableCoarsePowerGating:skl,bxt */
2585 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2586 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2587 IS_SKL_GT3(dev_priv) || \
2588 IS_SKL_GT4(dev_priv))
2591 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2592 * even when in MSI mode. This results in spurious interrupt warnings if the
2593 * legacy irq no. is shared with another device. The kernel then disables that
2594 * interrupt source and so prevents the other device from working properly.
2596 #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
2597 #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2599 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2600 * rows, which changed the alignment requirements and fence programming.
2602 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2603 !(IS_I915G(dev_priv) || \
2604 IS_I915GM(dev_priv)))
2605 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2606 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2608 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2609 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
2610 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2612 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2614 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2616 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2617 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2618 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2619 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2620 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2622 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2624 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2625 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2628 * For now, anything with a GuC requires uCode loading, and then supports
2629 * command submission once loaded. But these are logically independent
2630 * properties, so we have separate macros to test them.
2632 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2633 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2634 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2636 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2638 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2640 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2641 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2642 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2643 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2644 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2645 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2646 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2647 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2648 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2649 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2650 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2651 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2653 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2654 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2655 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2656 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2657 #define HAS_PCH_LPT_LP(dev_priv) \
2658 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2659 #define HAS_PCH_LPT_H(dev_priv) \
2660 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2661 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2662 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2663 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2664 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2666 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2668 #define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))
2670 /* DPF == dynamic parity feature */
2671 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2672 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2673 2 : HAS_L3_DPF(dev_priv))
2675 #define GT_FREQUENCY_MULTIPLIER 50
2676 #define GEN9_FREQ_SCALER 3
2678 #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
2680 #include "i915_trace.h"
2682 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2684 #ifdef CONFIG_INTEL_IOMMU
2685 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2691 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2692 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2694 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2697 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2701 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2702 const char *fmt
, ...);
2704 #define i915_report_error(dev_priv, fmt, ...) \
2705 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2707 #ifdef CONFIG_COMPAT
2708 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2711 #define i915_compat_ioctl NULL
2713 extern const struct dev_pm_ops i915_pm_ops
;
2715 extern int i915_driver_load(struct pci_dev
*pdev
,
2716 const struct pci_device_id
*ent
);
2717 extern void i915_driver_unload(struct drm_device
*dev
);
2718 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2719 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2720 extern void i915_reset(struct drm_i915_private
*dev_priv
);
2721 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2722 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2723 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
2724 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2725 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2726 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2727 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2728 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2730 /* intel_hotplug.c */
2731 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2732 u32 pin_mask
, u32 long_mask
);
2733 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2734 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2735 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2736 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2737 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2738 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2741 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2743 unsigned long delay
;
2745 if (unlikely(!i915
.enable_hangcheck
))
2748 /* Don't continually defer the hangcheck so that it is always run at
2749 * least once after work has been scheduled on any ring. Otherwise,
2750 * we will ignore a hung ring if a second ring is kept busy.
2753 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2754 queue_delayed_work(system_long_wq
,
2755 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2759 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2761 const char *fmt
, ...);
2763 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2764 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2765 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2767 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2768 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2769 bool restore_forcewake
);
2770 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2771 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2772 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2773 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2774 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2776 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2777 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2778 enum forcewake_domains domains
);
2779 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2780 enum forcewake_domains domains
);
2781 /* Like above but the caller must manage the uncore.lock itself.
2782 * Must be used with I915_READ_FW and friends.
2784 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2785 enum forcewake_domains domains
);
2786 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2787 enum forcewake_domains domains
);
2788 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2790 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2792 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
2796 const unsigned long timeout_ms
);
2797 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
2801 const unsigned long timeout_ms
);
2803 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
2805 return dev_priv
->gvt
;
2808 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
2810 return dev_priv
->vgpu
.active
;
2814 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2818 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2821 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2822 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2823 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2826 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2827 uint32_t interrupt_mask
,
2828 uint32_t enabled_irq_mask
);
2830 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2832 ilk_update_display_irq(dev_priv
, bits
, bits
);
2835 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2837 ilk_update_display_irq(dev_priv
, bits
, 0);
2839 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2841 uint32_t interrupt_mask
,
2842 uint32_t enabled_irq_mask
);
2843 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2844 enum pipe pipe
, uint32_t bits
)
2846 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2848 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2849 enum pipe pipe
, uint32_t bits
)
2851 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2853 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2854 uint32_t interrupt_mask
,
2855 uint32_t enabled_irq_mask
);
2857 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2859 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2862 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2864 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2868 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2869 struct drm_file
*file_priv
);
2870 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2871 struct drm_file
*file_priv
);
2872 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2873 struct drm_file
*file_priv
);
2874 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2875 struct drm_file
*file_priv
);
2876 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2877 struct drm_file
*file_priv
);
2878 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2879 struct drm_file
*file_priv
);
2880 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2881 struct drm_file
*file_priv
);
2882 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2883 struct drm_file
*file_priv
);
2884 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2885 struct drm_file
*file_priv
);
2886 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2887 struct drm_file
*file_priv
);
2888 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2889 struct drm_file
*file
);
2890 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2891 struct drm_file
*file
);
2892 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2893 struct drm_file
*file_priv
);
2894 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2895 struct drm_file
*file_priv
);
2896 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2897 struct drm_file
*file_priv
);
2898 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2899 struct drm_file
*file_priv
);
2900 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
2901 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2902 struct drm_file
*file
);
2903 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2904 struct drm_file
*file_priv
);
2905 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2906 struct drm_file
*file_priv
);
2907 int i915_gem_load_init(struct drm_device
*dev
);
2908 void i915_gem_load_cleanup(struct drm_device
*dev
);
2909 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
2910 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
2911 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
2913 void *i915_gem_object_alloc(struct drm_device
*dev
);
2914 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2915 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2916 const struct drm_i915_gem_object_ops
*ops
);
2917 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
2919 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2920 struct drm_device
*dev
, const void *data
, size_t size
);
2921 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
2922 void i915_gem_free_object(struct drm_gem_object
*obj
);
2924 struct i915_vma
* __must_check
2925 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2926 const struct i915_ggtt_view
*view
,
2931 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
2932 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2934 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
2936 static inline int __sg_page_count(const struct scatterlist
*sg
)
2938 return sg
->length
>> PAGE_SHIFT
;
2941 struct scatterlist
*
2942 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
2943 unsigned int n
, unsigned int *offset
);
2946 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
2950 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
2954 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
2957 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2958 struct sg_table
*pages
);
2959 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2961 static inline int __must_check
2962 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2964 might_lock(&obj
->mm
.lock
);
2966 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
2969 return __i915_gem_object_get_pages(obj
);
2973 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2975 GEM_BUG_ON(!obj
->mm
.pages
);
2977 atomic_inc(&obj
->mm
.pages_pin_count
);
2981 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
2983 return atomic_read(&obj
->mm
.pages_pin_count
);
2987 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2989 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
2990 GEM_BUG_ON(!obj
->mm
.pages
);
2992 atomic_dec(&obj
->mm
.pages_pin_count
);
2993 GEM_BUG_ON(atomic_read(&obj
->mm
.pages_pin_count
) < obj
->bind_count
);
2997 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2999 __i915_gem_object_unpin_pages(obj
);
3002 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3007 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3008 enum i915_mm_subclass subclass
);
3009 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3011 enum i915_map_type
{
3017 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3018 * @obj - the object to map into kernel address space
3019 * @type - the type of mapping, used to select pgprot_t
3021 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3022 * pages and then returns a contiguous mapping of the backing storage into
3023 * the kernel address space. Based on the @type of mapping, the PTE will be
3024 * set to either WriteBack or WriteCombine (via pgprot_t).
3026 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3027 * mapping is no longer required.
3029 * Returns the pointer through which to access the mapped object, or an
3030 * ERR_PTR() on error.
3032 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3033 enum i915_map_type type
);
3036 * i915_gem_object_unpin_map - releases an earlier mapping
3037 * @obj - the object to unmap
3039 * After pinning the object and mapping its pages, once you are finished
3040 * with your access, call i915_gem_object_unpin_map() to release the pin
3041 * upon the mapping. Once the pin count reaches zero, that mapping may be
3044 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3046 i915_gem_object_unpin_pages(obj
);
3049 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3050 unsigned int *needs_clflush
);
3051 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3052 unsigned int *needs_clflush
);
3053 #define CLFLUSH_BEFORE 0x1
3054 #define CLFLUSH_AFTER 0x2
3055 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3058 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3060 i915_gem_object_unpin_pages(obj
);
3063 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3064 void i915_vma_move_to_active(struct i915_vma
*vma
,
3065 struct drm_i915_gem_request
*req
,
3066 unsigned int flags
);
3067 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3068 struct drm_device
*dev
,
3069 struct drm_mode_create_dumb
*args
);
3070 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3071 uint32_t handle
, uint64_t *offset
);
3072 int i915_gem_mmap_gtt_version(void);
3074 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3075 struct drm_i915_gem_object
*new,
3076 unsigned frontbuffer_bits
);
3078 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3080 struct drm_i915_gem_request
*
3081 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3083 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3085 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3087 return unlikely(test_bit(I915_RESET_IN_PROGRESS
, &error
->flags
));
3090 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3092 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3095 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3097 return i915_reset_in_progress(error
) | i915_terminally_wedged(error
);
3100 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3102 return READ_ONCE(error
->reset_count
);
3105 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3106 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3107 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3108 int __must_check
i915_gem_init(struct drm_device
*dev
);
3109 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3110 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3111 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3112 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3113 unsigned int flags
);
3114 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3115 void i915_gem_resume(struct drm_device
*dev
);
3116 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3117 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3120 struct intel_rps_client
*rps
);
3121 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3124 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3127 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3130 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3131 struct i915_vma
* __must_check
3132 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3134 const struct i915_ggtt_view
*view
);
3135 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3136 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3138 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3139 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3141 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
, u64 size
,
3143 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
3144 int tiling_mode
, bool fenced
);
3146 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3147 enum i915_cache_level cache_level
);
3149 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3150 struct dma_buf
*dma_buf
);
3152 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3153 struct drm_gem_object
*gem_obj
, int flags
);
3156 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3157 struct i915_address_space
*vm
,
3158 const struct i915_ggtt_view
*view
);
3161 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3162 struct i915_address_space
*vm
,
3163 const struct i915_ggtt_view
*view
);
3165 static inline struct i915_hw_ppgtt
*
3166 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3168 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3171 static inline struct i915_vma
*
3172 i915_gem_object_to_ggtt(struct drm_i915_gem_object
*obj
,
3173 const struct i915_ggtt_view
*view
)
3175 return i915_gem_obj_to_vma(obj
, &to_i915(obj
->base
.dev
)->ggtt
.base
, view
);
3178 static inline unsigned long
3179 i915_gem_object_ggtt_offset(struct drm_i915_gem_object
*o
,
3180 const struct i915_ggtt_view
*view
)
3182 return i915_ggtt_offset(i915_gem_object_to_ggtt(o
, view
));
3185 /* i915_gem_fence_reg.c */
3186 int __must_check
i915_vma_get_fence(struct i915_vma
*vma
);
3187 int __must_check
i915_vma_put_fence(struct i915_vma
*vma
);
3189 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3191 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3192 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3193 struct sg_table
*pages
);
3194 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3195 struct sg_table
*pages
);
3197 /* i915_gem_context.c */
3198 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3199 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3200 void i915_gem_context_fini(struct drm_device
*dev
);
3201 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3202 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3203 int i915_switch_context(struct drm_i915_gem_request
*req
);
3204 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
);
3206 i915_gem_context_pin_legacy(struct i915_gem_context
*ctx
,
3207 unsigned int flags
);
3208 void i915_gem_context_free(struct kref
*ctx_ref
);
3209 struct drm_i915_gem_object
*
3210 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3211 struct i915_gem_context
*
3212 i915_gem_context_create_gvt(struct drm_device
*dev
);
3214 static inline struct i915_gem_context
*
3215 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3217 struct i915_gem_context
*ctx
;
3219 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3221 ctx
= idr_find(&file_priv
->context_idr
, id
);
3223 return ERR_PTR(-ENOENT
);
3228 static inline struct i915_gem_context
*
3229 i915_gem_context_get(struct i915_gem_context
*ctx
)
3231 kref_get(&ctx
->ref
);
3235 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3237 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3238 kref_put(&ctx
->ref
, i915_gem_context_free
);
3241 static inline struct intel_timeline
*
3242 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3243 struct intel_engine_cs
*engine
)
3245 struct i915_address_space
*vm
;
3247 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3248 return &vm
->timeline
.engine
[engine
->id
];
3251 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3253 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3256 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3257 struct drm_file
*file
);
3258 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3259 struct drm_file
*file
);
3260 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3261 struct drm_file
*file_priv
);
3262 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3263 struct drm_file
*file_priv
);
3264 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3265 struct drm_file
*file
);
3267 /* i915_gem_evict.c */
3268 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3269 u64 min_size
, u64 alignment
,
3270 unsigned cache_level
,
3273 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3274 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3276 /* belongs in i915_gem_gtt.h */
3277 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3280 if (INTEL_GEN(dev_priv
) < 6)
3281 intel_gtt_chipset_flush();
3284 /* i915_gem_stolen.c */
3285 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3286 struct drm_mm_node
*node
, u64 size
,
3287 unsigned alignment
);
3288 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3289 struct drm_mm_node
*node
, u64 size
,
3290 unsigned alignment
, u64 start
,
3292 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3293 struct drm_mm_node
*node
);
3294 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3295 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3296 struct drm_i915_gem_object
*
3297 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3298 struct drm_i915_gem_object
*
3299 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3304 /* i915_gem_internal.c */
3305 struct drm_i915_gem_object
*
3306 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3309 /* i915_gem_shrinker.c */
3310 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3311 unsigned long target
,
3313 #define I915_SHRINK_PURGEABLE 0x1
3314 #define I915_SHRINK_UNBOUND 0x2
3315 #define I915_SHRINK_BOUND 0x4
3316 #define I915_SHRINK_ACTIVE 0x8
3317 #define I915_SHRINK_VMAPS 0x10
3318 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3319 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3320 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3323 /* i915_gem_tiling.c */
3324 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3326 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3328 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3329 i915_gem_object_is_tiled(obj
);
3332 /* i915_debugfs.c */
3333 #ifdef CONFIG_DEBUG_FS
3334 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3335 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3336 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3337 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3339 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3340 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3341 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3343 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3346 /* i915_gpu_error.c */
3347 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3350 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3351 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3352 const struct i915_error_state_file_priv
*error
);
3353 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3354 struct drm_i915_private
*i915
,
3355 size_t count
, loff_t pos
);
3356 static inline void i915_error_state_buf_release(
3357 struct drm_i915_error_state_buf
*eb
)
3361 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3363 const char *error_msg
);
3364 void i915_error_state_get(struct drm_device
*dev
,
3365 struct i915_error_state_file_priv
*error_priv
);
3366 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3367 void i915_destroy_error_state(struct drm_device
*dev
);
3371 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3373 const char *error_msg
)
3377 static inline void i915_destroy_error_state(struct drm_device
*dev
)
3383 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3385 /* i915_cmd_parser.c */
3386 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3387 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3388 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3389 bool intel_engine_needs_cmd_parser(struct intel_engine_cs
*engine
);
3390 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3391 struct drm_i915_gem_object
*batch_obj
,
3392 struct drm_i915_gem_object
*shadow_batch_obj
,
3393 u32 batch_start_offset
,
3397 /* i915_suspend.c */
3398 extern int i915_save_state(struct drm_device
*dev
);
3399 extern int i915_restore_state(struct drm_device
*dev
);
3402 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3403 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3406 extern int intel_setup_gmbus(struct drm_device
*dev
);
3407 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3408 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3411 extern struct i2c_adapter
*
3412 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3413 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3414 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3415 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3417 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3419 extern void intel_i2c_reset(struct drm_device
*dev
);
3422 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3423 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3424 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3425 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3426 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3427 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3428 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3429 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3430 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3432 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
3436 /* intel_opregion.c */
3438 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3439 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3440 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3441 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3442 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3444 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3446 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3448 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3449 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3450 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3451 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3455 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3460 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3464 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3472 extern void intel_register_dsm_handler(void);
3473 extern void intel_unregister_dsm_handler(void);
3475 static inline void intel_register_dsm_handler(void) { return; }
3476 static inline void intel_unregister_dsm_handler(void) { return; }
3477 #endif /* CONFIG_ACPI */
3479 /* intel_device_info.c */
3480 static inline struct intel_device_info
*
3481 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3483 return (struct intel_device_info
*)&dev_priv
->info
;
3486 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3487 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3490 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3491 extern int intel_modeset_init(struct drm_device
*dev
);
3492 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3493 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3494 extern int intel_connector_register(struct drm_connector
*);
3495 extern void intel_connector_unregister(struct drm_connector
*);
3496 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
3498 extern void intel_display_resume(struct drm_device
*dev
);
3499 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
3500 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
3501 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3502 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3503 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3504 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3507 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3508 struct drm_file
*file
);
3511 extern struct intel_overlay_error_state
*
3512 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3513 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3514 struct intel_overlay_error_state
*error
);
3516 extern struct intel_display_error_state
*
3517 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3518 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3519 struct drm_i915_private
*dev_priv
,
3520 struct intel_display_error_state
*error
);
3522 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3523 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3525 /* intel_sideband.c */
3526 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3527 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3528 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3529 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3530 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3531 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3532 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3533 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3534 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3535 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3536 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3537 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3538 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3539 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3540 enum intel_sbi_destination destination
);
3541 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3542 enum intel_sbi_destination destination
);
3543 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3544 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3546 /* intel_dpio_phy.c */
3547 void bxt_port_to_phy_channel(enum port port
,
3548 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
3549 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
3550 enum port port
, u32 margin
, u32 scale
,
3551 u32 enable
, u32 deemphasis
);
3552 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3553 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
3554 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
3556 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
3558 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
3559 uint8_t lane_count
);
3560 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
3561 uint8_t lane_lat_optim_mask
);
3562 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
3564 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3565 u32 deemph_reg_value
, u32 margin_reg_value
,
3566 bool uniq_trans_scale
);
3567 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3569 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3570 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3571 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3572 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3574 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3575 u32 demph_reg_value
, u32 preemph_reg_value
,
3576 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3577 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3578 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3579 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3581 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3582 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3584 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3585 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3587 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3588 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3589 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3590 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3592 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3593 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3594 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3595 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3597 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3598 * will be implemented using 2 32-bit writes in an arbitrary order with
3599 * an arbitrary delay between them. This can cause the hardware to
3600 * act upon the intermediate value, possibly leading to corruption and
3601 * machine death. For this reason we do not support I915_WRITE64, or
3602 * dev_priv->uncore.funcs.mmio_writeq.
3604 * When reading a 64-bit value as two 32-bit values, the delay may cause
3605 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3606 * occasionally a 64-bit register does not actualy support a full readq
3607 * and must be read using two 32-bit reads.
3609 * You have been warned.
3611 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3613 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3614 u32 upper, lower, old_upper, loop = 0; \
3615 upper = I915_READ(upper_reg); \
3617 old_upper = upper; \
3618 lower = I915_READ(lower_reg); \
3619 upper = I915_READ(upper_reg); \
3620 } while (upper != old_upper && loop++ < 2); \
3621 (u64)upper << 32 | lower; })
3623 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3624 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3626 #define __raw_read(x, s) \
3627 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3630 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3633 #define __raw_write(x, s) \
3634 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3635 i915_reg_t reg, uint##x##_t val) \
3637 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3652 /* These are untraced mmio-accessors that are only valid to be used inside
3653 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3656 * Think twice, and think again, before using these.
3658 * As an example, these accessors can possibly be used between:
3660 * spin_lock_irq(&dev_priv->uncore.lock);
3661 * intel_uncore_forcewake_get__locked();
3665 * intel_uncore_forcewake_put__locked();
3666 * spin_unlock_irq(&dev_priv->uncore.lock);
3669 * Note: some registers may not need forcewake held, so
3670 * intel_uncore_forcewake_{get,put} can be omitted, see
3671 * intel_uncore_forcewake_for_reg().
3673 * Certain architectures will die if the same cacheline is concurrently accessed
3674 * by different clients (e.g. on Ivybridge). Access to registers should
3675 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3676 * a more localised lock guarding all access to that bank of registers.
3678 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3679 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3680 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3681 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3683 /* "Broadcast RGB" property */
3684 #define INTEL_BROADCAST_RGB_AUTO 0
3685 #define INTEL_BROADCAST_RGB_FULL 1
3686 #define INTEL_BROADCAST_RGB_LIMITED 2
3688 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
3690 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
3691 return VLV_VGACNTRL
;
3692 else if (INTEL_GEN(dev_priv
) >= 5)
3693 return CPU_VGACNTRL
;
3698 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3700 unsigned long j
= msecs_to_jiffies(m
);
3702 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3705 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3707 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3710 static inline unsigned long
3711 timespec_to_jiffies_timeout(const struct timespec
*value
)
3713 unsigned long j
= timespec_to_jiffies(value
);
3715 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3719 * If you need to wait X milliseconds between events A and B, but event B
3720 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3721 * when event A happened, then just before event B you call this function and
3722 * pass the timestamp as the first argument, and X as the second argument.
3725 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3727 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3730 * Don't re-read the value of "jiffies" every time since it may change
3731 * behind our back and break the math.
3733 tmp_jiffies
= jiffies
;
3734 target_jiffies
= timestamp_jiffies
+
3735 msecs_to_jiffies_timeout(to_wait_ms
);
3737 if (time_after(target_jiffies
, tmp_jiffies
)) {
3738 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3739 while (remaining_jiffies
)
3741 schedule_timeout_uninterruptible(remaining_jiffies
);
3746 __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3748 struct intel_engine_cs
*engine
= req
->engine
;
3750 /* Before we do the heavier coherent read of the seqno,
3751 * check the value (hopefully) in the CPU cacheline.
3753 if (__i915_gem_request_completed(req
))
3756 /* Ensure our read of the seqno is coherent so that we
3757 * do not "miss an interrupt" (i.e. if this is the last
3758 * request and the seqno write from the GPU is not visible
3759 * by the time the interrupt fires, we will see that the
3760 * request is incomplete and go back to sleep awaiting
3761 * another interrupt that will never come.)
3763 * Strictly, we only need to do this once after an interrupt,
3764 * but it is easier and safer to do it every time the waiter
3767 if (engine
->irq_seqno_barrier
&&
3768 rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
3769 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
3770 struct task_struct
*tsk
;
3772 /* The ordering of irq_posted versus applying the barrier
3773 * is crucial. The clearing of the current irq_posted must
3774 * be visible before we perform the barrier operation,
3775 * such that if a subsequent interrupt arrives, irq_posted
3776 * is reasserted and our task rewoken (which causes us to
3777 * do another __i915_request_irq_complete() immediately
3778 * and reapply the barrier). Conversely, if the clear
3779 * occurs after the barrier, then an interrupt that arrived
3780 * whilst we waited on the barrier would not trigger a
3781 * barrier on the next pass, and the read may not see the
3784 engine
->irq_seqno_barrier(engine
);
3786 /* If we consume the irq, but we are no longer the bottom-half,
3787 * the real bottom-half may not have serialised their own
3788 * seqno check with the irq-barrier (i.e. may have inspected
3789 * the seqno before we believe it coherent since they see
3790 * irq_posted == false but we are still running).
3793 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
3794 if (tsk
&& tsk
!= current
)
3795 /* Note that if the bottom-half is changed as we
3796 * are sending the wake-up, the new bottom-half will
3797 * be woken by whomever made the change. We only have
3798 * to worry about when we steal the irq-posted for
3801 wake_up_process(tsk
);
3804 if (__i915_gem_request_completed(req
))
3811 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
3812 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
3815 int remap_io_mapping(struct vm_area_struct
*vma
,
3816 unsigned long addr
, unsigned long pfn
, unsigned long size
,
3817 struct io_mapping
*iomap
);
3819 #define ptr_mask_bits(ptr) ({ \
3820 unsigned long __v = (unsigned long)(ptr); \
3821 (typeof(ptr))(__v & PAGE_MASK); \
3824 #define ptr_unpack_bits(ptr, bits) ({ \
3825 unsigned long __v = (unsigned long)(ptr); \
3826 (bits) = __v & ~PAGE_MASK; \
3827 (typeof(ptr))(__v & PAGE_MASK); \
3830 #define ptr_pack_bits(ptr, bits) \
3831 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3833 #define fetch_and_zero(ptr) ({ \
3834 typeof(*ptr) __T = *(ptr); \
3835 *(ptr) = (typeof(*ptr))0; \