1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150313"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES
= _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 3
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain
{
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
173 POWER_DOMAIN_TRANSCODER_A
,
174 POWER_DOMAIN_TRANSCODER_B
,
175 POWER_DOMAIN_TRANSCODER_C
,
176 POWER_DOMAIN_TRANSCODER_EDP
,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
185 POWER_DOMAIN_PORT_DSI
,
186 POWER_DOMAIN_PORT_CRT
,
187 POWER_DOMAIN_PORT_OTHER
,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
210 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_crtc(dev, intel_crtc) \
242 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
244 #define for_each_intel_encoder(dev, intel_encoder) \
245 list_for_each_entry(intel_encoder, \
246 &(dev)->mode_config.encoder_list, \
249 #define for_each_intel_connector(dev, intel_connector) \
250 list_for_each_entry(intel_connector, \
251 &dev->mode_config.connector_list, \
255 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
256 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
257 if ((intel_encoder)->base.crtc == (__crtc))
259 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
260 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
261 if ((intel_connector)->base.encoder == (__encoder))
263 #define for_each_power_domain(domain, mask) \
264 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
265 if ((1 << (domain)) & (mask))
267 struct drm_i915_private
;
268 struct i915_mm_struct
;
269 struct i915_mmu_object
;
272 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
273 /* real shared dpll ids must be >= 0 */
274 DPLL_ID_PCH_PLL_A
= 0,
275 DPLL_ID_PCH_PLL_B
= 1,
280 DPLL_ID_SKL_DPLL1
= 0,
281 DPLL_ID_SKL_DPLL2
= 1,
282 DPLL_ID_SKL_DPLL3
= 2,
284 #define I915_NUM_PLLS 3
286 struct intel_dpll_hw_state
{
298 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
299 * lower part of crtl1 and they get shifted into position when writing
300 * the register. This allows us to easily compare the state to share
304 /* HDMI only, 0 when used for DP */
305 uint32_t cfgcr1
, cfgcr2
;
308 struct intel_shared_dpll_config
{
309 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
310 struct intel_dpll_hw_state hw_state
;
313 struct intel_shared_dpll
{
314 struct intel_shared_dpll_config config
;
315 struct intel_shared_dpll_config
*new_config
;
317 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
318 bool on
; /* is the PLL actually active? Disabled during modeset */
320 /* should match the index in the dev_priv->shared_dplls array */
321 enum intel_dpll_id id
;
322 /* The mode_set hook is optional and should be used together with the
323 * intel_prepare_shared_dpll function. */
324 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
325 struct intel_shared_dpll
*pll
);
326 void (*enable
)(struct drm_i915_private
*dev_priv
,
327 struct intel_shared_dpll
*pll
);
328 void (*disable
)(struct drm_i915_private
*dev_priv
,
329 struct intel_shared_dpll
*pll
);
330 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
331 struct intel_shared_dpll
*pll
,
332 struct intel_dpll_hw_state
*hw_state
);
340 /* Used by dp and fdi links */
341 struct intel_link_m_n
{
349 void intel_link_compute_m_n(int bpp
, int nlanes
,
350 int pixel_clock
, int link_clock
,
351 struct intel_link_m_n
*m_n
);
353 /* Interface history:
356 * 1.2: Add Power Management
357 * 1.3: Add vblank support
358 * 1.4: Fix cmdbuffer path, add heap destroy
359 * 1.5: Add vblank pipe configuration
360 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
361 * - Support vertical blank on secondary display pipe
363 #define DRIVER_MAJOR 1
364 #define DRIVER_MINOR 6
365 #define DRIVER_PATCHLEVEL 0
367 #define WATCH_LISTS 0
369 struct opregion_header
;
370 struct opregion_acpi
;
371 struct opregion_swsci
;
372 struct opregion_asle
;
374 struct intel_opregion
{
375 struct opregion_header __iomem
*header
;
376 struct opregion_acpi __iomem
*acpi
;
377 struct opregion_swsci __iomem
*swsci
;
378 u32 swsci_gbda_sub_functions
;
379 u32 swsci_sbcb_sub_functions
;
380 struct opregion_asle __iomem
*asle
;
382 u32 __iomem
*lid_state
;
383 struct work_struct asle_work
;
385 #define OPREGION_SIZE (8*1024)
387 struct intel_overlay
;
388 struct intel_overlay_error_state
;
390 #define I915_FENCE_REG_NONE -1
391 #define I915_MAX_NUM_FENCES 32
392 /* 32 fences + sign bit for FENCE_REG_NONE */
393 #define I915_MAX_NUM_FENCE_BITS 6
395 struct drm_i915_fence_reg
{
396 struct list_head lru_list
;
397 struct drm_i915_gem_object
*obj
;
401 struct sdvo_device_mapping
{
410 struct intel_display_error_state
;
412 struct drm_i915_error_state
{
420 /* Generic register state */
428 u32 error
; /* gen6+ */
429 u32 err_int
; /* gen7 */
435 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
436 u64 fence
[I915_MAX_NUM_FENCES
];
437 struct intel_overlay_error_state
*overlay
;
438 struct intel_display_error_state
*display
;
439 struct drm_i915_error_object
*semaphore_obj
;
441 struct drm_i915_error_ring
{
443 /* Software tracked state */
446 enum intel_ring_hangcheck_action hangcheck_action
;
449 /* our own tracking of ring head and tail */
453 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
471 u32 rc_psmi
; /* sleep state */
472 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
474 struct drm_i915_error_object
{
478 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
480 struct drm_i915_error_request
{
495 char comm
[TASK_COMM_LEN
];
496 } ring
[I915_NUM_RINGS
];
498 struct drm_i915_error_buffer
{
505 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
513 } **active_bo
, **pinned_bo
;
515 u32
*active_bo_count
, *pinned_bo_count
;
519 struct intel_connector
;
520 struct intel_encoder
;
521 struct intel_crtc_state
;
522 struct intel_initial_plane_config
;
527 struct drm_i915_display_funcs
{
528 bool (*fbc_enabled
)(struct drm_device
*dev
);
529 void (*enable_fbc
)(struct drm_crtc
*crtc
);
530 void (*disable_fbc
)(struct drm_device
*dev
);
531 int (*get_display_clock_speed
)(struct drm_device
*dev
);
532 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
534 * find_dpll() - Find the best values for the PLL
535 * @limit: limits for the PLL
536 * @crtc: current CRTC
537 * @target: target frequency in kHz
538 * @refclk: reference clock frequency in kHz
539 * @match_clock: if provided, @best_clock P divider must
540 * match the P divider from @match_clock
541 * used for LVDS downclocking
542 * @best_clock: best PLL values found
544 * Returns true on success, false on failure.
546 bool (*find_dpll
)(const struct intel_limit
*limit
,
547 struct intel_crtc
*crtc
,
548 int target
, int refclk
,
549 struct dpll
*match_clock
,
550 struct dpll
*best_clock
);
551 void (*update_wm
)(struct drm_crtc
*crtc
);
552 void (*update_sprite_wm
)(struct drm_plane
*plane
,
553 struct drm_crtc
*crtc
,
554 uint32_t sprite_width
, uint32_t sprite_height
,
555 int pixel_size
, bool enable
, bool scaled
);
556 void (*modeset_global_resources
)(struct drm_device
*dev
);
557 /* Returns the active state of the crtc, and if the crtc is active,
558 * fills out the pipe-config with the hw state. */
559 bool (*get_pipe_config
)(struct intel_crtc
*,
560 struct intel_crtc_state
*);
561 void (*get_initial_plane_config
)(struct intel_crtc
*,
562 struct intel_initial_plane_config
*);
563 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
564 struct intel_crtc_state
*crtc_state
);
565 void (*crtc_enable
)(struct drm_crtc
*crtc
);
566 void (*crtc_disable
)(struct drm_crtc
*crtc
);
567 void (*off
)(struct drm_crtc
*crtc
);
568 void (*audio_codec_enable
)(struct drm_connector
*connector
,
569 struct intel_encoder
*encoder
,
570 struct drm_display_mode
*mode
);
571 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
572 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
573 void (*init_clock_gating
)(struct drm_device
*dev
);
574 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
575 struct drm_framebuffer
*fb
,
576 struct drm_i915_gem_object
*obj
,
577 struct intel_engine_cs
*ring
,
579 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
580 struct drm_framebuffer
*fb
,
582 void (*hpd_irq_setup
)(struct drm_device
*dev
);
583 /* clock updates for mode set */
585 /* render clock increase/decrease */
586 /* display clock increase/decrease */
587 /* pll clock increase/decrease */
589 int (*setup_backlight
)(struct intel_connector
*connector
, enum pipe pipe
);
590 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
591 void (*set_backlight
)(struct intel_connector
*connector
,
593 void (*disable_backlight
)(struct intel_connector
*connector
);
594 void (*enable_backlight
)(struct intel_connector
*connector
);
597 enum forcewake_domain_id
{
598 FW_DOMAIN_ID_RENDER
= 0,
599 FW_DOMAIN_ID_BLITTER
,
605 enum forcewake_domains
{
606 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
607 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
608 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
609 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
614 struct intel_uncore_funcs
{
615 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
616 enum forcewake_domains domains
);
617 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
618 enum forcewake_domains domains
);
620 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
621 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
622 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
623 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
625 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
626 uint8_t val
, bool trace
);
627 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
628 uint16_t val
, bool trace
);
629 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
630 uint32_t val
, bool trace
);
631 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
632 uint64_t val
, bool trace
);
635 struct intel_uncore
{
636 spinlock_t lock
; /** lock is also taken in irq contexts. */
638 struct intel_uncore_funcs funcs
;
641 enum forcewake_domains fw_domains
;
643 struct intel_uncore_forcewake_domain
{
644 struct drm_i915_private
*i915
;
645 enum forcewake_domain_id id
;
647 struct timer_list timer
;
654 } fw_domain
[FW_DOMAIN_ID_COUNT
];
657 /* Iterate over initialised fw domains */
658 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
659 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
660 (i__) < FW_DOMAIN_ID_COUNT; \
661 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
662 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
664 #define for_each_fw_domain(domain__, dev_priv__, i__) \
665 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
667 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
668 func(is_mobile) sep \
671 func(is_i945gm) sep \
673 func(need_gfx_hws) sep \
675 func(is_pineview) sep \
676 func(is_broadwater) sep \
677 func(is_crestline) sep \
678 func(is_ivybridge) sep \
679 func(is_valleyview) sep \
680 func(is_haswell) sep \
681 func(is_skylake) sep \
682 func(is_preliminary) sep \
684 func(has_pipe_cxsr) sep \
685 func(has_hotplug) sep \
686 func(cursor_needs_physical) sep \
687 func(has_overlay) sep \
688 func(overlay_needs_physical) sep \
689 func(supports_tv) sep \
694 #define DEFINE_FLAG(name) u8 name:1
695 #define SEP_SEMICOLON ;
697 struct intel_device_info
{
698 u32 display_mmio_offset
;
701 u8 num_sprites
[I915_MAX_PIPES
];
703 u8 ring_mask
; /* Rings supported by the HW */
704 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
705 /* Register offsets for the various display pipes and transcoders */
706 int pipe_offsets
[I915_MAX_TRANSCODERS
];
707 int trans_offsets
[I915_MAX_TRANSCODERS
];
708 int palette_offsets
[I915_MAX_PIPES
];
709 int cursor_offsets
[I915_MAX_PIPES
];
711 /* Slice/subslice/EU info */
714 u8 subslice_per_slice
;
717 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
720 u8 has_subslice_pg
:1;
727 enum i915_cache_level
{
729 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
730 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
731 caches, eg sampler/render caches, and the
732 large Last-Level-Cache. LLC is coherent with
733 the CPU, but L3 is only visible to the GPU. */
734 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
737 struct i915_ctx_hang_stats
{
738 /* This context had batch pending when hang was declared */
739 unsigned batch_pending
;
741 /* This context had batch active when hang was declared */
742 unsigned batch_active
;
744 /* Time when this context was last blamed for a GPU reset */
745 unsigned long guilty_ts
;
747 /* If the contexts causes a second GPU hang within this time,
748 * it is permanently banned from submitting any more work.
750 unsigned long ban_period_seconds
;
752 /* This context is banned to submit more work */
756 /* This must match up with the value previously used for execbuf2.rsvd1. */
757 #define DEFAULT_CONTEXT_HANDLE 0
759 * struct intel_context - as the name implies, represents a context.
760 * @ref: reference count.
761 * @user_handle: userspace tracking identity for this context.
762 * @remap_slice: l3 row remapping information.
763 * @file_priv: filp associated with this context (NULL for global default
765 * @hang_stats: information about the role of this context in possible GPU
767 * @vm: virtual memory space used by this context.
768 * @legacy_hw_ctx: render context backing object and whether it is correctly
769 * initialized (legacy ring submission mechanism only).
770 * @link: link in the global list of contexts.
772 * Contexts are memory images used by the hardware to store copies of their
775 struct intel_context
{
779 struct drm_i915_file_private
*file_priv
;
780 struct i915_ctx_hang_stats hang_stats
;
781 struct i915_hw_ppgtt
*ppgtt
;
783 /* Legacy ring buffer submission */
785 struct drm_i915_gem_object
*rcs_state
;
790 bool rcs_initialized
;
792 struct drm_i915_gem_object
*state
;
793 struct intel_ringbuffer
*ringbuf
;
795 } engine
[I915_NUM_RINGS
];
797 struct list_head link
;
808 unsigned long uncompressed_size
;
811 unsigned int possible_framebuffer_bits
;
812 unsigned int busy_bits
;
813 struct intel_crtc
*crtc
;
816 struct drm_mm_node compressed_fb
;
817 struct drm_mm_node
*compressed_llb
;
821 /* Tracks whether the HW is actually enabled, not whether the feature is
825 struct intel_fbc_work
{
826 struct delayed_work work
;
827 struct drm_crtc
*crtc
;
828 struct drm_framebuffer
*fb
;
832 FBC_OK
, /* FBC is enabled */
833 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
834 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
835 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
836 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
837 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
838 FBC_BAD_PLANE
, /* fbc not supported on plane */
839 FBC_NOT_TILED
, /* buffer not tiled */
840 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
842 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
847 * HIGH_RR is the highest eDP panel refresh rate read from EDID
848 * LOW_RR is the lowest eDP panel refresh rate found from EDID
849 * parsing for same resolution.
851 enum drrs_refresh_rate_type
{
854 DRRS_MAX_RR
, /* RR count */
857 enum drrs_support_type
{
858 DRRS_NOT_SUPPORTED
= 0,
859 STATIC_DRRS_SUPPORT
= 1,
860 SEAMLESS_DRRS_SUPPORT
= 2
866 struct delayed_work work
;
868 unsigned busy_frontbuffer_bits
;
869 enum drrs_refresh_rate_type refresh_rate_type
;
870 enum drrs_support_type type
;
877 struct intel_dp
*enabled
;
879 struct delayed_work work
;
880 unsigned busy_frontbuffer_bits
;
885 PCH_NONE
= 0, /* No PCH present */
886 PCH_IBX
, /* Ibexpeak PCH */
887 PCH_CPT
, /* Cougarpoint PCH */
888 PCH_LPT
, /* Lynxpoint PCH */
889 PCH_SPT
, /* Sunrisepoint PCH */
893 enum intel_sbi_destination
{
898 #define QUIRK_PIPEA_FORCE (1<<0)
899 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
900 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
901 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
902 #define QUIRK_PIPEB_FORCE (1<<4)
903 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
906 struct intel_fbc_work
;
909 struct i2c_adapter adapter
;
913 struct i2c_algo_bit_data bit_algo
;
914 struct drm_i915_private
*dev_priv
;
917 struct i915_suspend_saved_registers
{
920 u32 savePP_ON_DELAYS
;
921 u32 savePP_OFF_DELAYS
;
927 u32 saveCACHE_MODE_0
;
928 u32 saveMI_ARB_STATE
;
932 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
933 u32 savePCH_PORT_HOTPLUG
;
937 struct vlv_s0ix_state
{
944 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
945 u32 media_max_req_count
;
946 u32 gfx_max_req_count
;
978 /* Display 1 CZ domain */
983 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
985 /* GT SA CZ domain */
992 /* Display 2 CZ domain */
998 struct intel_rps_ei
{
1004 struct intel_gen6_power_mgmt
{
1006 * work, interrupts_enabled and pm_iir are protected by
1007 * dev_priv->irq_lock
1009 struct work_struct work
;
1010 bool interrupts_enabled
;
1013 /* Frequencies are stored in potentially platform dependent multiples.
1014 * In other words, *_freq needs to be multiplied by X to be interesting.
1015 * Soft limits are those which are used for the dynamic reclocking done
1016 * by the driver (raise frequencies under heavy loads, and lower for
1017 * lighter loads). Hard limits are those imposed by the hardware.
1019 * A distinction is made for overclocking, which is never enabled by
1020 * default, and is considered to be above the hard limit if it's
1023 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1024 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1025 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1026 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1027 u8 min_freq
; /* AKA RPn. Minimum frequency */
1028 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1029 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1030 u8 rp0_freq
; /* Non-overclocked max frequency. */
1033 u32 ei_interrupt_count
;
1036 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1039 struct delayed_work delayed_resume_work
;
1041 /* manual wa residency calculations */
1042 struct intel_rps_ei up_ei
, down_ei
;
1045 * Protects RPS/RC6 register access and PCU communication.
1046 * Must be taken after struct_mutex if nested.
1048 struct mutex hw_lock
;
1051 /* defined intel_pm.c */
1052 extern spinlock_t mchdev_lock
;
1054 struct intel_ilk_power_mgmt
{
1062 unsigned long last_time1
;
1063 unsigned long chipset_power
;
1066 unsigned long gfx_power
;
1073 struct drm_i915_private
;
1074 struct i915_power_well
;
1076 struct i915_power_well_ops
{
1078 * Synchronize the well's hw state to match the current sw state, for
1079 * example enable/disable it based on the current refcount. Called
1080 * during driver init and resume time, possibly after first calling
1081 * the enable/disable handlers.
1083 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1084 struct i915_power_well
*power_well
);
1086 * Enable the well and resources that depend on it (for example
1087 * interrupts located on the well). Called after the 0->1 refcount
1090 void (*enable
)(struct drm_i915_private
*dev_priv
,
1091 struct i915_power_well
*power_well
);
1093 * Disable the well and resources that depend on it. Called after
1094 * the 1->0 refcount transition.
1096 void (*disable
)(struct drm_i915_private
*dev_priv
,
1097 struct i915_power_well
*power_well
);
1098 /* Returns the hw enabled state. */
1099 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1100 struct i915_power_well
*power_well
);
1103 /* Power well structure for haswell */
1104 struct i915_power_well
{
1107 /* power well enable/disable usage count */
1109 /* cached hw enabled state */
1111 unsigned long domains
;
1113 const struct i915_power_well_ops
*ops
;
1116 struct i915_power_domains
{
1118 * Power wells needed for initialization at driver init and suspend
1119 * time are on. They are kept on until after the first modeset.
1123 int power_well_count
;
1126 int domain_use_count
[POWER_DOMAIN_NUM
];
1127 struct i915_power_well
*power_wells
;
1130 #define MAX_L3_SLICES 2
1131 struct intel_l3_parity
{
1132 u32
*remap_info
[MAX_L3_SLICES
];
1133 struct work_struct error_work
;
1137 struct i915_gem_batch_pool
{
1138 struct drm_device
*dev
;
1139 struct list_head cache_list
;
1142 struct i915_gem_mm
{
1143 /** Memory allocator for GTT stolen memory */
1144 struct drm_mm stolen
;
1145 /** List of all objects in gtt_space. Used to restore gtt
1146 * mappings on resume */
1147 struct list_head bound_list
;
1149 * List of objects which are not bound to the GTT (thus
1150 * are idle and not used by the GPU) but still have
1151 * (presumably uncached) pages still attached.
1153 struct list_head unbound_list
;
1156 * A pool of objects to use as shadow copies of client batch buffers
1157 * when the command parser is enabled. Prevents the client from
1158 * modifying the batch contents after software parsing.
1160 struct i915_gem_batch_pool batch_pool
;
1162 /** Usable portion of the GTT for GEM */
1163 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1165 /** PPGTT used for aliasing the PPGTT with the GTT */
1166 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1168 struct notifier_block oom_notifier
;
1169 struct shrinker shrinker
;
1170 bool shrinker_no_lock_stealing
;
1172 /** LRU list of objects with fence regs on them. */
1173 struct list_head fence_list
;
1176 * We leave the user IRQ off as much as possible,
1177 * but this means that requests will finish and never
1178 * be retired once the system goes idle. Set a timer to
1179 * fire periodically while the ring is running. When it
1180 * fires, go retire requests.
1182 struct delayed_work retire_work
;
1185 * When we detect an idle GPU, we want to turn on
1186 * powersaving features. So once we see that there
1187 * are no more requests outstanding and no more
1188 * arrive within a small period of time, we fire
1189 * off the idle_work.
1191 struct delayed_work idle_work
;
1194 * Are we in a non-interruptible section of code like
1200 * Is the GPU currently considered idle, or busy executing userspace
1201 * requests? Whilst idle, we attempt to power down the hardware and
1202 * display clocks. In order to reduce the effect on performance, there
1203 * is a slight delay before we do so.
1207 /* the indicator for dispatch video commands on two BSD rings */
1208 int bsd_ring_dispatch_index
;
1210 /** Bit 6 swizzling required for X tiling */
1211 uint32_t bit_6_swizzle_x
;
1212 /** Bit 6 swizzling required for Y tiling */
1213 uint32_t bit_6_swizzle_y
;
1215 /* accounting, useful for userland debugging */
1216 spinlock_t object_stat_lock
;
1217 size_t object_memory
;
1221 struct drm_i915_error_state_buf
{
1222 struct drm_i915_private
*i915
;
1231 struct i915_error_state_file_priv
{
1232 struct drm_device
*dev
;
1233 struct drm_i915_error_state
*error
;
1236 struct i915_gpu_error
{
1237 /* For hangcheck timer */
1238 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1239 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1240 /* Hang gpu twice in this window and your context gets banned */
1241 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1243 struct workqueue_struct
*hangcheck_wq
;
1244 struct delayed_work hangcheck_work
;
1246 /* For reset and error_state handling. */
1248 /* Protected by the above dev->gpu_error.lock. */
1249 struct drm_i915_error_state
*first_error
;
1251 unsigned long missed_irq_rings
;
1254 * State variable controlling the reset flow and count
1256 * This is a counter which gets incremented when reset is triggered,
1257 * and again when reset has been handled. So odd values (lowest bit set)
1258 * means that reset is in progress and even values that
1259 * (reset_counter >> 1):th reset was successfully completed.
1261 * If reset is not completed succesfully, the I915_WEDGE bit is
1262 * set meaning that hardware is terminally sour and there is no
1263 * recovery. All waiters on the reset_queue will be woken when
1266 * This counter is used by the wait_seqno code to notice that reset
1267 * event happened and it needs to restart the entire ioctl (since most
1268 * likely the seqno it waited for won't ever signal anytime soon).
1270 * This is important for lock-free wait paths, where no contended lock
1271 * naturally enforces the correct ordering between the bail-out of the
1272 * waiter and the gpu reset work code.
1274 atomic_t reset_counter
;
1276 #define I915_RESET_IN_PROGRESS_FLAG 1
1277 #define I915_WEDGED (1 << 31)
1280 * Waitqueue to signal when the reset has completed. Used by clients
1281 * that wait for dev_priv->mm.wedged to settle.
1283 wait_queue_head_t reset_queue
;
1285 /* Userspace knobs for gpu hang simulation;
1286 * combines both a ring mask, and extra flags
1289 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1290 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1292 /* For missed irq/seqno simulation. */
1293 unsigned int test_irq_rings
;
1295 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1296 bool reload_in_reset
;
1299 enum modeset_restore
{
1300 MODESET_ON_LID_OPEN
,
1305 struct ddi_vbt_port_info
{
1307 * This is an index in the HDMI/DVI DDI buffer translation table.
1308 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1309 * populate this field.
1311 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1312 uint8_t hdmi_level_shift
;
1314 uint8_t supports_dvi
:1;
1315 uint8_t supports_hdmi
:1;
1316 uint8_t supports_dp
:1;
1319 enum psr_lines_to_wait
{
1320 PSR_0_LINES_TO_WAIT
= 0,
1322 PSR_4_LINES_TO_WAIT
,
1326 struct intel_vbt_data
{
1327 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1328 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1331 unsigned int int_tv_support
:1;
1332 unsigned int lvds_dither
:1;
1333 unsigned int lvds_vbt
:1;
1334 unsigned int int_crt_support
:1;
1335 unsigned int lvds_use_ssc
:1;
1336 unsigned int display_clock_mode
:1;
1337 unsigned int fdi_rx_polarity_inverted
:1;
1338 unsigned int has_mipi
:1;
1340 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1342 enum drrs_support_type drrs_type
;
1347 int edp_preemphasis
;
1349 bool edp_initialized
;
1352 bool edp_low_vswing
;
1353 struct edp_power_seq edp_pps
;
1357 bool require_aux_wakeup
;
1359 enum psr_lines_to_wait lines_to_wait
;
1360 int tp1_wakeup_time
;
1361 int tp2_tp3_wakeup_time
;
1367 bool active_low_pwm
;
1368 u8 min_brightness
; /* min_brightness/255 of max */
1375 struct mipi_config
*config
;
1376 struct mipi_pps_data
*pps
;
1380 u8
*sequence
[MIPI_SEQ_MAX
];
1386 union child_device_config
*child_dev
;
1388 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1391 enum intel_ddb_partitioning
{
1393 INTEL_DDB_PART_5_6
, /* IVB+ */
1396 struct intel_wm_level
{
1404 struct ilk_wm_values
{
1405 uint32_t wm_pipe
[3];
1407 uint32_t wm_lp_spr
[3];
1408 uint32_t wm_linetime
[3];
1410 enum intel_ddb_partitioning partitioning
;
1413 struct vlv_wm_values
{
1432 struct skl_ddb_entry
{
1433 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1436 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1438 return entry
->end
- entry
->start
;
1441 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1442 const struct skl_ddb_entry
*e2
)
1444 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1450 struct skl_ddb_allocation
{
1451 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1452 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1453 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1456 struct skl_wm_values
{
1457 bool dirty
[I915_MAX_PIPES
];
1458 struct skl_ddb_allocation ddb
;
1459 uint32_t wm_linetime
[I915_MAX_PIPES
];
1460 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1461 uint32_t cursor
[I915_MAX_PIPES
][8];
1462 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1463 uint32_t cursor_trans
[I915_MAX_PIPES
];
1466 struct skl_wm_level
{
1467 bool plane_en
[I915_MAX_PLANES
];
1469 uint16_t plane_res_b
[I915_MAX_PLANES
];
1470 uint8_t plane_res_l
[I915_MAX_PLANES
];
1471 uint16_t cursor_res_b
;
1472 uint8_t cursor_res_l
;
1476 * This struct helps tracking the state needed for runtime PM, which puts the
1477 * device in PCI D3 state. Notice that when this happens, nothing on the
1478 * graphics device works, even register access, so we don't get interrupts nor
1481 * Every piece of our code that needs to actually touch the hardware needs to
1482 * either call intel_runtime_pm_get or call intel_display_power_get with the
1483 * appropriate power domain.
1485 * Our driver uses the autosuspend delay feature, which means we'll only really
1486 * suspend if we stay with zero refcount for a certain amount of time. The
1487 * default value is currently very conservative (see intel_runtime_pm_enable), but
1488 * it can be changed with the standard runtime PM files from sysfs.
1490 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1491 * goes back to false exactly before we reenable the IRQs. We use this variable
1492 * to check if someone is trying to enable/disable IRQs while they're supposed
1493 * to be disabled. This shouldn't happen and we'll print some error messages in
1496 * For more, read the Documentation/power/runtime_pm.txt.
1498 struct i915_runtime_pm
{
1503 enum intel_pipe_crc_source
{
1504 INTEL_PIPE_CRC_SOURCE_NONE
,
1505 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1506 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1507 INTEL_PIPE_CRC_SOURCE_PF
,
1508 INTEL_PIPE_CRC_SOURCE_PIPE
,
1509 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1510 INTEL_PIPE_CRC_SOURCE_TV
,
1511 INTEL_PIPE_CRC_SOURCE_DP_B
,
1512 INTEL_PIPE_CRC_SOURCE_DP_C
,
1513 INTEL_PIPE_CRC_SOURCE_DP_D
,
1514 INTEL_PIPE_CRC_SOURCE_AUTO
,
1515 INTEL_PIPE_CRC_SOURCE_MAX
,
1518 struct intel_pipe_crc_entry
{
1523 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1524 struct intel_pipe_crc
{
1526 bool opened
; /* exclusive access to the result file */
1527 struct intel_pipe_crc_entry
*entries
;
1528 enum intel_pipe_crc_source source
;
1530 wait_queue_head_t wq
;
1533 struct i915_frontbuffer_tracking
{
1537 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1544 struct i915_wa_reg
{
1547 /* bitmask representing WA bits */
1551 #define I915_MAX_WA_REGS 16
1553 struct i915_workarounds
{
1554 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1558 struct i915_virtual_gpu
{
1562 struct drm_i915_private
{
1563 struct drm_device
*dev
;
1564 struct kmem_cache
*slab
;
1566 const struct intel_device_info info
;
1568 int relative_constants_mode
;
1572 struct intel_uncore uncore
;
1574 struct i915_virtual_gpu vgpu
;
1576 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1579 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1580 * controller on different i2c buses. */
1581 struct mutex gmbus_mutex
;
1584 * Base address of the gmbus and gpio block.
1586 uint32_t gpio_mmio_base
;
1588 /* MMIO base address for MIPI regs */
1589 uint32_t mipi_mmio_base
;
1591 wait_queue_head_t gmbus_wait_queue
;
1593 struct pci_dev
*bridge_dev
;
1594 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1595 struct drm_i915_gem_object
*semaphore_obj
;
1596 uint32_t last_seqno
, next_seqno
;
1598 struct drm_dma_handle
*status_page_dmah
;
1599 struct resource mch_res
;
1601 /* protects the irq masks */
1602 spinlock_t irq_lock
;
1604 /* protects the mmio flip data */
1605 spinlock_t mmio_flip_lock
;
1607 bool display_irqs_enabled
;
1609 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1610 struct pm_qos_request pm_qos
;
1612 /* DPIO indirect register protection */
1613 struct mutex dpio_lock
;
1615 /** Cached value of IMR to avoid reads in updating the bitfield */
1618 u32 de_irq_mask
[I915_MAX_PIPES
];
1623 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1625 struct work_struct hotplug_work
;
1627 unsigned long hpd_last_jiffies
;
1632 HPD_MARK_DISABLED
= 2
1634 } hpd_stats
[HPD_NUM_PINS
];
1636 struct delayed_work hotplug_reenable_work
;
1638 struct i915_fbc fbc
;
1639 struct i915_drrs drrs
;
1640 struct intel_opregion opregion
;
1641 struct intel_vbt_data vbt
;
1643 bool preserve_bios_swizzle
;
1646 struct intel_overlay
*overlay
;
1648 /* backlight registers and fields in struct intel_panel */
1649 struct mutex backlight_lock
;
1652 bool no_aux_handshake
;
1654 /* protects panel power sequencer state */
1655 struct mutex pps_mutex
;
1657 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1658 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1659 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1661 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1662 unsigned int vlv_cdclk_freq
;
1663 unsigned int hpll_freq
;
1666 * wq - Driver workqueue for GEM.
1668 * NOTE: Work items scheduled here are not allowed to grab any modeset
1669 * locks, for otherwise the flushing done in the pageflip code will
1670 * result in deadlocks.
1672 struct workqueue_struct
*wq
;
1674 /* Display functions */
1675 struct drm_i915_display_funcs display
;
1677 /* PCH chipset type */
1678 enum intel_pch pch_type
;
1679 unsigned short pch_id
;
1681 unsigned long quirks
;
1683 enum modeset_restore modeset_restore
;
1684 struct mutex modeset_restore_lock
;
1686 struct list_head vm_list
; /* Global list of all address spaces */
1687 struct i915_gtt gtt
; /* VM representing the global address space */
1689 struct i915_gem_mm mm
;
1690 DECLARE_HASHTABLE(mm_structs
, 7);
1691 struct mutex mm_lock
;
1693 /* Kernel Modesetting */
1695 struct sdvo_device_mapping sdvo_mappings
[2];
1697 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1698 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1699 wait_queue_head_t pending_flip_queue
;
1701 #ifdef CONFIG_DEBUG_FS
1702 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1705 int num_shared_dpll
;
1706 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1707 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1709 struct i915_workarounds workarounds
;
1711 /* Reclocking support */
1712 bool render_reclock_avail
;
1713 bool lvds_downclock_avail
;
1714 /* indicates the reduced downclock for LVDS*/
1717 struct i915_frontbuffer_tracking fb_tracking
;
1721 bool mchbar_need_disable
;
1723 struct intel_l3_parity l3_parity
;
1725 /* Cannot be determined by PCIID. You must always read a register. */
1728 /* gen6+ rps state */
1729 struct intel_gen6_power_mgmt rps
;
1731 /* ilk-only ips/rps state. Everything in here is protected by the global
1732 * mchdev_lock in intel_pm.c */
1733 struct intel_ilk_power_mgmt ips
;
1735 struct i915_power_domains power_domains
;
1737 struct i915_psr psr
;
1739 struct i915_gpu_error gpu_error
;
1741 struct drm_i915_gem_object
*vlv_pctx
;
1743 #ifdef CONFIG_DRM_I915_FBDEV
1744 /* list of fbdev register on this device */
1745 struct intel_fbdev
*fbdev
;
1746 struct work_struct fbdev_suspend_work
;
1749 struct drm_property
*broadcast_rgb_property
;
1750 struct drm_property
*force_audio_property
;
1752 /* hda/i915 audio component */
1753 bool audio_component_registered
;
1755 uint32_t hw_context_size
;
1756 struct list_head context_list
;
1761 struct i915_suspend_saved_registers regfile
;
1762 struct vlv_s0ix_state vlv_s0ix_state
;
1766 * Raw watermark latency values:
1767 * in 0.1us units for WM0,
1768 * in 0.5us units for WM1+.
1771 uint16_t pri_latency
[5];
1773 uint16_t spr_latency
[5];
1775 uint16_t cur_latency
[5];
1777 * Raw watermark memory latency values
1778 * for SKL for all 8 levels
1781 uint16_t skl_latency
[8];
1784 * The skl_wm_values structure is a bit too big for stack
1785 * allocation, so we keep the staging struct where we store
1786 * intermediate results here instead.
1788 struct skl_wm_values skl_results
;
1790 /* current hardware state */
1792 struct ilk_wm_values hw
;
1793 struct skl_wm_values skl_hw
;
1794 struct vlv_wm_values vlv
;
1798 struct i915_runtime_pm pm
;
1800 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1801 u32 long_hpd_port_mask
;
1802 u32 short_hpd_port_mask
;
1803 struct work_struct dig_port_work
;
1806 * if we get a HPD irq from DP and a HPD irq from non-DP
1807 * the non-DP HPD could block the workqueue on a mode config
1808 * mutex getting, that userspace may have taken. However
1809 * userspace is waiting on the DP workqueue to run which is
1810 * blocked behind the non-DP one.
1812 struct workqueue_struct
*dp_wq
;
1814 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1816 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1817 struct intel_engine_cs
*ring
,
1818 struct intel_context
*ctx
,
1819 struct drm_i915_gem_execbuffer2
*args
,
1820 struct list_head
*vmas
,
1821 struct drm_i915_gem_object
*batch_obj
,
1822 u64 exec_start
, u32 flags
);
1823 int (*init_rings
)(struct drm_device
*dev
);
1824 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1825 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1828 uint32_t request_uniq
;
1831 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1832 * will be rejected. Instead look for a better place.
1836 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1838 return dev
->dev_private
;
1841 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1843 return to_i915(dev_get_drvdata(dev
));
1846 /* Iterate over initialised rings */
1847 #define for_each_ring(ring__, dev_priv__, i__) \
1848 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1849 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1851 enum hdmi_force_audio
{
1852 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1853 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1854 HDMI_AUDIO_AUTO
, /* trust EDID */
1855 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1858 #define I915_GTT_OFFSET_NONE ((u32)-1)
1860 struct drm_i915_gem_object_ops
{
1861 /* Interface between the GEM object and its backing storage.
1862 * get_pages() is called once prior to the use of the associated set
1863 * of pages before to binding them into the GTT, and put_pages() is
1864 * called after we no longer need them. As we expect there to be
1865 * associated cost with migrating pages between the backing storage
1866 * and making them available for the GPU (e.g. clflush), we may hold
1867 * onto the pages after they are no longer referenced by the GPU
1868 * in case they may be used again shortly (for example migrating the
1869 * pages to a different memory domain within the GTT). put_pages()
1870 * will therefore most likely be called when the object itself is
1871 * being released or under memory pressure (where we attempt to
1872 * reap pages for the shrinker).
1874 int (*get_pages
)(struct drm_i915_gem_object
*);
1875 void (*put_pages
)(struct drm_i915_gem_object
*);
1876 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1877 void (*release
)(struct drm_i915_gem_object
*);
1881 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1882 * considered to be the frontbuffer for the given plane interface-vise. This
1883 * doesn't mean that the hw necessarily already scans it out, but that any
1884 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1886 * We have one bit per pipe and per scanout plane type.
1888 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1889 #define INTEL_FRONTBUFFER_BITS \
1890 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1891 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1892 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1893 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1894 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1895 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1896 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1897 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1898 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1899 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1900 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1902 struct drm_i915_gem_object
{
1903 struct drm_gem_object base
;
1905 const struct drm_i915_gem_object_ops
*ops
;
1907 /** List of VMAs backed by this object */
1908 struct list_head vma_list
;
1910 /** Stolen memory for this object, instead of being backed by shmem. */
1911 struct drm_mm_node
*stolen
;
1912 struct list_head global_list
;
1914 struct list_head ring_list
;
1915 /** Used in execbuf to temporarily hold a ref */
1916 struct list_head obj_exec_link
;
1918 struct list_head batch_pool_list
;
1921 * This is set if the object is on the active lists (has pending
1922 * rendering and so a non-zero seqno), and is not set if it i s on
1923 * inactive (ready to be unbound) list.
1925 unsigned int active
:1;
1928 * This is set if the object has been written to since last bound
1931 unsigned int dirty
:1;
1934 * Fence register bits (if any) for this object. Will be set
1935 * as needed when mapped into the GTT.
1936 * Protected by dev->struct_mutex.
1938 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1941 * Advice: are the backing pages purgeable?
1943 unsigned int madv
:2;
1946 * Current tiling mode for the object.
1948 unsigned int tiling_mode
:2;
1950 * Whether the tiling parameters for the currently associated fence
1951 * register have changed. Note that for the purposes of tracking
1952 * tiling changes we also treat the unfenced register, the register
1953 * slot that the object occupies whilst it executes a fenced
1954 * command (such as BLT on gen2/3), as a "fence".
1956 unsigned int fence_dirty
:1;
1959 * Is the object at the current location in the gtt mappable and
1960 * fenceable? Used to avoid costly recalculations.
1962 unsigned int map_and_fenceable
:1;
1965 * Whether the current gtt mapping needs to be mappable (and isn't just
1966 * mappable by accident). Track pin and fault separate for a more
1967 * accurate mappable working set.
1969 unsigned int fault_mappable
:1;
1970 unsigned int pin_mappable
:1;
1971 unsigned int pin_display
:1;
1974 * Is the object to be mapped as read-only to the GPU
1975 * Only honoured if hardware has relevant pte bit
1977 unsigned long gt_ro
:1;
1978 unsigned int cache_level
:3;
1979 unsigned int cache_dirty
:1;
1981 unsigned int has_dma_mapping
:1;
1983 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1985 struct sg_table
*pages
;
1986 int pages_pin_count
;
1988 /* prime dma-buf support */
1989 void *dma_buf_vmapping
;
1992 /** Breadcrumb of last rendering to the buffer. */
1993 struct drm_i915_gem_request
*last_read_req
;
1994 struct drm_i915_gem_request
*last_write_req
;
1995 /** Breadcrumb of last fenced GPU access to the buffer. */
1996 struct drm_i915_gem_request
*last_fenced_req
;
1998 /** Current tiling stride for the object, if it's tiled. */
2001 /** References from framebuffers, locks out tiling changes. */
2002 unsigned long framebuffer_references
;
2004 /** Record of address bit 17 of each page at last unbind. */
2005 unsigned long *bit_17
;
2008 /** for phy allocated objects */
2009 struct drm_dma_handle
*phys_handle
;
2011 struct i915_gem_userptr
{
2013 unsigned read_only
:1;
2014 unsigned workers
:4;
2015 #define I915_GEM_USERPTR_MAX_WORKERS 15
2017 struct i915_mm_struct
*mm
;
2018 struct i915_mmu_object
*mmu_object
;
2019 struct work_struct
*work
;
2023 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2025 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2026 struct drm_i915_gem_object
*new,
2027 unsigned frontbuffer_bits
);
2030 * Request queue structure.
2032 * The request queue allows us to note sequence numbers that have been emitted
2033 * and may be associated with active buffers to be retired.
2035 * By keeping this list, we can avoid having to do questionable sequence
2036 * number comparisons on buffer last_read|write_seqno. It also allows an
2037 * emission time to be associated with the request for tracking how far ahead
2038 * of the GPU the submission is.
2040 * The requests are reference counted, so upon creation they should have an
2041 * initial reference taken using kref_init
2043 struct drm_i915_gem_request
{
2046 /** On Which ring this request was generated */
2047 struct intel_engine_cs
*ring
;
2049 /** GEM sequence number associated with this request. */
2052 /** Position in the ringbuffer of the start of the request */
2056 * Position in the ringbuffer of the start of the postfix.
2057 * This is required to calculate the maximum available ringbuffer
2058 * space without overwriting the postfix.
2062 /** Position in the ringbuffer of the end of the whole request */
2066 * Context and ring buffer related to this request
2067 * Contexts are refcounted, so when this request is associated with a
2068 * context, we must increment the context's refcount, to guarantee that
2069 * it persists while any request is linked to it. Requests themselves
2070 * are also refcounted, so the request will only be freed when the last
2071 * reference to it is dismissed, and the code in
2072 * i915_gem_request_free() will then decrement the refcount on the
2075 struct intel_context
*ctx
;
2076 struct intel_ringbuffer
*ringbuf
;
2078 /** Batch buffer related to this request if any */
2079 struct drm_i915_gem_object
*batch_obj
;
2081 /** Time at which this request was emitted, in jiffies. */
2082 unsigned long emitted_jiffies
;
2084 /** global list entry for this request */
2085 struct list_head list
;
2087 struct drm_i915_file_private
*file_priv
;
2088 /** file_priv list entry for this request */
2089 struct list_head client_list
;
2091 /** process identifier submitting this request */
2097 * The ELSP only accepts two elements at a time, so we queue
2098 * context/tail pairs on a given queue (ring->execlist_queue) until the
2099 * hardware is available. The queue serves a double purpose: we also use
2100 * it to keep track of the up to 2 contexts currently in the hardware
2101 * (usually one in execution and the other queued up by the GPU): We
2102 * only remove elements from the head of the queue when the hardware
2103 * informs us that an element has been completed.
2105 * All accesses to the queue are mediated by a spinlock
2106 * (ring->execlist_lock).
2109 /** Execlist link in the submission queue.*/
2110 struct list_head execlist_link
;
2112 /** Execlists no. of times this request has been sent to the ELSP */
2117 void i915_gem_request_free(struct kref
*req_ref
);
2119 static inline uint32_t
2120 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2122 return req
? req
->seqno
: 0;
2125 static inline struct intel_engine_cs
*
2126 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2128 return req
? req
->ring
: NULL
;
2132 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2134 kref_get(&req
->ref
);
2138 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2140 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2141 kref_put(&req
->ref
, i915_gem_request_free
);
2144 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2145 struct drm_i915_gem_request
*src
)
2148 i915_gem_request_reference(src
);
2151 i915_gem_request_unreference(*pdst
);
2157 * XXX: i915_gem_request_completed should be here but currently needs the
2158 * definition of i915_seqno_passed() which is below. It will be moved in
2159 * a later patch when the call to i915_seqno_passed() is obsoleted...
2162 struct drm_i915_file_private
{
2163 struct drm_i915_private
*dev_priv
;
2164 struct drm_file
*file
;
2168 struct list_head request_list
;
2169 struct delayed_work idle_work
;
2171 struct idr context_idr
;
2173 atomic_t rps_wait_boost
;
2174 struct intel_engine_cs
*bsd_ring
;
2178 * A command that requires special handling by the command parser.
2180 struct drm_i915_cmd_descriptor
{
2182 * Flags describing how the command parser processes the command.
2184 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2185 * a length mask if not set
2186 * CMD_DESC_SKIP: The command is allowed but does not follow the
2187 * standard length encoding for the opcode range in
2189 * CMD_DESC_REJECT: The command is never allowed
2190 * CMD_DESC_REGISTER: The command should be checked against the
2191 * register whitelist for the appropriate ring
2192 * CMD_DESC_MASTER: The command is allowed if the submitting process
2196 #define CMD_DESC_FIXED (1<<0)
2197 #define CMD_DESC_SKIP (1<<1)
2198 #define CMD_DESC_REJECT (1<<2)
2199 #define CMD_DESC_REGISTER (1<<3)
2200 #define CMD_DESC_BITMASK (1<<4)
2201 #define CMD_DESC_MASTER (1<<5)
2204 * The command's unique identification bits and the bitmask to get them.
2205 * This isn't strictly the opcode field as defined in the spec and may
2206 * also include type, subtype, and/or subop fields.
2214 * The command's length. The command is either fixed length (i.e. does
2215 * not include a length field) or has a length field mask. The flag
2216 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2217 * a length mask. All command entries in a command table must include
2218 * length information.
2226 * Describes where to find a register address in the command to check
2227 * against the ring's register whitelist. Only valid if flags has the
2228 * CMD_DESC_REGISTER bit set.
2235 #define MAX_CMD_DESC_BITMASKS 3
2237 * Describes command checks where a particular dword is masked and
2238 * compared against an expected value. If the command does not match
2239 * the expected value, the parser rejects it. Only valid if flags has
2240 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2243 * If the check specifies a non-zero condition_mask then the parser
2244 * only performs the check when the bits specified by condition_mask
2251 u32 condition_offset
;
2253 } bits
[MAX_CMD_DESC_BITMASKS
];
2257 * A table of commands requiring special handling by the command parser.
2259 * Each ring has an array of tables. Each table consists of an array of command
2260 * descriptors, which must be sorted with command opcodes in ascending order.
2262 struct drm_i915_cmd_table
{
2263 const struct drm_i915_cmd_descriptor
*table
;
2267 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2268 #define __I915__(p) ({ \
2269 struct drm_i915_private *__p; \
2270 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2271 __p = (struct drm_i915_private *)p; \
2272 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2273 __p = to_i915((struct drm_device *)p); \
2278 #define INTEL_INFO(p) (&__I915__(p)->info)
2279 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2280 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2282 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2283 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2284 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2285 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2286 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2287 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2288 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2289 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2290 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2291 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2292 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2293 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2294 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2295 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2296 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2297 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2298 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2299 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2300 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2301 INTEL_DEVID(dev) == 0x0152 || \
2302 INTEL_DEVID(dev) == 0x015a)
2303 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2304 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2305 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2306 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2307 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2308 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2309 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2310 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2311 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2312 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2313 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2314 (INTEL_DEVID(dev) & 0xf) == 0xe))
2315 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2316 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2317 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2318 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2319 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2320 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2321 /* ULX machines are also considered ULT. */
2322 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2323 INTEL_DEVID(dev) == 0x0A1E)
2324 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2326 #define SKL_REVID_A0 (0x0)
2327 #define SKL_REVID_B0 (0x1)
2328 #define SKL_REVID_C0 (0x2)
2329 #define SKL_REVID_D0 (0x3)
2330 #define SKL_REVID_E0 (0x4)
2333 * The genX designation typically refers to the render engine, so render
2334 * capability related checks should use IS_GEN, while display and other checks
2335 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2338 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2339 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2340 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2341 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2342 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2343 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2344 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2345 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2347 #define RENDER_RING (1<<RCS)
2348 #define BSD_RING (1<<VCS)
2349 #define BLT_RING (1<<BCS)
2350 #define VEBOX_RING (1<<VECS)
2351 #define BSD2_RING (1<<VCS2)
2352 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2353 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2354 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2355 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2356 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2357 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2358 __I915__(dev)->ellc_size)
2359 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2361 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2362 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2363 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2364 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2366 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2367 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2369 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2370 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2372 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2373 * even when in MSI mode. This results in spurious interrupt warnings if the
2374 * legacy irq no. is shared with another device. The kernel then disables that
2375 * interrupt source and so prevents the other device from working properly.
2377 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2378 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2380 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2381 * rows, which changed the alignment requirements and fence programming.
2383 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2385 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2386 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2387 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2388 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2389 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2391 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2392 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2393 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2395 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2397 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2398 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2399 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2400 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2402 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2403 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2404 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2405 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2407 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2408 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2409 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2410 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2411 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2412 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2413 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2414 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2416 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2417 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2418 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2419 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2420 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2421 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2422 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2424 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2426 /* DPF == dynamic parity feature */
2427 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2428 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2430 #define GT_FREQUENCY_MULTIPLIER 50
2431 #define GEN9_FREQ_SCALER 3
2433 #include "i915_trace.h"
2435 extern const struct drm_ioctl_desc i915_ioctls
[];
2436 extern int i915_max_ioctl
;
2438 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2439 extern int i915_resume_legacy(struct drm_device
*dev
);
2442 struct i915_params
{
2444 int panel_ignore_lid
;
2445 unsigned int powersave
;
2447 unsigned int lvds_downclock
;
2448 int lvds_channel_mode
;
2450 int vbt_sdvo_panel_type
;
2454 int enable_execlists
;
2456 unsigned int preliminary_hw_support
;
2457 int disable_power_well
;
2459 int invert_brightness
;
2460 int enable_cmd_parser
;
2461 /* leave bools at the end to not create holes */
2462 bool enable_hangcheck
;
2464 bool prefault_disable
;
2466 bool disable_display
;
2467 bool disable_vtd_wa
;
2470 bool verbose_state_checks
;
2471 bool nuclear_pageflip
;
2473 extern struct i915_params i915 __read_mostly
;
2476 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2477 extern int i915_driver_unload(struct drm_device
*);
2478 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2479 extern void i915_driver_lastclose(struct drm_device
* dev
);
2480 extern void i915_driver_preclose(struct drm_device
*dev
,
2481 struct drm_file
*file
);
2482 extern void i915_driver_postclose(struct drm_device
*dev
,
2483 struct drm_file
*file
);
2484 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2485 #ifdef CONFIG_COMPAT
2486 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2489 extern int intel_gpu_reset(struct drm_device
*dev
);
2490 extern int i915_reset(struct drm_device
*dev
);
2491 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2492 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2493 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2494 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2495 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2496 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2499 void i915_queue_hangcheck(struct drm_device
*dev
);
2501 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2502 const char *fmt
, ...);
2504 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2505 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2506 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2507 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2509 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2510 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2511 bool restore_forcewake
);
2512 extern void intel_uncore_init(struct drm_device
*dev
);
2513 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2514 extern void intel_uncore_fini(struct drm_device
*dev
);
2515 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2516 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2517 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2518 enum forcewake_domains domains
);
2519 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2520 enum forcewake_domains domains
);
2521 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2522 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2524 return to_i915(dev
)->vgpu
.active
;
2528 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2532 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2535 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2536 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2538 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2540 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2541 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2542 uint32_t interrupt_mask
,
2543 uint32_t enabled_irq_mask
);
2544 #define ibx_enable_display_interrupt(dev_priv, bits) \
2545 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2546 #define ibx_disable_display_interrupt(dev_priv, bits) \
2547 ibx_display_interrupt_update((dev_priv), (bits), 0)
2550 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2551 struct drm_file
*file_priv
);
2552 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2553 struct drm_file
*file_priv
);
2554 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2555 struct drm_file
*file_priv
);
2556 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2557 struct drm_file
*file_priv
);
2558 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2559 struct drm_file
*file_priv
);
2560 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2561 struct drm_file
*file_priv
);
2562 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2563 struct drm_file
*file_priv
);
2564 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2565 struct intel_engine_cs
*ring
);
2566 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2567 struct drm_file
*file
,
2568 struct intel_engine_cs
*ring
,
2569 struct drm_i915_gem_object
*obj
);
2570 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2571 struct drm_file
*file
,
2572 struct intel_engine_cs
*ring
,
2573 struct intel_context
*ctx
,
2574 struct drm_i915_gem_execbuffer2
*args
,
2575 struct list_head
*vmas
,
2576 struct drm_i915_gem_object
*batch_obj
,
2577 u64 exec_start
, u32 flags
);
2578 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2579 struct drm_file
*file_priv
);
2580 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2581 struct drm_file
*file_priv
);
2582 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2583 struct drm_file
*file_priv
);
2584 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2585 struct drm_file
*file
);
2586 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2587 struct drm_file
*file
);
2588 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2589 struct drm_file
*file_priv
);
2590 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2591 struct drm_file
*file_priv
);
2592 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2593 struct drm_file
*file_priv
);
2594 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2595 struct drm_file
*file_priv
);
2596 int i915_gem_init_userptr(struct drm_device
*dev
);
2597 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2598 struct drm_file
*file
);
2599 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2600 struct drm_file
*file_priv
);
2601 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2602 struct drm_file
*file_priv
);
2603 void i915_gem_load(struct drm_device
*dev
);
2604 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2607 #define I915_SHRINK_PURGEABLE 0x1
2608 #define I915_SHRINK_UNBOUND 0x2
2609 #define I915_SHRINK_BOUND 0x4
2610 void *i915_gem_object_alloc(struct drm_device
*dev
);
2611 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2612 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2613 const struct drm_i915_gem_object_ops
*ops
);
2614 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2616 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2617 struct i915_address_space
*vm
);
2618 void i915_gem_free_object(struct drm_gem_object
*obj
);
2619 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2621 #define PIN_MAPPABLE 0x1
2622 #define PIN_NONBLOCK 0x2
2623 #define PIN_GLOBAL 0x4
2624 #define PIN_OFFSET_BIAS 0x8
2625 #define PIN_OFFSET_MASK (~4095)
2627 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2628 struct i915_address_space
*vm
,
2632 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2633 const struct i915_ggtt_view
*view
,
2637 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2639 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2640 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2641 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2642 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2644 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2645 int *needs_clflush
);
2647 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2648 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2650 struct sg_page_iter sg_iter
;
2652 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2653 return sg_page_iter_page(&sg_iter
);
2657 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2659 BUG_ON(obj
->pages
== NULL
);
2660 obj
->pages_pin_count
++;
2662 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2664 BUG_ON(obj
->pages_pin_count
== 0);
2665 obj
->pages_pin_count
--;
2668 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2669 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2670 struct intel_engine_cs
*to
);
2671 void i915_vma_move_to_active(struct i915_vma
*vma
,
2672 struct intel_engine_cs
*ring
);
2673 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2674 struct drm_device
*dev
,
2675 struct drm_mode_create_dumb
*args
);
2676 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2677 uint32_t handle
, uint64_t *offset
);
2679 * Returns true if seq1 is later than seq2.
2682 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2684 return (int32_t)(seq1
- seq2
) >= 0;
2687 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2688 bool lazy_coherency
)
2692 BUG_ON(req
== NULL
);
2694 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2696 return i915_seqno_passed(seqno
, req
->seqno
);
2699 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2700 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2701 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2702 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2704 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2705 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2707 struct drm_i915_gem_request
*
2708 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2710 bool i915_gem_retire_requests(struct drm_device
*dev
);
2711 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2712 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2713 bool interruptible
);
2714 int __must_check
i915_gem_check_olr(struct drm_i915_gem_request
*req
);
2716 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2718 return unlikely(atomic_read(&error
->reset_counter
)
2719 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2722 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2724 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2727 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2729 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2732 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2734 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2735 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2738 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2740 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2741 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2744 void i915_gem_reset(struct drm_device
*dev
);
2745 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2746 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2747 int __must_check
i915_gem_init(struct drm_device
*dev
);
2748 int i915_gem_init_rings(struct drm_device
*dev
);
2749 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2750 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2751 void i915_gem_init_swizzling(struct drm_device
*dev
);
2752 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2753 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2754 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2755 int __i915_add_request(struct intel_engine_cs
*ring
,
2756 struct drm_file
*file
,
2757 struct drm_i915_gem_object
*batch_obj
);
2758 #define i915_add_request(ring) \
2759 __i915_add_request(ring, NULL, NULL)
2760 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2761 unsigned reset_counter
,
2764 struct drm_i915_file_private
*file_priv
);
2765 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2766 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2768 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2771 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2773 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2775 struct intel_engine_cs
*pipelined
);
2776 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2777 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2779 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2780 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2783 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2785 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2786 int tiling_mode
, bool fenced
);
2788 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2789 enum i915_cache_level cache_level
);
2791 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2792 struct dma_buf
*dma_buf
);
2794 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2795 struct drm_gem_object
*gem_obj
, int flags
);
2797 void i915_gem_restore_fences(struct drm_device
*dev
);
2800 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
2801 enum i915_ggtt_view_type view
);
2803 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2804 struct i915_address_space
*vm
);
2805 static inline unsigned long
2806 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
2808 return i915_gem_obj_ggtt_offset_view(o
, I915_GGTT_VIEW_NORMAL
);
2811 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2812 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
2813 enum i915_ggtt_view_type view
);
2814 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2815 struct i915_address_space
*vm
);
2817 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2818 struct i915_address_space
*vm
);
2820 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2821 struct i915_address_space
*vm
);
2823 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
2824 const struct i915_ggtt_view
*view
);
2827 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2828 struct i915_address_space
*vm
);
2830 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2831 const struct i915_ggtt_view
*view
);
2833 static inline struct i915_vma
*
2834 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
2836 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
2838 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
2840 /* Some GGTT VM helpers */
2841 #define i915_obj_to_ggtt(obj) \
2842 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2843 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2845 struct i915_address_space
*ggtt
=
2846 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2850 static inline struct i915_hw_ppgtt
*
2851 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2853 WARN_ON(i915_is_ggtt(vm
));
2855 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2859 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2861 return i915_gem_obj_ggtt_bound_view(obj
, I915_GGTT_VIEW_NORMAL
);
2864 static inline unsigned long
2865 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2867 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2870 static inline int __must_check
2871 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2875 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2876 alignment
, flags
| PIN_GLOBAL
);
2880 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2882 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2885 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2887 /* i915_gem_context.c */
2888 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2889 void i915_gem_context_fini(struct drm_device
*dev
);
2890 void i915_gem_context_reset(struct drm_device
*dev
);
2891 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2892 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2893 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2894 int i915_switch_context(struct intel_engine_cs
*ring
,
2895 struct intel_context
*to
);
2896 struct intel_context
*
2897 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2898 void i915_gem_context_free(struct kref
*ctx_ref
);
2899 struct drm_i915_gem_object
*
2900 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2901 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2903 kref_get(&ctx
->ref
);
2906 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2908 kref_put(&ctx
->ref
, i915_gem_context_free
);
2911 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2913 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2916 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2917 struct drm_file
*file
);
2918 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2919 struct drm_file
*file
);
2920 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
2921 struct drm_file
*file_priv
);
2922 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
2923 struct drm_file
*file_priv
);
2925 /* i915_gem_evict.c */
2926 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2927 struct i915_address_space
*vm
,
2930 unsigned cache_level
,
2931 unsigned long start
,
2934 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2935 int i915_gem_evict_everything(struct drm_device
*dev
);
2937 /* belongs in i915_gem_gtt.h */
2938 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2940 if (INTEL_INFO(dev
)->gen
< 6)
2941 intel_gtt_chipset_flush();
2944 /* i915_gem_stolen.c */
2945 int i915_gem_init_stolen(struct drm_device
*dev
);
2946 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2947 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2948 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2949 struct drm_i915_gem_object
*
2950 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2951 struct drm_i915_gem_object
*
2952 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2957 /* i915_gem_tiling.c */
2958 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2960 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2962 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2963 obj
->tiling_mode
!= I915_TILING_NONE
;
2966 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2967 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2968 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2970 /* i915_gem_debug.c */
2972 int i915_verify_lists(struct drm_device
*dev
);
2974 #define i915_verify_lists(dev) 0
2977 /* i915_debugfs.c */
2978 int i915_debugfs_init(struct drm_minor
*minor
);
2979 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2980 #ifdef CONFIG_DEBUG_FS
2981 void intel_display_crc_init(struct drm_device
*dev
);
2983 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2986 /* i915_gpu_error.c */
2988 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2989 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2990 const struct i915_error_state_file_priv
*error
);
2991 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2992 struct drm_i915_private
*i915
,
2993 size_t count
, loff_t pos
);
2994 static inline void i915_error_state_buf_release(
2995 struct drm_i915_error_state_buf
*eb
)
2999 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3000 const char *error_msg
);
3001 void i915_error_state_get(struct drm_device
*dev
,
3002 struct i915_error_state_file_priv
*error_priv
);
3003 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3004 void i915_destroy_error_state(struct drm_device
*dev
);
3006 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3007 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3009 /* i915_gem_batch_pool.c */
3010 void i915_gem_batch_pool_init(struct drm_device
*dev
,
3011 struct i915_gem_batch_pool
*pool
);
3012 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool
*pool
);
3013 struct drm_i915_gem_object
*
3014 i915_gem_batch_pool_get(struct i915_gem_batch_pool
*pool
, size_t size
);
3016 /* i915_cmd_parser.c */
3017 int i915_cmd_parser_get_version(void);
3018 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3019 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3020 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3021 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3022 struct drm_i915_gem_object
*batch_obj
,
3023 struct drm_i915_gem_object
*shadow_batch_obj
,
3024 u32 batch_start_offset
,
3028 /* i915_suspend.c */
3029 extern int i915_save_state(struct drm_device
*dev
);
3030 extern int i915_restore_state(struct drm_device
*dev
);
3033 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3034 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3037 extern int intel_setup_gmbus(struct drm_device
*dev
);
3038 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3039 static inline bool intel_gmbus_is_port_valid(unsigned port
)
3041 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
3044 extern struct i2c_adapter
*intel_gmbus_get_adapter(
3045 struct drm_i915_private
*dev_priv
, unsigned port
);
3046 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3047 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3048 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3050 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3052 extern void intel_i2c_reset(struct drm_device
*dev
);
3054 /* intel_opregion.c */
3056 extern int intel_opregion_setup(struct drm_device
*dev
);
3057 extern void intel_opregion_init(struct drm_device
*dev
);
3058 extern void intel_opregion_fini(struct drm_device
*dev
);
3059 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3060 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3062 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3065 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3066 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3067 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3068 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3070 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3075 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3083 extern void intel_register_dsm_handler(void);
3084 extern void intel_unregister_dsm_handler(void);
3086 static inline void intel_register_dsm_handler(void) { return; }
3087 static inline void intel_unregister_dsm_handler(void) { return; }
3088 #endif /* CONFIG_ACPI */
3091 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3092 extern void intel_modeset_init(struct drm_device
*dev
);
3093 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3094 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3095 extern void intel_connector_unregister(struct intel_connector
*);
3096 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3097 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
3098 bool force_restore
);
3099 extern void i915_redisable_vga(struct drm_device
*dev
);
3100 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3101 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3102 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3103 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3104 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3106 extern void intel_detect_pch(struct drm_device
*dev
);
3107 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3108 extern int intel_enable_rc6(const struct drm_device
*dev
);
3110 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3111 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3112 struct drm_file
*file
);
3113 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3114 struct drm_file
*file
);
3117 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3118 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3119 struct intel_overlay_error_state
*error
);
3121 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3122 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3123 struct drm_device
*dev
,
3124 struct intel_display_error_state
*error
);
3126 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3127 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3129 /* intel_sideband.c */
3130 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3131 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3132 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3133 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3134 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3135 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3136 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3137 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3138 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3139 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3140 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3141 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3142 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3143 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3144 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3145 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3146 enum intel_sbi_destination destination
);
3147 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3148 enum intel_sbi_destination destination
);
3149 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3150 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3152 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3153 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3155 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3156 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3158 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3159 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3160 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3161 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3163 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3164 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3165 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3166 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3168 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3169 * will be implemented using 2 32-bit writes in an arbitrary order with
3170 * an arbitrary delay between them. This can cause the hardware to
3171 * act upon the intermediate value, possibly leading to corruption and
3172 * machine death. You have been warned.
3174 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3175 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3177 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3178 u32 upper = I915_READ(upper_reg); \
3179 u32 lower = I915_READ(lower_reg); \
3180 u32 tmp = I915_READ(upper_reg); \
3181 if (upper != tmp) { \
3183 lower = I915_READ(lower_reg); \
3184 WARN_ON(I915_READ(upper_reg) != upper); \
3186 (u64)upper << 32 | lower; })
3188 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3189 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3191 /* "Broadcast RGB" property */
3192 #define INTEL_BROADCAST_RGB_AUTO 0
3193 #define INTEL_BROADCAST_RGB_FULL 1
3194 #define INTEL_BROADCAST_RGB_LIMITED 2
3196 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3198 if (IS_VALLEYVIEW(dev
))
3199 return VLV_VGACNTRL
;
3200 else if (INTEL_INFO(dev
)->gen
>= 5)
3201 return CPU_VGACNTRL
;
3206 static inline void __user
*to_user_ptr(u64 address
)
3208 return (void __user
*)(uintptr_t)address
;
3211 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3213 unsigned long j
= msecs_to_jiffies(m
);
3215 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3218 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3220 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3223 static inline unsigned long
3224 timespec_to_jiffies_timeout(const struct timespec
*value
)
3226 unsigned long j
= timespec_to_jiffies(value
);
3228 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3232 * If you need to wait X milliseconds between events A and B, but event B
3233 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3234 * when event A happened, then just before event B you call this function and
3235 * pass the timestamp as the first argument, and X as the second argument.
3238 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3240 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3243 * Don't re-read the value of "jiffies" every time since it may change
3244 * behind our back and break the math.
3246 tmp_jiffies
= jiffies
;
3247 target_jiffies
= timestamp_jiffies
+
3248 msecs_to_jiffies_timeout(to_wait_ms
);
3250 if (time_after(target_jiffies
, tmp_jiffies
)) {
3251 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3252 while (remaining_jiffies
)
3254 schedule_timeout_uninterruptible(remaining_jiffies
);
3258 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3259 struct drm_i915_gem_request
*req
)
3261 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3262 i915_gem_request_assign(&ring
->trace_irq_req
, req
);