1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/reservation.h>
45 #include <linux/shmem_fs.h>
48 #include <drm/intel-gtt.h>
49 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
50 #include <drm/drm_gem.h>
51 #include <drm/drm_auth.h>
52 #include <drm/drm_cache.h>
54 #include "i915_params.h"
56 #include "i915_utils.h"
58 #include "intel_uncore.h"
59 #include "intel_bios.h"
60 #include "intel_dpll_mgr.h"
62 #include "intel_lrc.h"
63 #include "intel_ringbuffer.h"
66 #include "i915_gem_context.h"
67 #include "i915_gem_fence_reg.h"
68 #include "i915_gem_object.h"
69 #include "i915_gem_gtt.h"
70 #include "i915_gem_render_state.h"
71 #include "i915_gem_request.h"
72 #include "i915_gem_timeline.h"
76 #include "intel_gvt.h"
78 /* General customization:
81 #define DRIVER_NAME "i915"
82 #define DRIVER_DESC "Intel Graphics"
83 #define DRIVER_DATE "20171012"
84 #define DRIVER_TIMESTAMP 1507831511
86 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
87 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
88 * which may not necessarily be a user visible problem. This will either
89 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
90 * enable distros and users to tailor their preferred amount of i915 abrt
93 #define I915_STATE_WARN(condition, format...) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) \
96 if (!WARN(i915_modparams.verbose_state_checks, format)) \
98 unlikely(__ret_warn_on); \
101 #define I915_STATE_WARN_ON(x) \
102 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
104 bool __i915_inject_load_failure(const char *func
, int line
);
105 #define i915_inject_load_failure() \
106 __i915_inject_load_failure(__func__, __LINE__)
110 } uint_fixed_16_16_t
;
112 #define FP_16_16_MAX ({ \
113 uint_fixed_16_16_t fp; \
118 static inline bool is_fixed16_zero(uint_fixed_16_16_t val
)
125 static inline uint_fixed_16_16_t
u32_to_fixed16(uint32_t val
)
127 uint_fixed_16_16_t fp
;
129 WARN_ON(val
> U16_MAX
);
135 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp
)
137 return DIV_ROUND_UP(fp
.val
, 1 << 16);
140 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp
)
145 static inline uint_fixed_16_16_t
min_fixed16(uint_fixed_16_16_t min1
,
146 uint_fixed_16_16_t min2
)
148 uint_fixed_16_16_t min
;
150 min
.val
= min(min1
.val
, min2
.val
);
154 static inline uint_fixed_16_16_t
max_fixed16(uint_fixed_16_16_t max1
,
155 uint_fixed_16_16_t max2
)
157 uint_fixed_16_16_t max
;
159 max
.val
= max(max1
.val
, max2
.val
);
163 static inline uint_fixed_16_16_t
clamp_u64_to_fixed16(uint64_t val
)
165 uint_fixed_16_16_t fp
;
166 WARN_ON(val
> U32_MAX
);
167 fp
.val
= (uint32_t) val
;
171 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val
,
172 uint_fixed_16_16_t d
)
174 return DIV_ROUND_UP(val
.val
, d
.val
);
177 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val
,
178 uint_fixed_16_16_t mul
)
180 uint64_t intermediate_val
;
182 intermediate_val
= (uint64_t) val
* mul
.val
;
183 intermediate_val
= DIV_ROUND_UP_ULL(intermediate_val
, 1 << 16);
184 WARN_ON(intermediate_val
> U32_MAX
);
185 return (uint32_t) intermediate_val
;
188 static inline uint_fixed_16_16_t
mul_fixed16(uint_fixed_16_16_t val
,
189 uint_fixed_16_16_t mul
)
191 uint64_t intermediate_val
;
193 intermediate_val
= (uint64_t) val
.val
* mul
.val
;
194 intermediate_val
= intermediate_val
>> 16;
195 return clamp_u64_to_fixed16(intermediate_val
);
198 static inline uint_fixed_16_16_t
div_fixed16(uint32_t val
, uint32_t d
)
202 interm_val
= (uint64_t)val
<< 16;
203 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
);
204 return clamp_u64_to_fixed16(interm_val
);
207 static inline uint32_t div_round_up_u32_fixed16(uint32_t val
,
208 uint_fixed_16_16_t d
)
212 interm_val
= (uint64_t)val
<< 16;
213 interm_val
= DIV_ROUND_UP_ULL(interm_val
, d
.val
);
214 WARN_ON(interm_val
> U32_MAX
);
215 return (uint32_t) interm_val
;
218 static inline uint_fixed_16_16_t
mul_u32_fixed16(uint32_t val
,
219 uint_fixed_16_16_t mul
)
221 uint64_t intermediate_val
;
223 intermediate_val
= (uint64_t) val
* mul
.val
;
224 return clamp_u64_to_fixed16(intermediate_val
);
227 static inline uint_fixed_16_16_t
add_fixed16(uint_fixed_16_16_t add1
,
228 uint_fixed_16_16_t add2
)
232 interm_sum
= (uint64_t) add1
.val
+ add2
.val
;
233 return clamp_u64_to_fixed16(interm_sum
);
236 static inline uint_fixed_16_16_t
add_fixed16_u32(uint_fixed_16_16_t add1
,
240 uint_fixed_16_16_t interm_add2
= u32_to_fixed16(add2
);
242 interm_sum
= (uint64_t) add1
.val
+ interm_add2
.val
;
243 return clamp_u64_to_fixed16(interm_sum
);
246 static inline const char *yesno(bool v
)
248 return v
? "yes" : "no";
251 static inline const char *onoff(bool v
)
253 return v
? "on" : "off";
256 static inline const char *enableddisabled(bool v
)
258 return v
? "enabled" : "disabled";
267 I915_MAX_PIPES
= _PIPE_EDP
269 #define pipe_name(p) ((p) + 'A')
281 static inline const char *transcoder_name(enum transcoder transcoder
)
283 switch (transcoder
) {
292 case TRANSCODER_DSI_A
:
294 case TRANSCODER_DSI_C
:
301 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
303 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
307 * Global legacy plane identifier. Valid only for primary/sprite
308 * planes on pre-g4x, and only for primary planes on g4x+.
315 #define plane_name(p) ((p) + 'A')
317 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
320 * Per-pipe plane identifier.
321 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
322 * number of planes per CRTC. Not all platforms really have this many planes,
323 * which means some arrays of size I915_MAX_PLANES may have unused entries
324 * between the topmost sprite plane and the cursor plane.
326 * This is expected to be passed to various register macros
327 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
338 #define for_each_plane_id_on_crtc(__crtc, __p) \
339 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
340 for_each_if ((__crtc)->plane_ids_mask & BIT(__p))
351 #define port_name(p) ((p) + 'A')
353 #define I915_NUM_PHYS_VLV 2
366 enum intel_display_power_domain
{
370 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
371 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
372 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
373 POWER_DOMAIN_TRANSCODER_A
,
374 POWER_DOMAIN_TRANSCODER_B
,
375 POWER_DOMAIN_TRANSCODER_C
,
376 POWER_DOMAIN_TRANSCODER_EDP
,
377 POWER_DOMAIN_TRANSCODER_DSI_A
,
378 POWER_DOMAIN_TRANSCODER_DSI_C
,
379 POWER_DOMAIN_PORT_DDI_A_LANES
,
380 POWER_DOMAIN_PORT_DDI_B_LANES
,
381 POWER_DOMAIN_PORT_DDI_C_LANES
,
382 POWER_DOMAIN_PORT_DDI_D_LANES
,
383 POWER_DOMAIN_PORT_DDI_E_LANES
,
384 POWER_DOMAIN_PORT_DDI_A_IO
,
385 POWER_DOMAIN_PORT_DDI_B_IO
,
386 POWER_DOMAIN_PORT_DDI_C_IO
,
387 POWER_DOMAIN_PORT_DDI_D_IO
,
388 POWER_DOMAIN_PORT_DDI_E_IO
,
389 POWER_DOMAIN_PORT_DSI
,
390 POWER_DOMAIN_PORT_CRT
,
391 POWER_DOMAIN_PORT_OTHER
,
400 POWER_DOMAIN_MODESET
,
406 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
407 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
408 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
409 #define POWER_DOMAIN_TRANSCODER(tran) \
410 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
411 (tran) + POWER_DOMAIN_TRANSCODER_A)
415 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
427 #define for_each_hpd_pin(__pin) \
428 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
430 #define HPD_STORM_DEFAULT_THRESHOLD 5
432 struct i915_hotplug
{
433 struct work_struct hotplug_work
;
436 unsigned long last_jiffies
;
441 HPD_MARK_DISABLED
= 2
443 } stats
[HPD_NUM_PINS
];
445 struct delayed_work reenable_work
;
447 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
450 struct work_struct dig_port_work
;
452 struct work_struct poll_init_work
;
455 unsigned int hpd_storm_threshold
;
458 * if we get a HPD irq from DP and a HPD irq from non-DP
459 * the non-DP HPD could block the workqueue on a mode config
460 * mutex getting, that userspace may have taken. However
461 * userspace is waiting on the DP workqueue to run which is
462 * blocked behind the non-DP one.
464 struct workqueue_struct
*dp_wq
;
467 #define I915_GEM_GPU_DOMAINS \
468 (I915_GEM_DOMAIN_RENDER | \
469 I915_GEM_DOMAIN_SAMPLER | \
470 I915_GEM_DOMAIN_COMMAND | \
471 I915_GEM_DOMAIN_INSTRUCTION | \
472 I915_GEM_DOMAIN_VERTEX)
474 #define for_each_pipe(__dev_priv, __p) \
475 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
476 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
477 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
478 for_each_if ((__mask) & (1 << (__p)))
479 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
481 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
483 #define for_each_sprite(__dev_priv, __p, __s) \
485 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
488 #define for_each_port_masked(__port, __ports_mask) \
489 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
490 for_each_if ((__ports_mask) & (1 << (__port)))
492 #define for_each_crtc(dev, crtc) \
493 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
495 #define for_each_intel_plane(dev, intel_plane) \
496 list_for_each_entry(intel_plane, \
497 &(dev)->mode_config.plane_list, \
500 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
501 list_for_each_entry(intel_plane, \
502 &(dev)->mode_config.plane_list, \
504 for_each_if ((plane_mask) & \
505 (1 << drm_plane_index(&intel_plane->base)))
507 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
508 list_for_each_entry(intel_plane, \
509 &(dev)->mode_config.plane_list, \
511 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
513 #define for_each_intel_crtc(dev, intel_crtc) \
514 list_for_each_entry(intel_crtc, \
515 &(dev)->mode_config.crtc_list, \
518 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
519 list_for_each_entry(intel_crtc, \
520 &(dev)->mode_config.crtc_list, \
522 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
524 #define for_each_intel_encoder(dev, intel_encoder) \
525 list_for_each_entry(intel_encoder, \
526 &(dev)->mode_config.encoder_list, \
529 #define for_each_intel_connector_iter(intel_connector, iter) \
530 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
532 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
533 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
534 for_each_if ((intel_encoder)->base.crtc == (__crtc))
536 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
537 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
538 for_each_if ((intel_connector)->base.encoder == (__encoder))
540 #define for_each_power_domain(domain, mask) \
541 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
542 for_each_if (BIT_ULL(domain) & (mask))
544 #define for_each_power_well(__dev_priv, __power_well) \
545 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
546 (__power_well) - (__dev_priv)->power_domains.power_wells < \
547 (__dev_priv)->power_domains.power_well_count; \
550 #define for_each_power_well_rev(__dev_priv, __power_well) \
551 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
552 (__dev_priv)->power_domains.power_well_count - 1; \
553 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
556 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
557 for_each_power_well(__dev_priv, __power_well) \
558 for_each_if ((__power_well)->domains & (__domain_mask))
560 #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
561 for_each_power_well_rev(__dev_priv, __power_well) \
562 for_each_if ((__power_well)->domains & (__domain_mask))
564 #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
566 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
567 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
568 (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
570 for_each_if (plane_state)
572 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
574 (__i) < (__state)->base.dev->mode_config.num_crtc && \
575 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
576 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
581 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
583 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
584 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
585 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
586 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
590 struct drm_i915_private
;
591 struct i915_mm_struct
;
592 struct i915_mmu_object
;
594 struct drm_i915_file_private
{
595 struct drm_i915_private
*dev_priv
;
596 struct drm_file
*file
;
600 struct list_head request_list
;
601 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
602 * chosen to prevent the CPU getting more than a frame ahead of the GPU
603 * (when using lax throttling for the frontbuffer). We also use it to
604 * offer free GPU waitboosts for severely congested workloads.
606 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
608 struct idr context_idr
;
610 struct intel_rps_client
{
614 unsigned int bsd_engine
;
616 /* Client can have a maximum of 3 contexts banned before
617 * it is denied of creating new contexts. As one context
618 * ban needs 4 consecutive hangs, and more if there is
619 * progress in between, this is a last resort stop gap measure
620 * to limit the badly behaving clients access to gpu.
622 #define I915_MAX_CLIENT_CONTEXT_BANS 3
623 atomic_t context_bans
;
626 /* Used by dp and fdi links */
627 struct intel_link_m_n
{
635 void intel_link_compute_m_n(int bpp
, int nlanes
,
636 int pixel_clock
, int link_clock
,
637 struct intel_link_m_n
*m_n
,
640 /* Interface history:
643 * 1.2: Add Power Management
644 * 1.3: Add vblank support
645 * 1.4: Fix cmdbuffer path, add heap destroy
646 * 1.5: Add vblank pipe configuration
647 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
648 * - Support vertical blank on secondary display pipe
650 #define DRIVER_MAJOR 1
651 #define DRIVER_MINOR 6
652 #define DRIVER_PATCHLEVEL 0
654 struct opregion_header
;
655 struct opregion_acpi
;
656 struct opregion_swsci
;
657 struct opregion_asle
;
659 struct intel_opregion
{
660 struct opregion_header
*header
;
661 struct opregion_acpi
*acpi
;
662 struct opregion_swsci
*swsci
;
663 u32 swsci_gbda_sub_functions
;
664 u32 swsci_sbcb_sub_functions
;
665 struct opregion_asle
*asle
;
671 struct work_struct asle_work
;
673 #define OPREGION_SIZE (8*1024)
675 struct intel_overlay
;
676 struct intel_overlay_error_state
;
678 struct sdvo_device_mapping
{
687 struct intel_connector
;
688 struct intel_encoder
;
689 struct intel_atomic_state
;
690 struct intel_crtc_state
;
691 struct intel_initial_plane_config
;
695 struct intel_cdclk_state
;
697 struct drm_i915_display_funcs
{
698 void (*get_cdclk
)(struct drm_i915_private
*dev_priv
,
699 struct intel_cdclk_state
*cdclk_state
);
700 void (*set_cdclk
)(struct drm_i915_private
*dev_priv
,
701 const struct intel_cdclk_state
*cdclk_state
);
702 int (*get_fifo_size
)(struct drm_i915_private
*dev_priv
, int plane
);
703 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
704 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
705 struct intel_crtc
*intel_crtc
,
706 struct intel_crtc_state
*newstate
);
707 void (*initial_watermarks
)(struct intel_atomic_state
*state
,
708 struct intel_crtc_state
*cstate
);
709 void (*atomic_update_watermarks
)(struct intel_atomic_state
*state
,
710 struct intel_crtc_state
*cstate
);
711 void (*optimize_watermarks
)(struct intel_atomic_state
*state
,
712 struct intel_crtc_state
*cstate
);
713 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
714 void (*update_wm
)(struct intel_crtc
*crtc
);
715 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
716 /* Returns the active state of the crtc, and if the crtc is active,
717 * fills out the pipe-config with the hw state. */
718 bool (*get_pipe_config
)(struct intel_crtc
*,
719 struct intel_crtc_state
*);
720 void (*get_initial_plane_config
)(struct intel_crtc
*,
721 struct intel_initial_plane_config
*);
722 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
723 struct intel_crtc_state
*crtc_state
);
724 void (*crtc_enable
)(struct intel_crtc_state
*pipe_config
,
725 struct drm_atomic_state
*old_state
);
726 void (*crtc_disable
)(struct intel_crtc_state
*old_crtc_state
,
727 struct drm_atomic_state
*old_state
);
728 void (*update_crtcs
)(struct drm_atomic_state
*state
);
729 void (*audio_codec_enable
)(struct drm_connector
*connector
,
730 struct intel_encoder
*encoder
,
731 const struct drm_display_mode
*adjusted_mode
);
732 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
733 void (*fdi_link_train
)(struct intel_crtc
*crtc
,
734 const struct intel_crtc_state
*crtc_state
);
735 void (*init_clock_gating
)(struct drm_i915_private
*dev_priv
);
736 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
737 /* clock updates for mode set */
739 /* render clock increase/decrease */
740 /* display clock increase/decrease */
741 /* pll clock increase/decrease */
743 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
744 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
747 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
748 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
749 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
752 struct work_struct work
;
754 uint32_t *dmc_payload
;
755 uint32_t dmc_fw_size
;
758 i915_reg_t mmioaddr
[8];
759 uint32_t mmiodata
[8];
761 uint32_t allowed_dc_mask
;
764 #define DEV_INFO_FOR_EACH_FLAG(func) \
767 func(is_alpha_support); \
768 /* Keep has_* in alphabetical order */ \
769 func(has_64bit_reloc); \
770 func(has_aliasing_ppgtt); \
774 func(has_reset_engine); \
776 func(has_fpga_dbg); \
777 func(has_full_ppgtt); \
778 func(has_full_48bit_ppgtt); \
779 func(has_gmch_display); \
785 func(has_logical_ring_contexts); \
786 func(has_logical_ring_preemption); \
788 func(has_pipe_cxsr); \
789 func(has_pooled_eu); \
793 func(has_resource_streamer); \
794 func(has_runtime_pm); \
796 func(unfenced_needs_alignment); \
797 func(cursor_needs_physical); \
798 func(hws_needs_physical); \
799 func(overlay_needs_physical); \
803 struct sseu_dev_info
{
809 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
812 u8 has_subslice_pg
:1;
816 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu
)
818 return hweight8(sseu
->slice_mask
) * hweight8(sseu
->subslice_mask
);
821 /* Keep in gen based order, and chronological order within a gen */
822 enum intel_platform
{
823 INTEL_PLATFORM_UNINITIALIZED
= 0,
854 struct intel_device_info
{
859 u8 gt
; /* GT number, 0 if undefined */
861 u8 ring_mask
; /* Rings supported by the HW */
863 enum intel_platform platform
;
866 u32 display_mmio_offset
;
869 u8 num_sprites
[I915_MAX_PIPES
];
870 u8 num_scalers
[I915_MAX_PIPES
];
872 unsigned int page_sizes
; /* page sizes supported by the HW */
874 #define DEFINE_FLAG(name) u8 name:1
875 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
);
877 u16 ddb_size
; /* in blocks */
879 /* Register offsets for the various display pipes and transcoders */
880 int pipe_offsets
[I915_MAX_TRANSCODERS
];
881 int trans_offsets
[I915_MAX_TRANSCODERS
];
882 int palette_offsets
[I915_MAX_PIPES
];
883 int cursor_offsets
[I915_MAX_PIPES
];
885 /* Slice/subslice/EU info */
886 struct sseu_dev_info sseu
;
889 u16 degamma_lut_size
;
894 struct intel_display_error_state
;
896 struct i915_gpu_state
{
899 struct timeval boottime
;
900 struct timeval uptime
;
902 struct drm_i915_private
*i915
;
912 struct intel_device_info device_info
;
913 struct i915_params params
;
915 /* Generic register state */
919 u32 gtier
[4], ngtier
;
923 u32 error
; /* gen6+ */
924 u32 err_int
; /* gen7 */
925 u32 fault_data0
; /* gen8, gen9 */
926 u32 fault_data1
; /* gen8, gen9 */
934 u64 fence
[I915_MAX_NUM_FENCES
];
935 struct intel_overlay_error_state
*overlay
;
936 struct intel_display_error_state
*display
;
937 struct drm_i915_error_object
*semaphore
;
938 struct drm_i915_error_object
*guc_log
;
940 struct drm_i915_error_engine
{
942 /* Software tracked state */
945 unsigned long hangcheck_timestamp
;
946 bool hangcheck_stalled
;
947 enum intel_engine_hangcheck_action hangcheck_action
;
948 struct i915_address_space
*vm
;
952 /* position of active request inside the ring */
953 u32 rq_head
, rq_post
, rq_tail
;
955 /* our own tracking of ring head and tail */
978 u32 rc_psmi
; /* sleep state */
979 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
980 struct intel_instdone instdone
;
982 struct drm_i915_error_context
{
983 char comm
[TASK_COMM_LEN
];
993 struct drm_i915_error_object
{
999 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
1001 struct drm_i915_error_object
**user_bo
;
1004 struct drm_i915_error_object
*wa_ctx
;
1006 struct drm_i915_error_request
{
1015 } *requests
, execlist
[EXECLIST_MAX_PORTS
];
1016 unsigned int num_ports
;
1018 struct drm_i915_error_waiter
{
1019 char comm
[TASK_COMM_LEN
];
1031 } engine
[I915_NUM_ENGINES
];
1033 struct drm_i915_error_buffer
{
1036 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
1040 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1047 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
1048 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
1049 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
1052 enum i915_cache_level
{
1053 I915_CACHE_NONE
= 0,
1054 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
1055 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
1056 caches, eg sampler/render caches, and the
1057 large Last-Level-Cache. LLC is coherent with
1058 the CPU, but L3 is only visible to the GPU. */
1059 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
1062 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
1073 /* This is always the inner lock when overlapping with struct_mutex and
1074 * it's the outer lock when overlapping with stolen_lock. */
1077 unsigned int possible_framebuffer_bits
;
1078 unsigned int busy_bits
;
1079 unsigned int visible_pipes_mask
;
1080 struct intel_crtc
*crtc
;
1082 struct drm_mm_node compressed_fb
;
1083 struct drm_mm_node
*compressed_llb
;
1090 bool underrun_detected
;
1091 struct work_struct underrun_work
;
1094 * Due to the atomic rules we can't access some structures without the
1095 * appropriate locking, so we cache information here in order to avoid
1098 struct intel_fbc_state_cache
{
1099 struct i915_vma
*vma
;
1102 unsigned int mode_flags
;
1103 uint32_t hsw_bdw_pixel_rate
;
1107 unsigned int rotation
;
1114 const struct drm_format_info
*format
;
1115 unsigned int stride
;
1120 * This structure contains everything that's relevant to program the
1121 * hardware registers. When we want to figure out if we need to disable
1122 * and re-enable FBC for a new configuration we just check if there's
1123 * something different in the struct. The genx_fbc_activate functions
1124 * are supposed to read from it in order to program the registers.
1126 struct intel_fbc_reg_params
{
1127 struct i915_vma
*vma
;
1132 unsigned int fence_y_offset
;
1136 const struct drm_format_info
*format
;
1137 unsigned int stride
;
1141 unsigned int gen9_wa_cfb_stride
;
1144 struct intel_fbc_work
{
1146 u32 scheduled_vblank
;
1147 struct work_struct work
;
1150 const char *no_fbc_reason
;
1154 * HIGH_RR is the highest eDP panel refresh rate read from EDID
1155 * LOW_RR is the lowest eDP panel refresh rate found from EDID
1156 * parsing for same resolution.
1158 enum drrs_refresh_rate_type
{
1161 DRRS_MAX_RR
, /* RR count */
1164 enum drrs_support_type
{
1165 DRRS_NOT_SUPPORTED
= 0,
1166 STATIC_DRRS_SUPPORT
= 1,
1167 SEAMLESS_DRRS_SUPPORT
= 2
1173 struct delayed_work work
;
1174 struct intel_dp
*dp
;
1175 unsigned busy_frontbuffer_bits
;
1176 enum drrs_refresh_rate_type refresh_rate_type
;
1177 enum drrs_support_type type
;
1184 struct intel_dp
*enabled
;
1186 struct delayed_work work
;
1187 unsigned busy_frontbuffer_bits
;
1189 bool aux_frame_sync
;
1191 bool y_cord_support
;
1192 bool colorimetry_support
;
1195 void (*enable_source
)(struct intel_dp
*,
1196 const struct intel_crtc_state
*);
1197 void (*disable_source
)(struct intel_dp
*,
1198 const struct intel_crtc_state
*);
1199 void (*enable_sink
)(struct intel_dp
*);
1200 void (*activate
)(struct intel_dp
*);
1201 void (*setup_vsc
)(struct intel_dp
*, const struct intel_crtc_state
*);
1205 PCH_NONE
= 0, /* No PCH present */
1206 PCH_IBX
, /* Ibexpeak PCH */
1207 PCH_CPT
, /* Cougarpoint/Pantherpoint PCH */
1208 PCH_LPT
, /* Lynxpoint/Wildcatpoint PCH */
1209 PCH_SPT
, /* Sunrisepoint PCH */
1210 PCH_KBP
, /* Kaby Lake PCH */
1211 PCH_CNP
, /* Cannon Lake PCH */
1215 enum intel_sbi_destination
{
1220 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1221 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1222 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1223 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1224 #define QUIRK_INCREASE_T12_DELAY (1<<6)
1227 struct intel_fbc_work
;
1229 struct intel_gmbus
{
1230 struct i2c_adapter adapter
;
1231 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1234 i915_reg_t gpio_reg
;
1235 struct i2c_algo_bit_data bit_algo
;
1236 struct drm_i915_private
*dev_priv
;
1239 struct i915_suspend_saved_registers
{
1241 u32 saveFBC_CONTROL
;
1242 u32 saveCACHE_MODE_0
;
1243 u32 saveMI_ARB_STATE
;
1247 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1248 u32 savePCH_PORT_HOTPLUG
;
1252 struct vlv_s0ix_state
{
1259 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1260 u32 media_max_req_count
;
1261 u32 gfx_max_req_count
;
1287 u32 rp_down_timeout
;
1293 /* Display 1 CZ domain */
1298 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1300 /* GT SA CZ domain */
1307 /* Display 2 CZ domain */
1311 u32 clock_gate_dis2
;
1314 struct intel_rps_ei
{
1322 * work, interrupts_enabled and pm_iir are protected by
1323 * dev_priv->irq_lock
1325 struct work_struct work
;
1326 bool interrupts_enabled
;
1329 /* PM interrupt bits that should never be masked */
1332 /* Frequencies are stored in potentially platform dependent multiples.
1333 * In other words, *_freq needs to be multiplied by X to be interesting.
1334 * Soft limits are those which are used for the dynamic reclocking done
1335 * by the driver (raise frequencies under heavy loads, and lower for
1336 * lighter loads). Hard limits are those imposed by the hardware.
1338 * A distinction is made for overclocking, which is never enabled by
1339 * default, and is considered to be above the hard limit if it's
1342 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1343 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1344 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1345 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1346 u8 min_freq
; /* AKA RPn. Minimum frequency */
1347 u8 boost_freq
; /* Frequency to request when wait boosting */
1348 u8 idle_freq
; /* Frequency to request when we are idle */
1349 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1350 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1351 u8 rp0_freq
; /* Non-overclocked max frequency. */
1352 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1354 u8 up_threshold
; /* Current %busy required to uplock */
1355 u8 down_threshold
; /* Current %busy required to downclock */
1358 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1361 atomic_t num_waiters
;
1364 /* manual wa residency calculations */
1365 struct intel_rps_ei ei
;
1372 struct intel_llc_pstate
{
1376 struct intel_gen6_power_mgmt
{
1377 struct intel_rps rps
;
1378 struct intel_rc6 rc6
;
1379 struct intel_llc_pstate llc_pstate
;
1380 struct delayed_work autoenable_work
;
1383 /* defined intel_pm.c */
1384 extern spinlock_t mchdev_lock
;
1386 struct intel_ilk_power_mgmt
{
1394 unsigned long last_time1
;
1395 unsigned long chipset_power
;
1398 unsigned long gfx_power
;
1405 struct drm_i915_private
;
1406 struct i915_power_well
;
1408 struct i915_power_well_ops
{
1410 * Synchronize the well's hw state to match the current sw state, for
1411 * example enable/disable it based on the current refcount. Called
1412 * during driver init and resume time, possibly after first calling
1413 * the enable/disable handlers.
1415 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1416 struct i915_power_well
*power_well
);
1418 * Enable the well and resources that depend on it (for example
1419 * interrupts located on the well). Called after the 0->1 refcount
1422 void (*enable
)(struct drm_i915_private
*dev_priv
,
1423 struct i915_power_well
*power_well
);
1425 * Disable the well and resources that depend on it. Called after
1426 * the 1->0 refcount transition.
1428 void (*disable
)(struct drm_i915_private
*dev_priv
,
1429 struct i915_power_well
*power_well
);
1430 /* Returns the hw enabled state. */
1431 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1432 struct i915_power_well
*power_well
);
1435 /* Power well structure for haswell */
1436 struct i915_power_well
{
1439 /* power well enable/disable usage count */
1441 /* cached hw enabled state */
1444 /* unique identifier for this power well */
1445 enum i915_power_well_id id
;
1447 * Arbitraty data associated with this power well. Platform and power
1455 /* Mask of pipes whose IRQ logic is backed by the pw */
1457 /* The pw is backing the VGA functionality */
1462 const struct i915_power_well_ops
*ops
;
1465 struct i915_power_domains
{
1467 * Power wells needed for initialization at driver init and suspend
1468 * time are on. They are kept on until after the first modeset.
1472 int power_well_count
;
1475 int domain_use_count
[POWER_DOMAIN_NUM
];
1476 struct i915_power_well
*power_wells
;
1479 #define MAX_L3_SLICES 2
1480 struct intel_l3_parity
{
1481 u32
*remap_info
[MAX_L3_SLICES
];
1482 struct work_struct error_work
;
1486 struct i915_gem_mm
{
1487 /** Memory allocator for GTT stolen memory */
1488 struct drm_mm stolen
;
1489 /** Protects the usage of the GTT stolen memory allocator. This is
1490 * always the inner lock when overlapping with struct_mutex. */
1491 struct mutex stolen_lock
;
1493 /** List of all objects in gtt_space. Used to restore gtt
1494 * mappings on resume */
1495 struct list_head bound_list
;
1497 * List of objects which are not bound to the GTT (thus
1498 * are idle and not used by the GPU). These objects may or may
1499 * not actually have any pages attached.
1501 struct list_head unbound_list
;
1503 /** List of all objects in gtt_space, currently mmaped by userspace.
1504 * All objects within this list must also be on bound_list.
1506 struct list_head userfault_list
;
1509 * List of objects which are pending destruction.
1511 struct llist_head free_list
;
1512 struct work_struct free_work
;
1515 * Small stash of WC pages
1517 struct pagevec wc_stash
;
1519 /** Usable portion of the GTT for GEM */
1520 dma_addr_t stolen_base
; /* limited to low memory (32-bit) */
1523 * tmpfs instance used for shmem backed objects
1525 struct vfsmount
*gemfs
;
1527 /** PPGTT used for aliasing the PPGTT with the GTT */
1528 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1530 struct notifier_block oom_notifier
;
1531 struct notifier_block vmap_notifier
;
1532 struct shrinker shrinker
;
1534 /** LRU list of objects with fence regs on them. */
1535 struct list_head fence_list
;
1538 * Workqueue to fault in userptr pages, flushed by the execbuf
1539 * when required but otherwise left to userspace to try again
1542 struct workqueue_struct
*userptr_wq
;
1544 u64 unordered_timeline
;
1546 /* the indicator for dispatch video commands on two BSD rings */
1547 atomic_t bsd_engine_dispatch_index
;
1549 /** Bit 6 swizzling required for X tiling */
1550 uint32_t bit_6_swizzle_x
;
1551 /** Bit 6 swizzling required for Y tiling */
1552 uint32_t bit_6_swizzle_y
;
1554 /* accounting, useful for userland debugging */
1555 spinlock_t object_stat_lock
;
1560 struct drm_i915_error_state_buf
{
1561 struct drm_i915_private
*i915
;
1570 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1571 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1573 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1574 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1576 struct i915_gpu_error
{
1577 /* For hangcheck timer */
1578 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1579 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1581 struct delayed_work hangcheck_work
;
1583 /* For reset and error_state handling. */
1585 /* Protected by the above dev->gpu_error.lock. */
1586 struct i915_gpu_state
*first_error
;
1588 atomic_t pending_fb_pin
;
1590 unsigned long missed_irq_rings
;
1593 * State variable controlling the reset flow and count
1595 * This is a counter which gets incremented when reset is triggered,
1597 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1598 * meaning that any waiters holding onto the struct_mutex should
1599 * relinquish the lock immediately in order for the reset to start.
1601 * If reset is not completed succesfully, the I915_WEDGE bit is
1602 * set meaning that hardware is terminally sour and there is no
1603 * recovery. All waiters on the reset_queue will be woken when
1606 * This counter is used by the wait_seqno code to notice that reset
1607 * event happened and it needs to restart the entire ioctl (since most
1608 * likely the seqno it waited for won't ever signal anytime soon).
1610 * This is important for lock-free wait paths, where no contended lock
1611 * naturally enforces the correct ordering between the bail-out of the
1612 * waiter and the gpu reset work code.
1614 unsigned long reset_count
;
1617 * flags: Control various stages of the GPU reset
1619 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1620 * other users acquiring the struct_mutex. To do this we set the
1621 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1622 * and then check for that bit before acquiring the struct_mutex (in
1623 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1624 * secondary role in preventing two concurrent global reset attempts.
1626 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1627 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1628 * but it may be held by some long running waiter (that we cannot
1629 * interrupt without causing trouble). Once we are ready to do the GPU
1630 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1631 * they already hold the struct_mutex and want to participate they can
1632 * inspect the bit and do the reset directly, otherwise the worker
1633 * waits for the struct_mutex.
1635 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1636 * acquire the struct_mutex to reset an engine, we need an explicit
1637 * flag to prevent two concurrent reset attempts in the same engine.
1638 * As the number of engines continues to grow, allocate the flags from
1639 * the most significant bits.
1641 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1642 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1643 * i915_gem_request_alloc(), this bit is checked and the sequence
1644 * aborted (with -EIO reported to userspace) if set.
1646 unsigned long flags
;
1647 #define I915_RESET_BACKOFF 0
1648 #define I915_RESET_HANDOFF 1
1649 #define I915_RESET_MODESET 2
1650 #define I915_WEDGED (BITS_PER_LONG - 1)
1651 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1653 /** Number of times an engine has been reset */
1654 u32 reset_engine_count
[I915_NUM_ENGINES
];
1657 * Waitqueue to signal when a hang is detected. Used to for waiters
1658 * to release the struct_mutex for the reset to procede.
1660 wait_queue_head_t wait_queue
;
1663 * Waitqueue to signal when the reset has completed. Used by clients
1664 * that wait for dev_priv->mm.wedged to settle.
1666 wait_queue_head_t reset_queue
;
1668 /* For missed irq/seqno simulation. */
1669 unsigned long test_irq_rings
;
1672 enum modeset_restore
{
1673 MODESET_ON_LID_OPEN
,
1678 #define DP_AUX_A 0x40
1679 #define DP_AUX_B 0x10
1680 #define DP_AUX_C 0x20
1681 #define DP_AUX_D 0x30
1683 #define DDC_PIN_B 0x05
1684 #define DDC_PIN_C 0x04
1685 #define DDC_PIN_D 0x06
1687 struct ddi_vbt_port_info
{
1689 * This is an index in the HDMI/DVI DDI buffer translation table.
1690 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1691 * populate this field.
1693 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1694 uint8_t hdmi_level_shift
;
1696 uint8_t supports_dvi
:1;
1697 uint8_t supports_hdmi
:1;
1698 uint8_t supports_dp
:1;
1699 uint8_t supports_edp
:1;
1701 uint8_t alternate_aux_channel
;
1702 uint8_t alternate_ddc_pin
;
1704 uint8_t dp_boost_level
;
1705 uint8_t hdmi_boost_level
;
1708 enum psr_lines_to_wait
{
1709 PSR_0_LINES_TO_WAIT
= 0,
1711 PSR_4_LINES_TO_WAIT
,
1715 struct intel_vbt_data
{
1716 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1717 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1720 unsigned int int_tv_support
:1;
1721 unsigned int lvds_dither
:1;
1722 unsigned int lvds_vbt
:1;
1723 unsigned int int_crt_support
:1;
1724 unsigned int lvds_use_ssc
:1;
1725 unsigned int display_clock_mode
:1;
1726 unsigned int fdi_rx_polarity_inverted
:1;
1727 unsigned int panel_type
:4;
1729 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1731 enum drrs_support_type drrs_type
;
1742 struct edp_power_seq pps
;
1747 bool require_aux_wakeup
;
1749 enum psr_lines_to_wait lines_to_wait
;
1750 int tp1_wakeup_time
;
1751 int tp2_tp3_wakeup_time
;
1757 bool active_low_pwm
;
1758 u8 min_brightness
; /* min_brightness/255 of max */
1759 u8 controller
; /* brightness controller number */
1760 enum intel_backlight_type type
;
1766 struct mipi_config
*config
;
1767 struct mipi_pps_data
*pps
;
1771 const u8
*sequence
[MIPI_SEQ_MAX
];
1777 struct child_device_config
*child_dev
;
1779 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1780 struct sdvo_device_mapping sdvo_mappings
[2];
1783 enum intel_ddb_partitioning
{
1785 INTEL_DDB_PART_5_6
, /* IVB+ */
1788 struct intel_wm_level
{
1796 struct ilk_wm_values
{
1797 uint32_t wm_pipe
[3];
1799 uint32_t wm_lp_spr
[3];
1800 uint32_t wm_linetime
[3];
1802 enum intel_ddb_partitioning partitioning
;
1805 struct g4x_pipe_wm
{
1806 uint16_t plane
[I915_MAX_PLANES
];
1816 struct vlv_wm_ddl_values
{
1817 uint8_t plane
[I915_MAX_PLANES
];
1820 struct vlv_wm_values
{
1821 struct g4x_pipe_wm pipe
[3];
1822 struct g4x_sr_wm sr
;
1823 struct vlv_wm_ddl_values ddl
[3];
1828 struct g4x_wm_values
{
1829 struct g4x_pipe_wm pipe
[2];
1830 struct g4x_sr_wm sr
;
1831 struct g4x_sr_wm hpll
;
1837 struct skl_ddb_entry
{
1838 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1841 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1843 return entry
->end
- entry
->start
;
1846 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1847 const struct skl_ddb_entry
*e2
)
1849 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1855 struct skl_ddb_allocation
{
1856 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1857 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1860 struct skl_wm_values
{
1861 unsigned dirty_pipes
;
1862 struct skl_ddb_allocation ddb
;
1865 struct skl_wm_level
{
1867 uint16_t plane_res_b
;
1868 uint8_t plane_res_l
;
1871 /* Stores plane specific WM parameters */
1872 struct skl_wm_params
{
1873 bool x_tiled
, y_tiled
;
1877 uint32_t plane_pixel_rate
;
1878 uint32_t y_min_scanlines
;
1879 uint32_t plane_bytes_per_line
;
1880 uint_fixed_16_16_t plane_blocks_per_line
;
1881 uint_fixed_16_16_t y_tile_minimum
;
1882 uint32_t linetime_us
;
1886 * This struct helps tracking the state needed for runtime PM, which puts the
1887 * device in PCI D3 state. Notice that when this happens, nothing on the
1888 * graphics device works, even register access, so we don't get interrupts nor
1891 * Every piece of our code that needs to actually touch the hardware needs to
1892 * either call intel_runtime_pm_get or call intel_display_power_get with the
1893 * appropriate power domain.
1895 * Our driver uses the autosuspend delay feature, which means we'll only really
1896 * suspend if we stay with zero refcount for a certain amount of time. The
1897 * default value is currently very conservative (see intel_runtime_pm_enable), but
1898 * it can be changed with the standard runtime PM files from sysfs.
1900 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1901 * goes back to false exactly before we reenable the IRQs. We use this variable
1902 * to check if someone is trying to enable/disable IRQs while they're supposed
1903 * to be disabled. This shouldn't happen and we'll print some error messages in
1906 * For more, read the Documentation/power/runtime_pm.txt.
1908 struct i915_runtime_pm
{
1909 atomic_t wakeref_count
;
1914 enum intel_pipe_crc_source
{
1915 INTEL_PIPE_CRC_SOURCE_NONE
,
1916 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1917 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1918 INTEL_PIPE_CRC_SOURCE_PF
,
1919 INTEL_PIPE_CRC_SOURCE_PIPE
,
1920 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1921 INTEL_PIPE_CRC_SOURCE_TV
,
1922 INTEL_PIPE_CRC_SOURCE_DP_B
,
1923 INTEL_PIPE_CRC_SOURCE_DP_C
,
1924 INTEL_PIPE_CRC_SOURCE_DP_D
,
1925 INTEL_PIPE_CRC_SOURCE_AUTO
,
1926 INTEL_PIPE_CRC_SOURCE_MAX
,
1929 struct intel_pipe_crc_entry
{
1934 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1935 struct intel_pipe_crc
{
1937 bool opened
; /* exclusive access to the result file */
1938 struct intel_pipe_crc_entry
*entries
;
1939 enum intel_pipe_crc_source source
;
1941 wait_queue_head_t wq
;
1945 struct i915_frontbuffer_tracking
{
1949 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1956 struct i915_wa_reg
{
1959 /* bitmask representing WA bits */
1964 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1965 * allowing it for RCS as we don't foresee any requirement of having
1966 * a whitelist for other engines. When it is really required for
1967 * other engines then the limit need to be increased.
1969 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1971 struct i915_workarounds
{
1972 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1974 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1977 struct i915_virtual_gpu
{
1982 /* used in computing the new watermarks state */
1983 struct intel_wm_config
{
1984 unsigned int num_pipes_active
;
1985 bool sprites_enabled
;
1986 bool sprites_scaled
;
1989 struct i915_oa_format
{
1994 struct i915_oa_reg
{
1999 struct i915_oa_config
{
2000 char uuid
[UUID_STRING_LEN
+ 1];
2003 const struct i915_oa_reg
*mux_regs
;
2005 const struct i915_oa_reg
*b_counter_regs
;
2006 u32 b_counter_regs_len
;
2007 const struct i915_oa_reg
*flex_regs
;
2010 struct attribute_group sysfs_metric
;
2011 struct attribute
*attrs
[2];
2012 struct device_attribute sysfs_metric_id
;
2017 struct i915_perf_stream
;
2020 * struct i915_perf_stream_ops - the OPs to support a specific stream type
2022 struct i915_perf_stream_ops
{
2024 * @enable: Enables the collection of HW samples, either in response to
2025 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
2026 * without `I915_PERF_FLAG_DISABLED`.
2028 void (*enable
)(struct i915_perf_stream
*stream
);
2031 * @disable: Disables the collection of HW samples, either in response
2032 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
2035 void (*disable
)(struct i915_perf_stream
*stream
);
2038 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
2039 * once there is something ready to read() for the stream
2041 void (*poll_wait
)(struct i915_perf_stream
*stream
,
2046 * @wait_unlocked: For handling a blocking read, wait until there is
2047 * something to ready to read() for the stream. E.g. wait on the same
2048 * wait queue that would be passed to poll_wait().
2050 int (*wait_unlocked
)(struct i915_perf_stream
*stream
);
2053 * @read: Copy buffered metrics as records to userspace
2054 * **buf**: the userspace, destination buffer
2055 * **count**: the number of bytes to copy, requested by userspace
2056 * **offset**: zero at the start of the read, updated as the read
2057 * proceeds, it represents how many bytes have been copied so far and
2058 * the buffer offset for copying the next record.
2060 * Copy as many buffered i915 perf samples and records for this stream
2061 * to userspace as will fit in the given buffer.
2063 * Only write complete records; returning -%ENOSPC if there isn't room
2064 * for a complete record.
2066 * Return any error condition that results in a short read such as
2067 * -%ENOSPC or -%EFAULT, even though these may be squashed before
2068 * returning to userspace.
2070 int (*read
)(struct i915_perf_stream
*stream
,
2076 * @destroy: Cleanup any stream specific resources.
2078 * The stream will always be disabled before this is called.
2080 void (*destroy
)(struct i915_perf_stream
*stream
);
2084 * struct i915_perf_stream - state for a single open stream FD
2086 struct i915_perf_stream
{
2088 * @dev_priv: i915 drm device
2090 struct drm_i915_private
*dev_priv
;
2093 * @link: Links the stream into ``&drm_i915_private->streams``
2095 struct list_head link
;
2098 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
2099 * properties given when opening a stream, representing the contents
2100 * of a single sample as read() by userspace.
2105 * @sample_size: Considering the configured contents of a sample
2106 * combined with the required header size, this is the total size
2107 * of a single sample record.
2112 * @ctx: %NULL if measuring system-wide across all contexts or a
2113 * specific context that is being monitored.
2115 struct i915_gem_context
*ctx
;
2118 * @enabled: Whether the stream is currently enabled, considering
2119 * whether the stream was opened in a disabled state and based
2120 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
2125 * @ops: The callbacks providing the implementation of this specific
2126 * type of configured stream.
2128 const struct i915_perf_stream_ops
*ops
;
2131 * @oa_config: The OA configuration used by the stream.
2133 struct i915_oa_config
*oa_config
;
2137 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
2139 struct i915_oa_ops
{
2141 * @is_valid_b_counter_reg: Validates register's address for
2142 * programming boolean counters for a particular platform.
2144 bool (*is_valid_b_counter_reg
)(struct drm_i915_private
*dev_priv
,
2148 * @is_valid_mux_reg: Validates register's address for programming mux
2149 * for a particular platform.
2151 bool (*is_valid_mux_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
2154 * @is_valid_flex_reg: Validates register's address for programming
2155 * flex EU filtering for a particular platform.
2157 bool (*is_valid_flex_reg
)(struct drm_i915_private
*dev_priv
, u32 addr
);
2160 * @init_oa_buffer: Resets the head and tail pointers of the
2161 * circular buffer for periodic OA reports.
2163 * Called when first opening a stream for OA metrics, but also may be
2164 * called in response to an OA buffer overflow or other error
2167 * Note it may be necessary to clear the full OA buffer here as part of
2168 * maintaining the invariable that new reports must be written to
2169 * zeroed memory for us to be able to reliable detect if an expected
2170 * report has not yet landed in memory. (At least on Haswell the OA
2171 * buffer tail pointer is not synchronized with reports being visible
2174 void (*init_oa_buffer
)(struct drm_i915_private
*dev_priv
);
2177 * @enable_metric_set: Selects and applies any MUX configuration to set
2178 * up the Boolean and Custom (B/C) counters that are part of the
2179 * counter reports being sampled. May apply system constraints such as
2180 * disabling EU clock gating as required.
2182 int (*enable_metric_set
)(struct drm_i915_private
*dev_priv
,
2183 const struct i915_oa_config
*oa_config
);
2186 * @disable_metric_set: Remove system constraints associated with using
2189 void (*disable_metric_set
)(struct drm_i915_private
*dev_priv
);
2192 * @oa_enable: Enable periodic sampling
2194 void (*oa_enable
)(struct drm_i915_private
*dev_priv
);
2197 * @oa_disable: Disable periodic sampling
2199 void (*oa_disable
)(struct drm_i915_private
*dev_priv
);
2202 * @read: Copy data from the circular OA buffer into a given userspace
2205 int (*read
)(struct i915_perf_stream
*stream
,
2211 * @oa_hw_tail_read: read the OA tail pointer register
2213 * In particular this enables us to share all the fiddly code for
2214 * handling the OA unit tail pointer race that affects multiple
2217 u32 (*oa_hw_tail_read
)(struct drm_i915_private
*dev_priv
);
2220 struct intel_cdclk_state
{
2221 unsigned int cdclk
, vco
, ref
;
2224 struct drm_i915_private
{
2225 struct drm_device drm
;
2227 struct kmem_cache
*objects
;
2228 struct kmem_cache
*vmas
;
2229 struct kmem_cache
*luts
;
2230 struct kmem_cache
*requests
;
2231 struct kmem_cache
*dependencies
;
2232 struct kmem_cache
*priorities
;
2234 const struct intel_device_info info
;
2238 struct intel_uncore uncore
;
2240 struct i915_virtual_gpu vgpu
;
2242 struct intel_gvt
*gvt
;
2244 struct intel_huc huc
;
2245 struct intel_guc guc
;
2247 struct intel_csr csr
;
2249 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
2251 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
2252 * controller on different i2c buses. */
2253 struct mutex gmbus_mutex
;
2256 * Base address of the gmbus and gpio block.
2258 uint32_t gpio_mmio_base
;
2260 /* MMIO base address for MIPI regs */
2261 uint32_t mipi_mmio_base
;
2263 uint32_t psr_mmio_base
;
2265 uint32_t pps_mmio_base
;
2267 wait_queue_head_t gmbus_wait_queue
;
2269 struct pci_dev
*bridge_dev
;
2270 struct intel_engine_cs
*engine
[I915_NUM_ENGINES
];
2271 /* Context used internally to idle the GPU and setup initial state */
2272 struct i915_gem_context
*kernel_context
;
2273 /* Context only to be used for injecting preemption commands */
2274 struct i915_gem_context
*preempt_context
;
2275 struct i915_vma
*semaphore
;
2277 struct drm_dma_handle
*status_page_dmah
;
2278 struct resource mch_res
;
2280 /* protects the irq masks */
2281 spinlock_t irq_lock
;
2283 bool display_irqs_enabled
;
2285 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
2286 struct pm_qos_request pm_qos
;
2288 /* Sideband mailbox protection */
2289 struct mutex sb_lock
;
2291 /** Cached value of IMR to avoid reads in updating the bitfield */
2294 u32 de_irq_mask
[I915_MAX_PIPES
];
2301 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
2303 struct i915_hotplug hotplug
;
2304 struct intel_fbc fbc
;
2305 struct i915_drrs drrs
;
2306 struct intel_opregion opregion
;
2307 struct intel_vbt_data vbt
;
2309 bool preserve_bios_swizzle
;
2312 struct intel_overlay
*overlay
;
2314 /* backlight registers and fields in struct intel_panel */
2315 struct mutex backlight_lock
;
2318 bool no_aux_handshake
;
2320 /* protects panel power sequencer state */
2321 struct mutex pps_mutex
;
2323 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
2324 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
2326 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
2327 unsigned int skl_preferred_vco_freq
;
2328 unsigned int max_cdclk_freq
;
2330 unsigned int max_dotclk_freq
;
2331 unsigned int rawclk_freq
;
2332 unsigned int hpll_freq
;
2333 unsigned int czclk_freq
;
2337 * The current logical cdclk state.
2338 * See intel_atomic_state.cdclk.logical
2340 * For reading holding any crtc lock is sufficient,
2341 * for writing must hold all of them.
2343 struct intel_cdclk_state logical
;
2345 * The current actual cdclk state.
2346 * See intel_atomic_state.cdclk.actual
2348 struct intel_cdclk_state actual
;
2349 /* The current hardware cdclk state */
2350 struct intel_cdclk_state hw
;
2354 * wq - Driver workqueue for GEM.
2356 * NOTE: Work items scheduled here are not allowed to grab any modeset
2357 * locks, for otherwise the flushing done in the pageflip code will
2358 * result in deadlocks.
2360 struct workqueue_struct
*wq
;
2362 /* Display functions */
2363 struct drm_i915_display_funcs display
;
2365 /* PCH chipset type */
2366 enum intel_pch pch_type
;
2367 unsigned short pch_id
;
2369 unsigned long quirks
;
2371 enum modeset_restore modeset_restore
;
2372 struct mutex modeset_restore_lock
;
2373 struct drm_atomic_state
*modeset_restore_state
;
2374 struct drm_modeset_acquire_ctx reset_ctx
;
2376 struct list_head vm_list
; /* Global list of all address spaces */
2377 struct i915_ggtt ggtt
; /* VM representing the global address space */
2379 struct i915_gem_mm mm
;
2380 DECLARE_HASHTABLE(mm_structs
, 7);
2381 struct mutex mm_lock
;
2383 struct intel_ppat ppat
;
2385 /* Kernel Modesetting */
2387 struct intel_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
2388 struct intel_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
2390 #ifdef CONFIG_DEBUG_FS
2391 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
2394 /* dpll and cdclk state is protected by connection_mutex */
2395 int num_shared_dpll
;
2396 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
2397 const struct intel_dpll_mgr
*dpll_mgr
;
2400 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2401 * Must be global rather than per dpll, because on some platforms
2402 * plls share registers.
2404 struct mutex dpll_lock
;
2406 unsigned int active_crtcs
;
2407 /* minimum acceptable cdclk for each pipe */
2408 int min_cdclk
[I915_MAX_PIPES
];
2410 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
2412 struct i915_workarounds workarounds
;
2414 struct i915_frontbuffer_tracking fb_tracking
;
2416 struct intel_atomic_helper
{
2417 struct llist_head free_list
;
2418 struct work_struct free_work
;
2423 bool mchbar_need_disable
;
2425 struct intel_l3_parity l3_parity
;
2427 /* Cannot be determined by PCIID. You must always read a register. */
2431 * Protects RPS/RC6 register access and PCU communication.
2432 * Must be taken after struct_mutex if nested. Note that
2433 * this lock may be held for long periods of time when
2434 * talking to hw - so only take it when talking to hw!
2436 struct mutex pcu_lock
;
2438 /* gen6+ GT PM state */
2439 struct intel_gen6_power_mgmt gt_pm
;
2441 /* ilk-only ips/rps state. Everything in here is protected by the global
2442 * mchdev_lock in intel_pm.c */
2443 struct intel_ilk_power_mgmt ips
;
2445 struct i915_power_domains power_domains
;
2447 struct i915_psr psr
;
2449 struct i915_gpu_error gpu_error
;
2451 struct drm_i915_gem_object
*vlv_pctx
;
2453 /* list of fbdev register on this device */
2454 struct intel_fbdev
*fbdev
;
2455 struct work_struct fbdev_suspend_work
;
2457 struct drm_property
*broadcast_rgb_property
;
2458 struct drm_property
*force_audio_property
;
2460 /* hda/i915 audio component */
2461 struct i915_audio_component
*audio_component
;
2462 bool audio_component_registered
;
2464 * av_mutex - mutex for audio/video sync
2467 struct mutex av_mutex
;
2470 struct list_head list
;
2471 struct llist_head free_list
;
2472 struct work_struct free_work
;
2474 /* The hw wants to have a stable context identifier for the
2475 * lifetime of the context (for OA, PASID, faults, etc).
2476 * This is limited in execlists to 21 bits.
2479 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2484 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2485 u32 chv_phy_control
;
2487 * Shadows for CHV DPLL_MD regs to keep the state
2488 * checker somewhat working in the presence hardware
2489 * crappiness (can't read out DPLL_MD for pipes B & C).
2491 u32 chv_dpll_md
[I915_MAX_PIPES
];
2495 bool suspended_to_idle
;
2496 struct i915_suspend_saved_registers regfile
;
2497 struct vlv_s0ix_state vlv_s0ix_state
;
2500 I915_SAGV_UNKNOWN
= 0,
2503 I915_SAGV_NOT_CONTROLLED
2508 * Raw watermark latency values:
2509 * in 0.1us units for WM0,
2510 * in 0.5us units for WM1+.
2513 uint16_t pri_latency
[5];
2515 uint16_t spr_latency
[5];
2517 uint16_t cur_latency
[5];
2519 * Raw watermark memory latency values
2520 * for SKL for all 8 levels
2523 uint16_t skl_latency
[8];
2525 /* current hardware state */
2527 struct ilk_wm_values hw
;
2528 struct skl_wm_values skl_hw
;
2529 struct vlv_wm_values vlv
;
2530 struct g4x_wm_values g4x
;
2536 * Should be held around atomic WM register writing; also
2537 * protects * intel_crtc->wm.active and
2538 * cstate->wm.need_postvbl_update.
2540 struct mutex wm_mutex
;
2543 * Set during HW readout of watermarks/DDB. Some platforms
2544 * need to know when we're still using BIOS-provided values
2545 * (which we don't fully trust).
2547 bool distrust_bios_wm
;
2550 struct i915_runtime_pm runtime_pm
;
2555 struct kobject
*metrics_kobj
;
2556 struct ctl_table_header
*sysctl_header
;
2559 * Lock associated with adding/modifying/removing OA configs
2560 * in dev_priv->perf.metrics_idr.
2562 struct mutex metrics_lock
;
2565 * List of dynamic configurations, you need to hold
2566 * dev_priv->perf.metrics_lock to access it.
2568 struct idr metrics_idr
;
2571 * Lock associated with anything below within this structure
2572 * except exclusive_stream.
2575 struct list_head streams
;
2579 * The stream currently using the OA unit. If accessed
2580 * outside a syscall associated to its file
2581 * descriptor, you need to hold
2582 * dev_priv->drm.struct_mutex.
2584 struct i915_perf_stream
*exclusive_stream
;
2586 u32 specific_ctx_id
;
2588 struct hrtimer poll_check_timer
;
2589 wait_queue_head_t poll_wq
;
2593 * For rate limiting any notifications of spurious
2594 * invalid OA reports
2596 struct ratelimit_state spurious_report_rs
;
2599 int period_exponent
;
2600 int timestamp_frequency
;
2602 struct i915_oa_config test_config
;
2605 struct i915_vma
*vma
;
2612 * Locks reads and writes to all head/tail state
2614 * Consider: the head and tail pointer state
2615 * needs to be read consistently from a hrtimer
2616 * callback (atomic context) and read() fop
2617 * (user context) with tail pointer updates
2618 * happening in atomic context and head updates
2619 * in user context and the (unlikely)
2620 * possibility of read() errors needing to
2621 * reset all head/tail state.
2623 * Note: Contention or performance aren't
2624 * currently a significant concern here
2625 * considering the relatively low frequency of
2626 * hrtimer callbacks (5ms period) and that
2627 * reads typically only happen in response to a
2628 * hrtimer event and likely complete before the
2631 * Note: This lock is not held *while* reading
2632 * and copying data to userspace so the value
2633 * of head observed in htrimer callbacks won't
2634 * represent any partial consumption of data.
2636 spinlock_t ptr_lock
;
2639 * One 'aging' tail pointer and one 'aged'
2640 * tail pointer ready to used for reading.
2642 * Initial values of 0xffffffff are invalid
2643 * and imply that an update is required
2644 * (and should be ignored by an attempted
2652 * Index for the aged tail ready to read()
2655 unsigned int aged_tail_idx
;
2658 * A monotonic timestamp for when the current
2659 * aging tail pointer was read; used to
2660 * determine when it is old enough to trust.
2662 u64 aging_timestamp
;
2665 * Although we can always read back the head
2666 * pointer register, we prefer to avoid
2667 * trusting the HW state, just to avoid any
2668 * risk that some hardware condition could
2669 * somehow bump the head pointer unpredictably
2670 * and cause us to forward the wrong OA buffer
2671 * data to userspace.
2676 u32 gen7_latched_oastatus1
;
2677 u32 ctx_oactxctrl_offset
;
2678 u32 ctx_flexeu0_offset
;
2681 * The RPT_ID/reason field for Gen8+ includes a bit
2682 * to determine if the CTX ID in the report is valid
2683 * but the specific bit differs between Gen 8 and 9
2685 u32 gen8_valid_ctx_bit
;
2687 struct i915_oa_ops ops
;
2688 const struct i915_oa_format
*oa_formats
;
2692 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2694 void (*resume
)(struct drm_i915_private
*);
2695 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2697 struct list_head timelines
;
2698 struct i915_gem_timeline global_timeline
;
2699 u32 active_requests
;
2702 * Is the GPU currently considered idle, or busy executing
2703 * userspace requests? Whilst idle, we allow runtime power
2704 * management to power down the hardware and display clocks.
2705 * In order to reduce the effect on performance, there
2706 * is a slight delay before we do so.
2711 * We leave the user IRQ off as much as possible,
2712 * but this means that requests will finish and never
2713 * be retired once the system goes idle. Set a timer to
2714 * fire periodically while the ring is running. When it
2715 * fires, go retire requests.
2717 struct delayed_work retire_work
;
2720 * When we detect an idle GPU, we want to turn on
2721 * powersaving features. So once we see that there
2722 * are no more requests outstanding and no more
2723 * arrive within a small period of time, we fire
2724 * off the idle_work.
2726 struct delayed_work idle_work
;
2728 ktime_t last_init_time
;
2731 /* perform PHY state sanity checks? */
2732 bool chv_phy_assert
[2];
2736 /* Used to save the pipe-to-encoder mapping for audio */
2737 struct intel_encoder
*av_enc_map
[I915_MAX_PIPES
];
2739 /* necessary resource sharing with HDMI LPE audio driver. */
2741 struct platform_device
*platdev
;
2746 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2747 * will be rejected. Instead look for a better place.
2751 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2753 return container_of(dev
, struct drm_i915_private
, drm
);
2756 static inline struct drm_i915_private
*kdev_to_i915(struct device
*kdev
)
2758 return to_i915(dev_get_drvdata(kdev
));
2761 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2763 return container_of(guc
, struct drm_i915_private
, guc
);
2766 static inline struct drm_i915_private
*huc_to_i915(struct intel_huc
*huc
)
2768 return container_of(huc
, struct drm_i915_private
, huc
);
2771 /* Simple iterator over all initialised engines */
2772 #define for_each_engine(engine__, dev_priv__, id__) \
2774 (id__) < I915_NUM_ENGINES; \
2776 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2778 /* Iterator over subset of engines selected by mask */
2779 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2780 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2781 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2783 enum hdmi_force_audio
{
2784 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2785 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2786 HDMI_AUDIO_AUTO
, /* trust EDID */
2787 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2790 #define I915_GTT_OFFSET_NONE ((u32)-1)
2793 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2794 * considered to be the frontbuffer for the given plane interface-wise. This
2795 * doesn't mean that the hw necessarily already scans it out, but that any
2796 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2798 * We have one bit per pipe and per scanout plane type.
2800 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2801 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2802 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2803 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2804 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2805 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2806 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2807 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2808 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2809 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2810 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2811 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2814 * Optimised SGL iterator for GEM objects
2816 static __always_inline
struct sgt_iter
{
2817 struct scatterlist
*sgp
;
2824 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2825 struct sgt_iter s
= { .sgp
= sgl
};
2828 s
.max
= s
.curr
= s
.sgp
->offset
;
2829 s
.max
+= s
.sgp
->length
;
2831 s
.dma
= sg_dma_address(s
.sgp
);
2833 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2839 static inline struct scatterlist
*____sg_next(struct scatterlist
*sg
)
2842 if (unlikely(sg_is_chain(sg
)))
2843 sg
= sg_chain_ptr(sg
);
2848 * __sg_next - return the next scatterlist entry in a list
2849 * @sg: The current sg entry
2852 * If the entry is the last, return NULL; otherwise, step to the next
2853 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2854 * otherwise just return the pointer to the current element.
2856 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2858 #ifdef CONFIG_DEBUG_SG
2859 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2861 return sg_is_last(sg
) ? NULL
: ____sg_next(sg
);
2865 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2866 * @__dmap: DMA address (output)
2867 * @__iter: 'struct sgt_iter' (iterator state, internal)
2868 * @__sgt: sg_table to iterate over (input)
2870 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2871 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2872 ((__dmap) = (__iter).dma + (__iter).curr); \
2873 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2874 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2877 * for_each_sgt_page - iterate over the pages of the given sg_table
2878 * @__pp: page pointer (output)
2879 * @__iter: 'struct sgt_iter' (iterator state, internal)
2880 * @__sgt: sg_table to iterate over (input)
2882 #define for_each_sgt_page(__pp, __iter, __sgt) \
2883 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2884 ((__pp) = (__iter).pfn == 0 ? NULL : \
2885 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2886 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2887 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2889 static inline unsigned int i915_sg_page_sizes(struct scatterlist
*sg
)
2891 unsigned int page_sizes
;
2895 GEM_BUG_ON(sg
->offset
);
2896 GEM_BUG_ON(!IS_ALIGNED(sg
->length
, PAGE_SIZE
));
2897 page_sizes
|= sg
->length
;
2904 static inline unsigned int i915_sg_segment_size(void)
2906 unsigned int size
= swiotlb_max_segment();
2909 return SCATTERLIST_MAX_SEGMENT
;
2911 size
= rounddown(size
, PAGE_SIZE
);
2912 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2913 if (size
< PAGE_SIZE
)
2919 static inline const struct intel_device_info
*
2920 intel_info(const struct drm_i915_private
*dev_priv
)
2922 return &dev_priv
->info
;
2925 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2927 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2928 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2930 #define REVID_FOREVER 0xff
2931 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2933 #define GEN_FOREVER (0)
2935 #define INTEL_GEN_MASK(s, e) ( \
2936 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2937 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2938 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2939 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2943 * Returns true if Gen is in inclusive range [Start, End].
2945 * Use GEN_FOREVER for unbound start and or end.
2947 #define IS_GEN(dev_priv, s, e) \
2948 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2951 * Return true if revision is in range [since,until] inclusive.
2953 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2955 #define IS_REVID(p, since, until) \
2956 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2958 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2960 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2961 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2962 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2963 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2964 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2965 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2966 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2967 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2968 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2969 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2970 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2971 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2972 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2973 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2974 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2975 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2976 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2977 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2978 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2979 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2980 (dev_priv)->info.gt == 1)
2981 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2982 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2983 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2984 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2985 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2986 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2987 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2988 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2989 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2990 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2991 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2992 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2993 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2994 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2995 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2996 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2997 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2998 /* ULX machines are also considered ULT. */
2999 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
3000 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
3001 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
3002 (dev_priv)->info.gt == 3)
3003 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
3004 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
3005 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
3006 (dev_priv)->info.gt == 3)
3007 /* ULX machines are also considered ULT. */
3008 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
3009 INTEL_DEVID(dev_priv) == 0x0A1E)
3010 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
3011 INTEL_DEVID(dev_priv) == 0x1913 || \
3012 INTEL_DEVID(dev_priv) == 0x1916 || \
3013 INTEL_DEVID(dev_priv) == 0x1921 || \
3014 INTEL_DEVID(dev_priv) == 0x1926)
3015 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
3016 INTEL_DEVID(dev_priv) == 0x1915 || \
3017 INTEL_DEVID(dev_priv) == 0x191E)
3018 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
3019 INTEL_DEVID(dev_priv) == 0x5913 || \
3020 INTEL_DEVID(dev_priv) == 0x5916 || \
3021 INTEL_DEVID(dev_priv) == 0x5921 || \
3022 INTEL_DEVID(dev_priv) == 0x5926)
3023 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
3024 INTEL_DEVID(dev_priv) == 0x5915 || \
3025 INTEL_DEVID(dev_priv) == 0x591E)
3026 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
3027 (dev_priv)->info.gt == 2)
3028 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
3029 (dev_priv)->info.gt == 3)
3030 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
3031 (dev_priv)->info.gt == 4)
3032 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
3033 (dev_priv)->info.gt == 2)
3034 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
3035 (dev_priv)->info.gt == 3)
3036 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
3037 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
3038 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
3039 (dev_priv)->info.gt == 2)
3041 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
3043 #define SKL_REVID_A0 0x0
3044 #define SKL_REVID_B0 0x1
3045 #define SKL_REVID_C0 0x2
3046 #define SKL_REVID_D0 0x3
3047 #define SKL_REVID_E0 0x4
3048 #define SKL_REVID_F0 0x5
3049 #define SKL_REVID_G0 0x6
3050 #define SKL_REVID_H0 0x7
3052 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
3054 #define BXT_REVID_A0 0x0
3055 #define BXT_REVID_A1 0x1
3056 #define BXT_REVID_B0 0x3
3057 #define BXT_REVID_B_LAST 0x8
3058 #define BXT_REVID_C0 0x9
3060 #define IS_BXT_REVID(dev_priv, since, until) \
3061 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
3063 #define KBL_REVID_A0 0x0
3064 #define KBL_REVID_B0 0x1
3065 #define KBL_REVID_C0 0x2
3066 #define KBL_REVID_D0 0x3
3067 #define KBL_REVID_E0 0x4
3069 #define IS_KBL_REVID(dev_priv, since, until) \
3070 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
3072 #define GLK_REVID_A0 0x0
3073 #define GLK_REVID_A1 0x1
3075 #define IS_GLK_REVID(dev_priv, since, until) \
3076 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
3078 #define CNL_REVID_A0 0x0
3079 #define CNL_REVID_B0 0x1
3081 #define IS_CNL_REVID(p, since, until) \
3082 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
3085 * The genX designation typically refers to the render engine, so render
3086 * capability related checks should use IS_GEN, while display and other checks
3087 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
3090 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
3091 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
3092 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
3093 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
3094 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
3095 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
3096 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
3097 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
3098 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
3100 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
3101 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
3102 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
3104 #define ENGINE_MASK(id) BIT(id)
3105 #define RENDER_RING ENGINE_MASK(RCS)
3106 #define BSD_RING ENGINE_MASK(VCS)
3107 #define BLT_RING ENGINE_MASK(BCS)
3108 #define VEBOX_RING ENGINE_MASK(VECS)
3109 #define BSD2_RING ENGINE_MASK(VCS2)
3110 #define ALL_ENGINES (~0)
3112 #define HAS_ENGINE(dev_priv, id) \
3113 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
3115 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
3116 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
3117 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
3118 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
3120 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
3121 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
3122 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
3123 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
3124 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
3126 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
3128 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
3129 ((dev_priv)->info.has_logical_ring_contexts)
3130 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
3131 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
3132 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
3133 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
3134 GEM_BUG_ON((sizes) == 0); \
3135 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
3138 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
3139 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
3140 ((dev_priv)->info.overlay_needs_physical)
3142 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
3143 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
3145 /* WaRsDisableCoarsePowerGating:skl,bxt */
3146 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
3147 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
3150 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
3151 * even when in MSI mode. This results in spurious interrupt warnings if the
3152 * legacy irq no. is shared with another device. The kernel then disables that
3153 * interrupt source and so prevents the other device from working properly.
3155 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
3158 #define HAS_AUX_IRQ(dev_priv) true
3159 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
3161 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
3162 * rows, which changed the alignment requirements and fence programming.
3164 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
3165 !(IS_I915G(dev_priv) || \
3166 IS_I915GM(dev_priv)))
3167 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
3168 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
3170 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
3171 #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
3172 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
3173 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
3175 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
3177 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
3179 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
3180 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
3181 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
3182 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
3183 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
3185 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
3187 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
3188 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
3190 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
3193 * For now, anything with a GuC requires uCode loading, and then supports
3194 * command submission once loaded. But these are logically independent
3195 * properties, so we have separate macros to test them.
3197 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
3198 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
3199 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3200 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
3201 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
3203 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
3205 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
3207 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
3208 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
3209 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
3210 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
3211 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
3212 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
3213 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
3214 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
3215 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
3216 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
3217 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
3218 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
3219 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
3220 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
3221 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
3222 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
3224 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3225 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3226 #define HAS_PCH_CNP_LP(dev_priv) \
3227 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3228 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
3229 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
3230 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3231 #define HAS_PCH_LPT_LP(dev_priv) \
3232 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
3233 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
3234 #define HAS_PCH_LPT_H(dev_priv) \
3235 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
3236 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
3237 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
3238 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
3239 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
3240 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3242 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3244 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3246 /* DPF == dynamic parity feature */
3247 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3248 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
3249 2 : HAS_L3_DPF(dev_priv))
3251 #define GT_FREQUENCY_MULTIPLIER 50
3252 #define GEN9_FREQ_SCALER 3
3254 #include "i915_trace.h"
3256 static inline bool intel_vtd_active(void)
3258 #ifdef CONFIG_INTEL_IOMMU
3259 if (intel_iommu_gfx_mapped
)
3265 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3267 return INTEL_GEN(dev_priv
) >= 6 && intel_vtd_active();
3271 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
3273 return IS_BROXTON(dev_priv
) && intel_vtd_active();
3276 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
3279 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
3283 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
3284 const char *fmt
, ...);
3286 #define i915_report_error(dev_priv, fmt, ...) \
3287 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
3289 #ifdef CONFIG_COMPAT
3290 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
3293 #define i915_compat_ioctl NULL
3295 extern const struct dev_pm_ops i915_pm_ops
;
3297 extern int i915_driver_load(struct pci_dev
*pdev
,
3298 const struct pci_device_id
*ent
);
3299 extern void i915_driver_unload(struct drm_device
*dev
);
3300 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
3301 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
3303 #define I915_RESET_QUIET BIT(0)
3304 extern void i915_reset(struct drm_i915_private
*i915
, unsigned int flags
);
3305 extern int i915_reset_engine(struct intel_engine_cs
*engine
,
3306 unsigned int flags
);
3308 extern bool intel_has_reset_engine(struct drm_i915_private
*dev_priv
);
3309 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
3310 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
3311 extern void intel_hangcheck_init(struct drm_i915_private
*dev_priv
);
3312 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
3313 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
3314 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
3315 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
3316 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
3318 int intel_engines_init_mmio(struct drm_i915_private
*dev_priv
);
3319 int intel_engines_init(struct drm_i915_private
*dev_priv
);
3321 /* intel_hotplug.c */
3322 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
3323 u32 pin_mask
, u32 long_mask
);
3324 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
3325 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
3326 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
3327 enum port
intel_hpd_pin_to_port(enum hpd_pin pin
);
3328 enum hpd_pin
intel_hpd_pin(enum port port
);
3329 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3330 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
3333 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
3335 unsigned long delay
;
3337 if (unlikely(!i915_modparams
.enable_hangcheck
))
3340 /* Don't continually defer the hangcheck so that it is always run at
3341 * least once after work has been scheduled on any ring. Otherwise,
3342 * we will ignore a hung ring if a second ring is kept busy.
3345 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
3346 queue_delayed_work(system_long_wq
,
3347 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
3351 void i915_handle_error(struct drm_i915_private
*dev_priv
,
3353 const char *fmt
, ...);
3355 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
3356 extern void intel_irq_fini(struct drm_i915_private
*dev_priv
);
3357 int intel_irq_install(struct drm_i915_private
*dev_priv
);
3358 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
3360 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3362 return dev_priv
->gvt
;
3365 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3367 return dev_priv
->vgpu
.active
;
3370 u32
i915_pipestat_enable_mask(struct drm_i915_private
*dev_priv
,
3373 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3377 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3380 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3381 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3382 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3385 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3386 uint32_t interrupt_mask
,
3387 uint32_t enabled_irq_mask
);
3389 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3391 ilk_update_display_irq(dev_priv
, bits
, bits
);
3394 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3396 ilk_update_display_irq(dev_priv
, bits
, 0);
3398 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3400 uint32_t interrupt_mask
,
3401 uint32_t enabled_irq_mask
);
3402 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3403 enum pipe pipe
, uint32_t bits
)
3405 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3407 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3408 enum pipe pipe
, uint32_t bits
)
3410 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3412 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3413 uint32_t interrupt_mask
,
3414 uint32_t enabled_irq_mask
);
3416 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3418 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3421 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3423 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3427 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3428 struct drm_file
*file_priv
);
3429 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3430 struct drm_file
*file_priv
);
3431 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3432 struct drm_file
*file_priv
);
3433 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3434 struct drm_file
*file_priv
);
3435 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3436 struct drm_file
*file_priv
);
3437 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3438 struct drm_file
*file_priv
);
3439 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3440 struct drm_file
*file_priv
);
3441 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3442 struct drm_file
*file_priv
);
3443 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3444 struct drm_file
*file_priv
);
3445 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3446 struct drm_file
*file_priv
);
3447 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3448 struct drm_file
*file
);
3449 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3450 struct drm_file
*file
);
3451 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3452 struct drm_file
*file_priv
);
3453 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3454 struct drm_file
*file_priv
);
3455 int i915_gem_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
3456 struct drm_file
*file_priv
);
3457 int i915_gem_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
3458 struct drm_file
*file_priv
);
3459 int i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3460 void i915_gem_cleanup_userptr(struct drm_i915_private
*dev_priv
);
3461 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3462 struct drm_file
*file
);
3463 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3464 struct drm_file
*file_priv
);
3465 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3466 struct drm_file
*file_priv
);
3467 void i915_gem_sanitize(struct drm_i915_private
*i915
);
3468 int i915_gem_load_init(struct drm_i915_private
*dev_priv
);
3469 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
);
3470 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3471 int i915_gem_freeze(struct drm_i915_private
*dev_priv
);
3472 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3474 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
);
3475 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3476 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3477 const struct drm_i915_gem_object_ops
*ops
);
3478 struct drm_i915_gem_object
*
3479 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
);
3480 struct drm_i915_gem_object
*
3481 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
3482 const void *data
, size_t size
);
3483 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3484 void i915_gem_free_object(struct drm_gem_object
*obj
);
3486 static inline void i915_gem_drain_freed_objects(struct drm_i915_private
*i915
)
3488 /* A single pass should suffice to release all the freed objects (along
3489 * most call paths) , but be a little more paranoid in that freeing
3490 * the objects does take a little amount of time, during which the rcu
3491 * callbacks could have added new objects into the freed list, and
3492 * armed the work again.
3496 } while (flush_work(&i915
->mm
.free_work
));
3499 static inline void i915_gem_drain_workqueue(struct drm_i915_private
*i915
)
3502 * Similar to objects above (see i915_gem_drain_freed-objects), in
3503 * general we have workers that are armed by RCU and then rearm
3504 * themselves in their callbacks. To be paranoid, we need to
3505 * drain the workqueue a second time after waiting for the RCU
3506 * grace period so that we catch work queued via RCU from the first
3507 * pass. As neither drain_workqueue() nor flush_workqueue() report
3508 * a result, we make an assumption that we only don't require more
3509 * than 2 passes to catch all recursive RCU delayed work.
3515 drain_workqueue(i915
->wq
);
3519 struct i915_vma
* __must_check
3520 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3521 const struct i915_ggtt_view
*view
,
3526 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3527 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3529 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
);
3531 static inline int __sg_page_count(const struct scatterlist
*sg
)
3533 return sg
->length
>> PAGE_SHIFT
;
3536 struct scatterlist
*
3537 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
3538 unsigned int n
, unsigned int *offset
);
3541 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
,
3545 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
3549 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
3552 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
3553 struct sg_table
*pages
,
3554 unsigned int sg_page_sizes
);
3555 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3557 static inline int __must_check
3558 i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3560 might_lock(&obj
->mm
.lock
);
3562 if (atomic_inc_not_zero(&obj
->mm
.pages_pin_count
))
3565 return __i915_gem_object_get_pages(obj
);
3569 __i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3571 GEM_BUG_ON(!obj
->mm
.pages
);
3573 atomic_inc(&obj
->mm
.pages_pin_count
);
3577 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object
*obj
)
3579 return atomic_read(&obj
->mm
.pages_pin_count
);
3583 __i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3585 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
3586 GEM_BUG_ON(!obj
->mm
.pages
);
3588 atomic_dec(&obj
->mm
.pages_pin_count
);
3592 i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3594 __i915_gem_object_unpin_pages(obj
);
3597 enum i915_mm_subclass
{ /* lockdep subclass for obj->mm.lock */
3602 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
3603 enum i915_mm_subclass subclass
);
3604 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
);
3606 enum i915_map_type
{
3609 #define I915_MAP_OVERRIDE BIT(31)
3610 I915_MAP_FORCE_WB
= I915_MAP_WB
| I915_MAP_OVERRIDE
,
3611 I915_MAP_FORCE_WC
= I915_MAP_WC
| I915_MAP_OVERRIDE
,
3615 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3616 * @obj: the object to map into kernel address space
3617 * @type: the type of mapping, used to select pgprot_t
3619 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3620 * pages and then returns a contiguous mapping of the backing storage into
3621 * the kernel address space. Based on the @type of mapping, the PTE will be
3622 * set to either WriteBack or WriteCombine (via pgprot_t).
3624 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3625 * mapping is no longer required.
3627 * Returns the pointer through which to access the mapped object, or an
3628 * ERR_PTR() on error.
3630 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3631 enum i915_map_type type
);
3634 * i915_gem_object_unpin_map - releases an earlier mapping
3635 * @obj: the object to unmap
3637 * After pinning the object and mapping its pages, once you are finished
3638 * with your access, call i915_gem_object_unpin_map() to release the pin
3639 * upon the mapping. Once the pin count reaches zero, that mapping may be
3642 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3644 i915_gem_object_unpin_pages(obj
);
3647 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3648 unsigned int *needs_clflush
);
3649 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
3650 unsigned int *needs_clflush
);
3651 #define CLFLUSH_BEFORE BIT(0)
3652 #define CLFLUSH_AFTER BIT(1)
3653 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3656 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object
*obj
)
3658 i915_gem_object_unpin_pages(obj
);
3661 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3662 void i915_vma_move_to_active(struct i915_vma
*vma
,
3663 struct drm_i915_gem_request
*req
,
3664 unsigned int flags
);
3665 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3666 struct drm_device
*dev
,
3667 struct drm_mode_create_dumb
*args
);
3668 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3669 uint32_t handle
, uint64_t *offset
);
3670 int i915_gem_mmap_gtt_version(void);
3672 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3673 struct drm_i915_gem_object
*new,
3674 unsigned frontbuffer_bits
);
3676 int __must_check
i915_gem_set_global_seqno(struct drm_device
*dev
, u32 seqno
);
3678 struct drm_i915_gem_request
*
3679 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3681 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3683 static inline bool i915_reset_backoff(struct i915_gpu_error
*error
)
3685 return unlikely(test_bit(I915_RESET_BACKOFF
, &error
->flags
));
3688 static inline bool i915_reset_handoff(struct i915_gpu_error
*error
)
3690 return unlikely(test_bit(I915_RESET_HANDOFF
, &error
->flags
));
3693 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3695 return unlikely(test_bit(I915_WEDGED
, &error
->flags
));
3698 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error
*error
)
3700 return i915_reset_backoff(error
) | i915_terminally_wedged(error
);
3703 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3705 return READ_ONCE(error
->reset_count
);
3708 static inline u32
i915_reset_engine_count(struct i915_gpu_error
*error
,
3709 struct intel_engine_cs
*engine
)
3711 return READ_ONCE(error
->reset_engine_count
[engine
->id
]);
3714 struct drm_i915_gem_request
*
3715 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
);
3716 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
);
3717 void i915_gem_reset(struct drm_i915_private
*dev_priv
);
3718 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
);
3719 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
);
3720 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
);
3721 bool i915_gem_unset_wedged(struct drm_i915_private
*dev_priv
);
3722 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
3723 struct drm_i915_gem_request
*request
);
3725 void i915_gem_init_mmio(struct drm_i915_private
*i915
);
3726 int __must_check
i915_gem_init(struct drm_i915_private
*dev_priv
);
3727 int __must_check
i915_gem_init_hw(struct drm_i915_private
*dev_priv
);
3728 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
);
3729 void i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
);
3730 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3731 unsigned int flags
);
3732 int __must_check
i915_gem_suspend(struct drm_i915_private
*dev_priv
);
3733 void i915_gem_resume(struct drm_i915_private
*dev_priv
);
3734 int i915_gem_fault(struct vm_fault
*vmf
);
3735 int i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
3738 struct intel_rps_client
*rps
);
3739 int i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
3742 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3745 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
);
3747 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
);
3749 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3750 struct i915_vma
* __must_check
3751 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3753 const struct i915_ggtt_view
*view
);
3754 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3755 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3757 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
);
3758 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3760 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3761 enum i915_cache_level cache_level
);
3763 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3764 struct dma_buf
*dma_buf
);
3766 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3767 struct drm_gem_object
*gem_obj
, int flags
);
3769 static inline struct i915_hw_ppgtt
*
3770 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3772 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3775 /* i915_gem_fence_reg.c */
3776 struct drm_i915_fence_reg
*
3777 i915_reserve_fence(struct drm_i915_private
*dev_priv
);
3778 void i915_unreserve_fence(struct drm_i915_fence_reg
*fence
);
3780 void i915_gem_revoke_fences(struct drm_i915_private
*dev_priv
);
3781 void i915_gem_restore_fences(struct drm_i915_private
*dev_priv
);
3783 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv
);
3784 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3785 struct sg_table
*pages
);
3786 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
,
3787 struct sg_table
*pages
);
3789 static inline struct i915_gem_context
*
3790 __i915_gem_context_lookup_rcu(struct drm_i915_file_private
*file_priv
, u32 id
)
3792 return idr_find(&file_priv
->context_idr
, id
);
3795 static inline struct i915_gem_context
*
3796 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3798 struct i915_gem_context
*ctx
;
3801 ctx
= __i915_gem_context_lookup_rcu(file_priv
, id
);
3802 if (ctx
&& !kref_get_unless_zero(&ctx
->ref
))
3809 static inline struct intel_timeline
*
3810 i915_gem_context_lookup_timeline(struct i915_gem_context
*ctx
,
3811 struct intel_engine_cs
*engine
)
3813 struct i915_address_space
*vm
;
3815 vm
= ctx
->ppgtt
? &ctx
->ppgtt
->base
: &ctx
->i915
->ggtt
.base
;
3816 return &vm
->timeline
.engine
[engine
->id
];
3819 int i915_perf_open_ioctl(struct drm_device
*dev
, void *data
,
3820 struct drm_file
*file
);
3821 int i915_perf_add_config_ioctl(struct drm_device
*dev
, void *data
,
3822 struct drm_file
*file
);
3823 int i915_perf_remove_config_ioctl(struct drm_device
*dev
, void *data
,
3824 struct drm_file
*file
);
3825 void i915_oa_init_reg_state(struct intel_engine_cs
*engine
,
3826 struct i915_gem_context
*ctx
,
3827 uint32_t *reg_state
);
3829 /* i915_gem_evict.c */
3830 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3831 u64 min_size
, u64 alignment
,
3832 unsigned cache_level
,
3835 int __must_check
i915_gem_evict_for_node(struct i915_address_space
*vm
,
3836 struct drm_mm_node
*node
,
3837 unsigned int flags
);
3838 int i915_gem_evict_vm(struct i915_address_space
*vm
);
3840 /* belongs in i915_gem_gtt.h */
3841 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3844 if (INTEL_GEN(dev_priv
) < 6)
3845 intel_gtt_chipset_flush();
3848 /* i915_gem_stolen.c */
3849 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3850 struct drm_mm_node
*node
, u64 size
,
3851 unsigned alignment
);
3852 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3853 struct drm_mm_node
*node
, u64 size
,
3854 unsigned alignment
, u64 start
,
3856 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3857 struct drm_mm_node
*node
);
3858 int i915_gem_init_stolen(struct drm_i915_private
*dev_priv
);
3859 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3860 struct drm_i915_gem_object
*
3861 i915_gem_object_create_stolen(struct drm_i915_private
*dev_priv
, u32 size
);
3862 struct drm_i915_gem_object
*
3863 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private
*dev_priv
,
3868 /* i915_gem_internal.c */
3869 struct drm_i915_gem_object
*
3870 i915_gem_object_create_internal(struct drm_i915_private
*dev_priv
,
3873 /* i915_gem_shrinker.c */
3874 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3875 unsigned long target
,
3876 unsigned long *nr_scanned
,
3878 #define I915_SHRINK_PURGEABLE 0x1
3879 #define I915_SHRINK_UNBOUND 0x2
3880 #define I915_SHRINK_BOUND 0x4
3881 #define I915_SHRINK_ACTIVE 0x8
3882 #define I915_SHRINK_VMAPS 0x10
3883 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3884 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3885 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3888 /* i915_gem_tiling.c */
3889 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3891 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3893 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3894 i915_gem_object_is_tiled(obj
);
3897 u32
i915_gem_fence_size(struct drm_i915_private
*dev_priv
, u32 size
,
3898 unsigned int tiling
, unsigned int stride
);
3899 u32
i915_gem_fence_alignment(struct drm_i915_private
*dev_priv
, u32 size
,
3900 unsigned int tiling
, unsigned int stride
);
3902 /* i915_debugfs.c */
3903 #ifdef CONFIG_DEBUG_FS
3904 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3905 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3906 void intel_display_crc_init(struct drm_i915_private
*dev_priv
);
3908 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3909 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3911 static inline void intel_display_crc_init(struct drm_i915_private
*dev_priv
) {}
3914 /* i915_gpu_error.c */
3915 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3918 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3919 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3920 const struct i915_gpu_state
*gpu
);
3921 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3922 struct drm_i915_private
*i915
,
3923 size_t count
, loff_t pos
);
3924 static inline void i915_error_state_buf_release(
3925 struct drm_i915_error_state_buf
*eb
)
3930 struct i915_gpu_state
*i915_capture_gpu_state(struct drm_i915_private
*i915
);
3931 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3933 const char *error_msg
);
3935 static inline struct i915_gpu_state
*
3936 i915_gpu_state_get(struct i915_gpu_state
*gpu
)
3938 kref_get(&gpu
->ref
);
3942 void __i915_gpu_state_free(struct kref
*kref
);
3943 static inline void i915_gpu_state_put(struct i915_gpu_state
*gpu
)
3946 kref_put(&gpu
->ref
, __i915_gpu_state_free
);
3949 struct i915_gpu_state
*i915_first_error_state(struct drm_i915_private
*i915
);
3950 void i915_reset_error_state(struct drm_i915_private
*i915
);
3954 static inline void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3956 const char *error_msg
)
3960 static inline struct i915_gpu_state
*
3961 i915_first_error_state(struct drm_i915_private
*i915
)
3966 static inline void i915_reset_error_state(struct drm_i915_private
*i915
)
3972 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3974 /* i915_cmd_parser.c */
3975 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3976 void intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3977 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3978 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3979 struct drm_i915_gem_object
*batch_obj
,
3980 struct drm_i915_gem_object
*shadow_batch_obj
,
3981 u32 batch_start_offset
,
3986 extern void i915_perf_init(struct drm_i915_private
*dev_priv
);
3987 extern void i915_perf_fini(struct drm_i915_private
*dev_priv
);
3988 extern void i915_perf_register(struct drm_i915_private
*dev_priv
);
3989 extern void i915_perf_unregister(struct drm_i915_private
*dev_priv
);
3991 /* i915_suspend.c */
3992 extern int i915_save_state(struct drm_i915_private
*dev_priv
);
3993 extern int i915_restore_state(struct drm_i915_private
*dev_priv
);
3996 void i915_setup_sysfs(struct drm_i915_private
*dev_priv
);
3997 void i915_teardown_sysfs(struct drm_i915_private
*dev_priv
);
3999 /* intel_lpe_audio.c */
4000 int intel_lpe_audio_init(struct drm_i915_private
*dev_priv
);
4001 void intel_lpe_audio_teardown(struct drm_i915_private
*dev_priv
);
4002 void intel_lpe_audio_irq_handler(struct drm_i915_private
*dev_priv
);
4003 void intel_lpe_audio_notify(struct drm_i915_private
*dev_priv
,
4004 enum pipe pipe
, enum port port
,
4005 const void *eld
, int ls_clock
, bool dp_output
);
4008 extern int intel_setup_gmbus(struct drm_i915_private
*dev_priv
);
4009 extern void intel_teardown_gmbus(struct drm_i915_private
*dev_priv
);
4010 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
4013 extern struct i2c_adapter
*
4014 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
4015 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
4016 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
4017 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
4019 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
4021 extern void intel_i2c_reset(struct drm_i915_private
*dev_priv
);
4024 void intel_bios_init(struct drm_i915_private
*dev_priv
);
4025 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
4026 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
4027 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
4028 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
4029 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
4030 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
4031 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
4032 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
4034 bool intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv
,
4038 /* intel_opregion.c */
4040 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
4041 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
4042 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
4043 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
4044 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
4046 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
4048 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
4050 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
4051 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
4052 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
4053 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
4057 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
4062 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
4066 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
4074 extern void intel_register_dsm_handler(void);
4075 extern void intel_unregister_dsm_handler(void);
4077 static inline void intel_register_dsm_handler(void) { return; }
4078 static inline void intel_unregister_dsm_handler(void) { return; }
4079 #endif /* CONFIG_ACPI */
4081 /* intel_device_info.c */
4082 static inline struct intel_device_info
*
4083 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
4085 return (struct intel_device_info
*)&dev_priv
->info
;
4088 const char *intel_platform_name(enum intel_platform platform
);
4089 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
4090 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
4093 extern void intel_modeset_init_hw(struct drm_device
*dev
);
4094 extern int intel_modeset_init(struct drm_device
*dev
);
4095 extern void intel_modeset_gem_init(struct drm_device
*dev
);
4096 extern void intel_modeset_cleanup(struct drm_device
*dev
);
4097 extern int intel_connector_register(struct drm_connector
*);
4098 extern void intel_connector_unregister(struct drm_connector
*);
4099 extern int intel_modeset_vga_set_state(struct drm_i915_private
*dev_priv
,
4101 extern void intel_display_resume(struct drm_device
*dev
);
4102 extern void i915_redisable_vga(struct drm_i915_private
*dev_priv
);
4103 extern void i915_redisable_vga_power_on(struct drm_i915_private
*dev_priv
);
4104 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
4105 extern void intel_init_pch_refclk(struct drm_i915_private
*dev_priv
);
4106 extern int intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
4107 extern bool intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
4110 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
4111 struct drm_file
*file
);
4114 extern struct intel_overlay_error_state
*
4115 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
4116 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
4117 struct intel_overlay_error_state
*error
);
4119 extern struct intel_display_error_state
*
4120 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
4121 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
4122 struct intel_display_error_state
*error
);
4124 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
4125 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
4126 int skl_pcode_request(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 request
,
4127 u32 reply_mask
, u32 reply
, int timeout_base_ms
);
4129 /* intel_sideband.c */
4130 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
4131 int vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
4132 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
4133 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
4134 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
4135 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4136 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4137 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4138 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4139 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4140 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4141 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
4142 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
4143 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
4144 enum intel_sbi_destination destination
);
4145 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
4146 enum intel_sbi_destination destination
);
4147 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
4148 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
4150 /* intel_dpio_phy.c */
4151 void bxt_port_to_phy_channel(struct drm_i915_private
*dev_priv
, enum port port
,
4152 enum dpio_phy
*phy
, enum dpio_channel
*ch
);
4153 void bxt_ddi_phy_set_signal_level(struct drm_i915_private
*dev_priv
,
4154 enum port port
, u32 margin
, u32 scale
,
4155 u32 enable
, u32 deemphasis
);
4156 void bxt_ddi_phy_init(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
4157 void bxt_ddi_phy_uninit(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
);
4158 bool bxt_ddi_phy_is_enabled(struct drm_i915_private
*dev_priv
,
4160 bool bxt_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
,
4162 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder
*encoder
,
4163 uint8_t lane_count
);
4164 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder
*encoder
,
4165 uint8_t lane_lat_optim_mask
);
4166 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder
*encoder
);
4168 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
4169 u32 deemph_reg_value
, u32 margin_reg_value
,
4170 bool uniq_trans_scale
);
4171 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
4173 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
4174 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
4175 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
4176 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
4178 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
4179 u32 demph_reg_value
, u32 preemph_reg_value
,
4180 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
4181 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
4182 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
4183 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
4185 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
4186 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
4187 u64
intel_rc6_residency_us(struct drm_i915_private
*dev_priv
,
4188 const i915_reg_t reg
);
4190 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
4191 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
4193 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
4194 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
4195 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
4196 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
4198 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
4199 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
4200 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
4201 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
4203 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
4204 * will be implemented using 2 32-bit writes in an arbitrary order with
4205 * an arbitrary delay between them. This can cause the hardware to
4206 * act upon the intermediate value, possibly leading to corruption and
4207 * machine death. For this reason we do not support I915_WRITE64, or
4208 * dev_priv->uncore.funcs.mmio_writeq.
4210 * When reading a 64-bit value as two 32-bit values, the delay may cause
4211 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
4212 * occasionally a 64-bit register does not actualy support a full readq
4213 * and must be read using two 32-bit reads.
4215 * You have been warned.
4217 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
4219 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
4220 u32 upper, lower, old_upper, loop = 0; \
4221 upper = I915_READ(upper_reg); \
4223 old_upper = upper; \
4224 lower = I915_READ(lower_reg); \
4225 upper = I915_READ(upper_reg); \
4226 } while (upper != old_upper && loop++ < 2); \
4227 (u64)upper << 32 | lower; })
4229 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
4230 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
4232 #define __raw_read(x, s) \
4233 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
4236 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
4239 #define __raw_write(x, s) \
4240 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
4241 i915_reg_t reg, uint##x##_t val) \
4243 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
4258 /* These are untraced mmio-accessors that are only valid to be used inside
4259 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4262 * Think twice, and think again, before using these.
4264 * As an example, these accessors can possibly be used between:
4266 * spin_lock_irq(&dev_priv->uncore.lock);
4267 * intel_uncore_forcewake_get__locked();
4271 * intel_uncore_forcewake_put__locked();
4272 * spin_unlock_irq(&dev_priv->uncore.lock);
4275 * Note: some registers may not need forcewake held, so
4276 * intel_uncore_forcewake_{get,put} can be omitted, see
4277 * intel_uncore_forcewake_for_reg().
4279 * Certain architectures will die if the same cacheline is concurrently accessed
4280 * by different clients (e.g. on Ivybridge). Access to registers should
4281 * therefore generally be serialised, by either the dev_priv->uncore.lock or
4282 * a more localised lock guarding all access to that bank of registers.
4284 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
4285 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4286 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4287 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
4289 /* "Broadcast RGB" property */
4290 #define INTEL_BROADCAST_RGB_AUTO 0
4291 #define INTEL_BROADCAST_RGB_FULL 1
4292 #define INTEL_BROADCAST_RGB_LIMITED 2
4294 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_i915_private
*dev_priv
)
4296 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4297 return VLV_VGACNTRL
;
4298 else if (INTEL_GEN(dev_priv
) >= 5)
4299 return CPU_VGACNTRL
;
4304 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
4306 unsigned long j
= msecs_to_jiffies(m
);
4308 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4311 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
4313 /* nsecs_to_jiffies64() does not guard against overflow */
4314 if (NSEC_PER_SEC
% HZ
&&
4315 div_u64(n
, NSEC_PER_SEC
) >= MAX_JIFFY_OFFSET
/ HZ
)
4316 return MAX_JIFFY_OFFSET
;
4318 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
4321 static inline unsigned long
4322 timespec_to_jiffies_timeout(const struct timespec
*value
)
4324 unsigned long j
= timespec_to_jiffies(value
);
4326 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
4330 * If you need to wait X milliseconds between events A and B, but event B
4331 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
4332 * when event A happened, then just before event B you call this function and
4333 * pass the timestamp as the first argument, and X as the second argument.
4336 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
4338 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
4341 * Don't re-read the value of "jiffies" every time since it may change
4342 * behind our back and break the math.
4344 tmp_jiffies
= jiffies
;
4345 target_jiffies
= timestamp_jiffies
+
4346 msecs_to_jiffies_timeout(to_wait_ms
);
4348 if (time_after(target_jiffies
, tmp_jiffies
)) {
4349 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
4350 while (remaining_jiffies
)
4352 schedule_timeout_uninterruptible(remaining_jiffies
);
4357 __i915_request_irq_complete(const struct drm_i915_gem_request
*req
)
4359 struct intel_engine_cs
*engine
= req
->engine
;
4362 /* Note that the engine may have wrapped around the seqno, and
4363 * so our request->global_seqno will be ahead of the hardware,
4364 * even though it completed the request before wrapping. We catch
4365 * this by kicking all the waiters before resetting the seqno
4366 * in hardware, and also signal the fence.
4368 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &req
->fence
.flags
))
4371 /* The request was dequeued before we were awoken. We check after
4372 * inspecting the hw to confirm that this was the same request
4373 * that generated the HWS update. The memory barriers within
4374 * the request execution are sufficient to ensure that a check
4375 * after reading the value from hw matches this request.
4377 seqno
= i915_gem_request_global_seqno(req
);
4381 /* Before we do the heavier coherent read of the seqno,
4382 * check the value (hopefully) in the CPU cacheline.
4384 if (__i915_gem_request_completed(req
, seqno
))
4387 /* Ensure our read of the seqno is coherent so that we
4388 * do not "miss an interrupt" (i.e. if this is the last
4389 * request and the seqno write from the GPU is not visible
4390 * by the time the interrupt fires, we will see that the
4391 * request is incomplete and go back to sleep awaiting
4392 * another interrupt that will never come.)
4394 * Strictly, we only need to do this once after an interrupt,
4395 * but it is easier and safer to do it every time the waiter
4398 if (engine
->irq_seqno_barrier
&&
4399 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB
, &engine
->irq_posted
)) {
4400 struct intel_breadcrumbs
*b
= &engine
->breadcrumbs
;
4402 /* The ordering of irq_posted versus applying the barrier
4403 * is crucial. The clearing of the current irq_posted must
4404 * be visible before we perform the barrier operation,
4405 * such that if a subsequent interrupt arrives, irq_posted
4406 * is reasserted and our task rewoken (which causes us to
4407 * do another __i915_request_irq_complete() immediately
4408 * and reapply the barrier). Conversely, if the clear
4409 * occurs after the barrier, then an interrupt that arrived
4410 * whilst we waited on the barrier would not trigger a
4411 * barrier on the next pass, and the read may not see the
4414 engine
->irq_seqno_barrier(engine
);
4416 /* If we consume the irq, but we are no longer the bottom-half,
4417 * the real bottom-half may not have serialised their own
4418 * seqno check with the irq-barrier (i.e. may have inspected
4419 * the seqno before we believe it coherent since they see
4420 * irq_posted == false but we are still running).
4422 spin_lock_irq(&b
->irq_lock
);
4423 if (b
->irq_wait
&& b
->irq_wait
->tsk
!= current
)
4424 /* Note that if the bottom-half is changed as we
4425 * are sending the wake-up, the new bottom-half will
4426 * be woken by whomever made the change. We only have
4427 * to worry about when we steal the irq-posted for
4430 wake_up_process(b
->irq_wait
->tsk
);
4431 spin_unlock_irq(&b
->irq_lock
);
4433 if (__i915_gem_request_completed(req
, seqno
))
4440 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
4441 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
4443 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4444 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4445 * perform the operation. To check beforehand, pass in the parameters to
4446 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4447 * you only need to pass in the minor offsets, page-aligned pointers are
4450 * For just checking for SSE4.1, in the foreknowledge that the future use
4451 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4453 #define i915_can_memcpy_from_wc(dst, src, len) \
4454 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4456 #define i915_has_memcpy_from_wc() \
4457 i915_memcpy_from_wc(NULL, NULL, 0)
4460 int remap_io_mapping(struct vm_area_struct
*vma
,
4461 unsigned long addr
, unsigned long pfn
, unsigned long size
,
4462 struct io_mapping
*iomap
);
4464 static inline int intel_hws_csb_write_index(struct drm_i915_private
*i915
)
4466 if (INTEL_GEN(i915
) >= 10)
4467 return CNL_HWS_CSB_WRITE_INDEX
;
4469 return I915_HWS_CSB_WRITE_INDEX
;