2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_frontbuffer.h"
36 #include "intel_mocs.h"
37 #include <linux/dma-fence-array.h>
38 #include <linux/reservation.h>
39 #include <linux/shmem_fs.h>
40 #include <linux/slab.h>
41 #include <linux/swap.h>
42 #include <linux/pci.h>
43 #include <linux/dma-buf.h>
45 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
);
46 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
47 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
49 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
50 enum i915_cache_level level
)
52 return HAS_LLC(to_i915(dev
)) || level
!= I915_CACHE_NONE
;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
57 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
60 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
63 return obj
->pin_display
;
67 insert_mappable_node(struct i915_ggtt
*ggtt
,
68 struct drm_mm_node
*node
, u32 size
)
70 memset(node
, 0, sizeof(*node
));
71 return drm_mm_insert_node_in_range_generic(&ggtt
->base
.mm
, node
,
73 0, ggtt
->mappable_end
,
74 DRM_MM_SEARCH_DEFAULT
,
75 DRM_MM_CREATE_DEFAULT
);
79 remove_mappable_node(struct drm_mm_node
*node
)
81 drm_mm_remove_node(node
);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
88 spin_lock(&dev_priv
->mm
.object_stat_lock
);
89 dev_priv
->mm
.object_count
++;
90 dev_priv
->mm
.object_memory
+= size
;
91 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
94 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
97 spin_lock(&dev_priv
->mm
.object_stat_lock
);
98 dev_priv
->mm
.object_count
--;
99 dev_priv
->mm
.object_memory
-= size
;
100 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
104 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
110 if (!i915_reset_in_progress(error
))
114 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
115 * userspace. If it takes that long something really bad is going on and
116 * we should simply try to bail out and fail as gracefully as possible.
118 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 !i915_reset_in_progress(error
),
122 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
124 } else if (ret
< 0) {
131 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
136 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
140 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
148 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_private
*dev_priv
= to_i915(dev
);
152 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
153 struct drm_i915_gem_get_aperture
*args
= data
;
154 struct i915_vma
*vma
;
158 mutex_lock(&dev
->struct_mutex
);
159 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
160 if (i915_vma_is_pinned(vma
))
161 pinned
+= vma
->node
.size
;
162 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
163 if (i915_vma_is_pinned(vma
))
164 pinned
+= vma
->node
.size
;
165 mutex_unlock(&dev
->struct_mutex
);
167 args
->aper_size
= ggtt
->base
.total
;
168 args
->aper_available_size
= args
->aper_size
- pinned
;
173 static struct sg_table
*
174 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
176 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
177 drm_dma_handle_t
*phys
;
179 struct scatterlist
*sg
;
183 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 return ERR_PTR(-EINVAL
);
186 /* Always aligning to the object size, allows a single allocation
187 * to handle all possible callers, and given typical object sizes,
188 * the alignment of the buddy allocation will naturally match.
190 phys
= drm_pci_alloc(obj
->base
.dev
,
192 roundup_pow_of_two(obj
->base
.size
));
194 return ERR_PTR(-ENOMEM
);
197 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
201 page
= shmem_read_mapping_page(mapping
, i
);
207 src
= kmap_atomic(page
);
208 memcpy(vaddr
, src
, PAGE_SIZE
);
209 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
216 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
218 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
220 st
= ERR_PTR(-ENOMEM
);
224 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
226 st
= ERR_PTR(-ENOMEM
);
232 sg
->length
= obj
->base
.size
;
234 sg_dma_address(sg
) = phys
->busaddr
;
235 sg_dma_len(sg
) = obj
->base
.size
;
237 obj
->phys_handle
= phys
;
241 drm_pci_free(obj
->base
.dev
, phys
);
246 __i915_gem_object_release_shmem(struct drm_i915_gem_object
*obj
,
247 struct sg_table
*pages
,
250 GEM_BUG_ON(obj
->mm
.madv
== __I915_MADV_PURGED
);
252 if (obj
->mm
.madv
== I915_MADV_DONTNEED
)
253 obj
->mm
.dirty
= false;
256 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0 &&
257 !cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
258 drm_clflush_sg(pages
);
260 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
261 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
265 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
,
266 struct sg_table
*pages
)
268 __i915_gem_object_release_shmem(obj
, pages
, false);
271 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
272 char *vaddr
= obj
->phys_handle
->vaddr
;
275 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
279 page
= shmem_read_mapping_page(mapping
, i
);
283 dst
= kmap_atomic(page
);
284 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
285 memcpy(dst
, vaddr
, PAGE_SIZE
);
288 set_page_dirty(page
);
289 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
290 mark_page_accessed(page
);
294 obj
->mm
.dirty
= false;
297 sg_free_table(pages
);
300 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
304 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
306 i915_gem_object_unpin_pages(obj
);
309 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
310 .get_pages
= i915_gem_object_get_pages_phys
,
311 .put_pages
= i915_gem_object_put_pages_phys
,
312 .release
= i915_gem_object_release_phys
,
315 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
317 struct i915_vma
*vma
;
318 LIST_HEAD(still_in_list
);
321 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret
= i915_gem_object_wait(obj
,
329 I915_WAIT_INTERRUPTIBLE
|
332 MAX_SCHEDULE_TIMEOUT
,
337 i915_gem_retire_requests(to_i915(obj
->base
.dev
));
339 while ((vma
= list_first_entry_or_null(&obj
->vma_list
,
342 list_move_tail(&vma
->obj_link
, &still_in_list
);
343 ret
= i915_vma_unbind(vma
);
347 list_splice(&still_in_list
, &obj
->vma_list
);
353 i915_gem_object_wait_fence(struct dma_fence
*fence
,
356 struct intel_rps_client
*rps
)
358 struct drm_i915_gem_request
*rq
;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE
!= 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &fence
->flags
))
365 if (!dma_fence_is_i915(fence
))
366 return dma_fence_wait_timeout(fence
,
367 flags
& I915_WAIT_INTERRUPTIBLE
,
370 rq
= to_request(fence
);
371 if (i915_gem_request_completed(rq
))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq
->i915
) >= 6)
391 gen6_rps_boost(rq
->i915
, rps
, rq
->emitted_jiffies
);
396 timeout
= i915_wait_request(rq
, flags
, timeout
);
399 if (flags
& I915_WAIT_LOCKED
&& i915_gem_request_completed(rq
))
400 i915_gem_request_retire_upto(rq
);
402 if (rps
&& rq
->global_seqno
== intel_engine_last_submit(rq
->engine
)) {
403 /* The GPU is now idle and this client has stalled.
404 * Since no other client has submitted a request in the
405 * meantime, assume that this client is the only one
406 * supplying work to the GPU but is unable to keep that
407 * work supplied because it is waiting. Since the GPU is
408 * then never kept fully busy, RPS autoclocking will
409 * keep the clocks relatively low, causing further delays.
410 * Compensate by giving the synchronous client credit for
411 * a waitboost next time.
413 spin_lock(&rq
->i915
->rps
.client_lock
);
414 list_del_init(&rps
->link
);
415 spin_unlock(&rq
->i915
->rps
.client_lock
);
422 i915_gem_object_wait_reservation(struct reservation_object
*resv
,
425 struct intel_rps_client
*rps
)
427 struct dma_fence
*excl
;
429 if (flags
& I915_WAIT_ALL
) {
430 struct dma_fence
**shared
;
431 unsigned int count
, i
;
434 ret
= reservation_object_get_fences_rcu(resv
,
435 &excl
, &count
, &shared
);
439 for (i
= 0; i
< count
; i
++) {
440 timeout
= i915_gem_object_wait_fence(shared
[i
],
446 dma_fence_put(shared
[i
]);
449 for (; i
< count
; i
++)
450 dma_fence_put(shared
[i
]);
453 excl
= reservation_object_get_excl_rcu(resv
);
456 if (excl
&& timeout
> 0)
457 timeout
= i915_gem_object_wait_fence(excl
, flags
, timeout
, rps
);
464 static void __fence_set_priority(struct dma_fence
*fence
, int prio
)
466 struct drm_i915_gem_request
*rq
;
467 struct intel_engine_cs
*engine
;
469 if (!dma_fence_is_i915(fence
))
472 rq
= to_request(fence
);
474 if (!engine
->schedule
)
477 engine
->schedule(rq
, prio
);
480 static void fence_set_priority(struct dma_fence
*fence
, int prio
)
482 /* Recurse once into a fence-array */
483 if (dma_fence_is_array(fence
)) {
484 struct dma_fence_array
*array
= to_dma_fence_array(fence
);
487 for (i
= 0; i
< array
->num_fences
; i
++)
488 __fence_set_priority(array
->fences
[i
], prio
);
490 __fence_set_priority(fence
, prio
);
495 i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
499 struct dma_fence
*excl
;
501 if (flags
& I915_WAIT_ALL
) {
502 struct dma_fence
**shared
;
503 unsigned int count
, i
;
506 ret
= reservation_object_get_fences_rcu(obj
->resv
,
507 &excl
, &count
, &shared
);
511 for (i
= 0; i
< count
; i
++) {
512 fence_set_priority(shared
[i
], prio
);
513 dma_fence_put(shared
[i
]);
518 excl
= reservation_object_get_excl_rcu(obj
->resv
);
522 fence_set_priority(excl
, prio
);
529 * Waits for rendering to the object to be completed
530 * @obj: i915 gem object
531 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
532 * @timeout: how long to wait
533 * @rps: client (user process) to charge for any waitboosting
536 i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
539 struct intel_rps_client
*rps
)
542 #if IS_ENABLED(CONFIG_LOCKDEP)
543 GEM_BUG_ON(debug_locks
&&
544 !!lockdep_is_held(&obj
->base
.dev
->struct_mutex
) !=
545 !!(flags
& I915_WAIT_LOCKED
));
547 GEM_BUG_ON(timeout
< 0);
549 timeout
= i915_gem_object_wait_reservation(obj
->resv
,
552 return timeout
< 0 ? timeout
: 0;
555 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
557 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
563 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
568 if (align
> obj
->base
.size
)
571 if (obj
->ops
== &i915_gem_phys_ops
)
574 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
577 if (obj
->base
.filp
== NULL
)
580 ret
= i915_gem_object_unbind(obj
);
584 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
588 obj
->ops
= &i915_gem_phys_ops
;
590 return i915_gem_object_pin_pages(obj
);
594 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
595 struct drm_i915_gem_pwrite
*args
,
596 struct drm_file
*file
)
598 struct drm_device
*dev
= obj
->base
.dev
;
599 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
600 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
603 /* We manually control the domain here and pretend that it
604 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
606 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
607 ret
= i915_gem_object_wait(obj
,
608 I915_WAIT_INTERRUPTIBLE
|
611 MAX_SCHEDULE_TIMEOUT
,
612 to_rps_client(file
));
616 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
617 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
618 unsigned long unwritten
;
620 /* The physical object once assigned is fixed for the lifetime
621 * of the obj, so we can safely drop the lock and continue
624 mutex_unlock(&dev
->struct_mutex
);
625 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
626 mutex_lock(&dev
->struct_mutex
);
633 drm_clflush_virt_range(vaddr
, args
->size
);
634 i915_gem_chipset_flush(to_i915(dev
));
637 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
641 void *i915_gem_object_alloc(struct drm_device
*dev
)
643 struct drm_i915_private
*dev_priv
= to_i915(dev
);
644 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
647 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
649 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
650 kmem_cache_free(dev_priv
->objects
, obj
);
654 i915_gem_create(struct drm_file
*file
,
655 struct drm_device
*dev
,
659 struct drm_i915_gem_object
*obj
;
663 size
= roundup(size
, PAGE_SIZE
);
667 /* Allocate the new object */
668 obj
= i915_gem_object_create(dev
, size
);
672 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
673 /* drop reference from allocate - handle holds it now */
674 i915_gem_object_put(obj
);
683 i915_gem_dumb_create(struct drm_file
*file
,
684 struct drm_device
*dev
,
685 struct drm_mode_create_dumb
*args
)
687 /* have to work out size/pitch and return them */
688 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
689 args
->size
= args
->pitch
* args
->height
;
690 return i915_gem_create(file
, dev
,
691 args
->size
, &args
->handle
);
695 * Creates a new mm object and returns a handle to it.
696 * @dev: drm device pointer
697 * @data: ioctl data blob
698 * @file: drm file pointer
701 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
702 struct drm_file
*file
)
704 struct drm_i915_gem_create
*args
= data
;
706 i915_gem_flush_free_objects(to_i915(dev
));
708 return i915_gem_create(file
, dev
,
709 args
->size
, &args
->handle
);
713 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
714 const char *gpu_vaddr
, int gpu_offset
,
717 int ret
, cpu_offset
= 0;
720 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
721 int this_length
= min(cacheline_end
- gpu_offset
, length
);
722 int swizzled_gpu_offset
= gpu_offset
^ 64;
724 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
725 gpu_vaddr
+ swizzled_gpu_offset
,
730 cpu_offset
+= this_length
;
731 gpu_offset
+= this_length
;
732 length
-= this_length
;
739 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
740 const char __user
*cpu_vaddr
,
743 int ret
, cpu_offset
= 0;
746 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
747 int this_length
= min(cacheline_end
- gpu_offset
, length
);
748 int swizzled_gpu_offset
= gpu_offset
^ 64;
750 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
751 cpu_vaddr
+ cpu_offset
,
756 cpu_offset
+= this_length
;
757 gpu_offset
+= this_length
;
758 length
-= this_length
;
765 * Pins the specified object's pages and synchronizes the object with
766 * GPU accesses. Sets needs_clflush to non-zero if the caller should
767 * flush the object from the CPU cache.
769 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
770 unsigned int *needs_clflush
)
774 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
777 if (!i915_gem_object_has_struct_page(obj
))
780 ret
= i915_gem_object_wait(obj
,
781 I915_WAIT_INTERRUPTIBLE
|
783 MAX_SCHEDULE_TIMEOUT
,
788 ret
= i915_gem_object_pin_pages(obj
);
792 i915_gem_object_flush_gtt_write_domain(obj
);
794 /* If we're not in the cpu read domain, set ourself into the gtt
795 * read domain and manually flush cachelines (if required). This
796 * optimizes for the case when the gpu will dirty the data
797 * anyway again before the next pread happens.
799 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
800 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
803 if (*needs_clflush
&& !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
804 ret
= i915_gem_object_set_to_cpu_domain(obj
, false);
811 /* return with the pages pinned */
815 i915_gem_object_unpin_pages(obj
);
819 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
820 unsigned int *needs_clflush
)
824 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
827 if (!i915_gem_object_has_struct_page(obj
))
830 ret
= i915_gem_object_wait(obj
,
831 I915_WAIT_INTERRUPTIBLE
|
834 MAX_SCHEDULE_TIMEOUT
,
839 ret
= i915_gem_object_pin_pages(obj
);
843 i915_gem_object_flush_gtt_write_domain(obj
);
845 /* If we're not in the cpu write domain, set ourself into the
846 * gtt write domain and manually flush cachelines (as required).
847 * This optimizes for the case when the gpu will use the data
848 * right away and we therefore have to clflush anyway.
850 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
851 *needs_clflush
|= cpu_write_needs_clflush(obj
) << 1;
853 /* Same trick applies to invalidate partially written cachelines read
856 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
857 *needs_clflush
|= !cpu_cache_is_coherent(obj
->base
.dev
,
860 if (*needs_clflush
&& !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
861 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
868 if ((*needs_clflush
& CLFLUSH_AFTER
) == 0)
869 obj
->cache_dirty
= true;
871 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
872 obj
->mm
.dirty
= true;
873 /* return with the pages pinned */
877 i915_gem_object_unpin_pages(obj
);
882 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
885 if (unlikely(swizzled
)) {
886 unsigned long start
= (unsigned long) addr
;
887 unsigned long end
= (unsigned long) addr
+ length
;
889 /* For swizzling simply ensure that we always flush both
890 * channels. Lame, but simple and it works. Swizzled
891 * pwrite/pread is far from a hotpath - current userspace
892 * doesn't use it at all. */
893 start
= round_down(start
, 128);
894 end
= round_up(end
, 128);
896 drm_clflush_virt_range((void *)start
, end
- start
);
898 drm_clflush_virt_range(addr
, length
);
903 /* Only difference to the fast-path function is that this can handle bit17
904 * and uses non-atomic copy and kmap functions. */
906 shmem_pread_slow(struct page
*page
, int offset
, int length
,
907 char __user
*user_data
,
908 bool page_do_bit17_swizzling
, bool needs_clflush
)
915 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
916 page_do_bit17_swizzling
);
918 if (page_do_bit17_swizzling
)
919 ret
= __copy_to_user_swizzled(user_data
, vaddr
, offset
, length
);
921 ret
= __copy_to_user(user_data
, vaddr
+ offset
, length
);
924 return ret
? - EFAULT
: 0;
928 shmem_pread(struct page
*page
, int offset
, int length
, char __user
*user_data
,
929 bool page_do_bit17_swizzling
, bool needs_clflush
)
934 if (!page_do_bit17_swizzling
) {
935 char *vaddr
= kmap_atomic(page
);
938 drm_clflush_virt_range(vaddr
+ offset
, length
);
939 ret
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
940 kunmap_atomic(vaddr
);
945 return shmem_pread_slow(page
, offset
, length
, user_data
,
946 page_do_bit17_swizzling
, needs_clflush
);
950 i915_gem_shmem_pread(struct drm_i915_gem_object
*obj
,
951 struct drm_i915_gem_pread
*args
)
953 char __user
*user_data
;
955 unsigned int obj_do_bit17_swizzling
;
956 unsigned int needs_clflush
;
957 unsigned int idx
, offset
;
960 obj_do_bit17_swizzling
= 0;
961 if (i915_gem_object_needs_bit17_swizzle(obj
))
962 obj_do_bit17_swizzling
= BIT(17);
964 ret
= mutex_lock_interruptible(&obj
->base
.dev
->struct_mutex
);
968 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
969 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
974 user_data
= u64_to_user_ptr(args
->data_ptr
);
975 offset
= offset_in_page(args
->offset
);
976 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
977 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
981 if (offset
+ length
> PAGE_SIZE
)
982 length
= PAGE_SIZE
- offset
;
984 ret
= shmem_pread(page
, offset
, length
, user_data
,
985 page_to_phys(page
) & obj_do_bit17_swizzling
,
995 i915_gem_obj_finish_shmem_access(obj
);
1000 gtt_user_read(struct io_mapping
*mapping
,
1001 loff_t base
, int offset
,
1002 char __user
*user_data
, int length
)
1005 unsigned long unwritten
;
1007 /* We can use the cpu mem copy function because this is X86. */
1008 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
1009 unwritten
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
1010 io_mapping_unmap_atomic(vaddr
);
1012 vaddr
= (void __force
*)
1013 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1014 unwritten
= copy_to_user(user_data
, vaddr
+ offset
, length
);
1015 io_mapping_unmap(vaddr
);
1021 i915_gem_gtt_pread(struct drm_i915_gem_object
*obj
,
1022 const struct drm_i915_gem_pread
*args
)
1024 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1025 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1026 struct drm_mm_node node
;
1027 struct i915_vma
*vma
;
1028 void __user
*user_data
;
1032 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1036 intel_runtime_pm_get(i915
);
1037 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1038 PIN_MAPPABLE
| PIN_NONBLOCK
);
1040 node
.start
= i915_ggtt_offset(vma
);
1041 node
.allocated
= false;
1042 ret
= i915_vma_put_fence(vma
);
1044 i915_vma_unpin(vma
);
1049 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1052 GEM_BUG_ON(!node
.allocated
);
1055 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1059 mutex_unlock(&i915
->drm
.struct_mutex
);
1061 user_data
= u64_to_user_ptr(args
->data_ptr
);
1062 remain
= args
->size
;
1063 offset
= args
->offset
;
1065 while (remain
> 0) {
1066 /* Operation in this page
1068 * page_base = page offset within aperture
1069 * page_offset = offset within page
1070 * page_length = bytes to copy for this page
1072 u32 page_base
= node
.start
;
1073 unsigned page_offset
= offset_in_page(offset
);
1074 unsigned page_length
= PAGE_SIZE
- page_offset
;
1075 page_length
= remain
< page_length
? remain
: page_length
;
1076 if (node
.allocated
) {
1078 ggtt
->base
.insert_page(&ggtt
->base
,
1079 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1080 node
.start
, I915_CACHE_NONE
, 0);
1083 page_base
+= offset
& PAGE_MASK
;
1086 if (gtt_user_read(&ggtt
->mappable
, page_base
, page_offset
,
1087 user_data
, page_length
)) {
1092 remain
-= page_length
;
1093 user_data
+= page_length
;
1094 offset
+= page_length
;
1097 mutex_lock(&i915
->drm
.struct_mutex
);
1099 if (node
.allocated
) {
1101 ggtt
->base
.clear_range(&ggtt
->base
,
1102 node
.start
, node
.size
);
1103 remove_mappable_node(&node
);
1105 i915_vma_unpin(vma
);
1108 intel_runtime_pm_put(i915
);
1109 mutex_unlock(&i915
->drm
.struct_mutex
);
1115 * Reads data from the object referenced by handle.
1116 * @dev: drm device pointer
1117 * @data: ioctl data blob
1118 * @file: drm file pointer
1120 * On error, the contents of *data are undefined.
1123 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1124 struct drm_file
*file
)
1126 struct drm_i915_gem_pread
*args
= data
;
1127 struct drm_i915_gem_object
*obj
;
1130 if (args
->size
== 0)
1133 if (!access_ok(VERIFY_WRITE
,
1134 u64_to_user_ptr(args
->data_ptr
),
1138 obj
= i915_gem_object_lookup(file
, args
->handle
);
1142 /* Bounds check source. */
1143 if (args
->offset
> obj
->base
.size
||
1144 args
->size
> obj
->base
.size
- args
->offset
) {
1149 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
1151 ret
= i915_gem_object_wait(obj
,
1152 I915_WAIT_INTERRUPTIBLE
,
1153 MAX_SCHEDULE_TIMEOUT
,
1154 to_rps_client(file
));
1158 ret
= i915_gem_object_pin_pages(obj
);
1162 ret
= i915_gem_shmem_pread(obj
, args
);
1163 if (ret
== -EFAULT
|| ret
== -ENODEV
)
1164 ret
= i915_gem_gtt_pread(obj
, args
);
1166 i915_gem_object_unpin_pages(obj
);
1168 i915_gem_object_put(obj
);
1172 /* This is the fast write path which cannot handle
1173 * page faults in the source data
1177 ggtt_write(struct io_mapping
*mapping
,
1178 loff_t base
, int offset
,
1179 char __user
*user_data
, int length
)
1182 unsigned long unwritten
;
1184 /* We can use the cpu mem copy function because this is X86. */
1185 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
1186 unwritten
= __copy_from_user_inatomic_nocache(vaddr
+ offset
,
1188 io_mapping_unmap_atomic(vaddr
);
1190 vaddr
= (void __force
*)
1191 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1192 unwritten
= copy_from_user(vaddr
+ offset
, user_data
, length
);
1193 io_mapping_unmap(vaddr
);
1200 * This is the fast pwrite path, where we copy the data directly from the
1201 * user into the GTT, uncached.
1202 * @obj: i915 GEM object
1203 * @args: pwrite arguments structure
1206 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object
*obj
,
1207 const struct drm_i915_gem_pwrite
*args
)
1209 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1210 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1211 struct drm_mm_node node
;
1212 struct i915_vma
*vma
;
1214 void __user
*user_data
;
1217 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1221 intel_runtime_pm_get(i915
);
1222 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1223 PIN_MAPPABLE
| PIN_NONBLOCK
);
1225 node
.start
= i915_ggtt_offset(vma
);
1226 node
.allocated
= false;
1227 ret
= i915_vma_put_fence(vma
);
1229 i915_vma_unpin(vma
);
1234 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1237 GEM_BUG_ON(!node
.allocated
);
1240 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1244 mutex_unlock(&i915
->drm
.struct_mutex
);
1246 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1248 user_data
= u64_to_user_ptr(args
->data_ptr
);
1249 offset
= args
->offset
;
1250 remain
= args
->size
;
1252 /* Operation in this page
1254 * page_base = page offset within aperture
1255 * page_offset = offset within page
1256 * page_length = bytes to copy for this page
1258 u32 page_base
= node
.start
;
1259 unsigned int page_offset
= offset_in_page(offset
);
1260 unsigned int page_length
= PAGE_SIZE
- page_offset
;
1261 page_length
= remain
< page_length
? remain
: page_length
;
1262 if (node
.allocated
) {
1263 wmb(); /* flush the write before we modify the GGTT */
1264 ggtt
->base
.insert_page(&ggtt
->base
,
1265 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1266 node
.start
, I915_CACHE_NONE
, 0);
1267 wmb(); /* flush modifications to the GGTT (insert_page) */
1269 page_base
+= offset
& PAGE_MASK
;
1271 /* If we get a fault while copying data, then (presumably) our
1272 * source page isn't available. Return the error and we'll
1273 * retry in the slow path.
1274 * If the object is non-shmem backed, we retry again with the
1275 * path that handles page fault.
1277 if (ggtt_write(&ggtt
->mappable
, page_base
, page_offset
,
1278 user_data
, page_length
)) {
1283 remain
-= page_length
;
1284 user_data
+= page_length
;
1285 offset
+= page_length
;
1287 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1289 mutex_lock(&i915
->drm
.struct_mutex
);
1291 if (node
.allocated
) {
1293 ggtt
->base
.clear_range(&ggtt
->base
,
1294 node
.start
, node
.size
);
1295 remove_mappable_node(&node
);
1297 i915_vma_unpin(vma
);
1300 intel_runtime_pm_put(i915
);
1301 mutex_unlock(&i915
->drm
.struct_mutex
);
1306 shmem_pwrite_slow(struct page
*page
, int offset
, int length
,
1307 char __user
*user_data
,
1308 bool page_do_bit17_swizzling
,
1309 bool needs_clflush_before
,
1310 bool needs_clflush_after
)
1316 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1317 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1318 page_do_bit17_swizzling
);
1319 if (page_do_bit17_swizzling
)
1320 ret
= __copy_from_user_swizzled(vaddr
, offset
, user_data
,
1323 ret
= __copy_from_user(vaddr
+ offset
, user_data
, length
);
1324 if (needs_clflush_after
)
1325 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1326 page_do_bit17_swizzling
);
1329 return ret
? -EFAULT
: 0;
1332 /* Per-page copy function for the shmem pwrite fastpath.
1333 * Flushes invalid cachelines before writing to the target if
1334 * needs_clflush_before is set and flushes out any written cachelines after
1335 * writing if needs_clflush is set.
1338 shmem_pwrite(struct page
*page
, int offset
, int len
, char __user
*user_data
,
1339 bool page_do_bit17_swizzling
,
1340 bool needs_clflush_before
,
1341 bool needs_clflush_after
)
1346 if (!page_do_bit17_swizzling
) {
1347 char *vaddr
= kmap_atomic(page
);
1349 if (needs_clflush_before
)
1350 drm_clflush_virt_range(vaddr
+ offset
, len
);
1351 ret
= __copy_from_user_inatomic(vaddr
+ offset
, user_data
, len
);
1352 if (needs_clflush_after
)
1353 drm_clflush_virt_range(vaddr
+ offset
, len
);
1355 kunmap_atomic(vaddr
);
1360 return shmem_pwrite_slow(page
, offset
, len
, user_data
,
1361 page_do_bit17_swizzling
,
1362 needs_clflush_before
,
1363 needs_clflush_after
);
1367 i915_gem_shmem_pwrite(struct drm_i915_gem_object
*obj
,
1368 const struct drm_i915_gem_pwrite
*args
)
1370 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1371 void __user
*user_data
;
1373 unsigned int obj_do_bit17_swizzling
;
1374 unsigned int partial_cacheline_write
;
1375 unsigned int needs_clflush
;
1376 unsigned int offset
, idx
;
1379 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1383 ret
= i915_gem_obj_prepare_shmem_write(obj
, &needs_clflush
);
1384 mutex_unlock(&i915
->drm
.struct_mutex
);
1388 obj_do_bit17_swizzling
= 0;
1389 if (i915_gem_object_needs_bit17_swizzle(obj
))
1390 obj_do_bit17_swizzling
= BIT(17);
1392 /* If we don't overwrite a cacheline completely we need to be
1393 * careful to have up-to-date data by first clflushing. Don't
1394 * overcomplicate things and flush the entire patch.
1396 partial_cacheline_write
= 0;
1397 if (needs_clflush
& CLFLUSH_BEFORE
)
1398 partial_cacheline_write
= boot_cpu_data
.x86_clflush_size
- 1;
1400 user_data
= u64_to_user_ptr(args
->data_ptr
);
1401 remain
= args
->size
;
1402 offset
= offset_in_page(args
->offset
);
1403 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
1404 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
1408 if (offset
+ length
> PAGE_SIZE
)
1409 length
= PAGE_SIZE
- offset
;
1411 ret
= shmem_pwrite(page
, offset
, length
, user_data
,
1412 page_to_phys(page
) & obj_do_bit17_swizzling
,
1413 (offset
| length
) & partial_cacheline_write
,
1414 needs_clflush
& CLFLUSH_AFTER
);
1419 user_data
+= length
;
1423 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1424 i915_gem_obj_finish_shmem_access(obj
);
1429 * Writes data to the object referenced by handle.
1431 * @data: ioctl data blob
1434 * On error, the contents of the buffer that were to be modified are undefined.
1437 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1438 struct drm_file
*file
)
1440 struct drm_i915_gem_pwrite
*args
= data
;
1441 struct drm_i915_gem_object
*obj
;
1444 if (args
->size
== 0)
1447 if (!access_ok(VERIFY_READ
,
1448 u64_to_user_ptr(args
->data_ptr
),
1452 obj
= i915_gem_object_lookup(file
, args
->handle
);
1456 /* Bounds check destination. */
1457 if (args
->offset
> obj
->base
.size
||
1458 args
->size
> obj
->base
.size
- args
->offset
) {
1463 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1465 ret
= i915_gem_object_wait(obj
,
1466 I915_WAIT_INTERRUPTIBLE
|
1468 MAX_SCHEDULE_TIMEOUT
,
1469 to_rps_client(file
));
1473 ret
= i915_gem_object_pin_pages(obj
);
1478 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1479 * it would end up going through the fenced access, and we'll get
1480 * different detiling behavior between reading and writing.
1481 * pread/pwrite currently are reading and writing from the CPU
1482 * perspective, requiring manual detiling by the client.
1484 if (!i915_gem_object_has_struct_page(obj
) ||
1485 cpu_write_needs_clflush(obj
))
1486 /* Note that the gtt paths might fail with non-page-backed user
1487 * pointers (e.g. gtt mappings when moving data between
1488 * textures). Fallback to the shmem path in that case.
1490 ret
= i915_gem_gtt_pwrite_fast(obj
, args
);
1492 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1493 if (obj
->phys_handle
)
1494 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1496 ret
= i915_gem_shmem_pwrite(obj
, args
);
1499 i915_gem_object_unpin_pages(obj
);
1501 i915_gem_object_put(obj
);
1505 static inline enum fb_op_origin
1506 write_origin(struct drm_i915_gem_object
*obj
, unsigned domain
)
1508 return (domain
== I915_GEM_DOMAIN_GTT
?
1509 obj
->frontbuffer_ggtt_origin
: ORIGIN_CPU
);
1512 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object
*obj
)
1514 struct drm_i915_private
*i915
;
1515 struct list_head
*list
;
1516 struct i915_vma
*vma
;
1518 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
1519 if (!i915_vma_is_ggtt(vma
))
1522 if (i915_vma_is_active(vma
))
1525 if (!drm_mm_node_allocated(&vma
->node
))
1528 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
1531 i915
= to_i915(obj
->base
.dev
);
1532 list
= obj
->bind_count
? &i915
->mm
.bound_list
: &i915
->mm
.unbound_list
;
1533 list_move_tail(&obj
->global_link
, list
);
1537 * Called when user space prepares to use an object with the CPU, either
1538 * through the mmap ioctl's mapping or a GTT mapping.
1540 * @data: ioctl data blob
1544 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1545 struct drm_file
*file
)
1547 struct drm_i915_gem_set_domain
*args
= data
;
1548 struct drm_i915_gem_object
*obj
;
1549 uint32_t read_domains
= args
->read_domains
;
1550 uint32_t write_domain
= args
->write_domain
;
1553 /* Only handle setting domains to types used by the CPU. */
1554 if ((write_domain
| read_domains
) & I915_GEM_GPU_DOMAINS
)
1557 /* Having something in the write domain implies it's in the read
1558 * domain, and only that read domain. Enforce that in the request.
1560 if (write_domain
!= 0 && read_domains
!= write_domain
)
1563 obj
= i915_gem_object_lookup(file
, args
->handle
);
1567 /* Try to flush the object off the GPU without holding the lock.
1568 * We will repeat the flush holding the lock in the normal manner
1569 * to catch cases where we are gazumped.
1571 err
= i915_gem_object_wait(obj
,
1572 I915_WAIT_INTERRUPTIBLE
|
1573 (write_domain
? I915_WAIT_ALL
: 0),
1574 MAX_SCHEDULE_TIMEOUT
,
1575 to_rps_client(file
));
1579 /* Flush and acquire obj->pages so that we are coherent through
1580 * direct access in memory with previous cached writes through
1581 * shmemfs and that our cache domain tracking remains valid.
1582 * For example, if the obj->filp was moved to swap without us
1583 * being notified and releasing the pages, we would mistakenly
1584 * continue to assume that the obj remained out of the CPU cached
1587 err
= i915_gem_object_pin_pages(obj
);
1591 err
= i915_mutex_lock_interruptible(dev
);
1595 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1596 err
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1598 err
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1600 /* And bump the LRU for this access */
1601 i915_gem_object_bump_inactive_ggtt(obj
);
1603 mutex_unlock(&dev
->struct_mutex
);
1605 if (write_domain
!= 0)
1606 intel_fb_obj_invalidate(obj
, write_origin(obj
, write_domain
));
1609 i915_gem_object_unpin_pages(obj
);
1611 i915_gem_object_put(obj
);
1616 * Called when user space has done writes to this buffer
1618 * @data: ioctl data blob
1622 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1623 struct drm_file
*file
)
1625 struct drm_i915_gem_sw_finish
*args
= data
;
1626 struct drm_i915_gem_object
*obj
;
1629 obj
= i915_gem_object_lookup(file
, args
->handle
);
1633 /* Pinned buffers may be scanout, so flush the cache */
1634 if (READ_ONCE(obj
->pin_display
)) {
1635 err
= i915_mutex_lock_interruptible(dev
);
1637 i915_gem_object_flush_cpu_write_domain(obj
);
1638 mutex_unlock(&dev
->struct_mutex
);
1642 i915_gem_object_put(obj
);
1647 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1650 * @data: ioctl data blob
1653 * While the mapping holds a reference on the contents of the object, it doesn't
1654 * imply a ref on the object itself.
1658 * DRM driver writers who look a this function as an example for how to do GEM
1659 * mmap support, please don't implement mmap support like here. The modern way
1660 * to implement DRM mmap support is with an mmap offset ioctl (like
1661 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1662 * That way debug tooling like valgrind will understand what's going on, hiding
1663 * the mmap call in a driver private ioctl will break that. The i915 driver only
1664 * does cpu mmaps this way because we didn't know better.
1667 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1668 struct drm_file
*file
)
1670 struct drm_i915_gem_mmap
*args
= data
;
1671 struct drm_i915_gem_object
*obj
;
1674 if (args
->flags
& ~(I915_MMAP_WC
))
1677 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1680 obj
= i915_gem_object_lookup(file
, args
->handle
);
1684 /* prime objects have no backing filp to GEM mmap
1687 if (!obj
->base
.filp
) {
1688 i915_gem_object_put(obj
);
1692 addr
= vm_mmap(obj
->base
.filp
, 0, args
->size
,
1693 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1695 if (args
->flags
& I915_MMAP_WC
) {
1696 struct mm_struct
*mm
= current
->mm
;
1697 struct vm_area_struct
*vma
;
1699 if (down_write_killable(&mm
->mmap_sem
)) {
1700 i915_gem_object_put(obj
);
1703 vma
= find_vma(mm
, addr
);
1706 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1709 up_write(&mm
->mmap_sem
);
1711 /* This may race, but that's ok, it only gets set */
1712 WRITE_ONCE(obj
->frontbuffer_ggtt_origin
, ORIGIN_CPU
);
1714 i915_gem_object_put(obj
);
1715 if (IS_ERR((void *)addr
))
1718 args
->addr_ptr
= (uint64_t) addr
;
1723 static unsigned int tile_row_pages(struct drm_i915_gem_object
*obj
)
1727 size
= i915_gem_object_get_stride(obj
);
1728 size
*= i915_gem_object_get_tiling(obj
) == I915_TILING_Y
? 32 : 8;
1730 return size
>> PAGE_SHIFT
;
1734 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1736 * A history of the GTT mmap interface:
1738 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1739 * aligned and suitable for fencing, and still fit into the available
1740 * mappable space left by the pinned display objects. A classic problem
1741 * we called the page-fault-of-doom where we would ping-pong between
1742 * two objects that could not fit inside the GTT and so the memcpy
1743 * would page one object in at the expense of the other between every
1746 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1747 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1748 * object is too large for the available space (or simply too large
1749 * for the mappable aperture!), a view is created instead and faulted
1750 * into userspace. (This view is aligned and sized appropriately for
1755 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1756 * hangs on some architectures, corruption on others. An attempt to service
1757 * a GTT page fault from a snoopable object will generate a SIGBUS.
1759 * * the object must be able to fit into RAM (physical memory, though no
1760 * limited to the mappable aperture).
1765 * * a new GTT page fault will synchronize rendering from the GPU and flush
1766 * all data to system memory. Subsequent access will not be synchronized.
1768 * * all mappings are revoked on runtime device suspend.
1770 * * there are only 8, 16 or 32 fence registers to share between all users
1771 * (older machines require fence register for display and blitter access
1772 * as well). Contention of the fence registers will cause the previous users
1773 * to be unmapped and any new access will generate new page faults.
1775 * * running out of memory while servicing a fault may generate a SIGBUS,
1776 * rather than the expected SIGSEGV.
1778 int i915_gem_mmap_gtt_version(void)
1784 * i915_gem_fault - fault a page into the GTT
1785 * @area: CPU VMA in question
1788 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1789 * from userspace. The fault handler takes care of binding the object to
1790 * the GTT (if needed), allocating and programming a fence register (again,
1791 * only if needed based on whether the old reg is still valid or the object
1792 * is tiled) and inserting a new PTE into the faulting process.
1794 * Note that the faulting process may involve evicting existing objects
1795 * from the GTT and/or fence registers to make room. So performance may
1796 * suffer if the GTT working set is large or there are few fence registers
1799 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1800 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1802 int i915_gem_fault(struct vm_area_struct
*area
, struct vm_fault
*vmf
)
1804 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1805 struct drm_i915_gem_object
*obj
= to_intel_bo(area
->vm_private_data
);
1806 struct drm_device
*dev
= obj
->base
.dev
;
1807 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1808 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1809 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1810 struct i915_vma
*vma
;
1811 pgoff_t page_offset
;
1815 /* We don't use vmf->pgoff since that has the fake offset */
1816 page_offset
= (vmf
->address
- area
->vm_start
) >> PAGE_SHIFT
;
1818 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1820 /* Try to flush the object off the GPU first without holding the lock.
1821 * Upon acquiring the lock, we will perform our sanity checks and then
1822 * repeat the flush holding the lock in the normal manner to catch cases
1823 * where we are gazumped.
1825 ret
= i915_gem_object_wait(obj
,
1826 I915_WAIT_INTERRUPTIBLE
,
1827 MAX_SCHEDULE_TIMEOUT
,
1832 ret
= i915_gem_object_pin_pages(obj
);
1836 intel_runtime_pm_get(dev_priv
);
1838 ret
= i915_mutex_lock_interruptible(dev
);
1842 /* Access to snoopable pages through the GTT is incoherent. */
1843 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev_priv
)) {
1848 /* If the object is smaller than a couple of partial vma, it is
1849 * not worth only creating a single partial vma - we may as well
1850 * clear enough space for the full object.
1852 flags
= PIN_MAPPABLE
;
1853 if (obj
->base
.size
> 2 * MIN_CHUNK_PAGES
<< PAGE_SHIFT
)
1854 flags
|= PIN_NONBLOCK
| PIN_NONFAULT
;
1856 /* Now pin it into the GTT as needed */
1857 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, flags
);
1859 struct i915_ggtt_view view
;
1860 unsigned int chunk_size
;
1862 /* Use a partial view if it is bigger than available space */
1863 chunk_size
= MIN_CHUNK_PAGES
;
1864 if (i915_gem_object_is_tiled(obj
))
1865 chunk_size
= roundup(chunk_size
, tile_row_pages(obj
));
1867 memset(&view
, 0, sizeof(view
));
1868 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1869 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1870 view
.params
.partial
.size
=
1871 min_t(unsigned int, chunk_size
,
1872 vma_pages(area
) - view
.params
.partial
.offset
);
1874 /* If the partial covers the entire object, just create a
1877 if (chunk_size
>= obj
->base
.size
>> PAGE_SHIFT
)
1878 view
.type
= I915_GGTT_VIEW_NORMAL
;
1880 /* Userspace is now writing through an untracked VMA, abandon
1881 * all hope that the hardware is able to track future writes.
1883 obj
->frontbuffer_ggtt_origin
= ORIGIN_CPU
;
1885 vma
= i915_gem_object_ggtt_pin(obj
, &view
, 0, 0, PIN_MAPPABLE
);
1892 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1896 ret
= i915_vma_get_fence(vma
);
1900 /* Mark as being mmapped into userspace for later revocation */
1901 assert_rpm_wakelock_held(dev_priv
);
1902 if (list_empty(&obj
->userfault_link
))
1903 list_add(&obj
->userfault_link
, &dev_priv
->mm
.userfault_list
);
1905 /* Finally, remap it using the new GTT offset */
1906 ret
= remap_io_mapping(area
,
1907 area
->vm_start
+ (vma
->ggtt_view
.params
.partial
.offset
<< PAGE_SHIFT
),
1908 (ggtt
->mappable_base
+ vma
->node
.start
) >> PAGE_SHIFT
,
1909 min_t(u64
, vma
->size
, area
->vm_end
- area
->vm_start
),
1913 __i915_vma_unpin(vma
);
1915 mutex_unlock(&dev
->struct_mutex
);
1917 intel_runtime_pm_put(dev_priv
);
1918 i915_gem_object_unpin_pages(obj
);
1923 * We eat errors when the gpu is terminally wedged to avoid
1924 * userspace unduly crashing (gl has no provisions for mmaps to
1925 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1926 * and so needs to be reported.
1928 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1929 ret
= VM_FAULT_SIGBUS
;
1934 * EAGAIN means the gpu is hung and we'll wait for the error
1935 * handler to reset everything when re-faulting in
1936 * i915_mutex_lock_interruptible.
1943 * EBUSY is ok: this just means that another thread
1944 * already did the job.
1946 ret
= VM_FAULT_NOPAGE
;
1953 ret
= VM_FAULT_SIGBUS
;
1956 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1957 ret
= VM_FAULT_SIGBUS
;
1964 * i915_gem_release_mmap - remove physical page mappings
1965 * @obj: obj in question
1967 * Preserve the reservation of the mmapping with the DRM core code, but
1968 * relinquish ownership of the pages back to the system.
1970 * It is vital that we remove the page mapping if we have mapped a tiled
1971 * object through the GTT and then lose the fence register due to
1972 * resource pressure. Similarly if the object has been moved out of the
1973 * aperture, than pages mapped into userspace must be revoked. Removing the
1974 * mapping will then trigger a page fault on the next user access, allowing
1975 * fixup by i915_gem_fault().
1978 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1980 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1982 /* Serialisation between user GTT access and our code depends upon
1983 * revoking the CPU's PTE whilst the mutex is held. The next user
1984 * pagefault then has to wait until we release the mutex.
1986 * Note that RPM complicates somewhat by adding an additional
1987 * requirement that operations to the GGTT be made holding the RPM
1990 lockdep_assert_held(&i915
->drm
.struct_mutex
);
1991 intel_runtime_pm_get(i915
);
1993 if (list_empty(&obj
->userfault_link
))
1996 list_del_init(&obj
->userfault_link
);
1997 drm_vma_node_unmap(&obj
->base
.vma_node
,
1998 obj
->base
.dev
->anon_inode
->i_mapping
);
2000 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2001 * memory transactions from userspace before we return. The TLB
2002 * flushing implied above by changing the PTE above *should* be
2003 * sufficient, an extra barrier here just provides us with a bit
2004 * of paranoid documentation about our requirement to serialise
2005 * memory writes before touching registers / GSM.
2010 intel_runtime_pm_put(i915
);
2013 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
)
2015 struct drm_i915_gem_object
*obj
, *on
;
2019 * Only called during RPM suspend. All users of the userfault_list
2020 * must be holding an RPM wakeref to ensure that this can not
2021 * run concurrently with themselves (and use the struct_mutex for
2022 * protection between themselves).
2025 list_for_each_entry_safe(obj
, on
,
2026 &dev_priv
->mm
.userfault_list
, userfault_link
) {
2027 list_del_init(&obj
->userfault_link
);
2028 drm_vma_node_unmap(&obj
->base
.vma_node
,
2029 obj
->base
.dev
->anon_inode
->i_mapping
);
2032 /* The fence will be lost when the device powers down. If any were
2033 * in use by hardware (i.e. they are pinned), we should not be powering
2034 * down! All other fences will be reacquired by the user upon waking.
2036 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2037 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2039 if (WARN_ON(reg
->pin_count
))
2045 GEM_BUG_ON(!list_empty(®
->vma
->obj
->userfault_link
));
2051 * i915_gem_get_ggtt_size - return required global GTT size for an object
2052 * @dev_priv: i915 device
2053 * @size: object size
2054 * @tiling_mode: tiling mode
2056 * Return the required global GTT size for an object, taking into account
2057 * potential fence register mapping.
2059 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
,
2060 u64 size
, int tiling_mode
)
2064 GEM_BUG_ON(size
== 0);
2066 if (INTEL_GEN(dev_priv
) >= 4 ||
2067 tiling_mode
== I915_TILING_NONE
)
2070 /* Previous chips need a power-of-two fence region when tiling */
2071 if (IS_GEN3(dev_priv
))
2072 ggtt_size
= 1024*1024;
2074 ggtt_size
= 512*1024;
2076 while (ggtt_size
< size
)
2083 * i915_gem_get_ggtt_alignment - return required global GTT alignment
2084 * @dev_priv: i915 device
2085 * @size: object size
2086 * @tiling_mode: tiling mode
2087 * @fenced: is fenced alignment required or not
2089 * Return the required global GTT alignment for an object, taking into account
2090 * potential fence register mapping.
2092 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
2093 int tiling_mode
, bool fenced
)
2095 GEM_BUG_ON(size
== 0);
2098 * Minimum alignment is 4k (GTT page size), but might be greater
2099 * if a fence register is needed for the object.
2101 if (INTEL_GEN(dev_priv
) >= 4 || (!fenced
&& IS_G33(dev_priv
)) ||
2102 tiling_mode
== I915_TILING_NONE
)
2106 * Previous chips need to be aligned to the size of the smallest
2107 * fence register that can contain the object.
2109 return i915_gem_get_ggtt_size(dev_priv
, size
, tiling_mode
);
2112 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2114 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2117 err
= drm_gem_create_mmap_offset(&obj
->base
);
2121 /* We can idle the GPU locklessly to flush stale objects, but in order
2122 * to claim that space for ourselves, we need to take the big
2123 * struct_mutex to free the requests+objects and allocate our slot.
2125 err
= i915_gem_wait_for_idle(dev_priv
, I915_WAIT_INTERRUPTIBLE
);
2129 err
= i915_mutex_lock_interruptible(&dev_priv
->drm
);
2131 i915_gem_retire_requests(dev_priv
);
2132 err
= drm_gem_create_mmap_offset(&obj
->base
);
2133 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2139 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2141 drm_gem_free_mmap_offset(&obj
->base
);
2145 i915_gem_mmap_gtt(struct drm_file
*file
,
2146 struct drm_device
*dev
,
2150 struct drm_i915_gem_object
*obj
;
2153 obj
= i915_gem_object_lookup(file
, handle
);
2157 ret
= i915_gem_object_create_mmap_offset(obj
);
2159 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2161 i915_gem_object_put(obj
);
2166 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2168 * @data: GTT mapping ioctl data
2169 * @file: GEM object info
2171 * Simply returns the fake offset to userspace so it can mmap it.
2172 * The mmap call will end up in drm_gem_mmap(), which will set things
2173 * up so we can get faults in the handler above.
2175 * The fault handler will take care of binding the object into the GTT
2176 * (since it may have been evicted to make room for something), allocating
2177 * a fence register, and mapping the appropriate aperture address into
2181 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2182 struct drm_file
*file
)
2184 struct drm_i915_gem_mmap_gtt
*args
= data
;
2186 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2189 /* Immediately discard the backing storage */
2191 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2193 i915_gem_object_free_mmap_offset(obj
);
2195 if (obj
->base
.filp
== NULL
)
2198 /* Our goal here is to return as much of the memory as
2199 * is possible back to the system as we are called from OOM.
2200 * To do this we must instruct the shmfs to drop all of its
2201 * backing pages, *now*.
2203 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2204 obj
->mm
.madv
= __I915_MADV_PURGED
;
2207 /* Try to discard unwanted pages */
2208 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2210 struct address_space
*mapping
;
2212 lockdep_assert_held(&obj
->mm
.lock
);
2213 GEM_BUG_ON(obj
->mm
.pages
);
2215 switch (obj
->mm
.madv
) {
2216 case I915_MADV_DONTNEED
:
2217 i915_gem_object_truncate(obj
);
2218 case __I915_MADV_PURGED
:
2222 if (obj
->base
.filp
== NULL
)
2225 mapping
= obj
->base
.filp
->f_mapping
,
2226 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2230 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
,
2231 struct sg_table
*pages
)
2233 struct sgt_iter sgt_iter
;
2236 __i915_gem_object_release_shmem(obj
, pages
, true);
2238 i915_gem_gtt_finish_pages(obj
, pages
);
2240 if (i915_gem_object_needs_bit17_swizzle(obj
))
2241 i915_gem_object_save_bit_17_swizzle(obj
, pages
);
2243 for_each_sgt_page(page
, sgt_iter
, pages
) {
2245 set_page_dirty(page
);
2247 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
2248 mark_page_accessed(page
);
2252 obj
->mm
.dirty
= false;
2254 sg_free_table(pages
);
2258 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object
*obj
)
2260 struct radix_tree_iter iter
;
2263 radix_tree_for_each_slot(slot
, &obj
->mm
.get_page
.radix
, &iter
, 0)
2264 radix_tree_delete(&obj
->mm
.get_page
.radix
, iter
.index
);
2267 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
2268 enum i915_mm_subclass subclass
)
2270 struct sg_table
*pages
;
2272 if (i915_gem_object_has_pinned_pages(obj
))
2275 GEM_BUG_ON(obj
->bind_count
);
2276 if (!READ_ONCE(obj
->mm
.pages
))
2279 /* May be called by shrinker from within get_pages() (on another bo) */
2280 mutex_lock_nested(&obj
->mm
.lock
, subclass
);
2281 if (unlikely(atomic_read(&obj
->mm
.pages_pin_count
)))
2284 /* ->put_pages might need to allocate memory for the bit17 swizzle
2285 * array, hence protect them from being reaped by removing them from gtt
2287 pages
= fetch_and_zero(&obj
->mm
.pages
);
2290 if (obj
->mm
.mapping
) {
2293 ptr
= ptr_mask_bits(obj
->mm
.mapping
);
2294 if (is_vmalloc_addr(ptr
))
2297 kunmap(kmap_to_page(ptr
));
2299 obj
->mm
.mapping
= NULL
;
2302 __i915_gem_object_reset_page_iter(obj
);
2304 obj
->ops
->put_pages(obj
, pages
);
2306 mutex_unlock(&obj
->mm
.lock
);
2309 static unsigned int swiotlb_max_size(void)
2311 #if IS_ENABLED(CONFIG_SWIOTLB)
2312 return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT
, PAGE_SIZE
);
2318 static void i915_sg_trim(struct sg_table
*orig_st
)
2320 struct sg_table new_st
;
2321 struct scatterlist
*sg
, *new_sg
;
2324 if (orig_st
->nents
== orig_st
->orig_nents
)
2327 if (sg_alloc_table(&new_st
, orig_st
->nents
, GFP_KERNEL
| __GFP_NOWARN
))
2330 new_sg
= new_st
.sgl
;
2331 for_each_sg(orig_st
->sgl
, sg
, orig_st
->nents
, i
) {
2332 sg_set_page(new_sg
, sg_page(sg
), sg
->length
, 0);
2333 /* called before being DMA mapped, no need to copy sg->dma_* */
2334 new_sg
= sg_next(new_sg
);
2337 sg_free_table(orig_st
);
2342 static struct sg_table
*
2343 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2345 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2346 const unsigned long page_count
= obj
->base
.size
/ PAGE_SIZE
;
2348 struct address_space
*mapping
;
2349 struct sg_table
*st
;
2350 struct scatterlist
*sg
;
2351 struct sgt_iter sgt_iter
;
2353 unsigned long last_pfn
= 0; /* suppress gcc warning */
2354 unsigned int max_segment
;
2358 /* Assert that the object is not currently in any GPU domain. As it
2359 * wasn't in the GTT, there shouldn't be any way it could have been in
2362 GEM_BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2363 GEM_BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2365 max_segment
= swiotlb_max_size();
2367 max_segment
= rounddown(UINT_MAX
, PAGE_SIZE
);
2369 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2371 return ERR_PTR(-ENOMEM
);
2374 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2376 return ERR_PTR(-ENOMEM
);
2379 /* Get the list of pages out of our struct file. They'll be pinned
2380 * at this point until we release them.
2382 * Fail silently without starting the shrinker
2384 mapping
= obj
->base
.filp
->f_mapping
;
2385 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2386 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2389 for (i
= 0; i
< page_count
; i
++) {
2390 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2392 i915_gem_shrink(dev_priv
,
2395 I915_SHRINK_UNBOUND
|
2396 I915_SHRINK_PURGEABLE
);
2397 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2400 /* We've tried hard to allocate the memory by reaping
2401 * our own buffer, now let the real VM do its job and
2402 * go down in flames if truly OOM.
2404 page
= shmem_read_mapping_page(mapping
, i
);
2406 ret
= PTR_ERR(page
);
2411 sg
->length
>= max_segment
||
2412 page_to_pfn(page
) != last_pfn
+ 1) {
2416 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2418 sg
->length
+= PAGE_SIZE
;
2420 last_pfn
= page_to_pfn(page
);
2422 /* Check that the i965g/gm workaround works. */
2423 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2425 if (sg
) /* loop terminated early; short sg table */
2428 /* Trim unused sg entries to avoid wasting memory. */
2431 ret
= i915_gem_gtt_prepare_pages(obj
, st
);
2433 /* DMA remapping failed? One possible cause is that
2434 * it could not reserve enough large entries, asking
2435 * for PAGE_SIZE chunks instead may be helpful.
2437 if (max_segment
> PAGE_SIZE
) {
2438 for_each_sgt_page(page
, sgt_iter
, st
)
2442 max_segment
= PAGE_SIZE
;
2445 dev_warn(&dev_priv
->drm
.pdev
->dev
,
2446 "Failed to DMA remap %lu pages\n",
2452 if (i915_gem_object_needs_bit17_swizzle(obj
))
2453 i915_gem_object_do_bit_17_swizzle(obj
, st
);
2460 for_each_sgt_page(page
, sgt_iter
, st
)
2465 /* shmemfs first checks if there is enough memory to allocate the page
2466 * and reports ENOSPC should there be insufficient, along with the usual
2467 * ENOMEM for a genuine allocation failure.
2469 * We use ENOSPC in our driver to mean that we have run out of aperture
2470 * space and so want to translate the error from shmemfs back to our
2471 * usual understanding of ENOMEM.
2476 return ERR_PTR(ret
);
2479 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2480 struct sg_table
*pages
)
2482 lockdep_assert_held(&obj
->mm
.lock
);
2484 obj
->mm
.get_page
.sg_pos
= pages
->sgl
;
2485 obj
->mm
.get_page
.sg_idx
= 0;
2487 obj
->mm
.pages
= pages
;
2489 if (i915_gem_object_is_tiled(obj
) &&
2490 to_i915(obj
->base
.dev
)->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
2491 GEM_BUG_ON(obj
->mm
.quirked
);
2492 __i915_gem_object_pin_pages(obj
);
2493 obj
->mm
.quirked
= true;
2497 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2499 struct sg_table
*pages
;
2501 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj
));
2503 if (unlikely(obj
->mm
.madv
!= I915_MADV_WILLNEED
)) {
2504 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2508 pages
= obj
->ops
->get_pages(obj
);
2509 if (unlikely(IS_ERR(pages
)))
2510 return PTR_ERR(pages
);
2512 __i915_gem_object_set_pages(obj
, pages
);
2516 /* Ensure that the associated pages are gathered from the backing storage
2517 * and pinned into our object. i915_gem_object_pin_pages() may be called
2518 * multiple times before they are released by a single call to
2519 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2520 * either as a result of memory pressure (reaping pages under the shrinker)
2521 * or as the object is itself released.
2523 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2527 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
2531 if (unlikely(!obj
->mm
.pages
)) {
2532 err
= ____i915_gem_object_get_pages(obj
);
2536 smp_mb__before_atomic();
2538 atomic_inc(&obj
->mm
.pages_pin_count
);
2541 mutex_unlock(&obj
->mm
.lock
);
2545 /* The 'mapping' part of i915_gem_object_pin_map() below */
2546 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
,
2547 enum i915_map_type type
)
2549 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2550 struct sg_table
*sgt
= obj
->mm
.pages
;
2551 struct sgt_iter sgt_iter
;
2553 struct page
*stack_pages
[32];
2554 struct page
**pages
= stack_pages
;
2555 unsigned long i
= 0;
2559 /* A single page can always be kmapped */
2560 if (n_pages
== 1 && type
== I915_MAP_WB
)
2561 return kmap(sg_page(sgt
->sgl
));
2563 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2564 /* Too big for stack -- allocate temporary array instead */
2565 pages
= drm_malloc_gfp(n_pages
, sizeof(*pages
), GFP_TEMPORARY
);
2570 for_each_sgt_page(page
, sgt_iter
, sgt
)
2573 /* Check that we have the expected number of pages */
2574 GEM_BUG_ON(i
!= n_pages
);
2578 pgprot
= PAGE_KERNEL
;
2581 pgprot
= pgprot_writecombine(PAGE_KERNEL_IO
);
2584 addr
= vmap(pages
, n_pages
, 0, pgprot
);
2586 if (pages
!= stack_pages
)
2587 drm_free_large(pages
);
2592 /* get, pin, and map the pages of the object into kernel space */
2593 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
2594 enum i915_map_type type
)
2596 enum i915_map_type has_type
;
2601 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
2603 ret
= mutex_lock_interruptible(&obj
->mm
.lock
);
2605 return ERR_PTR(ret
);
2608 if (!atomic_inc_not_zero(&obj
->mm
.pages_pin_count
)) {
2609 if (unlikely(!obj
->mm
.pages
)) {
2610 ret
= ____i915_gem_object_get_pages(obj
);
2614 smp_mb__before_atomic();
2616 atomic_inc(&obj
->mm
.pages_pin_count
);
2619 GEM_BUG_ON(!obj
->mm
.pages
);
2621 ptr
= ptr_unpack_bits(obj
->mm
.mapping
, has_type
);
2622 if (ptr
&& has_type
!= type
) {
2628 if (is_vmalloc_addr(ptr
))
2631 kunmap(kmap_to_page(ptr
));
2633 ptr
= obj
->mm
.mapping
= NULL
;
2637 ptr
= i915_gem_object_map(obj
, type
);
2643 obj
->mm
.mapping
= ptr_pack_bits(ptr
, type
);
2647 mutex_unlock(&obj
->mm
.lock
);
2651 atomic_dec(&obj
->mm
.pages_pin_count
);
2657 static bool i915_context_is_banned(const struct i915_gem_context
*ctx
)
2659 unsigned long elapsed
;
2661 if (ctx
->hang_stats
.banned
)
2664 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2665 if (ctx
->hang_stats
.ban_period_seconds
&&
2666 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2667 DRM_DEBUG("context hanging too fast, banning!\n");
2674 static void i915_set_reset_status(struct i915_gem_context
*ctx
,
2677 struct i915_ctx_hang_stats
*hs
= &ctx
->hang_stats
;
2680 hs
->banned
= i915_context_is_banned(ctx
);
2682 hs
->guilty_ts
= get_seconds();
2684 hs
->batch_pending
++;
2688 struct drm_i915_gem_request
*
2689 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2691 struct drm_i915_gem_request
*request
;
2693 /* We are called by the error capture and reset at a random
2694 * point in time. In particular, note that neither is crucially
2695 * ordered with an interrupt. After a hang, the GPU is dead and we
2696 * assume that no more writes can happen (we waited long enough for
2697 * all writes that were in transaction to be flushed) - adding an
2698 * extra delay for a recent interrupt is pointless. Hence, we do
2699 * not need an engine->irq_seqno_barrier() before the seqno reads.
2701 list_for_each_entry(request
, &engine
->timeline
->requests
, link
) {
2702 if (__i915_gem_request_completed(request
))
2711 static void reset_request(struct drm_i915_gem_request
*request
)
2713 void *vaddr
= request
->ring
->vaddr
;
2716 /* As this request likely depends on state from the lost
2717 * context, clear out all the user operations leaving the
2718 * breadcrumb at the end (so we get the fence notifications).
2720 head
= request
->head
;
2721 if (request
->postfix
< head
) {
2722 memset(vaddr
+ head
, 0, request
->ring
->size
- head
);
2725 memset(vaddr
+ head
, 0, request
->postfix
- head
);
2728 static void i915_gem_reset_engine(struct intel_engine_cs
*engine
)
2730 struct drm_i915_gem_request
*request
;
2731 struct i915_gem_context
*incomplete_ctx
;
2732 struct intel_timeline
*timeline
;
2733 unsigned long flags
;
2736 if (engine
->irq_seqno_barrier
)
2737 engine
->irq_seqno_barrier(engine
);
2739 request
= i915_gem_find_active_request(engine
);
2743 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2744 if (engine
->hangcheck
.seqno
!= intel_engine_get_seqno(engine
))
2747 i915_set_reset_status(request
->ctx
, ring_hung
);
2751 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2752 engine
->name
, request
->global_seqno
);
2754 /* Setup the CS to resume from the breadcrumb of the hung request */
2755 engine
->reset_hw(engine
, request
);
2757 /* Users of the default context do not rely on logical state
2758 * preserved between batches. They have to emit full state on
2759 * every batch and so it is safe to execute queued requests following
2762 * Other contexts preserve state, now corrupt. We want to skip all
2763 * queued requests that reference the corrupt context.
2765 incomplete_ctx
= request
->ctx
;
2766 if (i915_gem_context_is_default(incomplete_ctx
))
2769 timeline
= i915_gem_context_lookup_timeline(incomplete_ctx
, engine
);
2771 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2772 spin_lock(&timeline
->lock
);
2774 list_for_each_entry_continue(request
, &engine
->timeline
->requests
, link
)
2775 if (request
->ctx
== incomplete_ctx
)
2776 reset_request(request
);
2778 list_for_each_entry(request
, &timeline
->requests
, link
)
2779 reset_request(request
);
2781 spin_unlock(&timeline
->lock
);
2782 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2785 void i915_gem_reset(struct drm_i915_private
*dev_priv
)
2787 struct intel_engine_cs
*engine
;
2788 enum intel_engine_id id
;
2790 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2792 i915_gem_retire_requests(dev_priv
);
2794 for_each_engine(engine
, dev_priv
, id
)
2795 i915_gem_reset_engine(engine
);
2797 i915_gem_restore_fences(dev_priv
);
2799 if (dev_priv
->gt
.awake
) {
2800 intel_sanitize_gt_powersave(dev_priv
);
2801 intel_enable_gt_powersave(dev_priv
);
2802 if (INTEL_GEN(dev_priv
) >= 6)
2803 gen6_rps_busy(dev_priv
);
2807 static void nop_submit_request(struct drm_i915_gem_request
*request
)
2809 i915_gem_request_submit(request
);
2810 intel_engine_init_global_seqno(request
->engine
, request
->global_seqno
);
2813 static void i915_gem_cleanup_engine(struct intel_engine_cs
*engine
)
2815 engine
->submit_request
= nop_submit_request
;
2817 /* Mark all pending requests as complete so that any concurrent
2818 * (lockless) lookup doesn't try and wait upon the request as we
2821 intel_engine_init_global_seqno(engine
,
2822 intel_engine_last_submit(engine
));
2825 * Clear the execlists queue up before freeing the requests, as those
2826 * are the ones that keep the context and ringbuffer backing objects
2830 if (i915
.enable_execlists
) {
2831 unsigned long flags
;
2833 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2835 i915_gem_request_put(engine
->execlist_port
[0].request
);
2836 i915_gem_request_put(engine
->execlist_port
[1].request
);
2837 memset(engine
->execlist_port
, 0, sizeof(engine
->execlist_port
));
2838 engine
->execlist_queue
= RB_ROOT
;
2839 engine
->execlist_first
= NULL
;
2841 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2845 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
)
2847 struct intel_engine_cs
*engine
;
2848 enum intel_engine_id id
;
2850 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2851 set_bit(I915_WEDGED
, &dev_priv
->gpu_error
.flags
);
2853 i915_gem_context_lost(dev_priv
);
2854 for_each_engine(engine
, dev_priv
, id
)
2855 i915_gem_cleanup_engine(engine
);
2856 mod_delayed_work(dev_priv
->wq
, &dev_priv
->gt
.idle_work
, 0);
2858 i915_gem_retire_requests(dev_priv
);
2862 i915_gem_retire_work_handler(struct work_struct
*work
)
2864 struct drm_i915_private
*dev_priv
=
2865 container_of(work
, typeof(*dev_priv
), gt
.retire_work
.work
);
2866 struct drm_device
*dev
= &dev_priv
->drm
;
2868 /* Come back later if the device is busy... */
2869 if (mutex_trylock(&dev
->struct_mutex
)) {
2870 i915_gem_retire_requests(dev_priv
);
2871 mutex_unlock(&dev
->struct_mutex
);
2874 /* Keep the retire handler running until we are finally idle.
2875 * We do not need to do this test under locking as in the worst-case
2876 * we queue the retire worker once too often.
2878 if (READ_ONCE(dev_priv
->gt
.awake
)) {
2879 i915_queue_hangcheck(dev_priv
);
2880 queue_delayed_work(dev_priv
->wq
,
2881 &dev_priv
->gt
.retire_work
,
2882 round_jiffies_up_relative(HZ
));
2887 i915_gem_idle_work_handler(struct work_struct
*work
)
2889 struct drm_i915_private
*dev_priv
=
2890 container_of(work
, typeof(*dev_priv
), gt
.idle_work
.work
);
2891 struct drm_device
*dev
= &dev_priv
->drm
;
2892 struct intel_engine_cs
*engine
;
2893 enum intel_engine_id id
;
2894 bool rearm_hangcheck
;
2896 if (!READ_ONCE(dev_priv
->gt
.awake
))
2900 * Wait for last execlists context complete, but bail out in case a
2901 * new request is submitted.
2903 wait_for(READ_ONCE(dev_priv
->gt
.active_requests
) ||
2904 intel_execlists_idle(dev_priv
), 10);
2906 if (READ_ONCE(dev_priv
->gt
.active_requests
))
2910 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
2912 if (!mutex_trylock(&dev
->struct_mutex
)) {
2913 /* Currently busy, come back later */
2914 mod_delayed_work(dev_priv
->wq
,
2915 &dev_priv
->gt
.idle_work
,
2916 msecs_to_jiffies(50));
2921 * New request retired after this work handler started, extend active
2922 * period until next instance of the work.
2924 if (work_pending(work
))
2927 if (dev_priv
->gt
.active_requests
)
2930 if (wait_for(intel_execlists_idle(dev_priv
), 10))
2931 DRM_ERROR("Timeout waiting for engines to idle\n");
2933 for_each_engine(engine
, dev_priv
, id
)
2934 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2936 GEM_BUG_ON(!dev_priv
->gt
.awake
);
2937 dev_priv
->gt
.awake
= false;
2938 rearm_hangcheck
= false;
2940 if (INTEL_GEN(dev_priv
) >= 6)
2941 gen6_rps_idle(dev_priv
);
2942 intel_runtime_pm_put(dev_priv
);
2944 mutex_unlock(&dev
->struct_mutex
);
2947 if (rearm_hangcheck
) {
2948 GEM_BUG_ON(!dev_priv
->gt
.awake
);
2949 i915_queue_hangcheck(dev_priv
);
2953 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
)
2955 struct drm_i915_gem_object
*obj
= to_intel_bo(gem
);
2956 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
2957 struct i915_vma
*vma
, *vn
;
2959 mutex_lock(&obj
->base
.dev
->struct_mutex
);
2960 list_for_each_entry_safe(vma
, vn
, &obj
->vma_list
, obj_link
)
2961 if (vma
->vm
->file
== fpriv
)
2962 i915_vma_close(vma
);
2964 if (i915_gem_object_is_active(obj
) &&
2965 !i915_gem_object_has_active_reference(obj
)) {
2966 i915_gem_object_set_active_reference(obj
);
2967 i915_gem_object_get(obj
);
2969 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
2972 static unsigned long to_wait_timeout(s64 timeout_ns
)
2975 return MAX_SCHEDULE_TIMEOUT
;
2977 if (timeout_ns
== 0)
2980 return nsecs_to_jiffies_timeout(timeout_ns
);
2984 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2985 * @dev: drm device pointer
2986 * @data: ioctl data blob
2987 * @file: drm file pointer
2989 * Returns 0 if successful, else an error is returned with the remaining time in
2990 * the timeout parameter.
2991 * -ETIME: object is still busy after timeout
2992 * -ERESTARTSYS: signal interrupted the wait
2993 * -ENONENT: object doesn't exist
2994 * Also possible, but rare:
2995 * -EAGAIN: GPU wedged
2997 * -ENODEV: Internal IRQ fail
2998 * -E?: The add request failed
3000 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3001 * non-zero timeout parameter the wait ioctl will wait for the given number of
3002 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3003 * without holding struct_mutex the object may become re-busied before this
3004 * function completes. A similar but shorter * race condition exists in the busy
3008 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3010 struct drm_i915_gem_wait
*args
= data
;
3011 struct drm_i915_gem_object
*obj
;
3015 if (args
->flags
!= 0)
3018 obj
= i915_gem_object_lookup(file
, args
->bo_handle
);
3022 start
= ktime_get();
3024 ret
= i915_gem_object_wait(obj
,
3025 I915_WAIT_INTERRUPTIBLE
| I915_WAIT_ALL
,
3026 to_wait_timeout(args
->timeout_ns
),
3027 to_rps_client(file
));
3029 if (args
->timeout_ns
> 0) {
3030 args
->timeout_ns
-= ktime_to_ns(ktime_sub(ktime_get(), start
));
3031 if (args
->timeout_ns
< 0)
3032 args
->timeout_ns
= 0;
3035 i915_gem_object_put(obj
);
3039 static int wait_for_timeline(struct i915_gem_timeline
*tl
, unsigned int flags
)
3043 for (i
= 0; i
< ARRAY_SIZE(tl
->engine
); i
++) {
3044 ret
= i915_gem_active_wait(&tl
->engine
[i
].last_request
, flags
);
3052 int i915_gem_wait_for_idle(struct drm_i915_private
*i915
, unsigned int flags
)
3056 if (flags
& I915_WAIT_LOCKED
) {
3057 struct i915_gem_timeline
*tl
;
3059 lockdep_assert_held(&i915
->drm
.struct_mutex
);
3061 list_for_each_entry(tl
, &i915
->gt
.timelines
, link
) {
3062 ret
= wait_for_timeline(tl
, flags
);
3067 ret
= wait_for_timeline(&i915
->gt
.global_timeline
, flags
);
3075 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3078 /* If we don't have a page list set up, then we're not pinned
3079 * to GPU, and we can ignore the cache flush because it'll happen
3080 * again at bind time.
3086 * Stolen memory is always coherent with the GPU as it is explicitly
3087 * marked as wc by the system, or the system is cache-coherent.
3089 if (obj
->stolen
|| obj
->phys_handle
)
3092 /* If the GPU is snooping the contents of the CPU cache,
3093 * we do not need to manually clear the CPU cache lines. However,
3094 * the caches are only snooped when the render cache is
3095 * flushed/invalidated. As we always have to emit invalidations
3096 * and flushes when moving into and out of the RENDER domain, correct
3097 * snooping behaviour occurs naturally as the result of our domain
3100 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3101 obj
->cache_dirty
= true;
3105 trace_i915_gem_object_clflush(obj
);
3106 drm_clflush_sg(obj
->mm
.pages
);
3107 obj
->cache_dirty
= false;
3110 /** Flushes the GTT write domain for the object if it's dirty. */
3112 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3114 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3116 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3119 /* No actual flushing is required for the GTT write domain. Writes
3120 * to it "immediately" go to main memory as far as we know, so there's
3121 * no chipset flush. It also doesn't land in render cache.
3123 * However, we do have to enforce the order so that all writes through
3124 * the GTT land before any writes to the device, such as updates to
3127 * We also have to wait a bit for the writes to land from the GTT.
3128 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3129 * timing. This issue has only been observed when switching quickly
3130 * between GTT writes and CPU reads from inside the kernel on recent hw,
3131 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3132 * system agents we cannot reproduce this behaviour).
3135 if (INTEL_GEN(dev_priv
) >= 6 && !HAS_LLC(dev_priv
))
3136 POSTING_READ(RING_ACTHD(dev_priv
->engine
[RCS
]->mmio_base
));
3138 intel_fb_obj_flush(obj
, false, write_origin(obj
, I915_GEM_DOMAIN_GTT
));
3140 obj
->base
.write_domain
= 0;
3141 trace_i915_gem_object_change_domain(obj
,
3142 obj
->base
.read_domains
,
3143 I915_GEM_DOMAIN_GTT
);
3146 /** Flushes the CPU write domain for the object if it's dirty. */
3148 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3150 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3153 i915_gem_clflush_object(obj
, obj
->pin_display
);
3154 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3156 obj
->base
.write_domain
= 0;
3157 trace_i915_gem_object_change_domain(obj
,
3158 obj
->base
.read_domains
,
3159 I915_GEM_DOMAIN_CPU
);
3163 * Moves a single object to the GTT read, and possibly write domain.
3164 * @obj: object to act on
3165 * @write: ask for write access or read only
3167 * This function returns when the move is complete, including waiting on
3171 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3173 uint32_t old_write_domain
, old_read_domains
;
3176 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3178 ret
= i915_gem_object_wait(obj
,
3179 I915_WAIT_INTERRUPTIBLE
|
3181 (write
? I915_WAIT_ALL
: 0),
3182 MAX_SCHEDULE_TIMEOUT
,
3187 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3190 /* Flush and acquire obj->pages so that we are coherent through
3191 * direct access in memory with previous cached writes through
3192 * shmemfs and that our cache domain tracking remains valid.
3193 * For example, if the obj->filp was moved to swap without us
3194 * being notified and releasing the pages, we would mistakenly
3195 * continue to assume that the obj remained out of the CPU cached
3198 ret
= i915_gem_object_pin_pages(obj
);
3202 i915_gem_object_flush_cpu_write_domain(obj
);
3204 /* Serialise direct access to this object with the barriers for
3205 * coherent writes from the GPU, by effectively invalidating the
3206 * GTT domain upon first access.
3208 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3211 old_write_domain
= obj
->base
.write_domain
;
3212 old_read_domains
= obj
->base
.read_domains
;
3214 /* It should now be out of any other write domains, and we can update
3215 * the domain values for our changes.
3217 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3218 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3220 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3221 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3222 obj
->mm
.dirty
= true;
3225 trace_i915_gem_object_change_domain(obj
,
3229 i915_gem_object_unpin_pages(obj
);
3234 * Changes the cache-level of an object across all VMA.
3235 * @obj: object to act on
3236 * @cache_level: new cache level to set for the object
3238 * After this function returns, the object will be in the new cache-level
3239 * across all GTT and the contents of the backing storage will be coherent,
3240 * with respect to the new cache-level. In order to keep the backing storage
3241 * coherent for all users, we only allow a single cache level to be set
3242 * globally on the object and prevent it from being changed whilst the
3243 * hardware is reading from the object. That is if the object is currently
3244 * on the scanout it will be set to uncached (or equivalent display
3245 * cache coherency) and all non-MOCS GPU access will also be uncached so
3246 * that all direct access to the scanout remains coherent.
3248 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3249 enum i915_cache_level cache_level
)
3251 struct i915_vma
*vma
;
3254 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3256 if (obj
->cache_level
== cache_level
)
3259 /* Inspect the list of currently bound VMA and unbind any that would
3260 * be invalid given the new cache-level. This is principally to
3261 * catch the issue of the CS prefetch crossing page boundaries and
3262 * reading an invalid PTE on older architectures.
3265 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3266 if (!drm_mm_node_allocated(&vma
->node
))
3269 if (i915_vma_is_pinned(vma
)) {
3270 DRM_DEBUG("can not change the cache level of pinned objects\n");
3274 if (i915_gem_valid_gtt_space(vma
, cache_level
))
3277 ret
= i915_vma_unbind(vma
);
3281 /* As unbinding may affect other elements in the
3282 * obj->vma_list (due to side-effects from retiring
3283 * an active vma), play safe and restart the iterator.
3288 /* We can reuse the existing drm_mm nodes but need to change the
3289 * cache-level on the PTE. We could simply unbind them all and
3290 * rebind with the correct cache-level on next use. However since
3291 * we already have a valid slot, dma mapping, pages etc, we may as
3292 * rewrite the PTE in the belief that doing so tramples upon less
3293 * state and so involves less work.
3295 if (obj
->bind_count
) {
3296 /* Before we change the PTE, the GPU must not be accessing it.
3297 * If we wait upon the object, we know that all the bound
3298 * VMA are no longer active.
3300 ret
= i915_gem_object_wait(obj
,
3301 I915_WAIT_INTERRUPTIBLE
|
3304 MAX_SCHEDULE_TIMEOUT
,
3309 if (!HAS_LLC(to_i915(obj
->base
.dev
)) &&
3310 cache_level
!= I915_CACHE_NONE
) {
3311 /* Access to snoopable pages through the GTT is
3312 * incoherent and on some machines causes a hard
3313 * lockup. Relinquish the CPU mmaping to force
3314 * userspace to refault in the pages and we can
3315 * then double check if the GTT mapping is still
3316 * valid for that pointer access.
3318 i915_gem_release_mmap(obj
);
3320 /* As we no longer need a fence for GTT access,
3321 * we can relinquish it now (and so prevent having
3322 * to steal a fence from someone else on the next
3323 * fence request). Note GPU activity would have
3324 * dropped the fence as all snoopable access is
3325 * supposed to be linear.
3327 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3328 ret
= i915_vma_put_fence(vma
);
3333 /* We either have incoherent backing store and
3334 * so no GTT access or the architecture is fully
3335 * coherent. In such cases, existing GTT mmaps
3336 * ignore the cache bit in the PTE and we can
3337 * rewrite it without confusing the GPU or having
3338 * to force userspace to fault back in its mmaps.
3342 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3343 if (!drm_mm_node_allocated(&vma
->node
))
3346 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3352 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
&&
3353 cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3354 obj
->cache_dirty
= true;
3356 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3357 vma
->node
.color
= cache_level
;
3358 obj
->cache_level
= cache_level
;
3363 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3364 struct drm_file
*file
)
3366 struct drm_i915_gem_caching
*args
= data
;
3367 struct drm_i915_gem_object
*obj
;
3371 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3377 switch (obj
->cache_level
) {
3378 case I915_CACHE_LLC
:
3379 case I915_CACHE_L3_LLC
:
3380 args
->caching
= I915_CACHING_CACHED
;
3384 args
->caching
= I915_CACHING_DISPLAY
;
3388 args
->caching
= I915_CACHING_NONE
;
3396 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3397 struct drm_file
*file
)
3399 struct drm_i915_private
*i915
= to_i915(dev
);
3400 struct drm_i915_gem_caching
*args
= data
;
3401 struct drm_i915_gem_object
*obj
;
3402 enum i915_cache_level level
;
3405 switch (args
->caching
) {
3406 case I915_CACHING_NONE
:
3407 level
= I915_CACHE_NONE
;
3409 case I915_CACHING_CACHED
:
3411 * Due to a HW issue on BXT A stepping, GPU stores via a
3412 * snooped mapping may leave stale data in a corresponding CPU
3413 * cacheline, whereas normally such cachelines would get
3416 if (!HAS_LLC(i915
) && !HAS_SNOOP(i915
))
3419 level
= I915_CACHE_LLC
;
3421 case I915_CACHING_DISPLAY
:
3422 level
= HAS_WT(i915
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3428 ret
= i915_mutex_lock_interruptible(dev
);
3432 obj
= i915_gem_object_lookup(file
, args
->handle
);
3438 ret
= i915_gem_object_set_cache_level(obj
, level
);
3439 i915_gem_object_put(obj
);
3441 mutex_unlock(&dev
->struct_mutex
);
3446 * Prepare buffer for display plane (scanout, cursors, etc).
3447 * Can be called from an uninterruptible phase (modesetting) and allows
3448 * any flushes to be pipelined (for pageflips).
3451 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3453 const struct i915_ggtt_view
*view
)
3455 struct i915_vma
*vma
;
3456 u32 old_read_domains
, old_write_domain
;
3459 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3461 /* Mark the pin_display early so that we account for the
3462 * display coherency whilst setting up the cache domains.
3466 /* The display engine is not coherent with the LLC cache on gen6. As
3467 * a result, we make sure that the pinning that is about to occur is
3468 * done with uncached PTEs. This is lowest common denominator for all
3471 * However for gen6+, we could do better by using the GFDT bit instead
3472 * of uncaching, which would allow us to flush all the LLC-cached data
3473 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3475 ret
= i915_gem_object_set_cache_level(obj
,
3476 HAS_WT(to_i915(obj
->base
.dev
)) ?
3477 I915_CACHE_WT
: I915_CACHE_NONE
);
3480 goto err_unpin_display
;
3483 /* As the user may map the buffer once pinned in the display plane
3484 * (e.g. libkms for the bootup splash), we have to ensure that we
3485 * always use map_and_fenceable for all scanout buffers. However,
3486 * it may simply be too big to fit into mappable, in which case
3487 * put it anyway and hope that userspace can cope (but always first
3488 * try to preserve the existing ABI).
3490 vma
= ERR_PTR(-ENOSPC
);
3491 if (view
->type
== I915_GGTT_VIEW_NORMAL
)
3492 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
,
3493 PIN_MAPPABLE
| PIN_NONBLOCK
);
3495 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3498 /* Valleyview is definitely limited to scanning out the first
3499 * 512MiB. Lets presume this behaviour was inherited from the
3500 * g4x display engine and that all earlier gen are similarly
3501 * limited. Testing suggests that it is a little more
3502 * complicated than this. For example, Cherryview appears quite
3503 * happy to scanout from anywhere within its global aperture.
3506 if (HAS_GMCH_DISPLAY(i915
))
3507 flags
= PIN_MAPPABLE
;
3508 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
, flags
);
3511 goto err_unpin_display
;
3513 vma
->display_alignment
= max_t(u64
, vma
->display_alignment
, alignment
);
3515 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3516 if (obj
->cache_dirty
) {
3517 i915_gem_clflush_object(obj
, true);
3518 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
3521 old_write_domain
= obj
->base
.write_domain
;
3522 old_read_domains
= obj
->base
.read_domains
;
3524 /* It should now be out of any other write domains, and we can update
3525 * the domain values for our changes.
3527 obj
->base
.write_domain
= 0;
3528 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3530 trace_i915_gem_object_change_domain(obj
,
3542 i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
)
3544 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3546 if (WARN_ON(vma
->obj
->pin_display
== 0))
3549 if (--vma
->obj
->pin_display
== 0)
3550 vma
->display_alignment
= 0;
3552 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3553 if (!i915_vma_is_active(vma
))
3554 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
3556 i915_vma_unpin(vma
);
3560 * Moves a single object to the CPU read, and possibly write domain.
3561 * @obj: object to act on
3562 * @write: requesting write or read-only access
3564 * This function returns when the move is complete, including waiting on
3568 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3570 uint32_t old_write_domain
, old_read_domains
;
3573 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3575 ret
= i915_gem_object_wait(obj
,
3576 I915_WAIT_INTERRUPTIBLE
|
3578 (write
? I915_WAIT_ALL
: 0),
3579 MAX_SCHEDULE_TIMEOUT
,
3584 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3587 i915_gem_object_flush_gtt_write_domain(obj
);
3589 old_write_domain
= obj
->base
.write_domain
;
3590 old_read_domains
= obj
->base
.read_domains
;
3592 /* Flush the CPU cache if it's still invalid. */
3593 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3594 i915_gem_clflush_object(obj
, false);
3596 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3599 /* It should now be out of any other write domains, and we can update
3600 * the domain values for our changes.
3602 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3604 /* If we're writing through the CPU, then the GPU read domains will
3605 * need to be invalidated at next use.
3608 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3609 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3612 trace_i915_gem_object_change_domain(obj
,
3619 /* Throttle our rendering by waiting until the ring has completed our requests
3620 * emitted over 20 msec ago.
3622 * Note that if we were to use the current jiffies each time around the loop,
3623 * we wouldn't escape the function with any frames outstanding if the time to
3624 * render a frame was over 20ms.
3626 * This should get us reasonable parallelism between CPU and GPU but also
3627 * relatively low latency when blocking on a particular request to finish.
3630 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3632 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3633 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3634 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
3635 struct drm_i915_gem_request
*request
, *target
= NULL
;
3638 /* ABI: return -EIO if already wedged */
3639 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
3642 spin_lock(&file_priv
->mm
.lock
);
3643 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3644 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3648 * Note that the request might not have been submitted yet.
3649 * In which case emitted_jiffies will be zero.
3651 if (!request
->emitted_jiffies
)
3657 i915_gem_request_get(target
);
3658 spin_unlock(&file_priv
->mm
.lock
);
3663 ret
= i915_wait_request(target
,
3664 I915_WAIT_INTERRUPTIBLE
,
3665 MAX_SCHEDULE_TIMEOUT
);
3666 i915_gem_request_put(target
);
3668 return ret
< 0 ? ret
: 0;
3672 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3673 const struct i915_ggtt_view
*view
,
3678 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3679 struct i915_address_space
*vm
= &dev_priv
->ggtt
.base
;
3680 struct i915_vma
*vma
;
3683 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3685 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
, view
);
3689 if (i915_vma_misplaced(vma
, size
, alignment
, flags
)) {
3690 if (flags
& PIN_NONBLOCK
&&
3691 (i915_vma_is_pinned(vma
) || i915_vma_is_active(vma
)))
3692 return ERR_PTR(-ENOSPC
);
3694 if (flags
& PIN_MAPPABLE
) {
3697 fence_size
= i915_gem_get_ggtt_size(dev_priv
, vma
->size
,
3698 i915_gem_object_get_tiling(obj
));
3699 /* If the required space is larger than the available
3700 * aperture, we will not able to find a slot for the
3701 * object and unbinding the object now will be in
3702 * vain. Worse, doing so may cause us to ping-pong
3703 * the object in and out of the Global GTT and
3704 * waste a lot of cycles under the mutex.
3706 if (fence_size
> dev_priv
->ggtt
.mappable_end
)
3707 return ERR_PTR(-E2BIG
);
3709 /* If NONBLOCK is set the caller is optimistically
3710 * trying to cache the full object within the mappable
3711 * aperture, and *must* have a fallback in place for
3712 * situations where we cannot bind the object. We
3713 * can be a little more lax here and use the fallback
3714 * more often to avoid costly migrations of ourselves
3715 * and other objects within the aperture.
3717 * Half-the-aperture is used as a simple heuristic.
3718 * More interesting would to do search for a free
3719 * block prior to making the commitment to unbind.
3720 * That caters for the self-harm case, and with a
3721 * little more heuristics (e.g. NOFAULT, NOEVICT)
3722 * we could try to minimise harm to others.
3724 if (flags
& PIN_NONBLOCK
&&
3725 fence_size
> dev_priv
->ggtt
.mappable_end
/ 2)
3726 return ERR_PTR(-ENOSPC
);
3729 WARN(i915_vma_is_pinned(vma
),
3730 "bo is already pinned in ggtt with incorrect alignment:"
3731 " offset=%08x, req.alignment=%llx,"
3732 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3733 i915_ggtt_offset(vma
), alignment
,
3734 !!(flags
& PIN_MAPPABLE
),
3735 i915_vma_is_map_and_fenceable(vma
));
3736 ret
= i915_vma_unbind(vma
);
3738 return ERR_PTR(ret
);
3741 ret
= i915_vma_pin(vma
, size
, alignment
, flags
| PIN_GLOBAL
);
3743 return ERR_PTR(ret
);
3748 static __always_inline
unsigned int __busy_read_flag(unsigned int id
)
3750 /* Note that we could alias engines in the execbuf API, but
3751 * that would be very unwise as it prevents userspace from
3752 * fine control over engine selection. Ahem.
3754 * This should be something like EXEC_MAX_ENGINE instead of
3757 BUILD_BUG_ON(I915_NUM_ENGINES
> 16);
3758 return 0x10000 << id
;
3761 static __always_inline
unsigned int __busy_write_id(unsigned int id
)
3763 /* The uABI guarantees an active writer is also amongst the read
3764 * engines. This would be true if we accessed the activity tracking
3765 * under the lock, but as we perform the lookup of the object and
3766 * its activity locklessly we can not guarantee that the last_write
3767 * being active implies that we have set the same engine flag from
3768 * last_read - hence we always set both read and write busy for
3771 return id
| __busy_read_flag(id
);
3774 static __always_inline
unsigned int
3775 __busy_set_if_active(const struct dma_fence
*fence
,
3776 unsigned int (*flag
)(unsigned int id
))
3778 struct drm_i915_gem_request
*rq
;
3780 /* We have to check the current hw status of the fence as the uABI
3781 * guarantees forward progress. We could rely on the idle worker
3782 * to eventually flush us, but to minimise latency just ask the
3785 * Note we only report on the status of native fences.
3787 if (!dma_fence_is_i915(fence
))
3790 /* opencode to_request() in order to avoid const warnings */
3791 rq
= container_of(fence
, struct drm_i915_gem_request
, fence
);
3792 if (i915_gem_request_completed(rq
))
3795 return flag(rq
->engine
->exec_id
);
3798 static __always_inline
unsigned int
3799 busy_check_reader(const struct dma_fence
*fence
)
3801 return __busy_set_if_active(fence
, __busy_read_flag
);
3804 static __always_inline
unsigned int
3805 busy_check_writer(const struct dma_fence
*fence
)
3810 return __busy_set_if_active(fence
, __busy_write_id
);
3814 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3815 struct drm_file
*file
)
3817 struct drm_i915_gem_busy
*args
= data
;
3818 struct drm_i915_gem_object
*obj
;
3819 struct reservation_object_list
*list
;
3825 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3829 /* A discrepancy here is that we do not report the status of
3830 * non-i915 fences, i.e. even though we may report the object as idle,
3831 * a call to set-domain may still stall waiting for foreign rendering.
3832 * This also means that wait-ioctl may report an object as busy,
3833 * where busy-ioctl considers it idle.
3835 * We trade the ability to warn of foreign fences to report on which
3836 * i915 engines are active for the object.
3838 * Alternatively, we can trade that extra information on read/write
3841 * !reservation_object_test_signaled_rcu(obj->resv, true);
3842 * to report the overall busyness. This is what the wait-ioctl does.
3846 seq
= raw_read_seqcount(&obj
->resv
->seq
);
3848 /* Translate the exclusive fence to the READ *and* WRITE engine */
3849 args
->busy
= busy_check_writer(rcu_dereference(obj
->resv
->fence_excl
));
3851 /* Translate shared fences to READ set of engines */
3852 list
= rcu_dereference(obj
->resv
->fence
);
3854 unsigned int shared_count
= list
->shared_count
, i
;
3856 for (i
= 0; i
< shared_count
; ++i
) {
3857 struct dma_fence
*fence
=
3858 rcu_dereference(list
->shared
[i
]);
3860 args
->busy
|= busy_check_reader(fence
);
3864 if (args
->busy
&& read_seqcount_retry(&obj
->resv
->seq
, seq
))
3874 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3875 struct drm_file
*file_priv
)
3877 return i915_gem_ring_throttle(dev
, file_priv
);
3881 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3882 struct drm_file
*file_priv
)
3884 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3885 struct drm_i915_gem_madvise
*args
= data
;
3886 struct drm_i915_gem_object
*obj
;
3889 switch (args
->madv
) {
3890 case I915_MADV_DONTNEED
:
3891 case I915_MADV_WILLNEED
:
3897 obj
= i915_gem_object_lookup(file_priv
, args
->handle
);
3901 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
3905 if (obj
->mm
.pages
&&
3906 i915_gem_object_is_tiled(obj
) &&
3907 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
3908 if (obj
->mm
.madv
== I915_MADV_WILLNEED
) {
3909 GEM_BUG_ON(!obj
->mm
.quirked
);
3910 __i915_gem_object_unpin_pages(obj
);
3911 obj
->mm
.quirked
= false;
3913 if (args
->madv
== I915_MADV_WILLNEED
) {
3914 GEM_BUG_ON(obj
->mm
.quirked
);
3915 __i915_gem_object_pin_pages(obj
);
3916 obj
->mm
.quirked
= true;
3920 if (obj
->mm
.madv
!= __I915_MADV_PURGED
)
3921 obj
->mm
.madv
= args
->madv
;
3923 /* if the object is no longer attached, discard its backing storage */
3924 if (obj
->mm
.madv
== I915_MADV_DONTNEED
&& !obj
->mm
.pages
)
3925 i915_gem_object_truncate(obj
);
3927 args
->retained
= obj
->mm
.madv
!= __I915_MADV_PURGED
;
3928 mutex_unlock(&obj
->mm
.lock
);
3931 i915_gem_object_put(obj
);
3936 frontbuffer_retire(struct i915_gem_active
*active
,
3937 struct drm_i915_gem_request
*request
)
3939 struct drm_i915_gem_object
*obj
=
3940 container_of(active
, typeof(*obj
), frontbuffer_write
);
3942 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
3945 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3946 const struct drm_i915_gem_object_ops
*ops
)
3948 mutex_init(&obj
->mm
.lock
);
3950 INIT_LIST_HEAD(&obj
->global_link
);
3951 INIT_LIST_HEAD(&obj
->userfault_link
);
3952 INIT_LIST_HEAD(&obj
->obj_exec_link
);
3953 INIT_LIST_HEAD(&obj
->vma_list
);
3954 INIT_LIST_HEAD(&obj
->batch_pool_link
);
3958 reservation_object_init(&obj
->__builtin_resv
);
3959 obj
->resv
= &obj
->__builtin_resv
;
3961 obj
->frontbuffer_ggtt_origin
= ORIGIN_GTT
;
3962 init_request_active(&obj
->frontbuffer_write
, frontbuffer_retire
);
3964 obj
->mm
.madv
= I915_MADV_WILLNEED
;
3965 INIT_RADIX_TREE(&obj
->mm
.get_page
.radix
, GFP_KERNEL
| __GFP_NOWARN
);
3966 mutex_init(&obj
->mm
.get_page
.lock
);
3968 i915_gem_info_add_obj(to_i915(obj
->base
.dev
), obj
->base
.size
);
3971 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3972 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
|
3973 I915_GEM_OBJECT_IS_SHRINKABLE
,
3974 .get_pages
= i915_gem_object_get_pages_gtt
,
3975 .put_pages
= i915_gem_object_put_pages_gtt
,
3978 /* Note we don't consider signbits :| */
3979 #define overflows_type(x, T) \
3980 (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
3982 struct drm_i915_gem_object
*
3983 i915_gem_object_create(struct drm_device
*dev
, u64 size
)
3985 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3986 struct drm_i915_gem_object
*obj
;
3987 struct address_space
*mapping
;
3991 /* There is a prevalence of the assumption that we fit the object's
3992 * page count inside a 32bit _signed_ variable. Let's document this and
3993 * catch if we ever need to fix it. In the meantime, if you do spot
3994 * such a local variable, please consider fixing!
3996 if (WARN_ON(size
>> PAGE_SHIFT
> INT_MAX
))
3997 return ERR_PTR(-E2BIG
);
3999 if (overflows_type(size
, obj
->base
.size
))
4000 return ERR_PTR(-E2BIG
);
4002 obj
= i915_gem_object_alloc(dev
);
4004 return ERR_PTR(-ENOMEM
);
4006 ret
= drm_gem_object_init(dev
, &obj
->base
, size
);
4010 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4011 if (IS_CRESTLINE(dev_priv
) || IS_BROADWATER(dev_priv
)) {
4012 /* 965gm cannot relocate objects above 4GiB. */
4013 mask
&= ~__GFP_HIGHMEM
;
4014 mask
|= __GFP_DMA32
;
4017 mapping
= obj
->base
.filp
->f_mapping
;
4018 mapping_set_gfp_mask(mapping
, mask
);
4020 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4022 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4023 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4025 if (HAS_LLC(dev_priv
)) {
4026 /* On some devices, we can have the GPU use the LLC (the CPU
4027 * cache) for about a 10% performance improvement
4028 * compared to uncached. Graphics requests other than
4029 * display scanout are coherent with the CPU in
4030 * accessing this cache. This means in this mode we
4031 * don't need to clflush on the CPU side, and on the
4032 * GPU side we only need to flush internal caches to
4033 * get data visible to the CPU.
4035 * However, we maintain the display planes as UC, and so
4036 * need to rebind when first used as such.
4038 obj
->cache_level
= I915_CACHE_LLC
;
4040 obj
->cache_level
= I915_CACHE_NONE
;
4042 trace_i915_gem_object_create(obj
);
4047 i915_gem_object_free(obj
);
4048 return ERR_PTR(ret
);
4051 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4053 /* If we are the last user of the backing storage (be it shmemfs
4054 * pages or stolen etc), we know that the pages are going to be
4055 * immediately released. In this case, we can then skip copying
4056 * back the contents from the GPU.
4059 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
4062 if (obj
->base
.filp
== NULL
)
4065 /* At first glance, this looks racy, but then again so would be
4066 * userspace racing mmap against close. However, the first external
4067 * reference to the filp can only be obtained through the
4068 * i915_gem_mmap_ioctl() which safeguards us against the user
4069 * acquiring such a reference whilst we are in the middle of
4070 * freeing the object.
4072 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4075 static void __i915_gem_free_objects(struct drm_i915_private
*i915
,
4076 struct llist_node
*freed
)
4078 struct drm_i915_gem_object
*obj
, *on
;
4080 mutex_lock(&i915
->drm
.struct_mutex
);
4081 intel_runtime_pm_get(i915
);
4082 llist_for_each_entry(obj
, freed
, freed
) {
4083 struct i915_vma
*vma
, *vn
;
4085 trace_i915_gem_object_destroy(obj
);
4087 GEM_BUG_ON(i915_gem_object_is_active(obj
));
4088 list_for_each_entry_safe(vma
, vn
,
4089 &obj
->vma_list
, obj_link
) {
4090 GEM_BUG_ON(!i915_vma_is_ggtt(vma
));
4091 GEM_BUG_ON(i915_vma_is_active(vma
));
4092 vma
->flags
&= ~I915_VMA_PIN_MASK
;
4093 i915_vma_close(vma
);
4095 GEM_BUG_ON(!list_empty(&obj
->vma_list
));
4096 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj
->vma_tree
));
4098 list_del(&obj
->global_link
);
4100 intel_runtime_pm_put(i915
);
4101 mutex_unlock(&i915
->drm
.struct_mutex
);
4103 llist_for_each_entry_safe(obj
, on
, freed
, freed
) {
4104 GEM_BUG_ON(obj
->bind_count
);
4105 GEM_BUG_ON(atomic_read(&obj
->frontbuffer_bits
));
4107 if (obj
->ops
->release
)
4108 obj
->ops
->release(obj
);
4110 if (WARN_ON(i915_gem_object_has_pinned_pages(obj
)))
4111 atomic_set(&obj
->mm
.pages_pin_count
, 0);
4112 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
4113 GEM_BUG_ON(obj
->mm
.pages
);
4115 if (obj
->base
.import_attach
)
4116 drm_prime_gem_destroy(&obj
->base
, NULL
);
4118 reservation_object_fini(&obj
->__builtin_resv
);
4119 drm_gem_object_release(&obj
->base
);
4120 i915_gem_info_remove_obj(i915
, obj
->base
.size
);
4123 i915_gem_object_free(obj
);
4127 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
)
4129 struct llist_node
*freed
;
4131 freed
= llist_del_all(&i915
->mm
.free_list
);
4132 if (unlikely(freed
))
4133 __i915_gem_free_objects(i915
, freed
);
4136 static void __i915_gem_free_work(struct work_struct
*work
)
4138 struct drm_i915_private
*i915
=
4139 container_of(work
, struct drm_i915_private
, mm
.free_work
);
4140 struct llist_node
*freed
;
4142 /* All file-owned VMA should have been released by this point through
4143 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4144 * However, the object may also be bound into the global GTT (e.g.
4145 * older GPUs without per-process support, or for direct access through
4146 * the GTT either for the user or for scanout). Those VMA still need to
4150 while ((freed
= llist_del_all(&i915
->mm
.free_list
)))
4151 __i915_gem_free_objects(i915
, freed
);
4154 static void __i915_gem_free_object_rcu(struct rcu_head
*head
)
4156 struct drm_i915_gem_object
*obj
=
4157 container_of(head
, typeof(*obj
), rcu
);
4158 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
4160 /* We can't simply use call_rcu() from i915_gem_free_object()
4161 * as we need to block whilst unbinding, and the call_rcu
4162 * task may be called from softirq context. So we take a
4163 * detour through a worker.
4165 if (llist_add(&obj
->freed
, &i915
->mm
.free_list
))
4166 schedule_work(&i915
->mm
.free_work
);
4169 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4171 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4173 if (obj
->mm
.quirked
)
4174 __i915_gem_object_unpin_pages(obj
);
4176 if (discard_backing_storage(obj
))
4177 obj
->mm
.madv
= I915_MADV_DONTNEED
;
4179 /* Before we free the object, make sure any pure RCU-only
4180 * read-side critical sections are complete, e.g.
4181 * i915_gem_busy_ioctl(). For the corresponding synchronized
4182 * lookup see i915_gem_object_lookup_rcu().
4184 call_rcu(&obj
->rcu
, __i915_gem_free_object_rcu
);
4187 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object
*obj
)
4189 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
4191 GEM_BUG_ON(i915_gem_object_has_active_reference(obj
));
4192 if (i915_gem_object_is_active(obj
))
4193 i915_gem_object_set_active_reference(obj
);
4195 i915_gem_object_put(obj
);
4198 static void assert_kernel_context_is_current(struct drm_i915_private
*dev_priv
)
4200 struct intel_engine_cs
*engine
;
4201 enum intel_engine_id id
;
4203 for_each_engine(engine
, dev_priv
, id
)
4204 GEM_BUG_ON(engine
->last_context
!= dev_priv
->kernel_context
);
4207 int i915_gem_suspend(struct drm_device
*dev
)
4209 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4212 intel_suspend_gt_powersave(dev_priv
);
4214 mutex_lock(&dev
->struct_mutex
);
4216 /* We have to flush all the executing contexts to main memory so
4217 * that they can saved in the hibernation image. To ensure the last
4218 * context image is coherent, we have to switch away from it. That
4219 * leaves the dev_priv->kernel_context still active when
4220 * we actually suspend, and its image in memory may not match the GPU
4221 * state. Fortunately, the kernel_context is disposable and we do
4222 * not rely on its state.
4224 ret
= i915_gem_switch_to_kernel_context(dev_priv
);
4228 ret
= i915_gem_wait_for_idle(dev_priv
,
4229 I915_WAIT_INTERRUPTIBLE
|
4234 i915_gem_retire_requests(dev_priv
);
4235 GEM_BUG_ON(dev_priv
->gt
.active_requests
);
4237 assert_kernel_context_is_current(dev_priv
);
4238 i915_gem_context_lost(dev_priv
);
4239 mutex_unlock(&dev
->struct_mutex
);
4241 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4242 cancel_delayed_work_sync(&dev_priv
->gt
.retire_work
);
4243 flush_delayed_work(&dev_priv
->gt
.idle_work
);
4244 flush_work(&dev_priv
->mm
.free_work
);
4246 /* Assert that we sucessfully flushed all the work and
4247 * reset the GPU back to its idle, low power state.
4249 WARN_ON(dev_priv
->gt
.awake
);
4250 WARN_ON(!intel_execlists_idle(dev_priv
));
4253 * Neither the BIOS, ourselves or any other kernel
4254 * expects the system to be in execlists mode on startup,
4255 * so we need to reset the GPU back to legacy mode. And the only
4256 * known way to disable logical contexts is through a GPU reset.
4258 * So in order to leave the system in a known default configuration,
4259 * always reset the GPU upon unload and suspend. Afterwards we then
4260 * clean up the GEM state tracking, flushing off the requests and
4261 * leaving the system in a known idle state.
4263 * Note that is of the upmost importance that the GPU is idle and
4264 * all stray writes are flushed *before* we dismantle the backing
4265 * storage for the pinned objects.
4267 * However, since we are uncertain that resetting the GPU on older
4268 * machines is a good idea, we don't - just in case it leaves the
4269 * machine in an unusable condition.
4271 if (HAS_HW_CONTEXTS(dev_priv
)) {
4272 int reset
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
4273 WARN_ON(reset
&& reset
!= -ENODEV
);
4279 mutex_unlock(&dev
->struct_mutex
);
4283 void i915_gem_resume(struct drm_device
*dev
)
4285 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4287 WARN_ON(dev_priv
->gt
.awake
);
4289 mutex_lock(&dev
->struct_mutex
);
4290 i915_gem_restore_gtt_mappings(dev_priv
);
4292 /* As we didn't flush the kernel context before suspend, we cannot
4293 * guarantee that the context image is complete. So let's just reset
4294 * it and start again.
4296 dev_priv
->gt
.resume(dev_priv
);
4298 mutex_unlock(&dev
->struct_mutex
);
4301 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
)
4303 if (INTEL_GEN(dev_priv
) < 5 ||
4304 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4307 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4308 DISP_TILE_SURFACE_SWIZZLING
);
4310 if (IS_GEN5(dev_priv
))
4313 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4314 if (IS_GEN6(dev_priv
))
4315 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4316 else if (IS_GEN7(dev_priv
))
4317 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4318 else if (IS_GEN8(dev_priv
))
4319 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4324 static void init_unused_ring(struct drm_i915_private
*dev_priv
, u32 base
)
4326 I915_WRITE(RING_CTL(base
), 0);
4327 I915_WRITE(RING_HEAD(base
), 0);
4328 I915_WRITE(RING_TAIL(base
), 0);
4329 I915_WRITE(RING_START(base
), 0);
4332 static void init_unused_rings(struct drm_i915_private
*dev_priv
)
4334 if (IS_I830(dev_priv
)) {
4335 init_unused_ring(dev_priv
, PRB1_BASE
);
4336 init_unused_ring(dev_priv
, SRB0_BASE
);
4337 init_unused_ring(dev_priv
, SRB1_BASE
);
4338 init_unused_ring(dev_priv
, SRB2_BASE
);
4339 init_unused_ring(dev_priv
, SRB3_BASE
);
4340 } else if (IS_GEN2(dev_priv
)) {
4341 init_unused_ring(dev_priv
, SRB0_BASE
);
4342 init_unused_ring(dev_priv
, SRB1_BASE
);
4343 } else if (IS_GEN3(dev_priv
)) {
4344 init_unused_ring(dev_priv
, PRB1_BASE
);
4345 init_unused_ring(dev_priv
, PRB2_BASE
);
4350 i915_gem_init_hw(struct drm_device
*dev
)
4352 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4353 struct intel_engine_cs
*engine
;
4354 enum intel_engine_id id
;
4357 dev_priv
->gt
.last_init_time
= ktime_get();
4359 /* Double layer security blanket, see i915_gem_init() */
4360 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4362 if (HAS_EDRAM(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
4363 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4365 if (IS_HASWELL(dev_priv
))
4366 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev_priv
) ?
4367 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4369 if (HAS_PCH_NOP(dev_priv
)) {
4370 if (IS_IVYBRIDGE(dev_priv
)) {
4371 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4372 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4373 I915_WRITE(GEN7_MSG_CTL
, temp
);
4374 } else if (INTEL_GEN(dev_priv
) >= 7) {
4375 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4376 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4377 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4381 i915_gem_init_swizzling(dev_priv
);
4384 * At least 830 can leave some of the unused rings
4385 * "active" (ie. head != tail) after resume which
4386 * will prevent c3 entry. Makes sure all unused rings
4389 init_unused_rings(dev_priv
);
4391 BUG_ON(!dev_priv
->kernel_context
);
4393 ret
= i915_ppgtt_init_hw(dev_priv
);
4395 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4399 /* Need to do basic initialisation of all rings first: */
4400 for_each_engine(engine
, dev_priv
, id
) {
4401 ret
= engine
->init_hw(engine
);
4406 intel_mocs_init_l3cc_table(dev
);
4408 /* We can't enable contexts until all firmware is loaded */
4409 ret
= intel_guc_setup(dev
);
4414 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4418 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
)
4420 if (INTEL_INFO(dev_priv
)->gen
< 6)
4423 /* TODO: make semaphores and Execlists play nicely together */
4424 if (i915
.enable_execlists
)
4430 #ifdef CONFIG_INTEL_IOMMU
4431 /* Enable semaphores on SNB when IO remapping is off */
4432 if (INTEL_INFO(dev_priv
)->gen
== 6 && intel_iommu_gfx_mapped
)
4439 int i915_gem_init(struct drm_device
*dev
)
4441 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4444 mutex_lock(&dev
->struct_mutex
);
4446 if (!i915
.enable_execlists
) {
4447 dev_priv
->gt
.resume
= intel_legacy_submission_resume
;
4448 dev_priv
->gt
.cleanup_engine
= intel_engine_cleanup
;
4450 dev_priv
->gt
.resume
= intel_lr_context_resume
;
4451 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4454 /* This is just a security blanket to placate dragons.
4455 * On some systems, we very sporadically observe that the first TLBs
4456 * used by the CS may be stale, despite us poking the TLB reset. If
4457 * we hold the forcewake during initialisation these problems
4458 * just magically go away.
4460 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4462 i915_gem_init_userptr(dev_priv
);
4464 ret
= i915_gem_init_ggtt(dev_priv
);
4468 ret
= i915_gem_context_init(dev
);
4472 ret
= intel_engines_init(dev
);
4476 ret
= i915_gem_init_hw(dev
);
4478 /* Allow engine initialisation to fail by marking the GPU as
4479 * wedged. But we only want to do this where the GPU is angry,
4480 * for all other failure, such as an allocation failure, bail.
4482 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4483 i915_gem_set_wedged(dev_priv
);
4488 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4489 mutex_unlock(&dev
->struct_mutex
);
4495 i915_gem_cleanup_engines(struct drm_device
*dev
)
4497 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4498 struct intel_engine_cs
*engine
;
4499 enum intel_engine_id id
;
4501 for_each_engine(engine
, dev_priv
, id
)
4502 dev_priv
->gt
.cleanup_engine(engine
);
4506 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
4510 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
4511 !IS_CHERRYVIEW(dev_priv
))
4512 dev_priv
->num_fence_regs
= 32;
4513 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
4514 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
4515 dev_priv
->num_fence_regs
= 16;
4517 dev_priv
->num_fence_regs
= 8;
4519 if (intel_vgpu_active(dev_priv
))
4520 dev_priv
->num_fence_regs
=
4521 I915_READ(vgtif_reg(avail_rs
.fence_num
));
4523 /* Initialize fence registers to zero */
4524 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
4525 struct drm_i915_fence_reg
*fence
= &dev_priv
->fence_regs
[i
];
4527 fence
->i915
= dev_priv
;
4529 list_add_tail(&fence
->link
, &dev_priv
->mm
.fence_list
);
4531 i915_gem_restore_fences(dev_priv
);
4533 i915_gem_detect_bit_6_swizzle(dev_priv
);
4537 i915_gem_load_init(struct drm_device
*dev
)
4539 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4542 dev_priv
->objects
= KMEM_CACHE(drm_i915_gem_object
, SLAB_HWCACHE_ALIGN
);
4543 if (!dev_priv
->objects
)
4546 dev_priv
->vmas
= KMEM_CACHE(i915_vma
, SLAB_HWCACHE_ALIGN
);
4547 if (!dev_priv
->vmas
)
4550 dev_priv
->requests
= KMEM_CACHE(drm_i915_gem_request
,
4551 SLAB_HWCACHE_ALIGN
|
4552 SLAB_RECLAIM_ACCOUNT
|
4553 SLAB_DESTROY_BY_RCU
);
4554 if (!dev_priv
->requests
)
4557 dev_priv
->dependencies
= KMEM_CACHE(i915_dependency
,
4558 SLAB_HWCACHE_ALIGN
|
4559 SLAB_RECLAIM_ACCOUNT
);
4560 if (!dev_priv
->dependencies
)
4563 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4564 INIT_LIST_HEAD(&dev_priv
->gt
.timelines
);
4565 err
= i915_gem_timeline_init__global(dev_priv
);
4566 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4568 goto err_dependencies
;
4570 INIT_LIST_HEAD(&dev_priv
->context_list
);
4571 INIT_WORK(&dev_priv
->mm
.free_work
, __i915_gem_free_work
);
4572 init_llist_head(&dev_priv
->mm
.free_list
);
4573 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4574 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4575 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4576 INIT_LIST_HEAD(&dev_priv
->mm
.userfault_list
);
4577 INIT_DELAYED_WORK(&dev_priv
->gt
.retire_work
,
4578 i915_gem_retire_work_handler
);
4579 INIT_DELAYED_WORK(&dev_priv
->gt
.idle_work
,
4580 i915_gem_idle_work_handler
);
4581 init_waitqueue_head(&dev_priv
->gpu_error
.wait_queue
);
4582 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4584 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4586 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4588 dev_priv
->mm
.interruptible
= true;
4590 atomic_set(&dev_priv
->mm
.bsd_engine_dispatch_index
, 0);
4592 spin_lock_init(&dev_priv
->fb_tracking
.lock
);
4597 kmem_cache_destroy(dev_priv
->dependencies
);
4599 kmem_cache_destroy(dev_priv
->requests
);
4601 kmem_cache_destroy(dev_priv
->vmas
);
4603 kmem_cache_destroy(dev_priv
->objects
);
4608 void i915_gem_load_cleanup(struct drm_device
*dev
)
4610 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4612 WARN_ON(!llist_empty(&dev_priv
->mm
.free_list
));
4614 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4615 i915_gem_timeline_fini(&dev_priv
->gt
.global_timeline
);
4616 WARN_ON(!list_empty(&dev_priv
->gt
.timelines
));
4617 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4619 kmem_cache_destroy(dev_priv
->dependencies
);
4620 kmem_cache_destroy(dev_priv
->requests
);
4621 kmem_cache_destroy(dev_priv
->vmas
);
4622 kmem_cache_destroy(dev_priv
->objects
);
4624 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4628 int i915_gem_freeze(struct drm_i915_private
*dev_priv
)
4630 intel_runtime_pm_get(dev_priv
);
4632 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4633 i915_gem_shrink_all(dev_priv
);
4634 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4636 intel_runtime_pm_put(dev_priv
);
4641 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
4643 struct drm_i915_gem_object
*obj
;
4644 struct list_head
*phases
[] = {
4645 &dev_priv
->mm
.unbound_list
,
4646 &dev_priv
->mm
.bound_list
,
4650 /* Called just before we write the hibernation image.
4652 * We need to update the domain tracking to reflect that the CPU
4653 * will be accessing all the pages to create and restore from the
4654 * hibernation, and so upon restoration those pages will be in the
4657 * To make sure the hibernation image contains the latest state,
4658 * we update that state just before writing out the image.
4660 * To try and reduce the hibernation image, we manually shrink
4661 * the objects as well.
4664 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4665 i915_gem_shrink(dev_priv
, -1UL, I915_SHRINK_UNBOUND
);
4667 for (p
= phases
; *p
; p
++) {
4668 list_for_each_entry(obj
, *p
, global_link
) {
4669 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4670 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4673 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4678 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4680 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4681 struct drm_i915_gem_request
*request
;
4683 /* Clean up our request list when the client is going away, so that
4684 * later retire_requests won't dereference our soon-to-be-gone
4687 spin_lock(&file_priv
->mm
.lock
);
4688 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
)
4689 request
->file_priv
= NULL
;
4690 spin_unlock(&file_priv
->mm
.lock
);
4692 if (!list_empty(&file_priv
->rps
.link
)) {
4693 spin_lock(&to_i915(dev
)->rps
.client_lock
);
4694 list_del(&file_priv
->rps
.link
);
4695 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
4699 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4701 struct drm_i915_file_private
*file_priv
;
4706 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4710 file
->driver_priv
= file_priv
;
4711 file_priv
->dev_priv
= to_i915(dev
);
4712 file_priv
->file
= file
;
4713 INIT_LIST_HEAD(&file_priv
->rps
.link
);
4715 spin_lock_init(&file_priv
->mm
.lock
);
4716 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4718 file_priv
->bsd_engine
= -1;
4720 ret
= i915_gem_context_open(dev
, file
);
4728 * i915_gem_track_fb - update frontbuffer tracking
4729 * @old: current GEM buffer for the frontbuffer slots
4730 * @new: new GEM buffer for the frontbuffer slots
4731 * @frontbuffer_bits: bitmask of frontbuffer slots
4733 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4734 * from @old and setting them in @new. Both @old and @new can be NULL.
4736 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
4737 struct drm_i915_gem_object
*new,
4738 unsigned frontbuffer_bits
)
4740 /* Control of individual bits within the mask are guarded by
4741 * the owning plane->mutex, i.e. we can never see concurrent
4742 * manipulation of individual bits. But since the bitfield as a whole
4743 * is updated using RMW, we need to use atomics in order to update
4746 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE
* I915_MAX_PIPES
>
4747 sizeof(atomic_t
) * BITS_PER_BYTE
);
4750 WARN_ON(!(atomic_read(&old
->frontbuffer_bits
) & frontbuffer_bits
));
4751 atomic_andnot(frontbuffer_bits
, &old
->frontbuffer_bits
);
4755 WARN_ON(atomic_read(&new->frontbuffer_bits
) & frontbuffer_bits
);
4756 atomic_or(frontbuffer_bits
, &new->frontbuffer_bits
);
4760 /* Allocate a new GEM object and fill it with the supplied data */
4761 struct drm_i915_gem_object
*
4762 i915_gem_object_create_from_data(struct drm_device
*dev
,
4763 const void *data
, size_t size
)
4765 struct drm_i915_gem_object
*obj
;
4766 struct sg_table
*sg
;
4770 obj
= i915_gem_object_create(dev
, round_up(size
, PAGE_SIZE
));
4774 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
4778 ret
= i915_gem_object_pin_pages(obj
);
4783 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
4784 obj
->mm
.dirty
= true; /* Backing store is now out of date */
4785 i915_gem_object_unpin_pages(obj
);
4787 if (WARN_ON(bytes
!= size
)) {
4788 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
4796 i915_gem_object_put(obj
);
4797 return ERR_PTR(ret
);
4800 struct scatterlist
*
4801 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
4803 unsigned int *offset
)
4805 struct i915_gem_object_page_iter
*iter
= &obj
->mm
.get_page
;
4806 struct scatterlist
*sg
;
4807 unsigned int idx
, count
;
4810 GEM_BUG_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
);
4811 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
4813 /* As we iterate forward through the sg, we record each entry in a
4814 * radixtree for quick repeated (backwards) lookups. If we have seen
4815 * this index previously, we will have an entry for it.
4817 * Initial lookup is O(N), but this is amortized to O(1) for
4818 * sequential page access (where each new request is consecutive
4819 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4820 * i.e. O(1) with a large constant!
4822 if (n
< READ_ONCE(iter
->sg_idx
))
4825 mutex_lock(&iter
->lock
);
4827 /* We prefer to reuse the last sg so that repeated lookup of this
4828 * (or the subsequent) sg are fast - comparing against the last
4829 * sg is faster than going through the radixtree.
4834 count
= __sg_page_count(sg
);
4836 while (idx
+ count
<= n
) {
4837 unsigned long exception
, i
;
4840 /* If we cannot allocate and insert this entry, or the
4841 * individual pages from this range, cancel updating the
4842 * sg_idx so that on this lookup we are forced to linearly
4843 * scan onwards, but on future lookups we will try the
4844 * insertion again (in which case we need to be careful of
4845 * the error return reporting that we have already inserted
4848 ret
= radix_tree_insert(&iter
->radix
, idx
, sg
);
4849 if (ret
&& ret
!= -EEXIST
)
4853 RADIX_TREE_EXCEPTIONAL_ENTRY
|
4854 idx
<< RADIX_TREE_EXCEPTIONAL_SHIFT
;
4855 for (i
= 1; i
< count
; i
++) {
4856 ret
= radix_tree_insert(&iter
->radix
, idx
+ i
,
4858 if (ret
&& ret
!= -EEXIST
)
4863 sg
= ____sg_next(sg
);
4864 count
= __sg_page_count(sg
);
4871 mutex_unlock(&iter
->lock
);
4873 if (unlikely(n
< idx
)) /* insertion completed by another thread */
4876 /* In case we failed to insert the entry into the radixtree, we need
4877 * to look beyond the current sg.
4879 while (idx
+ count
<= n
) {
4881 sg
= ____sg_next(sg
);
4882 count
= __sg_page_count(sg
);
4891 sg
= radix_tree_lookup(&iter
->radix
, n
);
4894 /* If this index is in the middle of multi-page sg entry,
4895 * the radixtree will contain an exceptional entry that points
4896 * to the start of that range. We will return the pointer to
4897 * the base page and the offset of this page within the
4901 if (unlikely(radix_tree_exception(sg
))) {
4902 unsigned long base
=
4903 (unsigned long)sg
>> RADIX_TREE_EXCEPTIONAL_SHIFT
;
4905 sg
= radix_tree_lookup(&iter
->radix
, base
);
4917 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, unsigned int n
)
4919 struct scatterlist
*sg
;
4920 unsigned int offset
;
4922 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
4924 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
4925 return nth_page(sg_page(sg
), offset
);
4928 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
4930 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
4935 page
= i915_gem_object_get_page(obj
, n
);
4937 set_page_dirty(page
);
4943 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
4946 struct scatterlist
*sg
;
4947 unsigned int offset
;
4949 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
4950 return sg_dma_address(sg
) + (offset
<< PAGE_SHIFT
);