2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_mocs.h"
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
45 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
47 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
50 enum i915_cache_level level
)
52 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
57 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
60 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
63 return obj
->pin_display
;
67 insert_mappable_node(struct drm_i915_private
*i915
,
68 struct drm_mm_node
*node
, u32 size
)
70 memset(node
, 0, sizeof(*node
));
71 return drm_mm_insert_node_in_range_generic(&i915
->ggtt
.base
.mm
, node
,
73 i915
->ggtt
.mappable_end
,
74 DRM_MM_SEARCH_DEFAULT
,
75 DRM_MM_CREATE_DEFAULT
);
79 remove_mappable_node(struct drm_mm_node
*node
)
81 drm_mm_remove_node(node
);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
88 spin_lock(&dev_priv
->mm
.object_stat_lock
);
89 dev_priv
->mm
.object_count
++;
90 dev_priv
->mm
.object_memory
+= size
;
91 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
94 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
97 spin_lock(&dev_priv
->mm
.object_stat_lock
);
98 dev_priv
->mm
.object_count
--;
99 dev_priv
->mm
.object_memory
-= size
;
100 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
104 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
108 if (!i915_reset_in_progress(error
))
112 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
113 * userspace. If it takes that long something really bad is going on and
114 * we should simply try to bail out and fail as gracefully as possible.
116 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
117 !i915_reset_in_progress(error
),
120 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
122 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= to_i915(dev
);
151 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
152 struct drm_i915_gem_get_aperture
*args
= data
;
153 struct i915_vma
*vma
;
157 mutex_lock(&dev
->struct_mutex
);
158 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
160 pinned
+= vma
->node
.size
;
161 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
163 pinned
+= vma
->node
.size
;
164 mutex_unlock(&dev
->struct_mutex
);
166 args
->aper_size
= ggtt
->base
.total
;
167 args
->aper_available_size
= args
->aper_size
- pinned
;
173 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
175 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
176 char *vaddr
= obj
->phys_handle
->vaddr
;
178 struct scatterlist
*sg
;
181 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
188 page
= shmem_read_mapping_page(mapping
, i
);
190 return PTR_ERR(page
);
192 src
= kmap_atomic(page
);
193 memcpy(vaddr
, src
, PAGE_SIZE
);
194 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
201 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
203 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
207 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
214 sg
->length
= obj
->base
.size
;
216 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
217 sg_dma_len(sg
) = obj
->base
.size
;
224 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
228 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
230 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
232 /* In the event of a disaster, abandon all caches and
235 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
238 if (obj
->madv
== I915_MADV_DONTNEED
)
242 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
243 char *vaddr
= obj
->phys_handle
->vaddr
;
246 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
250 page
= shmem_read_mapping_page(mapping
, i
);
254 dst
= kmap_atomic(page
);
255 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
256 memcpy(dst
, vaddr
, PAGE_SIZE
);
259 set_page_dirty(page
);
260 if (obj
->madv
== I915_MADV_WILLNEED
)
261 mark_page_accessed(page
);
268 sg_free_table(obj
->pages
);
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(to_i915(dev
));
374 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_object_create(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
433 * @dev: drm device pointer
434 * @data: ioctl data blob
435 * @file: drm file pointer
438 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
439 struct drm_file
*file
)
441 struct drm_i915_gem_create
*args
= data
;
443 return i915_gem_create(file
, dev
,
444 args
->size
, &args
->handle
);
448 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
449 const char *gpu_vaddr
, int gpu_offset
,
452 int ret
, cpu_offset
= 0;
455 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
456 int this_length
= min(cacheline_end
- gpu_offset
, length
);
457 int swizzled_gpu_offset
= gpu_offset
^ 64;
459 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
460 gpu_vaddr
+ swizzled_gpu_offset
,
465 cpu_offset
+= this_length
;
466 gpu_offset
+= this_length
;
467 length
-= this_length
;
474 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
475 const char __user
*cpu_vaddr
,
478 int ret
, cpu_offset
= 0;
481 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
482 int this_length
= min(cacheline_end
- gpu_offset
, length
);
483 int swizzled_gpu_offset
= gpu_offset
^ 64;
485 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
486 cpu_vaddr
+ cpu_offset
,
491 cpu_offset
+= this_length
;
492 gpu_offset
+= this_length
;
493 length
-= this_length
;
500 * Pins the specified object's pages and synchronizes the object with
501 * GPU accesses. Sets needs_clflush to non-zero if the caller should
502 * flush the object from the CPU cache.
504 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (WARN_ON(!i915_gem_object_has_struct_page(obj
)))
514 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
515 /* If we're not in the cpu read domain, set ourself into the gtt
516 * read domain and manually flush cachelines (if required). This
517 * optimizes for the case when the gpu will dirty the data
518 * anyway again before the next pread happens. */
519 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
521 ret
= i915_gem_object_wait_rendering(obj
, true);
526 ret
= i915_gem_object_get_pages(obj
);
530 i915_gem_object_pin_pages(obj
);
535 /* Per-page copy function for the shmem pread fastpath.
536 * Flushes invalid cachelines before reading the target if
537 * needs_clflush is set. */
539 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
540 char __user
*user_data
,
541 bool page_do_bit17_swizzling
, bool needs_clflush
)
546 if (unlikely(page_do_bit17_swizzling
))
549 vaddr
= kmap_atomic(page
);
551 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
553 ret
= __copy_to_user_inatomic(user_data
,
554 vaddr
+ shmem_page_offset
,
556 kunmap_atomic(vaddr
);
558 return ret
? -EFAULT
: 0;
562 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
565 if (unlikely(swizzled
)) {
566 unsigned long start
= (unsigned long) addr
;
567 unsigned long end
= (unsigned long) addr
+ length
;
569 /* For swizzling simply ensure that we always flush both
570 * channels. Lame, but simple and it works. Swizzled
571 * pwrite/pread is far from a hotpath - current userspace
572 * doesn't use it at all. */
573 start
= round_down(start
, 128);
574 end
= round_up(end
, 128);
576 drm_clflush_virt_range((void *)start
, end
- start
);
578 drm_clflush_virt_range(addr
, length
);
583 /* Only difference to the fast-path function is that this can handle bit17
584 * and uses non-atomic copy and kmap functions. */
586 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
587 char __user
*user_data
,
588 bool page_do_bit17_swizzling
, bool needs_clflush
)
595 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
597 page_do_bit17_swizzling
);
599 if (page_do_bit17_swizzling
)
600 ret
= __copy_to_user_swizzled(user_data
,
601 vaddr
, shmem_page_offset
,
604 ret
= __copy_to_user(user_data
,
605 vaddr
+ shmem_page_offset
,
609 return ret
? - EFAULT
: 0;
612 static inline unsigned long
613 slow_user_access(struct io_mapping
*mapping
,
614 uint64_t page_base
, int page_offset
,
615 char __user
*user_data
,
616 unsigned long length
, bool pwrite
)
618 void __iomem
*ioaddr
;
622 ioaddr
= io_mapping_map_wc(mapping
, page_base
, PAGE_SIZE
);
623 /* We can use the cpu mem copy function because this is X86. */
624 vaddr
= (void __force
*)ioaddr
+ page_offset
;
626 unwritten
= __copy_from_user(vaddr
, user_data
, length
);
628 unwritten
= __copy_to_user(user_data
, vaddr
, length
);
630 io_mapping_unmap(ioaddr
);
635 i915_gem_gtt_pread(struct drm_device
*dev
,
636 struct drm_i915_gem_object
*obj
, uint64_t size
,
637 uint64_t data_offset
, uint64_t data_ptr
)
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
640 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
641 struct drm_mm_node node
;
642 char __user
*user_data
;
647 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
649 ret
= insert_mappable_node(dev_priv
, &node
, PAGE_SIZE
);
653 ret
= i915_gem_object_get_pages(obj
);
655 remove_mappable_node(&node
);
659 i915_gem_object_pin_pages(obj
);
661 node
.start
= i915_gem_obj_ggtt_offset(obj
);
662 node
.allocated
= false;
663 ret
= i915_gem_object_put_fence(obj
);
668 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
672 user_data
= u64_to_user_ptr(data_ptr
);
674 offset
= data_offset
;
676 mutex_unlock(&dev
->struct_mutex
);
677 if (likely(!i915
.prefault_disable
)) {
678 ret
= fault_in_multipages_writeable(user_data
, remain
);
680 mutex_lock(&dev
->struct_mutex
);
686 /* Operation in this page
688 * page_base = page offset within aperture
689 * page_offset = offset within page
690 * page_length = bytes to copy for this page
692 u32 page_base
= node
.start
;
693 unsigned page_offset
= offset_in_page(offset
);
694 unsigned page_length
= PAGE_SIZE
- page_offset
;
695 page_length
= remain
< page_length
? remain
: page_length
;
696 if (node
.allocated
) {
698 ggtt
->base
.insert_page(&ggtt
->base
,
699 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
704 page_base
+= offset
& PAGE_MASK
;
706 /* This is a slow read/write as it tries to read from
707 * and write to user memory which may result into page
708 * faults, and so we cannot perform this under struct_mutex.
710 if (slow_user_access(ggtt
->mappable
, page_base
,
711 page_offset
, user_data
,
712 page_length
, false)) {
717 remain
-= page_length
;
718 user_data
+= page_length
;
719 offset
+= page_length
;
722 mutex_lock(&dev
->struct_mutex
);
723 if (ret
== 0 && (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0) {
724 /* The user has modified the object whilst we tried
725 * reading from it, and we now have no idea what domain
726 * the pages should be in. As we have just been touching
727 * them directly, flush everything back to the GTT
730 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
734 if (node
.allocated
) {
736 ggtt
->base
.clear_range(&ggtt
->base
,
737 node
.start
, node
.size
,
739 i915_gem_object_unpin_pages(obj
);
740 remove_mappable_node(&node
);
742 i915_gem_object_ggtt_unpin(obj
);
749 i915_gem_shmem_pread(struct drm_device
*dev
,
750 struct drm_i915_gem_object
*obj
,
751 struct drm_i915_gem_pread
*args
,
752 struct drm_file
*file
)
754 char __user
*user_data
;
757 int shmem_page_offset
, page_length
, ret
= 0;
758 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
760 int needs_clflush
= 0;
761 struct sg_page_iter sg_iter
;
763 if (!i915_gem_object_has_struct_page(obj
))
766 user_data
= u64_to_user_ptr(args
->data_ptr
);
769 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
771 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
775 offset
= args
->offset
;
777 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
778 offset
>> PAGE_SHIFT
) {
779 struct page
*page
= sg_page_iter_page(&sg_iter
);
784 /* Operation in this page
786 * shmem_page_offset = offset within page in shmem file
787 * page_length = bytes to copy for this page
789 shmem_page_offset
= offset_in_page(offset
);
790 page_length
= remain
;
791 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
792 page_length
= PAGE_SIZE
- shmem_page_offset
;
794 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
795 (page_to_phys(page
) & (1 << 17)) != 0;
797 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
798 user_data
, page_do_bit17_swizzling
,
803 mutex_unlock(&dev
->struct_mutex
);
805 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
806 ret
= fault_in_multipages_writeable(user_data
, remain
);
807 /* Userspace is tricking us, but we've already clobbered
808 * its pages with the prefault and promised to write the
809 * data up to the first fault. Hence ignore any errors
810 * and just continue. */
815 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
816 user_data
, page_do_bit17_swizzling
,
819 mutex_lock(&dev
->struct_mutex
);
825 remain
-= page_length
;
826 user_data
+= page_length
;
827 offset
+= page_length
;
831 i915_gem_object_unpin_pages(obj
);
837 * Reads data from the object referenced by handle.
838 * @dev: drm device pointer
839 * @data: ioctl data blob
840 * @file: drm file pointer
842 * On error, the contents of *data are undefined.
845 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
846 struct drm_file
*file
)
848 struct drm_i915_gem_pread
*args
= data
;
849 struct drm_i915_gem_object
*obj
;
855 if (!access_ok(VERIFY_WRITE
,
856 u64_to_user_ptr(args
->data_ptr
),
860 ret
= i915_mutex_lock_interruptible(dev
);
864 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
865 if (&obj
->base
== NULL
) {
870 /* Bounds check source. */
871 if (args
->offset
> obj
->base
.size
||
872 args
->size
> obj
->base
.size
- args
->offset
) {
877 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
879 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
881 /* pread for non shmem backed objects */
882 if (ret
== -EFAULT
|| ret
== -ENODEV
)
883 ret
= i915_gem_gtt_pread(dev
, obj
, args
->size
,
884 args
->offset
, args
->data_ptr
);
887 drm_gem_object_unreference(&obj
->base
);
889 mutex_unlock(&dev
->struct_mutex
);
893 /* This is the fast write path which cannot handle
894 * page faults in the source data
898 fast_user_write(struct io_mapping
*mapping
,
899 loff_t page_base
, int page_offset
,
900 char __user
*user_data
,
903 void __iomem
*vaddr_atomic
;
905 unsigned long unwritten
;
907 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
908 /* We can use the cpu mem copy function because this is X86. */
909 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
910 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
912 io_mapping_unmap_atomic(vaddr_atomic
);
917 * This is the fast pwrite path, where we copy the data directly from the
918 * user into the GTT, uncached.
919 * @dev: drm device pointer
920 * @obj: i915 gem object
921 * @args: pwrite arguments structure
922 * @file: drm file pointer
925 i915_gem_gtt_pwrite_fast(struct drm_i915_private
*i915
,
926 struct drm_i915_gem_object
*obj
,
927 struct drm_i915_gem_pwrite
*args
,
928 struct drm_file
*file
)
930 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
931 struct drm_device
*dev
= obj
->base
.dev
;
932 struct drm_mm_node node
;
933 uint64_t remain
, offset
;
934 char __user
*user_data
;
936 bool hit_slow_path
= false;
938 if (obj
->tiling_mode
!= I915_TILING_NONE
)
941 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
943 ret
= insert_mappable_node(i915
, &node
, PAGE_SIZE
);
947 ret
= i915_gem_object_get_pages(obj
);
949 remove_mappable_node(&node
);
953 i915_gem_object_pin_pages(obj
);
955 node
.start
= i915_gem_obj_ggtt_offset(obj
);
956 node
.allocated
= false;
957 ret
= i915_gem_object_put_fence(obj
);
962 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
966 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
969 user_data
= u64_to_user_ptr(args
->data_ptr
);
970 offset
= args
->offset
;
973 /* Operation in this page
975 * page_base = page offset within aperture
976 * page_offset = offset within page
977 * page_length = bytes to copy for this page
979 u32 page_base
= node
.start
;
980 unsigned page_offset
= offset_in_page(offset
);
981 unsigned page_length
= PAGE_SIZE
- page_offset
;
982 page_length
= remain
< page_length
? remain
: page_length
;
983 if (node
.allocated
) {
984 wmb(); /* flush the write before we modify the GGTT */
985 ggtt
->base
.insert_page(&ggtt
->base
,
986 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
987 node
.start
, I915_CACHE_NONE
, 0);
988 wmb(); /* flush modifications to the GGTT (insert_page) */
990 page_base
+= offset
& PAGE_MASK
;
992 /* If we get a fault while copying data, then (presumably) our
993 * source page isn't available. Return the error and we'll
994 * retry in the slow path.
995 * If the object is non-shmem backed, we retry again with the
996 * path that handles page fault.
998 if (fast_user_write(ggtt
->mappable
, page_base
,
999 page_offset
, user_data
, page_length
)) {
1000 hit_slow_path
= true;
1001 mutex_unlock(&dev
->struct_mutex
);
1002 if (slow_user_access(ggtt
->mappable
,
1004 page_offset
, user_data
,
1005 page_length
, true)) {
1007 mutex_lock(&dev
->struct_mutex
);
1011 mutex_lock(&dev
->struct_mutex
);
1014 remain
-= page_length
;
1015 user_data
+= page_length
;
1016 offset
+= page_length
;
1020 if (hit_slow_path
) {
1022 (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0) {
1023 /* The user has modified the object whilst we tried
1024 * reading from it, and we now have no idea what domain
1025 * the pages should be in. As we have just been touching
1026 * them directly, flush everything back to the GTT
1029 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1033 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
1035 if (node
.allocated
) {
1037 ggtt
->base
.clear_range(&ggtt
->base
,
1038 node
.start
, node
.size
,
1040 i915_gem_object_unpin_pages(obj
);
1041 remove_mappable_node(&node
);
1043 i915_gem_object_ggtt_unpin(obj
);
1049 /* Per-page copy function for the shmem pwrite fastpath.
1050 * Flushes invalid cachelines before writing to the target if
1051 * needs_clflush_before is set and flushes out any written cachelines after
1052 * writing if needs_clflush is set. */
1054 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
1055 char __user
*user_data
,
1056 bool page_do_bit17_swizzling
,
1057 bool needs_clflush_before
,
1058 bool needs_clflush_after
)
1063 if (unlikely(page_do_bit17_swizzling
))
1066 vaddr
= kmap_atomic(page
);
1067 if (needs_clflush_before
)
1068 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
1070 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
1071 user_data
, page_length
);
1072 if (needs_clflush_after
)
1073 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
1075 kunmap_atomic(vaddr
);
1077 return ret
? -EFAULT
: 0;
1080 /* Only difference to the fast-path function is that this can handle bit17
1081 * and uses non-atomic copy and kmap functions. */
1083 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
1084 char __user
*user_data
,
1085 bool page_do_bit17_swizzling
,
1086 bool needs_clflush_before
,
1087 bool needs_clflush_after
)
1093 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1094 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
1096 page_do_bit17_swizzling
);
1097 if (page_do_bit17_swizzling
)
1098 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
1102 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
1105 if (needs_clflush_after
)
1106 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
1108 page_do_bit17_swizzling
);
1111 return ret
? -EFAULT
: 0;
1115 i915_gem_shmem_pwrite(struct drm_device
*dev
,
1116 struct drm_i915_gem_object
*obj
,
1117 struct drm_i915_gem_pwrite
*args
,
1118 struct drm_file
*file
)
1122 char __user
*user_data
;
1123 int shmem_page_offset
, page_length
, ret
= 0;
1124 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
1125 int hit_slowpath
= 0;
1126 int needs_clflush_after
= 0;
1127 int needs_clflush_before
= 0;
1128 struct sg_page_iter sg_iter
;
1130 user_data
= u64_to_user_ptr(args
->data_ptr
);
1131 remain
= args
->size
;
1133 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
1135 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1136 /* If we're not in the cpu write domain, set ourself into the gtt
1137 * write domain and manually flush cachelines (if required). This
1138 * optimizes for the case when the gpu will use the data
1139 * right away and we therefore have to clflush anyway. */
1140 needs_clflush_after
= cpu_write_needs_clflush(obj
);
1141 ret
= i915_gem_object_wait_rendering(obj
, false);
1145 /* Same trick applies to invalidate partially written cachelines read
1146 * before writing. */
1147 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
1148 needs_clflush_before
=
1149 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
1151 ret
= i915_gem_object_get_pages(obj
);
1155 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1157 i915_gem_object_pin_pages(obj
);
1159 offset
= args
->offset
;
1162 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
1163 offset
>> PAGE_SHIFT
) {
1164 struct page
*page
= sg_page_iter_page(&sg_iter
);
1165 int partial_cacheline_write
;
1170 /* Operation in this page
1172 * shmem_page_offset = offset within page in shmem file
1173 * page_length = bytes to copy for this page
1175 shmem_page_offset
= offset_in_page(offset
);
1177 page_length
= remain
;
1178 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
1179 page_length
= PAGE_SIZE
- shmem_page_offset
;
1181 /* If we don't overwrite a cacheline completely we need to be
1182 * careful to have up-to-date data by first clflushing. Don't
1183 * overcomplicate things and flush the entire patch. */
1184 partial_cacheline_write
= needs_clflush_before
&&
1185 ((shmem_page_offset
| page_length
)
1186 & (boot_cpu_data
.x86_clflush_size
- 1));
1188 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
1189 (page_to_phys(page
) & (1 << 17)) != 0;
1191 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
1192 user_data
, page_do_bit17_swizzling
,
1193 partial_cacheline_write
,
1194 needs_clflush_after
);
1199 mutex_unlock(&dev
->struct_mutex
);
1200 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1201 user_data
, page_do_bit17_swizzling
,
1202 partial_cacheline_write
,
1203 needs_clflush_after
);
1205 mutex_lock(&dev
->struct_mutex
);
1211 remain
-= page_length
;
1212 user_data
+= page_length
;
1213 offset
+= page_length
;
1217 i915_gem_object_unpin_pages(obj
);
1221 * Fixup: Flush cpu caches in case we didn't flush the dirty
1222 * cachelines in-line while writing and the object moved
1223 * out of the cpu write domain while we've dropped the lock.
1225 if (!needs_clflush_after
&&
1226 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1227 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1228 needs_clflush_after
= true;
1232 if (needs_clflush_after
)
1233 i915_gem_chipset_flush(to_i915(dev
));
1235 obj
->cache_dirty
= true;
1237 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1242 * Writes data to the object referenced by handle.
1244 * @data: ioctl data blob
1247 * On error, the contents of the buffer that were to be modified are undefined.
1250 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1251 struct drm_file
*file
)
1253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1254 struct drm_i915_gem_pwrite
*args
= data
;
1255 struct drm_i915_gem_object
*obj
;
1258 if (args
->size
== 0)
1261 if (!access_ok(VERIFY_READ
,
1262 u64_to_user_ptr(args
->data_ptr
),
1266 if (likely(!i915
.prefault_disable
)) {
1267 ret
= fault_in_multipages_readable(u64_to_user_ptr(args
->data_ptr
),
1273 intel_runtime_pm_get(dev_priv
);
1275 ret
= i915_mutex_lock_interruptible(dev
);
1279 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1280 if (&obj
->base
== NULL
) {
1285 /* Bounds check destination. */
1286 if (args
->offset
> obj
->base
.size
||
1287 args
->size
> obj
->base
.size
- args
->offset
) {
1292 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1295 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1296 * it would end up going through the fenced access, and we'll get
1297 * different detiling behavior between reading and writing.
1298 * pread/pwrite currently are reading and writing from the CPU
1299 * perspective, requiring manual detiling by the client.
1301 if (!i915_gem_object_has_struct_page(obj
) ||
1302 cpu_write_needs_clflush(obj
)) {
1303 ret
= i915_gem_gtt_pwrite_fast(dev_priv
, obj
, args
, file
);
1304 /* Note that the gtt paths might fail with non-page-backed user
1305 * pointers (e.g. gtt mappings when moving data between
1306 * textures). Fallback to the shmem path in that case. */
1309 if (ret
== -EFAULT
) {
1310 if (obj
->phys_handle
)
1311 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1312 else if (i915_gem_object_has_struct_page(obj
))
1313 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1319 drm_gem_object_unreference(&obj
->base
);
1321 mutex_unlock(&dev
->struct_mutex
);
1323 intel_runtime_pm_put(dev_priv
);
1329 i915_gem_check_wedge(unsigned reset_counter
, bool interruptible
)
1331 if (__i915_terminally_wedged(reset_counter
))
1334 if (__i915_reset_in_progress(reset_counter
)) {
1335 /* Non-interruptible callers can't handle -EAGAIN, hence return
1336 * -EIO unconditionally for these. */
1346 static unsigned long local_clock_us(unsigned *cpu
)
1350 /* Cheaply and approximately convert from nanoseconds to microseconds.
1351 * The result and subsequent calculations are also defined in the same
1352 * approximate microseconds units. The principal source of timing
1353 * error here is from the simple truncation.
1355 * Note that local_clock() is only defined wrt to the current CPU;
1356 * the comparisons are no longer valid if we switch CPUs. Instead of
1357 * blocking preemption for the entire busywait, we can detect the CPU
1358 * switch and use that as indicator of system load and a reason to
1359 * stop busywaiting, see busywait_stop().
1362 t
= local_clock() >> 10;
1368 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1372 if (time_after(local_clock_us(&this_cpu
), timeout
))
1375 return this_cpu
!= cpu
;
1378 bool __i915_spin_request(const struct drm_i915_gem_request
*req
,
1379 int state
, unsigned long timeout_us
)
1383 /* When waiting for high frequency requests, e.g. during synchronous
1384 * rendering split between the CPU and GPU, the finite amount of time
1385 * required to set up the irq and wait upon it limits the response
1386 * rate. By busywaiting on the request completion for a short while we
1387 * can service the high frequency waits as quick as possible. However,
1388 * if it is a slow request, we want to sleep as quickly as possible.
1389 * The tradeoff between waiting and sleeping is roughly the time it
1390 * takes to sleep on a request, on the order of a microsecond.
1393 timeout_us
+= local_clock_us(&cpu
);
1395 if (i915_gem_request_completed(req
))
1398 if (signal_pending_state(state
, current
))
1401 if (busywait_stop(timeout_us
, cpu
))
1404 cpu_relax_lowlatency();
1405 } while (!need_resched());
1411 * __i915_wait_request - wait until execution of request has finished
1413 * @interruptible: do an interruptible wait (normally yes)
1414 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1417 * Note: It is of utmost importance that the passed in seqno and reset_counter
1418 * values have been read by the caller in an smp safe manner. Where read-side
1419 * locks are involved, it is sufficient to read the reset_counter before
1420 * unlocking the lock that protects the seqno. For lockless tricks, the
1421 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1424 * Returns 0 if the request was found within the alloted time. Else returns the
1425 * errno with remaining time filled in timeout argument.
1427 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1430 struct intel_rps_client
*rps
)
1432 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1434 struct intel_wait wait
;
1435 unsigned long timeout_remain
;
1436 s64 before
= 0; /* Only to silence a compiler warning. */
1441 if (list_empty(&req
->list
))
1444 if (i915_gem_request_completed(req
))
1447 timeout_remain
= MAX_SCHEDULE_TIMEOUT
;
1449 if (WARN_ON(*timeout
< 0))
1455 timeout_remain
= nsecs_to_jiffies_timeout(*timeout
);
1458 * Record current time in case interrupted by signal, or wedged.
1460 before
= ktime_get_raw_ns();
1463 trace_i915_gem_request_wait_begin(req
);
1465 if (INTEL_INFO(req
->i915
)->gen
>= 6)
1466 gen6_rps_boost(req
->i915
, rps
, req
->emitted_jiffies
);
1468 /* Optimistic spin for the next ~jiffie before touching IRQs */
1469 if (i915_spin_request(req
, state
, 5))
1472 set_current_state(state
);
1473 add_wait_queue(&req
->i915
->gpu_error
.wait_queue
, &reset
);
1475 intel_wait_init(&wait
, req
->seqno
);
1476 if (intel_engine_add_wait(req
->engine
, &wait
))
1477 /* In order to check that we haven't missed the interrupt
1478 * as we enabled it, we need to kick ourselves to do a
1479 * coherent check on the seqno before we sleep.
1484 if (signal_pending_state(state
, current
)) {
1489 /* Ensure that even if the GPU hangs, we get woken up.
1491 * However, note that if no one is waiting, we never notice
1492 * a gpu hang. Eventually, we will have to wait for a resource
1493 * held by the GPU and so trigger a hangcheck. In the most
1494 * pathological case, this will be upon memory starvation!
1496 i915_queue_hangcheck(req
->i915
);
1498 timeout_remain
= io_schedule_timeout(timeout_remain
);
1499 if (timeout_remain
== 0) {
1504 if (intel_wait_complete(&wait
))
1507 set_current_state(state
);
1510 /* Carefully check if the request is complete, giving time
1511 * for the seqno to be visible following the interrupt.
1512 * We also have to check in case we are kicked by the GPU
1513 * reset in order to drop the struct_mutex.
1515 if (__i915_request_irq_complete(req
))
1518 /* Only spin if we know the GPU is processing this request */
1519 if (i915_spin_request(req
, state
, 2))
1522 remove_wait_queue(&req
->i915
->gpu_error
.wait_queue
, &reset
);
1524 intel_engine_remove_wait(req
->engine
, &wait
);
1525 __set_current_state(TASK_RUNNING
);
1527 trace_i915_gem_request_wait_end(req
);
1530 s64 tres
= *timeout
- (ktime_get_raw_ns() - before
);
1532 *timeout
= tres
< 0 ? 0 : tres
;
1535 * Apparently ktime isn't accurate enough and occasionally has a
1536 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1537 * things up to make the test happy. We allow up to 1 jiffy.
1539 * This is a regrssion from the timespec->ktime conversion.
1541 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1548 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1549 struct drm_file
*file
)
1551 struct drm_i915_file_private
*file_priv
;
1553 WARN_ON(!req
|| !file
|| req
->file_priv
);
1561 file_priv
= file
->driver_priv
;
1563 spin_lock(&file_priv
->mm
.lock
);
1564 req
->file_priv
= file_priv
;
1565 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1566 spin_unlock(&file_priv
->mm
.lock
);
1568 req
->pid
= get_pid(task_pid(current
));
1574 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1576 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1581 spin_lock(&file_priv
->mm
.lock
);
1582 list_del(&request
->client_list
);
1583 request
->file_priv
= NULL
;
1584 spin_unlock(&file_priv
->mm
.lock
);
1586 put_pid(request
->pid
);
1587 request
->pid
= NULL
;
1590 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1592 trace_i915_gem_request_retire(request
);
1594 /* We know the GPU must have read the request to have
1595 * sent us the seqno + interrupt, so use the position
1596 * of tail of the request to update the last known position
1599 * Note this requires that we are always called in request
1602 request
->ringbuf
->last_retired_head
= request
->postfix
;
1604 list_del_init(&request
->list
);
1605 i915_gem_request_remove_from_client(request
);
1607 if (request
->previous_context
) {
1608 if (i915
.enable_execlists
)
1609 intel_lr_context_unpin(request
->previous_context
,
1613 i915_gem_context_unreference(request
->ctx
);
1614 i915_gem_request_unreference(request
);
1618 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1620 struct intel_engine_cs
*engine
= req
->engine
;
1621 struct drm_i915_gem_request
*tmp
;
1623 lockdep_assert_held(&engine
->i915
->dev
->struct_mutex
);
1625 if (list_empty(&req
->list
))
1629 tmp
= list_first_entry(&engine
->request_list
,
1630 typeof(*tmp
), list
);
1632 i915_gem_request_retire(tmp
);
1633 } while (tmp
!= req
);
1635 WARN_ON(i915_verify_lists(engine
->dev
));
1639 * Waits for a request to be signaled, and cleans up the
1640 * request and object lists appropriately for that event.
1641 * @req: request to wait on
1644 i915_wait_request(struct drm_i915_gem_request
*req
)
1646 struct drm_i915_private
*dev_priv
= req
->i915
;
1650 interruptible
= dev_priv
->mm
.interruptible
;
1652 BUG_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
1654 ret
= __i915_wait_request(req
, interruptible
, NULL
, NULL
);
1658 /* If the GPU hung, we want to keep the requests to find the guilty. */
1659 if (!i915_reset_in_progress(&dev_priv
->gpu_error
))
1660 __i915_gem_request_retire__upto(req
);
1666 * Ensures that all rendering to the object has completed and the object is
1667 * safe to unbind from the GTT or access from the CPU.
1668 * @obj: i915 gem object
1669 * @readonly: waiting for read access or write
1672 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1681 if (obj
->last_write_req
!= NULL
) {
1682 ret
= i915_wait_request(obj
->last_write_req
);
1686 i
= obj
->last_write_req
->engine
->id
;
1687 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1688 i915_gem_object_retire__read(obj
, i
);
1690 i915_gem_object_retire__write(obj
);
1693 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1694 if (obj
->last_read_req
[i
] == NULL
)
1697 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1701 i915_gem_object_retire__read(obj
, i
);
1703 GEM_BUG_ON(obj
->active
);
1710 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1711 struct drm_i915_gem_request
*req
)
1713 int ring
= req
->engine
->id
;
1715 if (obj
->last_read_req
[ring
] == req
)
1716 i915_gem_object_retire__read(obj
, ring
);
1717 else if (obj
->last_write_req
== req
)
1718 i915_gem_object_retire__write(obj
);
1720 if (!i915_reset_in_progress(&req
->i915
->gpu_error
))
1721 __i915_gem_request_retire__upto(req
);
1724 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1725 * as the object state may change during this call.
1727 static __must_check
int
1728 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1729 struct intel_rps_client
*rps
,
1732 struct drm_device
*dev
= obj
->base
.dev
;
1733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1734 struct drm_i915_gem_request
*requests
[I915_NUM_ENGINES
];
1737 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1738 BUG_ON(!dev_priv
->mm
.interruptible
);
1744 struct drm_i915_gem_request
*req
;
1746 req
= obj
->last_write_req
;
1750 requests
[n
++] = i915_gem_request_reference(req
);
1752 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1753 struct drm_i915_gem_request
*req
;
1755 req
= obj
->last_read_req
[i
];
1759 requests
[n
++] = i915_gem_request_reference(req
);
1763 mutex_unlock(&dev
->struct_mutex
);
1765 for (i
= 0; ret
== 0 && i
< n
; i
++)
1766 ret
= __i915_wait_request(requests
[i
], true, NULL
, rps
);
1767 mutex_lock(&dev
->struct_mutex
);
1769 for (i
= 0; i
< n
; i
++) {
1771 i915_gem_object_retire_request(obj
, requests
[i
]);
1772 i915_gem_request_unreference(requests
[i
]);
1778 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1780 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1784 static enum fb_op_origin
1785 write_origin(struct drm_i915_gem_object
*obj
, unsigned domain
)
1787 return domain
== I915_GEM_DOMAIN_GTT
&& !obj
->has_wc_mmap
?
1788 ORIGIN_GTT
: ORIGIN_CPU
;
1792 * Called when user space prepares to use an object with the CPU, either
1793 * through the mmap ioctl's mapping or a GTT mapping.
1795 * @data: ioctl data blob
1799 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1800 struct drm_file
*file
)
1802 struct drm_i915_gem_set_domain
*args
= data
;
1803 struct drm_i915_gem_object
*obj
;
1804 uint32_t read_domains
= args
->read_domains
;
1805 uint32_t write_domain
= args
->write_domain
;
1808 /* Only handle setting domains to types used by the CPU. */
1809 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1812 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1815 /* Having something in the write domain implies it's in the read
1816 * domain, and only that read domain. Enforce that in the request.
1818 if (write_domain
!= 0 && read_domains
!= write_domain
)
1821 ret
= i915_mutex_lock_interruptible(dev
);
1825 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1826 if (&obj
->base
== NULL
) {
1831 /* Try to flush the object off the GPU without holding the lock.
1832 * We will repeat the flush holding the lock in the normal manner
1833 * to catch cases where we are gazumped.
1835 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1836 to_rps_client(file
),
1841 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1842 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1844 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1846 if (write_domain
!= 0)
1847 intel_fb_obj_invalidate(obj
, write_origin(obj
, write_domain
));
1850 drm_gem_object_unreference(&obj
->base
);
1852 mutex_unlock(&dev
->struct_mutex
);
1857 * Called when user space has done writes to this buffer
1859 * @data: ioctl data blob
1863 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1864 struct drm_file
*file
)
1866 struct drm_i915_gem_sw_finish
*args
= data
;
1867 struct drm_i915_gem_object
*obj
;
1870 ret
= i915_mutex_lock_interruptible(dev
);
1874 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1875 if (&obj
->base
== NULL
) {
1880 /* Pinned buffers may be scanout, so flush the cache */
1881 if (obj
->pin_display
)
1882 i915_gem_object_flush_cpu_write_domain(obj
);
1884 drm_gem_object_unreference(&obj
->base
);
1886 mutex_unlock(&dev
->struct_mutex
);
1891 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1894 * @data: ioctl data blob
1897 * While the mapping holds a reference on the contents of the object, it doesn't
1898 * imply a ref on the object itself.
1902 * DRM driver writers who look a this function as an example for how to do GEM
1903 * mmap support, please don't implement mmap support like here. The modern way
1904 * to implement DRM mmap support is with an mmap offset ioctl (like
1905 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1906 * That way debug tooling like valgrind will understand what's going on, hiding
1907 * the mmap call in a driver private ioctl will break that. The i915 driver only
1908 * does cpu mmaps this way because we didn't know better.
1911 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1912 struct drm_file
*file
)
1914 struct drm_i915_gem_mmap
*args
= data
;
1915 struct drm_gem_object
*obj
;
1918 if (args
->flags
& ~(I915_MMAP_WC
))
1921 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1924 obj
= drm_gem_object_lookup(file
, args
->handle
);
1928 /* prime objects have no backing filp to GEM mmap
1932 drm_gem_object_unreference_unlocked(obj
);
1936 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1937 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1939 if (args
->flags
& I915_MMAP_WC
) {
1940 struct mm_struct
*mm
= current
->mm
;
1941 struct vm_area_struct
*vma
;
1943 if (down_write_killable(&mm
->mmap_sem
)) {
1944 drm_gem_object_unreference_unlocked(obj
);
1947 vma
= find_vma(mm
, addr
);
1950 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1953 up_write(&mm
->mmap_sem
);
1955 /* This may race, but that's ok, it only gets set */
1956 WRITE_ONCE(to_intel_bo(obj
)->has_wc_mmap
, true);
1958 drm_gem_object_unreference_unlocked(obj
);
1959 if (IS_ERR((void *)addr
))
1962 args
->addr_ptr
= (uint64_t) addr
;
1968 * i915_gem_fault - fault a page into the GTT
1969 * @vma: VMA in question
1972 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1973 * from userspace. The fault handler takes care of binding the object to
1974 * the GTT (if needed), allocating and programming a fence register (again,
1975 * only if needed based on whether the old reg is still valid or the object
1976 * is tiled) and inserting a new PTE into the faulting process.
1978 * Note that the faulting process may involve evicting existing objects
1979 * from the GTT and/or fence registers to make room. So performance may
1980 * suffer if the GTT working set is large or there are few fence registers
1983 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1985 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1986 struct drm_device
*dev
= obj
->base
.dev
;
1987 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1988 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1989 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1990 pgoff_t page_offset
;
1993 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1995 intel_runtime_pm_get(dev_priv
);
1997 /* We don't use vmf->pgoff since that has the fake offset */
1998 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
2001 ret
= i915_mutex_lock_interruptible(dev
);
2005 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
2007 /* Try to flush the object off the GPU first without holding the lock.
2008 * Upon reacquiring the lock, we will perform our sanity checks and then
2009 * repeat the flush holding the lock in the normal manner to catch cases
2010 * where we are gazumped.
2012 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
2016 /* Access to snoopable pages through the GTT is incoherent. */
2017 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
2022 /* Use a partial view if the object is bigger than the aperture. */
2023 if (obj
->base
.size
>= ggtt
->mappable_end
&&
2024 obj
->tiling_mode
== I915_TILING_NONE
) {
2025 static const unsigned int chunk_size
= 256; // 1 MiB
2027 memset(&view
, 0, sizeof(view
));
2028 view
.type
= I915_GGTT_VIEW_PARTIAL
;
2029 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
2030 view
.params
.partial
.size
=
2033 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
2034 view
.params
.partial
.offset
);
2037 /* Now pin it into the GTT if needed */
2038 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
2042 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
2046 ret
= i915_gem_object_get_fence(obj
);
2050 /* Finally, remap it using the new GTT offset */
2051 pfn
= ggtt
->mappable_base
+
2052 i915_gem_obj_ggtt_offset_view(obj
, &view
);
2055 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
2056 /* Overriding existing pages in partial view does not cause
2057 * us any trouble as TLBs are still valid because the fault
2058 * is due to userspace losing part of the mapping or never
2059 * having accessed it before (at this partials' range).
2061 unsigned long base
= vma
->vm_start
+
2062 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
2065 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
2066 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
2071 obj
->fault_mappable
= true;
2073 if (!obj
->fault_mappable
) {
2074 unsigned long size
= min_t(unsigned long,
2075 vma
->vm_end
- vma
->vm_start
,
2079 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
2080 ret
= vm_insert_pfn(vma
,
2081 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
2087 obj
->fault_mappable
= true;
2089 ret
= vm_insert_pfn(vma
,
2090 (unsigned long)vmf
->virtual_address
,
2094 i915_gem_object_ggtt_unpin_view(obj
, &view
);
2096 mutex_unlock(&dev
->struct_mutex
);
2101 * We eat errors when the gpu is terminally wedged to avoid
2102 * userspace unduly crashing (gl has no provisions for mmaps to
2103 * fail). But any other -EIO isn't ours (e.g. swap in failure)
2104 * and so needs to be reported.
2106 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
2107 ret
= VM_FAULT_SIGBUS
;
2112 * EAGAIN means the gpu is hung and we'll wait for the error
2113 * handler to reset everything when re-faulting in
2114 * i915_mutex_lock_interruptible.
2121 * EBUSY is ok: this just means that another thread
2122 * already did the job.
2124 ret
= VM_FAULT_NOPAGE
;
2131 ret
= VM_FAULT_SIGBUS
;
2134 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
2135 ret
= VM_FAULT_SIGBUS
;
2139 intel_runtime_pm_put(dev_priv
);
2144 * i915_gem_release_mmap - remove physical page mappings
2145 * @obj: obj in question
2147 * Preserve the reservation of the mmapping with the DRM core code, but
2148 * relinquish ownership of the pages back to the system.
2150 * It is vital that we remove the page mapping if we have mapped a tiled
2151 * object through the GTT and then lose the fence register due to
2152 * resource pressure. Similarly if the object has been moved out of the
2153 * aperture, than pages mapped into userspace must be revoked. Removing the
2154 * mapping will then trigger a page fault on the next user access, allowing
2155 * fixup by i915_gem_fault().
2158 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
2160 /* Serialisation between user GTT access and our code depends upon
2161 * revoking the CPU's PTE whilst the mutex is held. The next user
2162 * pagefault then has to wait until we release the mutex.
2164 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2166 if (!obj
->fault_mappable
)
2169 drm_vma_node_unmap(&obj
->base
.vma_node
,
2170 obj
->base
.dev
->anon_inode
->i_mapping
);
2172 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2173 * memory transactions from userspace before we return. The TLB
2174 * flushing implied above by changing the PTE above *should* be
2175 * sufficient, an extra barrier here just provides us with a bit
2176 * of paranoid documentation about our requirement to serialise
2177 * memory writes before touching registers / GSM.
2181 obj
->fault_mappable
= false;
2185 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
2187 struct drm_i915_gem_object
*obj
;
2189 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
2190 i915_gem_release_mmap(obj
);
2194 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
2198 if (INTEL_INFO(dev
)->gen
>= 4 ||
2199 tiling_mode
== I915_TILING_NONE
)
2202 /* Previous chips need a power-of-two fence region when tiling */
2204 gtt_size
= 1024*1024;
2206 gtt_size
= 512*1024;
2208 while (gtt_size
< size
)
2215 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2217 * @size: object size
2218 * @tiling_mode: tiling mode
2219 * @fenced: is fenced alignemned required or not
2221 * Return the required GTT alignment for an object, taking into account
2222 * potential fence register mapping.
2225 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2226 int tiling_mode
, bool fenced
)
2229 * Minimum alignment is 4k (GTT page size), but might be greater
2230 * if a fence register is needed for the object.
2232 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2233 tiling_mode
== I915_TILING_NONE
)
2237 * Previous chips need to be aligned to the size of the smallest
2238 * fence register that can contain the object.
2240 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2243 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2245 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2248 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2250 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2254 /* Badly fragmented mmap space? The only way we can recover
2255 * space is by destroying unwanted objects. We can't randomly release
2256 * mmap_offsets as userspace expects them to be persistent for the
2257 * lifetime of the objects. The closest we can is to release the
2258 * offsets on purgeable objects by truncating it and marking it purged,
2259 * which prevents userspace from ever using that object again.
2261 i915_gem_shrink(dev_priv
,
2262 obj
->base
.size
>> PAGE_SHIFT
,
2264 I915_SHRINK_UNBOUND
|
2265 I915_SHRINK_PURGEABLE
);
2266 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2270 i915_gem_shrink_all(dev_priv
);
2271 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2273 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2278 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2280 drm_gem_free_mmap_offset(&obj
->base
);
2284 i915_gem_mmap_gtt(struct drm_file
*file
,
2285 struct drm_device
*dev
,
2289 struct drm_i915_gem_object
*obj
;
2292 ret
= i915_mutex_lock_interruptible(dev
);
2296 obj
= to_intel_bo(drm_gem_object_lookup(file
, handle
));
2297 if (&obj
->base
== NULL
) {
2302 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2303 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2308 ret
= i915_gem_object_create_mmap_offset(obj
);
2312 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2315 drm_gem_object_unreference(&obj
->base
);
2317 mutex_unlock(&dev
->struct_mutex
);
2322 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2324 * @data: GTT mapping ioctl data
2325 * @file: GEM object info
2327 * Simply returns the fake offset to userspace so it can mmap it.
2328 * The mmap call will end up in drm_gem_mmap(), which will set things
2329 * up so we can get faults in the handler above.
2331 * The fault handler will take care of binding the object into the GTT
2332 * (since it may have been evicted to make room for something), allocating
2333 * a fence register, and mapping the appropriate aperture address into
2337 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2338 struct drm_file
*file
)
2340 struct drm_i915_gem_mmap_gtt
*args
= data
;
2342 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2345 /* Immediately discard the backing storage */
2347 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2349 i915_gem_object_free_mmap_offset(obj
);
2351 if (obj
->base
.filp
== NULL
)
2354 /* Our goal here is to return as much of the memory as
2355 * is possible back to the system as we are called from OOM.
2356 * To do this we must instruct the shmfs to drop all of its
2357 * backing pages, *now*.
2359 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2360 obj
->madv
= __I915_MADV_PURGED
;
2363 /* Try to discard unwanted pages */
2365 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2367 struct address_space
*mapping
;
2369 switch (obj
->madv
) {
2370 case I915_MADV_DONTNEED
:
2371 i915_gem_object_truncate(obj
);
2372 case __I915_MADV_PURGED
:
2376 if (obj
->base
.filp
== NULL
)
2379 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2380 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2384 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2386 struct sgt_iter sgt_iter
;
2390 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2392 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2394 /* In the event of a disaster, abandon all caches and
2395 * hope for the best.
2397 i915_gem_clflush_object(obj
, true);
2398 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2401 i915_gem_gtt_finish_object(obj
);
2403 if (i915_gem_object_needs_bit17_swizzle(obj
))
2404 i915_gem_object_save_bit_17_swizzle(obj
);
2406 if (obj
->madv
== I915_MADV_DONTNEED
)
2409 for_each_sgt_page(page
, sgt_iter
, obj
->pages
) {
2411 set_page_dirty(page
);
2413 if (obj
->madv
== I915_MADV_WILLNEED
)
2414 mark_page_accessed(page
);
2420 sg_free_table(obj
->pages
);
2425 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2427 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2429 if (obj
->pages
== NULL
)
2432 if (obj
->pages_pin_count
)
2435 BUG_ON(i915_gem_obj_bound_any(obj
));
2437 /* ->put_pages might need to allocate memory for the bit17 swizzle
2438 * array, hence protect them from being reaped by removing them from gtt
2440 list_del(&obj
->global_list
);
2443 if (is_vmalloc_addr(obj
->mapping
))
2444 vunmap(obj
->mapping
);
2446 kunmap(kmap_to_page(obj
->mapping
));
2447 obj
->mapping
= NULL
;
2450 ops
->put_pages(obj
);
2453 i915_gem_object_invalidate(obj
);
2459 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2461 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2463 struct address_space
*mapping
;
2464 struct sg_table
*st
;
2465 struct scatterlist
*sg
;
2466 struct sgt_iter sgt_iter
;
2468 unsigned long last_pfn
= 0; /* suppress gcc warning */
2472 /* Assert that the object is not currently in any GPU domain. As it
2473 * wasn't in the GTT, there shouldn't be any way it could have been in
2476 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2477 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2479 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2483 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2484 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2489 /* Get the list of pages out of our struct file. They'll be pinned
2490 * at this point until we release them.
2492 * Fail silently without starting the shrinker
2494 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2495 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2496 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2499 for (i
= 0; i
< page_count
; i
++) {
2500 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2502 i915_gem_shrink(dev_priv
,
2505 I915_SHRINK_UNBOUND
|
2506 I915_SHRINK_PURGEABLE
);
2507 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2510 /* We've tried hard to allocate the memory by reaping
2511 * our own buffer, now let the real VM do its job and
2512 * go down in flames if truly OOM.
2514 i915_gem_shrink_all(dev_priv
);
2515 page
= shmem_read_mapping_page(mapping
, i
);
2517 ret
= PTR_ERR(page
);
2521 #ifdef CONFIG_SWIOTLB
2522 if (swiotlb_nr_tbl()) {
2524 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2529 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2533 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2535 sg
->length
+= PAGE_SIZE
;
2537 last_pfn
= page_to_pfn(page
);
2539 /* Check that the i965g/gm workaround works. */
2540 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2542 #ifdef CONFIG_SWIOTLB
2543 if (!swiotlb_nr_tbl())
2548 ret
= i915_gem_gtt_prepare_object(obj
);
2552 if (i915_gem_object_needs_bit17_swizzle(obj
))
2553 i915_gem_object_do_bit_17_swizzle(obj
);
2555 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2556 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2557 i915_gem_object_pin_pages(obj
);
2563 for_each_sgt_page(page
, sgt_iter
, st
)
2568 /* shmemfs first checks if there is enough memory to allocate the page
2569 * and reports ENOSPC should there be insufficient, along with the usual
2570 * ENOMEM for a genuine allocation failure.
2572 * We use ENOSPC in our driver to mean that we have run out of aperture
2573 * space and so want to translate the error from shmemfs back to our
2574 * usual understanding of ENOMEM.
2582 /* Ensure that the associated pages are gathered from the backing storage
2583 * and pinned into our object. i915_gem_object_get_pages() may be called
2584 * multiple times before they are released by a single call to
2585 * i915_gem_object_put_pages() - once the pages are no longer referenced
2586 * either as a result of memory pressure (reaping pages under the shrinker)
2587 * or as the object is itself released.
2590 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2592 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2593 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2599 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2600 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2604 BUG_ON(obj
->pages_pin_count
);
2606 ret
= ops
->get_pages(obj
);
2610 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2612 obj
->get_page
.sg
= obj
->pages
->sgl
;
2613 obj
->get_page
.last
= 0;
2618 /* The 'mapping' part of i915_gem_object_pin_map() below */
2619 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
)
2621 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2622 struct sg_table
*sgt
= obj
->pages
;
2623 struct sgt_iter sgt_iter
;
2625 struct page
*stack_pages
[32];
2626 struct page
**pages
= stack_pages
;
2627 unsigned long i
= 0;
2630 /* A single page can always be kmapped */
2632 return kmap(sg_page(sgt
->sgl
));
2634 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2635 /* Too big for stack -- allocate temporary array instead */
2636 pages
= drm_malloc_gfp(n_pages
, sizeof(*pages
), GFP_TEMPORARY
);
2641 for_each_sgt_page(page
, sgt_iter
, sgt
)
2644 /* Check that we have the expected number of pages */
2645 GEM_BUG_ON(i
!= n_pages
);
2647 addr
= vmap(pages
, n_pages
, 0, PAGE_KERNEL
);
2649 if (pages
!= stack_pages
)
2650 drm_free_large(pages
);
2655 /* get, pin, and map the pages of the object into kernel space */
2656 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
)
2660 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2662 ret
= i915_gem_object_get_pages(obj
);
2664 return ERR_PTR(ret
);
2666 i915_gem_object_pin_pages(obj
);
2668 if (!obj
->mapping
) {
2669 obj
->mapping
= i915_gem_object_map(obj
);
2670 if (!obj
->mapping
) {
2671 i915_gem_object_unpin_pages(obj
);
2672 return ERR_PTR(-ENOMEM
);
2676 return obj
->mapping
;
2679 void i915_vma_move_to_active(struct i915_vma
*vma
,
2680 struct drm_i915_gem_request
*req
)
2682 struct drm_i915_gem_object
*obj
= vma
->obj
;
2683 struct intel_engine_cs
*engine
;
2685 engine
= i915_gem_request_get_engine(req
);
2687 /* Add a reference if we're newly entering the active list. */
2688 if (obj
->active
== 0)
2689 drm_gem_object_reference(&obj
->base
);
2690 obj
->active
|= intel_engine_flag(engine
);
2692 list_move_tail(&obj
->engine_list
[engine
->id
], &engine
->active_list
);
2693 i915_gem_request_assign(&obj
->last_read_req
[engine
->id
], req
);
2695 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
2699 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2701 GEM_BUG_ON(obj
->last_write_req
== NULL
);
2702 GEM_BUG_ON(!(obj
->active
& intel_engine_flag(obj
->last_write_req
->engine
)));
2704 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2705 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2709 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2711 struct i915_vma
*vma
;
2713 GEM_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2714 GEM_BUG_ON(!(obj
->active
& (1 << ring
)));
2716 list_del_init(&obj
->engine_list
[ring
]);
2717 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2719 if (obj
->last_write_req
&& obj
->last_write_req
->engine
->id
== ring
)
2720 i915_gem_object_retire__write(obj
);
2722 obj
->active
&= ~(1 << ring
);
2726 /* Bump our place on the bound list to keep it roughly in LRU order
2727 * so that we don't steal from recently used but inactive objects
2728 * (unless we are forced to ofc!)
2730 list_move_tail(&obj
->global_list
,
2731 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2733 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
2734 if (!list_empty(&vma
->vm_link
))
2735 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
2738 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2739 drm_gem_object_unreference(&obj
->base
);
2743 i915_gem_init_seqno(struct drm_i915_private
*dev_priv
, u32 seqno
)
2745 struct intel_engine_cs
*engine
;
2748 /* Carefully retire all requests without writing to the rings */
2749 for_each_engine(engine
, dev_priv
) {
2750 ret
= intel_engine_idle(engine
);
2754 i915_gem_retire_requests(dev_priv
);
2756 /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
2757 if (!i915_seqno_passed(seqno
, dev_priv
->next_seqno
)) {
2758 while (intel_kick_waiters(dev_priv
))
2762 /* Finally reset hw state */
2763 for_each_engine(engine
, dev_priv
)
2764 intel_ring_init_seqno(engine
, seqno
);
2769 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2777 /* HWS page needs to be set less than what we
2778 * will inject to ring
2780 ret
= i915_gem_init_seqno(dev_priv
, seqno
- 1);
2784 /* Carefully set the last_seqno value so that wrap
2785 * detection still works
2787 dev_priv
->next_seqno
= seqno
;
2788 dev_priv
->last_seqno
= seqno
- 1;
2789 if (dev_priv
->last_seqno
== 0)
2790 dev_priv
->last_seqno
--;
2796 i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
)
2798 /* reserve 0 for non-seqno */
2799 if (dev_priv
->next_seqno
== 0) {
2800 int ret
= i915_gem_init_seqno(dev_priv
, 0);
2804 dev_priv
->next_seqno
= 1;
2807 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2812 * NB: This function is not allowed to fail. Doing so would mean the the
2813 * request is not being tracked for completion but the work itself is
2814 * going to happen on the hardware. This would be a Bad Thing(tm).
2816 void __i915_add_request(struct drm_i915_gem_request
*request
,
2817 struct drm_i915_gem_object
*obj
,
2820 struct intel_engine_cs
*engine
;
2821 struct drm_i915_private
*dev_priv
;
2822 struct intel_ringbuffer
*ringbuf
;
2827 if (WARN_ON(request
== NULL
))
2830 engine
= request
->engine
;
2831 dev_priv
= request
->i915
;
2832 ringbuf
= request
->ringbuf
;
2835 * To ensure that this call will not fail, space for its emissions
2836 * should already have been reserved in the ring buffer. Let the ring
2837 * know that it is time to use that space up.
2839 request_start
= intel_ring_get_tail(ringbuf
);
2840 reserved_tail
= request
->reserved_space
;
2841 request
->reserved_space
= 0;
2844 * Emit any outstanding flushes - execbuf can fail to emit the flush
2845 * after having emitted the batchbuffer command. Hence we need to fix
2846 * things up similar to emitting the lazy request. The difference here
2847 * is that the flush _must_ happen before the next request, no matter
2851 if (i915
.enable_execlists
)
2852 ret
= logical_ring_flush_all_caches(request
);
2854 ret
= intel_ring_flush_all_caches(request
);
2855 /* Not allowed to fail! */
2856 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2859 trace_i915_gem_request_add(request
);
2861 request
->head
= request_start
;
2863 /* Whilst this request exists, batch_obj will be on the
2864 * active_list, and so will hold the active reference. Only when this
2865 * request is retired will the the batch_obj be moved onto the
2866 * inactive_list and lose its active reference. Hence we do not need
2867 * to explicitly hold another reference here.
2869 request
->batch_obj
= obj
;
2871 /* Seal the request and mark it as pending execution. Note that
2872 * we may inspect this state, without holding any locks, during
2873 * hangcheck. Hence we apply the barrier to ensure that we do not
2874 * see a more recent value in the hws than we are tracking.
2876 request
->emitted_jiffies
= jiffies
;
2877 request
->previous_seqno
= engine
->last_submitted_seqno
;
2878 smp_store_mb(engine
->last_submitted_seqno
, request
->seqno
);
2879 list_add_tail(&request
->list
, &engine
->request_list
);
2881 /* Record the position of the start of the request so that
2882 * should we detect the updated seqno part-way through the
2883 * GPU processing the request, we never over-estimate the
2884 * position of the head.
2886 request
->postfix
= intel_ring_get_tail(ringbuf
);
2888 if (i915
.enable_execlists
)
2889 ret
= engine
->emit_request(request
);
2891 ret
= engine
->add_request(request
);
2893 request
->tail
= intel_ring_get_tail(ringbuf
);
2895 /* Not allowed to fail! */
2896 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2898 queue_delayed_work(dev_priv
->wq
,
2899 &dev_priv
->mm
.retire_work
,
2900 round_jiffies_up_relative(HZ
));
2901 intel_mark_busy(dev_priv
);
2903 /* Sanity check that the reserved size was large enough. */
2904 ret
= intel_ring_get_tail(ringbuf
) - request_start
;
2906 ret
+= ringbuf
->size
;
2907 WARN_ONCE(ret
> reserved_tail
,
2908 "Not enough space reserved (%d bytes) "
2909 "for adding the request (%d bytes)\n",
2910 reserved_tail
, ret
);
2913 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2914 const struct i915_gem_context
*ctx
)
2916 unsigned long elapsed
;
2918 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2920 if (ctx
->hang_stats
.banned
)
2923 if (ctx
->hang_stats
.ban_period_seconds
&&
2924 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2925 if (!i915_gem_context_is_default(ctx
)) {
2926 DRM_DEBUG("context hanging too fast, banning!\n");
2928 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2929 if (i915_stop_ring_allow_warn(dev_priv
))
2930 DRM_ERROR("gpu hanging too fast, banning!\n");
2938 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2939 struct i915_gem_context
*ctx
,
2942 struct i915_ctx_hang_stats
*hs
;
2947 hs
= &ctx
->hang_stats
;
2950 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2952 hs
->guilty_ts
= get_seconds();
2954 hs
->batch_pending
++;
2958 void i915_gem_request_free(struct kref
*req_ref
)
2960 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2962 kmem_cache_free(req
->i915
->requests
, req
);
2966 __i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2967 struct i915_gem_context
*ctx
,
2968 struct drm_i915_gem_request
**req_out
)
2970 struct drm_i915_private
*dev_priv
= engine
->i915
;
2971 unsigned reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
2972 struct drm_i915_gem_request
*req
;
2980 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2981 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2984 ret
= i915_gem_check_wedge(reset_counter
, dev_priv
->mm
.interruptible
);
2988 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2992 ret
= i915_gem_get_seqno(engine
->i915
, &req
->seqno
);
2996 kref_init(&req
->ref
);
2997 req
->i915
= dev_priv
;
2998 req
->engine
= engine
;
3000 i915_gem_context_reference(req
->ctx
);
3003 * Reserve space in the ring buffer for all the commands required to
3004 * eventually emit this request. This is to guarantee that the
3005 * i915_add_request() call can't fail. Note that the reserve may need
3006 * to be redone if the request is not actually submitted straight
3007 * away, e.g. because a GPU scheduler has deferred it.
3009 req
->reserved_space
= MIN_SPACE_FOR_ADD_REQUEST
;
3011 if (i915
.enable_execlists
)
3012 ret
= intel_logical_ring_alloc_request_extras(req
);
3014 ret
= intel_ring_alloc_request_extras(req
);
3022 i915_gem_context_unreference(ctx
);
3024 kmem_cache_free(dev_priv
->requests
, req
);
3029 * i915_gem_request_alloc - allocate a request structure
3031 * @engine: engine that we wish to issue the request on.
3032 * @ctx: context that the request will be associated with.
3033 * This can be NULL if the request is not directly related to
3034 * any specific user context, in which case this function will
3035 * choose an appropriate context to use.
3037 * Returns a pointer to the allocated request if successful,
3038 * or an error code if not.
3040 struct drm_i915_gem_request
*
3041 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
3042 struct i915_gem_context
*ctx
)
3044 struct drm_i915_gem_request
*req
;
3048 ctx
= engine
->i915
->kernel_context
;
3049 err
= __i915_gem_request_alloc(engine
, ctx
, &req
);
3050 return err
? ERR_PTR(err
) : req
;
3053 struct drm_i915_gem_request
*
3054 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
3056 struct drm_i915_gem_request
*request
;
3058 /* We are called by the error capture and reset at a random
3059 * point in time. In particular, note that neither is crucially
3060 * ordered with an interrupt. After a hang, the GPU is dead and we
3061 * assume that no more writes can happen (we waited long enough for
3062 * all writes that were in transaction to be flushed) - adding an
3063 * extra delay for a recent interrupt is pointless. Hence, we do
3064 * not need an engine->irq_seqno_barrier() before the seqno reads.
3066 list_for_each_entry(request
, &engine
->request_list
, list
) {
3067 if (i915_gem_request_completed(request
))
3076 static void i915_gem_reset_engine_status(struct drm_i915_private
*dev_priv
,
3077 struct intel_engine_cs
*engine
)
3079 struct drm_i915_gem_request
*request
;
3082 request
= i915_gem_find_active_request(engine
);
3084 if (request
== NULL
)
3087 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
3089 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
3091 list_for_each_entry_continue(request
, &engine
->request_list
, list
)
3092 i915_set_reset_status(dev_priv
, request
->ctx
, false);
3095 static void i915_gem_reset_engine_cleanup(struct drm_i915_private
*dev_priv
,
3096 struct intel_engine_cs
*engine
)
3098 struct intel_ringbuffer
*buffer
;
3100 while (!list_empty(&engine
->active_list
)) {
3101 struct drm_i915_gem_object
*obj
;
3103 obj
= list_first_entry(&engine
->active_list
,
3104 struct drm_i915_gem_object
,
3105 engine_list
[engine
->id
]);
3107 i915_gem_object_retire__read(obj
, engine
->id
);
3111 * Clear the execlists queue up before freeing the requests, as those
3112 * are the ones that keep the context and ringbuffer backing objects
3116 if (i915
.enable_execlists
) {
3117 /* Ensure irq handler finishes or is cancelled. */
3118 tasklet_kill(&engine
->irq_tasklet
);
3120 intel_execlists_cancel_requests(engine
);
3124 * We must free the requests after all the corresponding objects have
3125 * been moved off active lists. Which is the same order as the normal
3126 * retire_requests function does. This is important if object hold
3127 * implicit references on things like e.g. ppgtt address spaces through
3130 while (!list_empty(&engine
->request_list
)) {
3131 struct drm_i915_gem_request
*request
;
3133 request
= list_first_entry(&engine
->request_list
,
3134 struct drm_i915_gem_request
,
3137 i915_gem_request_retire(request
);
3140 /* Having flushed all requests from all queues, we know that all
3141 * ringbuffers must now be empty. However, since we do not reclaim
3142 * all space when retiring the request (to prevent HEADs colliding
3143 * with rapid ringbuffer wraparound) the amount of available space
3144 * upon reset is less than when we start. Do one more pass over
3145 * all the ringbuffers to reset last_retired_head.
3147 list_for_each_entry(buffer
, &engine
->buffers
, link
) {
3148 buffer
->last_retired_head
= buffer
->tail
;
3149 intel_ring_update_space(buffer
);
3152 intel_ring_init_seqno(engine
, engine
->last_submitted_seqno
);
3155 void i915_gem_reset(struct drm_device
*dev
)
3157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3158 struct intel_engine_cs
*engine
;
3161 * Before we free the objects from the requests, we need to inspect
3162 * them for finding the guilty party. As the requests only borrow
3163 * their reference to the objects, the inspection must be done first.
3165 for_each_engine(engine
, dev_priv
)
3166 i915_gem_reset_engine_status(dev_priv
, engine
);
3168 for_each_engine(engine
, dev_priv
)
3169 i915_gem_reset_engine_cleanup(dev_priv
, engine
);
3171 i915_gem_context_reset(dev
);
3173 i915_gem_restore_fences(dev
);
3175 WARN_ON(i915_verify_lists(dev
));
3179 * This function clears the request list as sequence numbers are passed.
3180 * @engine: engine to retire requests on
3183 i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
)
3185 WARN_ON(i915_verify_lists(engine
->dev
));
3187 /* Retire requests first as we use it above for the early return.
3188 * If we retire requests last, we may use a later seqno and so clear
3189 * the requests lists without clearing the active list, leading to
3192 while (!list_empty(&engine
->request_list
)) {
3193 struct drm_i915_gem_request
*request
;
3195 request
= list_first_entry(&engine
->request_list
,
3196 struct drm_i915_gem_request
,
3199 if (!i915_gem_request_completed(request
))
3202 i915_gem_request_retire(request
);
3205 /* Move any buffers on the active list that are no longer referenced
3206 * by the ringbuffer to the flushing/inactive lists as appropriate,
3207 * before we free the context associated with the requests.
3209 while (!list_empty(&engine
->active_list
)) {
3210 struct drm_i915_gem_object
*obj
;
3212 obj
= list_first_entry(&engine
->active_list
,
3213 struct drm_i915_gem_object
,
3214 engine_list
[engine
->id
]);
3216 if (!list_empty(&obj
->last_read_req
[engine
->id
]->list
))
3219 i915_gem_object_retire__read(obj
, engine
->id
);
3222 if (unlikely(engine
->trace_irq_req
&&
3223 i915_gem_request_completed(engine
->trace_irq_req
))) {
3224 engine
->irq_put(engine
);
3225 i915_gem_request_assign(&engine
->trace_irq_req
, NULL
);
3228 WARN_ON(i915_verify_lists(engine
->dev
));
3232 i915_gem_retire_requests(struct drm_i915_private
*dev_priv
)
3234 struct intel_engine_cs
*engine
;
3237 for_each_engine(engine
, dev_priv
) {
3238 i915_gem_retire_requests_ring(engine
);
3239 idle
&= list_empty(&engine
->request_list
);
3240 if (i915
.enable_execlists
) {
3241 spin_lock_bh(&engine
->execlist_lock
);
3242 idle
&= list_empty(&engine
->execlist_queue
);
3243 spin_unlock_bh(&engine
->execlist_lock
);
3248 mod_delayed_work(dev_priv
->wq
,
3249 &dev_priv
->mm
.idle_work
,
3250 msecs_to_jiffies(100));
3256 i915_gem_retire_work_handler(struct work_struct
*work
)
3258 struct drm_i915_private
*dev_priv
=
3259 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
3260 struct drm_device
*dev
= dev_priv
->dev
;
3263 /* Come back later if the device is busy... */
3265 if (mutex_trylock(&dev
->struct_mutex
)) {
3266 idle
= i915_gem_retire_requests(dev_priv
);
3267 mutex_unlock(&dev
->struct_mutex
);
3270 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3271 round_jiffies_up_relative(HZ
));
3275 i915_gem_idle_work_handler(struct work_struct
*work
)
3277 struct drm_i915_private
*dev_priv
=
3278 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3279 struct drm_device
*dev
= dev_priv
->dev
;
3280 struct intel_engine_cs
*engine
;
3282 for_each_engine(engine
, dev_priv
)
3283 if (!list_empty(&engine
->request_list
))
3286 /* we probably should sync with hangcheck here, using cancel_work_sync.
3287 * Also locking seems to be fubar here, engine->request_list is protected
3288 * by dev->struct_mutex. */
3290 intel_mark_idle(dev_priv
);
3292 if (mutex_trylock(&dev
->struct_mutex
)) {
3293 for_each_engine(engine
, dev_priv
)
3294 i915_gem_batch_pool_fini(&engine
->batch_pool
);
3296 mutex_unlock(&dev
->struct_mutex
);
3301 * Ensures that an object will eventually get non-busy by flushing any required
3302 * write domains, emitting any outstanding lazy request and retiring and
3303 * completed requests.
3304 * @obj: object to flush
3307 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3314 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3315 struct drm_i915_gem_request
*req
;
3317 req
= obj
->last_read_req
[i
];
3321 if (i915_gem_request_completed(req
))
3322 i915_gem_object_retire__read(obj
, i
);
3329 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3330 * @dev: drm device pointer
3331 * @data: ioctl data blob
3332 * @file: drm file pointer
3334 * Returns 0 if successful, else an error is returned with the remaining time in
3335 * the timeout parameter.
3336 * -ETIME: object is still busy after timeout
3337 * -ERESTARTSYS: signal interrupted the wait
3338 * -ENONENT: object doesn't exist
3339 * Also possible, but rare:
3340 * -EAGAIN: GPU wedged
3342 * -ENODEV: Internal IRQ fail
3343 * -E?: The add request failed
3345 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3346 * non-zero timeout parameter the wait ioctl will wait for the given number of
3347 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3348 * without holding struct_mutex the object may become re-busied before this
3349 * function completes. A similar but shorter * race condition exists in the busy
3353 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3355 struct drm_i915_gem_wait
*args
= data
;
3356 struct drm_i915_gem_object
*obj
;
3357 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3361 if (args
->flags
!= 0)
3364 ret
= i915_mutex_lock_interruptible(dev
);
3368 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->bo_handle
));
3369 if (&obj
->base
== NULL
) {
3370 mutex_unlock(&dev
->struct_mutex
);
3374 /* Need to make sure the object gets inactive eventually. */
3375 ret
= i915_gem_object_flush_active(obj
);
3382 /* Do this after OLR check to make sure we make forward progress polling
3383 * on this IOCTL with a timeout == 0 (like busy ioctl)
3385 if (args
->timeout_ns
== 0) {
3390 drm_gem_object_unreference(&obj
->base
);
3392 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3393 if (obj
->last_read_req
[i
] == NULL
)
3396 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3399 mutex_unlock(&dev
->struct_mutex
);
3401 for (i
= 0; i
< n
; i
++) {
3403 ret
= __i915_wait_request(req
[i
], true,
3404 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3405 to_rps_client(file
));
3406 i915_gem_request_unreference(req
[i
]);
3411 drm_gem_object_unreference(&obj
->base
);
3412 mutex_unlock(&dev
->struct_mutex
);
3417 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3418 struct intel_engine_cs
*to
,
3419 struct drm_i915_gem_request
*from_req
,
3420 struct drm_i915_gem_request
**to_req
)
3422 struct intel_engine_cs
*from
;
3425 from
= i915_gem_request_get_engine(from_req
);
3429 if (i915_gem_request_completed(from_req
))
3432 if (!i915_semaphore_is_enabled(to_i915(obj
->base
.dev
))) {
3433 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3434 ret
= __i915_wait_request(from_req
,
3435 i915
->mm
.interruptible
,
3437 &i915
->rps
.semaphores
);
3441 i915_gem_object_retire_request(obj
, from_req
);
3443 int idx
= intel_ring_sync_index(from
, to
);
3444 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3448 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3451 if (*to_req
== NULL
) {
3452 struct drm_i915_gem_request
*req
;
3454 req
= i915_gem_request_alloc(to
, NULL
);
3456 return PTR_ERR(req
);
3461 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3462 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3466 /* We use last_read_req because sync_to()
3467 * might have just caused seqno wrap under
3470 from
->semaphore
.sync_seqno
[idx
] =
3471 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3478 * i915_gem_object_sync - sync an object to a ring.
3480 * @obj: object which may be in use on another ring.
3481 * @to: ring we wish to use the object on. May be NULL.
3482 * @to_req: request we wish to use the object for. See below.
3483 * This will be allocated and returned if a request is
3484 * required but not passed in.
3486 * This code is meant to abstract object synchronization with the GPU.
3487 * Calling with NULL implies synchronizing the object with the CPU
3488 * rather than a particular GPU ring. Conceptually we serialise writes
3489 * between engines inside the GPU. We only allow one engine to write
3490 * into a buffer at any time, but multiple readers. To ensure each has
3491 * a coherent view of memory, we must:
3493 * - If there is an outstanding write request to the object, the new
3494 * request must wait for it to complete (either CPU or in hw, requests
3495 * on the same ring will be naturally ordered).
3497 * - If we are a write request (pending_write_domain is set), the new
3498 * request must wait for outstanding read requests to complete.
3500 * For CPU synchronisation (NULL to) no request is required. For syncing with
3501 * rings to_req must be non-NULL. However, a request does not have to be
3502 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3503 * request will be allocated automatically and returned through *to_req. Note
3504 * that it is not guaranteed that commands will be emitted (because the system
3505 * might already be idle). Hence there is no need to create a request that
3506 * might never have any work submitted. Note further that if a request is
3507 * returned in *to_req, it is the responsibility of the caller to submit
3508 * that request (after potentially adding more work to it).
3510 * Returns 0 if successful, else propagates up the lower layer error.
3513 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3514 struct intel_engine_cs
*to
,
3515 struct drm_i915_gem_request
**to_req
)
3517 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3518 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3525 return i915_gem_object_wait_rendering(obj
, readonly
);
3529 if (obj
->last_write_req
)
3530 req
[n
++] = obj
->last_write_req
;
3532 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
3533 if (obj
->last_read_req
[i
])
3534 req
[n
++] = obj
->last_read_req
[i
];
3536 for (i
= 0; i
< n
; i
++) {
3537 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3545 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3547 u32 old_write_domain
, old_read_domains
;
3549 /* Force a pagefault for domain tracking on next user access */
3550 i915_gem_release_mmap(obj
);
3552 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3555 old_read_domains
= obj
->base
.read_domains
;
3556 old_write_domain
= obj
->base
.write_domain
;
3558 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3559 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3561 trace_i915_gem_object_change_domain(obj
,
3566 static void __i915_vma_iounmap(struct i915_vma
*vma
)
3568 GEM_BUG_ON(vma
->pin_count
);
3570 if (vma
->iomap
== NULL
)
3573 io_mapping_unmap(vma
->iomap
);
3577 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3579 struct drm_i915_gem_object
*obj
= vma
->obj
;
3580 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3583 if (list_empty(&vma
->obj_link
))
3586 if (!drm_mm_node_allocated(&vma
->node
)) {
3587 i915_gem_vma_destroy(vma
);
3594 BUG_ON(obj
->pages
== NULL
);
3597 ret
= i915_gem_object_wait_rendering(obj
, false);
3602 if (vma
->is_ggtt
&& vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3603 i915_gem_object_finish_gtt(obj
);
3605 /* release the fence reg _after_ flushing */
3606 ret
= i915_gem_object_put_fence(obj
);
3610 __i915_vma_iounmap(vma
);
3613 trace_i915_vma_unbind(vma
);
3615 vma
->vm
->unbind_vma(vma
);
3618 list_del_init(&vma
->vm_link
);
3620 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3621 obj
->map_and_fenceable
= false;
3622 } else if (vma
->ggtt_view
.pages
) {
3623 sg_free_table(vma
->ggtt_view
.pages
);
3624 kfree(vma
->ggtt_view
.pages
);
3626 vma
->ggtt_view
.pages
= NULL
;
3629 drm_mm_remove_node(&vma
->node
);
3630 i915_gem_vma_destroy(vma
);
3632 /* Since the unbound list is global, only move to that list if
3633 * no more VMAs exist. */
3634 if (list_empty(&obj
->vma_list
))
3635 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3637 /* And finally now the object is completely decoupled from this vma,
3638 * we can drop its hold on the backing storage and allow it to be
3639 * reaped by the shrinker.
3641 i915_gem_object_unpin_pages(obj
);
3646 int i915_vma_unbind(struct i915_vma
*vma
)
3648 return __i915_vma_unbind(vma
, true);
3651 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3653 return __i915_vma_unbind(vma
, false);
3656 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
)
3658 struct intel_engine_cs
*engine
;
3661 lockdep_assert_held(&dev_priv
->dev
->struct_mutex
);
3663 for_each_engine(engine
, dev_priv
) {
3664 if (engine
->last_context
== NULL
)
3667 ret
= intel_engine_idle(engine
);
3672 WARN_ON(i915_verify_lists(dev
));
3676 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3677 unsigned long cache_level
)
3679 struct drm_mm_node
*gtt_space
= &vma
->node
;
3680 struct drm_mm_node
*other
;
3683 * On some machines we have to be careful when putting differing types
3684 * of snoopable memory together to avoid the prefetcher crossing memory
3685 * domains and dying. During vm initialisation, we decide whether or not
3686 * these constraints apply and set the drm_mm.color_adjust
3689 if (vma
->vm
->mm
.color_adjust
== NULL
)
3692 if (!drm_mm_node_allocated(gtt_space
))
3695 if (list_empty(>t_space
->node_list
))
3698 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3699 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3702 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3703 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3710 * Finds free space in the GTT aperture and binds the object or a view of it
3712 * @obj: object to bind
3713 * @vm: address space to bind into
3714 * @ggtt_view: global gtt view if applicable
3715 * @alignment: requested alignment
3716 * @flags: mask of PIN_* flags to use
3718 static struct i915_vma
*
3719 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3720 struct i915_address_space
*vm
,
3721 const struct i915_ggtt_view
*ggtt_view
,
3725 struct drm_device
*dev
= obj
->base
.dev
;
3726 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3727 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3728 u32 fence_alignment
, unfenced_alignment
;
3729 u32 search_flag
, alloc_flag
;
3731 u64 size
, fence_size
;
3732 struct i915_vma
*vma
;
3735 if (i915_is_ggtt(vm
)) {
3738 if (WARN_ON(!ggtt_view
))
3739 return ERR_PTR(-EINVAL
);
3741 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3743 fence_size
= i915_gem_get_gtt_size(dev
,
3746 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3750 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3754 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3756 fence_size
= i915_gem_get_gtt_size(dev
,
3759 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3763 unfenced_alignment
=
3764 i915_gem_get_gtt_alignment(dev
,
3768 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3771 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3773 if (flags
& PIN_MAPPABLE
)
3774 end
= min_t(u64
, end
, ggtt
->mappable_end
);
3775 if (flags
& PIN_ZONE_4G
)
3776 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3779 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3781 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3782 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3783 ggtt_view
? ggtt_view
->type
: 0,
3785 return ERR_PTR(-EINVAL
);
3788 /* If binding the object/GGTT view requires more space than the entire
3789 * aperture has, reject it early before evicting everything in a vain
3790 * attempt to find space.
3793 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3794 ggtt_view
? ggtt_view
->type
: 0,
3796 flags
& PIN_MAPPABLE
? "mappable" : "total",
3798 return ERR_PTR(-E2BIG
);
3801 ret
= i915_gem_object_get_pages(obj
);
3803 return ERR_PTR(ret
);
3805 i915_gem_object_pin_pages(obj
);
3807 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3808 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3813 if (flags
& PIN_OFFSET_FIXED
) {
3814 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3816 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3820 vma
->node
.start
= offset
;
3821 vma
->node
.size
= size
;
3822 vma
->node
.color
= obj
->cache_level
;
3823 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3825 ret
= i915_gem_evict_for_vma(vma
);
3827 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3832 if (flags
& PIN_HIGH
) {
3833 search_flag
= DRM_MM_SEARCH_BELOW
;
3834 alloc_flag
= DRM_MM_CREATE_TOP
;
3836 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3837 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3841 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3848 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3858 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3860 goto err_remove_node
;
3863 trace_i915_vma_bind(vma
, flags
);
3864 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3866 goto err_remove_node
;
3868 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3869 list_add_tail(&vma
->vm_link
, &vm
->inactive_list
);
3874 drm_mm_remove_node(&vma
->node
);
3876 i915_gem_vma_destroy(vma
);
3879 i915_gem_object_unpin_pages(obj
);
3884 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3887 /* If we don't have a page list set up, then we're not pinned
3888 * to GPU, and we can ignore the cache flush because it'll happen
3889 * again at bind time.
3891 if (obj
->pages
== NULL
)
3895 * Stolen memory is always coherent with the GPU as it is explicitly
3896 * marked as wc by the system, or the system is cache-coherent.
3898 if (obj
->stolen
|| obj
->phys_handle
)
3901 /* If the GPU is snooping the contents of the CPU cache,
3902 * we do not need to manually clear the CPU cache lines. However,
3903 * the caches are only snooped when the render cache is
3904 * flushed/invalidated. As we always have to emit invalidations
3905 * and flushes when moving into and out of the RENDER domain, correct
3906 * snooping behaviour occurs naturally as the result of our domain
3909 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3910 obj
->cache_dirty
= true;
3914 trace_i915_gem_object_clflush(obj
);
3915 drm_clflush_sg(obj
->pages
);
3916 obj
->cache_dirty
= false;
3921 /** Flushes the GTT write domain for the object if it's dirty. */
3923 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3925 uint32_t old_write_domain
;
3927 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3930 /* No actual flushing is required for the GTT write domain. Writes
3931 * to it immediately go to main memory as far as we know, so there's
3932 * no chipset flush. It also doesn't land in render cache.
3934 * However, we do have to enforce the order so that all writes through
3935 * the GTT land before any writes to the device, such as updates to
3940 old_write_domain
= obj
->base
.write_domain
;
3941 obj
->base
.write_domain
= 0;
3943 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3945 trace_i915_gem_object_change_domain(obj
,
3946 obj
->base
.read_domains
,
3950 /** Flushes the CPU write domain for the object if it's dirty. */
3952 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3954 uint32_t old_write_domain
;
3956 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3959 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3960 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
3962 old_write_domain
= obj
->base
.write_domain
;
3963 obj
->base
.write_domain
= 0;
3965 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3967 trace_i915_gem_object_change_domain(obj
,
3968 obj
->base
.read_domains
,
3973 * Moves a single object to the GTT read, and possibly write domain.
3974 * @obj: object to act on
3975 * @write: ask for write access or read only
3977 * This function returns when the move is complete, including waiting on
3981 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3983 struct drm_device
*dev
= obj
->base
.dev
;
3984 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3985 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3986 uint32_t old_write_domain
, old_read_domains
;
3987 struct i915_vma
*vma
;
3990 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3993 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3997 /* Flush and acquire obj->pages so that we are coherent through
3998 * direct access in memory with previous cached writes through
3999 * shmemfs and that our cache domain tracking remains valid.
4000 * For example, if the obj->filp was moved to swap without us
4001 * being notified and releasing the pages, we would mistakenly
4002 * continue to assume that the obj remained out of the CPU cached
4005 ret
= i915_gem_object_get_pages(obj
);
4009 i915_gem_object_flush_cpu_write_domain(obj
);
4011 /* Serialise direct access to this object with the barriers for
4012 * coherent writes from the GPU, by effectively invalidating the
4013 * GTT domain upon first access.
4015 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
4018 old_write_domain
= obj
->base
.write_domain
;
4019 old_read_domains
= obj
->base
.read_domains
;
4021 /* It should now be out of any other write domains, and we can update
4022 * the domain values for our changes.
4024 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
4025 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4027 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
4028 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
4032 trace_i915_gem_object_change_domain(obj
,
4036 /* And bump the LRU for this access */
4037 vma
= i915_gem_obj_to_ggtt(obj
);
4038 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
4039 list_move_tail(&vma
->vm_link
,
4040 &ggtt
->base
.inactive_list
);
4046 * Changes the cache-level of an object across all VMA.
4047 * @obj: object to act on
4048 * @cache_level: new cache level to set for the object
4050 * After this function returns, the object will be in the new cache-level
4051 * across all GTT and the contents of the backing storage will be coherent,
4052 * with respect to the new cache-level. In order to keep the backing storage
4053 * coherent for all users, we only allow a single cache level to be set
4054 * globally on the object and prevent it from being changed whilst the
4055 * hardware is reading from the object. That is if the object is currently
4056 * on the scanout it will be set to uncached (or equivalent display
4057 * cache coherency) and all non-MOCS GPU access will also be uncached so
4058 * that all direct access to the scanout remains coherent.
4060 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
4061 enum i915_cache_level cache_level
)
4063 struct drm_device
*dev
= obj
->base
.dev
;
4064 struct i915_vma
*vma
, *next
;
4068 if (obj
->cache_level
== cache_level
)
4071 /* Inspect the list of currently bound VMA and unbind any that would
4072 * be invalid given the new cache-level. This is principally to
4073 * catch the issue of the CS prefetch crossing page boundaries and
4074 * reading an invalid PTE on older architectures.
4076 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4077 if (!drm_mm_node_allocated(&vma
->node
))
4080 if (vma
->pin_count
) {
4081 DRM_DEBUG("can not change the cache level of pinned objects\n");
4085 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
4086 ret
= i915_vma_unbind(vma
);
4093 /* We can reuse the existing drm_mm nodes but need to change the
4094 * cache-level on the PTE. We could simply unbind them all and
4095 * rebind with the correct cache-level on next use. However since
4096 * we already have a valid slot, dma mapping, pages etc, we may as
4097 * rewrite the PTE in the belief that doing so tramples upon less
4098 * state and so involves less work.
4101 /* Before we change the PTE, the GPU must not be accessing it.
4102 * If we wait upon the object, we know that all the bound
4103 * VMA are no longer active.
4105 ret
= i915_gem_object_wait_rendering(obj
, false);
4109 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
4110 /* Access to snoopable pages through the GTT is
4111 * incoherent and on some machines causes a hard
4112 * lockup. Relinquish the CPU mmaping to force
4113 * userspace to refault in the pages and we can
4114 * then double check if the GTT mapping is still
4115 * valid for that pointer access.
4117 i915_gem_release_mmap(obj
);
4119 /* As we no longer need a fence for GTT access,
4120 * we can relinquish it now (and so prevent having
4121 * to steal a fence from someone else on the next
4122 * fence request). Note GPU activity would have
4123 * dropped the fence as all snoopable access is
4124 * supposed to be linear.
4126 ret
= i915_gem_object_put_fence(obj
);
4130 /* We either have incoherent backing store and
4131 * so no GTT access or the architecture is fully
4132 * coherent. In such cases, existing GTT mmaps
4133 * ignore the cache bit in the PTE and we can
4134 * rewrite it without confusing the GPU or having
4135 * to force userspace to fault back in its mmaps.
4139 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4140 if (!drm_mm_node_allocated(&vma
->node
))
4143 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
4149 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4150 vma
->node
.color
= cache_level
;
4151 obj
->cache_level
= cache_level
;
4154 /* Flush the dirty CPU caches to the backing storage so that the
4155 * object is now coherent at its new cache level (with respect
4156 * to the access domain).
4158 if (obj
->cache_dirty
&& cpu_write_needs_clflush(obj
)) {
4159 if (i915_gem_clflush_object(obj
, true))
4160 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
4166 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4167 struct drm_file
*file
)
4169 struct drm_i915_gem_caching
*args
= data
;
4170 struct drm_i915_gem_object
*obj
;
4172 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4173 if (&obj
->base
== NULL
)
4176 switch (obj
->cache_level
) {
4177 case I915_CACHE_LLC
:
4178 case I915_CACHE_L3_LLC
:
4179 args
->caching
= I915_CACHING_CACHED
;
4183 args
->caching
= I915_CACHING_DISPLAY
;
4187 args
->caching
= I915_CACHING_NONE
;
4191 drm_gem_object_unreference_unlocked(&obj
->base
);
4195 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4196 struct drm_file
*file
)
4198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4199 struct drm_i915_gem_caching
*args
= data
;
4200 struct drm_i915_gem_object
*obj
;
4201 enum i915_cache_level level
;
4204 switch (args
->caching
) {
4205 case I915_CACHING_NONE
:
4206 level
= I915_CACHE_NONE
;
4208 case I915_CACHING_CACHED
:
4210 * Due to a HW issue on BXT A stepping, GPU stores via a
4211 * snooped mapping may leave stale data in a corresponding CPU
4212 * cacheline, whereas normally such cachelines would get
4215 if (!HAS_LLC(dev
) && !HAS_SNOOP(dev
))
4218 level
= I915_CACHE_LLC
;
4220 case I915_CACHING_DISPLAY
:
4221 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4227 intel_runtime_pm_get(dev_priv
);
4229 ret
= i915_mutex_lock_interruptible(dev
);
4233 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4234 if (&obj
->base
== NULL
) {
4239 ret
= i915_gem_object_set_cache_level(obj
, level
);
4241 drm_gem_object_unreference(&obj
->base
);
4243 mutex_unlock(&dev
->struct_mutex
);
4245 intel_runtime_pm_put(dev_priv
);
4251 * Prepare buffer for display plane (scanout, cursors, etc).
4252 * Can be called from an uninterruptible phase (modesetting) and allows
4253 * any flushes to be pipelined (for pageflips).
4256 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4258 const struct i915_ggtt_view
*view
)
4260 u32 old_read_domains
, old_write_domain
;
4263 /* Mark the pin_display early so that we account for the
4264 * display coherency whilst setting up the cache domains.
4268 /* The display engine is not coherent with the LLC cache on gen6. As
4269 * a result, we make sure that the pinning that is about to occur is
4270 * done with uncached PTEs. This is lowest common denominator for all
4273 * However for gen6+, we could do better by using the GFDT bit instead
4274 * of uncaching, which would allow us to flush all the LLC-cached data
4275 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4277 ret
= i915_gem_object_set_cache_level(obj
,
4278 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4280 goto err_unpin_display
;
4282 /* As the user may map the buffer once pinned in the display plane
4283 * (e.g. libkms for the bootup splash), we have to ensure that we
4284 * always use map_and_fenceable for all scanout buffers.
4286 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4287 view
->type
== I915_GGTT_VIEW_NORMAL
?
4290 goto err_unpin_display
;
4292 i915_gem_object_flush_cpu_write_domain(obj
);
4294 old_write_domain
= obj
->base
.write_domain
;
4295 old_read_domains
= obj
->base
.read_domains
;
4297 /* It should now be out of any other write domains, and we can update
4298 * the domain values for our changes.
4300 obj
->base
.write_domain
= 0;
4301 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4303 trace_i915_gem_object_change_domain(obj
,
4315 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4316 const struct i915_ggtt_view
*view
)
4318 if (WARN_ON(obj
->pin_display
== 0))
4321 i915_gem_object_ggtt_unpin_view(obj
, view
);
4327 * Moves a single object to the CPU read, and possibly write domain.
4328 * @obj: object to act on
4329 * @write: requesting write or read-only access
4331 * This function returns when the move is complete, including waiting on
4335 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4337 uint32_t old_write_domain
, old_read_domains
;
4340 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4343 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4347 i915_gem_object_flush_gtt_write_domain(obj
);
4349 old_write_domain
= obj
->base
.write_domain
;
4350 old_read_domains
= obj
->base
.read_domains
;
4352 /* Flush the CPU cache if it's still invalid. */
4353 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4354 i915_gem_clflush_object(obj
, false);
4356 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4359 /* It should now be out of any other write domains, and we can update
4360 * the domain values for our changes.
4362 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4364 /* If we're writing through the CPU, then the GPU read domains will
4365 * need to be invalidated at next use.
4368 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4369 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4372 trace_i915_gem_object_change_domain(obj
,
4379 /* Throttle our rendering by waiting until the ring has completed our requests
4380 * emitted over 20 msec ago.
4382 * Note that if we were to use the current jiffies each time around the loop,
4383 * we wouldn't escape the function with any frames outstanding if the time to
4384 * render a frame was over 20ms.
4386 * This should get us reasonable parallelism between CPU and GPU but also
4387 * relatively low latency when blocking on a particular request to finish.
4390 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4393 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4394 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4395 struct drm_i915_gem_request
*request
, *target
= NULL
;
4398 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4402 /* ABI: return -EIO if already wedged */
4403 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
4406 spin_lock(&file_priv
->mm
.lock
);
4407 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4408 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4412 * Note that the request might not have been submitted yet.
4413 * In which case emitted_jiffies will be zero.
4415 if (!request
->emitted_jiffies
)
4421 i915_gem_request_reference(target
);
4422 spin_unlock(&file_priv
->mm
.lock
);
4427 ret
= __i915_wait_request(target
, true, NULL
, NULL
);
4429 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4431 i915_gem_request_unreference(target
);
4437 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4439 struct drm_i915_gem_object
*obj
= vma
->obj
;
4442 vma
->node
.start
& (alignment
- 1))
4445 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4448 if (flags
& PIN_OFFSET_BIAS
&&
4449 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4452 if (flags
& PIN_OFFSET_FIXED
&&
4453 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4459 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4461 struct drm_i915_gem_object
*obj
= vma
->obj
;
4462 bool mappable
, fenceable
;
4463 u32 fence_size
, fence_alignment
;
4465 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4468 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4473 fenceable
= (vma
->node
.size
== fence_size
&&
4474 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4476 mappable
= (vma
->node
.start
+ fence_size
<=
4477 to_i915(obj
->base
.dev
)->ggtt
.mappable_end
);
4479 obj
->map_and_fenceable
= mappable
&& fenceable
;
4483 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4484 struct i915_address_space
*vm
,
4485 const struct i915_ggtt_view
*ggtt_view
,
4489 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4490 struct i915_vma
*vma
;
4494 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4497 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4500 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4503 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4506 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4507 i915_gem_obj_to_vma(obj
, vm
);
4510 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4513 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4514 WARN(vma
->pin_count
,
4515 "bo is already pinned in %s with incorrect alignment:"
4516 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4517 " obj->map_and_fenceable=%d\n",
4518 ggtt_view
? "ggtt" : "ppgtt",
4519 upper_32_bits(vma
->node
.start
),
4520 lower_32_bits(vma
->node
.start
),
4522 !!(flags
& PIN_MAPPABLE
),
4523 obj
->map_and_fenceable
);
4524 ret
= i915_vma_unbind(vma
);
4532 bound
= vma
? vma
->bound
: 0;
4533 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4534 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4537 return PTR_ERR(vma
);
4539 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4544 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4545 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4546 __i915_vma_set_map_and_fenceable(vma
);
4547 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4555 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4556 struct i915_address_space
*vm
,
4560 return i915_gem_object_do_pin(obj
, vm
,
4561 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4566 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4567 const struct i915_ggtt_view
*view
,
4571 struct drm_device
*dev
= obj
->base
.dev
;
4572 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4573 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4577 return i915_gem_object_do_pin(obj
, &ggtt
->base
, view
,
4578 alignment
, flags
| PIN_GLOBAL
);
4582 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4583 const struct i915_ggtt_view
*view
)
4585 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4587 WARN_ON(vma
->pin_count
== 0);
4588 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4594 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4595 struct drm_file
*file
)
4597 struct drm_i915_gem_busy
*args
= data
;
4598 struct drm_i915_gem_object
*obj
;
4601 ret
= i915_mutex_lock_interruptible(dev
);
4605 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4606 if (&obj
->base
== NULL
) {
4611 /* Count all active objects as busy, even if they are currently not used
4612 * by the gpu. Users of this interface expect objects to eventually
4613 * become non-busy without any further actions, therefore emit any
4614 * necessary flushes here.
4616 ret
= i915_gem_object_flush_active(obj
);
4624 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
4625 struct drm_i915_gem_request
*req
;
4627 req
= obj
->last_read_req
[i
];
4629 args
->busy
|= 1 << (16 + req
->engine
->exec_id
);
4631 if (obj
->last_write_req
)
4632 args
->busy
|= obj
->last_write_req
->engine
->exec_id
;
4636 drm_gem_object_unreference(&obj
->base
);
4638 mutex_unlock(&dev
->struct_mutex
);
4643 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4644 struct drm_file
*file_priv
)
4646 return i915_gem_ring_throttle(dev
, file_priv
);
4650 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4651 struct drm_file
*file_priv
)
4653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4654 struct drm_i915_gem_madvise
*args
= data
;
4655 struct drm_i915_gem_object
*obj
;
4658 switch (args
->madv
) {
4659 case I915_MADV_DONTNEED
:
4660 case I915_MADV_WILLNEED
:
4666 ret
= i915_mutex_lock_interruptible(dev
);
4670 obj
= to_intel_bo(drm_gem_object_lookup(file_priv
, args
->handle
));
4671 if (&obj
->base
== NULL
) {
4676 if (i915_gem_obj_is_pinned(obj
)) {
4682 obj
->tiling_mode
!= I915_TILING_NONE
&&
4683 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4684 if (obj
->madv
== I915_MADV_WILLNEED
)
4685 i915_gem_object_unpin_pages(obj
);
4686 if (args
->madv
== I915_MADV_WILLNEED
)
4687 i915_gem_object_pin_pages(obj
);
4690 if (obj
->madv
!= __I915_MADV_PURGED
)
4691 obj
->madv
= args
->madv
;
4693 /* if the object is no longer attached, discard its backing storage */
4694 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4695 i915_gem_object_truncate(obj
);
4697 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4700 drm_gem_object_unreference(&obj
->base
);
4702 mutex_unlock(&dev
->struct_mutex
);
4706 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4707 const struct drm_i915_gem_object_ops
*ops
)
4711 INIT_LIST_HEAD(&obj
->global_list
);
4712 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
4713 INIT_LIST_HEAD(&obj
->engine_list
[i
]);
4714 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4715 INIT_LIST_HEAD(&obj
->vma_list
);
4716 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4720 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4721 obj
->madv
= I915_MADV_WILLNEED
;
4723 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4726 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4727 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4728 .get_pages
= i915_gem_object_get_pages_gtt
,
4729 .put_pages
= i915_gem_object_put_pages_gtt
,
4732 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
4735 struct drm_i915_gem_object
*obj
;
4736 struct address_space
*mapping
;
4740 obj
= i915_gem_object_alloc(dev
);
4742 return ERR_PTR(-ENOMEM
);
4744 ret
= drm_gem_object_init(dev
, &obj
->base
, size
);
4748 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4749 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4750 /* 965gm cannot relocate objects above 4GiB. */
4751 mask
&= ~__GFP_HIGHMEM
;
4752 mask
|= __GFP_DMA32
;
4755 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4756 mapping_set_gfp_mask(mapping
, mask
);
4758 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4760 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4761 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4764 /* On some devices, we can have the GPU use the LLC (the CPU
4765 * cache) for about a 10% performance improvement
4766 * compared to uncached. Graphics requests other than
4767 * display scanout are coherent with the CPU in
4768 * accessing this cache. This means in this mode we
4769 * don't need to clflush on the CPU side, and on the
4770 * GPU side we only need to flush internal caches to
4771 * get data visible to the CPU.
4773 * However, we maintain the display planes as UC, and so
4774 * need to rebind when first used as such.
4776 obj
->cache_level
= I915_CACHE_LLC
;
4778 obj
->cache_level
= I915_CACHE_NONE
;
4780 trace_i915_gem_object_create(obj
);
4785 i915_gem_object_free(obj
);
4787 return ERR_PTR(ret
);
4790 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4792 /* If we are the last user of the backing storage (be it shmemfs
4793 * pages or stolen etc), we know that the pages are going to be
4794 * immediately released. In this case, we can then skip copying
4795 * back the contents from the GPU.
4798 if (obj
->madv
!= I915_MADV_WILLNEED
)
4801 if (obj
->base
.filp
== NULL
)
4804 /* At first glance, this looks racy, but then again so would be
4805 * userspace racing mmap against close. However, the first external
4806 * reference to the filp can only be obtained through the
4807 * i915_gem_mmap_ioctl() which safeguards us against the user
4808 * acquiring such a reference whilst we are in the middle of
4809 * freeing the object.
4811 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4814 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4816 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4817 struct drm_device
*dev
= obj
->base
.dev
;
4818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4819 struct i915_vma
*vma
, *next
;
4821 intel_runtime_pm_get(dev_priv
);
4823 trace_i915_gem_object_destroy(obj
);
4825 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4829 ret
= i915_vma_unbind(vma
);
4830 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4831 bool was_interruptible
;
4833 was_interruptible
= dev_priv
->mm
.interruptible
;
4834 dev_priv
->mm
.interruptible
= false;
4836 WARN_ON(i915_vma_unbind(vma
));
4838 dev_priv
->mm
.interruptible
= was_interruptible
;
4842 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4843 * before progressing. */
4845 i915_gem_object_unpin_pages(obj
);
4847 WARN_ON(obj
->frontbuffer_bits
);
4849 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4850 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4851 obj
->tiling_mode
!= I915_TILING_NONE
)
4852 i915_gem_object_unpin_pages(obj
);
4854 if (WARN_ON(obj
->pages_pin_count
))
4855 obj
->pages_pin_count
= 0;
4856 if (discard_backing_storage(obj
))
4857 obj
->madv
= I915_MADV_DONTNEED
;
4858 i915_gem_object_put_pages(obj
);
4859 i915_gem_object_free_mmap_offset(obj
);
4863 if (obj
->base
.import_attach
)
4864 drm_prime_gem_destroy(&obj
->base
, NULL
);
4866 if (obj
->ops
->release
)
4867 obj
->ops
->release(obj
);
4869 drm_gem_object_release(&obj
->base
);
4870 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4873 i915_gem_object_free(obj
);
4875 intel_runtime_pm_put(dev_priv
);
4878 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4879 struct i915_address_space
*vm
)
4881 struct i915_vma
*vma
;
4882 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4883 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4890 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4891 const struct i915_ggtt_view
*view
)
4893 struct i915_vma
*vma
;
4897 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4898 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4903 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4905 WARN_ON(vma
->node
.allocated
);
4907 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4908 if (!list_empty(&vma
->exec_list
))
4912 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
4914 list_del(&vma
->obj_link
);
4916 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4920 i915_gem_stop_engines(struct drm_device
*dev
)
4922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4923 struct intel_engine_cs
*engine
;
4925 for_each_engine(engine
, dev_priv
)
4926 dev_priv
->gt
.stop_engine(engine
);
4930 i915_gem_suspend(struct drm_device
*dev
)
4932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4935 mutex_lock(&dev
->struct_mutex
);
4936 ret
= i915_gem_wait_for_idle(dev_priv
);
4940 i915_gem_retire_requests(dev_priv
);
4942 i915_gem_stop_engines(dev
);
4943 i915_gem_context_lost(dev_priv
);
4944 mutex_unlock(&dev
->struct_mutex
);
4946 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4947 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4948 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4950 /* Assert that we sucessfully flushed all the work and
4951 * reset the GPU back to its idle, low power state.
4953 WARN_ON(dev_priv
->mm
.busy
);
4958 mutex_unlock(&dev
->struct_mutex
);
4962 void i915_gem_init_swizzling(struct drm_device
*dev
)
4964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4966 if (INTEL_INFO(dev
)->gen
< 5 ||
4967 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4970 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4971 DISP_TILE_SURFACE_SWIZZLING
);
4976 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4978 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4979 else if (IS_GEN7(dev
))
4980 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4981 else if (IS_GEN8(dev
))
4982 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4987 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4991 I915_WRITE(RING_CTL(base
), 0);
4992 I915_WRITE(RING_HEAD(base
), 0);
4993 I915_WRITE(RING_TAIL(base
), 0);
4994 I915_WRITE(RING_START(base
), 0);
4997 static void init_unused_rings(struct drm_device
*dev
)
5000 init_unused_ring(dev
, PRB1_BASE
);
5001 init_unused_ring(dev
, SRB0_BASE
);
5002 init_unused_ring(dev
, SRB1_BASE
);
5003 init_unused_ring(dev
, SRB2_BASE
);
5004 init_unused_ring(dev
, SRB3_BASE
);
5005 } else if (IS_GEN2(dev
)) {
5006 init_unused_ring(dev
, SRB0_BASE
);
5007 init_unused_ring(dev
, SRB1_BASE
);
5008 } else if (IS_GEN3(dev
)) {
5009 init_unused_ring(dev
, PRB1_BASE
);
5010 init_unused_ring(dev
, PRB2_BASE
);
5014 int i915_gem_init_engines(struct drm_device
*dev
)
5016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5019 ret
= intel_init_render_ring_buffer(dev
);
5024 ret
= intel_init_bsd_ring_buffer(dev
);
5026 goto cleanup_render_ring
;
5030 ret
= intel_init_blt_ring_buffer(dev
);
5032 goto cleanup_bsd_ring
;
5035 if (HAS_VEBOX(dev
)) {
5036 ret
= intel_init_vebox_ring_buffer(dev
);
5038 goto cleanup_blt_ring
;
5041 if (HAS_BSD2(dev
)) {
5042 ret
= intel_init_bsd2_ring_buffer(dev
);
5044 goto cleanup_vebox_ring
;
5050 intel_cleanup_engine(&dev_priv
->engine
[VECS
]);
5052 intel_cleanup_engine(&dev_priv
->engine
[BCS
]);
5054 intel_cleanup_engine(&dev_priv
->engine
[VCS
]);
5055 cleanup_render_ring
:
5056 intel_cleanup_engine(&dev_priv
->engine
[RCS
]);
5062 i915_gem_init_hw(struct drm_device
*dev
)
5064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5065 struct intel_engine_cs
*engine
;
5068 /* Double layer security blanket, see i915_gem_init() */
5069 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5071 if (HAS_EDRAM(dev
) && INTEL_GEN(dev_priv
) < 9)
5072 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
5074 if (IS_HASWELL(dev
))
5075 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
5076 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
5078 if (HAS_PCH_NOP(dev
)) {
5079 if (IS_IVYBRIDGE(dev
)) {
5080 u32 temp
= I915_READ(GEN7_MSG_CTL
);
5081 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
5082 I915_WRITE(GEN7_MSG_CTL
, temp
);
5083 } else if (INTEL_INFO(dev
)->gen
>= 7) {
5084 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5085 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5086 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
5090 i915_gem_init_swizzling(dev
);
5093 * At least 830 can leave some of the unused rings
5094 * "active" (ie. head != tail) after resume which
5095 * will prevent c3 entry. Makes sure all unused rings
5098 init_unused_rings(dev
);
5100 BUG_ON(!dev_priv
->kernel_context
);
5102 ret
= i915_ppgtt_init_hw(dev
);
5104 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
5108 /* Need to do basic initialisation of all rings first: */
5109 for_each_engine(engine
, dev_priv
) {
5110 ret
= engine
->init_hw(engine
);
5115 intel_mocs_init_l3cc_table(dev
);
5117 /* We can't enable contexts until all firmware is loaded */
5118 ret
= intel_guc_setup(dev
);
5123 * Increment the next seqno by 0x100 so we have a visible break
5124 * on re-initialisation
5126 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
5129 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5133 int i915_gem_init(struct drm_device
*dev
)
5135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5138 mutex_lock(&dev
->struct_mutex
);
5140 if (!i915
.enable_execlists
) {
5141 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5142 dev_priv
->gt
.init_engines
= i915_gem_init_engines
;
5143 dev_priv
->gt
.cleanup_engine
= intel_cleanup_engine
;
5144 dev_priv
->gt
.stop_engine
= intel_stop_engine
;
5146 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5147 dev_priv
->gt
.init_engines
= intel_logical_rings_init
;
5148 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
5149 dev_priv
->gt
.stop_engine
= intel_logical_ring_stop
;
5152 /* This is just a security blanket to placate dragons.
5153 * On some systems, we very sporadically observe that the first TLBs
5154 * used by the CS may be stale, despite us poking the TLB reset. If
5155 * we hold the forcewake during initialisation these problems
5156 * just magically go away.
5158 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5160 i915_gem_init_userptr(dev_priv
);
5161 i915_gem_init_ggtt(dev
);
5163 ret
= i915_gem_context_init(dev
);
5167 ret
= dev_priv
->gt
.init_engines(dev
);
5171 ret
= i915_gem_init_hw(dev
);
5173 /* Allow ring initialisation to fail by marking the GPU as
5174 * wedged. But we only want to do this where the GPU is angry,
5175 * for all other failure, such as an allocation failure, bail.
5177 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5178 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5183 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5184 mutex_unlock(&dev
->struct_mutex
);
5190 i915_gem_cleanup_engines(struct drm_device
*dev
)
5192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5193 struct intel_engine_cs
*engine
;
5195 for_each_engine(engine
, dev_priv
)
5196 dev_priv
->gt
.cleanup_engine(engine
);
5200 init_engine_lists(struct intel_engine_cs
*engine
)
5202 INIT_LIST_HEAD(&engine
->active_list
);
5203 INIT_LIST_HEAD(&engine
->request_list
);
5207 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
5209 struct drm_device
*dev
= dev_priv
->dev
;
5211 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
5212 !IS_CHERRYVIEW(dev_priv
))
5213 dev_priv
->num_fence_regs
= 32;
5214 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
5215 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
5216 dev_priv
->num_fence_regs
= 16;
5218 dev_priv
->num_fence_regs
= 8;
5220 if (intel_vgpu_active(dev_priv
))
5221 dev_priv
->num_fence_regs
=
5222 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5224 /* Initialize fence registers to zero */
5225 i915_gem_restore_fences(dev
);
5227 i915_gem_detect_bit_6_swizzle(dev
);
5231 i915_gem_load_init(struct drm_device
*dev
)
5233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5237 kmem_cache_create("i915_gem_object",
5238 sizeof(struct drm_i915_gem_object
), 0,
5242 kmem_cache_create("i915_gem_vma",
5243 sizeof(struct i915_vma
), 0,
5246 dev_priv
->requests
=
5247 kmem_cache_create("i915_gem_request",
5248 sizeof(struct drm_i915_gem_request
), 0,
5252 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5253 INIT_LIST_HEAD(&dev_priv
->context_list
);
5254 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5255 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5256 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5257 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
5258 init_engine_lists(&dev_priv
->engine
[i
]);
5259 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5260 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5261 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5262 i915_gem_retire_work_handler
);
5263 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5264 i915_gem_idle_work_handler
);
5265 init_waitqueue_head(&dev_priv
->gpu_error
.wait_queue
);
5266 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5268 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5271 * Set initial sequence number for requests.
5272 * Using this number allows the wraparound to happen early,
5273 * catching any obvious problems.
5275 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5276 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5278 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5280 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5282 dev_priv
->mm
.interruptible
= true;
5284 mutex_init(&dev_priv
->fb_tracking
.lock
);
5287 void i915_gem_load_cleanup(struct drm_device
*dev
)
5289 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5291 kmem_cache_destroy(dev_priv
->requests
);
5292 kmem_cache_destroy(dev_priv
->vmas
);
5293 kmem_cache_destroy(dev_priv
->objects
);
5296 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
5298 struct drm_i915_gem_object
*obj
;
5300 /* Called just before we write the hibernation image.
5302 * We need to update the domain tracking to reflect that the CPU
5303 * will be accessing all the pages to create and restore from the
5304 * hibernation, and so upon restoration those pages will be in the
5307 * To make sure the hibernation image contains the latest state,
5308 * we update that state just before writing out the image.
5311 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5312 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
5313 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
5316 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5317 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
5318 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
5324 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5326 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5328 /* Clean up our request list when the client is going away, so that
5329 * later retire_requests won't dereference our soon-to-be-gone
5332 spin_lock(&file_priv
->mm
.lock
);
5333 while (!list_empty(&file_priv
->mm
.request_list
)) {
5334 struct drm_i915_gem_request
*request
;
5336 request
= list_first_entry(&file_priv
->mm
.request_list
,
5337 struct drm_i915_gem_request
,
5339 list_del(&request
->client_list
);
5340 request
->file_priv
= NULL
;
5342 spin_unlock(&file_priv
->mm
.lock
);
5344 if (!list_empty(&file_priv
->rps
.link
)) {
5345 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5346 list_del(&file_priv
->rps
.link
);
5347 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5351 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5353 struct drm_i915_file_private
*file_priv
;
5356 DRM_DEBUG_DRIVER("\n");
5358 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5362 file
->driver_priv
= file_priv
;
5363 file_priv
->dev_priv
= dev
->dev_private
;
5364 file_priv
->file
= file
;
5365 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5367 spin_lock_init(&file_priv
->mm
.lock
);
5368 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5370 file_priv
->bsd_ring
= -1;
5372 ret
= i915_gem_context_open(dev
, file
);
5380 * i915_gem_track_fb - update frontbuffer tracking
5381 * @old: current GEM buffer for the frontbuffer slots
5382 * @new: new GEM buffer for the frontbuffer slots
5383 * @frontbuffer_bits: bitmask of frontbuffer slots
5385 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5386 * from @old and setting them in @new. Both @old and @new can be NULL.
5388 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5389 struct drm_i915_gem_object
*new,
5390 unsigned frontbuffer_bits
)
5393 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5394 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5395 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5399 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5400 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5401 new->frontbuffer_bits
|= frontbuffer_bits
;
5405 /* All the new VM stuff */
5406 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5407 struct i915_address_space
*vm
)
5409 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5410 struct i915_vma
*vma
;
5412 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5414 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5416 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5419 return vma
->node
.start
;
5422 WARN(1, "%s vma for this object not found.\n",
5423 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5427 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5428 const struct i915_ggtt_view
*view
)
5430 struct i915_vma
*vma
;
5432 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5433 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5434 return vma
->node
.start
;
5436 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5440 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5441 struct i915_address_space
*vm
)
5443 struct i915_vma
*vma
;
5445 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5447 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5449 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5456 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5457 const struct i915_ggtt_view
*view
)
5459 struct i915_vma
*vma
;
5461 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5463 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5464 drm_mm_node_allocated(&vma
->node
))
5470 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5472 struct i915_vma
*vma
;
5474 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5475 if (drm_mm_node_allocated(&vma
->node
))
5481 unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*o
)
5483 struct i915_vma
*vma
;
5485 GEM_BUG_ON(list_empty(&o
->vma_list
));
5487 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5489 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
5490 return vma
->node
.size
;
5496 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5498 struct i915_vma
*vma
;
5499 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
5500 if (vma
->pin_count
> 0)
5506 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5508 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5512 /* Only default objects have per-page dirty tracking */
5513 if (WARN_ON(!i915_gem_object_has_struct_page(obj
)))
5516 page
= i915_gem_object_get_page(obj
, n
);
5517 set_page_dirty(page
);
5521 /* Allocate a new GEM object and fill it with the supplied data */
5522 struct drm_i915_gem_object
*
5523 i915_gem_object_create_from_data(struct drm_device
*dev
,
5524 const void *data
, size_t size
)
5526 struct drm_i915_gem_object
*obj
;
5527 struct sg_table
*sg
;
5531 obj
= i915_gem_object_create(dev
, round_up(size
, PAGE_SIZE
));
5535 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5539 ret
= i915_gem_object_get_pages(obj
);
5543 i915_gem_object_pin_pages(obj
);
5545 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5546 obj
->dirty
= 1; /* Backing store is now out of date */
5547 i915_gem_object_unpin_pages(obj
);
5549 if (WARN_ON(bytes
!= size
)) {
5550 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5558 drm_gem_object_unreference(&obj
->base
);
5559 return ERR_PTR(ret
);