2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
);
50 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
55 if (!(obj
->cache_coherent
& I915_BO_CACHE_COHERENT_FOR_WRITE
))
58 return obj
->pin_display
;
62 insert_mappable_node(struct i915_ggtt
*ggtt
,
63 struct drm_mm_node
*node
, u32 size
)
65 memset(node
, 0, sizeof(*node
));
66 return drm_mm_insert_node_in_range(&ggtt
->base
.mm
, node
,
67 size
, 0, I915_COLOR_UNEVICTABLE
,
68 0, ggtt
->mappable_end
,
73 remove_mappable_node(struct drm_mm_node
*node
)
75 drm_mm_remove_node(node
);
78 /* some bookkeeping */
79 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
82 spin_lock(&dev_priv
->mm
.object_stat_lock
);
83 dev_priv
->mm
.object_count
++;
84 dev_priv
->mm
.object_memory
+= size
;
85 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
88 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
91 spin_lock(&dev_priv
->mm
.object_stat_lock
);
92 dev_priv
->mm
.object_count
--;
93 dev_priv
->mm
.object_memory
-= size
;
94 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
98 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
106 * userspace. If it takes that long something really bad is going on and
107 * we should simply try to bail out and fail as gracefully as possible.
109 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
110 !i915_reset_backoff(error
),
113 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
115 } else if (ret
< 0) {
122 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
124 struct drm_i915_private
*dev_priv
= to_i915(dev
);
127 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
131 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
139 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
140 struct drm_file
*file
)
142 struct drm_i915_private
*dev_priv
= to_i915(dev
);
143 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
144 struct drm_i915_gem_get_aperture
*args
= data
;
145 struct i915_vma
*vma
;
148 pinned
= ggtt
->base
.reserved
;
149 mutex_lock(&dev
->struct_mutex
);
150 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
151 if (i915_vma_is_pinned(vma
))
152 pinned
+= vma
->node
.size
;
153 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
154 if (i915_vma_is_pinned(vma
))
155 pinned
+= vma
->node
.size
;
156 mutex_unlock(&dev
->struct_mutex
);
158 args
->aper_size
= ggtt
->base
.total
;
159 args
->aper_available_size
= args
->aper_size
- pinned
;
164 static struct sg_table
*
165 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
167 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
168 drm_dma_handle_t
*phys
;
170 struct scatterlist
*sg
;
174 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
175 return ERR_PTR(-EINVAL
);
177 /* Always aligning to the object size, allows a single allocation
178 * to handle all possible callers, and given typical object sizes,
179 * the alignment of the buddy allocation will naturally match.
181 phys
= drm_pci_alloc(obj
->base
.dev
,
183 roundup_pow_of_two(obj
->base
.size
));
185 return ERR_PTR(-ENOMEM
);
188 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
192 page
= shmem_read_mapping_page(mapping
, i
);
198 src
= kmap_atomic(page
);
199 memcpy(vaddr
, src
, PAGE_SIZE
);
200 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
207 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
209 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
211 st
= ERR_PTR(-ENOMEM
);
215 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
217 st
= ERR_PTR(-ENOMEM
);
223 sg
->length
= obj
->base
.size
;
225 sg_dma_address(sg
) = phys
->busaddr
;
226 sg_dma_len(sg
) = obj
->base
.size
;
228 obj
->phys_handle
= phys
;
232 drm_pci_free(obj
->base
.dev
, phys
);
236 static void __start_cpu_write(struct drm_i915_gem_object
*obj
)
238 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
239 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
240 if (cpu_write_needs_clflush(obj
))
241 obj
->cache_dirty
= true;
245 __i915_gem_object_release_shmem(struct drm_i915_gem_object
*obj
,
246 struct sg_table
*pages
,
249 GEM_BUG_ON(obj
->mm
.madv
== __I915_MADV_PURGED
);
251 if (obj
->mm
.madv
== I915_MADV_DONTNEED
)
252 obj
->mm
.dirty
= false;
255 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0 &&
256 !(obj
->cache_coherent
& I915_BO_CACHE_COHERENT_FOR_READ
))
257 drm_clflush_sg(pages
);
259 __start_cpu_write(obj
);
263 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
,
264 struct sg_table
*pages
)
266 __i915_gem_object_release_shmem(obj
, pages
, false);
269 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
270 char *vaddr
= obj
->phys_handle
->vaddr
;
273 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
277 page
= shmem_read_mapping_page(mapping
, i
);
281 dst
= kmap_atomic(page
);
282 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
283 memcpy(dst
, vaddr
, PAGE_SIZE
);
286 set_page_dirty(page
);
287 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
288 mark_page_accessed(page
);
292 obj
->mm
.dirty
= false;
295 sg_free_table(pages
);
298 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
302 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
304 i915_gem_object_unpin_pages(obj
);
307 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
308 .get_pages
= i915_gem_object_get_pages_phys
,
309 .put_pages
= i915_gem_object_put_pages_phys
,
310 .release
= i915_gem_object_release_phys
,
313 static const struct drm_i915_gem_object_ops i915_gem_object_ops
;
315 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
317 struct i915_vma
*vma
;
318 LIST_HEAD(still_in_list
);
321 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret
= i915_gem_object_wait(obj
,
329 I915_WAIT_INTERRUPTIBLE
|
332 MAX_SCHEDULE_TIMEOUT
,
337 i915_gem_retire_requests(to_i915(obj
->base
.dev
));
339 while ((vma
= list_first_entry_or_null(&obj
->vma_list
,
342 list_move_tail(&vma
->obj_link
, &still_in_list
);
343 ret
= i915_vma_unbind(vma
);
347 list_splice(&still_in_list
, &obj
->vma_list
);
353 i915_gem_object_wait_fence(struct dma_fence
*fence
,
356 struct intel_rps_client
*rps
)
358 struct drm_i915_gem_request
*rq
;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE
!= 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &fence
->flags
))
365 if (!dma_fence_is_i915(fence
))
366 return dma_fence_wait_timeout(fence
,
367 flags
& I915_WAIT_INTERRUPTIBLE
,
370 rq
= to_request(fence
);
371 if (i915_gem_request_completed(rq
))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq
->i915
) >= 6)
391 gen6_rps_boost(rq
, rps
);
396 timeout
= i915_wait_request(rq
, flags
, timeout
);
399 if (flags
& I915_WAIT_LOCKED
&& i915_gem_request_completed(rq
))
400 i915_gem_request_retire_upto(rq
);
406 i915_gem_object_wait_reservation(struct reservation_object
*resv
,
409 struct intel_rps_client
*rps
)
411 unsigned int seq
= __read_seqcount_begin(&resv
->seq
);
412 struct dma_fence
*excl
;
413 bool prune_fences
= false;
415 if (flags
& I915_WAIT_ALL
) {
416 struct dma_fence
**shared
;
417 unsigned int count
, i
;
420 ret
= reservation_object_get_fences_rcu(resv
,
421 &excl
, &count
, &shared
);
425 for (i
= 0; i
< count
; i
++) {
426 timeout
= i915_gem_object_wait_fence(shared
[i
],
432 dma_fence_put(shared
[i
]);
435 for (; i
< count
; i
++)
436 dma_fence_put(shared
[i
]);
439 prune_fences
= count
&& timeout
>= 0;
441 excl
= reservation_object_get_excl_rcu(resv
);
444 if (excl
&& timeout
>= 0) {
445 timeout
= i915_gem_object_wait_fence(excl
, flags
, timeout
, rps
);
446 prune_fences
= timeout
>= 0;
451 /* Oportunistically prune the fences iff we know they have *all* been
452 * signaled and that the reservation object has not been changed (i.e.
453 * no new fences have been added).
455 if (prune_fences
&& !__read_seqcount_retry(&resv
->seq
, seq
)) {
456 if (reservation_object_trylock(resv
)) {
457 if (!__read_seqcount_retry(&resv
->seq
, seq
))
458 reservation_object_add_excl_fence(resv
, NULL
);
459 reservation_object_unlock(resv
);
466 static void __fence_set_priority(struct dma_fence
*fence
, int prio
)
468 struct drm_i915_gem_request
*rq
;
469 struct intel_engine_cs
*engine
;
471 if (!dma_fence_is_i915(fence
))
474 rq
= to_request(fence
);
476 if (!engine
->schedule
)
479 engine
->schedule(rq
, prio
);
482 static void fence_set_priority(struct dma_fence
*fence
, int prio
)
484 /* Recurse once into a fence-array */
485 if (dma_fence_is_array(fence
)) {
486 struct dma_fence_array
*array
= to_dma_fence_array(fence
);
489 for (i
= 0; i
< array
->num_fences
; i
++)
490 __fence_set_priority(array
->fences
[i
], prio
);
492 __fence_set_priority(fence
, prio
);
497 i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
501 struct dma_fence
*excl
;
503 if (flags
& I915_WAIT_ALL
) {
504 struct dma_fence
**shared
;
505 unsigned int count
, i
;
508 ret
= reservation_object_get_fences_rcu(obj
->resv
,
509 &excl
, &count
, &shared
);
513 for (i
= 0; i
< count
; i
++) {
514 fence_set_priority(shared
[i
], prio
);
515 dma_fence_put(shared
[i
]);
520 excl
= reservation_object_get_excl_rcu(obj
->resv
);
524 fence_set_priority(excl
, prio
);
531 * Waits for rendering to the object to be completed
532 * @obj: i915 gem object
533 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
534 * @timeout: how long to wait
535 * @rps: client (user process) to charge for any waitboosting
538 i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
541 struct intel_rps_client
*rps
)
544 #if IS_ENABLED(CONFIG_LOCKDEP)
545 GEM_BUG_ON(debug_locks
&&
546 !!lockdep_is_held(&obj
->base
.dev
->struct_mutex
) !=
547 !!(flags
& I915_WAIT_LOCKED
));
549 GEM_BUG_ON(timeout
< 0);
551 timeout
= i915_gem_object_wait_reservation(obj
->resv
,
554 return timeout
< 0 ? timeout
: 0;
557 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
559 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
565 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
566 struct drm_i915_gem_pwrite
*args
,
567 struct drm_file
*file
)
569 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
570 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
572 /* We manually control the domain here and pretend that it
573 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
575 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
576 if (copy_from_user(vaddr
, user_data
, args
->size
))
579 drm_clflush_virt_range(vaddr
, args
->size
);
580 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
582 intel_fb_obj_flush(obj
, ORIGIN_CPU
);
586 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
)
588 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
591 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
593 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
594 kmem_cache_free(dev_priv
->objects
, obj
);
598 i915_gem_create(struct drm_file
*file
,
599 struct drm_i915_private
*dev_priv
,
603 struct drm_i915_gem_object
*obj
;
607 size
= roundup(size
, PAGE_SIZE
);
611 /* Allocate the new object */
612 obj
= i915_gem_object_create(dev_priv
, size
);
616 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
617 /* drop reference from allocate - handle holds it now */
618 i915_gem_object_put(obj
);
627 i915_gem_dumb_create(struct drm_file
*file
,
628 struct drm_device
*dev
,
629 struct drm_mode_create_dumb
*args
)
631 /* have to work out size/pitch and return them */
632 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
633 args
->size
= args
->pitch
* args
->height
;
634 return i915_gem_create(file
, to_i915(dev
),
635 args
->size
, &args
->handle
);
638 static bool gpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
640 return !(obj
->cache_level
== I915_CACHE_NONE
||
641 obj
->cache_level
== I915_CACHE_WT
);
645 * Creates a new mm object and returns a handle to it.
646 * @dev: drm device pointer
647 * @data: ioctl data blob
648 * @file: drm file pointer
651 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
652 struct drm_file
*file
)
654 struct drm_i915_private
*dev_priv
= to_i915(dev
);
655 struct drm_i915_gem_create
*args
= data
;
657 i915_gem_flush_free_objects(dev_priv
);
659 return i915_gem_create(file
, dev_priv
,
660 args
->size
, &args
->handle
);
663 static inline enum fb_op_origin
664 fb_write_origin(struct drm_i915_gem_object
*obj
, unsigned int domain
)
666 return (domain
== I915_GEM_DOMAIN_GTT
?
667 obj
->frontbuffer_ggtt_origin
: ORIGIN_CPU
);
671 flush_write_domain(struct drm_i915_gem_object
*obj
, unsigned int flush_domains
)
673 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
675 if (!(obj
->base
.write_domain
& flush_domains
))
678 /* No actual flushing is required for the GTT write domain. Writes
679 * to it "immediately" go to main memory as far as we know, so there's
680 * no chipset flush. It also doesn't land in render cache.
682 * However, we do have to enforce the order so that all writes through
683 * the GTT land before any writes to the device, such as updates to
686 * We also have to wait a bit for the writes to land from the GTT.
687 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
688 * timing. This issue has only been observed when switching quickly
689 * between GTT writes and CPU reads from inside the kernel on recent hw,
690 * and it appears to only affect discrete GTT blocks (i.e. on LLC
691 * system agents we cannot reproduce this behaviour).
695 switch (obj
->base
.write_domain
) {
696 case I915_GEM_DOMAIN_GTT
:
697 if (INTEL_GEN(dev_priv
) >= 6 && !HAS_LLC(dev_priv
)) {
698 intel_runtime_pm_get(dev_priv
);
699 spin_lock_irq(&dev_priv
->uncore
.lock
);
700 POSTING_READ_FW(RING_ACTHD(dev_priv
->engine
[RCS
]->mmio_base
));
701 spin_unlock_irq(&dev_priv
->uncore
.lock
);
702 intel_runtime_pm_put(dev_priv
);
705 intel_fb_obj_flush(obj
,
706 fb_write_origin(obj
, I915_GEM_DOMAIN_GTT
));
709 case I915_GEM_DOMAIN_CPU
:
710 i915_gem_clflush_object(obj
, I915_CLFLUSH_SYNC
);
713 case I915_GEM_DOMAIN_RENDER
:
714 if (gpu_write_needs_clflush(obj
))
715 obj
->cache_dirty
= true;
719 obj
->base
.write_domain
= 0;
723 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
724 const char *gpu_vaddr
, int gpu_offset
,
727 int ret
, cpu_offset
= 0;
730 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
731 int this_length
= min(cacheline_end
- gpu_offset
, length
);
732 int swizzled_gpu_offset
= gpu_offset
^ 64;
734 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
735 gpu_vaddr
+ swizzled_gpu_offset
,
740 cpu_offset
+= this_length
;
741 gpu_offset
+= this_length
;
742 length
-= this_length
;
749 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
750 const char __user
*cpu_vaddr
,
753 int ret
, cpu_offset
= 0;
756 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
757 int this_length
= min(cacheline_end
- gpu_offset
, length
);
758 int swizzled_gpu_offset
= gpu_offset
^ 64;
760 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
761 cpu_vaddr
+ cpu_offset
,
766 cpu_offset
+= this_length
;
767 gpu_offset
+= this_length
;
768 length
-= this_length
;
775 * Pins the specified object's pages and synchronizes the object with
776 * GPU accesses. Sets needs_clflush to non-zero if the caller should
777 * flush the object from the CPU cache.
779 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
780 unsigned int *needs_clflush
)
784 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
787 if (!i915_gem_object_has_struct_page(obj
))
790 ret
= i915_gem_object_wait(obj
,
791 I915_WAIT_INTERRUPTIBLE
|
793 MAX_SCHEDULE_TIMEOUT
,
798 ret
= i915_gem_object_pin_pages(obj
);
802 if (obj
->cache_coherent
& I915_BO_CACHE_COHERENT_FOR_READ
||
803 !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
804 ret
= i915_gem_object_set_to_cpu_domain(obj
, false);
811 flush_write_domain(obj
, ~I915_GEM_DOMAIN_CPU
);
813 /* If we're not in the cpu read domain, set ourself into the gtt
814 * read domain and manually flush cachelines (if required). This
815 * optimizes for the case when the gpu will dirty the data
816 * anyway again before the next pread happens.
818 if (!obj
->cache_dirty
&&
819 !(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
820 *needs_clflush
= CLFLUSH_BEFORE
;
823 /* return with the pages pinned */
827 i915_gem_object_unpin_pages(obj
);
831 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
832 unsigned int *needs_clflush
)
836 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
839 if (!i915_gem_object_has_struct_page(obj
))
842 ret
= i915_gem_object_wait(obj
,
843 I915_WAIT_INTERRUPTIBLE
|
846 MAX_SCHEDULE_TIMEOUT
,
851 ret
= i915_gem_object_pin_pages(obj
);
855 if (obj
->cache_coherent
& I915_BO_CACHE_COHERENT_FOR_WRITE
||
856 !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
857 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
864 flush_write_domain(obj
, ~I915_GEM_DOMAIN_CPU
);
866 /* If we're not in the cpu write domain, set ourself into the
867 * gtt write domain and manually flush cachelines (as required).
868 * This optimizes for the case when the gpu will use the data
869 * right away and we therefore have to clflush anyway.
871 if (!obj
->cache_dirty
) {
872 *needs_clflush
|= CLFLUSH_AFTER
;
875 * Same trick applies to invalidate partially written
876 * cachelines read before writing.
878 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
879 *needs_clflush
|= CLFLUSH_BEFORE
;
883 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
884 obj
->mm
.dirty
= true;
885 /* return with the pages pinned */
889 i915_gem_object_unpin_pages(obj
);
894 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
897 if (unlikely(swizzled
)) {
898 unsigned long start
= (unsigned long) addr
;
899 unsigned long end
= (unsigned long) addr
+ length
;
901 /* For swizzling simply ensure that we always flush both
902 * channels. Lame, but simple and it works. Swizzled
903 * pwrite/pread is far from a hotpath - current userspace
904 * doesn't use it at all. */
905 start
= round_down(start
, 128);
906 end
= round_up(end
, 128);
908 drm_clflush_virt_range((void *)start
, end
- start
);
910 drm_clflush_virt_range(addr
, length
);
915 /* Only difference to the fast-path function is that this can handle bit17
916 * and uses non-atomic copy and kmap functions. */
918 shmem_pread_slow(struct page
*page
, int offset
, int length
,
919 char __user
*user_data
,
920 bool page_do_bit17_swizzling
, bool needs_clflush
)
927 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
928 page_do_bit17_swizzling
);
930 if (page_do_bit17_swizzling
)
931 ret
= __copy_to_user_swizzled(user_data
, vaddr
, offset
, length
);
933 ret
= __copy_to_user(user_data
, vaddr
+ offset
, length
);
936 return ret
? - EFAULT
: 0;
940 shmem_pread(struct page
*page
, int offset
, int length
, char __user
*user_data
,
941 bool page_do_bit17_swizzling
, bool needs_clflush
)
946 if (!page_do_bit17_swizzling
) {
947 char *vaddr
= kmap_atomic(page
);
950 drm_clflush_virt_range(vaddr
+ offset
, length
);
951 ret
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
952 kunmap_atomic(vaddr
);
957 return shmem_pread_slow(page
, offset
, length
, user_data
,
958 page_do_bit17_swizzling
, needs_clflush
);
962 i915_gem_shmem_pread(struct drm_i915_gem_object
*obj
,
963 struct drm_i915_gem_pread
*args
)
965 char __user
*user_data
;
967 unsigned int obj_do_bit17_swizzling
;
968 unsigned int needs_clflush
;
969 unsigned int idx
, offset
;
972 obj_do_bit17_swizzling
= 0;
973 if (i915_gem_object_needs_bit17_swizzle(obj
))
974 obj_do_bit17_swizzling
= BIT(17);
976 ret
= mutex_lock_interruptible(&obj
->base
.dev
->struct_mutex
);
980 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
981 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
986 user_data
= u64_to_user_ptr(args
->data_ptr
);
987 offset
= offset_in_page(args
->offset
);
988 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
989 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
993 if (offset
+ length
> PAGE_SIZE
)
994 length
= PAGE_SIZE
- offset
;
996 ret
= shmem_pread(page
, offset
, length
, user_data
,
997 page_to_phys(page
) & obj_do_bit17_swizzling
,
1003 user_data
+= length
;
1007 i915_gem_obj_finish_shmem_access(obj
);
1012 gtt_user_read(struct io_mapping
*mapping
,
1013 loff_t base
, int offset
,
1014 char __user
*user_data
, int length
)
1017 unsigned long unwritten
;
1019 /* We can use the cpu mem copy function because this is X86. */
1020 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
1021 unwritten
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
1022 io_mapping_unmap_atomic(vaddr
);
1024 vaddr
= (void __force
*)
1025 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1026 unwritten
= copy_to_user(user_data
, vaddr
+ offset
, length
);
1027 io_mapping_unmap(vaddr
);
1033 i915_gem_gtt_pread(struct drm_i915_gem_object
*obj
,
1034 const struct drm_i915_gem_pread
*args
)
1036 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1037 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1038 struct drm_mm_node node
;
1039 struct i915_vma
*vma
;
1040 void __user
*user_data
;
1044 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1048 intel_runtime_pm_get(i915
);
1049 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1050 PIN_MAPPABLE
| PIN_NONBLOCK
);
1052 node
.start
= i915_ggtt_offset(vma
);
1053 node
.allocated
= false;
1054 ret
= i915_vma_put_fence(vma
);
1056 i915_vma_unpin(vma
);
1061 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1064 GEM_BUG_ON(!node
.allocated
);
1067 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1071 mutex_unlock(&i915
->drm
.struct_mutex
);
1073 user_data
= u64_to_user_ptr(args
->data_ptr
);
1074 remain
= args
->size
;
1075 offset
= args
->offset
;
1077 while (remain
> 0) {
1078 /* Operation in this page
1080 * page_base = page offset within aperture
1081 * page_offset = offset within page
1082 * page_length = bytes to copy for this page
1084 u32 page_base
= node
.start
;
1085 unsigned page_offset
= offset_in_page(offset
);
1086 unsigned page_length
= PAGE_SIZE
- page_offset
;
1087 page_length
= remain
< page_length
? remain
: page_length
;
1088 if (node
.allocated
) {
1090 ggtt
->base
.insert_page(&ggtt
->base
,
1091 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1092 node
.start
, I915_CACHE_NONE
, 0);
1095 page_base
+= offset
& PAGE_MASK
;
1098 if (gtt_user_read(&ggtt
->mappable
, page_base
, page_offset
,
1099 user_data
, page_length
)) {
1104 remain
-= page_length
;
1105 user_data
+= page_length
;
1106 offset
+= page_length
;
1109 mutex_lock(&i915
->drm
.struct_mutex
);
1111 if (node
.allocated
) {
1113 ggtt
->base
.clear_range(&ggtt
->base
,
1114 node
.start
, node
.size
);
1115 remove_mappable_node(&node
);
1117 i915_vma_unpin(vma
);
1120 intel_runtime_pm_put(i915
);
1121 mutex_unlock(&i915
->drm
.struct_mutex
);
1127 * Reads data from the object referenced by handle.
1128 * @dev: drm device pointer
1129 * @data: ioctl data blob
1130 * @file: drm file pointer
1132 * On error, the contents of *data are undefined.
1135 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1136 struct drm_file
*file
)
1138 struct drm_i915_gem_pread
*args
= data
;
1139 struct drm_i915_gem_object
*obj
;
1142 if (args
->size
== 0)
1145 if (!access_ok(VERIFY_WRITE
,
1146 u64_to_user_ptr(args
->data_ptr
),
1150 obj
= i915_gem_object_lookup(file
, args
->handle
);
1154 /* Bounds check source. */
1155 if (range_overflows_t(u64
, args
->offset
, args
->size
, obj
->base
.size
)) {
1160 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
1162 ret
= i915_gem_object_wait(obj
,
1163 I915_WAIT_INTERRUPTIBLE
,
1164 MAX_SCHEDULE_TIMEOUT
,
1165 to_rps_client(file
));
1169 ret
= i915_gem_object_pin_pages(obj
);
1173 ret
= i915_gem_shmem_pread(obj
, args
);
1174 if (ret
== -EFAULT
|| ret
== -ENODEV
)
1175 ret
= i915_gem_gtt_pread(obj
, args
);
1177 i915_gem_object_unpin_pages(obj
);
1179 i915_gem_object_put(obj
);
1183 /* This is the fast write path which cannot handle
1184 * page faults in the source data
1188 ggtt_write(struct io_mapping
*mapping
,
1189 loff_t base
, int offset
,
1190 char __user
*user_data
, int length
)
1193 unsigned long unwritten
;
1195 /* We can use the cpu mem copy function because this is X86. */
1196 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
1197 unwritten
= __copy_from_user_inatomic_nocache(vaddr
+ offset
,
1199 io_mapping_unmap_atomic(vaddr
);
1201 vaddr
= (void __force
*)
1202 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1203 unwritten
= copy_from_user(vaddr
+ offset
, user_data
, length
);
1204 io_mapping_unmap(vaddr
);
1211 * This is the fast pwrite path, where we copy the data directly from the
1212 * user into the GTT, uncached.
1213 * @obj: i915 GEM object
1214 * @args: pwrite arguments structure
1217 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object
*obj
,
1218 const struct drm_i915_gem_pwrite
*args
)
1220 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1221 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1222 struct drm_mm_node node
;
1223 struct i915_vma
*vma
;
1225 void __user
*user_data
;
1228 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1232 intel_runtime_pm_get(i915
);
1233 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1234 PIN_MAPPABLE
| PIN_NONBLOCK
);
1236 node
.start
= i915_ggtt_offset(vma
);
1237 node
.allocated
= false;
1238 ret
= i915_vma_put_fence(vma
);
1240 i915_vma_unpin(vma
);
1245 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1248 GEM_BUG_ON(!node
.allocated
);
1251 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1255 mutex_unlock(&i915
->drm
.struct_mutex
);
1257 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1259 user_data
= u64_to_user_ptr(args
->data_ptr
);
1260 offset
= args
->offset
;
1261 remain
= args
->size
;
1263 /* Operation in this page
1265 * page_base = page offset within aperture
1266 * page_offset = offset within page
1267 * page_length = bytes to copy for this page
1269 u32 page_base
= node
.start
;
1270 unsigned int page_offset
= offset_in_page(offset
);
1271 unsigned int page_length
= PAGE_SIZE
- page_offset
;
1272 page_length
= remain
< page_length
? remain
: page_length
;
1273 if (node
.allocated
) {
1274 wmb(); /* flush the write before we modify the GGTT */
1275 ggtt
->base
.insert_page(&ggtt
->base
,
1276 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1277 node
.start
, I915_CACHE_NONE
, 0);
1278 wmb(); /* flush modifications to the GGTT (insert_page) */
1280 page_base
+= offset
& PAGE_MASK
;
1282 /* If we get a fault while copying data, then (presumably) our
1283 * source page isn't available. Return the error and we'll
1284 * retry in the slow path.
1285 * If the object is non-shmem backed, we retry again with the
1286 * path that handles page fault.
1288 if (ggtt_write(&ggtt
->mappable
, page_base
, page_offset
,
1289 user_data
, page_length
)) {
1294 remain
-= page_length
;
1295 user_data
+= page_length
;
1296 offset
+= page_length
;
1298 intel_fb_obj_flush(obj
, ORIGIN_CPU
);
1300 mutex_lock(&i915
->drm
.struct_mutex
);
1302 if (node
.allocated
) {
1304 ggtt
->base
.clear_range(&ggtt
->base
,
1305 node
.start
, node
.size
);
1306 remove_mappable_node(&node
);
1308 i915_vma_unpin(vma
);
1311 intel_runtime_pm_put(i915
);
1312 mutex_unlock(&i915
->drm
.struct_mutex
);
1317 shmem_pwrite_slow(struct page
*page
, int offset
, int length
,
1318 char __user
*user_data
,
1319 bool page_do_bit17_swizzling
,
1320 bool needs_clflush_before
,
1321 bool needs_clflush_after
)
1327 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1328 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1329 page_do_bit17_swizzling
);
1330 if (page_do_bit17_swizzling
)
1331 ret
= __copy_from_user_swizzled(vaddr
, offset
, user_data
,
1334 ret
= __copy_from_user(vaddr
+ offset
, user_data
, length
);
1335 if (needs_clflush_after
)
1336 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1337 page_do_bit17_swizzling
);
1340 return ret
? -EFAULT
: 0;
1343 /* Per-page copy function for the shmem pwrite fastpath.
1344 * Flushes invalid cachelines before writing to the target if
1345 * needs_clflush_before is set and flushes out any written cachelines after
1346 * writing if needs_clflush is set.
1349 shmem_pwrite(struct page
*page
, int offset
, int len
, char __user
*user_data
,
1350 bool page_do_bit17_swizzling
,
1351 bool needs_clflush_before
,
1352 bool needs_clflush_after
)
1357 if (!page_do_bit17_swizzling
) {
1358 char *vaddr
= kmap_atomic(page
);
1360 if (needs_clflush_before
)
1361 drm_clflush_virt_range(vaddr
+ offset
, len
);
1362 ret
= __copy_from_user_inatomic(vaddr
+ offset
, user_data
, len
);
1363 if (needs_clflush_after
)
1364 drm_clflush_virt_range(vaddr
+ offset
, len
);
1366 kunmap_atomic(vaddr
);
1371 return shmem_pwrite_slow(page
, offset
, len
, user_data
,
1372 page_do_bit17_swizzling
,
1373 needs_clflush_before
,
1374 needs_clflush_after
);
1378 i915_gem_shmem_pwrite(struct drm_i915_gem_object
*obj
,
1379 const struct drm_i915_gem_pwrite
*args
)
1381 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1382 void __user
*user_data
;
1384 unsigned int obj_do_bit17_swizzling
;
1385 unsigned int partial_cacheline_write
;
1386 unsigned int needs_clflush
;
1387 unsigned int offset
, idx
;
1390 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1394 ret
= i915_gem_obj_prepare_shmem_write(obj
, &needs_clflush
);
1395 mutex_unlock(&i915
->drm
.struct_mutex
);
1399 obj_do_bit17_swizzling
= 0;
1400 if (i915_gem_object_needs_bit17_swizzle(obj
))
1401 obj_do_bit17_swizzling
= BIT(17);
1403 /* If we don't overwrite a cacheline completely we need to be
1404 * careful to have up-to-date data by first clflushing. Don't
1405 * overcomplicate things and flush the entire patch.
1407 partial_cacheline_write
= 0;
1408 if (needs_clflush
& CLFLUSH_BEFORE
)
1409 partial_cacheline_write
= boot_cpu_data
.x86_clflush_size
- 1;
1411 user_data
= u64_to_user_ptr(args
->data_ptr
);
1412 remain
= args
->size
;
1413 offset
= offset_in_page(args
->offset
);
1414 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
1415 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
1419 if (offset
+ length
> PAGE_SIZE
)
1420 length
= PAGE_SIZE
- offset
;
1422 ret
= shmem_pwrite(page
, offset
, length
, user_data
,
1423 page_to_phys(page
) & obj_do_bit17_swizzling
,
1424 (offset
| length
) & partial_cacheline_write
,
1425 needs_clflush
& CLFLUSH_AFTER
);
1430 user_data
+= length
;
1434 intel_fb_obj_flush(obj
, ORIGIN_CPU
);
1435 i915_gem_obj_finish_shmem_access(obj
);
1440 * Writes data to the object referenced by handle.
1442 * @data: ioctl data blob
1445 * On error, the contents of the buffer that were to be modified are undefined.
1448 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1449 struct drm_file
*file
)
1451 struct drm_i915_gem_pwrite
*args
= data
;
1452 struct drm_i915_gem_object
*obj
;
1455 if (args
->size
== 0)
1458 if (!access_ok(VERIFY_READ
,
1459 u64_to_user_ptr(args
->data_ptr
),
1463 obj
= i915_gem_object_lookup(file
, args
->handle
);
1467 /* Bounds check destination. */
1468 if (range_overflows_t(u64
, args
->offset
, args
->size
, obj
->base
.size
)) {
1473 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1476 if (obj
->ops
->pwrite
)
1477 ret
= obj
->ops
->pwrite(obj
, args
);
1481 ret
= i915_gem_object_wait(obj
,
1482 I915_WAIT_INTERRUPTIBLE
|
1484 MAX_SCHEDULE_TIMEOUT
,
1485 to_rps_client(file
));
1489 ret
= i915_gem_object_pin_pages(obj
);
1494 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1495 * it would end up going through the fenced access, and we'll get
1496 * different detiling behavior between reading and writing.
1497 * pread/pwrite currently are reading and writing from the CPU
1498 * perspective, requiring manual detiling by the client.
1500 if (!i915_gem_object_has_struct_page(obj
) ||
1501 cpu_write_needs_clflush(obj
))
1502 /* Note that the gtt paths might fail with non-page-backed user
1503 * pointers (e.g. gtt mappings when moving data between
1504 * textures). Fallback to the shmem path in that case.
1506 ret
= i915_gem_gtt_pwrite_fast(obj
, args
);
1508 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1509 if (obj
->phys_handle
)
1510 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1512 ret
= i915_gem_shmem_pwrite(obj
, args
);
1515 i915_gem_object_unpin_pages(obj
);
1517 i915_gem_object_put(obj
);
1521 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object
*obj
)
1523 struct drm_i915_private
*i915
;
1524 struct list_head
*list
;
1525 struct i915_vma
*vma
;
1527 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
1528 if (!i915_vma_is_ggtt(vma
))
1531 if (i915_vma_is_active(vma
))
1534 if (!drm_mm_node_allocated(&vma
->node
))
1537 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
1540 i915
= to_i915(obj
->base
.dev
);
1541 list
= obj
->bind_count
? &i915
->mm
.bound_list
: &i915
->mm
.unbound_list
;
1542 list_move_tail(&obj
->global_link
, list
);
1546 * Called when user space prepares to use an object with the CPU, either
1547 * through the mmap ioctl's mapping or a GTT mapping.
1549 * @data: ioctl data blob
1553 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1554 struct drm_file
*file
)
1556 struct drm_i915_gem_set_domain
*args
= data
;
1557 struct drm_i915_gem_object
*obj
;
1558 uint32_t read_domains
= args
->read_domains
;
1559 uint32_t write_domain
= args
->write_domain
;
1562 /* Only handle setting domains to types used by the CPU. */
1563 if ((write_domain
| read_domains
) & I915_GEM_GPU_DOMAINS
)
1566 /* Having something in the write domain implies it's in the read
1567 * domain, and only that read domain. Enforce that in the request.
1569 if (write_domain
!= 0 && read_domains
!= write_domain
)
1572 obj
= i915_gem_object_lookup(file
, args
->handle
);
1576 /* Try to flush the object off the GPU without holding the lock.
1577 * We will repeat the flush holding the lock in the normal manner
1578 * to catch cases where we are gazumped.
1580 err
= i915_gem_object_wait(obj
,
1581 I915_WAIT_INTERRUPTIBLE
|
1582 (write_domain
? I915_WAIT_ALL
: 0),
1583 MAX_SCHEDULE_TIMEOUT
,
1584 to_rps_client(file
));
1588 /* Flush and acquire obj->pages so that we are coherent through
1589 * direct access in memory with previous cached writes through
1590 * shmemfs and that our cache domain tracking remains valid.
1591 * For example, if the obj->filp was moved to swap without us
1592 * being notified and releasing the pages, we would mistakenly
1593 * continue to assume that the obj remained out of the CPU cached
1596 err
= i915_gem_object_pin_pages(obj
);
1600 err
= i915_mutex_lock_interruptible(dev
);
1604 if (read_domains
& I915_GEM_DOMAIN_WC
)
1605 err
= i915_gem_object_set_to_wc_domain(obj
, write_domain
);
1606 else if (read_domains
& I915_GEM_DOMAIN_GTT
)
1607 err
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
);
1609 err
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
);
1611 /* And bump the LRU for this access */
1612 i915_gem_object_bump_inactive_ggtt(obj
);
1614 mutex_unlock(&dev
->struct_mutex
);
1616 if (write_domain
!= 0)
1617 intel_fb_obj_invalidate(obj
,
1618 fb_write_origin(obj
, write_domain
));
1621 i915_gem_object_unpin_pages(obj
);
1623 i915_gem_object_put(obj
);
1628 * Called when user space has done writes to this buffer
1630 * @data: ioctl data blob
1634 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1635 struct drm_file
*file
)
1637 struct drm_i915_gem_sw_finish
*args
= data
;
1638 struct drm_i915_gem_object
*obj
;
1640 obj
= i915_gem_object_lookup(file
, args
->handle
);
1644 /* Pinned buffers may be scanout, so flush the cache */
1645 i915_gem_object_flush_if_display(obj
);
1646 i915_gem_object_put(obj
);
1652 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1655 * @data: ioctl data blob
1658 * While the mapping holds a reference on the contents of the object, it doesn't
1659 * imply a ref on the object itself.
1663 * DRM driver writers who look a this function as an example for how to do GEM
1664 * mmap support, please don't implement mmap support like here. The modern way
1665 * to implement DRM mmap support is with an mmap offset ioctl (like
1666 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1667 * That way debug tooling like valgrind will understand what's going on, hiding
1668 * the mmap call in a driver private ioctl will break that. The i915 driver only
1669 * does cpu mmaps this way because we didn't know better.
1672 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1673 struct drm_file
*file
)
1675 struct drm_i915_gem_mmap
*args
= data
;
1676 struct drm_i915_gem_object
*obj
;
1679 if (args
->flags
& ~(I915_MMAP_WC
))
1682 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1685 obj
= i915_gem_object_lookup(file
, args
->handle
);
1689 /* prime objects have no backing filp to GEM mmap
1692 if (!obj
->base
.filp
) {
1693 i915_gem_object_put(obj
);
1697 addr
= vm_mmap(obj
->base
.filp
, 0, args
->size
,
1698 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1700 if (args
->flags
& I915_MMAP_WC
) {
1701 struct mm_struct
*mm
= current
->mm
;
1702 struct vm_area_struct
*vma
;
1704 if (down_write_killable(&mm
->mmap_sem
)) {
1705 i915_gem_object_put(obj
);
1708 vma
= find_vma(mm
, addr
);
1711 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1714 up_write(&mm
->mmap_sem
);
1716 /* This may race, but that's ok, it only gets set */
1717 WRITE_ONCE(obj
->frontbuffer_ggtt_origin
, ORIGIN_CPU
);
1719 i915_gem_object_put(obj
);
1720 if (IS_ERR((void *)addr
))
1723 args
->addr_ptr
= (uint64_t) addr
;
1728 static unsigned int tile_row_pages(struct drm_i915_gem_object
*obj
)
1730 return i915_gem_object_get_tile_row_size(obj
) >> PAGE_SHIFT
;
1734 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1736 * A history of the GTT mmap interface:
1738 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1739 * aligned and suitable for fencing, and still fit into the available
1740 * mappable space left by the pinned display objects. A classic problem
1741 * we called the page-fault-of-doom where we would ping-pong between
1742 * two objects that could not fit inside the GTT and so the memcpy
1743 * would page one object in at the expense of the other between every
1746 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1747 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1748 * object is too large for the available space (or simply too large
1749 * for the mappable aperture!), a view is created instead and faulted
1750 * into userspace. (This view is aligned and sized appropriately for
1753 * 2 - Recognise WC as a separate cache domain so that we can flush the
1754 * delayed writes via GTT before performing direct access via WC.
1758 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1759 * hangs on some architectures, corruption on others. An attempt to service
1760 * a GTT page fault from a snoopable object will generate a SIGBUS.
1762 * * the object must be able to fit into RAM (physical memory, though no
1763 * limited to the mappable aperture).
1768 * * a new GTT page fault will synchronize rendering from the GPU and flush
1769 * all data to system memory. Subsequent access will not be synchronized.
1771 * * all mappings are revoked on runtime device suspend.
1773 * * there are only 8, 16 or 32 fence registers to share between all users
1774 * (older machines require fence register for display and blitter access
1775 * as well). Contention of the fence registers will cause the previous users
1776 * to be unmapped and any new access will generate new page faults.
1778 * * running out of memory while servicing a fault may generate a SIGBUS,
1779 * rather than the expected SIGSEGV.
1781 int i915_gem_mmap_gtt_version(void)
1786 static inline struct i915_ggtt_view
1787 compute_partial_view(struct drm_i915_gem_object
*obj
,
1788 pgoff_t page_offset
,
1791 struct i915_ggtt_view view
;
1793 if (i915_gem_object_is_tiled(obj
))
1794 chunk
= roundup(chunk
, tile_row_pages(obj
));
1796 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1797 view
.partial
.offset
= rounddown(page_offset
, chunk
);
1799 min_t(unsigned int, chunk
,
1800 (obj
->base
.size
>> PAGE_SHIFT
) - view
.partial
.offset
);
1802 /* If the partial covers the entire object, just create a normal VMA. */
1803 if (chunk
>= obj
->base
.size
>> PAGE_SHIFT
)
1804 view
.type
= I915_GGTT_VIEW_NORMAL
;
1810 * i915_gem_fault - fault a page into the GTT
1813 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1814 * from userspace. The fault handler takes care of binding the object to
1815 * the GTT (if needed), allocating and programming a fence register (again,
1816 * only if needed based on whether the old reg is still valid or the object
1817 * is tiled) and inserting a new PTE into the faulting process.
1819 * Note that the faulting process may involve evicting existing objects
1820 * from the GTT and/or fence registers to make room. So performance may
1821 * suffer if the GTT working set is large or there are few fence registers
1824 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1825 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1827 int i915_gem_fault(struct vm_fault
*vmf
)
1829 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1830 struct vm_area_struct
*area
= vmf
->vma
;
1831 struct drm_i915_gem_object
*obj
= to_intel_bo(area
->vm_private_data
);
1832 struct drm_device
*dev
= obj
->base
.dev
;
1833 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1834 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1835 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1836 struct i915_vma
*vma
;
1837 pgoff_t page_offset
;
1841 /* We don't use vmf->pgoff since that has the fake offset */
1842 page_offset
= (vmf
->address
- area
->vm_start
) >> PAGE_SHIFT
;
1844 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1846 /* Try to flush the object off the GPU first without holding the lock.
1847 * Upon acquiring the lock, we will perform our sanity checks and then
1848 * repeat the flush holding the lock in the normal manner to catch cases
1849 * where we are gazumped.
1851 ret
= i915_gem_object_wait(obj
,
1852 I915_WAIT_INTERRUPTIBLE
,
1853 MAX_SCHEDULE_TIMEOUT
,
1858 ret
= i915_gem_object_pin_pages(obj
);
1862 intel_runtime_pm_get(dev_priv
);
1864 ret
= i915_mutex_lock_interruptible(dev
);
1868 /* Access to snoopable pages through the GTT is incoherent. */
1869 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev_priv
)) {
1874 /* If the object is smaller than a couple of partial vma, it is
1875 * not worth only creating a single partial vma - we may as well
1876 * clear enough space for the full object.
1878 flags
= PIN_MAPPABLE
;
1879 if (obj
->base
.size
> 2 * MIN_CHUNK_PAGES
<< PAGE_SHIFT
)
1880 flags
|= PIN_NONBLOCK
| PIN_NONFAULT
;
1882 /* Now pin it into the GTT as needed */
1883 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, flags
);
1885 /* Use a partial view if it is bigger than available space */
1886 struct i915_ggtt_view view
=
1887 compute_partial_view(obj
, page_offset
, MIN_CHUNK_PAGES
);
1889 /* Userspace is now writing through an untracked VMA, abandon
1890 * all hope that the hardware is able to track future writes.
1892 obj
->frontbuffer_ggtt_origin
= ORIGIN_CPU
;
1894 vma
= i915_gem_object_ggtt_pin(obj
, &view
, 0, 0, PIN_MAPPABLE
);
1901 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1905 ret
= i915_vma_get_fence(vma
);
1909 /* Mark as being mmapped into userspace for later revocation */
1910 assert_rpm_wakelock_held(dev_priv
);
1911 if (list_empty(&obj
->userfault_link
))
1912 list_add(&obj
->userfault_link
, &dev_priv
->mm
.userfault_list
);
1914 /* Finally, remap it using the new GTT offset */
1915 ret
= remap_io_mapping(area
,
1916 area
->vm_start
+ (vma
->ggtt_view
.partial
.offset
<< PAGE_SHIFT
),
1917 (ggtt
->mappable_base
+ vma
->node
.start
) >> PAGE_SHIFT
,
1918 min_t(u64
, vma
->size
, area
->vm_end
- area
->vm_start
),
1922 __i915_vma_unpin(vma
);
1924 mutex_unlock(&dev
->struct_mutex
);
1926 intel_runtime_pm_put(dev_priv
);
1927 i915_gem_object_unpin_pages(obj
);
1932 * We eat errors when the gpu is terminally wedged to avoid
1933 * userspace unduly crashing (gl has no provisions for mmaps to
1934 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1935 * and so needs to be reported.
1937 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1938 ret
= VM_FAULT_SIGBUS
;
1943 * EAGAIN means the gpu is hung and we'll wait for the error
1944 * handler to reset everything when re-faulting in
1945 * i915_mutex_lock_interruptible.
1952 * EBUSY is ok: this just means that another thread
1953 * already did the job.
1955 ret
= VM_FAULT_NOPAGE
;
1962 ret
= VM_FAULT_SIGBUS
;
1965 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1966 ret
= VM_FAULT_SIGBUS
;
1973 * i915_gem_release_mmap - remove physical page mappings
1974 * @obj: obj in question
1976 * Preserve the reservation of the mmapping with the DRM core code, but
1977 * relinquish ownership of the pages back to the system.
1979 * It is vital that we remove the page mapping if we have mapped a tiled
1980 * object through the GTT and then lose the fence register due to
1981 * resource pressure. Similarly if the object has been moved out of the
1982 * aperture, than pages mapped into userspace must be revoked. Removing the
1983 * mapping will then trigger a page fault on the next user access, allowing
1984 * fixup by i915_gem_fault().
1987 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1989 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1991 /* Serialisation between user GTT access and our code depends upon
1992 * revoking the CPU's PTE whilst the mutex is held. The next user
1993 * pagefault then has to wait until we release the mutex.
1995 * Note that RPM complicates somewhat by adding an additional
1996 * requirement that operations to the GGTT be made holding the RPM
1999 lockdep_assert_held(&i915
->drm
.struct_mutex
);
2000 intel_runtime_pm_get(i915
);
2002 if (list_empty(&obj
->userfault_link
))
2005 list_del_init(&obj
->userfault_link
);
2006 drm_vma_node_unmap(&obj
->base
.vma_node
,
2007 obj
->base
.dev
->anon_inode
->i_mapping
);
2009 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2010 * memory transactions from userspace before we return. The TLB
2011 * flushing implied above by changing the PTE above *should* be
2012 * sufficient, an extra barrier here just provides us with a bit
2013 * of paranoid documentation about our requirement to serialise
2014 * memory writes before touching registers / GSM.
2019 intel_runtime_pm_put(i915
);
2022 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
)
2024 struct drm_i915_gem_object
*obj
, *on
;
2028 * Only called during RPM suspend. All users of the userfault_list
2029 * must be holding an RPM wakeref to ensure that this can not
2030 * run concurrently with themselves (and use the struct_mutex for
2031 * protection between themselves).
2034 list_for_each_entry_safe(obj
, on
,
2035 &dev_priv
->mm
.userfault_list
, userfault_link
) {
2036 list_del_init(&obj
->userfault_link
);
2037 drm_vma_node_unmap(&obj
->base
.vma_node
,
2038 obj
->base
.dev
->anon_inode
->i_mapping
);
2041 /* The fence will be lost when the device powers down. If any were
2042 * in use by hardware (i.e. they are pinned), we should not be powering
2043 * down! All other fences will be reacquired by the user upon waking.
2045 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2046 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2048 /* Ideally we want to assert that the fence register is not
2049 * live at this point (i.e. that no piece of code will be
2050 * trying to write through fence + GTT, as that both violates
2051 * our tracking of activity and associated locking/barriers,
2052 * but also is illegal given that the hw is powered down).
2054 * Previously we used reg->pin_count as a "liveness" indicator.
2055 * That is not sufficient, and we need a more fine-grained
2056 * tool if we want to have a sanity check here.
2062 GEM_BUG_ON(!list_empty(®
->vma
->obj
->userfault_link
));
2067 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2069 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2072 err
= drm_gem_create_mmap_offset(&obj
->base
);
2076 /* Attempt to reap some mmap space from dead objects */
2078 err
= i915_gem_wait_for_idle(dev_priv
, I915_WAIT_INTERRUPTIBLE
);
2082 i915_gem_drain_freed_objects(dev_priv
);
2083 err
= drm_gem_create_mmap_offset(&obj
->base
);
2087 } while (flush_delayed_work(&dev_priv
->gt
.retire_work
));
2092 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2094 drm_gem_free_mmap_offset(&obj
->base
);
2098 i915_gem_mmap_gtt(struct drm_file
*file
,
2099 struct drm_device
*dev
,
2103 struct drm_i915_gem_object
*obj
;
2106 obj
= i915_gem_object_lookup(file
, handle
);
2110 ret
= i915_gem_object_create_mmap_offset(obj
);
2112 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2114 i915_gem_object_put(obj
);
2119 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2121 * @data: GTT mapping ioctl data
2122 * @file: GEM object info
2124 * Simply returns the fake offset to userspace so it can mmap it.
2125 * The mmap call will end up in drm_gem_mmap(), which will set things
2126 * up so we can get faults in the handler above.
2128 * The fault handler will take care of binding the object into the GTT
2129 * (since it may have been evicted to make room for something), allocating
2130 * a fence register, and mapping the appropriate aperture address into
2134 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2135 struct drm_file
*file
)
2137 struct drm_i915_gem_mmap_gtt
*args
= data
;
2139 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2142 /* Immediately discard the backing storage */
2144 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2146 i915_gem_object_free_mmap_offset(obj
);
2148 if (obj
->base
.filp
== NULL
)
2151 /* Our goal here is to return as much of the memory as
2152 * is possible back to the system as we are called from OOM.
2153 * To do this we must instruct the shmfs to drop all of its
2154 * backing pages, *now*.
2156 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2157 obj
->mm
.madv
= __I915_MADV_PURGED
;
2158 obj
->mm
.pages
= ERR_PTR(-EFAULT
);
2161 /* Try to discard unwanted pages */
2162 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2164 struct address_space
*mapping
;
2166 lockdep_assert_held(&obj
->mm
.lock
);
2167 GEM_BUG_ON(obj
->mm
.pages
);
2169 switch (obj
->mm
.madv
) {
2170 case I915_MADV_DONTNEED
:
2171 i915_gem_object_truncate(obj
);
2172 case __I915_MADV_PURGED
:
2176 if (obj
->base
.filp
== NULL
)
2179 mapping
= obj
->base
.filp
->f_mapping
,
2180 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2184 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
,
2185 struct sg_table
*pages
)
2187 struct sgt_iter sgt_iter
;
2190 __i915_gem_object_release_shmem(obj
, pages
, true);
2192 i915_gem_gtt_finish_pages(obj
, pages
);
2194 if (i915_gem_object_needs_bit17_swizzle(obj
))
2195 i915_gem_object_save_bit_17_swizzle(obj
, pages
);
2197 for_each_sgt_page(page
, sgt_iter
, pages
) {
2199 set_page_dirty(page
);
2201 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
2202 mark_page_accessed(page
);
2206 obj
->mm
.dirty
= false;
2208 sg_free_table(pages
);
2212 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object
*obj
)
2214 struct radix_tree_iter iter
;
2217 radix_tree_for_each_slot(slot
, &obj
->mm
.get_page
.radix
, &iter
, 0)
2218 radix_tree_delete(&obj
->mm
.get_page
.radix
, iter
.index
);
2221 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
2222 enum i915_mm_subclass subclass
)
2224 struct sg_table
*pages
;
2226 if (i915_gem_object_has_pinned_pages(obj
))
2229 GEM_BUG_ON(obj
->bind_count
);
2230 if (!READ_ONCE(obj
->mm
.pages
))
2233 /* May be called by shrinker from within get_pages() (on another bo) */
2234 mutex_lock_nested(&obj
->mm
.lock
, subclass
);
2235 if (unlikely(atomic_read(&obj
->mm
.pages_pin_count
)))
2238 /* ->put_pages might need to allocate memory for the bit17 swizzle
2239 * array, hence protect them from being reaped by removing them from gtt
2241 pages
= fetch_and_zero(&obj
->mm
.pages
);
2244 if (obj
->mm
.mapping
) {
2247 ptr
= page_mask_bits(obj
->mm
.mapping
);
2248 if (is_vmalloc_addr(ptr
))
2251 kunmap(kmap_to_page(ptr
));
2253 obj
->mm
.mapping
= NULL
;
2256 __i915_gem_object_reset_page_iter(obj
);
2259 obj
->ops
->put_pages(obj
, pages
);
2262 mutex_unlock(&obj
->mm
.lock
);
2265 static bool i915_sg_trim(struct sg_table
*orig_st
)
2267 struct sg_table new_st
;
2268 struct scatterlist
*sg
, *new_sg
;
2271 if (orig_st
->nents
== orig_st
->orig_nents
)
2274 if (sg_alloc_table(&new_st
, orig_st
->nents
, GFP_KERNEL
| __GFP_NOWARN
))
2277 new_sg
= new_st
.sgl
;
2278 for_each_sg(orig_st
->sgl
, sg
, orig_st
->nents
, i
) {
2279 sg_set_page(new_sg
, sg_page(sg
), sg
->length
, 0);
2280 /* called before being DMA mapped, no need to copy sg->dma_* */
2281 new_sg
= sg_next(new_sg
);
2283 GEM_BUG_ON(new_sg
); /* Should walk exactly nents and hit the end */
2285 sg_free_table(orig_st
);
2291 static struct sg_table
*
2292 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2294 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2295 const unsigned long page_count
= obj
->base
.size
/ PAGE_SIZE
;
2297 struct address_space
*mapping
;
2298 struct sg_table
*st
;
2299 struct scatterlist
*sg
;
2300 struct sgt_iter sgt_iter
;
2302 unsigned long last_pfn
= 0; /* suppress gcc warning */
2303 unsigned int max_segment
;
2307 /* Assert that the object is not currently in any GPU domain. As it
2308 * wasn't in the GTT, there shouldn't be any way it could have been in
2311 GEM_BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2312 GEM_BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2314 max_segment
= swiotlb_max_segment();
2316 max_segment
= rounddown(UINT_MAX
, PAGE_SIZE
);
2318 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2320 return ERR_PTR(-ENOMEM
);
2323 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2325 return ERR_PTR(-ENOMEM
);
2328 /* Get the list of pages out of our struct file. They'll be pinned
2329 * at this point until we release them.
2331 * Fail silently without starting the shrinker
2333 mapping
= obj
->base
.filp
->f_mapping
;
2334 noreclaim
= mapping_gfp_constraint(mapping
, ~__GFP_RECLAIM
);
2335 noreclaim
|= __GFP_NORETRY
| __GFP_NOWARN
;
2339 for (i
= 0; i
< page_count
; i
++) {
2340 const unsigned int shrink
[] = {
2341 I915_SHRINK_BOUND
| I915_SHRINK_UNBOUND
| I915_SHRINK_PURGEABLE
,
2344 gfp_t gfp
= noreclaim
;
2347 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2348 if (likely(!IS_ERR(page
)))
2352 ret
= PTR_ERR(page
);
2356 i915_gem_shrink(dev_priv
, 2 * page_count
, NULL
, *s
++);
2359 /* We've tried hard to allocate the memory by reaping
2360 * our own buffer, now let the real VM do its job and
2361 * go down in flames if truly OOM.
2363 * However, since graphics tend to be disposable,
2364 * defer the oom here by reporting the ENOMEM back
2368 /* reclaim and warn, but no oom */
2369 gfp
= mapping_gfp_mask(mapping
);
2371 /* Our bo are always dirty and so we require
2372 * kswapd to reclaim our pages (direct reclaim
2373 * does not effectively begin pageout of our
2374 * buffers on its own). However, direct reclaim
2375 * only waits for kswapd when under allocation
2376 * congestion. So as a result __GFP_RECLAIM is
2377 * unreliable and fails to actually reclaim our
2378 * dirty pages -- unless you try over and over
2379 * again with !__GFP_NORETRY. However, we still
2380 * want to fail this allocation rather than
2381 * trigger the out-of-memory killer and for
2382 * this we want __GFP_RETRY_MAYFAIL.
2384 gfp
|= __GFP_RETRY_MAYFAIL
;
2389 sg
->length
>= max_segment
||
2390 page_to_pfn(page
) != last_pfn
+ 1) {
2394 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2396 sg
->length
+= PAGE_SIZE
;
2398 last_pfn
= page_to_pfn(page
);
2400 /* Check that the i965g/gm workaround works. */
2401 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2403 if (sg
) /* loop terminated early; short sg table */
2406 /* Trim unused sg entries to avoid wasting memory. */
2409 ret
= i915_gem_gtt_prepare_pages(obj
, st
);
2411 /* DMA remapping failed? One possible cause is that
2412 * it could not reserve enough large entries, asking
2413 * for PAGE_SIZE chunks instead may be helpful.
2415 if (max_segment
> PAGE_SIZE
) {
2416 for_each_sgt_page(page
, sgt_iter
, st
)
2420 max_segment
= PAGE_SIZE
;
2423 dev_warn(&dev_priv
->drm
.pdev
->dev
,
2424 "Failed to DMA remap %lu pages\n",
2430 if (i915_gem_object_needs_bit17_swizzle(obj
))
2431 i915_gem_object_do_bit_17_swizzle(obj
, st
);
2438 for_each_sgt_page(page
, sgt_iter
, st
)
2443 /* shmemfs first checks if there is enough memory to allocate the page
2444 * and reports ENOSPC should there be insufficient, along with the usual
2445 * ENOMEM for a genuine allocation failure.
2447 * We use ENOSPC in our driver to mean that we have run out of aperture
2448 * space and so want to translate the error from shmemfs back to our
2449 * usual understanding of ENOMEM.
2454 return ERR_PTR(ret
);
2457 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2458 struct sg_table
*pages
)
2460 lockdep_assert_held(&obj
->mm
.lock
);
2462 obj
->mm
.get_page
.sg_pos
= pages
->sgl
;
2463 obj
->mm
.get_page
.sg_idx
= 0;
2465 obj
->mm
.pages
= pages
;
2467 if (i915_gem_object_is_tiled(obj
) &&
2468 to_i915(obj
->base
.dev
)->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
2469 GEM_BUG_ON(obj
->mm
.quirked
);
2470 __i915_gem_object_pin_pages(obj
);
2471 obj
->mm
.quirked
= true;
2475 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2477 struct sg_table
*pages
;
2479 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj
));
2481 if (unlikely(obj
->mm
.madv
!= I915_MADV_WILLNEED
)) {
2482 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2486 pages
= obj
->ops
->get_pages(obj
);
2487 if (unlikely(IS_ERR(pages
)))
2488 return PTR_ERR(pages
);
2490 __i915_gem_object_set_pages(obj
, pages
);
2494 /* Ensure that the associated pages are gathered from the backing storage
2495 * and pinned into our object. i915_gem_object_pin_pages() may be called
2496 * multiple times before they are released by a single call to
2497 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2498 * either as a result of memory pressure (reaping pages under the shrinker)
2499 * or as the object is itself released.
2501 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2505 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
2509 if (unlikely(IS_ERR_OR_NULL(obj
->mm
.pages
))) {
2510 err
= ____i915_gem_object_get_pages(obj
);
2514 smp_mb__before_atomic();
2516 atomic_inc(&obj
->mm
.pages_pin_count
);
2519 mutex_unlock(&obj
->mm
.lock
);
2523 /* The 'mapping' part of i915_gem_object_pin_map() below */
2524 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
,
2525 enum i915_map_type type
)
2527 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2528 struct sg_table
*sgt
= obj
->mm
.pages
;
2529 struct sgt_iter sgt_iter
;
2531 struct page
*stack_pages
[32];
2532 struct page
**pages
= stack_pages
;
2533 unsigned long i
= 0;
2537 /* A single page can always be kmapped */
2538 if (n_pages
== 1 && type
== I915_MAP_WB
)
2539 return kmap(sg_page(sgt
->sgl
));
2541 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2542 /* Too big for stack -- allocate temporary array instead */
2543 pages
= kvmalloc_array(n_pages
, sizeof(*pages
), GFP_KERNEL
);
2548 for_each_sgt_page(page
, sgt_iter
, sgt
)
2551 /* Check that we have the expected number of pages */
2552 GEM_BUG_ON(i
!= n_pages
);
2557 /* fallthrough to use PAGE_KERNEL anyway */
2559 pgprot
= PAGE_KERNEL
;
2562 pgprot
= pgprot_writecombine(PAGE_KERNEL_IO
);
2565 addr
= vmap(pages
, n_pages
, 0, pgprot
);
2567 if (pages
!= stack_pages
)
2573 /* get, pin, and map the pages of the object into kernel space */
2574 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
2575 enum i915_map_type type
)
2577 enum i915_map_type has_type
;
2582 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
2584 ret
= mutex_lock_interruptible(&obj
->mm
.lock
);
2586 return ERR_PTR(ret
);
2588 pinned
= !(type
& I915_MAP_OVERRIDE
);
2589 type
&= ~I915_MAP_OVERRIDE
;
2591 if (!atomic_inc_not_zero(&obj
->mm
.pages_pin_count
)) {
2592 if (unlikely(IS_ERR_OR_NULL(obj
->mm
.pages
))) {
2593 ret
= ____i915_gem_object_get_pages(obj
);
2597 smp_mb__before_atomic();
2599 atomic_inc(&obj
->mm
.pages_pin_count
);
2602 GEM_BUG_ON(!obj
->mm
.pages
);
2604 ptr
= page_unpack_bits(obj
->mm
.mapping
, &has_type
);
2605 if (ptr
&& has_type
!= type
) {
2611 if (is_vmalloc_addr(ptr
))
2614 kunmap(kmap_to_page(ptr
));
2616 ptr
= obj
->mm
.mapping
= NULL
;
2620 ptr
= i915_gem_object_map(obj
, type
);
2626 obj
->mm
.mapping
= page_pack_bits(ptr
, type
);
2630 mutex_unlock(&obj
->mm
.lock
);
2634 atomic_dec(&obj
->mm
.pages_pin_count
);
2641 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object
*obj
,
2642 const struct drm_i915_gem_pwrite
*arg
)
2644 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
2645 char __user
*user_data
= u64_to_user_ptr(arg
->data_ptr
);
2649 /* Before we instantiate/pin the backing store for our use, we
2650 * can prepopulate the shmemfs filp efficiently using a write into
2651 * the pagecache. We avoid the penalty of instantiating all the
2652 * pages, important if the user is just writing to a few and never
2653 * uses the object on the GPU, and using a direct write into shmemfs
2654 * allows it to avoid the cost of retrieving a page (either swapin
2655 * or clearing-before-use) before it is overwritten.
2657 if (READ_ONCE(obj
->mm
.pages
))
2660 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
2663 /* Before the pages are instantiated the object is treated as being
2664 * in the CPU domain. The pages will be clflushed as required before
2665 * use, and we can freely write into the pages directly. If userspace
2666 * races pwrite with any other operation; corruption will ensue -
2667 * that is userspace's prerogative!
2671 offset
= arg
->offset
;
2672 pg
= offset_in_page(offset
);
2675 unsigned int len
, unwritten
;
2680 len
= PAGE_SIZE
- pg
;
2684 err
= pagecache_write_begin(obj
->base
.filp
, mapping
,
2691 unwritten
= copy_from_user(vaddr
+ pg
, user_data
, len
);
2694 err
= pagecache_write_end(obj
->base
.filp
, mapping
,
2695 offset
, len
, len
- unwritten
,
2712 static bool ban_context(const struct i915_gem_context
*ctx
,
2715 return (i915_gem_context_is_bannable(ctx
) &&
2716 score
>= CONTEXT_SCORE_BAN_THRESHOLD
);
2719 static void i915_gem_context_mark_guilty(struct i915_gem_context
*ctx
)
2724 atomic_inc(&ctx
->guilty_count
);
2726 score
= atomic_add_return(CONTEXT_SCORE_GUILTY
, &ctx
->ban_score
);
2727 banned
= ban_context(ctx
, score
);
2728 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2729 ctx
->name
, score
, yesno(banned
));
2733 i915_gem_context_set_banned(ctx
);
2734 if (!IS_ERR_OR_NULL(ctx
->file_priv
)) {
2735 atomic_inc(&ctx
->file_priv
->context_bans
);
2736 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2737 ctx
->name
, atomic_read(&ctx
->file_priv
->context_bans
));
2741 static void i915_gem_context_mark_innocent(struct i915_gem_context
*ctx
)
2743 atomic_inc(&ctx
->active_count
);
2746 struct drm_i915_gem_request
*
2747 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2749 struct drm_i915_gem_request
*request
, *active
= NULL
;
2750 unsigned long flags
;
2752 /* We are called by the error capture and reset at a random
2753 * point in time. In particular, note that neither is crucially
2754 * ordered with an interrupt. After a hang, the GPU is dead and we
2755 * assume that no more writes can happen (we waited long enough for
2756 * all writes that were in transaction to be flushed) - adding an
2757 * extra delay for a recent interrupt is pointless. Hence, we do
2758 * not need an engine->irq_seqno_barrier() before the seqno reads.
2760 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2761 list_for_each_entry(request
, &engine
->timeline
->requests
, link
) {
2762 if (__i915_gem_request_completed(request
,
2763 request
->global_seqno
))
2766 GEM_BUG_ON(request
->engine
!= engine
);
2767 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
,
2768 &request
->fence
.flags
));
2773 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2778 static bool engine_stalled(struct intel_engine_cs
*engine
)
2780 if (!engine
->hangcheck
.stalled
)
2783 /* Check for possible seqno movement after hang declaration */
2784 if (engine
->hangcheck
.seqno
!= intel_engine_get_seqno(engine
)) {
2785 DRM_DEBUG_DRIVER("%s pardoned\n", engine
->name
);
2793 * Ensure irq handler finishes, and not run again.
2794 * Also return the active request so that we only search for it once.
2796 struct drm_i915_gem_request
*
2797 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
)
2799 struct drm_i915_gem_request
*request
= NULL
;
2801 /* Prevent the signaler thread from updating the request
2802 * state (by calling dma_fence_signal) as we are processing
2803 * the reset. The write from the GPU of the seqno is
2804 * asynchronous and the signaler thread may see a different
2805 * value to us and declare the request complete, even though
2806 * the reset routine have picked that request as the active
2807 * (incomplete) request. This conflict is not handled
2810 kthread_park(engine
->breadcrumbs
.signaler
);
2812 /* Prevent request submission to the hardware until we have
2813 * completed the reset in i915_gem_reset_finish(). If a request
2814 * is completed by one engine, it may then queue a request
2815 * to a second via its engine->irq_tasklet *just* as we are
2816 * calling engine->init_hw() and also writing the ELSP.
2817 * Turning off the engine->irq_tasklet until the reset is over
2818 * prevents the race.
2820 tasklet_kill(&engine
->irq_tasklet
);
2821 tasklet_disable(&engine
->irq_tasklet
);
2823 if (engine
->irq_seqno_barrier
)
2824 engine
->irq_seqno_barrier(engine
);
2826 request
= i915_gem_find_active_request(engine
);
2827 if (request
&& request
->fence
.error
== -EIO
)
2828 request
= ERR_PTR(-EIO
); /* Previous reset failed! */
2833 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
)
2835 struct intel_engine_cs
*engine
;
2836 struct drm_i915_gem_request
*request
;
2837 enum intel_engine_id id
;
2840 for_each_engine(engine
, dev_priv
, id
) {
2841 request
= i915_gem_reset_prepare_engine(engine
);
2842 if (IS_ERR(request
)) {
2843 err
= PTR_ERR(request
);
2847 engine
->hangcheck
.active_request
= request
;
2850 i915_gem_revoke_fences(dev_priv
);
2855 static void skip_request(struct drm_i915_gem_request
*request
)
2857 void *vaddr
= request
->ring
->vaddr
;
2860 /* As this request likely depends on state from the lost
2861 * context, clear out all the user operations leaving the
2862 * breadcrumb at the end (so we get the fence notifications).
2864 head
= request
->head
;
2865 if (request
->postfix
< head
) {
2866 memset(vaddr
+ head
, 0, request
->ring
->size
- head
);
2869 memset(vaddr
+ head
, 0, request
->postfix
- head
);
2871 dma_fence_set_error(&request
->fence
, -EIO
);
2874 static void engine_skip_context(struct drm_i915_gem_request
*request
)
2876 struct intel_engine_cs
*engine
= request
->engine
;
2877 struct i915_gem_context
*hung_ctx
= request
->ctx
;
2878 struct intel_timeline
*timeline
;
2879 unsigned long flags
;
2881 timeline
= i915_gem_context_lookup_timeline(hung_ctx
, engine
);
2883 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2884 spin_lock(&timeline
->lock
);
2886 list_for_each_entry_continue(request
, &engine
->timeline
->requests
, link
)
2887 if (request
->ctx
== hung_ctx
)
2888 skip_request(request
);
2890 list_for_each_entry(request
, &timeline
->requests
, link
)
2891 skip_request(request
);
2893 spin_unlock(&timeline
->lock
);
2894 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2897 /* Returns the request if it was guilty of the hang */
2898 static struct drm_i915_gem_request
*
2899 i915_gem_reset_request(struct intel_engine_cs
*engine
,
2900 struct drm_i915_gem_request
*request
)
2902 /* The guilty request will get skipped on a hung engine.
2904 * Users of client default contexts do not rely on logical
2905 * state preserved between batches so it is safe to execute
2906 * queued requests following the hang. Non default contexts
2907 * rely on preserved state, so skipping a batch loses the
2908 * evolution of the state and it needs to be considered corrupted.
2909 * Executing more queued batches on top of corrupted state is
2910 * risky. But we take the risk by trying to advance through
2911 * the queued requests in order to make the client behaviour
2912 * more predictable around resets, by not throwing away random
2913 * amount of batches it has prepared for execution. Sophisticated
2914 * clients can use gem_reset_stats_ioctl and dma fence status
2915 * (exported via sync_file info ioctl on explicit fences) to observe
2916 * when it loses the context state and should rebuild accordingly.
2918 * The context ban, and ultimately the client ban, mechanism are safety
2919 * valves if client submission ends up resulting in nothing more than
2923 if (engine_stalled(engine
)) {
2924 i915_gem_context_mark_guilty(request
->ctx
);
2925 skip_request(request
);
2927 /* If this context is now banned, skip all pending requests. */
2928 if (i915_gem_context_is_banned(request
->ctx
))
2929 engine_skip_context(request
);
2932 * Since this is not the hung engine, it may have advanced
2933 * since the hang declaration. Double check by refinding
2934 * the active request at the time of the reset.
2936 request
= i915_gem_find_active_request(engine
);
2938 i915_gem_context_mark_innocent(request
->ctx
);
2939 dma_fence_set_error(&request
->fence
, -EAGAIN
);
2941 /* Rewind the engine to replay the incomplete rq */
2942 spin_lock_irq(&engine
->timeline
->lock
);
2943 request
= list_prev_entry(request
, link
);
2944 if (&request
->link
== &engine
->timeline
->requests
)
2946 spin_unlock_irq(&engine
->timeline
->lock
);
2953 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
2954 struct drm_i915_gem_request
*request
)
2956 engine
->irq_posted
= 0;
2959 request
= i915_gem_reset_request(engine
, request
);
2962 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2963 engine
->name
, request
->global_seqno
);
2966 /* Setup the CS to resume from the breadcrumb of the hung request */
2967 engine
->reset_hw(engine
, request
);
2970 void i915_gem_reset(struct drm_i915_private
*dev_priv
)
2972 struct intel_engine_cs
*engine
;
2973 enum intel_engine_id id
;
2975 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2977 i915_gem_retire_requests(dev_priv
);
2979 for_each_engine(engine
, dev_priv
, id
) {
2980 struct i915_gem_context
*ctx
;
2982 i915_gem_reset_engine(engine
, engine
->hangcheck
.active_request
);
2983 ctx
= fetch_and_zero(&engine
->last_retired_context
);
2985 engine
->context_unpin(engine
, ctx
);
2988 i915_gem_restore_fences(dev_priv
);
2990 if (dev_priv
->gt
.awake
) {
2991 intel_sanitize_gt_powersave(dev_priv
);
2992 intel_enable_gt_powersave(dev_priv
);
2993 if (INTEL_GEN(dev_priv
) >= 6)
2994 gen6_rps_busy(dev_priv
);
2998 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
)
3000 tasklet_enable(&engine
->irq_tasklet
);
3001 kthread_unpark(engine
->breadcrumbs
.signaler
);
3004 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
)
3006 struct intel_engine_cs
*engine
;
3007 enum intel_engine_id id
;
3009 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
3011 for_each_engine(engine
, dev_priv
, id
) {
3012 engine
->hangcheck
.active_request
= NULL
;
3013 i915_gem_reset_finish_engine(engine
);
3017 static void nop_submit_request(struct drm_i915_gem_request
*request
)
3019 unsigned long flags
;
3021 GEM_BUG_ON(!i915_terminally_wedged(&request
->i915
->gpu_error
));
3022 dma_fence_set_error(&request
->fence
, -EIO
);
3024 spin_lock_irqsave(&request
->engine
->timeline
->lock
, flags
);
3025 __i915_gem_request_submit(request
);
3026 intel_engine_init_global_seqno(request
->engine
, request
->global_seqno
);
3027 spin_unlock_irqrestore(&request
->engine
->timeline
->lock
, flags
);
3030 static void engine_set_wedged(struct intel_engine_cs
*engine
)
3032 struct drm_i915_gem_request
*request
;
3033 unsigned long flags
;
3035 /* We need to be sure that no thread is running the old callback as
3036 * we install the nop handler (otherwise we would submit a request
3037 * to hardware that will never complete). In order to prevent this
3038 * race, we wait until the machine is idle before making the swap
3039 * (using stop_machine()).
3041 engine
->submit_request
= nop_submit_request
;
3043 /* Mark all executing requests as skipped */
3044 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
3045 list_for_each_entry(request
, &engine
->timeline
->requests
, link
)
3046 if (!i915_gem_request_completed(request
))
3047 dma_fence_set_error(&request
->fence
, -EIO
);
3048 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
3051 * Clear the execlists queue up before freeing the requests, as those
3052 * are the ones that keep the context and ringbuffer backing objects
3056 if (i915
.enable_execlists
) {
3057 struct execlist_port
*port
= engine
->execlist_port
;
3058 unsigned long flags
;
3061 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
3063 for (n
= 0; n
< ARRAY_SIZE(engine
->execlist_port
); n
++)
3064 i915_gem_request_put(port_request(&port
[n
]));
3065 memset(engine
->execlist_port
, 0, sizeof(engine
->execlist_port
));
3066 engine
->execlist_queue
= RB_ROOT
;
3067 engine
->execlist_first
= NULL
;
3069 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
3071 /* The port is checked prior to scheduling a tasklet, but
3072 * just in case we have suspended the tasklet to do the
3073 * wedging make sure that when it wakes, it decides there
3074 * is no work to do by clearing the irq_posted bit.
3076 clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
3079 /* Mark all pending requests as complete so that any concurrent
3080 * (lockless) lookup doesn't try and wait upon the request as we
3083 intel_engine_init_global_seqno(engine
,
3084 intel_engine_last_submit(engine
));
3087 static int __i915_gem_set_wedged_BKL(void *data
)
3089 struct drm_i915_private
*i915
= data
;
3090 struct intel_engine_cs
*engine
;
3091 enum intel_engine_id id
;
3093 for_each_engine(engine
, i915
, id
)
3094 engine_set_wedged(engine
);
3096 set_bit(I915_WEDGED
, &i915
->gpu_error
.flags
);
3097 wake_up_all(&i915
->gpu_error
.reset_queue
);
3102 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
)
3104 stop_machine(__i915_gem_set_wedged_BKL
, dev_priv
, NULL
);
3107 bool i915_gem_unset_wedged(struct drm_i915_private
*i915
)
3109 struct i915_gem_timeline
*tl
;
3112 lockdep_assert_held(&i915
->drm
.struct_mutex
);
3113 if (!test_bit(I915_WEDGED
, &i915
->gpu_error
.flags
))
3116 /* Before unwedging, make sure that all pending operations
3117 * are flushed and errored out - we may have requests waiting upon
3118 * third party fences. We marked all inflight requests as EIO, and
3119 * every execbuf since returned EIO, for consistency we want all
3120 * the currently pending requests to also be marked as EIO, which
3121 * is done inside our nop_submit_request - and so we must wait.
3123 * No more can be submitted until we reset the wedged bit.
3125 list_for_each_entry(tl
, &i915
->gt
.timelines
, link
) {
3126 for (i
= 0; i
< ARRAY_SIZE(tl
->engine
); i
++) {
3127 struct drm_i915_gem_request
*rq
;
3129 rq
= i915_gem_active_peek(&tl
->engine
[i
].last_request
,
3130 &i915
->drm
.struct_mutex
);
3134 /* We can't use our normal waiter as we want to
3135 * avoid recursively trying to handle the current
3136 * reset. The basic dma_fence_default_wait() installs
3137 * a callback for dma_fence_signal(), which is
3138 * triggered by our nop handler (indirectly, the
3139 * callback enables the signaler thread which is
3140 * woken by the nop_submit_request() advancing the seqno
3141 * and when the seqno passes the fence, the signaler
3142 * then signals the fence waking us up).
3144 if (dma_fence_default_wait(&rq
->fence
, true,
3145 MAX_SCHEDULE_TIMEOUT
) < 0)
3150 /* Undo nop_submit_request. We prevent all new i915 requests from
3151 * being queued (by disallowing execbuf whilst wedged) so having
3152 * waited for all active requests above, we know the system is idle
3153 * and do not have to worry about a thread being inside
3154 * engine->submit_request() as we swap over. So unlike installing
3155 * the nop_submit_request on reset, we can do this from normal
3156 * context and do not require stop_machine().
3158 intel_engines_reset_default_submission(i915
);
3159 i915_gem_contexts_lost(i915
);
3161 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3162 clear_bit(I915_WEDGED
, &i915
->gpu_error
.flags
);
3168 i915_gem_retire_work_handler(struct work_struct
*work
)
3170 struct drm_i915_private
*dev_priv
=
3171 container_of(work
, typeof(*dev_priv
), gt
.retire_work
.work
);
3172 struct drm_device
*dev
= &dev_priv
->drm
;
3174 /* Come back later if the device is busy... */
3175 if (mutex_trylock(&dev
->struct_mutex
)) {
3176 i915_gem_retire_requests(dev_priv
);
3177 mutex_unlock(&dev
->struct_mutex
);
3180 /* Keep the retire handler running until we are finally idle.
3181 * We do not need to do this test under locking as in the worst-case
3182 * we queue the retire worker once too often.
3184 if (READ_ONCE(dev_priv
->gt
.awake
)) {
3185 i915_queue_hangcheck(dev_priv
);
3186 queue_delayed_work(dev_priv
->wq
,
3187 &dev_priv
->gt
.retire_work
,
3188 round_jiffies_up_relative(HZ
));
3193 i915_gem_idle_work_handler(struct work_struct
*work
)
3195 struct drm_i915_private
*dev_priv
=
3196 container_of(work
, typeof(*dev_priv
), gt
.idle_work
.work
);
3197 struct drm_device
*dev
= &dev_priv
->drm
;
3198 bool rearm_hangcheck
;
3200 if (!READ_ONCE(dev_priv
->gt
.awake
))
3204 * Wait for last execlists context complete, but bail out in case a
3205 * new request is submitted.
3207 wait_for(intel_engines_are_idle(dev_priv
), 10);
3208 if (READ_ONCE(dev_priv
->gt
.active_requests
))
3212 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
3214 if (!mutex_trylock(&dev
->struct_mutex
)) {
3215 /* Currently busy, come back later */
3216 mod_delayed_work(dev_priv
->wq
,
3217 &dev_priv
->gt
.idle_work
,
3218 msecs_to_jiffies(50));
3223 * New request retired after this work handler started, extend active
3224 * period until next instance of the work.
3226 if (work_pending(work
))
3229 if (dev_priv
->gt
.active_requests
)
3232 if (wait_for(intel_engines_are_idle(dev_priv
), 10))
3233 DRM_ERROR("Timeout waiting for engines to idle\n");
3235 intel_engines_mark_idle(dev_priv
);
3236 i915_gem_timelines_mark_idle(dev_priv
);
3238 GEM_BUG_ON(!dev_priv
->gt
.awake
);
3239 dev_priv
->gt
.awake
= false;
3240 rearm_hangcheck
= false;
3242 if (INTEL_GEN(dev_priv
) >= 6)
3243 gen6_rps_idle(dev_priv
);
3244 intel_runtime_pm_put(dev_priv
);
3246 mutex_unlock(&dev
->struct_mutex
);
3249 if (rearm_hangcheck
) {
3250 GEM_BUG_ON(!dev_priv
->gt
.awake
);
3251 i915_queue_hangcheck(dev_priv
);
3255 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
)
3257 struct drm_i915_private
*i915
= to_i915(gem
->dev
);
3258 struct drm_i915_gem_object
*obj
= to_intel_bo(gem
);
3259 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
3260 struct i915_lut_handle
*lut
, *ln
;
3262 mutex_lock(&i915
->drm
.struct_mutex
);
3264 list_for_each_entry_safe(lut
, ln
, &obj
->lut_list
, obj_link
) {
3265 struct i915_gem_context
*ctx
= lut
->ctx
;
3266 struct i915_vma
*vma
;
3268 if (ctx
->file_priv
!= fpriv
)
3271 vma
= radix_tree_delete(&ctx
->handles_vma
, lut
->handle
);
3273 GEM_BUG_ON(vma
->obj
!= obj
);
3275 /* We allow the process to have multiple handles to the same
3276 * vma, in the same fd namespace, by virtue of flink/open.
3278 GEM_BUG_ON(!vma
->open_count
);
3279 if (!--vma
->open_count
&& !i915_vma_is_ggtt(vma
))
3280 i915_vma_close(vma
);
3282 list_del(&lut
->obj_link
);
3283 list_del(&lut
->ctx_link
);
3285 kmem_cache_free(i915
->luts
, lut
);
3286 __i915_gem_object_release_unless_active(obj
);
3289 mutex_unlock(&i915
->drm
.struct_mutex
);
3292 static unsigned long to_wait_timeout(s64 timeout_ns
)
3295 return MAX_SCHEDULE_TIMEOUT
;
3297 if (timeout_ns
== 0)
3300 return nsecs_to_jiffies_timeout(timeout_ns
);
3304 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3305 * @dev: drm device pointer
3306 * @data: ioctl data blob
3307 * @file: drm file pointer
3309 * Returns 0 if successful, else an error is returned with the remaining time in
3310 * the timeout parameter.
3311 * -ETIME: object is still busy after timeout
3312 * -ERESTARTSYS: signal interrupted the wait
3313 * -ENONENT: object doesn't exist
3314 * Also possible, but rare:
3315 * -EAGAIN: incomplete, restart syscall
3317 * -ENODEV: Internal IRQ fail
3318 * -E?: The add request failed
3320 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3321 * non-zero timeout parameter the wait ioctl will wait for the given number of
3322 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3323 * without holding struct_mutex the object may become re-busied before this
3324 * function completes. A similar but shorter * race condition exists in the busy
3328 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3330 struct drm_i915_gem_wait
*args
= data
;
3331 struct drm_i915_gem_object
*obj
;
3335 if (args
->flags
!= 0)
3338 obj
= i915_gem_object_lookup(file
, args
->bo_handle
);
3342 start
= ktime_get();
3344 ret
= i915_gem_object_wait(obj
,
3345 I915_WAIT_INTERRUPTIBLE
| I915_WAIT_ALL
,
3346 to_wait_timeout(args
->timeout_ns
),
3347 to_rps_client(file
));
3349 if (args
->timeout_ns
> 0) {
3350 args
->timeout_ns
-= ktime_to_ns(ktime_sub(ktime_get(), start
));
3351 if (args
->timeout_ns
< 0)
3352 args
->timeout_ns
= 0;
3355 * Apparently ktime isn't accurate enough and occasionally has a
3356 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3357 * things up to make the test happy. We allow up to 1 jiffy.
3359 * This is a regression from the timespec->ktime conversion.
3361 if (ret
== -ETIME
&& !nsecs_to_jiffies(args
->timeout_ns
))
3362 args
->timeout_ns
= 0;
3364 /* Asked to wait beyond the jiffie/scheduler precision? */
3365 if (ret
== -ETIME
&& args
->timeout_ns
)
3369 i915_gem_object_put(obj
);
3373 static int wait_for_timeline(struct i915_gem_timeline
*tl
, unsigned int flags
)
3377 for (i
= 0; i
< ARRAY_SIZE(tl
->engine
); i
++) {
3378 ret
= i915_gem_active_wait(&tl
->engine
[i
].last_request
, flags
);
3386 static int wait_for_engine(struct intel_engine_cs
*engine
, int timeout_ms
)
3388 return wait_for(intel_engine_is_idle(engine
), timeout_ms
);
3391 static int wait_for_engines(struct drm_i915_private
*i915
)
3393 struct intel_engine_cs
*engine
;
3394 enum intel_engine_id id
;
3396 for_each_engine(engine
, i915
, id
) {
3397 if (GEM_WARN_ON(wait_for_engine(engine
, 50))) {
3398 i915_gem_set_wedged(i915
);
3402 GEM_BUG_ON(intel_engine_get_seqno(engine
) !=
3403 intel_engine_last_submit(engine
));
3409 int i915_gem_wait_for_idle(struct drm_i915_private
*i915
, unsigned int flags
)
3413 /* If the device is asleep, we have no requests outstanding */
3414 if (!READ_ONCE(i915
->gt
.awake
))
3417 if (flags
& I915_WAIT_LOCKED
) {
3418 struct i915_gem_timeline
*tl
;
3420 lockdep_assert_held(&i915
->drm
.struct_mutex
);
3422 list_for_each_entry(tl
, &i915
->gt
.timelines
, link
) {
3423 ret
= wait_for_timeline(tl
, flags
);
3428 i915_gem_retire_requests(i915
);
3429 GEM_BUG_ON(i915
->gt
.active_requests
);
3431 ret
= wait_for_engines(i915
);
3433 ret
= wait_for_timeline(&i915
->gt
.global_timeline
, flags
);
3439 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object
*obj
)
3442 * We manually flush the CPU domain so that we can override and
3443 * force the flush for the display, and perform it asyncrhonously.
3445 flush_write_domain(obj
, ~I915_GEM_DOMAIN_CPU
);
3446 if (obj
->cache_dirty
)
3447 i915_gem_clflush_object(obj
, I915_CLFLUSH_FORCE
);
3448 obj
->base
.write_domain
= 0;
3451 void i915_gem_object_flush_if_display(struct drm_i915_gem_object
*obj
)
3453 if (!READ_ONCE(obj
->pin_display
))
3456 mutex_lock(&obj
->base
.dev
->struct_mutex
);
3457 __i915_gem_object_flush_for_display(obj
);
3458 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
3462 * Moves a single object to the WC read, and possibly write domain.
3463 * @obj: object to act on
3464 * @write: ask for write access or read only
3466 * This function returns when the move is complete, including waiting on
3470 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
)
3474 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3476 ret
= i915_gem_object_wait(obj
,
3477 I915_WAIT_INTERRUPTIBLE
|
3479 (write
? I915_WAIT_ALL
: 0),
3480 MAX_SCHEDULE_TIMEOUT
,
3485 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_WC
)
3488 /* Flush and acquire obj->pages so that we are coherent through
3489 * direct access in memory with previous cached writes through
3490 * shmemfs and that our cache domain tracking remains valid.
3491 * For example, if the obj->filp was moved to swap without us
3492 * being notified and releasing the pages, we would mistakenly
3493 * continue to assume that the obj remained out of the CPU cached
3496 ret
= i915_gem_object_pin_pages(obj
);
3500 flush_write_domain(obj
, ~I915_GEM_DOMAIN_WC
);
3502 /* Serialise direct access to this object with the barriers for
3503 * coherent writes from the GPU, by effectively invalidating the
3504 * WC domain upon first access.
3506 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_WC
) == 0)
3509 /* It should now be out of any other write domains, and we can update
3510 * the domain values for our changes.
3512 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_WC
) != 0);
3513 obj
->base
.read_domains
|= I915_GEM_DOMAIN_WC
;
3515 obj
->base
.read_domains
= I915_GEM_DOMAIN_WC
;
3516 obj
->base
.write_domain
= I915_GEM_DOMAIN_WC
;
3517 obj
->mm
.dirty
= true;
3520 i915_gem_object_unpin_pages(obj
);
3525 * Moves a single object to the GTT read, and possibly write domain.
3526 * @obj: object to act on
3527 * @write: ask for write access or read only
3529 * This function returns when the move is complete, including waiting on
3533 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3537 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3539 ret
= i915_gem_object_wait(obj
,
3540 I915_WAIT_INTERRUPTIBLE
|
3542 (write
? I915_WAIT_ALL
: 0),
3543 MAX_SCHEDULE_TIMEOUT
,
3548 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3551 /* Flush and acquire obj->pages so that we are coherent through
3552 * direct access in memory with previous cached writes through
3553 * shmemfs and that our cache domain tracking remains valid.
3554 * For example, if the obj->filp was moved to swap without us
3555 * being notified and releasing the pages, we would mistakenly
3556 * continue to assume that the obj remained out of the CPU cached
3559 ret
= i915_gem_object_pin_pages(obj
);
3563 flush_write_domain(obj
, ~I915_GEM_DOMAIN_GTT
);
3565 /* Serialise direct access to this object with the barriers for
3566 * coherent writes from the GPU, by effectively invalidating the
3567 * GTT domain upon first access.
3569 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3572 /* It should now be out of any other write domains, and we can update
3573 * the domain values for our changes.
3575 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3576 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3578 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3579 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3580 obj
->mm
.dirty
= true;
3583 i915_gem_object_unpin_pages(obj
);
3588 * Changes the cache-level of an object across all VMA.
3589 * @obj: object to act on
3590 * @cache_level: new cache level to set for the object
3592 * After this function returns, the object will be in the new cache-level
3593 * across all GTT and the contents of the backing storage will be coherent,
3594 * with respect to the new cache-level. In order to keep the backing storage
3595 * coherent for all users, we only allow a single cache level to be set
3596 * globally on the object and prevent it from being changed whilst the
3597 * hardware is reading from the object. That is if the object is currently
3598 * on the scanout it will be set to uncached (or equivalent display
3599 * cache coherency) and all non-MOCS GPU access will also be uncached so
3600 * that all direct access to the scanout remains coherent.
3602 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3603 enum i915_cache_level cache_level
)
3605 struct i915_vma
*vma
;
3608 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3610 if (obj
->cache_level
== cache_level
)
3613 /* Inspect the list of currently bound VMA and unbind any that would
3614 * be invalid given the new cache-level. This is principally to
3615 * catch the issue of the CS prefetch crossing page boundaries and
3616 * reading an invalid PTE on older architectures.
3619 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3620 if (!drm_mm_node_allocated(&vma
->node
))
3623 if (i915_vma_is_pinned(vma
)) {
3624 DRM_DEBUG("can not change the cache level of pinned objects\n");
3628 if (i915_gem_valid_gtt_space(vma
, cache_level
))
3631 ret
= i915_vma_unbind(vma
);
3635 /* As unbinding may affect other elements in the
3636 * obj->vma_list (due to side-effects from retiring
3637 * an active vma), play safe and restart the iterator.
3642 /* We can reuse the existing drm_mm nodes but need to change the
3643 * cache-level on the PTE. We could simply unbind them all and
3644 * rebind with the correct cache-level on next use. However since
3645 * we already have a valid slot, dma mapping, pages etc, we may as
3646 * rewrite the PTE in the belief that doing so tramples upon less
3647 * state and so involves less work.
3649 if (obj
->bind_count
) {
3650 /* Before we change the PTE, the GPU must not be accessing it.
3651 * If we wait upon the object, we know that all the bound
3652 * VMA are no longer active.
3654 ret
= i915_gem_object_wait(obj
,
3655 I915_WAIT_INTERRUPTIBLE
|
3658 MAX_SCHEDULE_TIMEOUT
,
3663 if (!HAS_LLC(to_i915(obj
->base
.dev
)) &&
3664 cache_level
!= I915_CACHE_NONE
) {
3665 /* Access to snoopable pages through the GTT is
3666 * incoherent and on some machines causes a hard
3667 * lockup. Relinquish the CPU mmaping to force
3668 * userspace to refault in the pages and we can
3669 * then double check if the GTT mapping is still
3670 * valid for that pointer access.
3672 i915_gem_release_mmap(obj
);
3674 /* As we no longer need a fence for GTT access,
3675 * we can relinquish it now (and so prevent having
3676 * to steal a fence from someone else on the next
3677 * fence request). Note GPU activity would have
3678 * dropped the fence as all snoopable access is
3679 * supposed to be linear.
3681 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3682 ret
= i915_vma_put_fence(vma
);
3687 /* We either have incoherent backing store and
3688 * so no GTT access or the architecture is fully
3689 * coherent. In such cases, existing GTT mmaps
3690 * ignore the cache bit in the PTE and we can
3691 * rewrite it without confusing the GPU or having
3692 * to force userspace to fault back in its mmaps.
3696 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3697 if (!drm_mm_node_allocated(&vma
->node
))
3700 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3706 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3707 vma
->node
.color
= cache_level
;
3708 i915_gem_object_set_cache_coherency(obj
, cache_level
);
3709 obj
->cache_dirty
= true; /* Always invalidate stale cachelines */
3714 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3715 struct drm_file
*file
)
3717 struct drm_i915_gem_caching
*args
= data
;
3718 struct drm_i915_gem_object
*obj
;
3722 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3728 switch (obj
->cache_level
) {
3729 case I915_CACHE_LLC
:
3730 case I915_CACHE_L3_LLC
:
3731 args
->caching
= I915_CACHING_CACHED
;
3735 args
->caching
= I915_CACHING_DISPLAY
;
3739 args
->caching
= I915_CACHING_NONE
;
3747 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3748 struct drm_file
*file
)
3750 struct drm_i915_private
*i915
= to_i915(dev
);
3751 struct drm_i915_gem_caching
*args
= data
;
3752 struct drm_i915_gem_object
*obj
;
3753 enum i915_cache_level level
;
3756 switch (args
->caching
) {
3757 case I915_CACHING_NONE
:
3758 level
= I915_CACHE_NONE
;
3760 case I915_CACHING_CACHED
:
3762 * Due to a HW issue on BXT A stepping, GPU stores via a
3763 * snooped mapping may leave stale data in a corresponding CPU
3764 * cacheline, whereas normally such cachelines would get
3767 if (!HAS_LLC(i915
) && !HAS_SNOOP(i915
))
3770 level
= I915_CACHE_LLC
;
3772 case I915_CACHING_DISPLAY
:
3773 level
= HAS_WT(i915
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3779 obj
= i915_gem_object_lookup(file
, args
->handle
);
3783 if (obj
->cache_level
== level
)
3786 ret
= i915_gem_object_wait(obj
,
3787 I915_WAIT_INTERRUPTIBLE
,
3788 MAX_SCHEDULE_TIMEOUT
,
3789 to_rps_client(file
));
3793 ret
= i915_mutex_lock_interruptible(dev
);
3797 ret
= i915_gem_object_set_cache_level(obj
, level
);
3798 mutex_unlock(&dev
->struct_mutex
);
3801 i915_gem_object_put(obj
);
3806 * Prepare buffer for display plane (scanout, cursors, etc).
3807 * Can be called from an uninterruptible phase (modesetting) and allows
3808 * any flushes to be pipelined (for pageflips).
3811 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3813 const struct i915_ggtt_view
*view
)
3815 struct i915_vma
*vma
;
3818 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3820 /* Mark the pin_display early so that we account for the
3821 * display coherency whilst setting up the cache domains.
3825 /* The display engine is not coherent with the LLC cache on gen6. As
3826 * a result, we make sure that the pinning that is about to occur is
3827 * done with uncached PTEs. This is lowest common denominator for all
3830 * However for gen6+, we could do better by using the GFDT bit instead
3831 * of uncaching, which would allow us to flush all the LLC-cached data
3832 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3834 ret
= i915_gem_object_set_cache_level(obj
,
3835 HAS_WT(to_i915(obj
->base
.dev
)) ?
3836 I915_CACHE_WT
: I915_CACHE_NONE
);
3839 goto err_unpin_display
;
3842 /* As the user may map the buffer once pinned in the display plane
3843 * (e.g. libkms for the bootup splash), we have to ensure that we
3844 * always use map_and_fenceable for all scanout buffers. However,
3845 * it may simply be too big to fit into mappable, in which case
3846 * put it anyway and hope that userspace can cope (but always first
3847 * try to preserve the existing ABI).
3849 vma
= ERR_PTR(-ENOSPC
);
3850 if (!view
|| view
->type
== I915_GGTT_VIEW_NORMAL
)
3851 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
,
3852 PIN_MAPPABLE
| PIN_NONBLOCK
);
3854 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3857 /* Valleyview is definitely limited to scanning out the first
3858 * 512MiB. Lets presume this behaviour was inherited from the
3859 * g4x display engine and that all earlier gen are similarly
3860 * limited. Testing suggests that it is a little more
3861 * complicated than this. For example, Cherryview appears quite
3862 * happy to scanout from anywhere within its global aperture.
3865 if (HAS_GMCH_DISPLAY(i915
))
3866 flags
= PIN_MAPPABLE
;
3867 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
, flags
);
3870 goto err_unpin_display
;
3872 vma
->display_alignment
= max_t(u64
, vma
->display_alignment
, alignment
);
3874 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3875 __i915_gem_object_flush_for_display(obj
);
3876 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
3878 /* It should now be out of any other write domains, and we can update
3879 * the domain values for our changes.
3881 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3891 i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
)
3893 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
3895 if (WARN_ON(vma
->obj
->pin_display
== 0))
3898 if (--vma
->obj
->pin_display
== 0)
3899 vma
->display_alignment
= I915_GTT_MIN_ALIGNMENT
;
3901 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3902 i915_gem_object_bump_inactive_ggtt(vma
->obj
);
3904 i915_vma_unpin(vma
);
3908 * Moves a single object to the CPU read, and possibly write domain.
3909 * @obj: object to act on
3910 * @write: requesting write or read-only access
3912 * This function returns when the move is complete, including waiting on
3916 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3920 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3922 ret
= i915_gem_object_wait(obj
,
3923 I915_WAIT_INTERRUPTIBLE
|
3925 (write
? I915_WAIT_ALL
: 0),
3926 MAX_SCHEDULE_TIMEOUT
,
3931 flush_write_domain(obj
, ~I915_GEM_DOMAIN_CPU
);
3933 /* Flush the CPU cache if it's still invalid. */
3934 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3935 i915_gem_clflush_object(obj
, I915_CLFLUSH_SYNC
);
3936 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3939 /* It should now be out of any other write domains, and we can update
3940 * the domain values for our changes.
3942 GEM_BUG_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3944 /* If we're writing through the CPU, then the GPU read domains will
3945 * need to be invalidated at next use.
3948 __start_cpu_write(obj
);
3953 /* Throttle our rendering by waiting until the ring has completed our requests
3954 * emitted over 20 msec ago.
3956 * Note that if we were to use the current jiffies each time around the loop,
3957 * we wouldn't escape the function with any frames outstanding if the time to
3958 * render a frame was over 20ms.
3960 * This should get us reasonable parallelism between CPU and GPU but also
3961 * relatively low latency when blocking on a particular request to finish.
3964 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3966 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3967 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3968 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
3969 struct drm_i915_gem_request
*request
, *target
= NULL
;
3972 /* ABI: return -EIO if already wedged */
3973 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
3976 spin_lock(&file_priv
->mm
.lock
);
3977 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_link
) {
3978 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3982 list_del(&target
->client_link
);
3983 target
->file_priv
= NULL
;
3989 i915_gem_request_get(target
);
3990 spin_unlock(&file_priv
->mm
.lock
);
3995 ret
= i915_wait_request(target
,
3996 I915_WAIT_INTERRUPTIBLE
,
3997 MAX_SCHEDULE_TIMEOUT
);
3998 i915_gem_request_put(target
);
4000 return ret
< 0 ? ret
: 0;
4004 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4005 const struct i915_ggtt_view
*view
,
4010 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
4011 struct i915_address_space
*vm
= &dev_priv
->ggtt
.base
;
4012 struct i915_vma
*vma
;
4015 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
4017 vma
= i915_vma_instance(obj
, vm
, view
);
4018 if (unlikely(IS_ERR(vma
)))
4021 if (i915_vma_misplaced(vma
, size
, alignment
, flags
)) {
4022 if (flags
& PIN_NONBLOCK
&&
4023 (i915_vma_is_pinned(vma
) || i915_vma_is_active(vma
)))
4024 return ERR_PTR(-ENOSPC
);
4026 if (flags
& PIN_MAPPABLE
) {
4027 /* If the required space is larger than the available
4028 * aperture, we will not able to find a slot for the
4029 * object and unbinding the object now will be in
4030 * vain. Worse, doing so may cause us to ping-pong
4031 * the object in and out of the Global GTT and
4032 * waste a lot of cycles under the mutex.
4034 if (vma
->fence_size
> dev_priv
->ggtt
.mappable_end
)
4035 return ERR_PTR(-E2BIG
);
4037 /* If NONBLOCK is set the caller is optimistically
4038 * trying to cache the full object within the mappable
4039 * aperture, and *must* have a fallback in place for
4040 * situations where we cannot bind the object. We
4041 * can be a little more lax here and use the fallback
4042 * more often to avoid costly migrations of ourselves
4043 * and other objects within the aperture.
4045 * Half-the-aperture is used as a simple heuristic.
4046 * More interesting would to do search for a free
4047 * block prior to making the commitment to unbind.
4048 * That caters for the self-harm case, and with a
4049 * little more heuristics (e.g. NOFAULT, NOEVICT)
4050 * we could try to minimise harm to others.
4052 if (flags
& PIN_NONBLOCK
&&
4053 vma
->fence_size
> dev_priv
->ggtt
.mappable_end
/ 2)
4054 return ERR_PTR(-ENOSPC
);
4057 WARN(i915_vma_is_pinned(vma
),
4058 "bo is already pinned in ggtt with incorrect alignment:"
4059 " offset=%08x, req.alignment=%llx,"
4060 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
4061 i915_ggtt_offset(vma
), alignment
,
4062 !!(flags
& PIN_MAPPABLE
),
4063 i915_vma_is_map_and_fenceable(vma
));
4064 ret
= i915_vma_unbind(vma
);
4066 return ERR_PTR(ret
);
4069 ret
= i915_vma_pin(vma
, size
, alignment
, flags
| PIN_GLOBAL
);
4071 return ERR_PTR(ret
);
4076 static __always_inline
unsigned int __busy_read_flag(unsigned int id
)
4078 /* Note that we could alias engines in the execbuf API, but
4079 * that would be very unwise as it prevents userspace from
4080 * fine control over engine selection. Ahem.
4082 * This should be something like EXEC_MAX_ENGINE instead of
4085 BUILD_BUG_ON(I915_NUM_ENGINES
> 16);
4086 return 0x10000 << id
;
4089 static __always_inline
unsigned int __busy_write_id(unsigned int id
)
4091 /* The uABI guarantees an active writer is also amongst the read
4092 * engines. This would be true if we accessed the activity tracking
4093 * under the lock, but as we perform the lookup of the object and
4094 * its activity locklessly we can not guarantee that the last_write
4095 * being active implies that we have set the same engine flag from
4096 * last_read - hence we always set both read and write busy for
4099 return id
| __busy_read_flag(id
);
4102 static __always_inline
unsigned int
4103 __busy_set_if_active(const struct dma_fence
*fence
,
4104 unsigned int (*flag
)(unsigned int id
))
4106 struct drm_i915_gem_request
*rq
;
4108 /* We have to check the current hw status of the fence as the uABI
4109 * guarantees forward progress. We could rely on the idle worker
4110 * to eventually flush us, but to minimise latency just ask the
4113 * Note we only report on the status of native fences.
4115 if (!dma_fence_is_i915(fence
))
4118 /* opencode to_request() in order to avoid const warnings */
4119 rq
= container_of(fence
, struct drm_i915_gem_request
, fence
);
4120 if (i915_gem_request_completed(rq
))
4123 return flag(rq
->engine
->uabi_id
);
4126 static __always_inline
unsigned int
4127 busy_check_reader(const struct dma_fence
*fence
)
4129 return __busy_set_if_active(fence
, __busy_read_flag
);
4132 static __always_inline
unsigned int
4133 busy_check_writer(const struct dma_fence
*fence
)
4138 return __busy_set_if_active(fence
, __busy_write_id
);
4142 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4143 struct drm_file
*file
)
4145 struct drm_i915_gem_busy
*args
= data
;
4146 struct drm_i915_gem_object
*obj
;
4147 struct reservation_object_list
*list
;
4153 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
4157 /* A discrepancy here is that we do not report the status of
4158 * non-i915 fences, i.e. even though we may report the object as idle,
4159 * a call to set-domain may still stall waiting for foreign rendering.
4160 * This also means that wait-ioctl may report an object as busy,
4161 * where busy-ioctl considers it idle.
4163 * We trade the ability to warn of foreign fences to report on which
4164 * i915 engines are active for the object.
4166 * Alternatively, we can trade that extra information on read/write
4169 * !reservation_object_test_signaled_rcu(obj->resv, true);
4170 * to report the overall busyness. This is what the wait-ioctl does.
4174 seq
= raw_read_seqcount(&obj
->resv
->seq
);
4176 /* Translate the exclusive fence to the READ *and* WRITE engine */
4177 args
->busy
= busy_check_writer(rcu_dereference(obj
->resv
->fence_excl
));
4179 /* Translate shared fences to READ set of engines */
4180 list
= rcu_dereference(obj
->resv
->fence
);
4182 unsigned int shared_count
= list
->shared_count
, i
;
4184 for (i
= 0; i
< shared_count
; ++i
) {
4185 struct dma_fence
*fence
=
4186 rcu_dereference(list
->shared
[i
]);
4188 args
->busy
|= busy_check_reader(fence
);
4192 if (args
->busy
&& read_seqcount_retry(&obj
->resv
->seq
, seq
))
4202 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4203 struct drm_file
*file_priv
)
4205 return i915_gem_ring_throttle(dev
, file_priv
);
4209 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4210 struct drm_file
*file_priv
)
4212 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4213 struct drm_i915_gem_madvise
*args
= data
;
4214 struct drm_i915_gem_object
*obj
;
4217 switch (args
->madv
) {
4218 case I915_MADV_DONTNEED
:
4219 case I915_MADV_WILLNEED
:
4225 obj
= i915_gem_object_lookup(file_priv
, args
->handle
);
4229 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
4233 if (obj
->mm
.pages
&&
4234 i915_gem_object_is_tiled(obj
) &&
4235 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4236 if (obj
->mm
.madv
== I915_MADV_WILLNEED
) {
4237 GEM_BUG_ON(!obj
->mm
.quirked
);
4238 __i915_gem_object_unpin_pages(obj
);
4239 obj
->mm
.quirked
= false;
4241 if (args
->madv
== I915_MADV_WILLNEED
) {
4242 GEM_BUG_ON(obj
->mm
.quirked
);
4243 __i915_gem_object_pin_pages(obj
);
4244 obj
->mm
.quirked
= true;
4248 if (obj
->mm
.madv
!= __I915_MADV_PURGED
)
4249 obj
->mm
.madv
= args
->madv
;
4251 /* if the object is no longer attached, discard its backing storage */
4252 if (obj
->mm
.madv
== I915_MADV_DONTNEED
&& !obj
->mm
.pages
)
4253 i915_gem_object_truncate(obj
);
4255 args
->retained
= obj
->mm
.madv
!= __I915_MADV_PURGED
;
4256 mutex_unlock(&obj
->mm
.lock
);
4259 i915_gem_object_put(obj
);
4264 frontbuffer_retire(struct i915_gem_active
*active
,
4265 struct drm_i915_gem_request
*request
)
4267 struct drm_i915_gem_object
*obj
=
4268 container_of(active
, typeof(*obj
), frontbuffer_write
);
4270 intel_fb_obj_flush(obj
, ORIGIN_CS
);
4273 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4274 const struct drm_i915_gem_object_ops
*ops
)
4276 mutex_init(&obj
->mm
.lock
);
4278 INIT_LIST_HEAD(&obj
->global_link
);
4279 INIT_LIST_HEAD(&obj
->userfault_link
);
4280 INIT_LIST_HEAD(&obj
->vma_list
);
4281 INIT_LIST_HEAD(&obj
->lut_list
);
4282 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4286 reservation_object_init(&obj
->__builtin_resv
);
4287 obj
->resv
= &obj
->__builtin_resv
;
4289 obj
->frontbuffer_ggtt_origin
= ORIGIN_GTT
;
4290 init_request_active(&obj
->frontbuffer_write
, frontbuffer_retire
);
4292 obj
->mm
.madv
= I915_MADV_WILLNEED
;
4293 INIT_RADIX_TREE(&obj
->mm
.get_page
.radix
, GFP_KERNEL
| __GFP_NOWARN
);
4294 mutex_init(&obj
->mm
.get_page
.lock
);
4296 i915_gem_info_add_obj(to_i915(obj
->base
.dev
), obj
->base
.size
);
4299 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4300 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
|
4301 I915_GEM_OBJECT_IS_SHRINKABLE
,
4303 .get_pages
= i915_gem_object_get_pages_gtt
,
4304 .put_pages
= i915_gem_object_put_pages_gtt
,
4306 .pwrite
= i915_gem_object_pwrite_gtt
,
4309 struct drm_i915_gem_object
*
4310 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
)
4312 struct drm_i915_gem_object
*obj
;
4313 struct address_space
*mapping
;
4314 unsigned int cache_level
;
4318 /* There is a prevalence of the assumption that we fit the object's
4319 * page count inside a 32bit _signed_ variable. Let's document this and
4320 * catch if we ever need to fix it. In the meantime, if you do spot
4321 * such a local variable, please consider fixing!
4323 if (size
>> PAGE_SHIFT
> INT_MAX
)
4324 return ERR_PTR(-E2BIG
);
4326 if (overflows_type(size
, obj
->base
.size
))
4327 return ERR_PTR(-E2BIG
);
4329 obj
= i915_gem_object_alloc(dev_priv
);
4331 return ERR_PTR(-ENOMEM
);
4333 ret
= drm_gem_object_init(&dev_priv
->drm
, &obj
->base
, size
);
4337 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4338 if (IS_I965GM(dev_priv
) || IS_I965G(dev_priv
)) {
4339 /* 965gm cannot relocate objects above 4GiB. */
4340 mask
&= ~__GFP_HIGHMEM
;
4341 mask
|= __GFP_DMA32
;
4344 mapping
= obj
->base
.filp
->f_mapping
;
4345 mapping_set_gfp_mask(mapping
, mask
);
4346 GEM_BUG_ON(!(mapping_gfp_mask(mapping
) & __GFP_RECLAIM
));
4348 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4350 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4351 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4353 if (HAS_LLC(dev_priv
))
4354 /* On some devices, we can have the GPU use the LLC (the CPU
4355 * cache) for about a 10% performance improvement
4356 * compared to uncached. Graphics requests other than
4357 * display scanout are coherent with the CPU in
4358 * accessing this cache. This means in this mode we
4359 * don't need to clflush on the CPU side, and on the
4360 * GPU side we only need to flush internal caches to
4361 * get data visible to the CPU.
4363 * However, we maintain the display planes as UC, and so
4364 * need to rebind when first used as such.
4366 cache_level
= I915_CACHE_LLC
;
4368 cache_level
= I915_CACHE_NONE
;
4370 i915_gem_object_set_cache_coherency(obj
, cache_level
);
4372 trace_i915_gem_object_create(obj
);
4377 i915_gem_object_free(obj
);
4378 return ERR_PTR(ret
);
4381 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4383 /* If we are the last user of the backing storage (be it shmemfs
4384 * pages or stolen etc), we know that the pages are going to be
4385 * immediately released. In this case, we can then skip copying
4386 * back the contents from the GPU.
4389 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
4392 if (obj
->base
.filp
== NULL
)
4395 /* At first glance, this looks racy, but then again so would be
4396 * userspace racing mmap against close. However, the first external
4397 * reference to the filp can only be obtained through the
4398 * i915_gem_mmap_ioctl() which safeguards us against the user
4399 * acquiring such a reference whilst we are in the middle of
4400 * freeing the object.
4402 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4405 static void __i915_gem_free_objects(struct drm_i915_private
*i915
,
4406 struct llist_node
*freed
)
4408 struct drm_i915_gem_object
*obj
, *on
;
4410 mutex_lock(&i915
->drm
.struct_mutex
);
4411 intel_runtime_pm_get(i915
);
4412 llist_for_each_entry(obj
, freed
, freed
) {
4413 struct i915_vma
*vma
, *vn
;
4415 trace_i915_gem_object_destroy(obj
);
4417 GEM_BUG_ON(i915_gem_object_is_active(obj
));
4418 list_for_each_entry_safe(vma
, vn
,
4419 &obj
->vma_list
, obj_link
) {
4420 GEM_BUG_ON(i915_vma_is_active(vma
));
4421 vma
->flags
&= ~I915_VMA_PIN_MASK
;
4422 i915_vma_close(vma
);
4424 GEM_BUG_ON(!list_empty(&obj
->vma_list
));
4425 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj
->vma_tree
));
4427 list_del(&obj
->global_link
);
4429 intel_runtime_pm_put(i915
);
4430 mutex_unlock(&i915
->drm
.struct_mutex
);
4434 llist_for_each_entry_safe(obj
, on
, freed
, freed
) {
4435 GEM_BUG_ON(obj
->bind_count
);
4436 GEM_BUG_ON(atomic_read(&obj
->frontbuffer_bits
));
4438 if (obj
->ops
->release
)
4439 obj
->ops
->release(obj
);
4441 if (WARN_ON(i915_gem_object_has_pinned_pages(obj
)))
4442 atomic_set(&obj
->mm
.pages_pin_count
, 0);
4443 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
4444 GEM_BUG_ON(obj
->mm
.pages
);
4446 if (obj
->base
.import_attach
)
4447 drm_prime_gem_destroy(&obj
->base
, NULL
);
4449 reservation_object_fini(&obj
->__builtin_resv
);
4450 drm_gem_object_release(&obj
->base
);
4451 i915_gem_info_remove_obj(i915
, obj
->base
.size
);
4454 i915_gem_object_free(obj
);
4458 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
)
4460 struct llist_node
*freed
;
4462 freed
= llist_del_all(&i915
->mm
.free_list
);
4463 if (unlikely(freed
))
4464 __i915_gem_free_objects(i915
, freed
);
4467 static void __i915_gem_free_work(struct work_struct
*work
)
4469 struct drm_i915_private
*i915
=
4470 container_of(work
, struct drm_i915_private
, mm
.free_work
);
4471 struct llist_node
*freed
;
4473 /* All file-owned VMA should have been released by this point through
4474 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4475 * However, the object may also be bound into the global GTT (e.g.
4476 * older GPUs without per-process support, or for direct access through
4477 * the GTT either for the user or for scanout). Those VMA still need to
4481 while ((freed
= llist_del_all(&i915
->mm
.free_list
))) {
4482 __i915_gem_free_objects(i915
, freed
);
4488 static void __i915_gem_free_object_rcu(struct rcu_head
*head
)
4490 struct drm_i915_gem_object
*obj
=
4491 container_of(head
, typeof(*obj
), rcu
);
4492 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
4494 /* We can't simply use call_rcu() from i915_gem_free_object()
4495 * as we need to block whilst unbinding, and the call_rcu
4496 * task may be called from softirq context. So we take a
4497 * detour through a worker.
4499 if (llist_add(&obj
->freed
, &i915
->mm
.free_list
))
4500 schedule_work(&i915
->mm
.free_work
);
4503 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4505 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4507 if (obj
->mm
.quirked
)
4508 __i915_gem_object_unpin_pages(obj
);
4510 if (discard_backing_storage(obj
))
4511 obj
->mm
.madv
= I915_MADV_DONTNEED
;
4513 /* Before we free the object, make sure any pure RCU-only
4514 * read-side critical sections are complete, e.g.
4515 * i915_gem_busy_ioctl(). For the corresponding synchronized
4516 * lookup see i915_gem_object_lookup_rcu().
4518 call_rcu(&obj
->rcu
, __i915_gem_free_object_rcu
);
4521 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object
*obj
)
4523 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
4525 if (!i915_gem_object_has_active_reference(obj
) &&
4526 i915_gem_object_is_active(obj
))
4527 i915_gem_object_set_active_reference(obj
);
4529 i915_gem_object_put(obj
);
4532 static void assert_kernel_context_is_current(struct drm_i915_private
*dev_priv
)
4534 struct intel_engine_cs
*engine
;
4535 enum intel_engine_id id
;
4537 for_each_engine(engine
, dev_priv
, id
)
4538 GEM_BUG_ON(engine
->last_retired_context
&&
4539 !i915_gem_context_is_kernel(engine
->last_retired_context
));
4542 void i915_gem_sanitize(struct drm_i915_private
*i915
)
4545 * If we inherit context state from the BIOS or earlier occupants
4546 * of the GPU, the GPU may be in an inconsistent state when we
4547 * try to take over. The only way to remove the earlier state
4548 * is by resetting. However, resetting on earlier gen is tricky as
4549 * it may impact the display and we are uncertain about the stability
4550 * of the reset, so this could be applied to even earlier gen.
4552 if (INTEL_GEN(i915
) >= 5) {
4553 int reset
= intel_gpu_reset(i915
, ALL_ENGINES
);
4554 WARN_ON(reset
&& reset
!= -ENODEV
);
4558 int i915_gem_suspend(struct drm_i915_private
*dev_priv
)
4560 struct drm_device
*dev
= &dev_priv
->drm
;
4563 intel_runtime_pm_get(dev_priv
);
4564 intel_suspend_gt_powersave(dev_priv
);
4566 mutex_lock(&dev
->struct_mutex
);
4568 /* We have to flush all the executing contexts to main memory so
4569 * that they can saved in the hibernation image. To ensure the last
4570 * context image is coherent, we have to switch away from it. That
4571 * leaves the dev_priv->kernel_context still active when
4572 * we actually suspend, and its image in memory may not match the GPU
4573 * state. Fortunately, the kernel_context is disposable and we do
4574 * not rely on its state.
4576 ret
= i915_gem_switch_to_kernel_context(dev_priv
);
4580 ret
= i915_gem_wait_for_idle(dev_priv
,
4581 I915_WAIT_INTERRUPTIBLE
|
4586 assert_kernel_context_is_current(dev_priv
);
4587 i915_gem_contexts_lost(dev_priv
);
4588 mutex_unlock(&dev
->struct_mutex
);
4590 intel_guc_suspend(dev_priv
);
4592 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4593 cancel_delayed_work_sync(&dev_priv
->gt
.retire_work
);
4595 /* As the idle_work is rearming if it detects a race, play safe and
4596 * repeat the flush until it is definitely idle.
4598 while (flush_delayed_work(&dev_priv
->gt
.idle_work
))
4601 /* Assert that we sucessfully flushed all the work and
4602 * reset the GPU back to its idle, low power state.
4604 WARN_ON(dev_priv
->gt
.awake
);
4605 WARN_ON(!intel_engines_are_idle(dev_priv
));
4608 * Neither the BIOS, ourselves or any other kernel
4609 * expects the system to be in execlists mode on startup,
4610 * so we need to reset the GPU back to legacy mode. And the only
4611 * known way to disable logical contexts is through a GPU reset.
4613 * So in order to leave the system in a known default configuration,
4614 * always reset the GPU upon unload and suspend. Afterwards we then
4615 * clean up the GEM state tracking, flushing off the requests and
4616 * leaving the system in a known idle state.
4618 * Note that is of the upmost importance that the GPU is idle and
4619 * all stray writes are flushed *before* we dismantle the backing
4620 * storage for the pinned objects.
4622 * However, since we are uncertain that resetting the GPU on older
4623 * machines is a good idea, we don't - just in case it leaves the
4624 * machine in an unusable condition.
4626 i915_gem_sanitize(dev_priv
);
4630 mutex_unlock(&dev
->struct_mutex
);
4632 intel_runtime_pm_put(dev_priv
);
4636 void i915_gem_resume(struct drm_i915_private
*dev_priv
)
4638 struct drm_device
*dev
= &dev_priv
->drm
;
4640 WARN_ON(dev_priv
->gt
.awake
);
4642 mutex_lock(&dev
->struct_mutex
);
4643 i915_gem_restore_gtt_mappings(dev_priv
);
4645 /* As we didn't flush the kernel context before suspend, we cannot
4646 * guarantee that the context image is complete. So let's just reset
4647 * it and start again.
4649 dev_priv
->gt
.resume(dev_priv
);
4651 mutex_unlock(&dev
->struct_mutex
);
4654 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
)
4656 if (INTEL_GEN(dev_priv
) < 5 ||
4657 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4660 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4661 DISP_TILE_SURFACE_SWIZZLING
);
4663 if (IS_GEN5(dev_priv
))
4666 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4667 if (IS_GEN6(dev_priv
))
4668 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4669 else if (IS_GEN7(dev_priv
))
4670 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4671 else if (IS_GEN8(dev_priv
))
4672 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4677 static void init_unused_ring(struct drm_i915_private
*dev_priv
, u32 base
)
4679 I915_WRITE(RING_CTL(base
), 0);
4680 I915_WRITE(RING_HEAD(base
), 0);
4681 I915_WRITE(RING_TAIL(base
), 0);
4682 I915_WRITE(RING_START(base
), 0);
4685 static void init_unused_rings(struct drm_i915_private
*dev_priv
)
4687 if (IS_I830(dev_priv
)) {
4688 init_unused_ring(dev_priv
, PRB1_BASE
);
4689 init_unused_ring(dev_priv
, SRB0_BASE
);
4690 init_unused_ring(dev_priv
, SRB1_BASE
);
4691 init_unused_ring(dev_priv
, SRB2_BASE
);
4692 init_unused_ring(dev_priv
, SRB3_BASE
);
4693 } else if (IS_GEN2(dev_priv
)) {
4694 init_unused_ring(dev_priv
, SRB0_BASE
);
4695 init_unused_ring(dev_priv
, SRB1_BASE
);
4696 } else if (IS_GEN3(dev_priv
)) {
4697 init_unused_ring(dev_priv
, PRB1_BASE
);
4698 init_unused_ring(dev_priv
, PRB2_BASE
);
4702 static int __i915_gem_restart_engines(void *data
)
4704 struct drm_i915_private
*i915
= data
;
4705 struct intel_engine_cs
*engine
;
4706 enum intel_engine_id id
;
4709 for_each_engine(engine
, i915
, id
) {
4710 err
= engine
->init_hw(engine
);
4718 int i915_gem_init_hw(struct drm_i915_private
*dev_priv
)
4722 dev_priv
->gt
.last_init_time
= ktime_get();
4724 /* Double layer security blanket, see i915_gem_init() */
4725 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4727 if (HAS_EDRAM(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
4728 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4730 if (IS_HASWELL(dev_priv
))
4731 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev_priv
) ?
4732 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4734 if (HAS_PCH_NOP(dev_priv
)) {
4735 if (IS_IVYBRIDGE(dev_priv
)) {
4736 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4737 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4738 I915_WRITE(GEN7_MSG_CTL
, temp
);
4739 } else if (INTEL_GEN(dev_priv
) >= 7) {
4740 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4741 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4742 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4746 i915_gem_init_swizzling(dev_priv
);
4749 * At least 830 can leave some of the unused rings
4750 * "active" (ie. head != tail) after resume which
4751 * will prevent c3 entry. Makes sure all unused rings
4754 init_unused_rings(dev_priv
);
4756 BUG_ON(!dev_priv
->kernel_context
);
4758 ret
= i915_ppgtt_init_hw(dev_priv
);
4760 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4764 /* Need to do basic initialisation of all rings first: */
4765 ret
= __i915_gem_restart_engines(dev_priv
);
4769 intel_mocs_init_l3cc_table(dev_priv
);
4771 /* We can't enable contexts until all firmware is loaded */
4772 ret
= intel_uc_init_hw(dev_priv
);
4777 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4781 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
)
4783 if (INTEL_INFO(dev_priv
)->gen
< 6)
4786 /* TODO: make semaphores and Execlists play nicely together */
4787 if (i915
.enable_execlists
)
4793 /* Enable semaphores on SNB when IO remapping is off */
4794 if (IS_GEN6(dev_priv
) && intel_vtd_active())
4800 int i915_gem_init(struct drm_i915_private
*dev_priv
)
4804 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4806 dev_priv
->mm
.unordered_timeline
= dma_fence_context_alloc(1);
4808 if (!i915
.enable_execlists
) {
4809 dev_priv
->gt
.resume
= intel_legacy_submission_resume
;
4810 dev_priv
->gt
.cleanup_engine
= intel_engine_cleanup
;
4812 dev_priv
->gt
.resume
= intel_lr_context_resume
;
4813 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4816 /* This is just a security blanket to placate dragons.
4817 * On some systems, we very sporadically observe that the first TLBs
4818 * used by the CS may be stale, despite us poking the TLB reset. If
4819 * we hold the forcewake during initialisation these problems
4820 * just magically go away.
4822 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4824 ret
= i915_gem_init_userptr(dev_priv
);
4828 ret
= i915_gem_init_ggtt(dev_priv
);
4832 ret
= i915_gem_contexts_init(dev_priv
);
4836 ret
= intel_engines_init(dev_priv
);
4840 ret
= i915_gem_init_hw(dev_priv
);
4842 /* Allow engine initialisation to fail by marking the GPU as
4843 * wedged. But we only want to do this where the GPU is angry,
4844 * for all other failure, such as an allocation failure, bail.
4846 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4847 i915_gem_set_wedged(dev_priv
);
4852 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4853 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4858 void i915_gem_init_mmio(struct drm_i915_private
*i915
)
4860 i915_gem_sanitize(i915
);
4864 i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
)
4866 struct intel_engine_cs
*engine
;
4867 enum intel_engine_id id
;
4869 for_each_engine(engine
, dev_priv
, id
)
4870 dev_priv
->gt
.cleanup_engine(engine
);
4874 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
4878 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
4879 !IS_CHERRYVIEW(dev_priv
))
4880 dev_priv
->num_fence_regs
= 32;
4881 else if (INTEL_INFO(dev_priv
)->gen
>= 4 ||
4882 IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
4883 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
))
4884 dev_priv
->num_fence_regs
= 16;
4886 dev_priv
->num_fence_regs
= 8;
4888 if (intel_vgpu_active(dev_priv
))
4889 dev_priv
->num_fence_regs
=
4890 I915_READ(vgtif_reg(avail_rs
.fence_num
));
4892 /* Initialize fence registers to zero */
4893 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
4894 struct drm_i915_fence_reg
*fence
= &dev_priv
->fence_regs
[i
];
4896 fence
->i915
= dev_priv
;
4898 list_add_tail(&fence
->link
, &dev_priv
->mm
.fence_list
);
4900 i915_gem_restore_fences(dev_priv
);
4902 i915_gem_detect_bit_6_swizzle(dev_priv
);
4906 i915_gem_load_init(struct drm_i915_private
*dev_priv
)
4910 dev_priv
->objects
= KMEM_CACHE(drm_i915_gem_object
, SLAB_HWCACHE_ALIGN
);
4911 if (!dev_priv
->objects
)
4914 dev_priv
->vmas
= KMEM_CACHE(i915_vma
, SLAB_HWCACHE_ALIGN
);
4915 if (!dev_priv
->vmas
)
4918 dev_priv
->luts
= KMEM_CACHE(i915_lut_handle
, 0);
4919 if (!dev_priv
->luts
)
4922 dev_priv
->requests
= KMEM_CACHE(drm_i915_gem_request
,
4923 SLAB_HWCACHE_ALIGN
|
4924 SLAB_RECLAIM_ACCOUNT
|
4925 SLAB_TYPESAFE_BY_RCU
);
4926 if (!dev_priv
->requests
)
4929 dev_priv
->dependencies
= KMEM_CACHE(i915_dependency
,
4930 SLAB_HWCACHE_ALIGN
|
4931 SLAB_RECLAIM_ACCOUNT
);
4932 if (!dev_priv
->dependencies
)
4935 dev_priv
->priorities
= KMEM_CACHE(i915_priolist
, SLAB_HWCACHE_ALIGN
);
4936 if (!dev_priv
->priorities
)
4937 goto err_dependencies
;
4939 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4940 INIT_LIST_HEAD(&dev_priv
->gt
.timelines
);
4941 err
= i915_gem_timeline_init__global(dev_priv
);
4942 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4944 goto err_priorities
;
4946 INIT_WORK(&dev_priv
->mm
.free_work
, __i915_gem_free_work
);
4947 init_llist_head(&dev_priv
->mm
.free_list
);
4948 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4949 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4950 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4951 INIT_LIST_HEAD(&dev_priv
->mm
.userfault_list
);
4952 INIT_DELAYED_WORK(&dev_priv
->gt
.retire_work
,
4953 i915_gem_retire_work_handler
);
4954 INIT_DELAYED_WORK(&dev_priv
->gt
.idle_work
,
4955 i915_gem_idle_work_handler
);
4956 init_waitqueue_head(&dev_priv
->gpu_error
.wait_queue
);
4957 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4959 atomic_set(&dev_priv
->mm
.bsd_engine_dispatch_index
, 0);
4961 spin_lock_init(&dev_priv
->fb_tracking
.lock
);
4966 kmem_cache_destroy(dev_priv
->priorities
);
4968 kmem_cache_destroy(dev_priv
->dependencies
);
4970 kmem_cache_destroy(dev_priv
->requests
);
4972 kmem_cache_destroy(dev_priv
->luts
);
4974 kmem_cache_destroy(dev_priv
->vmas
);
4976 kmem_cache_destroy(dev_priv
->objects
);
4981 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
)
4983 i915_gem_drain_freed_objects(dev_priv
);
4984 WARN_ON(!llist_empty(&dev_priv
->mm
.free_list
));
4985 WARN_ON(dev_priv
->mm
.object_count
);
4987 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4988 i915_gem_timeline_fini(&dev_priv
->gt
.global_timeline
);
4989 WARN_ON(!list_empty(&dev_priv
->gt
.timelines
));
4990 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4992 kmem_cache_destroy(dev_priv
->priorities
);
4993 kmem_cache_destroy(dev_priv
->dependencies
);
4994 kmem_cache_destroy(dev_priv
->requests
);
4995 kmem_cache_destroy(dev_priv
->luts
);
4996 kmem_cache_destroy(dev_priv
->vmas
);
4997 kmem_cache_destroy(dev_priv
->objects
);
4999 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
5003 int i915_gem_freeze(struct drm_i915_private
*dev_priv
)
5005 /* Discard all purgeable objects, let userspace recover those as
5006 * required after resuming.
5008 i915_gem_shrink_all(dev_priv
);
5013 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
5015 struct drm_i915_gem_object
*obj
;
5016 struct list_head
*phases
[] = {
5017 &dev_priv
->mm
.unbound_list
,
5018 &dev_priv
->mm
.bound_list
,
5022 /* Called just before we write the hibernation image.
5024 * We need to update the domain tracking to reflect that the CPU
5025 * will be accessing all the pages to create and restore from the
5026 * hibernation, and so upon restoration those pages will be in the
5029 * To make sure the hibernation image contains the latest state,
5030 * we update that state just before writing out the image.
5032 * To try and reduce the hibernation image, we manually shrink
5033 * the objects as well, see i915_gem_freeze()
5036 i915_gem_shrink(dev_priv
, -1UL, NULL
, I915_SHRINK_UNBOUND
);
5037 i915_gem_drain_freed_objects(dev_priv
);
5039 mutex_lock(&dev_priv
->drm
.struct_mutex
);
5040 for (p
= phases
; *p
; p
++) {
5041 list_for_each_entry(obj
, *p
, global_link
)
5042 __start_cpu_write(obj
);
5044 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
5049 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5051 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5052 struct drm_i915_gem_request
*request
;
5054 /* Clean up our request list when the client is going away, so that
5055 * later retire_requests won't dereference our soon-to-be-gone
5058 spin_lock(&file_priv
->mm
.lock
);
5059 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_link
)
5060 request
->file_priv
= NULL
;
5061 spin_unlock(&file_priv
->mm
.lock
);
5064 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
)
5066 struct drm_i915_file_private
*file_priv
;
5071 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5075 file
->driver_priv
= file_priv
;
5076 file_priv
->dev_priv
= i915
;
5077 file_priv
->file
= file
;
5079 spin_lock_init(&file_priv
->mm
.lock
);
5080 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5082 file_priv
->bsd_engine
= -1;
5084 ret
= i915_gem_context_open(i915
, file
);
5092 * i915_gem_track_fb - update frontbuffer tracking
5093 * @old: current GEM buffer for the frontbuffer slots
5094 * @new: new GEM buffer for the frontbuffer slots
5095 * @frontbuffer_bits: bitmask of frontbuffer slots
5097 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5098 * from @old and setting them in @new. Both @old and @new can be NULL.
5100 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5101 struct drm_i915_gem_object
*new,
5102 unsigned frontbuffer_bits
)
5104 /* Control of individual bits within the mask are guarded by
5105 * the owning plane->mutex, i.e. we can never see concurrent
5106 * manipulation of individual bits. But since the bitfield as a whole
5107 * is updated using RMW, we need to use atomics in order to update
5110 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE
* I915_MAX_PIPES
>
5111 sizeof(atomic_t
) * BITS_PER_BYTE
);
5114 WARN_ON(!(atomic_read(&old
->frontbuffer_bits
) & frontbuffer_bits
));
5115 atomic_andnot(frontbuffer_bits
, &old
->frontbuffer_bits
);
5119 WARN_ON(atomic_read(&new->frontbuffer_bits
) & frontbuffer_bits
);
5120 atomic_or(frontbuffer_bits
, &new->frontbuffer_bits
);
5124 /* Allocate a new GEM object and fill it with the supplied data */
5125 struct drm_i915_gem_object
*
5126 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
5127 const void *data
, size_t size
)
5129 struct drm_i915_gem_object
*obj
;
5134 obj
= i915_gem_object_create(dev_priv
, round_up(size
, PAGE_SIZE
));
5138 GEM_BUG_ON(obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
);
5140 file
= obj
->base
.filp
;
5143 unsigned int len
= min_t(typeof(size
), size
, PAGE_SIZE
);
5145 void *pgdata
, *vaddr
;
5147 err
= pagecache_write_begin(file
, file
->f_mapping
,
5154 memcpy(vaddr
, data
, len
);
5157 err
= pagecache_write_end(file
, file
->f_mapping
,
5171 i915_gem_object_put(obj
);
5172 return ERR_PTR(err
);
5175 struct scatterlist
*
5176 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
5178 unsigned int *offset
)
5180 struct i915_gem_object_page_iter
*iter
= &obj
->mm
.get_page
;
5181 struct scatterlist
*sg
;
5182 unsigned int idx
, count
;
5185 GEM_BUG_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
);
5186 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
5188 /* As we iterate forward through the sg, we record each entry in a
5189 * radixtree for quick repeated (backwards) lookups. If we have seen
5190 * this index previously, we will have an entry for it.
5192 * Initial lookup is O(N), but this is amortized to O(1) for
5193 * sequential page access (where each new request is consecutive
5194 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
5195 * i.e. O(1) with a large constant!
5197 if (n
< READ_ONCE(iter
->sg_idx
))
5200 mutex_lock(&iter
->lock
);
5202 /* We prefer to reuse the last sg so that repeated lookup of this
5203 * (or the subsequent) sg are fast - comparing against the last
5204 * sg is faster than going through the radixtree.
5209 count
= __sg_page_count(sg
);
5211 while (idx
+ count
<= n
) {
5212 unsigned long exception
, i
;
5215 /* If we cannot allocate and insert this entry, or the
5216 * individual pages from this range, cancel updating the
5217 * sg_idx so that on this lookup we are forced to linearly
5218 * scan onwards, but on future lookups we will try the
5219 * insertion again (in which case we need to be careful of
5220 * the error return reporting that we have already inserted
5223 ret
= radix_tree_insert(&iter
->radix
, idx
, sg
);
5224 if (ret
&& ret
!= -EEXIST
)
5228 RADIX_TREE_EXCEPTIONAL_ENTRY
|
5229 idx
<< RADIX_TREE_EXCEPTIONAL_SHIFT
;
5230 for (i
= 1; i
< count
; i
++) {
5231 ret
= radix_tree_insert(&iter
->radix
, idx
+ i
,
5233 if (ret
&& ret
!= -EEXIST
)
5238 sg
= ____sg_next(sg
);
5239 count
= __sg_page_count(sg
);
5246 mutex_unlock(&iter
->lock
);
5248 if (unlikely(n
< idx
)) /* insertion completed by another thread */
5251 /* In case we failed to insert the entry into the radixtree, we need
5252 * to look beyond the current sg.
5254 while (idx
+ count
<= n
) {
5256 sg
= ____sg_next(sg
);
5257 count
= __sg_page_count(sg
);
5266 sg
= radix_tree_lookup(&iter
->radix
, n
);
5269 /* If this index is in the middle of multi-page sg entry,
5270 * the radixtree will contain an exceptional entry that points
5271 * to the start of that range. We will return the pointer to
5272 * the base page and the offset of this page within the
5276 if (unlikely(radix_tree_exception(sg
))) {
5277 unsigned long base
=
5278 (unsigned long)sg
>> RADIX_TREE_EXCEPTIONAL_SHIFT
;
5280 sg
= radix_tree_lookup(&iter
->radix
, base
);
5292 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, unsigned int n
)
5294 struct scatterlist
*sg
;
5295 unsigned int offset
;
5297 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
5299 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
5300 return nth_page(sg_page(sg
), offset
);
5303 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5305 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
5310 page
= i915_gem_object_get_page(obj
, n
);
5312 set_page_dirty(page
);
5318 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
5321 struct scatterlist
*sg
;
5322 unsigned int offset
;
5324 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
5325 return sg_dma_address(sg
) + (offset
<< PAGE_SHIFT
);
5328 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
, int align
)
5330 struct sg_table
*pages
;
5333 if (align
> obj
->base
.size
)
5336 if (obj
->ops
== &i915_gem_phys_ops
)
5339 if (obj
->ops
!= &i915_gem_object_ops
)
5342 err
= i915_gem_object_unbind(obj
);
5346 mutex_lock(&obj
->mm
.lock
);
5348 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
) {
5353 if (obj
->mm
.quirked
) {
5358 if (obj
->mm
.mapping
) {
5363 pages
= obj
->mm
.pages
;
5364 obj
->ops
= &i915_gem_phys_ops
;
5366 err
= ____i915_gem_object_get_pages(obj
);
5370 /* Perma-pin (until release) the physical set of pages */
5371 __i915_gem_object_pin_pages(obj
);
5373 if (!IS_ERR_OR_NULL(pages
))
5374 i915_gem_object_ops
.put_pages(obj
, pages
);
5375 mutex_unlock(&obj
->mm
.lock
);
5379 obj
->ops
= &i915_gem_object_ops
;
5380 obj
->mm
.pages
= pages
;
5382 mutex_unlock(&obj
->mm
.lock
);
5386 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5387 #include "selftests/scatterlist.c"
5388 #include "selftests/mock_gem_device.c"
5389 #include "selftests/huge_gem_object.c"
5390 #include "selftests/i915_gem_object.c"
5391 #include "selftests/i915_gem_coherency.c"