2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_frontbuffer.h"
36 #include "intel_mocs.h"
37 #include <linux/dma-fence-array.h>
38 #include <linux/reservation.h>
39 #include <linux/shmem_fs.h>
40 #include <linux/slab.h>
41 #include <linux/swap.h>
42 #include <linux/pci.h>
43 #include <linux/dma-buf.h>
45 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
);
46 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
47 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
49 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
50 enum i915_cache_level level
)
52 return HAS_LLC(to_i915(dev
)) || level
!= I915_CACHE_NONE
;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
57 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
60 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
63 return obj
->pin_display
;
67 insert_mappable_node(struct i915_ggtt
*ggtt
,
68 struct drm_mm_node
*node
, u32 size
)
70 memset(node
, 0, sizeof(*node
));
71 return drm_mm_insert_node_in_range_generic(&ggtt
->base
.mm
, node
,
73 0, ggtt
->mappable_end
,
74 DRM_MM_SEARCH_DEFAULT
,
75 DRM_MM_CREATE_DEFAULT
);
79 remove_mappable_node(struct drm_mm_node
*node
)
81 drm_mm_remove_node(node
);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
88 spin_lock(&dev_priv
->mm
.object_stat_lock
);
89 dev_priv
->mm
.object_count
++;
90 dev_priv
->mm
.object_memory
+= size
;
91 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
94 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
97 spin_lock(&dev_priv
->mm
.object_stat_lock
);
98 dev_priv
->mm
.object_count
--;
99 dev_priv
->mm
.object_memory
-= size
;
100 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
104 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
110 if (!i915_reset_in_progress(error
))
114 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
115 * userspace. If it takes that long something really bad is going on and
116 * we should simply try to bail out and fail as gracefully as possible.
118 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 !i915_reset_in_progress(error
),
122 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
124 } else if (ret
< 0) {
131 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
136 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
140 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
148 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_private
*dev_priv
= to_i915(dev
);
152 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
153 struct drm_i915_gem_get_aperture
*args
= data
;
154 struct i915_vma
*vma
;
158 mutex_lock(&dev
->struct_mutex
);
159 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
160 if (i915_vma_is_pinned(vma
))
161 pinned
+= vma
->node
.size
;
162 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
163 if (i915_vma_is_pinned(vma
))
164 pinned
+= vma
->node
.size
;
165 mutex_unlock(&dev
->struct_mutex
);
167 args
->aper_size
= ggtt
->base
.total
;
168 args
->aper_available_size
= args
->aper_size
- pinned
;
173 static struct sg_table
*
174 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
176 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
177 drm_dma_handle_t
*phys
;
179 struct scatterlist
*sg
;
183 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 return ERR_PTR(-EINVAL
);
186 /* Always aligning to the object size, allows a single allocation
187 * to handle all possible callers, and given typical object sizes,
188 * the alignment of the buddy allocation will naturally match.
190 phys
= drm_pci_alloc(obj
->base
.dev
,
192 roundup_pow_of_two(obj
->base
.size
));
194 return ERR_PTR(-ENOMEM
);
197 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
201 page
= shmem_read_mapping_page(mapping
, i
);
207 src
= kmap_atomic(page
);
208 memcpy(vaddr
, src
, PAGE_SIZE
);
209 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
216 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
218 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
220 st
= ERR_PTR(-ENOMEM
);
224 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
226 st
= ERR_PTR(-ENOMEM
);
232 sg
->length
= obj
->base
.size
;
234 sg_dma_address(sg
) = phys
->busaddr
;
235 sg_dma_len(sg
) = obj
->base
.size
;
237 obj
->phys_handle
= phys
;
241 drm_pci_free(obj
->base
.dev
, phys
);
246 __i915_gem_object_release_shmem(struct drm_i915_gem_object
*obj
,
247 struct sg_table
*pages
,
250 GEM_BUG_ON(obj
->mm
.madv
== __I915_MADV_PURGED
);
252 if (obj
->mm
.madv
== I915_MADV_DONTNEED
)
253 obj
->mm
.dirty
= false;
256 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0 &&
257 !cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
258 drm_clflush_sg(pages
);
260 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
261 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
265 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
,
266 struct sg_table
*pages
)
268 __i915_gem_object_release_shmem(obj
, pages
, false);
271 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
272 char *vaddr
= obj
->phys_handle
->vaddr
;
275 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
279 page
= shmem_read_mapping_page(mapping
, i
);
283 dst
= kmap_atomic(page
);
284 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
285 memcpy(dst
, vaddr
, PAGE_SIZE
);
288 set_page_dirty(page
);
289 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
290 mark_page_accessed(page
);
294 obj
->mm
.dirty
= false;
297 sg_free_table(pages
);
300 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
304 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
306 i915_gem_object_unpin_pages(obj
);
309 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
310 .get_pages
= i915_gem_object_get_pages_phys
,
311 .put_pages
= i915_gem_object_put_pages_phys
,
312 .release
= i915_gem_object_release_phys
,
315 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
317 struct i915_vma
*vma
;
318 LIST_HEAD(still_in_list
);
321 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret
= i915_gem_object_wait(obj
,
329 I915_WAIT_INTERRUPTIBLE
|
332 MAX_SCHEDULE_TIMEOUT
,
337 i915_gem_retire_requests(to_i915(obj
->base
.dev
));
339 while ((vma
= list_first_entry_or_null(&obj
->vma_list
,
342 list_move_tail(&vma
->obj_link
, &still_in_list
);
343 ret
= i915_vma_unbind(vma
);
347 list_splice(&still_in_list
, &obj
->vma_list
);
353 i915_gem_object_wait_fence(struct dma_fence
*fence
,
356 struct intel_rps_client
*rps
)
358 struct drm_i915_gem_request
*rq
;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE
!= 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &fence
->flags
))
365 if (!dma_fence_is_i915(fence
))
366 return dma_fence_wait_timeout(fence
,
367 flags
& I915_WAIT_INTERRUPTIBLE
,
370 rq
= to_request(fence
);
371 if (i915_gem_request_completed(rq
))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq
->i915
) >= 6)
391 gen6_rps_boost(rq
->i915
, rps
, rq
->emitted_jiffies
);
396 timeout
= i915_wait_request(rq
, flags
, timeout
);
399 if (flags
& I915_WAIT_LOCKED
&& i915_gem_request_completed(rq
))
400 i915_gem_request_retire_upto(rq
);
402 if (rps
&& rq
->global_seqno
== intel_engine_last_submit(rq
->engine
)) {
403 /* The GPU is now idle and this client has stalled.
404 * Since no other client has submitted a request in the
405 * meantime, assume that this client is the only one
406 * supplying work to the GPU but is unable to keep that
407 * work supplied because it is waiting. Since the GPU is
408 * then never kept fully busy, RPS autoclocking will
409 * keep the clocks relatively low, causing further delays.
410 * Compensate by giving the synchronous client credit for
411 * a waitboost next time.
413 spin_lock(&rq
->i915
->rps
.client_lock
);
414 list_del_init(&rps
->link
);
415 spin_unlock(&rq
->i915
->rps
.client_lock
);
422 i915_gem_object_wait_reservation(struct reservation_object
*resv
,
425 struct intel_rps_client
*rps
)
427 struct dma_fence
*excl
;
429 if (flags
& I915_WAIT_ALL
) {
430 struct dma_fence
**shared
;
431 unsigned int count
, i
;
434 ret
= reservation_object_get_fences_rcu(resv
,
435 &excl
, &count
, &shared
);
439 for (i
= 0; i
< count
; i
++) {
440 timeout
= i915_gem_object_wait_fence(shared
[i
],
446 dma_fence_put(shared
[i
]);
449 for (; i
< count
; i
++)
450 dma_fence_put(shared
[i
]);
453 excl
= reservation_object_get_excl_rcu(resv
);
456 if (excl
&& timeout
>= 0)
457 timeout
= i915_gem_object_wait_fence(excl
, flags
, timeout
, rps
);
464 static void __fence_set_priority(struct dma_fence
*fence
, int prio
)
466 struct drm_i915_gem_request
*rq
;
467 struct intel_engine_cs
*engine
;
469 if (!dma_fence_is_i915(fence
))
472 rq
= to_request(fence
);
474 if (!engine
->schedule
)
477 engine
->schedule(rq
, prio
);
480 static void fence_set_priority(struct dma_fence
*fence
, int prio
)
482 /* Recurse once into a fence-array */
483 if (dma_fence_is_array(fence
)) {
484 struct dma_fence_array
*array
= to_dma_fence_array(fence
);
487 for (i
= 0; i
< array
->num_fences
; i
++)
488 __fence_set_priority(array
->fences
[i
], prio
);
490 __fence_set_priority(fence
, prio
);
495 i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
499 struct dma_fence
*excl
;
501 if (flags
& I915_WAIT_ALL
) {
502 struct dma_fence
**shared
;
503 unsigned int count
, i
;
506 ret
= reservation_object_get_fences_rcu(obj
->resv
,
507 &excl
, &count
, &shared
);
511 for (i
= 0; i
< count
; i
++) {
512 fence_set_priority(shared
[i
], prio
);
513 dma_fence_put(shared
[i
]);
518 excl
= reservation_object_get_excl_rcu(obj
->resv
);
522 fence_set_priority(excl
, prio
);
529 * Waits for rendering to the object to be completed
530 * @obj: i915 gem object
531 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
532 * @timeout: how long to wait
533 * @rps: client (user process) to charge for any waitboosting
536 i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
539 struct intel_rps_client
*rps
)
542 #if IS_ENABLED(CONFIG_LOCKDEP)
543 GEM_BUG_ON(debug_locks
&&
544 !!lockdep_is_held(&obj
->base
.dev
->struct_mutex
) !=
545 !!(flags
& I915_WAIT_LOCKED
));
547 GEM_BUG_ON(timeout
< 0);
549 timeout
= i915_gem_object_wait_reservation(obj
->resv
,
552 return timeout
< 0 ? timeout
: 0;
555 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
557 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
563 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
568 if (align
> obj
->base
.size
)
571 if (obj
->ops
== &i915_gem_phys_ops
)
574 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
577 if (obj
->base
.filp
== NULL
)
580 ret
= i915_gem_object_unbind(obj
);
584 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
588 obj
->ops
= &i915_gem_phys_ops
;
590 return i915_gem_object_pin_pages(obj
);
594 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
595 struct drm_i915_gem_pwrite
*args
,
596 struct drm_file
*file
)
598 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
599 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
601 /* We manually control the domain here and pretend that it
602 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
604 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
605 if (copy_from_user(vaddr
, user_data
, args
->size
))
608 drm_clflush_virt_range(vaddr
, args
->size
);
609 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
611 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
615 void *i915_gem_object_alloc(struct drm_device
*dev
)
617 struct drm_i915_private
*dev_priv
= to_i915(dev
);
618 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
621 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
623 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
624 kmem_cache_free(dev_priv
->objects
, obj
);
628 i915_gem_create(struct drm_file
*file
,
629 struct drm_device
*dev
,
633 struct drm_i915_gem_object
*obj
;
637 size
= roundup(size
, PAGE_SIZE
);
641 /* Allocate the new object */
642 obj
= i915_gem_object_create(dev
, size
);
646 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
647 /* drop reference from allocate - handle holds it now */
648 i915_gem_object_put(obj
);
657 i915_gem_dumb_create(struct drm_file
*file
,
658 struct drm_device
*dev
,
659 struct drm_mode_create_dumb
*args
)
661 /* have to work out size/pitch and return them */
662 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
663 args
->size
= args
->pitch
* args
->height
;
664 return i915_gem_create(file
, dev
,
665 args
->size
, &args
->handle
);
669 * Creates a new mm object and returns a handle to it.
670 * @dev: drm device pointer
671 * @data: ioctl data blob
672 * @file: drm file pointer
675 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
676 struct drm_file
*file
)
678 struct drm_i915_gem_create
*args
= data
;
680 i915_gem_flush_free_objects(to_i915(dev
));
682 return i915_gem_create(file
, dev
,
683 args
->size
, &args
->handle
);
687 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
688 const char *gpu_vaddr
, int gpu_offset
,
691 int ret
, cpu_offset
= 0;
694 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
695 int this_length
= min(cacheline_end
- gpu_offset
, length
);
696 int swizzled_gpu_offset
= gpu_offset
^ 64;
698 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
699 gpu_vaddr
+ swizzled_gpu_offset
,
704 cpu_offset
+= this_length
;
705 gpu_offset
+= this_length
;
706 length
-= this_length
;
713 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
714 const char __user
*cpu_vaddr
,
717 int ret
, cpu_offset
= 0;
720 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
721 int this_length
= min(cacheline_end
- gpu_offset
, length
);
722 int swizzled_gpu_offset
= gpu_offset
^ 64;
724 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
725 cpu_vaddr
+ cpu_offset
,
730 cpu_offset
+= this_length
;
731 gpu_offset
+= this_length
;
732 length
-= this_length
;
739 * Pins the specified object's pages and synchronizes the object with
740 * GPU accesses. Sets needs_clflush to non-zero if the caller should
741 * flush the object from the CPU cache.
743 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
744 unsigned int *needs_clflush
)
748 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
751 if (!i915_gem_object_has_struct_page(obj
))
754 ret
= i915_gem_object_wait(obj
,
755 I915_WAIT_INTERRUPTIBLE
|
757 MAX_SCHEDULE_TIMEOUT
,
762 ret
= i915_gem_object_pin_pages(obj
);
766 i915_gem_object_flush_gtt_write_domain(obj
);
768 /* If we're not in the cpu read domain, set ourself into the gtt
769 * read domain and manually flush cachelines (if required). This
770 * optimizes for the case when the gpu will dirty the data
771 * anyway again before the next pread happens.
773 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
774 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
777 if (*needs_clflush
&& !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
778 ret
= i915_gem_object_set_to_cpu_domain(obj
, false);
785 /* return with the pages pinned */
789 i915_gem_object_unpin_pages(obj
);
793 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
794 unsigned int *needs_clflush
)
798 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
801 if (!i915_gem_object_has_struct_page(obj
))
804 ret
= i915_gem_object_wait(obj
,
805 I915_WAIT_INTERRUPTIBLE
|
808 MAX_SCHEDULE_TIMEOUT
,
813 ret
= i915_gem_object_pin_pages(obj
);
817 i915_gem_object_flush_gtt_write_domain(obj
);
819 /* If we're not in the cpu write domain, set ourself into the
820 * gtt write domain and manually flush cachelines (as required).
821 * This optimizes for the case when the gpu will use the data
822 * right away and we therefore have to clflush anyway.
824 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
825 *needs_clflush
|= cpu_write_needs_clflush(obj
) << 1;
827 /* Same trick applies to invalidate partially written cachelines read
830 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
831 *needs_clflush
|= !cpu_cache_is_coherent(obj
->base
.dev
,
834 if (*needs_clflush
&& !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
835 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
842 if ((*needs_clflush
& CLFLUSH_AFTER
) == 0)
843 obj
->cache_dirty
= true;
845 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
846 obj
->mm
.dirty
= true;
847 /* return with the pages pinned */
851 i915_gem_object_unpin_pages(obj
);
856 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
859 if (unlikely(swizzled
)) {
860 unsigned long start
= (unsigned long) addr
;
861 unsigned long end
= (unsigned long) addr
+ length
;
863 /* For swizzling simply ensure that we always flush both
864 * channels. Lame, but simple and it works. Swizzled
865 * pwrite/pread is far from a hotpath - current userspace
866 * doesn't use it at all. */
867 start
= round_down(start
, 128);
868 end
= round_up(end
, 128);
870 drm_clflush_virt_range((void *)start
, end
- start
);
872 drm_clflush_virt_range(addr
, length
);
877 /* Only difference to the fast-path function is that this can handle bit17
878 * and uses non-atomic copy and kmap functions. */
880 shmem_pread_slow(struct page
*page
, int offset
, int length
,
881 char __user
*user_data
,
882 bool page_do_bit17_swizzling
, bool needs_clflush
)
889 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
890 page_do_bit17_swizzling
);
892 if (page_do_bit17_swizzling
)
893 ret
= __copy_to_user_swizzled(user_data
, vaddr
, offset
, length
);
895 ret
= __copy_to_user(user_data
, vaddr
+ offset
, length
);
898 return ret
? - EFAULT
: 0;
902 shmem_pread(struct page
*page
, int offset
, int length
, char __user
*user_data
,
903 bool page_do_bit17_swizzling
, bool needs_clflush
)
908 if (!page_do_bit17_swizzling
) {
909 char *vaddr
= kmap_atomic(page
);
912 drm_clflush_virt_range(vaddr
+ offset
, length
);
913 ret
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
914 kunmap_atomic(vaddr
);
919 return shmem_pread_slow(page
, offset
, length
, user_data
,
920 page_do_bit17_swizzling
, needs_clflush
);
924 i915_gem_shmem_pread(struct drm_i915_gem_object
*obj
,
925 struct drm_i915_gem_pread
*args
)
927 char __user
*user_data
;
929 unsigned int obj_do_bit17_swizzling
;
930 unsigned int needs_clflush
;
931 unsigned int idx
, offset
;
934 obj_do_bit17_swizzling
= 0;
935 if (i915_gem_object_needs_bit17_swizzle(obj
))
936 obj_do_bit17_swizzling
= BIT(17);
938 ret
= mutex_lock_interruptible(&obj
->base
.dev
->struct_mutex
);
942 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
943 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
948 user_data
= u64_to_user_ptr(args
->data_ptr
);
949 offset
= offset_in_page(args
->offset
);
950 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
951 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
955 if (offset
+ length
> PAGE_SIZE
)
956 length
= PAGE_SIZE
- offset
;
958 ret
= shmem_pread(page
, offset
, length
, user_data
,
959 page_to_phys(page
) & obj_do_bit17_swizzling
,
969 i915_gem_obj_finish_shmem_access(obj
);
974 gtt_user_read(struct io_mapping
*mapping
,
975 loff_t base
, int offset
,
976 char __user
*user_data
, int length
)
979 unsigned long unwritten
;
981 /* We can use the cpu mem copy function because this is X86. */
982 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
983 unwritten
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
984 io_mapping_unmap_atomic(vaddr
);
986 vaddr
= (void __force
*)
987 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
988 unwritten
= copy_to_user(user_data
, vaddr
+ offset
, length
);
989 io_mapping_unmap(vaddr
);
995 i915_gem_gtt_pread(struct drm_i915_gem_object
*obj
,
996 const struct drm_i915_gem_pread
*args
)
998 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
999 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1000 struct drm_mm_node node
;
1001 struct i915_vma
*vma
;
1002 void __user
*user_data
;
1006 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1010 intel_runtime_pm_get(i915
);
1011 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1012 PIN_MAPPABLE
| PIN_NONBLOCK
);
1014 node
.start
= i915_ggtt_offset(vma
);
1015 node
.allocated
= false;
1016 ret
= i915_vma_put_fence(vma
);
1018 i915_vma_unpin(vma
);
1023 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1026 GEM_BUG_ON(!node
.allocated
);
1029 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1033 mutex_unlock(&i915
->drm
.struct_mutex
);
1035 user_data
= u64_to_user_ptr(args
->data_ptr
);
1036 remain
= args
->size
;
1037 offset
= args
->offset
;
1039 while (remain
> 0) {
1040 /* Operation in this page
1042 * page_base = page offset within aperture
1043 * page_offset = offset within page
1044 * page_length = bytes to copy for this page
1046 u32 page_base
= node
.start
;
1047 unsigned page_offset
= offset_in_page(offset
);
1048 unsigned page_length
= PAGE_SIZE
- page_offset
;
1049 page_length
= remain
< page_length
? remain
: page_length
;
1050 if (node
.allocated
) {
1052 ggtt
->base
.insert_page(&ggtt
->base
,
1053 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1054 node
.start
, I915_CACHE_NONE
, 0);
1057 page_base
+= offset
& PAGE_MASK
;
1060 if (gtt_user_read(&ggtt
->mappable
, page_base
, page_offset
,
1061 user_data
, page_length
)) {
1066 remain
-= page_length
;
1067 user_data
+= page_length
;
1068 offset
+= page_length
;
1071 mutex_lock(&i915
->drm
.struct_mutex
);
1073 if (node
.allocated
) {
1075 ggtt
->base
.clear_range(&ggtt
->base
,
1076 node
.start
, node
.size
);
1077 remove_mappable_node(&node
);
1079 i915_vma_unpin(vma
);
1082 intel_runtime_pm_put(i915
);
1083 mutex_unlock(&i915
->drm
.struct_mutex
);
1089 * Reads data from the object referenced by handle.
1090 * @dev: drm device pointer
1091 * @data: ioctl data blob
1092 * @file: drm file pointer
1094 * On error, the contents of *data are undefined.
1097 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1098 struct drm_file
*file
)
1100 struct drm_i915_gem_pread
*args
= data
;
1101 struct drm_i915_gem_object
*obj
;
1104 if (args
->size
== 0)
1107 if (!access_ok(VERIFY_WRITE
,
1108 u64_to_user_ptr(args
->data_ptr
),
1112 obj
= i915_gem_object_lookup(file
, args
->handle
);
1116 /* Bounds check source. */
1117 if (args
->offset
> obj
->base
.size
||
1118 args
->size
> obj
->base
.size
- args
->offset
) {
1123 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
1125 ret
= i915_gem_object_wait(obj
,
1126 I915_WAIT_INTERRUPTIBLE
,
1127 MAX_SCHEDULE_TIMEOUT
,
1128 to_rps_client(file
));
1132 ret
= i915_gem_object_pin_pages(obj
);
1136 ret
= i915_gem_shmem_pread(obj
, args
);
1137 if (ret
== -EFAULT
|| ret
== -ENODEV
)
1138 ret
= i915_gem_gtt_pread(obj
, args
);
1140 i915_gem_object_unpin_pages(obj
);
1142 i915_gem_object_put(obj
);
1146 /* This is the fast write path which cannot handle
1147 * page faults in the source data
1151 ggtt_write(struct io_mapping
*mapping
,
1152 loff_t base
, int offset
,
1153 char __user
*user_data
, int length
)
1156 unsigned long unwritten
;
1158 /* We can use the cpu mem copy function because this is X86. */
1159 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
1160 unwritten
= __copy_from_user_inatomic_nocache(vaddr
+ offset
,
1162 io_mapping_unmap_atomic(vaddr
);
1164 vaddr
= (void __force
*)
1165 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1166 unwritten
= copy_from_user(vaddr
+ offset
, user_data
, length
);
1167 io_mapping_unmap(vaddr
);
1174 * This is the fast pwrite path, where we copy the data directly from the
1175 * user into the GTT, uncached.
1176 * @obj: i915 GEM object
1177 * @args: pwrite arguments structure
1180 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object
*obj
,
1181 const struct drm_i915_gem_pwrite
*args
)
1183 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1184 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1185 struct drm_mm_node node
;
1186 struct i915_vma
*vma
;
1188 void __user
*user_data
;
1191 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1195 intel_runtime_pm_get(i915
);
1196 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1197 PIN_MAPPABLE
| PIN_NONBLOCK
);
1199 node
.start
= i915_ggtt_offset(vma
);
1200 node
.allocated
= false;
1201 ret
= i915_vma_put_fence(vma
);
1203 i915_vma_unpin(vma
);
1208 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1211 GEM_BUG_ON(!node
.allocated
);
1214 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1218 mutex_unlock(&i915
->drm
.struct_mutex
);
1220 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1222 user_data
= u64_to_user_ptr(args
->data_ptr
);
1223 offset
= args
->offset
;
1224 remain
= args
->size
;
1226 /* Operation in this page
1228 * page_base = page offset within aperture
1229 * page_offset = offset within page
1230 * page_length = bytes to copy for this page
1232 u32 page_base
= node
.start
;
1233 unsigned int page_offset
= offset_in_page(offset
);
1234 unsigned int page_length
= PAGE_SIZE
- page_offset
;
1235 page_length
= remain
< page_length
? remain
: page_length
;
1236 if (node
.allocated
) {
1237 wmb(); /* flush the write before we modify the GGTT */
1238 ggtt
->base
.insert_page(&ggtt
->base
,
1239 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1240 node
.start
, I915_CACHE_NONE
, 0);
1241 wmb(); /* flush modifications to the GGTT (insert_page) */
1243 page_base
+= offset
& PAGE_MASK
;
1245 /* If we get a fault while copying data, then (presumably) our
1246 * source page isn't available. Return the error and we'll
1247 * retry in the slow path.
1248 * If the object is non-shmem backed, we retry again with the
1249 * path that handles page fault.
1251 if (ggtt_write(&ggtt
->mappable
, page_base
, page_offset
,
1252 user_data
, page_length
)) {
1257 remain
-= page_length
;
1258 user_data
+= page_length
;
1259 offset
+= page_length
;
1261 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1263 mutex_lock(&i915
->drm
.struct_mutex
);
1265 if (node
.allocated
) {
1267 ggtt
->base
.clear_range(&ggtt
->base
,
1268 node
.start
, node
.size
);
1269 remove_mappable_node(&node
);
1271 i915_vma_unpin(vma
);
1274 intel_runtime_pm_put(i915
);
1275 mutex_unlock(&i915
->drm
.struct_mutex
);
1280 shmem_pwrite_slow(struct page
*page
, int offset
, int length
,
1281 char __user
*user_data
,
1282 bool page_do_bit17_swizzling
,
1283 bool needs_clflush_before
,
1284 bool needs_clflush_after
)
1290 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1291 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1292 page_do_bit17_swizzling
);
1293 if (page_do_bit17_swizzling
)
1294 ret
= __copy_from_user_swizzled(vaddr
, offset
, user_data
,
1297 ret
= __copy_from_user(vaddr
+ offset
, user_data
, length
);
1298 if (needs_clflush_after
)
1299 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1300 page_do_bit17_swizzling
);
1303 return ret
? -EFAULT
: 0;
1306 /* Per-page copy function for the shmem pwrite fastpath.
1307 * Flushes invalid cachelines before writing to the target if
1308 * needs_clflush_before is set and flushes out any written cachelines after
1309 * writing if needs_clflush is set.
1312 shmem_pwrite(struct page
*page
, int offset
, int len
, char __user
*user_data
,
1313 bool page_do_bit17_swizzling
,
1314 bool needs_clflush_before
,
1315 bool needs_clflush_after
)
1320 if (!page_do_bit17_swizzling
) {
1321 char *vaddr
= kmap_atomic(page
);
1323 if (needs_clflush_before
)
1324 drm_clflush_virt_range(vaddr
+ offset
, len
);
1325 ret
= __copy_from_user_inatomic(vaddr
+ offset
, user_data
, len
);
1326 if (needs_clflush_after
)
1327 drm_clflush_virt_range(vaddr
+ offset
, len
);
1329 kunmap_atomic(vaddr
);
1334 return shmem_pwrite_slow(page
, offset
, len
, user_data
,
1335 page_do_bit17_swizzling
,
1336 needs_clflush_before
,
1337 needs_clflush_after
);
1341 i915_gem_shmem_pwrite(struct drm_i915_gem_object
*obj
,
1342 const struct drm_i915_gem_pwrite
*args
)
1344 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1345 void __user
*user_data
;
1347 unsigned int obj_do_bit17_swizzling
;
1348 unsigned int partial_cacheline_write
;
1349 unsigned int needs_clflush
;
1350 unsigned int offset
, idx
;
1353 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1357 ret
= i915_gem_obj_prepare_shmem_write(obj
, &needs_clflush
);
1358 mutex_unlock(&i915
->drm
.struct_mutex
);
1362 obj_do_bit17_swizzling
= 0;
1363 if (i915_gem_object_needs_bit17_swizzle(obj
))
1364 obj_do_bit17_swizzling
= BIT(17);
1366 /* If we don't overwrite a cacheline completely we need to be
1367 * careful to have up-to-date data by first clflushing. Don't
1368 * overcomplicate things and flush the entire patch.
1370 partial_cacheline_write
= 0;
1371 if (needs_clflush
& CLFLUSH_BEFORE
)
1372 partial_cacheline_write
= boot_cpu_data
.x86_clflush_size
- 1;
1374 user_data
= u64_to_user_ptr(args
->data_ptr
);
1375 remain
= args
->size
;
1376 offset
= offset_in_page(args
->offset
);
1377 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
1378 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
1382 if (offset
+ length
> PAGE_SIZE
)
1383 length
= PAGE_SIZE
- offset
;
1385 ret
= shmem_pwrite(page
, offset
, length
, user_data
,
1386 page_to_phys(page
) & obj_do_bit17_swizzling
,
1387 (offset
| length
) & partial_cacheline_write
,
1388 needs_clflush
& CLFLUSH_AFTER
);
1393 user_data
+= length
;
1397 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1398 i915_gem_obj_finish_shmem_access(obj
);
1403 * Writes data to the object referenced by handle.
1405 * @data: ioctl data blob
1408 * On error, the contents of the buffer that were to be modified are undefined.
1411 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1412 struct drm_file
*file
)
1414 struct drm_i915_gem_pwrite
*args
= data
;
1415 struct drm_i915_gem_object
*obj
;
1418 if (args
->size
== 0)
1421 if (!access_ok(VERIFY_READ
,
1422 u64_to_user_ptr(args
->data_ptr
),
1426 obj
= i915_gem_object_lookup(file
, args
->handle
);
1430 /* Bounds check destination. */
1431 if (args
->offset
> obj
->base
.size
||
1432 args
->size
> obj
->base
.size
- args
->offset
) {
1437 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1439 ret
= i915_gem_object_wait(obj
,
1440 I915_WAIT_INTERRUPTIBLE
|
1442 MAX_SCHEDULE_TIMEOUT
,
1443 to_rps_client(file
));
1447 ret
= i915_gem_object_pin_pages(obj
);
1452 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1453 * it would end up going through the fenced access, and we'll get
1454 * different detiling behavior between reading and writing.
1455 * pread/pwrite currently are reading and writing from the CPU
1456 * perspective, requiring manual detiling by the client.
1458 if (!i915_gem_object_has_struct_page(obj
) ||
1459 cpu_write_needs_clflush(obj
))
1460 /* Note that the gtt paths might fail with non-page-backed user
1461 * pointers (e.g. gtt mappings when moving data between
1462 * textures). Fallback to the shmem path in that case.
1464 ret
= i915_gem_gtt_pwrite_fast(obj
, args
);
1466 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1467 if (obj
->phys_handle
)
1468 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1470 ret
= i915_gem_shmem_pwrite(obj
, args
);
1473 i915_gem_object_unpin_pages(obj
);
1475 i915_gem_object_put(obj
);
1479 static inline enum fb_op_origin
1480 write_origin(struct drm_i915_gem_object
*obj
, unsigned domain
)
1482 return (domain
== I915_GEM_DOMAIN_GTT
?
1483 obj
->frontbuffer_ggtt_origin
: ORIGIN_CPU
);
1486 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object
*obj
)
1488 struct drm_i915_private
*i915
;
1489 struct list_head
*list
;
1490 struct i915_vma
*vma
;
1492 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
1493 if (!i915_vma_is_ggtt(vma
))
1496 if (i915_vma_is_active(vma
))
1499 if (!drm_mm_node_allocated(&vma
->node
))
1502 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
1505 i915
= to_i915(obj
->base
.dev
);
1506 list
= obj
->bind_count
? &i915
->mm
.bound_list
: &i915
->mm
.unbound_list
;
1507 list_move_tail(&obj
->global_link
, list
);
1511 * Called when user space prepares to use an object with the CPU, either
1512 * through the mmap ioctl's mapping or a GTT mapping.
1514 * @data: ioctl data blob
1518 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1519 struct drm_file
*file
)
1521 struct drm_i915_gem_set_domain
*args
= data
;
1522 struct drm_i915_gem_object
*obj
;
1523 uint32_t read_domains
= args
->read_domains
;
1524 uint32_t write_domain
= args
->write_domain
;
1527 /* Only handle setting domains to types used by the CPU. */
1528 if ((write_domain
| read_domains
) & I915_GEM_GPU_DOMAINS
)
1531 /* Having something in the write domain implies it's in the read
1532 * domain, and only that read domain. Enforce that in the request.
1534 if (write_domain
!= 0 && read_domains
!= write_domain
)
1537 obj
= i915_gem_object_lookup(file
, args
->handle
);
1541 /* Try to flush the object off the GPU without holding the lock.
1542 * We will repeat the flush holding the lock in the normal manner
1543 * to catch cases where we are gazumped.
1545 err
= i915_gem_object_wait(obj
,
1546 I915_WAIT_INTERRUPTIBLE
|
1547 (write_domain
? I915_WAIT_ALL
: 0),
1548 MAX_SCHEDULE_TIMEOUT
,
1549 to_rps_client(file
));
1553 /* Flush and acquire obj->pages so that we are coherent through
1554 * direct access in memory with previous cached writes through
1555 * shmemfs and that our cache domain tracking remains valid.
1556 * For example, if the obj->filp was moved to swap without us
1557 * being notified and releasing the pages, we would mistakenly
1558 * continue to assume that the obj remained out of the CPU cached
1561 err
= i915_gem_object_pin_pages(obj
);
1565 err
= i915_mutex_lock_interruptible(dev
);
1569 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1570 err
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1572 err
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1574 /* And bump the LRU for this access */
1575 i915_gem_object_bump_inactive_ggtt(obj
);
1577 mutex_unlock(&dev
->struct_mutex
);
1579 if (write_domain
!= 0)
1580 intel_fb_obj_invalidate(obj
, write_origin(obj
, write_domain
));
1583 i915_gem_object_unpin_pages(obj
);
1585 i915_gem_object_put(obj
);
1590 * Called when user space has done writes to this buffer
1592 * @data: ioctl data blob
1596 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1597 struct drm_file
*file
)
1599 struct drm_i915_gem_sw_finish
*args
= data
;
1600 struct drm_i915_gem_object
*obj
;
1603 obj
= i915_gem_object_lookup(file
, args
->handle
);
1607 /* Pinned buffers may be scanout, so flush the cache */
1608 if (READ_ONCE(obj
->pin_display
)) {
1609 err
= i915_mutex_lock_interruptible(dev
);
1611 i915_gem_object_flush_cpu_write_domain(obj
);
1612 mutex_unlock(&dev
->struct_mutex
);
1616 i915_gem_object_put(obj
);
1621 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1624 * @data: ioctl data blob
1627 * While the mapping holds a reference on the contents of the object, it doesn't
1628 * imply a ref on the object itself.
1632 * DRM driver writers who look a this function as an example for how to do GEM
1633 * mmap support, please don't implement mmap support like here. The modern way
1634 * to implement DRM mmap support is with an mmap offset ioctl (like
1635 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1636 * That way debug tooling like valgrind will understand what's going on, hiding
1637 * the mmap call in a driver private ioctl will break that. The i915 driver only
1638 * does cpu mmaps this way because we didn't know better.
1641 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1642 struct drm_file
*file
)
1644 struct drm_i915_gem_mmap
*args
= data
;
1645 struct drm_i915_gem_object
*obj
;
1648 if (args
->flags
& ~(I915_MMAP_WC
))
1651 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1654 obj
= i915_gem_object_lookup(file
, args
->handle
);
1658 /* prime objects have no backing filp to GEM mmap
1661 if (!obj
->base
.filp
) {
1662 i915_gem_object_put(obj
);
1666 addr
= vm_mmap(obj
->base
.filp
, 0, args
->size
,
1667 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1669 if (args
->flags
& I915_MMAP_WC
) {
1670 struct mm_struct
*mm
= current
->mm
;
1671 struct vm_area_struct
*vma
;
1673 if (down_write_killable(&mm
->mmap_sem
)) {
1674 i915_gem_object_put(obj
);
1677 vma
= find_vma(mm
, addr
);
1680 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1683 up_write(&mm
->mmap_sem
);
1685 /* This may race, but that's ok, it only gets set */
1686 WRITE_ONCE(obj
->frontbuffer_ggtt_origin
, ORIGIN_CPU
);
1688 i915_gem_object_put(obj
);
1689 if (IS_ERR((void *)addr
))
1692 args
->addr_ptr
= (uint64_t) addr
;
1697 static unsigned int tile_row_pages(struct drm_i915_gem_object
*obj
)
1701 size
= i915_gem_object_get_stride(obj
);
1702 size
*= i915_gem_object_get_tiling(obj
) == I915_TILING_Y
? 32 : 8;
1704 return size
>> PAGE_SHIFT
;
1708 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1710 * A history of the GTT mmap interface:
1712 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1713 * aligned and suitable for fencing, and still fit into the available
1714 * mappable space left by the pinned display objects. A classic problem
1715 * we called the page-fault-of-doom where we would ping-pong between
1716 * two objects that could not fit inside the GTT and so the memcpy
1717 * would page one object in at the expense of the other between every
1720 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1721 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1722 * object is too large for the available space (or simply too large
1723 * for the mappable aperture!), a view is created instead and faulted
1724 * into userspace. (This view is aligned and sized appropriately for
1729 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1730 * hangs on some architectures, corruption on others. An attempt to service
1731 * a GTT page fault from a snoopable object will generate a SIGBUS.
1733 * * the object must be able to fit into RAM (physical memory, though no
1734 * limited to the mappable aperture).
1739 * * a new GTT page fault will synchronize rendering from the GPU and flush
1740 * all data to system memory. Subsequent access will not be synchronized.
1742 * * all mappings are revoked on runtime device suspend.
1744 * * there are only 8, 16 or 32 fence registers to share between all users
1745 * (older machines require fence register for display and blitter access
1746 * as well). Contention of the fence registers will cause the previous users
1747 * to be unmapped and any new access will generate new page faults.
1749 * * running out of memory while servicing a fault may generate a SIGBUS,
1750 * rather than the expected SIGSEGV.
1752 int i915_gem_mmap_gtt_version(void)
1758 * i915_gem_fault - fault a page into the GTT
1759 * @area: CPU VMA in question
1762 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1763 * from userspace. The fault handler takes care of binding the object to
1764 * the GTT (if needed), allocating and programming a fence register (again,
1765 * only if needed based on whether the old reg is still valid or the object
1766 * is tiled) and inserting a new PTE into the faulting process.
1768 * Note that the faulting process may involve evicting existing objects
1769 * from the GTT and/or fence registers to make room. So performance may
1770 * suffer if the GTT working set is large or there are few fence registers
1773 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1774 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1776 int i915_gem_fault(struct vm_area_struct
*area
, struct vm_fault
*vmf
)
1778 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1779 struct drm_i915_gem_object
*obj
= to_intel_bo(area
->vm_private_data
);
1780 struct drm_device
*dev
= obj
->base
.dev
;
1781 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1782 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1783 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1784 struct i915_vma
*vma
;
1785 pgoff_t page_offset
;
1789 /* We don't use vmf->pgoff since that has the fake offset */
1790 page_offset
= (vmf
->address
- area
->vm_start
) >> PAGE_SHIFT
;
1792 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1794 /* Try to flush the object off the GPU first without holding the lock.
1795 * Upon acquiring the lock, we will perform our sanity checks and then
1796 * repeat the flush holding the lock in the normal manner to catch cases
1797 * where we are gazumped.
1799 ret
= i915_gem_object_wait(obj
,
1800 I915_WAIT_INTERRUPTIBLE
,
1801 MAX_SCHEDULE_TIMEOUT
,
1806 ret
= i915_gem_object_pin_pages(obj
);
1810 intel_runtime_pm_get(dev_priv
);
1812 ret
= i915_mutex_lock_interruptible(dev
);
1816 /* Access to snoopable pages through the GTT is incoherent. */
1817 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev_priv
)) {
1822 /* If the object is smaller than a couple of partial vma, it is
1823 * not worth only creating a single partial vma - we may as well
1824 * clear enough space for the full object.
1826 flags
= PIN_MAPPABLE
;
1827 if (obj
->base
.size
> 2 * MIN_CHUNK_PAGES
<< PAGE_SHIFT
)
1828 flags
|= PIN_NONBLOCK
| PIN_NONFAULT
;
1830 /* Now pin it into the GTT as needed */
1831 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, flags
);
1833 struct i915_ggtt_view view
;
1834 unsigned int chunk_size
;
1836 /* Use a partial view if it is bigger than available space */
1837 chunk_size
= MIN_CHUNK_PAGES
;
1838 if (i915_gem_object_is_tiled(obj
))
1839 chunk_size
= roundup(chunk_size
, tile_row_pages(obj
));
1841 memset(&view
, 0, sizeof(view
));
1842 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1843 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1844 view
.params
.partial
.size
=
1845 min_t(unsigned int, chunk_size
,
1846 vma_pages(area
) - view
.params
.partial
.offset
);
1848 /* If the partial covers the entire object, just create a
1851 if (chunk_size
>= obj
->base
.size
>> PAGE_SHIFT
)
1852 view
.type
= I915_GGTT_VIEW_NORMAL
;
1854 /* Userspace is now writing through an untracked VMA, abandon
1855 * all hope that the hardware is able to track future writes.
1857 obj
->frontbuffer_ggtt_origin
= ORIGIN_CPU
;
1859 vma
= i915_gem_object_ggtt_pin(obj
, &view
, 0, 0, PIN_MAPPABLE
);
1866 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1870 ret
= i915_vma_get_fence(vma
);
1874 /* Mark as being mmapped into userspace for later revocation */
1875 assert_rpm_wakelock_held(dev_priv
);
1876 if (list_empty(&obj
->userfault_link
))
1877 list_add(&obj
->userfault_link
, &dev_priv
->mm
.userfault_list
);
1879 /* Finally, remap it using the new GTT offset */
1880 ret
= remap_io_mapping(area
,
1881 area
->vm_start
+ (vma
->ggtt_view
.params
.partial
.offset
<< PAGE_SHIFT
),
1882 (ggtt
->mappable_base
+ vma
->node
.start
) >> PAGE_SHIFT
,
1883 min_t(u64
, vma
->size
, area
->vm_end
- area
->vm_start
),
1887 __i915_vma_unpin(vma
);
1889 mutex_unlock(&dev
->struct_mutex
);
1891 intel_runtime_pm_put(dev_priv
);
1892 i915_gem_object_unpin_pages(obj
);
1897 * We eat errors when the gpu is terminally wedged to avoid
1898 * userspace unduly crashing (gl has no provisions for mmaps to
1899 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1900 * and so needs to be reported.
1902 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1903 ret
= VM_FAULT_SIGBUS
;
1908 * EAGAIN means the gpu is hung and we'll wait for the error
1909 * handler to reset everything when re-faulting in
1910 * i915_mutex_lock_interruptible.
1917 * EBUSY is ok: this just means that another thread
1918 * already did the job.
1920 ret
= VM_FAULT_NOPAGE
;
1927 ret
= VM_FAULT_SIGBUS
;
1930 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1931 ret
= VM_FAULT_SIGBUS
;
1938 * i915_gem_release_mmap - remove physical page mappings
1939 * @obj: obj in question
1941 * Preserve the reservation of the mmapping with the DRM core code, but
1942 * relinquish ownership of the pages back to the system.
1944 * It is vital that we remove the page mapping if we have mapped a tiled
1945 * object through the GTT and then lose the fence register due to
1946 * resource pressure. Similarly if the object has been moved out of the
1947 * aperture, than pages mapped into userspace must be revoked. Removing the
1948 * mapping will then trigger a page fault on the next user access, allowing
1949 * fixup by i915_gem_fault().
1952 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1954 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1956 /* Serialisation between user GTT access and our code depends upon
1957 * revoking the CPU's PTE whilst the mutex is held. The next user
1958 * pagefault then has to wait until we release the mutex.
1960 * Note that RPM complicates somewhat by adding an additional
1961 * requirement that operations to the GGTT be made holding the RPM
1964 lockdep_assert_held(&i915
->drm
.struct_mutex
);
1965 intel_runtime_pm_get(i915
);
1967 if (list_empty(&obj
->userfault_link
))
1970 list_del_init(&obj
->userfault_link
);
1971 drm_vma_node_unmap(&obj
->base
.vma_node
,
1972 obj
->base
.dev
->anon_inode
->i_mapping
);
1974 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1975 * memory transactions from userspace before we return. The TLB
1976 * flushing implied above by changing the PTE above *should* be
1977 * sufficient, an extra barrier here just provides us with a bit
1978 * of paranoid documentation about our requirement to serialise
1979 * memory writes before touching registers / GSM.
1984 intel_runtime_pm_put(i915
);
1987 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
)
1989 struct drm_i915_gem_object
*obj
, *on
;
1993 * Only called during RPM suspend. All users of the userfault_list
1994 * must be holding an RPM wakeref to ensure that this can not
1995 * run concurrently with themselves (and use the struct_mutex for
1996 * protection between themselves).
1999 list_for_each_entry_safe(obj
, on
,
2000 &dev_priv
->mm
.userfault_list
, userfault_link
) {
2001 list_del_init(&obj
->userfault_link
);
2002 drm_vma_node_unmap(&obj
->base
.vma_node
,
2003 obj
->base
.dev
->anon_inode
->i_mapping
);
2006 /* The fence will be lost when the device powers down. If any were
2007 * in use by hardware (i.e. they are pinned), we should not be powering
2008 * down! All other fences will be reacquired by the user upon waking.
2010 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2011 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2013 /* Ideally we want to assert that the fence register is not
2014 * live at this point (i.e. that no piece of code will be
2015 * trying to write through fence + GTT, as that both violates
2016 * our tracking of activity and associated locking/barriers,
2017 * but also is illegal given that the hw is powered down).
2019 * Previously we used reg->pin_count as a "liveness" indicator.
2020 * That is not sufficient, and we need a more fine-grained
2021 * tool if we want to have a sanity check here.
2027 GEM_BUG_ON(!list_empty(®
->vma
->obj
->userfault_link
));
2033 * i915_gem_get_ggtt_size - return required global GTT size for an object
2034 * @dev_priv: i915 device
2035 * @size: object size
2036 * @tiling_mode: tiling mode
2038 * Return the required global GTT size for an object, taking into account
2039 * potential fence register mapping.
2041 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
,
2042 u64 size
, int tiling_mode
)
2046 GEM_BUG_ON(size
== 0);
2048 if (INTEL_GEN(dev_priv
) >= 4 ||
2049 tiling_mode
== I915_TILING_NONE
)
2052 /* Previous chips need a power-of-two fence region when tiling */
2053 if (IS_GEN3(dev_priv
))
2054 ggtt_size
= 1024*1024;
2056 ggtt_size
= 512*1024;
2058 while (ggtt_size
< size
)
2065 * i915_gem_get_ggtt_alignment - return required global GTT alignment
2066 * @dev_priv: i915 device
2067 * @size: object size
2068 * @tiling_mode: tiling mode
2069 * @fenced: is fenced alignment required or not
2071 * Return the required global GTT alignment for an object, taking into account
2072 * potential fence register mapping.
2074 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
2075 int tiling_mode
, bool fenced
)
2077 GEM_BUG_ON(size
== 0);
2080 * Minimum alignment is 4k (GTT page size), but might be greater
2081 * if a fence register is needed for the object.
2083 if (INTEL_GEN(dev_priv
) >= 4 || (!fenced
&& IS_G33(dev_priv
)) ||
2084 tiling_mode
== I915_TILING_NONE
)
2088 * Previous chips need to be aligned to the size of the smallest
2089 * fence register that can contain the object.
2091 return i915_gem_get_ggtt_size(dev_priv
, size
, tiling_mode
);
2094 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2096 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2099 err
= drm_gem_create_mmap_offset(&obj
->base
);
2103 /* We can idle the GPU locklessly to flush stale objects, but in order
2104 * to claim that space for ourselves, we need to take the big
2105 * struct_mutex to free the requests+objects and allocate our slot.
2107 err
= i915_gem_wait_for_idle(dev_priv
, I915_WAIT_INTERRUPTIBLE
);
2111 err
= i915_mutex_lock_interruptible(&dev_priv
->drm
);
2113 i915_gem_retire_requests(dev_priv
);
2114 err
= drm_gem_create_mmap_offset(&obj
->base
);
2115 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2121 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2123 drm_gem_free_mmap_offset(&obj
->base
);
2127 i915_gem_mmap_gtt(struct drm_file
*file
,
2128 struct drm_device
*dev
,
2132 struct drm_i915_gem_object
*obj
;
2135 obj
= i915_gem_object_lookup(file
, handle
);
2139 ret
= i915_gem_object_create_mmap_offset(obj
);
2141 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2143 i915_gem_object_put(obj
);
2148 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2150 * @data: GTT mapping ioctl data
2151 * @file: GEM object info
2153 * Simply returns the fake offset to userspace so it can mmap it.
2154 * The mmap call will end up in drm_gem_mmap(), which will set things
2155 * up so we can get faults in the handler above.
2157 * The fault handler will take care of binding the object into the GTT
2158 * (since it may have been evicted to make room for something), allocating
2159 * a fence register, and mapping the appropriate aperture address into
2163 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2164 struct drm_file
*file
)
2166 struct drm_i915_gem_mmap_gtt
*args
= data
;
2168 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2171 /* Immediately discard the backing storage */
2173 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2175 i915_gem_object_free_mmap_offset(obj
);
2177 if (obj
->base
.filp
== NULL
)
2180 /* Our goal here is to return as much of the memory as
2181 * is possible back to the system as we are called from OOM.
2182 * To do this we must instruct the shmfs to drop all of its
2183 * backing pages, *now*.
2185 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2186 obj
->mm
.madv
= __I915_MADV_PURGED
;
2187 obj
->mm
.pages
= ERR_PTR(-EFAULT
);
2190 /* Try to discard unwanted pages */
2191 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2193 struct address_space
*mapping
;
2195 lockdep_assert_held(&obj
->mm
.lock
);
2196 GEM_BUG_ON(obj
->mm
.pages
);
2198 switch (obj
->mm
.madv
) {
2199 case I915_MADV_DONTNEED
:
2200 i915_gem_object_truncate(obj
);
2201 case __I915_MADV_PURGED
:
2205 if (obj
->base
.filp
== NULL
)
2208 mapping
= obj
->base
.filp
->f_mapping
,
2209 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2213 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
,
2214 struct sg_table
*pages
)
2216 struct sgt_iter sgt_iter
;
2219 __i915_gem_object_release_shmem(obj
, pages
, true);
2221 i915_gem_gtt_finish_pages(obj
, pages
);
2223 if (i915_gem_object_needs_bit17_swizzle(obj
))
2224 i915_gem_object_save_bit_17_swizzle(obj
, pages
);
2226 for_each_sgt_page(page
, sgt_iter
, pages
) {
2228 set_page_dirty(page
);
2230 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
2231 mark_page_accessed(page
);
2235 obj
->mm
.dirty
= false;
2237 sg_free_table(pages
);
2241 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object
*obj
)
2243 struct radix_tree_iter iter
;
2246 radix_tree_for_each_slot(slot
, &obj
->mm
.get_page
.radix
, &iter
, 0)
2247 radix_tree_delete(&obj
->mm
.get_page
.radix
, iter
.index
);
2250 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
2251 enum i915_mm_subclass subclass
)
2253 struct sg_table
*pages
;
2255 if (i915_gem_object_has_pinned_pages(obj
))
2258 GEM_BUG_ON(obj
->bind_count
);
2259 if (!READ_ONCE(obj
->mm
.pages
))
2262 /* May be called by shrinker from within get_pages() (on another bo) */
2263 mutex_lock_nested(&obj
->mm
.lock
, subclass
);
2264 if (unlikely(atomic_read(&obj
->mm
.pages_pin_count
)))
2267 /* ->put_pages might need to allocate memory for the bit17 swizzle
2268 * array, hence protect them from being reaped by removing them from gtt
2270 pages
= fetch_and_zero(&obj
->mm
.pages
);
2273 if (obj
->mm
.mapping
) {
2276 ptr
= ptr_mask_bits(obj
->mm
.mapping
);
2277 if (is_vmalloc_addr(ptr
))
2280 kunmap(kmap_to_page(ptr
));
2282 obj
->mm
.mapping
= NULL
;
2285 __i915_gem_object_reset_page_iter(obj
);
2288 obj
->ops
->put_pages(obj
, pages
);
2291 mutex_unlock(&obj
->mm
.lock
);
2294 static void i915_sg_trim(struct sg_table
*orig_st
)
2296 struct sg_table new_st
;
2297 struct scatterlist
*sg
, *new_sg
;
2300 if (orig_st
->nents
== orig_st
->orig_nents
)
2303 if (sg_alloc_table(&new_st
, orig_st
->nents
, GFP_KERNEL
| __GFP_NOWARN
))
2306 new_sg
= new_st
.sgl
;
2307 for_each_sg(orig_st
->sgl
, sg
, orig_st
->nents
, i
) {
2308 sg_set_page(new_sg
, sg_page(sg
), sg
->length
, 0);
2309 /* called before being DMA mapped, no need to copy sg->dma_* */
2310 new_sg
= sg_next(new_sg
);
2313 sg_free_table(orig_st
);
2318 static struct sg_table
*
2319 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2321 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2322 const unsigned long page_count
= obj
->base
.size
/ PAGE_SIZE
;
2324 struct address_space
*mapping
;
2325 struct sg_table
*st
;
2326 struct scatterlist
*sg
;
2327 struct sgt_iter sgt_iter
;
2329 unsigned long last_pfn
= 0; /* suppress gcc warning */
2330 unsigned int max_segment
;
2334 /* Assert that the object is not currently in any GPU domain. As it
2335 * wasn't in the GTT, there shouldn't be any way it could have been in
2338 GEM_BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2339 GEM_BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2341 max_segment
= swiotlb_max_segment();
2343 max_segment
= rounddown(UINT_MAX
, PAGE_SIZE
);
2345 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2347 return ERR_PTR(-ENOMEM
);
2350 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2352 return ERR_PTR(-ENOMEM
);
2355 /* Get the list of pages out of our struct file. They'll be pinned
2356 * at this point until we release them.
2358 * Fail silently without starting the shrinker
2360 mapping
= obj
->base
.filp
->f_mapping
;
2361 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2362 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2365 for (i
= 0; i
< page_count
; i
++) {
2366 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2368 i915_gem_shrink(dev_priv
,
2371 I915_SHRINK_UNBOUND
|
2372 I915_SHRINK_PURGEABLE
);
2373 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2376 /* We've tried hard to allocate the memory by reaping
2377 * our own buffer, now let the real VM do its job and
2378 * go down in flames if truly OOM.
2380 page
= shmem_read_mapping_page(mapping
, i
);
2382 ret
= PTR_ERR(page
);
2387 sg
->length
>= max_segment
||
2388 page_to_pfn(page
) != last_pfn
+ 1) {
2392 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2394 sg
->length
+= PAGE_SIZE
;
2396 last_pfn
= page_to_pfn(page
);
2398 /* Check that the i965g/gm workaround works. */
2399 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2401 if (sg
) /* loop terminated early; short sg table */
2404 /* Trim unused sg entries to avoid wasting memory. */
2407 ret
= i915_gem_gtt_prepare_pages(obj
, st
);
2409 /* DMA remapping failed? One possible cause is that
2410 * it could not reserve enough large entries, asking
2411 * for PAGE_SIZE chunks instead may be helpful.
2413 if (max_segment
> PAGE_SIZE
) {
2414 for_each_sgt_page(page
, sgt_iter
, st
)
2418 max_segment
= PAGE_SIZE
;
2421 dev_warn(&dev_priv
->drm
.pdev
->dev
,
2422 "Failed to DMA remap %lu pages\n",
2428 if (i915_gem_object_needs_bit17_swizzle(obj
))
2429 i915_gem_object_do_bit_17_swizzle(obj
, st
);
2436 for_each_sgt_page(page
, sgt_iter
, st
)
2441 /* shmemfs first checks if there is enough memory to allocate the page
2442 * and reports ENOSPC should there be insufficient, along with the usual
2443 * ENOMEM for a genuine allocation failure.
2445 * We use ENOSPC in our driver to mean that we have run out of aperture
2446 * space and so want to translate the error from shmemfs back to our
2447 * usual understanding of ENOMEM.
2452 return ERR_PTR(ret
);
2455 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2456 struct sg_table
*pages
)
2458 lockdep_assert_held(&obj
->mm
.lock
);
2460 obj
->mm
.get_page
.sg_pos
= pages
->sgl
;
2461 obj
->mm
.get_page
.sg_idx
= 0;
2463 obj
->mm
.pages
= pages
;
2465 if (i915_gem_object_is_tiled(obj
) &&
2466 to_i915(obj
->base
.dev
)->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
2467 GEM_BUG_ON(obj
->mm
.quirked
);
2468 __i915_gem_object_pin_pages(obj
);
2469 obj
->mm
.quirked
= true;
2473 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2475 struct sg_table
*pages
;
2477 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj
));
2479 if (unlikely(obj
->mm
.madv
!= I915_MADV_WILLNEED
)) {
2480 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2484 pages
= obj
->ops
->get_pages(obj
);
2485 if (unlikely(IS_ERR(pages
)))
2486 return PTR_ERR(pages
);
2488 __i915_gem_object_set_pages(obj
, pages
);
2492 /* Ensure that the associated pages are gathered from the backing storage
2493 * and pinned into our object. i915_gem_object_pin_pages() may be called
2494 * multiple times before they are released by a single call to
2495 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2496 * either as a result of memory pressure (reaping pages under the shrinker)
2497 * or as the object is itself released.
2499 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2503 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
2507 if (unlikely(IS_ERR_OR_NULL(obj
->mm
.pages
))) {
2508 err
= ____i915_gem_object_get_pages(obj
);
2512 smp_mb__before_atomic();
2514 atomic_inc(&obj
->mm
.pages_pin_count
);
2517 mutex_unlock(&obj
->mm
.lock
);
2521 /* The 'mapping' part of i915_gem_object_pin_map() below */
2522 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
,
2523 enum i915_map_type type
)
2525 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2526 struct sg_table
*sgt
= obj
->mm
.pages
;
2527 struct sgt_iter sgt_iter
;
2529 struct page
*stack_pages
[32];
2530 struct page
**pages
= stack_pages
;
2531 unsigned long i
= 0;
2535 /* A single page can always be kmapped */
2536 if (n_pages
== 1 && type
== I915_MAP_WB
)
2537 return kmap(sg_page(sgt
->sgl
));
2539 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2540 /* Too big for stack -- allocate temporary array instead */
2541 pages
= drm_malloc_gfp(n_pages
, sizeof(*pages
), GFP_TEMPORARY
);
2546 for_each_sgt_page(page
, sgt_iter
, sgt
)
2549 /* Check that we have the expected number of pages */
2550 GEM_BUG_ON(i
!= n_pages
);
2554 pgprot
= PAGE_KERNEL
;
2557 pgprot
= pgprot_writecombine(PAGE_KERNEL_IO
);
2560 addr
= vmap(pages
, n_pages
, 0, pgprot
);
2562 if (pages
!= stack_pages
)
2563 drm_free_large(pages
);
2568 /* get, pin, and map the pages of the object into kernel space */
2569 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
2570 enum i915_map_type type
)
2572 enum i915_map_type has_type
;
2577 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
2579 ret
= mutex_lock_interruptible(&obj
->mm
.lock
);
2581 return ERR_PTR(ret
);
2584 if (!atomic_inc_not_zero(&obj
->mm
.pages_pin_count
)) {
2585 if (unlikely(IS_ERR_OR_NULL(obj
->mm
.pages
))) {
2586 ret
= ____i915_gem_object_get_pages(obj
);
2590 smp_mb__before_atomic();
2592 atomic_inc(&obj
->mm
.pages_pin_count
);
2595 GEM_BUG_ON(!obj
->mm
.pages
);
2597 ptr
= ptr_unpack_bits(obj
->mm
.mapping
, has_type
);
2598 if (ptr
&& has_type
!= type
) {
2604 if (is_vmalloc_addr(ptr
))
2607 kunmap(kmap_to_page(ptr
));
2609 ptr
= obj
->mm
.mapping
= NULL
;
2613 ptr
= i915_gem_object_map(obj
, type
);
2619 obj
->mm
.mapping
= ptr_pack_bits(ptr
, type
);
2623 mutex_unlock(&obj
->mm
.lock
);
2627 atomic_dec(&obj
->mm
.pages_pin_count
);
2633 static bool i915_context_is_banned(const struct i915_gem_context
*ctx
)
2635 unsigned long elapsed
;
2637 if (ctx
->hang_stats
.banned
)
2640 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2641 if (ctx
->hang_stats
.ban_period_seconds
&&
2642 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2643 DRM_DEBUG("context hanging too fast, banning!\n");
2650 static void i915_set_reset_status(struct i915_gem_context
*ctx
,
2653 struct i915_ctx_hang_stats
*hs
= &ctx
->hang_stats
;
2656 hs
->banned
= i915_context_is_banned(ctx
);
2658 hs
->guilty_ts
= get_seconds();
2660 hs
->batch_pending
++;
2664 struct drm_i915_gem_request
*
2665 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2667 struct drm_i915_gem_request
*request
;
2669 /* We are called by the error capture and reset at a random
2670 * point in time. In particular, note that neither is crucially
2671 * ordered with an interrupt. After a hang, the GPU is dead and we
2672 * assume that no more writes can happen (we waited long enough for
2673 * all writes that were in transaction to be flushed) - adding an
2674 * extra delay for a recent interrupt is pointless. Hence, we do
2675 * not need an engine->irq_seqno_barrier() before the seqno reads.
2677 list_for_each_entry(request
, &engine
->timeline
->requests
, link
) {
2678 if (__i915_gem_request_completed(request
))
2687 static void reset_request(struct drm_i915_gem_request
*request
)
2689 void *vaddr
= request
->ring
->vaddr
;
2692 /* As this request likely depends on state from the lost
2693 * context, clear out all the user operations leaving the
2694 * breadcrumb at the end (so we get the fence notifications).
2696 head
= request
->head
;
2697 if (request
->postfix
< head
) {
2698 memset(vaddr
+ head
, 0, request
->ring
->size
- head
);
2701 memset(vaddr
+ head
, 0, request
->postfix
- head
);
2704 static void i915_gem_reset_engine(struct intel_engine_cs
*engine
)
2706 struct drm_i915_gem_request
*request
;
2707 struct i915_gem_context
*incomplete_ctx
;
2708 struct intel_timeline
*timeline
;
2709 unsigned long flags
;
2712 if (engine
->irq_seqno_barrier
)
2713 engine
->irq_seqno_barrier(engine
);
2715 request
= i915_gem_find_active_request(engine
);
2719 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2720 if (engine
->hangcheck
.seqno
!= intel_engine_get_seqno(engine
))
2723 i915_set_reset_status(request
->ctx
, ring_hung
);
2727 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2728 engine
->name
, request
->global_seqno
);
2730 /* Setup the CS to resume from the breadcrumb of the hung request */
2731 engine
->reset_hw(engine
, request
);
2733 /* Users of the default context do not rely on logical state
2734 * preserved between batches. They have to emit full state on
2735 * every batch and so it is safe to execute queued requests following
2738 * Other contexts preserve state, now corrupt. We want to skip all
2739 * queued requests that reference the corrupt context.
2741 incomplete_ctx
= request
->ctx
;
2742 if (i915_gem_context_is_default(incomplete_ctx
))
2745 timeline
= i915_gem_context_lookup_timeline(incomplete_ctx
, engine
);
2747 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2748 spin_lock(&timeline
->lock
);
2750 list_for_each_entry_continue(request
, &engine
->timeline
->requests
, link
)
2751 if (request
->ctx
== incomplete_ctx
)
2752 reset_request(request
);
2754 list_for_each_entry(request
, &timeline
->requests
, link
)
2755 reset_request(request
);
2757 spin_unlock(&timeline
->lock
);
2758 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2761 void i915_gem_reset(struct drm_i915_private
*dev_priv
)
2763 struct intel_engine_cs
*engine
;
2764 enum intel_engine_id id
;
2766 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2768 i915_gem_retire_requests(dev_priv
);
2770 for_each_engine(engine
, dev_priv
, id
)
2771 i915_gem_reset_engine(engine
);
2773 i915_gem_restore_fences(dev_priv
);
2775 if (dev_priv
->gt
.awake
) {
2776 intel_sanitize_gt_powersave(dev_priv
);
2777 intel_enable_gt_powersave(dev_priv
);
2778 if (INTEL_GEN(dev_priv
) >= 6)
2779 gen6_rps_busy(dev_priv
);
2783 static void nop_submit_request(struct drm_i915_gem_request
*request
)
2785 i915_gem_request_submit(request
);
2786 intel_engine_init_global_seqno(request
->engine
, request
->global_seqno
);
2789 static void i915_gem_cleanup_engine(struct intel_engine_cs
*engine
)
2791 engine
->submit_request
= nop_submit_request
;
2793 /* Mark all pending requests as complete so that any concurrent
2794 * (lockless) lookup doesn't try and wait upon the request as we
2797 intel_engine_init_global_seqno(engine
,
2798 intel_engine_last_submit(engine
));
2801 * Clear the execlists queue up before freeing the requests, as those
2802 * are the ones that keep the context and ringbuffer backing objects
2806 if (i915
.enable_execlists
) {
2807 unsigned long flags
;
2809 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2811 i915_gem_request_put(engine
->execlist_port
[0].request
);
2812 i915_gem_request_put(engine
->execlist_port
[1].request
);
2813 memset(engine
->execlist_port
, 0, sizeof(engine
->execlist_port
));
2814 engine
->execlist_queue
= RB_ROOT
;
2815 engine
->execlist_first
= NULL
;
2817 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2821 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
)
2823 struct intel_engine_cs
*engine
;
2824 enum intel_engine_id id
;
2826 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2827 set_bit(I915_WEDGED
, &dev_priv
->gpu_error
.flags
);
2829 i915_gem_context_lost(dev_priv
);
2830 for_each_engine(engine
, dev_priv
, id
)
2831 i915_gem_cleanup_engine(engine
);
2832 mod_delayed_work(dev_priv
->wq
, &dev_priv
->gt
.idle_work
, 0);
2834 i915_gem_retire_requests(dev_priv
);
2838 i915_gem_retire_work_handler(struct work_struct
*work
)
2840 struct drm_i915_private
*dev_priv
=
2841 container_of(work
, typeof(*dev_priv
), gt
.retire_work
.work
);
2842 struct drm_device
*dev
= &dev_priv
->drm
;
2844 /* Come back later if the device is busy... */
2845 if (mutex_trylock(&dev
->struct_mutex
)) {
2846 i915_gem_retire_requests(dev_priv
);
2847 mutex_unlock(&dev
->struct_mutex
);
2850 /* Keep the retire handler running until we are finally idle.
2851 * We do not need to do this test under locking as in the worst-case
2852 * we queue the retire worker once too often.
2854 if (READ_ONCE(dev_priv
->gt
.awake
)) {
2855 i915_queue_hangcheck(dev_priv
);
2856 queue_delayed_work(dev_priv
->wq
,
2857 &dev_priv
->gt
.retire_work
,
2858 round_jiffies_up_relative(HZ
));
2863 i915_gem_idle_work_handler(struct work_struct
*work
)
2865 struct drm_i915_private
*dev_priv
=
2866 container_of(work
, typeof(*dev_priv
), gt
.idle_work
.work
);
2867 struct drm_device
*dev
= &dev_priv
->drm
;
2868 struct intel_engine_cs
*engine
;
2869 enum intel_engine_id id
;
2870 bool rearm_hangcheck
;
2872 if (!READ_ONCE(dev_priv
->gt
.awake
))
2876 * Wait for last execlists context complete, but bail out in case a
2877 * new request is submitted.
2879 wait_for(READ_ONCE(dev_priv
->gt
.active_requests
) ||
2880 intel_execlists_idle(dev_priv
), 10);
2882 if (READ_ONCE(dev_priv
->gt
.active_requests
))
2886 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
2888 if (!mutex_trylock(&dev
->struct_mutex
)) {
2889 /* Currently busy, come back later */
2890 mod_delayed_work(dev_priv
->wq
,
2891 &dev_priv
->gt
.idle_work
,
2892 msecs_to_jiffies(50));
2897 * New request retired after this work handler started, extend active
2898 * period until next instance of the work.
2900 if (work_pending(work
))
2903 if (dev_priv
->gt
.active_requests
)
2906 if (wait_for(intel_execlists_idle(dev_priv
), 10))
2907 DRM_ERROR("Timeout waiting for engines to idle\n");
2909 for_each_engine(engine
, dev_priv
, id
)
2910 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2912 GEM_BUG_ON(!dev_priv
->gt
.awake
);
2913 dev_priv
->gt
.awake
= false;
2914 rearm_hangcheck
= false;
2916 if (INTEL_GEN(dev_priv
) >= 6)
2917 gen6_rps_idle(dev_priv
);
2918 intel_runtime_pm_put(dev_priv
);
2920 mutex_unlock(&dev
->struct_mutex
);
2923 if (rearm_hangcheck
) {
2924 GEM_BUG_ON(!dev_priv
->gt
.awake
);
2925 i915_queue_hangcheck(dev_priv
);
2929 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
)
2931 struct drm_i915_gem_object
*obj
= to_intel_bo(gem
);
2932 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
2933 struct i915_vma
*vma
, *vn
;
2935 mutex_lock(&obj
->base
.dev
->struct_mutex
);
2936 list_for_each_entry_safe(vma
, vn
, &obj
->vma_list
, obj_link
)
2937 if (vma
->vm
->file
== fpriv
)
2938 i915_vma_close(vma
);
2940 if (i915_gem_object_is_active(obj
) &&
2941 !i915_gem_object_has_active_reference(obj
)) {
2942 i915_gem_object_set_active_reference(obj
);
2943 i915_gem_object_get(obj
);
2945 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
2948 static unsigned long to_wait_timeout(s64 timeout_ns
)
2951 return MAX_SCHEDULE_TIMEOUT
;
2953 if (timeout_ns
== 0)
2956 return nsecs_to_jiffies_timeout(timeout_ns
);
2960 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2961 * @dev: drm device pointer
2962 * @data: ioctl data blob
2963 * @file: drm file pointer
2965 * Returns 0 if successful, else an error is returned with the remaining time in
2966 * the timeout parameter.
2967 * -ETIME: object is still busy after timeout
2968 * -ERESTARTSYS: signal interrupted the wait
2969 * -ENONENT: object doesn't exist
2970 * Also possible, but rare:
2971 * -EAGAIN: GPU wedged
2973 * -ENODEV: Internal IRQ fail
2974 * -E?: The add request failed
2976 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2977 * non-zero timeout parameter the wait ioctl will wait for the given number of
2978 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2979 * without holding struct_mutex the object may become re-busied before this
2980 * function completes. A similar but shorter * race condition exists in the busy
2984 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2986 struct drm_i915_gem_wait
*args
= data
;
2987 struct drm_i915_gem_object
*obj
;
2991 if (args
->flags
!= 0)
2994 obj
= i915_gem_object_lookup(file
, args
->bo_handle
);
2998 start
= ktime_get();
3000 ret
= i915_gem_object_wait(obj
,
3001 I915_WAIT_INTERRUPTIBLE
| I915_WAIT_ALL
,
3002 to_wait_timeout(args
->timeout_ns
),
3003 to_rps_client(file
));
3005 if (args
->timeout_ns
> 0) {
3006 args
->timeout_ns
-= ktime_to_ns(ktime_sub(ktime_get(), start
));
3007 if (args
->timeout_ns
< 0)
3008 args
->timeout_ns
= 0;
3011 * Apparently ktime isn't accurate enough and occasionally has a
3012 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3013 * things up to make the test happy. We allow up to 1 jiffy.
3015 * This is a regression from the timespec->ktime conversion.
3017 if (ret
== -ETIME
&& !nsecs_to_jiffies(args
->timeout_ns
))
3018 args
->timeout_ns
= 0;
3021 i915_gem_object_put(obj
);
3025 static int wait_for_timeline(struct i915_gem_timeline
*tl
, unsigned int flags
)
3029 for (i
= 0; i
< ARRAY_SIZE(tl
->engine
); i
++) {
3030 ret
= i915_gem_active_wait(&tl
->engine
[i
].last_request
, flags
);
3038 int i915_gem_wait_for_idle(struct drm_i915_private
*i915
, unsigned int flags
)
3042 if (flags
& I915_WAIT_LOCKED
) {
3043 struct i915_gem_timeline
*tl
;
3045 lockdep_assert_held(&i915
->drm
.struct_mutex
);
3047 list_for_each_entry(tl
, &i915
->gt
.timelines
, link
) {
3048 ret
= wait_for_timeline(tl
, flags
);
3053 ret
= wait_for_timeline(&i915
->gt
.global_timeline
, flags
);
3061 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3064 /* If we don't have a page list set up, then we're not pinned
3065 * to GPU, and we can ignore the cache flush because it'll happen
3066 * again at bind time.
3072 * Stolen memory is always coherent with the GPU as it is explicitly
3073 * marked as wc by the system, or the system is cache-coherent.
3075 if (obj
->stolen
|| obj
->phys_handle
)
3078 /* If the GPU is snooping the contents of the CPU cache,
3079 * we do not need to manually clear the CPU cache lines. However,
3080 * the caches are only snooped when the render cache is
3081 * flushed/invalidated. As we always have to emit invalidations
3082 * and flushes when moving into and out of the RENDER domain, correct
3083 * snooping behaviour occurs naturally as the result of our domain
3086 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3087 obj
->cache_dirty
= true;
3091 trace_i915_gem_object_clflush(obj
);
3092 drm_clflush_sg(obj
->mm
.pages
);
3093 obj
->cache_dirty
= false;
3096 /** Flushes the GTT write domain for the object if it's dirty. */
3098 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3100 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3102 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3105 /* No actual flushing is required for the GTT write domain. Writes
3106 * to it "immediately" go to main memory as far as we know, so there's
3107 * no chipset flush. It also doesn't land in render cache.
3109 * However, we do have to enforce the order so that all writes through
3110 * the GTT land before any writes to the device, such as updates to
3113 * We also have to wait a bit for the writes to land from the GTT.
3114 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3115 * timing. This issue has only been observed when switching quickly
3116 * between GTT writes and CPU reads from inside the kernel on recent hw,
3117 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3118 * system agents we cannot reproduce this behaviour).
3121 if (INTEL_GEN(dev_priv
) >= 6 && !HAS_LLC(dev_priv
))
3122 POSTING_READ(RING_ACTHD(dev_priv
->engine
[RCS
]->mmio_base
));
3124 intel_fb_obj_flush(obj
, false, write_origin(obj
, I915_GEM_DOMAIN_GTT
));
3126 obj
->base
.write_domain
= 0;
3127 trace_i915_gem_object_change_domain(obj
,
3128 obj
->base
.read_domains
,
3129 I915_GEM_DOMAIN_GTT
);
3132 /** Flushes the CPU write domain for the object if it's dirty. */
3134 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3136 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3139 i915_gem_clflush_object(obj
, obj
->pin_display
);
3140 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3142 obj
->base
.write_domain
= 0;
3143 trace_i915_gem_object_change_domain(obj
,
3144 obj
->base
.read_domains
,
3145 I915_GEM_DOMAIN_CPU
);
3149 * Moves a single object to the GTT read, and possibly write domain.
3150 * @obj: object to act on
3151 * @write: ask for write access or read only
3153 * This function returns when the move is complete, including waiting on
3157 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3159 uint32_t old_write_domain
, old_read_domains
;
3162 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3164 ret
= i915_gem_object_wait(obj
,
3165 I915_WAIT_INTERRUPTIBLE
|
3167 (write
? I915_WAIT_ALL
: 0),
3168 MAX_SCHEDULE_TIMEOUT
,
3173 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3176 /* Flush and acquire obj->pages so that we are coherent through
3177 * direct access in memory with previous cached writes through
3178 * shmemfs and that our cache domain tracking remains valid.
3179 * For example, if the obj->filp was moved to swap without us
3180 * being notified and releasing the pages, we would mistakenly
3181 * continue to assume that the obj remained out of the CPU cached
3184 ret
= i915_gem_object_pin_pages(obj
);
3188 i915_gem_object_flush_cpu_write_domain(obj
);
3190 /* Serialise direct access to this object with the barriers for
3191 * coherent writes from the GPU, by effectively invalidating the
3192 * GTT domain upon first access.
3194 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3197 old_write_domain
= obj
->base
.write_domain
;
3198 old_read_domains
= obj
->base
.read_domains
;
3200 /* It should now be out of any other write domains, and we can update
3201 * the domain values for our changes.
3203 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3204 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3206 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3207 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3208 obj
->mm
.dirty
= true;
3211 trace_i915_gem_object_change_domain(obj
,
3215 i915_gem_object_unpin_pages(obj
);
3220 * Changes the cache-level of an object across all VMA.
3221 * @obj: object to act on
3222 * @cache_level: new cache level to set for the object
3224 * After this function returns, the object will be in the new cache-level
3225 * across all GTT and the contents of the backing storage will be coherent,
3226 * with respect to the new cache-level. In order to keep the backing storage
3227 * coherent for all users, we only allow a single cache level to be set
3228 * globally on the object and prevent it from being changed whilst the
3229 * hardware is reading from the object. That is if the object is currently
3230 * on the scanout it will be set to uncached (or equivalent display
3231 * cache coherency) and all non-MOCS GPU access will also be uncached so
3232 * that all direct access to the scanout remains coherent.
3234 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3235 enum i915_cache_level cache_level
)
3237 struct i915_vma
*vma
;
3240 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3242 if (obj
->cache_level
== cache_level
)
3245 /* Inspect the list of currently bound VMA and unbind any that would
3246 * be invalid given the new cache-level. This is principally to
3247 * catch the issue of the CS prefetch crossing page boundaries and
3248 * reading an invalid PTE on older architectures.
3251 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3252 if (!drm_mm_node_allocated(&vma
->node
))
3255 if (i915_vma_is_pinned(vma
)) {
3256 DRM_DEBUG("can not change the cache level of pinned objects\n");
3260 if (i915_gem_valid_gtt_space(vma
, cache_level
))
3263 ret
= i915_vma_unbind(vma
);
3267 /* As unbinding may affect other elements in the
3268 * obj->vma_list (due to side-effects from retiring
3269 * an active vma), play safe and restart the iterator.
3274 /* We can reuse the existing drm_mm nodes but need to change the
3275 * cache-level on the PTE. We could simply unbind them all and
3276 * rebind with the correct cache-level on next use. However since
3277 * we already have a valid slot, dma mapping, pages etc, we may as
3278 * rewrite the PTE in the belief that doing so tramples upon less
3279 * state and so involves less work.
3281 if (obj
->bind_count
) {
3282 /* Before we change the PTE, the GPU must not be accessing it.
3283 * If we wait upon the object, we know that all the bound
3284 * VMA are no longer active.
3286 ret
= i915_gem_object_wait(obj
,
3287 I915_WAIT_INTERRUPTIBLE
|
3290 MAX_SCHEDULE_TIMEOUT
,
3295 if (!HAS_LLC(to_i915(obj
->base
.dev
)) &&
3296 cache_level
!= I915_CACHE_NONE
) {
3297 /* Access to snoopable pages through the GTT is
3298 * incoherent and on some machines causes a hard
3299 * lockup. Relinquish the CPU mmaping to force
3300 * userspace to refault in the pages and we can
3301 * then double check if the GTT mapping is still
3302 * valid for that pointer access.
3304 i915_gem_release_mmap(obj
);
3306 /* As we no longer need a fence for GTT access,
3307 * we can relinquish it now (and so prevent having
3308 * to steal a fence from someone else on the next
3309 * fence request). Note GPU activity would have
3310 * dropped the fence as all snoopable access is
3311 * supposed to be linear.
3313 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3314 ret
= i915_vma_put_fence(vma
);
3319 /* We either have incoherent backing store and
3320 * so no GTT access or the architecture is fully
3321 * coherent. In such cases, existing GTT mmaps
3322 * ignore the cache bit in the PTE and we can
3323 * rewrite it without confusing the GPU or having
3324 * to force userspace to fault back in its mmaps.
3328 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3329 if (!drm_mm_node_allocated(&vma
->node
))
3332 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3338 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
&&
3339 cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3340 obj
->cache_dirty
= true;
3342 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3343 vma
->node
.color
= cache_level
;
3344 obj
->cache_level
= cache_level
;
3349 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3350 struct drm_file
*file
)
3352 struct drm_i915_gem_caching
*args
= data
;
3353 struct drm_i915_gem_object
*obj
;
3357 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3363 switch (obj
->cache_level
) {
3364 case I915_CACHE_LLC
:
3365 case I915_CACHE_L3_LLC
:
3366 args
->caching
= I915_CACHING_CACHED
;
3370 args
->caching
= I915_CACHING_DISPLAY
;
3374 args
->caching
= I915_CACHING_NONE
;
3382 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3383 struct drm_file
*file
)
3385 struct drm_i915_private
*i915
= to_i915(dev
);
3386 struct drm_i915_gem_caching
*args
= data
;
3387 struct drm_i915_gem_object
*obj
;
3388 enum i915_cache_level level
;
3391 switch (args
->caching
) {
3392 case I915_CACHING_NONE
:
3393 level
= I915_CACHE_NONE
;
3395 case I915_CACHING_CACHED
:
3397 * Due to a HW issue on BXT A stepping, GPU stores via a
3398 * snooped mapping may leave stale data in a corresponding CPU
3399 * cacheline, whereas normally such cachelines would get
3402 if (!HAS_LLC(i915
) && !HAS_SNOOP(i915
))
3405 level
= I915_CACHE_LLC
;
3407 case I915_CACHING_DISPLAY
:
3408 level
= HAS_WT(i915
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3414 ret
= i915_mutex_lock_interruptible(dev
);
3418 obj
= i915_gem_object_lookup(file
, args
->handle
);
3424 ret
= i915_gem_object_set_cache_level(obj
, level
);
3425 i915_gem_object_put(obj
);
3427 mutex_unlock(&dev
->struct_mutex
);
3432 * Prepare buffer for display plane (scanout, cursors, etc).
3433 * Can be called from an uninterruptible phase (modesetting) and allows
3434 * any flushes to be pipelined (for pageflips).
3437 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3439 const struct i915_ggtt_view
*view
)
3441 struct i915_vma
*vma
;
3442 u32 old_read_domains
, old_write_domain
;
3445 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3447 /* Mark the pin_display early so that we account for the
3448 * display coherency whilst setting up the cache domains.
3452 /* The display engine is not coherent with the LLC cache on gen6. As
3453 * a result, we make sure that the pinning that is about to occur is
3454 * done with uncached PTEs. This is lowest common denominator for all
3457 * However for gen6+, we could do better by using the GFDT bit instead
3458 * of uncaching, which would allow us to flush all the LLC-cached data
3459 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3461 ret
= i915_gem_object_set_cache_level(obj
,
3462 HAS_WT(to_i915(obj
->base
.dev
)) ?
3463 I915_CACHE_WT
: I915_CACHE_NONE
);
3466 goto err_unpin_display
;
3469 /* As the user may map the buffer once pinned in the display plane
3470 * (e.g. libkms for the bootup splash), we have to ensure that we
3471 * always use map_and_fenceable for all scanout buffers. However,
3472 * it may simply be too big to fit into mappable, in which case
3473 * put it anyway and hope that userspace can cope (but always first
3474 * try to preserve the existing ABI).
3476 vma
= ERR_PTR(-ENOSPC
);
3477 if (view
->type
== I915_GGTT_VIEW_NORMAL
)
3478 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
,
3479 PIN_MAPPABLE
| PIN_NONBLOCK
);
3481 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3484 /* Valleyview is definitely limited to scanning out the first
3485 * 512MiB. Lets presume this behaviour was inherited from the
3486 * g4x display engine and that all earlier gen are similarly
3487 * limited. Testing suggests that it is a little more
3488 * complicated than this. For example, Cherryview appears quite
3489 * happy to scanout from anywhere within its global aperture.
3492 if (HAS_GMCH_DISPLAY(i915
))
3493 flags
= PIN_MAPPABLE
;
3494 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
, flags
);
3497 goto err_unpin_display
;
3499 vma
->display_alignment
= max_t(u64
, vma
->display_alignment
, alignment
);
3501 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3502 if (obj
->cache_dirty
|| obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3503 i915_gem_clflush_object(obj
, true);
3504 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
3507 old_write_domain
= obj
->base
.write_domain
;
3508 old_read_domains
= obj
->base
.read_domains
;
3510 /* It should now be out of any other write domains, and we can update
3511 * the domain values for our changes.
3513 obj
->base
.write_domain
= 0;
3514 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3516 trace_i915_gem_object_change_domain(obj
,
3528 i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
)
3530 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
3532 if (WARN_ON(vma
->obj
->pin_display
== 0))
3535 if (--vma
->obj
->pin_display
== 0)
3536 vma
->display_alignment
= 0;
3538 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3539 if (!i915_vma_is_active(vma
))
3540 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
3542 i915_vma_unpin(vma
);
3546 * Moves a single object to the CPU read, and possibly write domain.
3547 * @obj: object to act on
3548 * @write: requesting write or read-only access
3550 * This function returns when the move is complete, including waiting on
3554 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3556 uint32_t old_write_domain
, old_read_domains
;
3559 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3561 ret
= i915_gem_object_wait(obj
,
3562 I915_WAIT_INTERRUPTIBLE
|
3564 (write
? I915_WAIT_ALL
: 0),
3565 MAX_SCHEDULE_TIMEOUT
,
3570 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3573 i915_gem_object_flush_gtt_write_domain(obj
);
3575 old_write_domain
= obj
->base
.write_domain
;
3576 old_read_domains
= obj
->base
.read_domains
;
3578 /* Flush the CPU cache if it's still invalid. */
3579 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3580 i915_gem_clflush_object(obj
, false);
3582 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3585 /* It should now be out of any other write domains, and we can update
3586 * the domain values for our changes.
3588 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3590 /* If we're writing through the CPU, then the GPU read domains will
3591 * need to be invalidated at next use.
3594 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3595 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3598 trace_i915_gem_object_change_domain(obj
,
3605 /* Throttle our rendering by waiting until the ring has completed our requests
3606 * emitted over 20 msec ago.
3608 * Note that if we were to use the current jiffies each time around the loop,
3609 * we wouldn't escape the function with any frames outstanding if the time to
3610 * render a frame was over 20ms.
3612 * This should get us reasonable parallelism between CPU and GPU but also
3613 * relatively low latency when blocking on a particular request to finish.
3616 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3618 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3619 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3620 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
3621 struct drm_i915_gem_request
*request
, *target
= NULL
;
3624 /* ABI: return -EIO if already wedged */
3625 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
3628 spin_lock(&file_priv
->mm
.lock
);
3629 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3630 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3634 * Note that the request might not have been submitted yet.
3635 * In which case emitted_jiffies will be zero.
3637 if (!request
->emitted_jiffies
)
3643 i915_gem_request_get(target
);
3644 spin_unlock(&file_priv
->mm
.lock
);
3649 ret
= i915_wait_request(target
,
3650 I915_WAIT_INTERRUPTIBLE
,
3651 MAX_SCHEDULE_TIMEOUT
);
3652 i915_gem_request_put(target
);
3654 return ret
< 0 ? ret
: 0;
3658 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3659 const struct i915_ggtt_view
*view
,
3664 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3665 struct i915_address_space
*vm
= &dev_priv
->ggtt
.base
;
3666 struct i915_vma
*vma
;
3669 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3671 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
, view
);
3675 if (i915_vma_misplaced(vma
, size
, alignment
, flags
)) {
3676 if (flags
& PIN_NONBLOCK
&&
3677 (i915_vma_is_pinned(vma
) || i915_vma_is_active(vma
)))
3678 return ERR_PTR(-ENOSPC
);
3680 if (flags
& PIN_MAPPABLE
) {
3683 fence_size
= i915_gem_get_ggtt_size(dev_priv
, vma
->size
,
3684 i915_gem_object_get_tiling(obj
));
3685 /* If the required space is larger than the available
3686 * aperture, we will not able to find a slot for the
3687 * object and unbinding the object now will be in
3688 * vain. Worse, doing so may cause us to ping-pong
3689 * the object in and out of the Global GTT and
3690 * waste a lot of cycles under the mutex.
3692 if (fence_size
> dev_priv
->ggtt
.mappable_end
)
3693 return ERR_PTR(-E2BIG
);
3695 /* If NONBLOCK is set the caller is optimistically
3696 * trying to cache the full object within the mappable
3697 * aperture, and *must* have a fallback in place for
3698 * situations where we cannot bind the object. We
3699 * can be a little more lax here and use the fallback
3700 * more often to avoid costly migrations of ourselves
3701 * and other objects within the aperture.
3703 * Half-the-aperture is used as a simple heuristic.
3704 * More interesting would to do search for a free
3705 * block prior to making the commitment to unbind.
3706 * That caters for the self-harm case, and with a
3707 * little more heuristics (e.g. NOFAULT, NOEVICT)
3708 * we could try to minimise harm to others.
3710 if (flags
& PIN_NONBLOCK
&&
3711 fence_size
> dev_priv
->ggtt
.mappable_end
/ 2)
3712 return ERR_PTR(-ENOSPC
);
3715 WARN(i915_vma_is_pinned(vma
),
3716 "bo is already pinned in ggtt with incorrect alignment:"
3717 " offset=%08x, req.alignment=%llx,"
3718 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3719 i915_ggtt_offset(vma
), alignment
,
3720 !!(flags
& PIN_MAPPABLE
),
3721 i915_vma_is_map_and_fenceable(vma
));
3722 ret
= i915_vma_unbind(vma
);
3724 return ERR_PTR(ret
);
3727 ret
= i915_vma_pin(vma
, size
, alignment
, flags
| PIN_GLOBAL
);
3729 return ERR_PTR(ret
);
3734 static __always_inline
unsigned int __busy_read_flag(unsigned int id
)
3736 /* Note that we could alias engines in the execbuf API, but
3737 * that would be very unwise as it prevents userspace from
3738 * fine control over engine selection. Ahem.
3740 * This should be something like EXEC_MAX_ENGINE instead of
3743 BUILD_BUG_ON(I915_NUM_ENGINES
> 16);
3744 return 0x10000 << id
;
3747 static __always_inline
unsigned int __busy_write_id(unsigned int id
)
3749 /* The uABI guarantees an active writer is also amongst the read
3750 * engines. This would be true if we accessed the activity tracking
3751 * under the lock, but as we perform the lookup of the object and
3752 * its activity locklessly we can not guarantee that the last_write
3753 * being active implies that we have set the same engine flag from
3754 * last_read - hence we always set both read and write busy for
3757 return id
| __busy_read_flag(id
);
3760 static __always_inline
unsigned int
3761 __busy_set_if_active(const struct dma_fence
*fence
,
3762 unsigned int (*flag
)(unsigned int id
))
3764 struct drm_i915_gem_request
*rq
;
3766 /* We have to check the current hw status of the fence as the uABI
3767 * guarantees forward progress. We could rely on the idle worker
3768 * to eventually flush us, but to minimise latency just ask the
3771 * Note we only report on the status of native fences.
3773 if (!dma_fence_is_i915(fence
))
3776 /* opencode to_request() in order to avoid const warnings */
3777 rq
= container_of(fence
, struct drm_i915_gem_request
, fence
);
3778 if (i915_gem_request_completed(rq
))
3781 return flag(rq
->engine
->exec_id
);
3784 static __always_inline
unsigned int
3785 busy_check_reader(const struct dma_fence
*fence
)
3787 return __busy_set_if_active(fence
, __busy_read_flag
);
3790 static __always_inline
unsigned int
3791 busy_check_writer(const struct dma_fence
*fence
)
3796 return __busy_set_if_active(fence
, __busy_write_id
);
3800 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3801 struct drm_file
*file
)
3803 struct drm_i915_gem_busy
*args
= data
;
3804 struct drm_i915_gem_object
*obj
;
3805 struct reservation_object_list
*list
;
3811 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3815 /* A discrepancy here is that we do not report the status of
3816 * non-i915 fences, i.e. even though we may report the object as idle,
3817 * a call to set-domain may still stall waiting for foreign rendering.
3818 * This also means that wait-ioctl may report an object as busy,
3819 * where busy-ioctl considers it idle.
3821 * We trade the ability to warn of foreign fences to report on which
3822 * i915 engines are active for the object.
3824 * Alternatively, we can trade that extra information on read/write
3827 * !reservation_object_test_signaled_rcu(obj->resv, true);
3828 * to report the overall busyness. This is what the wait-ioctl does.
3832 seq
= raw_read_seqcount(&obj
->resv
->seq
);
3834 /* Translate the exclusive fence to the READ *and* WRITE engine */
3835 args
->busy
= busy_check_writer(rcu_dereference(obj
->resv
->fence_excl
));
3837 /* Translate shared fences to READ set of engines */
3838 list
= rcu_dereference(obj
->resv
->fence
);
3840 unsigned int shared_count
= list
->shared_count
, i
;
3842 for (i
= 0; i
< shared_count
; ++i
) {
3843 struct dma_fence
*fence
=
3844 rcu_dereference(list
->shared
[i
]);
3846 args
->busy
|= busy_check_reader(fence
);
3850 if (args
->busy
&& read_seqcount_retry(&obj
->resv
->seq
, seq
))
3860 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3861 struct drm_file
*file_priv
)
3863 return i915_gem_ring_throttle(dev
, file_priv
);
3867 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3868 struct drm_file
*file_priv
)
3870 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3871 struct drm_i915_gem_madvise
*args
= data
;
3872 struct drm_i915_gem_object
*obj
;
3875 switch (args
->madv
) {
3876 case I915_MADV_DONTNEED
:
3877 case I915_MADV_WILLNEED
:
3883 obj
= i915_gem_object_lookup(file_priv
, args
->handle
);
3887 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
3891 if (obj
->mm
.pages
&&
3892 i915_gem_object_is_tiled(obj
) &&
3893 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
3894 if (obj
->mm
.madv
== I915_MADV_WILLNEED
) {
3895 GEM_BUG_ON(!obj
->mm
.quirked
);
3896 __i915_gem_object_unpin_pages(obj
);
3897 obj
->mm
.quirked
= false;
3899 if (args
->madv
== I915_MADV_WILLNEED
) {
3900 GEM_BUG_ON(obj
->mm
.quirked
);
3901 __i915_gem_object_pin_pages(obj
);
3902 obj
->mm
.quirked
= true;
3906 if (obj
->mm
.madv
!= __I915_MADV_PURGED
)
3907 obj
->mm
.madv
= args
->madv
;
3909 /* if the object is no longer attached, discard its backing storage */
3910 if (obj
->mm
.madv
== I915_MADV_DONTNEED
&& !obj
->mm
.pages
)
3911 i915_gem_object_truncate(obj
);
3913 args
->retained
= obj
->mm
.madv
!= __I915_MADV_PURGED
;
3914 mutex_unlock(&obj
->mm
.lock
);
3917 i915_gem_object_put(obj
);
3922 frontbuffer_retire(struct i915_gem_active
*active
,
3923 struct drm_i915_gem_request
*request
)
3925 struct drm_i915_gem_object
*obj
=
3926 container_of(active
, typeof(*obj
), frontbuffer_write
);
3928 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
3931 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3932 const struct drm_i915_gem_object_ops
*ops
)
3934 mutex_init(&obj
->mm
.lock
);
3936 INIT_LIST_HEAD(&obj
->global_link
);
3937 INIT_LIST_HEAD(&obj
->userfault_link
);
3938 INIT_LIST_HEAD(&obj
->obj_exec_link
);
3939 INIT_LIST_HEAD(&obj
->vma_list
);
3940 INIT_LIST_HEAD(&obj
->batch_pool_link
);
3944 reservation_object_init(&obj
->__builtin_resv
);
3945 obj
->resv
= &obj
->__builtin_resv
;
3947 obj
->frontbuffer_ggtt_origin
= ORIGIN_GTT
;
3948 init_request_active(&obj
->frontbuffer_write
, frontbuffer_retire
);
3950 obj
->mm
.madv
= I915_MADV_WILLNEED
;
3951 INIT_RADIX_TREE(&obj
->mm
.get_page
.radix
, GFP_KERNEL
| __GFP_NOWARN
);
3952 mutex_init(&obj
->mm
.get_page
.lock
);
3954 i915_gem_info_add_obj(to_i915(obj
->base
.dev
), obj
->base
.size
);
3957 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3958 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
|
3959 I915_GEM_OBJECT_IS_SHRINKABLE
,
3960 .get_pages
= i915_gem_object_get_pages_gtt
,
3961 .put_pages
= i915_gem_object_put_pages_gtt
,
3964 /* Note we don't consider signbits :| */
3965 #define overflows_type(x, T) \
3966 (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
3968 struct drm_i915_gem_object
*
3969 i915_gem_object_create(struct drm_device
*dev
, u64 size
)
3971 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3972 struct drm_i915_gem_object
*obj
;
3973 struct address_space
*mapping
;
3977 /* There is a prevalence of the assumption that we fit the object's
3978 * page count inside a 32bit _signed_ variable. Let's document this and
3979 * catch if we ever need to fix it. In the meantime, if you do spot
3980 * such a local variable, please consider fixing!
3982 if (WARN_ON(size
>> PAGE_SHIFT
> INT_MAX
))
3983 return ERR_PTR(-E2BIG
);
3985 if (overflows_type(size
, obj
->base
.size
))
3986 return ERR_PTR(-E2BIG
);
3988 obj
= i915_gem_object_alloc(dev
);
3990 return ERR_PTR(-ENOMEM
);
3992 ret
= drm_gem_object_init(dev
, &obj
->base
, size
);
3996 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3997 if (IS_CRESTLINE(dev_priv
) || IS_BROADWATER(dev_priv
)) {
3998 /* 965gm cannot relocate objects above 4GiB. */
3999 mask
&= ~__GFP_HIGHMEM
;
4000 mask
|= __GFP_DMA32
;
4003 mapping
= obj
->base
.filp
->f_mapping
;
4004 mapping_set_gfp_mask(mapping
, mask
);
4006 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4008 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4009 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4011 if (HAS_LLC(dev_priv
)) {
4012 /* On some devices, we can have the GPU use the LLC (the CPU
4013 * cache) for about a 10% performance improvement
4014 * compared to uncached. Graphics requests other than
4015 * display scanout are coherent with the CPU in
4016 * accessing this cache. This means in this mode we
4017 * don't need to clflush on the CPU side, and on the
4018 * GPU side we only need to flush internal caches to
4019 * get data visible to the CPU.
4021 * However, we maintain the display planes as UC, and so
4022 * need to rebind when first used as such.
4024 obj
->cache_level
= I915_CACHE_LLC
;
4026 obj
->cache_level
= I915_CACHE_NONE
;
4028 trace_i915_gem_object_create(obj
);
4033 i915_gem_object_free(obj
);
4034 return ERR_PTR(ret
);
4037 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4039 /* If we are the last user of the backing storage (be it shmemfs
4040 * pages or stolen etc), we know that the pages are going to be
4041 * immediately released. In this case, we can then skip copying
4042 * back the contents from the GPU.
4045 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
4048 if (obj
->base
.filp
== NULL
)
4051 /* At first glance, this looks racy, but then again so would be
4052 * userspace racing mmap against close. However, the first external
4053 * reference to the filp can only be obtained through the
4054 * i915_gem_mmap_ioctl() which safeguards us against the user
4055 * acquiring such a reference whilst we are in the middle of
4056 * freeing the object.
4058 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4061 static void __i915_gem_free_objects(struct drm_i915_private
*i915
,
4062 struct llist_node
*freed
)
4064 struct drm_i915_gem_object
*obj
, *on
;
4066 mutex_lock(&i915
->drm
.struct_mutex
);
4067 intel_runtime_pm_get(i915
);
4068 llist_for_each_entry(obj
, freed
, freed
) {
4069 struct i915_vma
*vma
, *vn
;
4071 trace_i915_gem_object_destroy(obj
);
4073 GEM_BUG_ON(i915_gem_object_is_active(obj
));
4074 list_for_each_entry_safe(vma
, vn
,
4075 &obj
->vma_list
, obj_link
) {
4076 GEM_BUG_ON(!i915_vma_is_ggtt(vma
));
4077 GEM_BUG_ON(i915_vma_is_active(vma
));
4078 vma
->flags
&= ~I915_VMA_PIN_MASK
;
4079 i915_vma_close(vma
);
4081 GEM_BUG_ON(!list_empty(&obj
->vma_list
));
4082 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj
->vma_tree
));
4084 list_del(&obj
->global_link
);
4086 intel_runtime_pm_put(i915
);
4087 mutex_unlock(&i915
->drm
.struct_mutex
);
4089 llist_for_each_entry_safe(obj
, on
, freed
, freed
) {
4090 GEM_BUG_ON(obj
->bind_count
);
4091 GEM_BUG_ON(atomic_read(&obj
->frontbuffer_bits
));
4093 if (obj
->ops
->release
)
4094 obj
->ops
->release(obj
);
4096 if (WARN_ON(i915_gem_object_has_pinned_pages(obj
)))
4097 atomic_set(&obj
->mm
.pages_pin_count
, 0);
4098 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
4099 GEM_BUG_ON(obj
->mm
.pages
);
4101 if (obj
->base
.import_attach
)
4102 drm_prime_gem_destroy(&obj
->base
, NULL
);
4104 reservation_object_fini(&obj
->__builtin_resv
);
4105 drm_gem_object_release(&obj
->base
);
4106 i915_gem_info_remove_obj(i915
, obj
->base
.size
);
4109 i915_gem_object_free(obj
);
4113 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
)
4115 struct llist_node
*freed
;
4117 freed
= llist_del_all(&i915
->mm
.free_list
);
4118 if (unlikely(freed
))
4119 __i915_gem_free_objects(i915
, freed
);
4122 static void __i915_gem_free_work(struct work_struct
*work
)
4124 struct drm_i915_private
*i915
=
4125 container_of(work
, struct drm_i915_private
, mm
.free_work
);
4126 struct llist_node
*freed
;
4128 /* All file-owned VMA should have been released by this point through
4129 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4130 * However, the object may also be bound into the global GTT (e.g.
4131 * older GPUs without per-process support, or for direct access through
4132 * the GTT either for the user or for scanout). Those VMA still need to
4136 while ((freed
= llist_del_all(&i915
->mm
.free_list
)))
4137 __i915_gem_free_objects(i915
, freed
);
4140 static void __i915_gem_free_object_rcu(struct rcu_head
*head
)
4142 struct drm_i915_gem_object
*obj
=
4143 container_of(head
, typeof(*obj
), rcu
);
4144 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
4146 /* We can't simply use call_rcu() from i915_gem_free_object()
4147 * as we need to block whilst unbinding, and the call_rcu
4148 * task may be called from softirq context. So we take a
4149 * detour through a worker.
4151 if (llist_add(&obj
->freed
, &i915
->mm
.free_list
))
4152 schedule_work(&i915
->mm
.free_work
);
4155 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4157 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4159 if (obj
->mm
.quirked
)
4160 __i915_gem_object_unpin_pages(obj
);
4162 if (discard_backing_storage(obj
))
4163 obj
->mm
.madv
= I915_MADV_DONTNEED
;
4165 /* Before we free the object, make sure any pure RCU-only
4166 * read-side critical sections are complete, e.g.
4167 * i915_gem_busy_ioctl(). For the corresponding synchronized
4168 * lookup see i915_gem_object_lookup_rcu().
4170 call_rcu(&obj
->rcu
, __i915_gem_free_object_rcu
);
4173 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object
*obj
)
4175 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
4177 GEM_BUG_ON(i915_gem_object_has_active_reference(obj
));
4178 if (i915_gem_object_is_active(obj
))
4179 i915_gem_object_set_active_reference(obj
);
4181 i915_gem_object_put(obj
);
4184 static void assert_kernel_context_is_current(struct drm_i915_private
*dev_priv
)
4186 struct intel_engine_cs
*engine
;
4187 enum intel_engine_id id
;
4189 for_each_engine(engine
, dev_priv
, id
)
4190 GEM_BUG_ON(engine
->last_context
!= dev_priv
->kernel_context
);
4193 int i915_gem_suspend(struct drm_device
*dev
)
4195 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4198 intel_suspend_gt_powersave(dev_priv
);
4200 mutex_lock(&dev
->struct_mutex
);
4202 /* We have to flush all the executing contexts to main memory so
4203 * that they can saved in the hibernation image. To ensure the last
4204 * context image is coherent, we have to switch away from it. That
4205 * leaves the dev_priv->kernel_context still active when
4206 * we actually suspend, and its image in memory may not match the GPU
4207 * state. Fortunately, the kernel_context is disposable and we do
4208 * not rely on its state.
4210 ret
= i915_gem_switch_to_kernel_context(dev_priv
);
4214 ret
= i915_gem_wait_for_idle(dev_priv
,
4215 I915_WAIT_INTERRUPTIBLE
|
4220 i915_gem_retire_requests(dev_priv
);
4221 GEM_BUG_ON(dev_priv
->gt
.active_requests
);
4223 assert_kernel_context_is_current(dev_priv
);
4224 i915_gem_context_lost(dev_priv
);
4225 mutex_unlock(&dev
->struct_mutex
);
4227 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4228 cancel_delayed_work_sync(&dev_priv
->gt
.retire_work
);
4229 flush_delayed_work(&dev_priv
->gt
.idle_work
);
4230 flush_work(&dev_priv
->mm
.free_work
);
4232 /* Assert that we sucessfully flushed all the work and
4233 * reset the GPU back to its idle, low power state.
4235 WARN_ON(dev_priv
->gt
.awake
);
4236 WARN_ON(!intel_execlists_idle(dev_priv
));
4239 * Neither the BIOS, ourselves or any other kernel
4240 * expects the system to be in execlists mode on startup,
4241 * so we need to reset the GPU back to legacy mode. And the only
4242 * known way to disable logical contexts is through a GPU reset.
4244 * So in order to leave the system in a known default configuration,
4245 * always reset the GPU upon unload and suspend. Afterwards we then
4246 * clean up the GEM state tracking, flushing off the requests and
4247 * leaving the system in a known idle state.
4249 * Note that is of the upmost importance that the GPU is idle and
4250 * all stray writes are flushed *before* we dismantle the backing
4251 * storage for the pinned objects.
4253 * However, since we are uncertain that resetting the GPU on older
4254 * machines is a good idea, we don't - just in case it leaves the
4255 * machine in an unusable condition.
4257 if (HAS_HW_CONTEXTS(dev_priv
)) {
4258 int reset
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
4259 WARN_ON(reset
&& reset
!= -ENODEV
);
4265 mutex_unlock(&dev
->struct_mutex
);
4269 void i915_gem_resume(struct drm_device
*dev
)
4271 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4273 WARN_ON(dev_priv
->gt
.awake
);
4275 mutex_lock(&dev
->struct_mutex
);
4276 i915_gem_restore_gtt_mappings(dev_priv
);
4278 /* As we didn't flush the kernel context before suspend, we cannot
4279 * guarantee that the context image is complete. So let's just reset
4280 * it and start again.
4282 dev_priv
->gt
.resume(dev_priv
);
4284 mutex_unlock(&dev
->struct_mutex
);
4287 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
)
4289 if (INTEL_GEN(dev_priv
) < 5 ||
4290 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4293 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4294 DISP_TILE_SURFACE_SWIZZLING
);
4296 if (IS_GEN5(dev_priv
))
4299 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4300 if (IS_GEN6(dev_priv
))
4301 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4302 else if (IS_GEN7(dev_priv
))
4303 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4304 else if (IS_GEN8(dev_priv
))
4305 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4310 static void init_unused_ring(struct drm_i915_private
*dev_priv
, u32 base
)
4312 I915_WRITE(RING_CTL(base
), 0);
4313 I915_WRITE(RING_HEAD(base
), 0);
4314 I915_WRITE(RING_TAIL(base
), 0);
4315 I915_WRITE(RING_START(base
), 0);
4318 static void init_unused_rings(struct drm_i915_private
*dev_priv
)
4320 if (IS_I830(dev_priv
)) {
4321 init_unused_ring(dev_priv
, PRB1_BASE
);
4322 init_unused_ring(dev_priv
, SRB0_BASE
);
4323 init_unused_ring(dev_priv
, SRB1_BASE
);
4324 init_unused_ring(dev_priv
, SRB2_BASE
);
4325 init_unused_ring(dev_priv
, SRB3_BASE
);
4326 } else if (IS_GEN2(dev_priv
)) {
4327 init_unused_ring(dev_priv
, SRB0_BASE
);
4328 init_unused_ring(dev_priv
, SRB1_BASE
);
4329 } else if (IS_GEN3(dev_priv
)) {
4330 init_unused_ring(dev_priv
, PRB1_BASE
);
4331 init_unused_ring(dev_priv
, PRB2_BASE
);
4336 i915_gem_init_hw(struct drm_device
*dev
)
4338 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4339 struct intel_engine_cs
*engine
;
4340 enum intel_engine_id id
;
4343 dev_priv
->gt
.last_init_time
= ktime_get();
4345 /* Double layer security blanket, see i915_gem_init() */
4346 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4348 if (HAS_EDRAM(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
4349 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4351 if (IS_HASWELL(dev_priv
))
4352 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev_priv
) ?
4353 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4355 if (HAS_PCH_NOP(dev_priv
)) {
4356 if (IS_IVYBRIDGE(dev_priv
)) {
4357 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4358 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4359 I915_WRITE(GEN7_MSG_CTL
, temp
);
4360 } else if (INTEL_GEN(dev_priv
) >= 7) {
4361 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4362 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4363 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4367 i915_gem_init_swizzling(dev_priv
);
4370 * At least 830 can leave some of the unused rings
4371 * "active" (ie. head != tail) after resume which
4372 * will prevent c3 entry. Makes sure all unused rings
4375 init_unused_rings(dev_priv
);
4377 BUG_ON(!dev_priv
->kernel_context
);
4379 ret
= i915_ppgtt_init_hw(dev_priv
);
4381 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4385 /* Need to do basic initialisation of all rings first: */
4386 for_each_engine(engine
, dev_priv
, id
) {
4387 ret
= engine
->init_hw(engine
);
4392 intel_mocs_init_l3cc_table(dev
);
4394 /* We can't enable contexts until all firmware is loaded */
4395 ret
= intel_guc_setup(dev
);
4400 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4404 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
)
4406 if (INTEL_INFO(dev_priv
)->gen
< 6)
4409 /* TODO: make semaphores and Execlists play nicely together */
4410 if (i915
.enable_execlists
)
4416 #ifdef CONFIG_INTEL_IOMMU
4417 /* Enable semaphores on SNB when IO remapping is off */
4418 if (INTEL_INFO(dev_priv
)->gen
== 6 && intel_iommu_gfx_mapped
)
4425 int i915_gem_init(struct drm_device
*dev
)
4427 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4430 mutex_lock(&dev
->struct_mutex
);
4432 if (!i915
.enable_execlists
) {
4433 dev_priv
->gt
.resume
= intel_legacy_submission_resume
;
4434 dev_priv
->gt
.cleanup_engine
= intel_engine_cleanup
;
4436 dev_priv
->gt
.resume
= intel_lr_context_resume
;
4437 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4440 /* This is just a security blanket to placate dragons.
4441 * On some systems, we very sporadically observe that the first TLBs
4442 * used by the CS may be stale, despite us poking the TLB reset. If
4443 * we hold the forcewake during initialisation these problems
4444 * just magically go away.
4446 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4448 i915_gem_init_userptr(dev_priv
);
4450 ret
= i915_gem_init_ggtt(dev_priv
);
4454 ret
= i915_gem_context_init(dev
);
4458 ret
= intel_engines_init(dev
);
4462 ret
= i915_gem_init_hw(dev
);
4464 /* Allow engine initialisation to fail by marking the GPU as
4465 * wedged. But we only want to do this where the GPU is angry,
4466 * for all other failure, such as an allocation failure, bail.
4468 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4469 i915_gem_set_wedged(dev_priv
);
4474 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4475 mutex_unlock(&dev
->struct_mutex
);
4481 i915_gem_cleanup_engines(struct drm_device
*dev
)
4483 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4484 struct intel_engine_cs
*engine
;
4485 enum intel_engine_id id
;
4487 for_each_engine(engine
, dev_priv
, id
)
4488 dev_priv
->gt
.cleanup_engine(engine
);
4492 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
4496 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
4497 !IS_CHERRYVIEW(dev_priv
))
4498 dev_priv
->num_fence_regs
= 32;
4499 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
4500 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
4501 dev_priv
->num_fence_regs
= 16;
4503 dev_priv
->num_fence_regs
= 8;
4505 if (intel_vgpu_active(dev_priv
))
4506 dev_priv
->num_fence_regs
=
4507 I915_READ(vgtif_reg(avail_rs
.fence_num
));
4509 /* Initialize fence registers to zero */
4510 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
4511 struct drm_i915_fence_reg
*fence
= &dev_priv
->fence_regs
[i
];
4513 fence
->i915
= dev_priv
;
4515 list_add_tail(&fence
->link
, &dev_priv
->mm
.fence_list
);
4517 i915_gem_restore_fences(dev_priv
);
4519 i915_gem_detect_bit_6_swizzle(dev_priv
);
4523 i915_gem_load_init(struct drm_device
*dev
)
4525 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4528 dev_priv
->objects
= KMEM_CACHE(drm_i915_gem_object
, SLAB_HWCACHE_ALIGN
);
4529 if (!dev_priv
->objects
)
4532 dev_priv
->vmas
= KMEM_CACHE(i915_vma
, SLAB_HWCACHE_ALIGN
);
4533 if (!dev_priv
->vmas
)
4536 dev_priv
->requests
= KMEM_CACHE(drm_i915_gem_request
,
4537 SLAB_HWCACHE_ALIGN
|
4538 SLAB_RECLAIM_ACCOUNT
|
4539 SLAB_DESTROY_BY_RCU
);
4540 if (!dev_priv
->requests
)
4543 dev_priv
->dependencies
= KMEM_CACHE(i915_dependency
,
4544 SLAB_HWCACHE_ALIGN
|
4545 SLAB_RECLAIM_ACCOUNT
);
4546 if (!dev_priv
->dependencies
)
4549 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4550 INIT_LIST_HEAD(&dev_priv
->gt
.timelines
);
4551 err
= i915_gem_timeline_init__global(dev_priv
);
4552 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4554 goto err_dependencies
;
4556 INIT_LIST_HEAD(&dev_priv
->context_list
);
4557 INIT_WORK(&dev_priv
->mm
.free_work
, __i915_gem_free_work
);
4558 init_llist_head(&dev_priv
->mm
.free_list
);
4559 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4560 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4561 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4562 INIT_LIST_HEAD(&dev_priv
->mm
.userfault_list
);
4563 INIT_DELAYED_WORK(&dev_priv
->gt
.retire_work
,
4564 i915_gem_retire_work_handler
);
4565 INIT_DELAYED_WORK(&dev_priv
->gt
.idle_work
,
4566 i915_gem_idle_work_handler
);
4567 init_waitqueue_head(&dev_priv
->gpu_error
.wait_queue
);
4568 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4570 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4572 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4574 dev_priv
->mm
.interruptible
= true;
4576 atomic_set(&dev_priv
->mm
.bsd_engine_dispatch_index
, 0);
4578 spin_lock_init(&dev_priv
->fb_tracking
.lock
);
4583 kmem_cache_destroy(dev_priv
->dependencies
);
4585 kmem_cache_destroy(dev_priv
->requests
);
4587 kmem_cache_destroy(dev_priv
->vmas
);
4589 kmem_cache_destroy(dev_priv
->objects
);
4594 void i915_gem_load_cleanup(struct drm_device
*dev
)
4596 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4598 WARN_ON(!llist_empty(&dev_priv
->mm
.free_list
));
4600 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4601 i915_gem_timeline_fini(&dev_priv
->gt
.global_timeline
);
4602 WARN_ON(!list_empty(&dev_priv
->gt
.timelines
));
4603 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4605 kmem_cache_destroy(dev_priv
->dependencies
);
4606 kmem_cache_destroy(dev_priv
->requests
);
4607 kmem_cache_destroy(dev_priv
->vmas
);
4608 kmem_cache_destroy(dev_priv
->objects
);
4610 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4614 int i915_gem_freeze(struct drm_i915_private
*dev_priv
)
4616 intel_runtime_pm_get(dev_priv
);
4618 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4619 i915_gem_shrink_all(dev_priv
);
4620 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4622 intel_runtime_pm_put(dev_priv
);
4627 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
4629 struct drm_i915_gem_object
*obj
;
4630 struct list_head
*phases
[] = {
4631 &dev_priv
->mm
.unbound_list
,
4632 &dev_priv
->mm
.bound_list
,
4636 /* Called just before we write the hibernation image.
4638 * We need to update the domain tracking to reflect that the CPU
4639 * will be accessing all the pages to create and restore from the
4640 * hibernation, and so upon restoration those pages will be in the
4643 * To make sure the hibernation image contains the latest state,
4644 * we update that state just before writing out the image.
4646 * To try and reduce the hibernation image, we manually shrink
4647 * the objects as well.
4650 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4651 i915_gem_shrink(dev_priv
, -1UL, I915_SHRINK_UNBOUND
);
4653 for (p
= phases
; *p
; p
++) {
4654 list_for_each_entry(obj
, *p
, global_link
) {
4655 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4656 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4659 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4664 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4666 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4667 struct drm_i915_gem_request
*request
;
4669 /* Clean up our request list when the client is going away, so that
4670 * later retire_requests won't dereference our soon-to-be-gone
4673 spin_lock(&file_priv
->mm
.lock
);
4674 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
)
4675 request
->file_priv
= NULL
;
4676 spin_unlock(&file_priv
->mm
.lock
);
4678 if (!list_empty(&file_priv
->rps
.link
)) {
4679 spin_lock(&to_i915(dev
)->rps
.client_lock
);
4680 list_del(&file_priv
->rps
.link
);
4681 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
4685 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4687 struct drm_i915_file_private
*file_priv
;
4692 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4696 file
->driver_priv
= file_priv
;
4697 file_priv
->dev_priv
= to_i915(dev
);
4698 file_priv
->file
= file
;
4699 INIT_LIST_HEAD(&file_priv
->rps
.link
);
4701 spin_lock_init(&file_priv
->mm
.lock
);
4702 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4704 file_priv
->bsd_engine
= -1;
4706 ret
= i915_gem_context_open(dev
, file
);
4714 * i915_gem_track_fb - update frontbuffer tracking
4715 * @old: current GEM buffer for the frontbuffer slots
4716 * @new: new GEM buffer for the frontbuffer slots
4717 * @frontbuffer_bits: bitmask of frontbuffer slots
4719 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4720 * from @old and setting them in @new. Both @old and @new can be NULL.
4722 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
4723 struct drm_i915_gem_object
*new,
4724 unsigned frontbuffer_bits
)
4726 /* Control of individual bits within the mask are guarded by
4727 * the owning plane->mutex, i.e. we can never see concurrent
4728 * manipulation of individual bits. But since the bitfield as a whole
4729 * is updated using RMW, we need to use atomics in order to update
4732 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE
* I915_MAX_PIPES
>
4733 sizeof(atomic_t
) * BITS_PER_BYTE
);
4736 WARN_ON(!(atomic_read(&old
->frontbuffer_bits
) & frontbuffer_bits
));
4737 atomic_andnot(frontbuffer_bits
, &old
->frontbuffer_bits
);
4741 WARN_ON(atomic_read(&new->frontbuffer_bits
) & frontbuffer_bits
);
4742 atomic_or(frontbuffer_bits
, &new->frontbuffer_bits
);
4746 /* Allocate a new GEM object and fill it with the supplied data */
4747 struct drm_i915_gem_object
*
4748 i915_gem_object_create_from_data(struct drm_device
*dev
,
4749 const void *data
, size_t size
)
4751 struct drm_i915_gem_object
*obj
;
4752 struct sg_table
*sg
;
4756 obj
= i915_gem_object_create(dev
, round_up(size
, PAGE_SIZE
));
4760 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
4764 ret
= i915_gem_object_pin_pages(obj
);
4769 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
4770 obj
->mm
.dirty
= true; /* Backing store is now out of date */
4771 i915_gem_object_unpin_pages(obj
);
4773 if (WARN_ON(bytes
!= size
)) {
4774 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
4782 i915_gem_object_put(obj
);
4783 return ERR_PTR(ret
);
4786 struct scatterlist
*
4787 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
4789 unsigned int *offset
)
4791 struct i915_gem_object_page_iter
*iter
= &obj
->mm
.get_page
;
4792 struct scatterlist
*sg
;
4793 unsigned int idx
, count
;
4796 GEM_BUG_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
);
4797 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
4799 /* As we iterate forward through the sg, we record each entry in a
4800 * radixtree for quick repeated (backwards) lookups. If we have seen
4801 * this index previously, we will have an entry for it.
4803 * Initial lookup is O(N), but this is amortized to O(1) for
4804 * sequential page access (where each new request is consecutive
4805 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4806 * i.e. O(1) with a large constant!
4808 if (n
< READ_ONCE(iter
->sg_idx
))
4811 mutex_lock(&iter
->lock
);
4813 /* We prefer to reuse the last sg so that repeated lookup of this
4814 * (or the subsequent) sg are fast - comparing against the last
4815 * sg is faster than going through the radixtree.
4820 count
= __sg_page_count(sg
);
4822 while (idx
+ count
<= n
) {
4823 unsigned long exception
, i
;
4826 /* If we cannot allocate and insert this entry, or the
4827 * individual pages from this range, cancel updating the
4828 * sg_idx so that on this lookup we are forced to linearly
4829 * scan onwards, but on future lookups we will try the
4830 * insertion again (in which case we need to be careful of
4831 * the error return reporting that we have already inserted
4834 ret
= radix_tree_insert(&iter
->radix
, idx
, sg
);
4835 if (ret
&& ret
!= -EEXIST
)
4839 RADIX_TREE_EXCEPTIONAL_ENTRY
|
4840 idx
<< RADIX_TREE_EXCEPTIONAL_SHIFT
;
4841 for (i
= 1; i
< count
; i
++) {
4842 ret
= radix_tree_insert(&iter
->radix
, idx
+ i
,
4844 if (ret
&& ret
!= -EEXIST
)
4849 sg
= ____sg_next(sg
);
4850 count
= __sg_page_count(sg
);
4857 mutex_unlock(&iter
->lock
);
4859 if (unlikely(n
< idx
)) /* insertion completed by another thread */
4862 /* In case we failed to insert the entry into the radixtree, we need
4863 * to look beyond the current sg.
4865 while (idx
+ count
<= n
) {
4867 sg
= ____sg_next(sg
);
4868 count
= __sg_page_count(sg
);
4877 sg
= radix_tree_lookup(&iter
->radix
, n
);
4880 /* If this index is in the middle of multi-page sg entry,
4881 * the radixtree will contain an exceptional entry that points
4882 * to the start of that range. We will return the pointer to
4883 * the base page and the offset of this page within the
4887 if (unlikely(radix_tree_exception(sg
))) {
4888 unsigned long base
=
4889 (unsigned long)sg
>> RADIX_TREE_EXCEPTIONAL_SHIFT
;
4891 sg
= radix_tree_lookup(&iter
->radix
, base
);
4903 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, unsigned int n
)
4905 struct scatterlist
*sg
;
4906 unsigned int offset
;
4908 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
4910 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
4911 return nth_page(sg_page(sg
), offset
);
4914 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
4916 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
4921 page
= i915_gem_object_get_page(obj
, n
);
4923 set_page_dirty(page
);
4929 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
4932 struct scatterlist
*sg
;
4933 unsigned int offset
;
4935 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
4936 return sg_dma_address(sg
) + (offset
<< PAGE_SHIFT
);