2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
39 static __must_check
int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
44 bool map_and_fenceable
);
45 static void i915_gem_clear_fence_reg(struct drm_device
*dev
,
46 struct drm_i915_fence_reg
*reg
);
47 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
48 struct drm_i915_gem_object
*obj
,
49 struct drm_i915_gem_pwrite
*args
,
50 struct drm_file
*file
);
51 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
);
53 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
54 struct shrink_control
*sc
);
55 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
57 /* some bookkeeping */
58 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
61 dev_priv
->mm
.object_count
++;
62 dev_priv
->mm
.object_memory
+= size
;
65 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
68 dev_priv
->mm
.object_count
--;
69 dev_priv
->mm
.object_memory
-= size
;
73 i915_gem_wait_for_error(struct drm_device
*dev
)
75 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 struct completion
*x
= &dev_priv
->error_completion
;
80 if (!atomic_read(&dev_priv
->mm
.wedged
))
83 ret
= wait_for_completion_interruptible(x
);
87 if (atomic_read(&dev_priv
->mm
.wedged
)) {
88 /* GPU is hung, bump the completion count to account for
89 * the token we just consumed so that we never hit zero and
90 * end up waiting upon a subsequent completion event that
93 spin_lock_irqsave(&x
->wait
.lock
, flags
);
95 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
100 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
104 ret
= i915_gem_wait_for_error(dev
);
108 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
112 WARN_ON(i915_verify_lists(dev
));
117 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
119 return obj
->gtt_space
&& !obj
->active
&& obj
->pin_count
== 0;
123 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
124 struct drm_file
*file
)
126 struct drm_i915_gem_init
*args
= data
;
128 if (args
->gtt_start
>= args
->gtt_end
||
129 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
132 /* GEM with user mode setting was never supported on ilk and later. */
133 if (INTEL_INFO(dev
)->gen
>= 5)
136 mutex_lock(&dev
->struct_mutex
);
137 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
138 args
->gtt_end
, args
->gtt_end
);
139 mutex_unlock(&dev
->struct_mutex
);
145 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
146 struct drm_file
*file
)
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 struct drm_i915_gem_get_aperture
*args
= data
;
150 struct drm_i915_gem_object
*obj
;
153 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
157 mutex_lock(&dev
->struct_mutex
);
158 list_for_each_entry(obj
, &dev_priv
->mm
.pinned_list
, mm_list
)
159 pinned
+= obj
->gtt_space
->size
;
160 mutex_unlock(&dev
->struct_mutex
);
162 args
->aper_size
= dev_priv
->mm
.gtt_total
;
163 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_create(struct drm_file
*file
,
170 struct drm_device
*dev
,
174 struct drm_i915_gem_object
*obj
;
178 size
= roundup(size
, PAGE_SIZE
);
182 /* Allocate the new object */
183 obj
= i915_gem_alloc_object(dev
, size
);
187 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
189 drm_gem_object_release(&obj
->base
);
190 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
195 /* drop reference from allocate - handle holds it now */
196 drm_gem_object_unreference(&obj
->base
);
197 trace_i915_gem_object_create(obj
);
204 i915_gem_dumb_create(struct drm_file
*file
,
205 struct drm_device
*dev
,
206 struct drm_mode_create_dumb
*args
)
208 /* have to work out size/pitch and return them */
209 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
210 args
->size
= args
->pitch
* args
->height
;
211 return i915_gem_create(file
, dev
,
212 args
->size
, &args
->handle
);
215 int i915_gem_dumb_destroy(struct drm_file
*file
,
216 struct drm_device
*dev
,
219 return drm_gem_handle_delete(file
, handle
);
223 * Creates a new mm object and returns a handle to it.
226 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
227 struct drm_file
*file
)
229 struct drm_i915_gem_create
*args
= data
;
230 return i915_gem_create(file
, dev
,
231 args
->size
, &args
->handle
);
234 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
236 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
238 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
239 obj
->tiling_mode
!= I915_TILING_NONE
;
243 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
244 const char *gpu_vaddr
, int gpu_offset
,
247 int ret
, cpu_offset
= 0;
250 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
251 int this_length
= min(cacheline_end
- gpu_offset
, length
);
252 int swizzled_gpu_offset
= gpu_offset
^ 64;
254 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
255 gpu_vaddr
+ swizzled_gpu_offset
,
260 cpu_offset
+= this_length
;
261 gpu_offset
+= this_length
;
262 length
-= this_length
;
269 __copy_from_user_swizzled(char __user
*gpu_vaddr
, int gpu_offset
,
270 const char *cpu_vaddr
,
273 int ret
, cpu_offset
= 0;
276 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
277 int this_length
= min(cacheline_end
- gpu_offset
, length
);
278 int swizzled_gpu_offset
= gpu_offset
^ 64;
280 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
281 cpu_vaddr
+ cpu_offset
,
286 cpu_offset
+= this_length
;
287 gpu_offset
+= this_length
;
288 length
-= this_length
;
294 /* Per-page copy function for the shmem pread fastpath.
295 * Flushes invalid cachelines before reading the target if
296 * needs_clflush is set. */
298 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
299 char __user
*user_data
,
300 bool page_do_bit17_swizzling
, bool needs_clflush
)
305 if (unlikely(page_do_bit17_swizzling
))
308 vaddr
= kmap_atomic(page
);
310 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
312 ret
= __copy_to_user_inatomic(user_data
,
313 vaddr
+ shmem_page_offset
,
315 kunmap_atomic(vaddr
);
321 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
324 if (unlikely(swizzled
)) {
325 unsigned long start
= (unsigned long) addr
;
326 unsigned long end
= (unsigned long) addr
+ length
;
328 /* For swizzling simply ensure that we always flush both
329 * channels. Lame, but simple and it works. Swizzled
330 * pwrite/pread is far from a hotpath - current userspace
331 * doesn't use it at all. */
332 start
= round_down(start
, 128);
333 end
= round_up(end
, 128);
335 drm_clflush_virt_range((void *)start
, end
- start
);
337 drm_clflush_virt_range(addr
, length
);
342 /* Only difference to the fast-path function is that this can handle bit17
343 * and uses non-atomic copy and kmap functions. */
345 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
346 char __user
*user_data
,
347 bool page_do_bit17_swizzling
, bool needs_clflush
)
354 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
356 page_do_bit17_swizzling
);
358 if (page_do_bit17_swizzling
)
359 ret
= __copy_to_user_swizzled(user_data
,
360 vaddr
, shmem_page_offset
,
363 ret
= __copy_to_user(user_data
,
364 vaddr
+ shmem_page_offset
,
372 i915_gem_shmem_pread(struct drm_device
*dev
,
373 struct drm_i915_gem_object
*obj
,
374 struct drm_i915_gem_pread
*args
,
375 struct drm_file
*file
)
377 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
378 char __user
*user_data
;
381 int shmem_page_offset
, page_length
, ret
= 0;
382 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
383 int hit_slowpath
= 0;
385 int needs_clflush
= 0;
388 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
391 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
393 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
394 /* If we're not in the cpu read domain, set ourself into the gtt
395 * read domain and manually flush cachelines (if required). This
396 * optimizes for the case when the gpu will dirty the data
397 * anyway again before the next pread happens. */
398 if (obj
->cache_level
== I915_CACHE_NONE
)
400 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
405 offset
= args
->offset
;
410 /* Operation in this page
412 * shmem_page_offset = offset within page in shmem file
413 * page_length = bytes to copy for this page
415 shmem_page_offset
= offset_in_page(offset
);
416 page_length
= remain
;
417 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
418 page_length
= PAGE_SIZE
- shmem_page_offset
;
421 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
424 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
432 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
433 (page_to_phys(page
) & (1 << 17)) != 0;
435 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
436 user_data
, page_do_bit17_swizzling
,
442 page_cache_get(page
);
443 mutex_unlock(&dev
->struct_mutex
);
446 ret
= fault_in_multipages_writeable(user_data
, remain
);
447 /* Userspace is tricking us, but we've already clobbered
448 * its pages with the prefault and promised to write the
449 * data up to the first fault. Hence ignore any errors
450 * and just continue. */
455 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
456 user_data
, page_do_bit17_swizzling
,
459 mutex_lock(&dev
->struct_mutex
);
460 page_cache_release(page
);
462 mark_page_accessed(page
);
464 page_cache_release(page
);
471 remain
-= page_length
;
472 user_data
+= page_length
;
473 offset
+= page_length
;
478 /* Fixup: Kill any reinstated backing storage pages */
479 if (obj
->madv
== __I915_MADV_PURGED
)
480 i915_gem_object_truncate(obj
);
487 * Reads data from the object referenced by handle.
489 * On error, the contents of *data are undefined.
492 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
493 struct drm_file
*file
)
495 struct drm_i915_gem_pread
*args
= data
;
496 struct drm_i915_gem_object
*obj
;
502 if (!access_ok(VERIFY_WRITE
,
503 (char __user
*)(uintptr_t)args
->data_ptr
,
507 ret
= i915_mutex_lock_interruptible(dev
);
511 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
512 if (&obj
->base
== NULL
) {
517 /* Bounds check source. */
518 if (args
->offset
> obj
->base
.size
||
519 args
->size
> obj
->base
.size
- args
->offset
) {
524 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
526 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
529 drm_gem_object_unreference(&obj
->base
);
531 mutex_unlock(&dev
->struct_mutex
);
535 /* This is the fast write path which cannot handle
536 * page faults in the source data
540 fast_user_write(struct io_mapping
*mapping
,
541 loff_t page_base
, int page_offset
,
542 char __user
*user_data
,
546 unsigned long unwritten
;
548 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
549 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
551 io_mapping_unmap_atomic(vaddr_atomic
);
556 * This is the fast pwrite path, where we copy the data directly from the
557 * user into the GTT, uncached.
560 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
561 struct drm_i915_gem_object
*obj
,
562 struct drm_i915_gem_pwrite
*args
,
563 struct drm_file
*file
)
565 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
567 loff_t offset
, page_base
;
568 char __user
*user_data
;
569 int page_offset
, page_length
, ret
;
571 ret
= i915_gem_object_pin(obj
, 0, true);
575 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
579 ret
= i915_gem_object_put_fence(obj
);
583 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
586 offset
= obj
->gtt_offset
+ args
->offset
;
589 /* Operation in this page
591 * page_base = page offset within aperture
592 * page_offset = offset within page
593 * page_length = bytes to copy for this page
595 page_base
= offset
& PAGE_MASK
;
596 page_offset
= offset_in_page(offset
);
597 page_length
= remain
;
598 if ((page_offset
+ remain
) > PAGE_SIZE
)
599 page_length
= PAGE_SIZE
- page_offset
;
601 /* If we get a fault while copying data, then (presumably) our
602 * source page isn't available. Return the error and we'll
603 * retry in the slow path.
605 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
606 page_offset
, user_data
, page_length
)) {
611 remain
-= page_length
;
612 user_data
+= page_length
;
613 offset
+= page_length
;
617 i915_gem_object_unpin(obj
);
622 /* Per-page copy function for the shmem pwrite fastpath.
623 * Flushes invalid cachelines before writing to the target if
624 * needs_clflush_before is set and flushes out any written cachelines after
625 * writing if needs_clflush is set. */
627 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
628 char __user
*user_data
,
629 bool page_do_bit17_swizzling
,
630 bool needs_clflush_before
,
631 bool needs_clflush_after
)
636 if (unlikely(page_do_bit17_swizzling
))
639 vaddr
= kmap_atomic(page
);
640 if (needs_clflush_before
)
641 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
643 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
646 if (needs_clflush_after
)
647 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
649 kunmap_atomic(vaddr
);
654 /* Only difference to the fast-path function is that this can handle bit17
655 * and uses non-atomic copy and kmap functions. */
657 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
658 char __user
*user_data
,
659 bool page_do_bit17_swizzling
,
660 bool needs_clflush_before
,
661 bool needs_clflush_after
)
667 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
668 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
670 page_do_bit17_swizzling
);
671 if (page_do_bit17_swizzling
)
672 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
676 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
679 if (needs_clflush_after
)
680 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
682 page_do_bit17_swizzling
);
689 i915_gem_shmem_pwrite(struct drm_device
*dev
,
690 struct drm_i915_gem_object
*obj
,
691 struct drm_i915_gem_pwrite
*args
,
692 struct drm_file
*file
)
694 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
697 char __user
*user_data
;
698 int shmem_page_offset
, page_length
, ret
= 0;
699 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
700 int hit_slowpath
= 0;
701 int needs_clflush_after
= 0;
702 int needs_clflush_before
= 0;
705 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
708 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
710 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
711 /* If we're not in the cpu write domain, set ourself into the gtt
712 * write domain and manually flush cachelines (if required). This
713 * optimizes for the case when the gpu will use the data
714 * right away and we therefore have to clflush anyway. */
715 if (obj
->cache_level
== I915_CACHE_NONE
)
716 needs_clflush_after
= 1;
717 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
721 /* Same trick applies for invalidate partially written cachelines before
723 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
724 && obj
->cache_level
== I915_CACHE_NONE
)
725 needs_clflush_before
= 1;
727 offset
= args
->offset
;
732 int partial_cacheline_write
;
734 /* Operation in this page
736 * shmem_page_offset = offset within page in shmem file
737 * page_length = bytes to copy for this page
739 shmem_page_offset
= offset_in_page(offset
);
741 page_length
= remain
;
742 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
743 page_length
= PAGE_SIZE
- shmem_page_offset
;
745 /* If we don't overwrite a cacheline completely we need to be
746 * careful to have up-to-date data by first clflushing. Don't
747 * overcomplicate things and flush the entire patch. */
748 partial_cacheline_write
= needs_clflush_before
&&
749 ((shmem_page_offset
| page_length
)
750 & (boot_cpu_data
.x86_clflush_size
- 1));
753 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
756 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
764 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
765 (page_to_phys(page
) & (1 << 17)) != 0;
767 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
768 user_data
, page_do_bit17_swizzling
,
769 partial_cacheline_write
,
770 needs_clflush_after
);
775 page_cache_get(page
);
776 mutex_unlock(&dev
->struct_mutex
);
778 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
779 user_data
, page_do_bit17_swizzling
,
780 partial_cacheline_write
,
781 needs_clflush_after
);
783 mutex_lock(&dev
->struct_mutex
);
784 page_cache_release(page
);
786 set_page_dirty(page
);
787 mark_page_accessed(page
);
789 page_cache_release(page
);
796 remain
-= page_length
;
797 user_data
+= page_length
;
798 offset
+= page_length
;
803 /* Fixup: Kill any reinstated backing storage pages */
804 if (obj
->madv
== __I915_MADV_PURGED
)
805 i915_gem_object_truncate(obj
);
806 /* and flush dirty cachelines in case the object isn't in the cpu write
808 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
809 i915_gem_clflush_object(obj
);
810 intel_gtt_chipset_flush();
814 if (needs_clflush_after
)
815 intel_gtt_chipset_flush();
821 * Writes data to the object referenced by handle.
823 * On error, the contents of the buffer that were to be modified are undefined.
826 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
827 struct drm_file
*file
)
829 struct drm_i915_gem_pwrite
*args
= data
;
830 struct drm_i915_gem_object
*obj
;
836 if (!access_ok(VERIFY_READ
,
837 (char __user
*)(uintptr_t)args
->data_ptr
,
841 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
846 ret
= i915_mutex_lock_interruptible(dev
);
850 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
851 if (&obj
->base
== NULL
) {
856 /* Bounds check destination. */
857 if (args
->offset
> obj
->base
.size
||
858 args
->size
> obj
->base
.size
- args
->offset
) {
863 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
866 /* We can only do the GTT pwrite on untiled buffers, as otherwise
867 * it would end up going through the fenced access, and we'll get
868 * different detiling behavior between reading and writing.
869 * pread/pwrite currently are reading and writing from the CPU
870 * perspective, requiring manual detiling by the client.
873 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
877 if (obj
->gtt_space
&&
878 obj
->cache_level
== I915_CACHE_NONE
&&
879 obj
->tiling_mode
== I915_TILING_NONE
&&
880 obj
->map_and_fenceable
&&
881 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
882 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
883 /* Note that the gtt paths might fail with non-page-backed user
884 * pointers (e.g. gtt mappings when moving data between
885 * textures). Fallback to the shmem path in that case. */
889 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
892 drm_gem_object_unreference(&obj
->base
);
894 mutex_unlock(&dev
->struct_mutex
);
899 * Called when user space prepares to use an object with the CPU, either
900 * through the mmap ioctl's mapping or a GTT mapping.
903 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
904 struct drm_file
*file
)
906 struct drm_i915_gem_set_domain
*args
= data
;
907 struct drm_i915_gem_object
*obj
;
908 uint32_t read_domains
= args
->read_domains
;
909 uint32_t write_domain
= args
->write_domain
;
912 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
915 /* Only handle setting domains to types used by the CPU. */
916 if (write_domain
& I915_GEM_GPU_DOMAINS
)
919 if (read_domains
& I915_GEM_GPU_DOMAINS
)
922 /* Having something in the write domain implies it's in the read
923 * domain, and only that read domain. Enforce that in the request.
925 if (write_domain
!= 0 && read_domains
!= write_domain
)
928 ret
= i915_mutex_lock_interruptible(dev
);
932 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
933 if (&obj
->base
== NULL
) {
938 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
939 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
941 /* Silently promote "you're not bound, there was nothing to do"
942 * to success, since the client was just asking us to
943 * make sure everything was done.
948 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
951 drm_gem_object_unreference(&obj
->base
);
953 mutex_unlock(&dev
->struct_mutex
);
958 * Called when user space has done writes to this buffer
961 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
962 struct drm_file
*file
)
964 struct drm_i915_gem_sw_finish
*args
= data
;
965 struct drm_i915_gem_object
*obj
;
968 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
971 ret
= i915_mutex_lock_interruptible(dev
);
975 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
976 if (&obj
->base
== NULL
) {
981 /* Pinned buffers may be scanout, so flush the cache */
983 i915_gem_object_flush_cpu_write_domain(obj
);
985 drm_gem_object_unreference(&obj
->base
);
987 mutex_unlock(&dev
->struct_mutex
);
992 * Maps the contents of an object, returning the address it is mapped
995 * While the mapping holds a reference on the contents of the object, it doesn't
996 * imply a ref on the object itself.
999 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1000 struct drm_file
*file
)
1002 struct drm_i915_gem_mmap
*args
= data
;
1003 struct drm_gem_object
*obj
;
1006 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1009 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1013 down_write(¤t
->mm
->mmap_sem
);
1014 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1015 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1017 up_write(¤t
->mm
->mmap_sem
);
1018 drm_gem_object_unreference_unlocked(obj
);
1019 if (IS_ERR((void *)addr
))
1022 args
->addr_ptr
= (uint64_t) addr
;
1028 * i915_gem_fault - fault a page into the GTT
1029 * vma: VMA in question
1032 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1033 * from userspace. The fault handler takes care of binding the object to
1034 * the GTT (if needed), allocating and programming a fence register (again,
1035 * only if needed based on whether the old reg is still valid or the object
1036 * is tiled) and inserting a new PTE into the faulting process.
1038 * Note that the faulting process may involve evicting existing objects
1039 * from the GTT and/or fence registers to make room. So performance may
1040 * suffer if the GTT working set is large or there are few fence registers
1043 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1045 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1046 struct drm_device
*dev
= obj
->base
.dev
;
1047 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1048 pgoff_t page_offset
;
1051 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1053 /* We don't use vmf->pgoff since that has the fake offset */
1054 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1057 ret
= i915_mutex_lock_interruptible(dev
);
1061 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1063 /* Now bind it into the GTT if needed */
1064 if (!obj
->map_and_fenceable
) {
1065 ret
= i915_gem_object_unbind(obj
);
1069 if (!obj
->gtt_space
) {
1070 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1074 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1079 if (!obj
->has_global_gtt_mapping
)
1080 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
1082 ret
= i915_gem_object_get_fence(obj
);
1086 if (i915_gem_object_is_inactive(obj
))
1087 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1089 obj
->fault_mappable
= true;
1091 pfn
= ((dev
->agp
->base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1094 /* Finally, remap it using the new GTT offset */
1095 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1097 mutex_unlock(&dev
->struct_mutex
);
1102 /* Give the error handler a chance to run and move the
1103 * objects off the GPU active list. Next time we service the
1104 * fault, we should be able to transition the page into the
1105 * GTT without touching the GPU (and so avoid further
1106 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1107 * with coherency, just lost writes.
1113 return VM_FAULT_NOPAGE
;
1115 return VM_FAULT_OOM
;
1117 return VM_FAULT_SIGBUS
;
1122 * i915_gem_release_mmap - remove physical page mappings
1123 * @obj: obj in question
1125 * Preserve the reservation of the mmapping with the DRM core code, but
1126 * relinquish ownership of the pages back to the system.
1128 * It is vital that we remove the page mapping if we have mapped a tiled
1129 * object through the GTT and then lose the fence register due to
1130 * resource pressure. Similarly if the object has been moved out of the
1131 * aperture, than pages mapped into userspace must be revoked. Removing the
1132 * mapping will then trigger a page fault on the next user access, allowing
1133 * fixup by i915_gem_fault().
1136 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1138 if (!obj
->fault_mappable
)
1141 if (obj
->base
.dev
->dev_mapping
)
1142 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1143 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1146 obj
->fault_mappable
= false;
1150 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1154 if (INTEL_INFO(dev
)->gen
>= 4 ||
1155 tiling_mode
== I915_TILING_NONE
)
1158 /* Previous chips need a power-of-two fence region when tiling */
1159 if (INTEL_INFO(dev
)->gen
== 3)
1160 gtt_size
= 1024*1024;
1162 gtt_size
= 512*1024;
1164 while (gtt_size
< size
)
1171 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1172 * @obj: object to check
1174 * Return the required GTT alignment for an object, taking into account
1175 * potential fence register mapping.
1178 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1183 * Minimum alignment is 4k (GTT page size), but might be greater
1184 * if a fence register is needed for the object.
1186 if (INTEL_INFO(dev
)->gen
>= 4 ||
1187 tiling_mode
== I915_TILING_NONE
)
1191 * Previous chips need to be aligned to the size of the smallest
1192 * fence register that can contain the object.
1194 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1198 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1201 * @size: size of the object
1202 * @tiling_mode: tiling mode of the object
1204 * Return the required GTT alignment for an object, only taking into account
1205 * unfenced tiled surface requirements.
1208 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1213 * Minimum alignment is 4k (GTT page size) for sane hw.
1215 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1216 tiling_mode
== I915_TILING_NONE
)
1219 /* Previous hardware however needs to be aligned to a power-of-two
1220 * tile height. The simplest method for determining this is to reuse
1221 * the power-of-tile object size.
1223 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1227 i915_gem_mmap_gtt(struct drm_file
*file
,
1228 struct drm_device
*dev
,
1232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1233 struct drm_i915_gem_object
*obj
;
1236 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1239 ret
= i915_mutex_lock_interruptible(dev
);
1243 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1244 if (&obj
->base
== NULL
) {
1249 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1254 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1255 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1260 if (!obj
->base
.map_list
.map
) {
1261 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1266 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1269 drm_gem_object_unreference(&obj
->base
);
1271 mutex_unlock(&dev
->struct_mutex
);
1276 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1278 * @data: GTT mapping ioctl data
1279 * @file: GEM object info
1281 * Simply returns the fake offset to userspace so it can mmap it.
1282 * The mmap call will end up in drm_gem_mmap(), which will set things
1283 * up so we can get faults in the handler above.
1285 * The fault handler will take care of binding the object into the GTT
1286 * (since it may have been evicted to make room for something), allocating
1287 * a fence register, and mapping the appropriate aperture address into
1291 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1292 struct drm_file
*file
)
1294 struct drm_i915_gem_mmap_gtt
*args
= data
;
1296 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1299 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1304 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1308 struct address_space
*mapping
;
1309 struct inode
*inode
;
1312 /* Get the list of pages out of our struct file. They'll be pinned
1313 * at this point until we release them.
1315 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1316 BUG_ON(obj
->pages
!= NULL
);
1317 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1318 if (obj
->pages
== NULL
)
1321 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1322 mapping
= inode
->i_mapping
;
1323 gfpmask
|= mapping_gfp_mask(mapping
);
1325 for (i
= 0; i
< page_count
; i
++) {
1326 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfpmask
);
1330 obj
->pages
[i
] = page
;
1333 if (i915_gem_object_needs_bit17_swizzle(obj
))
1334 i915_gem_object_do_bit_17_swizzle(obj
);
1340 page_cache_release(obj
->pages
[i
]);
1342 drm_free_large(obj
->pages
);
1344 return PTR_ERR(page
);
1348 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1350 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1353 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1355 if (i915_gem_object_needs_bit17_swizzle(obj
))
1356 i915_gem_object_save_bit_17_swizzle(obj
);
1358 if (obj
->madv
== I915_MADV_DONTNEED
)
1361 for (i
= 0; i
< page_count
; i
++) {
1363 set_page_dirty(obj
->pages
[i
]);
1365 if (obj
->madv
== I915_MADV_WILLNEED
)
1366 mark_page_accessed(obj
->pages
[i
]);
1368 page_cache_release(obj
->pages
[i
]);
1372 drm_free_large(obj
->pages
);
1377 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1378 struct intel_ring_buffer
*ring
,
1381 struct drm_device
*dev
= obj
->base
.dev
;
1382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1384 BUG_ON(ring
== NULL
);
1387 /* Add a reference if we're newly entering the active list. */
1389 drm_gem_object_reference(&obj
->base
);
1393 /* Move from whatever list we were on to the tail of execution. */
1394 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1395 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1397 obj
->last_rendering_seqno
= seqno
;
1399 if (obj
->fenced_gpu_access
) {
1400 obj
->last_fenced_seqno
= seqno
;
1401 obj
->last_fenced_ring
= ring
;
1403 /* Bump MRU to take account of the delayed flush */
1404 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1405 struct drm_i915_fence_reg
*reg
;
1407 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1408 list_move_tail(®
->lru_list
,
1409 &dev_priv
->mm
.fence_list
);
1415 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1417 list_del_init(&obj
->ring_list
);
1418 obj
->last_rendering_seqno
= 0;
1419 obj
->last_fenced_seqno
= 0;
1423 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1425 struct drm_device
*dev
= obj
->base
.dev
;
1426 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1428 BUG_ON(!obj
->active
);
1429 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1431 i915_gem_object_move_off_active(obj
);
1435 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1437 struct drm_device
*dev
= obj
->base
.dev
;
1438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1440 if (obj
->pin_count
!= 0)
1441 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.pinned_list
);
1443 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1445 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1446 BUG_ON(!obj
->active
);
1448 obj
->last_fenced_ring
= NULL
;
1450 i915_gem_object_move_off_active(obj
);
1451 obj
->fenced_gpu_access
= false;
1454 obj
->pending_gpu_write
= false;
1455 drm_gem_object_unreference(&obj
->base
);
1457 WARN_ON(i915_verify_lists(dev
));
1460 /* Immediately discard the backing storage */
1462 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1464 struct inode
*inode
;
1466 /* Our goal here is to return as much of the memory as
1467 * is possible back to the system as we are called from OOM.
1468 * To do this we must instruct the shmfs to drop all of its
1469 * backing pages, *now*.
1471 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1472 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1474 if (obj
->base
.map_list
.map
)
1475 drm_gem_free_mmap_offset(&obj
->base
);
1477 obj
->madv
= __I915_MADV_PURGED
;
1481 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1483 return obj
->madv
== I915_MADV_DONTNEED
;
1487 i915_gem_process_flushing_list(struct intel_ring_buffer
*ring
,
1488 uint32_t flush_domains
)
1490 struct drm_i915_gem_object
*obj
, *next
;
1492 list_for_each_entry_safe(obj
, next
,
1493 &ring
->gpu_write_list
,
1495 if (obj
->base
.write_domain
& flush_domains
) {
1496 uint32_t old_write_domain
= obj
->base
.write_domain
;
1498 obj
->base
.write_domain
= 0;
1499 list_del_init(&obj
->gpu_write_list
);
1500 i915_gem_object_move_to_active(obj
, ring
,
1501 i915_gem_next_request_seqno(ring
));
1503 trace_i915_gem_object_change_domain(obj
,
1504 obj
->base
.read_domains
,
1511 i915_gem_get_seqno(struct drm_device
*dev
)
1513 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1514 u32 seqno
= dev_priv
->next_seqno
;
1516 /* reserve 0 for non-seqno */
1517 if (++dev_priv
->next_seqno
== 0)
1518 dev_priv
->next_seqno
= 1;
1524 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1526 if (ring
->outstanding_lazy_request
== 0)
1527 ring
->outstanding_lazy_request
= i915_gem_get_seqno(ring
->dev
);
1529 return ring
->outstanding_lazy_request
;
1533 i915_add_request(struct intel_ring_buffer
*ring
,
1534 struct drm_file
*file
,
1535 struct drm_i915_gem_request
*request
)
1537 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1539 u32 request_ring_position
;
1543 BUG_ON(request
== NULL
);
1544 seqno
= i915_gem_next_request_seqno(ring
);
1546 /* Record the position of the start of the request so that
1547 * should we detect the updated seqno part-way through the
1548 * GPU processing the request, we never over-estimate the
1549 * position of the head.
1551 request_ring_position
= intel_ring_get_tail(ring
);
1553 ret
= ring
->add_request(ring
, &seqno
);
1557 trace_i915_gem_request_add(ring
, seqno
);
1559 request
->seqno
= seqno
;
1560 request
->ring
= ring
;
1561 request
->tail
= request_ring_position
;
1562 request
->emitted_jiffies
= jiffies
;
1563 was_empty
= list_empty(&ring
->request_list
);
1564 list_add_tail(&request
->list
, &ring
->request_list
);
1567 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1569 spin_lock(&file_priv
->mm
.lock
);
1570 request
->file_priv
= file_priv
;
1571 list_add_tail(&request
->client_list
,
1572 &file_priv
->mm
.request_list
);
1573 spin_unlock(&file_priv
->mm
.lock
);
1576 ring
->outstanding_lazy_request
= 0;
1578 if (!dev_priv
->mm
.suspended
) {
1579 if (i915_enable_hangcheck
) {
1580 mod_timer(&dev_priv
->hangcheck_timer
,
1582 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1585 queue_delayed_work(dev_priv
->wq
,
1586 &dev_priv
->mm
.retire_work
, HZ
);
1592 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1594 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1599 spin_lock(&file_priv
->mm
.lock
);
1600 if (request
->file_priv
) {
1601 list_del(&request
->client_list
);
1602 request
->file_priv
= NULL
;
1604 spin_unlock(&file_priv
->mm
.lock
);
1607 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1608 struct intel_ring_buffer
*ring
)
1610 while (!list_empty(&ring
->request_list
)) {
1611 struct drm_i915_gem_request
*request
;
1613 request
= list_first_entry(&ring
->request_list
,
1614 struct drm_i915_gem_request
,
1617 list_del(&request
->list
);
1618 i915_gem_request_remove_from_client(request
);
1622 while (!list_empty(&ring
->active_list
)) {
1623 struct drm_i915_gem_object
*obj
;
1625 obj
= list_first_entry(&ring
->active_list
,
1626 struct drm_i915_gem_object
,
1629 obj
->base
.write_domain
= 0;
1630 list_del_init(&obj
->gpu_write_list
);
1631 i915_gem_object_move_to_inactive(obj
);
1635 static void i915_gem_reset_fences(struct drm_device
*dev
)
1637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1640 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1641 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1642 struct drm_i915_gem_object
*obj
= reg
->obj
;
1647 if (obj
->tiling_mode
)
1648 i915_gem_release_mmap(obj
);
1650 reg
->obj
->fence_reg
= I915_FENCE_REG_NONE
;
1651 reg
->obj
->fenced_gpu_access
= false;
1652 reg
->obj
->last_fenced_seqno
= 0;
1653 reg
->obj
->last_fenced_ring
= NULL
;
1654 i915_gem_clear_fence_reg(dev
, reg
);
1658 void i915_gem_reset(struct drm_device
*dev
)
1660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1661 struct drm_i915_gem_object
*obj
;
1664 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1665 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->ring
[i
]);
1667 /* Remove anything from the flushing lists. The GPU cache is likely
1668 * to be lost on reset along with the data, so simply move the
1669 * lost bo to the inactive list.
1671 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1672 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1673 struct drm_i915_gem_object
,
1676 obj
->base
.write_domain
= 0;
1677 list_del_init(&obj
->gpu_write_list
);
1678 i915_gem_object_move_to_inactive(obj
);
1681 /* Move everything out of the GPU domains to ensure we do any
1682 * necessary invalidation upon reuse.
1684 list_for_each_entry(obj
,
1685 &dev_priv
->mm
.inactive_list
,
1688 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1691 /* The fence registers are invalidated so clear them out */
1692 i915_gem_reset_fences(dev
);
1696 * This function clears the request list as sequence numbers are passed.
1699 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1704 if (list_empty(&ring
->request_list
))
1707 WARN_ON(i915_verify_lists(ring
->dev
));
1709 seqno
= ring
->get_seqno(ring
);
1711 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1712 if (seqno
>= ring
->sync_seqno
[i
])
1713 ring
->sync_seqno
[i
] = 0;
1715 while (!list_empty(&ring
->request_list
)) {
1716 struct drm_i915_gem_request
*request
;
1718 request
= list_first_entry(&ring
->request_list
,
1719 struct drm_i915_gem_request
,
1722 if (!i915_seqno_passed(seqno
, request
->seqno
))
1725 trace_i915_gem_request_retire(ring
, request
->seqno
);
1726 /* We know the GPU must have read the request to have
1727 * sent us the seqno + interrupt, so use the position
1728 * of tail of the request to update the last known position
1731 ring
->last_retired_head
= request
->tail
;
1733 list_del(&request
->list
);
1734 i915_gem_request_remove_from_client(request
);
1738 /* Move any buffers on the active list that are no longer referenced
1739 * by the ringbuffer to the flushing/inactive lists as appropriate.
1741 while (!list_empty(&ring
->active_list
)) {
1742 struct drm_i915_gem_object
*obj
;
1744 obj
= list_first_entry(&ring
->active_list
,
1745 struct drm_i915_gem_object
,
1748 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1751 if (obj
->base
.write_domain
!= 0)
1752 i915_gem_object_move_to_flushing(obj
);
1754 i915_gem_object_move_to_inactive(obj
);
1757 if (unlikely(ring
->trace_irq_seqno
&&
1758 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1759 ring
->irq_put(ring
);
1760 ring
->trace_irq_seqno
= 0;
1763 WARN_ON(i915_verify_lists(ring
->dev
));
1767 i915_gem_retire_requests(struct drm_device
*dev
)
1769 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1772 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1773 struct drm_i915_gem_object
*obj
, *next
;
1775 /* We must be careful that during unbind() we do not
1776 * accidentally infinitely recurse into retire requests.
1778 * retire -> free -> unbind -> wait -> retire_ring
1780 list_for_each_entry_safe(obj
, next
,
1781 &dev_priv
->mm
.deferred_free_list
,
1783 i915_gem_free_object_tail(obj
);
1786 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1787 i915_gem_retire_requests_ring(&dev_priv
->ring
[i
]);
1791 i915_gem_retire_work_handler(struct work_struct
*work
)
1793 drm_i915_private_t
*dev_priv
;
1794 struct drm_device
*dev
;
1798 dev_priv
= container_of(work
, drm_i915_private_t
,
1799 mm
.retire_work
.work
);
1800 dev
= dev_priv
->dev
;
1802 /* Come back later if the device is busy... */
1803 if (!mutex_trylock(&dev
->struct_mutex
)) {
1804 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1808 i915_gem_retire_requests(dev
);
1810 /* Send a periodic flush down the ring so we don't hold onto GEM
1811 * objects indefinitely.
1814 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1815 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[i
];
1817 if (!list_empty(&ring
->gpu_write_list
)) {
1818 struct drm_i915_gem_request
*request
;
1821 ret
= i915_gem_flush_ring(ring
,
1822 0, I915_GEM_GPU_DOMAINS
);
1823 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1824 if (ret
|| request
== NULL
||
1825 i915_add_request(ring
, NULL
, request
))
1829 idle
&= list_empty(&ring
->request_list
);
1832 if (!dev_priv
->mm
.suspended
&& !idle
)
1833 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1835 mutex_unlock(&dev
->struct_mutex
);
1839 * Waits for a sequence number to be signaled, and cleans up the
1840 * request and object lists appropriately for that event.
1843 i915_wait_request(struct intel_ring_buffer
*ring
,
1847 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1853 if (atomic_read(&dev_priv
->mm
.wedged
)) {
1854 struct completion
*x
= &dev_priv
->error_completion
;
1855 bool recovery_complete
;
1856 unsigned long flags
;
1858 /* Give the error handler a chance to run. */
1859 spin_lock_irqsave(&x
->wait
.lock
, flags
);
1860 recovery_complete
= x
->done
> 0;
1861 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
1863 return recovery_complete
? -EIO
: -EAGAIN
;
1866 if (seqno
== ring
->outstanding_lazy_request
) {
1867 struct drm_i915_gem_request
*request
;
1869 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1870 if (request
== NULL
)
1873 ret
= i915_add_request(ring
, NULL
, request
);
1879 seqno
= request
->seqno
;
1882 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
1883 if (HAS_PCH_SPLIT(ring
->dev
))
1884 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1885 else if (IS_VALLEYVIEW(ring
->dev
))
1886 ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1888 ier
= I915_READ(IER
);
1890 DRM_ERROR("something (likely vbetool) disabled "
1891 "interrupts, re-enabling\n");
1892 ring
->dev
->driver
->irq_preinstall(ring
->dev
);
1893 ring
->dev
->driver
->irq_postinstall(ring
->dev
);
1896 trace_i915_gem_request_wait_begin(ring
, seqno
);
1898 ring
->waiting_seqno
= seqno
;
1899 if (ring
->irq_get(ring
)) {
1900 if (dev_priv
->mm
.interruptible
)
1901 ret
= wait_event_interruptible(ring
->irq_queue
,
1902 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1903 || atomic_read(&dev_priv
->mm
.wedged
));
1905 wait_event(ring
->irq_queue
,
1906 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1907 || atomic_read(&dev_priv
->mm
.wedged
));
1909 ring
->irq_put(ring
);
1910 } else if (wait_for_atomic(i915_seqno_passed(ring
->get_seqno(ring
),
1912 atomic_read(&dev_priv
->mm
.wedged
), 3000))
1914 ring
->waiting_seqno
= 0;
1916 trace_i915_gem_request_wait_end(ring
, seqno
);
1918 if (atomic_read(&dev_priv
->mm
.wedged
))
1921 /* Directly dispatch request retiring. While we have the work queue
1922 * to handle this, the waiter on a request often wants an associated
1923 * buffer to have made it to the inactive list, and we would need
1924 * a separate wait queue to handle that.
1926 if (ret
== 0 && do_retire
)
1927 i915_gem_retire_requests_ring(ring
);
1933 * Ensures that all rendering to the object has completed and the object is
1934 * safe to unbind from the GTT or access from the CPU.
1937 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
)
1941 /* This function only exists to support waiting for existing rendering,
1942 * not for emitting required flushes.
1944 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1946 /* If there is rendering queued on the buffer being evicted, wait for
1950 ret
= i915_wait_request(obj
->ring
, obj
->last_rendering_seqno
,
1960 * i915_gem_object_sync - sync an object to a ring.
1962 * @obj: object which may be in use on another ring.
1963 * @to: ring we wish to use the object on. May be NULL.
1965 * This code is meant to abstract object synchronization with the GPU.
1966 * Calling with NULL implies synchronizing the object with the CPU
1967 * rather than a particular GPU ring.
1969 * Returns 0 if successful, else propagates up the lower layer error.
1972 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1973 struct intel_ring_buffer
*to
)
1975 struct intel_ring_buffer
*from
= obj
->ring
;
1979 if (from
== NULL
|| to
== from
)
1982 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
1983 return i915_gem_object_wait_rendering(obj
);
1985 idx
= intel_ring_sync_index(from
, to
);
1987 seqno
= obj
->last_rendering_seqno
;
1988 if (seqno
<= from
->sync_seqno
[idx
])
1991 if (seqno
== from
->outstanding_lazy_request
) {
1992 struct drm_i915_gem_request
*request
;
1994 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1995 if (request
== NULL
)
1998 ret
= i915_add_request(from
, NULL
, request
);
2004 seqno
= request
->seqno
;
2008 ret
= to
->sync_to(to
, from
, seqno
);
2010 from
->sync_seqno
[idx
] = seqno
;
2015 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2017 u32 old_write_domain
, old_read_domains
;
2019 /* Act a barrier for all accesses through the GTT */
2022 /* Force a pagefault for domain tracking on next user access */
2023 i915_gem_release_mmap(obj
);
2025 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2028 old_read_domains
= obj
->base
.read_domains
;
2029 old_write_domain
= obj
->base
.write_domain
;
2031 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2032 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2034 trace_i915_gem_object_change_domain(obj
,
2040 * Unbinds an object from the GTT aperture.
2043 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2045 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2048 if (obj
->gtt_space
== NULL
)
2051 if (obj
->pin_count
!= 0) {
2052 DRM_ERROR("Attempting to unbind pinned buffer\n");
2056 ret
= i915_gem_object_finish_gpu(obj
);
2057 if (ret
== -ERESTARTSYS
)
2059 /* Continue on if we fail due to EIO, the GPU is hung so we
2060 * should be safe and we need to cleanup or else we might
2061 * cause memory corruption through use-after-free.
2064 i915_gem_object_finish_gtt(obj
);
2066 /* Move the object to the CPU domain to ensure that
2067 * any possible CPU writes while it's not in the GTT
2068 * are flushed when we go to remap it.
2071 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2072 if (ret
== -ERESTARTSYS
)
2075 /* In the event of a disaster, abandon all caches and
2076 * hope for the best.
2078 i915_gem_clflush_object(obj
);
2079 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2082 /* release the fence reg _after_ flushing */
2083 ret
= i915_gem_object_put_fence(obj
);
2084 if (ret
== -ERESTARTSYS
)
2087 trace_i915_gem_object_unbind(obj
);
2089 if (obj
->has_global_gtt_mapping
)
2090 i915_gem_gtt_unbind_object(obj
);
2091 if (obj
->has_aliasing_ppgtt_mapping
) {
2092 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2093 obj
->has_aliasing_ppgtt_mapping
= 0;
2095 i915_gem_gtt_finish_object(obj
);
2097 i915_gem_object_put_pages_gtt(obj
);
2099 list_del_init(&obj
->gtt_list
);
2100 list_del_init(&obj
->mm_list
);
2101 /* Avoid an unnecessary call to unbind on rebind. */
2102 obj
->map_and_fenceable
= true;
2104 drm_mm_put_block(obj
->gtt_space
);
2105 obj
->gtt_space
= NULL
;
2106 obj
->gtt_offset
= 0;
2108 if (i915_gem_object_is_purgeable(obj
))
2109 i915_gem_object_truncate(obj
);
2115 i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
2116 uint32_t invalidate_domains
,
2117 uint32_t flush_domains
)
2121 if (((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) == 0)
2124 trace_i915_gem_ring_flush(ring
, invalidate_domains
, flush_domains
);
2126 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2130 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
2131 i915_gem_process_flushing_list(ring
, flush_domains
);
2136 static int i915_ring_idle(struct intel_ring_buffer
*ring
, bool do_retire
)
2140 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2143 if (!list_empty(&ring
->gpu_write_list
)) {
2144 ret
= i915_gem_flush_ring(ring
,
2145 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2150 return i915_wait_request(ring
, i915_gem_next_request_seqno(ring
),
2154 int i915_gpu_idle(struct drm_device
*dev
, bool do_retire
)
2156 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2159 /* Flush everything onto the inactive list. */
2160 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2161 ret
= i915_ring_idle(&dev_priv
->ring
[i
], do_retire
);
2169 static int sandybridge_write_fence_reg(struct drm_i915_gem_object
*obj
)
2171 struct drm_device
*dev
= obj
->base
.dev
;
2172 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2173 u32 size
= obj
->gtt_space
->size
;
2174 int regnum
= obj
->fence_reg
;
2177 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2179 val
|= obj
->gtt_offset
& 0xfffff000;
2180 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2181 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2183 if (obj
->tiling_mode
== I915_TILING_Y
)
2184 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2185 val
|= I965_FENCE_REG_VALID
;
2187 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ regnum
* 8, val
);
2192 static int i965_write_fence_reg(struct drm_i915_gem_object
*obj
)
2194 struct drm_device
*dev
= obj
->base
.dev
;
2195 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2196 u32 size
= obj
->gtt_space
->size
;
2197 int regnum
= obj
->fence_reg
;
2200 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2202 val
|= obj
->gtt_offset
& 0xfffff000;
2203 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2204 if (obj
->tiling_mode
== I915_TILING_Y
)
2205 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2206 val
|= I965_FENCE_REG_VALID
;
2208 I915_WRITE64(FENCE_REG_965_0
+ regnum
* 8, val
);
2213 static int i915_write_fence_reg(struct drm_i915_gem_object
*obj
)
2215 struct drm_device
*dev
= obj
->base
.dev
;
2216 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2217 u32 size
= obj
->gtt_space
->size
;
2218 u32 fence_reg
, val
, pitch_val
;
2221 if (WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2222 (size
& -size
) != size
||
2223 (obj
->gtt_offset
& (size
- 1)),
2224 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2225 obj
->gtt_offset
, obj
->map_and_fenceable
, size
))
2228 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2233 /* Note: pitch better be a power of two tile widths */
2234 pitch_val
= obj
->stride
/ tile_width
;
2235 pitch_val
= ffs(pitch_val
) - 1;
2237 val
= obj
->gtt_offset
;
2238 if (obj
->tiling_mode
== I915_TILING_Y
)
2239 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2240 val
|= I915_FENCE_SIZE_BITS(size
);
2241 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2242 val
|= I830_FENCE_REG_VALID
;
2244 fence_reg
= obj
->fence_reg
;
2246 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2248 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2250 I915_WRITE(fence_reg
, val
);
2255 static int i830_write_fence_reg(struct drm_i915_gem_object
*obj
)
2257 struct drm_device
*dev
= obj
->base
.dev
;
2258 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2259 u32 size
= obj
->gtt_space
->size
;
2260 int regnum
= obj
->fence_reg
;
2264 if (WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2265 (size
& -size
) != size
||
2266 (obj
->gtt_offset
& (size
- 1)),
2267 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2268 obj
->gtt_offset
, size
))
2271 pitch_val
= obj
->stride
/ 128;
2272 pitch_val
= ffs(pitch_val
) - 1;
2274 val
= obj
->gtt_offset
;
2275 if (obj
->tiling_mode
== I915_TILING_Y
)
2276 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2277 val
|= I830_FENCE_SIZE_BITS(size
);
2278 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2279 val
|= I830_FENCE_REG_VALID
;
2281 I915_WRITE(FENCE_REG_830_0
+ regnum
* 4, val
);
2286 static bool ring_passed_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
2288 return i915_seqno_passed(ring
->get_seqno(ring
), seqno
);
2292 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2296 if (obj
->fenced_gpu_access
) {
2297 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2298 ret
= i915_gem_flush_ring(obj
->last_fenced_ring
,
2299 0, obj
->base
.write_domain
);
2304 obj
->fenced_gpu_access
= false;
2307 if (obj
->last_fenced_seqno
&& NULL
!= obj
->last_fenced_ring
) {
2308 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2309 obj
->last_fenced_seqno
)) {
2310 ret
= i915_wait_request(obj
->last_fenced_ring
,
2311 obj
->last_fenced_seqno
,
2317 obj
->last_fenced_seqno
= 0;
2318 obj
->last_fenced_ring
= NULL
;
2321 /* Ensure that all CPU reads are completed before installing a fence
2322 * and all writes before removing the fence.
2324 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2331 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2335 if (obj
->tiling_mode
)
2336 i915_gem_release_mmap(obj
);
2338 ret
= i915_gem_object_flush_fence(obj
);
2342 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2343 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2345 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
);
2346 i915_gem_clear_fence_reg(obj
->base
.dev
,
2347 &dev_priv
->fence_regs
[obj
->fence_reg
]);
2349 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2355 static struct drm_i915_fence_reg
*
2356 i915_find_fence_reg(struct drm_device
*dev
)
2358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2359 struct drm_i915_fence_reg
*reg
, *first
, *avail
;
2362 /* First try to find a free reg */
2364 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2365 reg
= &dev_priv
->fence_regs
[i
];
2369 if (!reg
->pin_count
)
2376 /* None available, try to steal one or wait for a user to finish */
2377 avail
= first
= NULL
;
2378 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2385 if (reg
->obj
->last_fenced_ring
== NULL
) {
2398 * i915_gem_object_get_fence - set up fencing for an object
2399 * @obj: object to map through a fence reg
2401 * When mapping objects through the GTT, userspace wants to be able to write
2402 * to them without having to worry about swizzling if the object is tiled.
2403 * This function walks the fence regs looking for a free one for @obj,
2404 * stealing one if it can't find any.
2406 * It then sets up the reg based on the object's properties: address, pitch
2407 * and tiling format.
2409 * For an untiled surface, this removes any existing fence.
2412 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2414 struct drm_device
*dev
= obj
->base
.dev
;
2415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2416 struct drm_i915_fence_reg
*reg
;
2419 if (obj
->tiling_mode
== I915_TILING_NONE
)
2420 return i915_gem_object_put_fence(obj
);
2422 /* Just update our place in the LRU if our fence is getting reused. */
2423 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2424 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2425 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2427 if (obj
->tiling_changed
) {
2428 ret
= i915_gem_object_flush_fence(obj
);
2435 if (reg
->setup_seqno
) {
2436 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2437 reg
->setup_seqno
)) {
2438 ret
= i915_wait_request(obj
->last_fenced_ring
,
2445 reg
->setup_seqno
= 0;
2451 reg
= i915_find_fence_reg(dev
);
2455 ret
= i915_gem_object_flush_fence(obj
);
2460 struct drm_i915_gem_object
*old
= reg
->obj
;
2462 drm_gem_object_reference(&old
->base
);
2464 if (old
->tiling_mode
)
2465 i915_gem_release_mmap(old
);
2467 ret
= i915_gem_object_flush_fence(old
);
2469 drm_gem_object_unreference(&old
->base
);
2473 old
->fence_reg
= I915_FENCE_REG_NONE
;
2474 old
->last_fenced_ring
= NULL
;
2475 old
->last_fenced_seqno
= 0;
2477 drm_gem_object_unreference(&old
->base
);
2481 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2482 obj
->fence_reg
= reg
- dev_priv
->fence_regs
;
2483 obj
->last_fenced_ring
= NULL
;
2485 reg
->setup_seqno
= 0;
2486 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2489 obj
->tiling_changed
= false;
2490 switch (INTEL_INFO(dev
)->gen
) {
2493 ret
= sandybridge_write_fence_reg(obj
);
2497 ret
= i965_write_fence_reg(obj
);
2500 ret
= i915_write_fence_reg(obj
);
2503 ret
= i830_write_fence_reg(obj
);
2511 * i915_gem_clear_fence_reg - clear out fence register info
2512 * @obj: object to clear
2514 * Zeroes out the fence register itself and clears out the associated
2515 * data structures in dev_priv and obj.
2518 i915_gem_clear_fence_reg(struct drm_device
*dev
,
2519 struct drm_i915_fence_reg
*reg
)
2521 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2522 uint32_t fence_reg
= reg
- dev_priv
->fence_regs
;
2524 switch (INTEL_INFO(dev
)->gen
) {
2527 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ fence_reg
*8, 0);
2531 I915_WRITE64(FENCE_REG_965_0
+ fence_reg
*8, 0);
2535 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2538 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2540 I915_WRITE(fence_reg
, 0);
2544 list_del_init(®
->lru_list
);
2546 reg
->setup_seqno
= 0;
2551 * Finds free space in the GTT aperture and binds the object there.
2554 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2556 bool map_and_fenceable
)
2558 struct drm_device
*dev
= obj
->base
.dev
;
2559 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2560 struct drm_mm_node
*free_space
;
2561 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2562 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2563 bool mappable
, fenceable
;
2566 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2567 DRM_ERROR("Attempting to bind a purgeable object\n");
2571 fence_size
= i915_gem_get_gtt_size(dev
,
2574 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2577 unfenced_alignment
=
2578 i915_gem_get_unfenced_gtt_alignment(dev
,
2583 alignment
= map_and_fenceable
? fence_alignment
:
2585 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2586 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2590 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2592 /* If the object is bigger than the entire aperture, reject it early
2593 * before evicting everything in a vain attempt to find space.
2595 if (obj
->base
.size
>
2596 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2597 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2602 if (map_and_fenceable
)
2604 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2606 dev_priv
->mm
.gtt_mappable_end
,
2609 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2610 size
, alignment
, 0);
2612 if (free_space
!= NULL
) {
2613 if (map_and_fenceable
)
2615 drm_mm_get_block_range_generic(free_space
,
2617 dev_priv
->mm
.gtt_mappable_end
,
2621 drm_mm_get_block(free_space
, size
, alignment
);
2623 if (obj
->gtt_space
== NULL
) {
2624 /* If the gtt is empty and we're still having trouble
2625 * fitting our object in, we're out of memory.
2627 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2635 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2637 drm_mm_put_block(obj
->gtt_space
);
2638 obj
->gtt_space
= NULL
;
2640 if (ret
== -ENOMEM
) {
2641 /* first try to reclaim some memory by clearing the GTT */
2642 ret
= i915_gem_evict_everything(dev
, false);
2644 /* now try to shrink everyone else */
2659 ret
= i915_gem_gtt_prepare_object(obj
);
2661 i915_gem_object_put_pages_gtt(obj
);
2662 drm_mm_put_block(obj
->gtt_space
);
2663 obj
->gtt_space
= NULL
;
2665 if (i915_gem_evict_everything(dev
, false))
2671 if (!dev_priv
->mm
.aliasing_ppgtt
)
2672 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
2674 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2675 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2677 /* Assert that the object is not currently in any GPU domain. As it
2678 * wasn't in the GTT, there shouldn't be any way it could have been in
2681 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2682 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2684 obj
->gtt_offset
= obj
->gtt_space
->start
;
2687 obj
->gtt_space
->size
== fence_size
&&
2688 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2691 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2693 obj
->map_and_fenceable
= mappable
&& fenceable
;
2695 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2700 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2702 /* If we don't have a page list set up, then we're not pinned
2703 * to GPU, and we can ignore the cache flush because it'll happen
2704 * again at bind time.
2706 if (obj
->pages
== NULL
)
2709 /* If the GPU is snooping the contents of the CPU cache,
2710 * we do not need to manually clear the CPU cache lines. However,
2711 * the caches are only snooped when the render cache is
2712 * flushed/invalidated. As we always have to emit invalidations
2713 * and flushes when moving into and out of the RENDER domain, correct
2714 * snooping behaviour occurs naturally as the result of our domain
2717 if (obj
->cache_level
!= I915_CACHE_NONE
)
2720 trace_i915_gem_object_clflush(obj
);
2722 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2725 /** Flushes any GPU write domain for the object if it's dirty. */
2727 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
)
2729 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2732 /* Queue the GPU write cache flushing we need. */
2733 return i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2736 /** Flushes the GTT write domain for the object if it's dirty. */
2738 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2740 uint32_t old_write_domain
;
2742 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2745 /* No actual flushing is required for the GTT write domain. Writes
2746 * to it immediately go to main memory as far as we know, so there's
2747 * no chipset flush. It also doesn't land in render cache.
2749 * However, we do have to enforce the order so that all writes through
2750 * the GTT land before any writes to the device, such as updates to
2755 old_write_domain
= obj
->base
.write_domain
;
2756 obj
->base
.write_domain
= 0;
2758 trace_i915_gem_object_change_domain(obj
,
2759 obj
->base
.read_domains
,
2763 /** Flushes the CPU write domain for the object if it's dirty. */
2765 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2767 uint32_t old_write_domain
;
2769 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2772 i915_gem_clflush_object(obj
);
2773 intel_gtt_chipset_flush();
2774 old_write_domain
= obj
->base
.write_domain
;
2775 obj
->base
.write_domain
= 0;
2777 trace_i915_gem_object_change_domain(obj
,
2778 obj
->base
.read_domains
,
2783 * Moves a single object to the GTT read, and possibly write domain.
2785 * This function returns when the move is complete, including waiting on
2789 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2791 uint32_t old_write_domain
, old_read_domains
;
2794 /* Not valid to be called on unbound objects. */
2795 if (obj
->gtt_space
== NULL
)
2798 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2801 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2805 if (obj
->pending_gpu_write
|| write
) {
2806 ret
= i915_gem_object_wait_rendering(obj
);
2811 i915_gem_object_flush_cpu_write_domain(obj
);
2813 old_write_domain
= obj
->base
.write_domain
;
2814 old_read_domains
= obj
->base
.read_domains
;
2816 /* It should now be out of any other write domains, and we can update
2817 * the domain values for our changes.
2819 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2820 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2822 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2823 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2827 trace_i915_gem_object_change_domain(obj
,
2834 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2835 enum i915_cache_level cache_level
)
2837 struct drm_device
*dev
= obj
->base
.dev
;
2838 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2841 if (obj
->cache_level
== cache_level
)
2844 if (obj
->pin_count
) {
2845 DRM_DEBUG("can not change the cache level of pinned objects\n");
2849 if (obj
->gtt_space
) {
2850 ret
= i915_gem_object_finish_gpu(obj
);
2854 i915_gem_object_finish_gtt(obj
);
2856 /* Before SandyBridge, you could not use tiling or fence
2857 * registers with snooped memory, so relinquish any fences
2858 * currently pointing to our region in the aperture.
2860 if (INTEL_INFO(obj
->base
.dev
)->gen
< 6) {
2861 ret
= i915_gem_object_put_fence(obj
);
2866 if (obj
->has_global_gtt_mapping
)
2867 i915_gem_gtt_bind_object(obj
, cache_level
);
2868 if (obj
->has_aliasing_ppgtt_mapping
)
2869 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
2873 if (cache_level
== I915_CACHE_NONE
) {
2874 u32 old_read_domains
, old_write_domain
;
2876 /* If we're coming from LLC cached, then we haven't
2877 * actually been tracking whether the data is in the
2878 * CPU cache or not, since we only allow one bit set
2879 * in obj->write_domain and have been skipping the clflushes.
2880 * Just set it to the CPU cache for now.
2882 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
2883 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
2885 old_read_domains
= obj
->base
.read_domains
;
2886 old_write_domain
= obj
->base
.write_domain
;
2888 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
2889 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2891 trace_i915_gem_object_change_domain(obj
,
2896 obj
->cache_level
= cache_level
;
2901 * Prepare buffer for display plane (scanout, cursors, etc).
2902 * Can be called from an uninterruptible phase (modesetting) and allows
2903 * any flushes to be pipelined (for pageflips).
2906 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2908 struct intel_ring_buffer
*pipelined
)
2910 u32 old_read_domains
, old_write_domain
;
2913 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2917 if (pipelined
!= obj
->ring
) {
2918 ret
= i915_gem_object_sync(obj
, pipelined
);
2923 /* The display engine is not coherent with the LLC cache on gen6. As
2924 * a result, we make sure that the pinning that is about to occur is
2925 * done with uncached PTEs. This is lowest common denominator for all
2928 * However for gen6+, we could do better by using the GFDT bit instead
2929 * of uncaching, which would allow us to flush all the LLC-cached data
2930 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2932 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
2936 /* As the user may map the buffer once pinned in the display plane
2937 * (e.g. libkms for the bootup splash), we have to ensure that we
2938 * always use map_and_fenceable for all scanout buffers.
2940 ret
= i915_gem_object_pin(obj
, alignment
, true);
2944 i915_gem_object_flush_cpu_write_domain(obj
);
2946 old_write_domain
= obj
->base
.write_domain
;
2947 old_read_domains
= obj
->base
.read_domains
;
2949 /* It should now be out of any other write domains, and we can update
2950 * the domain values for our changes.
2952 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2953 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2955 trace_i915_gem_object_change_domain(obj
,
2963 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
2967 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
2970 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2971 ret
= i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2976 ret
= i915_gem_object_wait_rendering(obj
);
2980 /* Ensure that we invalidate the GPU's caches and TLBs. */
2981 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2986 * Moves a single object to the CPU read, and possibly write domain.
2988 * This function returns when the move is complete, including waiting on
2992 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
2994 uint32_t old_write_domain
, old_read_domains
;
2997 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3000 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3004 if (write
|| obj
->pending_gpu_write
) {
3005 ret
= i915_gem_object_wait_rendering(obj
);
3010 i915_gem_object_flush_gtt_write_domain(obj
);
3012 old_write_domain
= obj
->base
.write_domain
;
3013 old_read_domains
= obj
->base
.read_domains
;
3015 /* Flush the CPU cache if it's still invalid. */
3016 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3017 i915_gem_clflush_object(obj
);
3019 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3022 /* It should now be out of any other write domains, and we can update
3023 * the domain values for our changes.
3025 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3027 /* If we're writing through the CPU, then the GPU read domains will
3028 * need to be invalidated at next use.
3031 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3032 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3035 trace_i915_gem_object_change_domain(obj
,
3042 /* Throttle our rendering by waiting until the ring has completed our requests
3043 * emitted over 20 msec ago.
3045 * Note that if we were to use the current jiffies each time around the loop,
3046 * we wouldn't escape the function with any frames outstanding if the time to
3047 * render a frame was over 20ms.
3049 * This should get us reasonable parallelism between CPU and GPU but also
3050 * relatively low latency when blocking on a particular request to finish.
3053 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3056 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3057 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3058 struct drm_i915_gem_request
*request
;
3059 struct intel_ring_buffer
*ring
= NULL
;
3063 if (atomic_read(&dev_priv
->mm
.wedged
))
3066 spin_lock(&file_priv
->mm
.lock
);
3067 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3068 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3071 ring
= request
->ring
;
3072 seqno
= request
->seqno
;
3074 spin_unlock(&file_priv
->mm
.lock
);
3080 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3081 /* And wait for the seqno passing without holding any locks and
3082 * causing extra latency for others. This is safe as the irq
3083 * generation is designed to be run atomically and so is
3086 if (ring
->irq_get(ring
)) {
3087 ret
= wait_event_interruptible(ring
->irq_queue
,
3088 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3089 || atomic_read(&dev_priv
->mm
.wedged
));
3090 ring
->irq_put(ring
);
3092 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3094 } else if (wait_for_atomic(i915_seqno_passed(ring
->get_seqno(ring
),
3096 atomic_read(&dev_priv
->mm
.wedged
), 3000)) {
3102 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3108 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3110 bool map_and_fenceable
)
3112 struct drm_device
*dev
= obj
->base
.dev
;
3113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3116 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3117 WARN_ON(i915_verify_lists(dev
));
3119 if (obj
->gtt_space
!= NULL
) {
3120 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3121 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3122 WARN(obj
->pin_count
,
3123 "bo is already pinned with incorrect alignment:"
3124 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3125 " obj->map_and_fenceable=%d\n",
3126 obj
->gtt_offset
, alignment
,
3128 obj
->map_and_fenceable
);
3129 ret
= i915_gem_object_unbind(obj
);
3135 if (obj
->gtt_space
== NULL
) {
3136 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3142 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3143 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3145 if (obj
->pin_count
++ == 0) {
3147 list_move_tail(&obj
->mm_list
,
3148 &dev_priv
->mm
.pinned_list
);
3150 obj
->pin_mappable
|= map_and_fenceable
;
3152 WARN_ON(i915_verify_lists(dev
));
3157 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3159 struct drm_device
*dev
= obj
->base
.dev
;
3160 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3162 WARN_ON(i915_verify_lists(dev
));
3163 BUG_ON(obj
->pin_count
== 0);
3164 BUG_ON(obj
->gtt_space
== NULL
);
3166 if (--obj
->pin_count
== 0) {
3168 list_move_tail(&obj
->mm_list
,
3169 &dev_priv
->mm
.inactive_list
);
3170 obj
->pin_mappable
= false;
3172 WARN_ON(i915_verify_lists(dev
));
3176 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3177 struct drm_file
*file
)
3179 struct drm_i915_gem_pin
*args
= data
;
3180 struct drm_i915_gem_object
*obj
;
3183 ret
= i915_mutex_lock_interruptible(dev
);
3187 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3188 if (&obj
->base
== NULL
) {
3193 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3194 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3199 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3200 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3206 obj
->user_pin_count
++;
3207 obj
->pin_filp
= file
;
3208 if (obj
->user_pin_count
== 1) {
3209 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3214 /* XXX - flush the CPU caches for pinned objects
3215 * as the X server doesn't manage domains yet
3217 i915_gem_object_flush_cpu_write_domain(obj
);
3218 args
->offset
= obj
->gtt_offset
;
3220 drm_gem_object_unreference(&obj
->base
);
3222 mutex_unlock(&dev
->struct_mutex
);
3227 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3228 struct drm_file
*file
)
3230 struct drm_i915_gem_pin
*args
= data
;
3231 struct drm_i915_gem_object
*obj
;
3234 ret
= i915_mutex_lock_interruptible(dev
);
3238 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3239 if (&obj
->base
== NULL
) {
3244 if (obj
->pin_filp
!= file
) {
3245 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3250 obj
->user_pin_count
--;
3251 if (obj
->user_pin_count
== 0) {
3252 obj
->pin_filp
= NULL
;
3253 i915_gem_object_unpin(obj
);
3257 drm_gem_object_unreference(&obj
->base
);
3259 mutex_unlock(&dev
->struct_mutex
);
3264 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3265 struct drm_file
*file
)
3267 struct drm_i915_gem_busy
*args
= data
;
3268 struct drm_i915_gem_object
*obj
;
3271 ret
= i915_mutex_lock_interruptible(dev
);
3275 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3276 if (&obj
->base
== NULL
) {
3281 /* Count all active objects as busy, even if they are currently not used
3282 * by the gpu. Users of this interface expect objects to eventually
3283 * become non-busy without any further actions, therefore emit any
3284 * necessary flushes here.
3286 args
->busy
= obj
->active
;
3288 /* Unconditionally flush objects, even when the gpu still uses this
3289 * object. Userspace calling this function indicates that it wants to
3290 * use this buffer rather sooner than later, so issuing the required
3291 * flush earlier is beneficial.
3293 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3294 ret
= i915_gem_flush_ring(obj
->ring
,
3295 0, obj
->base
.write_domain
);
3296 } else if (obj
->ring
->outstanding_lazy_request
==
3297 obj
->last_rendering_seqno
) {
3298 struct drm_i915_gem_request
*request
;
3300 /* This ring is not being cleared by active usage,
3301 * so emit a request to do so.
3303 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3305 ret
= i915_add_request(obj
->ring
, NULL
, request
);
3312 /* Update the active list for the hardware's current position.
3313 * Otherwise this only updates on a delayed timer or when irqs
3314 * are actually unmasked, and our working set ends up being
3315 * larger than required.
3317 i915_gem_retire_requests_ring(obj
->ring
);
3319 args
->busy
= obj
->active
;
3322 drm_gem_object_unreference(&obj
->base
);
3324 mutex_unlock(&dev
->struct_mutex
);
3329 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3330 struct drm_file
*file_priv
)
3332 return i915_gem_ring_throttle(dev
, file_priv
);
3336 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3337 struct drm_file
*file_priv
)
3339 struct drm_i915_gem_madvise
*args
= data
;
3340 struct drm_i915_gem_object
*obj
;
3343 switch (args
->madv
) {
3344 case I915_MADV_DONTNEED
:
3345 case I915_MADV_WILLNEED
:
3351 ret
= i915_mutex_lock_interruptible(dev
);
3355 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3356 if (&obj
->base
== NULL
) {
3361 if (obj
->pin_count
) {
3366 if (obj
->madv
!= __I915_MADV_PURGED
)
3367 obj
->madv
= args
->madv
;
3369 /* if the object is no longer bound, discard its backing storage */
3370 if (i915_gem_object_is_purgeable(obj
) &&
3371 obj
->gtt_space
== NULL
)
3372 i915_gem_object_truncate(obj
);
3374 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3377 drm_gem_object_unreference(&obj
->base
);
3379 mutex_unlock(&dev
->struct_mutex
);
3383 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3387 struct drm_i915_gem_object
*obj
;
3388 struct address_space
*mapping
;
3390 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3394 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3399 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3400 mapping_set_gfp_mask(mapping
, GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3402 i915_gem_info_add_obj(dev_priv
, size
);
3404 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3405 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3408 /* On some devices, we can have the GPU use the LLC (the CPU
3409 * cache) for about a 10% performance improvement
3410 * compared to uncached. Graphics requests other than
3411 * display scanout are coherent with the CPU in
3412 * accessing this cache. This means in this mode we
3413 * don't need to clflush on the CPU side, and on the
3414 * GPU side we only need to flush internal caches to
3415 * get data visible to the CPU.
3417 * However, we maintain the display planes as UC, and so
3418 * need to rebind when first used as such.
3420 obj
->cache_level
= I915_CACHE_LLC
;
3422 obj
->cache_level
= I915_CACHE_NONE
;
3424 obj
->base
.driver_private
= NULL
;
3425 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3426 INIT_LIST_HEAD(&obj
->mm_list
);
3427 INIT_LIST_HEAD(&obj
->gtt_list
);
3428 INIT_LIST_HEAD(&obj
->ring_list
);
3429 INIT_LIST_HEAD(&obj
->exec_list
);
3430 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3431 obj
->madv
= I915_MADV_WILLNEED
;
3432 /* Avoid an unnecessary call to unbind on the first bind. */
3433 obj
->map_and_fenceable
= true;
3438 int i915_gem_init_object(struct drm_gem_object
*obj
)
3445 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
)
3447 struct drm_device
*dev
= obj
->base
.dev
;
3448 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3451 ret
= i915_gem_object_unbind(obj
);
3452 if (ret
== -ERESTARTSYS
) {
3453 list_move(&obj
->mm_list
,
3454 &dev_priv
->mm
.deferred_free_list
);
3458 trace_i915_gem_object_destroy(obj
);
3460 if (obj
->base
.map_list
.map
)
3461 drm_gem_free_mmap_offset(&obj
->base
);
3463 drm_gem_object_release(&obj
->base
);
3464 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3470 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3472 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3473 struct drm_device
*dev
= obj
->base
.dev
;
3475 while (obj
->pin_count
> 0)
3476 i915_gem_object_unpin(obj
);
3479 i915_gem_detach_phys_object(dev
, obj
);
3481 i915_gem_free_object_tail(obj
);
3485 i915_gem_idle(struct drm_device
*dev
)
3487 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3490 mutex_lock(&dev
->struct_mutex
);
3492 if (dev_priv
->mm
.suspended
) {
3493 mutex_unlock(&dev
->struct_mutex
);
3497 ret
= i915_gpu_idle(dev
, true);
3499 mutex_unlock(&dev
->struct_mutex
);
3503 /* Under UMS, be paranoid and evict. */
3504 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3505 ret
= i915_gem_evict_inactive(dev
, false);
3507 mutex_unlock(&dev
->struct_mutex
);
3512 i915_gem_reset_fences(dev
);
3514 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3515 * We need to replace this with a semaphore, or something.
3516 * And not confound mm.suspended!
3518 dev_priv
->mm
.suspended
= 1;
3519 del_timer_sync(&dev_priv
->hangcheck_timer
);
3521 i915_kernel_lost_context(dev
);
3522 i915_gem_cleanup_ringbuffer(dev
);
3524 mutex_unlock(&dev
->struct_mutex
);
3526 /* Cancel the retire work handler, which should be idle now. */
3527 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3532 void i915_gem_init_swizzling(struct drm_device
*dev
)
3534 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3536 if (INTEL_INFO(dev
)->gen
< 5 ||
3537 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3540 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3541 DISP_TILE_SURFACE_SWIZZLING
);
3546 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3548 I915_WRITE(ARB_MODE
, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3550 I915_WRITE(ARB_MODE
, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3553 void i915_gem_init_ppgtt(struct drm_device
*dev
)
3555 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3557 struct intel_ring_buffer
*ring
;
3558 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3559 uint32_t __iomem
*pd_addr
;
3563 if (!dev_priv
->mm
.aliasing_ppgtt
)
3567 pd_addr
= dev_priv
->mm
.gtt
->gtt
+ ppgtt
->pd_offset
/sizeof(uint32_t);
3568 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
3571 if (dev_priv
->mm
.gtt
->needs_dmar
)
3572 pt_addr
= ppgtt
->pt_dma_addr
[i
];
3574 pt_addr
= page_to_phys(ppgtt
->pt_pages
[i
]);
3576 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
3577 pd_entry
|= GEN6_PDE_VALID
;
3579 writel(pd_entry
, pd_addr
+ i
);
3583 pd_offset
= ppgtt
->pd_offset
;
3584 pd_offset
/= 64; /* in cachelines, */
3587 if (INTEL_INFO(dev
)->gen
== 6) {
3588 uint32_t ecochk
, gab_ctl
, ecobits
;
3590 ecobits
= I915_READ(GAC_ECO_BITS
);
3591 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
3593 gab_ctl
= I915_READ(GAB_CTL
);
3594 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
3596 ecochk
= I915_READ(GAM_ECOCHK
);
3597 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
3598 ECOCHK_PPGTT_CACHE64B
);
3599 I915_WRITE(GFX_MODE
, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE
));
3600 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3601 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
3602 /* GFX_MODE is per-ring on gen7+ */
3605 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3606 ring
= &dev_priv
->ring
[i
];
3608 if (INTEL_INFO(dev
)->gen
>= 7)
3609 I915_WRITE(RING_MODE_GEN7(ring
),
3610 GFX_MODE_ENABLE(GFX_PPGTT_ENABLE
));
3612 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
3613 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
3618 i915_gem_init_hw(struct drm_device
*dev
)
3620 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3623 i915_gem_init_swizzling(dev
);
3625 ret
= intel_init_render_ring_buffer(dev
);
3630 ret
= intel_init_bsd_ring_buffer(dev
);
3632 goto cleanup_render_ring
;
3636 ret
= intel_init_blt_ring_buffer(dev
);
3638 goto cleanup_bsd_ring
;
3641 dev_priv
->next_seqno
= 1;
3643 i915_gem_init_ppgtt(dev
);
3648 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3649 cleanup_render_ring
:
3650 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3655 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3657 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3660 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3661 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
3665 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3666 struct drm_file
*file_priv
)
3668 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3671 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3674 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3675 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3676 atomic_set(&dev_priv
->mm
.wedged
, 0);
3679 mutex_lock(&dev
->struct_mutex
);
3680 dev_priv
->mm
.suspended
= 0;
3682 ret
= i915_gem_init_hw(dev
);
3684 mutex_unlock(&dev
->struct_mutex
);
3688 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3689 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3690 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3691 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3692 BUG_ON(!list_empty(&dev_priv
->ring
[i
].active_list
));
3693 BUG_ON(!list_empty(&dev_priv
->ring
[i
].request_list
));
3695 mutex_unlock(&dev
->struct_mutex
);
3697 ret
= drm_irq_install(dev
);
3699 goto cleanup_ringbuffer
;
3704 mutex_lock(&dev
->struct_mutex
);
3705 i915_gem_cleanup_ringbuffer(dev
);
3706 dev_priv
->mm
.suspended
= 1;
3707 mutex_unlock(&dev
->struct_mutex
);
3713 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3714 struct drm_file
*file_priv
)
3716 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3719 drm_irq_uninstall(dev
);
3720 return i915_gem_idle(dev
);
3724 i915_gem_lastclose(struct drm_device
*dev
)
3728 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3731 ret
= i915_gem_idle(dev
);
3733 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3737 init_ring_lists(struct intel_ring_buffer
*ring
)
3739 INIT_LIST_HEAD(&ring
->active_list
);
3740 INIT_LIST_HEAD(&ring
->request_list
);
3741 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3745 i915_gem_load(struct drm_device
*dev
)
3748 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3750 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3751 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3752 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3753 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
3754 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3755 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
3756 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3757 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3758 init_ring_lists(&dev_priv
->ring
[i
]);
3759 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
3760 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3761 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3762 i915_gem_retire_work_handler
);
3763 init_completion(&dev_priv
->error_completion
);
3765 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3767 u32 tmp
= I915_READ(MI_ARB_STATE
);
3768 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
3769 /* arb state is a masked write, so set bit + bit in mask */
3770 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
3771 I915_WRITE(MI_ARB_STATE
, tmp
);
3775 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3777 /* Old X drivers will take 0-2 for front, back, depth buffers */
3778 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3779 dev_priv
->fence_reg_start
= 3;
3781 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3782 dev_priv
->num_fence_regs
= 16;
3784 dev_priv
->num_fence_regs
= 8;
3786 /* Initialize fence registers to zero */
3787 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
3788 i915_gem_clear_fence_reg(dev
, &dev_priv
->fence_regs
[i
]);
3791 i915_gem_detect_bit_6_swizzle(dev
);
3792 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3794 dev_priv
->mm
.interruptible
= true;
3796 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3797 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3798 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3802 * Create a physically contiguous memory object for this object
3803 * e.g. for cursor + overlay regs
3805 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3806 int id
, int size
, int align
)
3808 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3809 struct drm_i915_gem_phys_object
*phys_obj
;
3812 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3815 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3821 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3822 if (!phys_obj
->handle
) {
3827 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3830 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3838 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3840 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3841 struct drm_i915_gem_phys_object
*phys_obj
;
3843 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3846 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3847 if (phys_obj
->cur_obj
) {
3848 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3852 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3854 drm_pci_free(dev
, phys_obj
->handle
);
3856 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3859 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3863 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3864 i915_gem_free_phys_object(dev
, i
);
3867 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3868 struct drm_i915_gem_object
*obj
)
3870 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3877 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3879 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3880 for (i
= 0; i
< page_count
; i
++) {
3881 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
3882 if (!IS_ERR(page
)) {
3883 char *dst
= kmap_atomic(page
);
3884 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3887 drm_clflush_pages(&page
, 1);
3889 set_page_dirty(page
);
3890 mark_page_accessed(page
);
3891 page_cache_release(page
);
3894 intel_gtt_chipset_flush();
3896 obj
->phys_obj
->cur_obj
= NULL
;
3897 obj
->phys_obj
= NULL
;
3901 i915_gem_attach_phys_object(struct drm_device
*dev
,
3902 struct drm_i915_gem_object
*obj
,
3906 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3907 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3912 if (id
> I915_MAX_PHYS_OBJECT
)
3915 if (obj
->phys_obj
) {
3916 if (obj
->phys_obj
->id
== id
)
3918 i915_gem_detach_phys_object(dev
, obj
);
3921 /* create a new object */
3922 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3923 ret
= i915_gem_init_phys_object(dev
, id
,
3924 obj
->base
.size
, align
);
3926 DRM_ERROR("failed to init phys object %d size: %zu\n",
3927 id
, obj
->base
.size
);
3932 /* bind to the object */
3933 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3934 obj
->phys_obj
->cur_obj
= obj
;
3936 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3938 for (i
= 0; i
< page_count
; i
++) {
3942 page
= shmem_read_mapping_page(mapping
, i
);
3944 return PTR_ERR(page
);
3946 src
= kmap_atomic(page
);
3947 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3948 memcpy(dst
, src
, PAGE_SIZE
);
3951 mark_page_accessed(page
);
3952 page_cache_release(page
);
3959 i915_gem_phys_pwrite(struct drm_device
*dev
,
3960 struct drm_i915_gem_object
*obj
,
3961 struct drm_i915_gem_pwrite
*args
,
3962 struct drm_file
*file_priv
)
3964 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
3965 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
3967 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
3968 unsigned long unwritten
;
3970 /* The physical object once assigned is fixed for the lifetime
3971 * of the obj, so we can safely drop the lock and continue
3974 mutex_unlock(&dev
->struct_mutex
);
3975 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
3976 mutex_lock(&dev
->struct_mutex
);
3981 intel_gtt_chipset_flush();
3985 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
3987 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3989 /* Clean up our request list when the client is going away, so that
3990 * later retire_requests won't dereference our soon-to-be-gone
3993 spin_lock(&file_priv
->mm
.lock
);
3994 while (!list_empty(&file_priv
->mm
.request_list
)) {
3995 struct drm_i915_gem_request
*request
;
3997 request
= list_first_entry(&file_priv
->mm
.request_list
,
3998 struct drm_i915_gem_request
,
4000 list_del(&request
->client_list
);
4001 request
->file_priv
= NULL
;
4003 spin_unlock(&file_priv
->mm
.lock
);
4007 i915_gpu_is_active(struct drm_device
*dev
)
4009 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4012 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4013 list_empty(&dev_priv
->mm
.active_list
);
4015 return !lists_empty
;
4019 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4021 struct drm_i915_private
*dev_priv
=
4022 container_of(shrinker
,
4023 struct drm_i915_private
,
4024 mm
.inactive_shrinker
);
4025 struct drm_device
*dev
= dev_priv
->dev
;
4026 struct drm_i915_gem_object
*obj
, *next
;
4027 int nr_to_scan
= sc
->nr_to_scan
;
4030 if (!mutex_trylock(&dev
->struct_mutex
))
4033 /* "fast-path" to count number of available objects */
4034 if (nr_to_scan
== 0) {
4036 list_for_each_entry(obj
,
4037 &dev_priv
->mm
.inactive_list
,
4040 mutex_unlock(&dev
->struct_mutex
);
4041 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
4045 /* first scan for clean buffers */
4046 i915_gem_retire_requests(dev
);
4048 list_for_each_entry_safe(obj
, next
,
4049 &dev_priv
->mm
.inactive_list
,
4051 if (i915_gem_object_is_purgeable(obj
)) {
4052 if (i915_gem_object_unbind(obj
) == 0 &&
4058 /* second pass, evict/count anything still on the inactive list */
4060 list_for_each_entry_safe(obj
, next
,
4061 &dev_priv
->mm
.inactive_list
,
4064 i915_gem_object_unbind(obj
) == 0)
4070 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4072 * We are desperate for pages, so as a last resort, wait
4073 * for the GPU to finish and discard whatever we can.
4074 * This has a dramatic impact to reduce the number of
4075 * OOM-killer events whilst running the GPU aggressively.
4077 if (i915_gpu_idle(dev
, true) == 0)
4080 mutex_unlock(&dev
->struct_mutex
);
4081 return cnt
/ 100 * sysctl_vfs_cache_pressure
;