2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_frontbuffer.h"
36 #include "intel_mocs.h"
37 #include <linux/dma-fence-array.h>
38 #include <linux/reservation.h>
39 #include <linux/shmem_fs.h>
40 #include <linux/slab.h>
41 #include <linux/stop_machine.h>
42 #include <linux/swap.h>
43 #include <linux/pci.h>
44 #include <linux/dma-buf.h>
46 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
);
47 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
48 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
50 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
51 enum i915_cache_level level
)
53 return HAS_LLC(to_i915(dev
)) || level
!= I915_CACHE_NONE
;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
58 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
61 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
64 return obj
->pin_display
;
68 insert_mappable_node(struct i915_ggtt
*ggtt
,
69 struct drm_mm_node
*node
, u32 size
)
71 memset(node
, 0, sizeof(*node
));
72 return drm_mm_insert_node_in_range(&ggtt
->base
.mm
, node
,
73 size
, 0, I915_COLOR_UNEVICTABLE
,
74 0, ggtt
->mappable_end
,
79 remove_mappable_node(struct drm_mm_node
*node
)
81 drm_mm_remove_node(node
);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
88 spin_lock(&dev_priv
->mm
.object_stat_lock
);
89 dev_priv
->mm
.object_count
++;
90 dev_priv
->mm
.object_memory
+= size
;
91 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
94 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
97 spin_lock(&dev_priv
->mm
.object_stat_lock
);
98 dev_priv
->mm
.object_count
--;
99 dev_priv
->mm
.object_memory
-= size
;
100 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
104 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
110 if (!i915_reset_in_progress(error
))
114 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
115 * userspace. If it takes that long something really bad is going on and
116 * we should simply try to bail out and fail as gracefully as possible.
118 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 !i915_reset_in_progress(error
),
122 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
124 } else if (ret
< 0) {
131 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
133 struct drm_i915_private
*dev_priv
= to_i915(dev
);
136 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
140 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
148 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_private
*dev_priv
= to_i915(dev
);
152 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
153 struct drm_i915_gem_get_aperture
*args
= data
;
154 struct i915_vma
*vma
;
158 mutex_lock(&dev
->struct_mutex
);
159 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
160 if (i915_vma_is_pinned(vma
))
161 pinned
+= vma
->node
.size
;
162 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
163 if (i915_vma_is_pinned(vma
))
164 pinned
+= vma
->node
.size
;
165 mutex_unlock(&dev
->struct_mutex
);
167 args
->aper_size
= ggtt
->base
.total
;
168 args
->aper_available_size
= args
->aper_size
- pinned
;
173 static struct sg_table
*
174 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
176 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
177 drm_dma_handle_t
*phys
;
179 struct scatterlist
*sg
;
183 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 return ERR_PTR(-EINVAL
);
186 /* Always aligning to the object size, allows a single allocation
187 * to handle all possible callers, and given typical object sizes,
188 * the alignment of the buddy allocation will naturally match.
190 phys
= drm_pci_alloc(obj
->base
.dev
,
192 roundup_pow_of_two(obj
->base
.size
));
194 return ERR_PTR(-ENOMEM
);
197 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
201 page
= shmem_read_mapping_page(mapping
, i
);
207 src
= kmap_atomic(page
);
208 memcpy(vaddr
, src
, PAGE_SIZE
);
209 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
216 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
218 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
220 st
= ERR_PTR(-ENOMEM
);
224 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
226 st
= ERR_PTR(-ENOMEM
);
232 sg
->length
= obj
->base
.size
;
234 sg_dma_address(sg
) = phys
->busaddr
;
235 sg_dma_len(sg
) = obj
->base
.size
;
237 obj
->phys_handle
= phys
;
241 drm_pci_free(obj
->base
.dev
, phys
);
246 __i915_gem_object_release_shmem(struct drm_i915_gem_object
*obj
,
247 struct sg_table
*pages
,
250 GEM_BUG_ON(obj
->mm
.madv
== __I915_MADV_PURGED
);
252 if (obj
->mm
.madv
== I915_MADV_DONTNEED
)
253 obj
->mm
.dirty
= false;
256 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0 &&
257 !cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
258 drm_clflush_sg(pages
);
260 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
261 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
265 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
,
266 struct sg_table
*pages
)
268 __i915_gem_object_release_shmem(obj
, pages
, false);
271 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
272 char *vaddr
= obj
->phys_handle
->vaddr
;
275 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
279 page
= shmem_read_mapping_page(mapping
, i
);
283 dst
= kmap_atomic(page
);
284 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
285 memcpy(dst
, vaddr
, PAGE_SIZE
);
288 set_page_dirty(page
);
289 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
290 mark_page_accessed(page
);
294 obj
->mm
.dirty
= false;
297 sg_free_table(pages
);
300 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
304 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
306 i915_gem_object_unpin_pages(obj
);
309 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
310 .get_pages
= i915_gem_object_get_pages_phys
,
311 .put_pages
= i915_gem_object_put_pages_phys
,
312 .release
= i915_gem_object_release_phys
,
315 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
317 struct i915_vma
*vma
;
318 LIST_HEAD(still_in_list
);
321 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret
= i915_gem_object_wait(obj
,
329 I915_WAIT_INTERRUPTIBLE
|
332 MAX_SCHEDULE_TIMEOUT
,
337 i915_gem_retire_requests(to_i915(obj
->base
.dev
));
339 while ((vma
= list_first_entry_or_null(&obj
->vma_list
,
342 list_move_tail(&vma
->obj_link
, &still_in_list
);
343 ret
= i915_vma_unbind(vma
);
347 list_splice(&still_in_list
, &obj
->vma_list
);
353 i915_gem_object_wait_fence(struct dma_fence
*fence
,
356 struct intel_rps_client
*rps
)
358 struct drm_i915_gem_request
*rq
;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE
!= 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &fence
->flags
))
365 if (!dma_fence_is_i915(fence
))
366 return dma_fence_wait_timeout(fence
,
367 flags
& I915_WAIT_INTERRUPTIBLE
,
370 rq
= to_request(fence
);
371 if (i915_gem_request_completed(rq
))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq
->i915
) >= 6)
391 gen6_rps_boost(rq
->i915
, rps
, rq
->emitted_jiffies
);
396 timeout
= i915_wait_request(rq
, flags
, timeout
);
399 if (flags
& I915_WAIT_LOCKED
&& i915_gem_request_completed(rq
))
400 i915_gem_request_retire_upto(rq
);
402 if (rps
&& rq
->global_seqno
== intel_engine_last_submit(rq
->engine
)) {
403 /* The GPU is now idle and this client has stalled.
404 * Since no other client has submitted a request in the
405 * meantime, assume that this client is the only one
406 * supplying work to the GPU but is unable to keep that
407 * work supplied because it is waiting. Since the GPU is
408 * then never kept fully busy, RPS autoclocking will
409 * keep the clocks relatively low, causing further delays.
410 * Compensate by giving the synchronous client credit for
411 * a waitboost next time.
413 spin_lock(&rq
->i915
->rps
.client_lock
);
414 list_del_init(&rps
->link
);
415 spin_unlock(&rq
->i915
->rps
.client_lock
);
422 i915_gem_object_wait_reservation(struct reservation_object
*resv
,
425 struct intel_rps_client
*rps
)
427 struct dma_fence
*excl
;
429 if (flags
& I915_WAIT_ALL
) {
430 struct dma_fence
**shared
;
431 unsigned int count
, i
;
434 ret
= reservation_object_get_fences_rcu(resv
,
435 &excl
, &count
, &shared
);
439 for (i
= 0; i
< count
; i
++) {
440 timeout
= i915_gem_object_wait_fence(shared
[i
],
446 dma_fence_put(shared
[i
]);
449 for (; i
< count
; i
++)
450 dma_fence_put(shared
[i
]);
453 excl
= reservation_object_get_excl_rcu(resv
);
456 if (excl
&& timeout
>= 0)
457 timeout
= i915_gem_object_wait_fence(excl
, flags
, timeout
, rps
);
464 static void __fence_set_priority(struct dma_fence
*fence
, int prio
)
466 struct drm_i915_gem_request
*rq
;
467 struct intel_engine_cs
*engine
;
469 if (!dma_fence_is_i915(fence
))
472 rq
= to_request(fence
);
474 if (!engine
->schedule
)
477 engine
->schedule(rq
, prio
);
480 static void fence_set_priority(struct dma_fence
*fence
, int prio
)
482 /* Recurse once into a fence-array */
483 if (dma_fence_is_array(fence
)) {
484 struct dma_fence_array
*array
= to_dma_fence_array(fence
);
487 for (i
= 0; i
< array
->num_fences
; i
++)
488 __fence_set_priority(array
->fences
[i
], prio
);
490 __fence_set_priority(fence
, prio
);
495 i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
499 struct dma_fence
*excl
;
501 if (flags
& I915_WAIT_ALL
) {
502 struct dma_fence
**shared
;
503 unsigned int count
, i
;
506 ret
= reservation_object_get_fences_rcu(obj
->resv
,
507 &excl
, &count
, &shared
);
511 for (i
= 0; i
< count
; i
++) {
512 fence_set_priority(shared
[i
], prio
);
513 dma_fence_put(shared
[i
]);
518 excl
= reservation_object_get_excl_rcu(obj
->resv
);
522 fence_set_priority(excl
, prio
);
529 * Waits for rendering to the object to be completed
530 * @obj: i915 gem object
531 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
532 * @timeout: how long to wait
533 * @rps: client (user process) to charge for any waitboosting
536 i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
539 struct intel_rps_client
*rps
)
542 #if IS_ENABLED(CONFIG_LOCKDEP)
543 GEM_BUG_ON(debug_locks
&&
544 !!lockdep_is_held(&obj
->base
.dev
->struct_mutex
) !=
545 !!(flags
& I915_WAIT_LOCKED
));
547 GEM_BUG_ON(timeout
< 0);
549 timeout
= i915_gem_object_wait_reservation(obj
->resv
,
552 return timeout
< 0 ? timeout
: 0;
555 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
557 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
563 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
568 if (align
> obj
->base
.size
)
571 if (obj
->ops
== &i915_gem_phys_ops
)
574 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
577 if (obj
->base
.filp
== NULL
)
580 ret
= i915_gem_object_unbind(obj
);
584 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
588 obj
->ops
= &i915_gem_phys_ops
;
590 return i915_gem_object_pin_pages(obj
);
594 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
595 struct drm_i915_gem_pwrite
*args
,
596 struct drm_file
*file
)
598 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
599 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
601 /* We manually control the domain here and pretend that it
602 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
604 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
605 if (copy_from_user(vaddr
, user_data
, args
->size
))
608 drm_clflush_virt_range(vaddr
, args
->size
);
609 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
611 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
615 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
)
617 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
620 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
622 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
623 kmem_cache_free(dev_priv
->objects
, obj
);
627 i915_gem_create(struct drm_file
*file
,
628 struct drm_i915_private
*dev_priv
,
632 struct drm_i915_gem_object
*obj
;
636 size
= roundup(size
, PAGE_SIZE
);
640 /* Allocate the new object */
641 obj
= i915_gem_object_create(dev_priv
, size
);
645 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
646 /* drop reference from allocate - handle holds it now */
647 i915_gem_object_put(obj
);
656 i915_gem_dumb_create(struct drm_file
*file
,
657 struct drm_device
*dev
,
658 struct drm_mode_create_dumb
*args
)
660 /* have to work out size/pitch and return them */
661 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
662 args
->size
= args
->pitch
* args
->height
;
663 return i915_gem_create(file
, to_i915(dev
),
664 args
->size
, &args
->handle
);
668 * Creates a new mm object and returns a handle to it.
669 * @dev: drm device pointer
670 * @data: ioctl data blob
671 * @file: drm file pointer
674 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
675 struct drm_file
*file
)
677 struct drm_i915_private
*dev_priv
= to_i915(dev
);
678 struct drm_i915_gem_create
*args
= data
;
680 i915_gem_flush_free_objects(dev_priv
);
682 return i915_gem_create(file
, dev_priv
,
683 args
->size
, &args
->handle
);
687 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
688 const char *gpu_vaddr
, int gpu_offset
,
691 int ret
, cpu_offset
= 0;
694 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
695 int this_length
= min(cacheline_end
- gpu_offset
, length
);
696 int swizzled_gpu_offset
= gpu_offset
^ 64;
698 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
699 gpu_vaddr
+ swizzled_gpu_offset
,
704 cpu_offset
+= this_length
;
705 gpu_offset
+= this_length
;
706 length
-= this_length
;
713 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
714 const char __user
*cpu_vaddr
,
717 int ret
, cpu_offset
= 0;
720 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
721 int this_length
= min(cacheline_end
- gpu_offset
, length
);
722 int swizzled_gpu_offset
= gpu_offset
^ 64;
724 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
725 cpu_vaddr
+ cpu_offset
,
730 cpu_offset
+= this_length
;
731 gpu_offset
+= this_length
;
732 length
-= this_length
;
739 * Pins the specified object's pages and synchronizes the object with
740 * GPU accesses. Sets needs_clflush to non-zero if the caller should
741 * flush the object from the CPU cache.
743 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
744 unsigned int *needs_clflush
)
748 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
751 if (!i915_gem_object_has_struct_page(obj
))
754 ret
= i915_gem_object_wait(obj
,
755 I915_WAIT_INTERRUPTIBLE
|
757 MAX_SCHEDULE_TIMEOUT
,
762 ret
= i915_gem_object_pin_pages(obj
);
766 i915_gem_object_flush_gtt_write_domain(obj
);
768 /* If we're not in the cpu read domain, set ourself into the gtt
769 * read domain and manually flush cachelines (if required). This
770 * optimizes for the case when the gpu will dirty the data
771 * anyway again before the next pread happens.
773 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
774 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
777 if (*needs_clflush
&& !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
778 ret
= i915_gem_object_set_to_cpu_domain(obj
, false);
785 /* return with the pages pinned */
789 i915_gem_object_unpin_pages(obj
);
793 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
794 unsigned int *needs_clflush
)
798 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
801 if (!i915_gem_object_has_struct_page(obj
))
804 ret
= i915_gem_object_wait(obj
,
805 I915_WAIT_INTERRUPTIBLE
|
808 MAX_SCHEDULE_TIMEOUT
,
813 ret
= i915_gem_object_pin_pages(obj
);
817 i915_gem_object_flush_gtt_write_domain(obj
);
819 /* If we're not in the cpu write domain, set ourself into the
820 * gtt write domain and manually flush cachelines (as required).
821 * This optimizes for the case when the gpu will use the data
822 * right away and we therefore have to clflush anyway.
824 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
825 *needs_clflush
|= cpu_write_needs_clflush(obj
) << 1;
827 /* Same trick applies to invalidate partially written cachelines read
830 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
831 *needs_clflush
|= !cpu_cache_is_coherent(obj
->base
.dev
,
834 if (*needs_clflush
&& !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
835 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
842 if ((*needs_clflush
& CLFLUSH_AFTER
) == 0)
843 obj
->cache_dirty
= true;
845 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
846 obj
->mm
.dirty
= true;
847 /* return with the pages pinned */
851 i915_gem_object_unpin_pages(obj
);
856 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
859 if (unlikely(swizzled
)) {
860 unsigned long start
= (unsigned long) addr
;
861 unsigned long end
= (unsigned long) addr
+ length
;
863 /* For swizzling simply ensure that we always flush both
864 * channels. Lame, but simple and it works. Swizzled
865 * pwrite/pread is far from a hotpath - current userspace
866 * doesn't use it at all. */
867 start
= round_down(start
, 128);
868 end
= round_up(end
, 128);
870 drm_clflush_virt_range((void *)start
, end
- start
);
872 drm_clflush_virt_range(addr
, length
);
877 /* Only difference to the fast-path function is that this can handle bit17
878 * and uses non-atomic copy and kmap functions. */
880 shmem_pread_slow(struct page
*page
, int offset
, int length
,
881 char __user
*user_data
,
882 bool page_do_bit17_swizzling
, bool needs_clflush
)
889 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
890 page_do_bit17_swizzling
);
892 if (page_do_bit17_swizzling
)
893 ret
= __copy_to_user_swizzled(user_data
, vaddr
, offset
, length
);
895 ret
= __copy_to_user(user_data
, vaddr
+ offset
, length
);
898 return ret
? - EFAULT
: 0;
902 shmem_pread(struct page
*page
, int offset
, int length
, char __user
*user_data
,
903 bool page_do_bit17_swizzling
, bool needs_clflush
)
908 if (!page_do_bit17_swizzling
) {
909 char *vaddr
= kmap_atomic(page
);
912 drm_clflush_virt_range(vaddr
+ offset
, length
);
913 ret
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
914 kunmap_atomic(vaddr
);
919 return shmem_pread_slow(page
, offset
, length
, user_data
,
920 page_do_bit17_swizzling
, needs_clflush
);
924 i915_gem_shmem_pread(struct drm_i915_gem_object
*obj
,
925 struct drm_i915_gem_pread
*args
)
927 char __user
*user_data
;
929 unsigned int obj_do_bit17_swizzling
;
930 unsigned int needs_clflush
;
931 unsigned int idx
, offset
;
934 obj_do_bit17_swizzling
= 0;
935 if (i915_gem_object_needs_bit17_swizzle(obj
))
936 obj_do_bit17_swizzling
= BIT(17);
938 ret
= mutex_lock_interruptible(&obj
->base
.dev
->struct_mutex
);
942 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
943 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
948 user_data
= u64_to_user_ptr(args
->data_ptr
);
949 offset
= offset_in_page(args
->offset
);
950 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
951 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
955 if (offset
+ length
> PAGE_SIZE
)
956 length
= PAGE_SIZE
- offset
;
958 ret
= shmem_pread(page
, offset
, length
, user_data
,
959 page_to_phys(page
) & obj_do_bit17_swizzling
,
969 i915_gem_obj_finish_shmem_access(obj
);
974 gtt_user_read(struct io_mapping
*mapping
,
975 loff_t base
, int offset
,
976 char __user
*user_data
, int length
)
979 unsigned long unwritten
;
981 /* We can use the cpu mem copy function because this is X86. */
982 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
983 unwritten
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
984 io_mapping_unmap_atomic(vaddr
);
986 vaddr
= (void __force
*)
987 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
988 unwritten
= copy_to_user(user_data
, vaddr
+ offset
, length
);
989 io_mapping_unmap(vaddr
);
995 i915_gem_gtt_pread(struct drm_i915_gem_object
*obj
,
996 const struct drm_i915_gem_pread
*args
)
998 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
999 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1000 struct drm_mm_node node
;
1001 struct i915_vma
*vma
;
1002 void __user
*user_data
;
1006 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1010 intel_runtime_pm_get(i915
);
1011 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1012 PIN_MAPPABLE
| PIN_NONBLOCK
);
1014 node
.start
= i915_ggtt_offset(vma
);
1015 node
.allocated
= false;
1016 ret
= i915_vma_put_fence(vma
);
1018 i915_vma_unpin(vma
);
1023 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1026 GEM_BUG_ON(!node
.allocated
);
1029 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1033 mutex_unlock(&i915
->drm
.struct_mutex
);
1035 user_data
= u64_to_user_ptr(args
->data_ptr
);
1036 remain
= args
->size
;
1037 offset
= args
->offset
;
1039 while (remain
> 0) {
1040 /* Operation in this page
1042 * page_base = page offset within aperture
1043 * page_offset = offset within page
1044 * page_length = bytes to copy for this page
1046 u32 page_base
= node
.start
;
1047 unsigned page_offset
= offset_in_page(offset
);
1048 unsigned page_length
= PAGE_SIZE
- page_offset
;
1049 page_length
= remain
< page_length
? remain
: page_length
;
1050 if (node
.allocated
) {
1052 ggtt
->base
.insert_page(&ggtt
->base
,
1053 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1054 node
.start
, I915_CACHE_NONE
, 0);
1057 page_base
+= offset
& PAGE_MASK
;
1060 if (gtt_user_read(&ggtt
->mappable
, page_base
, page_offset
,
1061 user_data
, page_length
)) {
1066 remain
-= page_length
;
1067 user_data
+= page_length
;
1068 offset
+= page_length
;
1071 mutex_lock(&i915
->drm
.struct_mutex
);
1073 if (node
.allocated
) {
1075 ggtt
->base
.clear_range(&ggtt
->base
,
1076 node
.start
, node
.size
);
1077 remove_mappable_node(&node
);
1079 i915_vma_unpin(vma
);
1082 intel_runtime_pm_put(i915
);
1083 mutex_unlock(&i915
->drm
.struct_mutex
);
1089 * Reads data from the object referenced by handle.
1090 * @dev: drm device pointer
1091 * @data: ioctl data blob
1092 * @file: drm file pointer
1094 * On error, the contents of *data are undefined.
1097 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1098 struct drm_file
*file
)
1100 struct drm_i915_gem_pread
*args
= data
;
1101 struct drm_i915_gem_object
*obj
;
1104 if (args
->size
== 0)
1107 if (!access_ok(VERIFY_WRITE
,
1108 u64_to_user_ptr(args
->data_ptr
),
1112 obj
= i915_gem_object_lookup(file
, args
->handle
);
1116 /* Bounds check source. */
1117 if (range_overflows_t(u64
, args
->offset
, args
->size
, obj
->base
.size
)) {
1122 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
1124 ret
= i915_gem_object_wait(obj
,
1125 I915_WAIT_INTERRUPTIBLE
,
1126 MAX_SCHEDULE_TIMEOUT
,
1127 to_rps_client(file
));
1131 ret
= i915_gem_object_pin_pages(obj
);
1135 ret
= i915_gem_shmem_pread(obj
, args
);
1136 if (ret
== -EFAULT
|| ret
== -ENODEV
)
1137 ret
= i915_gem_gtt_pread(obj
, args
);
1139 i915_gem_object_unpin_pages(obj
);
1141 i915_gem_object_put(obj
);
1145 /* This is the fast write path which cannot handle
1146 * page faults in the source data
1150 ggtt_write(struct io_mapping
*mapping
,
1151 loff_t base
, int offset
,
1152 char __user
*user_data
, int length
)
1155 unsigned long unwritten
;
1157 /* We can use the cpu mem copy function because this is X86. */
1158 vaddr
= (void __force
*)io_mapping_map_atomic_wc(mapping
, base
);
1159 unwritten
= __copy_from_user_inatomic_nocache(vaddr
+ offset
,
1161 io_mapping_unmap_atomic(vaddr
);
1163 vaddr
= (void __force
*)
1164 io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1165 unwritten
= copy_from_user(vaddr
+ offset
, user_data
, length
);
1166 io_mapping_unmap(vaddr
);
1173 * This is the fast pwrite path, where we copy the data directly from the
1174 * user into the GTT, uncached.
1175 * @obj: i915 GEM object
1176 * @args: pwrite arguments structure
1179 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object
*obj
,
1180 const struct drm_i915_gem_pwrite
*args
)
1182 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1183 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1184 struct drm_mm_node node
;
1185 struct i915_vma
*vma
;
1187 void __user
*user_data
;
1190 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1194 intel_runtime_pm_get(i915
);
1195 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1196 PIN_MAPPABLE
| PIN_NONBLOCK
);
1198 node
.start
= i915_ggtt_offset(vma
);
1199 node
.allocated
= false;
1200 ret
= i915_vma_put_fence(vma
);
1202 i915_vma_unpin(vma
);
1207 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1210 GEM_BUG_ON(!node
.allocated
);
1213 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1217 mutex_unlock(&i915
->drm
.struct_mutex
);
1219 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1221 user_data
= u64_to_user_ptr(args
->data_ptr
);
1222 offset
= args
->offset
;
1223 remain
= args
->size
;
1225 /* Operation in this page
1227 * page_base = page offset within aperture
1228 * page_offset = offset within page
1229 * page_length = bytes to copy for this page
1231 u32 page_base
= node
.start
;
1232 unsigned int page_offset
= offset_in_page(offset
);
1233 unsigned int page_length
= PAGE_SIZE
- page_offset
;
1234 page_length
= remain
< page_length
? remain
: page_length
;
1235 if (node
.allocated
) {
1236 wmb(); /* flush the write before we modify the GGTT */
1237 ggtt
->base
.insert_page(&ggtt
->base
,
1238 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1239 node
.start
, I915_CACHE_NONE
, 0);
1240 wmb(); /* flush modifications to the GGTT (insert_page) */
1242 page_base
+= offset
& PAGE_MASK
;
1244 /* If we get a fault while copying data, then (presumably) our
1245 * source page isn't available. Return the error and we'll
1246 * retry in the slow path.
1247 * If the object is non-shmem backed, we retry again with the
1248 * path that handles page fault.
1250 if (ggtt_write(&ggtt
->mappable
, page_base
, page_offset
,
1251 user_data
, page_length
)) {
1256 remain
-= page_length
;
1257 user_data
+= page_length
;
1258 offset
+= page_length
;
1260 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1262 mutex_lock(&i915
->drm
.struct_mutex
);
1264 if (node
.allocated
) {
1266 ggtt
->base
.clear_range(&ggtt
->base
,
1267 node
.start
, node
.size
);
1268 remove_mappable_node(&node
);
1270 i915_vma_unpin(vma
);
1273 intel_runtime_pm_put(i915
);
1274 mutex_unlock(&i915
->drm
.struct_mutex
);
1279 shmem_pwrite_slow(struct page
*page
, int offset
, int length
,
1280 char __user
*user_data
,
1281 bool page_do_bit17_swizzling
,
1282 bool needs_clflush_before
,
1283 bool needs_clflush_after
)
1289 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1290 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1291 page_do_bit17_swizzling
);
1292 if (page_do_bit17_swizzling
)
1293 ret
= __copy_from_user_swizzled(vaddr
, offset
, user_data
,
1296 ret
= __copy_from_user(vaddr
+ offset
, user_data
, length
);
1297 if (needs_clflush_after
)
1298 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1299 page_do_bit17_swizzling
);
1302 return ret
? -EFAULT
: 0;
1305 /* Per-page copy function for the shmem pwrite fastpath.
1306 * Flushes invalid cachelines before writing to the target if
1307 * needs_clflush_before is set and flushes out any written cachelines after
1308 * writing if needs_clflush is set.
1311 shmem_pwrite(struct page
*page
, int offset
, int len
, char __user
*user_data
,
1312 bool page_do_bit17_swizzling
,
1313 bool needs_clflush_before
,
1314 bool needs_clflush_after
)
1319 if (!page_do_bit17_swizzling
) {
1320 char *vaddr
= kmap_atomic(page
);
1322 if (needs_clflush_before
)
1323 drm_clflush_virt_range(vaddr
+ offset
, len
);
1324 ret
= __copy_from_user_inatomic(vaddr
+ offset
, user_data
, len
);
1325 if (needs_clflush_after
)
1326 drm_clflush_virt_range(vaddr
+ offset
, len
);
1328 kunmap_atomic(vaddr
);
1333 return shmem_pwrite_slow(page
, offset
, len
, user_data
,
1334 page_do_bit17_swizzling
,
1335 needs_clflush_before
,
1336 needs_clflush_after
);
1340 i915_gem_shmem_pwrite(struct drm_i915_gem_object
*obj
,
1341 const struct drm_i915_gem_pwrite
*args
)
1343 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1344 void __user
*user_data
;
1346 unsigned int obj_do_bit17_swizzling
;
1347 unsigned int partial_cacheline_write
;
1348 unsigned int needs_clflush
;
1349 unsigned int offset
, idx
;
1352 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1356 ret
= i915_gem_obj_prepare_shmem_write(obj
, &needs_clflush
);
1357 mutex_unlock(&i915
->drm
.struct_mutex
);
1361 obj_do_bit17_swizzling
= 0;
1362 if (i915_gem_object_needs_bit17_swizzle(obj
))
1363 obj_do_bit17_swizzling
= BIT(17);
1365 /* If we don't overwrite a cacheline completely we need to be
1366 * careful to have up-to-date data by first clflushing. Don't
1367 * overcomplicate things and flush the entire patch.
1369 partial_cacheline_write
= 0;
1370 if (needs_clflush
& CLFLUSH_BEFORE
)
1371 partial_cacheline_write
= boot_cpu_data
.x86_clflush_size
- 1;
1373 user_data
= u64_to_user_ptr(args
->data_ptr
);
1374 remain
= args
->size
;
1375 offset
= offset_in_page(args
->offset
);
1376 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
1377 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
1381 if (offset
+ length
> PAGE_SIZE
)
1382 length
= PAGE_SIZE
- offset
;
1384 ret
= shmem_pwrite(page
, offset
, length
, user_data
,
1385 page_to_phys(page
) & obj_do_bit17_swizzling
,
1386 (offset
| length
) & partial_cacheline_write
,
1387 needs_clflush
& CLFLUSH_AFTER
);
1392 user_data
+= length
;
1396 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1397 i915_gem_obj_finish_shmem_access(obj
);
1402 * Writes data to the object referenced by handle.
1404 * @data: ioctl data blob
1407 * On error, the contents of the buffer that were to be modified are undefined.
1410 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1411 struct drm_file
*file
)
1413 struct drm_i915_gem_pwrite
*args
= data
;
1414 struct drm_i915_gem_object
*obj
;
1417 if (args
->size
== 0)
1420 if (!access_ok(VERIFY_READ
,
1421 u64_to_user_ptr(args
->data_ptr
),
1425 obj
= i915_gem_object_lookup(file
, args
->handle
);
1429 /* Bounds check destination. */
1430 if (range_overflows_t(u64
, args
->offset
, args
->size
, obj
->base
.size
)) {
1435 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1437 ret
= i915_gem_object_wait(obj
,
1438 I915_WAIT_INTERRUPTIBLE
|
1440 MAX_SCHEDULE_TIMEOUT
,
1441 to_rps_client(file
));
1445 ret
= i915_gem_object_pin_pages(obj
);
1450 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1451 * it would end up going through the fenced access, and we'll get
1452 * different detiling behavior between reading and writing.
1453 * pread/pwrite currently are reading and writing from the CPU
1454 * perspective, requiring manual detiling by the client.
1456 if (!i915_gem_object_has_struct_page(obj
) ||
1457 cpu_write_needs_clflush(obj
))
1458 /* Note that the gtt paths might fail with non-page-backed user
1459 * pointers (e.g. gtt mappings when moving data between
1460 * textures). Fallback to the shmem path in that case.
1462 ret
= i915_gem_gtt_pwrite_fast(obj
, args
);
1464 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1465 if (obj
->phys_handle
)
1466 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1468 ret
= i915_gem_shmem_pwrite(obj
, args
);
1471 i915_gem_object_unpin_pages(obj
);
1473 i915_gem_object_put(obj
);
1477 static inline enum fb_op_origin
1478 write_origin(struct drm_i915_gem_object
*obj
, unsigned domain
)
1480 return (domain
== I915_GEM_DOMAIN_GTT
?
1481 obj
->frontbuffer_ggtt_origin
: ORIGIN_CPU
);
1484 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object
*obj
)
1486 struct drm_i915_private
*i915
;
1487 struct list_head
*list
;
1488 struct i915_vma
*vma
;
1490 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
1491 if (!i915_vma_is_ggtt(vma
))
1494 if (i915_vma_is_active(vma
))
1497 if (!drm_mm_node_allocated(&vma
->node
))
1500 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
1503 i915
= to_i915(obj
->base
.dev
);
1504 list
= obj
->bind_count
? &i915
->mm
.bound_list
: &i915
->mm
.unbound_list
;
1505 list_move_tail(&obj
->global_link
, list
);
1509 * Called when user space prepares to use an object with the CPU, either
1510 * through the mmap ioctl's mapping or a GTT mapping.
1512 * @data: ioctl data blob
1516 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1517 struct drm_file
*file
)
1519 struct drm_i915_gem_set_domain
*args
= data
;
1520 struct drm_i915_gem_object
*obj
;
1521 uint32_t read_domains
= args
->read_domains
;
1522 uint32_t write_domain
= args
->write_domain
;
1525 /* Only handle setting domains to types used by the CPU. */
1526 if ((write_domain
| read_domains
) & I915_GEM_GPU_DOMAINS
)
1529 /* Having something in the write domain implies it's in the read
1530 * domain, and only that read domain. Enforce that in the request.
1532 if (write_domain
!= 0 && read_domains
!= write_domain
)
1535 obj
= i915_gem_object_lookup(file
, args
->handle
);
1539 /* Try to flush the object off the GPU without holding the lock.
1540 * We will repeat the flush holding the lock in the normal manner
1541 * to catch cases where we are gazumped.
1543 err
= i915_gem_object_wait(obj
,
1544 I915_WAIT_INTERRUPTIBLE
|
1545 (write_domain
? I915_WAIT_ALL
: 0),
1546 MAX_SCHEDULE_TIMEOUT
,
1547 to_rps_client(file
));
1551 /* Flush and acquire obj->pages so that we are coherent through
1552 * direct access in memory with previous cached writes through
1553 * shmemfs and that our cache domain tracking remains valid.
1554 * For example, if the obj->filp was moved to swap without us
1555 * being notified and releasing the pages, we would mistakenly
1556 * continue to assume that the obj remained out of the CPU cached
1559 err
= i915_gem_object_pin_pages(obj
);
1563 err
= i915_mutex_lock_interruptible(dev
);
1567 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1568 err
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1570 err
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1572 /* And bump the LRU for this access */
1573 i915_gem_object_bump_inactive_ggtt(obj
);
1575 mutex_unlock(&dev
->struct_mutex
);
1577 if (write_domain
!= 0)
1578 intel_fb_obj_invalidate(obj
, write_origin(obj
, write_domain
));
1581 i915_gem_object_unpin_pages(obj
);
1583 i915_gem_object_put(obj
);
1588 * Called when user space has done writes to this buffer
1590 * @data: ioctl data blob
1594 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1595 struct drm_file
*file
)
1597 struct drm_i915_gem_sw_finish
*args
= data
;
1598 struct drm_i915_gem_object
*obj
;
1601 obj
= i915_gem_object_lookup(file
, args
->handle
);
1605 /* Pinned buffers may be scanout, so flush the cache */
1606 if (READ_ONCE(obj
->pin_display
)) {
1607 err
= i915_mutex_lock_interruptible(dev
);
1609 i915_gem_object_flush_cpu_write_domain(obj
);
1610 mutex_unlock(&dev
->struct_mutex
);
1614 i915_gem_object_put(obj
);
1619 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1622 * @data: ioctl data blob
1625 * While the mapping holds a reference on the contents of the object, it doesn't
1626 * imply a ref on the object itself.
1630 * DRM driver writers who look a this function as an example for how to do GEM
1631 * mmap support, please don't implement mmap support like here. The modern way
1632 * to implement DRM mmap support is with an mmap offset ioctl (like
1633 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1634 * That way debug tooling like valgrind will understand what's going on, hiding
1635 * the mmap call in a driver private ioctl will break that. The i915 driver only
1636 * does cpu mmaps this way because we didn't know better.
1639 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1640 struct drm_file
*file
)
1642 struct drm_i915_gem_mmap
*args
= data
;
1643 struct drm_i915_gem_object
*obj
;
1646 if (args
->flags
& ~(I915_MMAP_WC
))
1649 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1652 obj
= i915_gem_object_lookup(file
, args
->handle
);
1656 /* prime objects have no backing filp to GEM mmap
1659 if (!obj
->base
.filp
) {
1660 i915_gem_object_put(obj
);
1664 addr
= vm_mmap(obj
->base
.filp
, 0, args
->size
,
1665 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1667 if (args
->flags
& I915_MMAP_WC
) {
1668 struct mm_struct
*mm
= current
->mm
;
1669 struct vm_area_struct
*vma
;
1671 if (down_write_killable(&mm
->mmap_sem
)) {
1672 i915_gem_object_put(obj
);
1675 vma
= find_vma(mm
, addr
);
1678 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1681 up_write(&mm
->mmap_sem
);
1683 /* This may race, but that's ok, it only gets set */
1684 WRITE_ONCE(obj
->frontbuffer_ggtt_origin
, ORIGIN_CPU
);
1686 i915_gem_object_put(obj
);
1687 if (IS_ERR((void *)addr
))
1690 args
->addr_ptr
= (uint64_t) addr
;
1695 static unsigned int tile_row_pages(struct drm_i915_gem_object
*obj
)
1697 return i915_gem_object_get_tile_row_size(obj
) >> PAGE_SHIFT
;
1701 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1703 * A history of the GTT mmap interface:
1705 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1706 * aligned and suitable for fencing, and still fit into the available
1707 * mappable space left by the pinned display objects. A classic problem
1708 * we called the page-fault-of-doom where we would ping-pong between
1709 * two objects that could not fit inside the GTT and so the memcpy
1710 * would page one object in at the expense of the other between every
1713 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1714 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1715 * object is too large for the available space (or simply too large
1716 * for the mappable aperture!), a view is created instead and faulted
1717 * into userspace. (This view is aligned and sized appropriately for
1722 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1723 * hangs on some architectures, corruption on others. An attempt to service
1724 * a GTT page fault from a snoopable object will generate a SIGBUS.
1726 * * the object must be able to fit into RAM (physical memory, though no
1727 * limited to the mappable aperture).
1732 * * a new GTT page fault will synchronize rendering from the GPU and flush
1733 * all data to system memory. Subsequent access will not be synchronized.
1735 * * all mappings are revoked on runtime device suspend.
1737 * * there are only 8, 16 or 32 fence registers to share between all users
1738 * (older machines require fence register for display and blitter access
1739 * as well). Contention of the fence registers will cause the previous users
1740 * to be unmapped and any new access will generate new page faults.
1742 * * running out of memory while servicing a fault may generate a SIGBUS,
1743 * rather than the expected SIGSEGV.
1745 int i915_gem_mmap_gtt_version(void)
1750 static inline struct i915_ggtt_view
1751 compute_partial_view(struct drm_i915_gem_object
*obj
,
1752 pgoff_t page_offset
,
1755 struct i915_ggtt_view view
;
1757 if (i915_gem_object_is_tiled(obj
))
1758 chunk
= roundup(chunk
, tile_row_pages(obj
));
1760 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1761 view
.partial
.offset
= rounddown(page_offset
, chunk
);
1763 min_t(unsigned int, chunk
,
1764 (obj
->base
.size
>> PAGE_SHIFT
) - view
.partial
.offset
);
1766 /* If the partial covers the entire object, just create a normal VMA. */
1767 if (chunk
>= obj
->base
.size
>> PAGE_SHIFT
)
1768 view
.type
= I915_GGTT_VIEW_NORMAL
;
1774 * i915_gem_fault - fault a page into the GTT
1777 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1778 * from userspace. The fault handler takes care of binding the object to
1779 * the GTT (if needed), allocating and programming a fence register (again,
1780 * only if needed based on whether the old reg is still valid or the object
1781 * is tiled) and inserting a new PTE into the faulting process.
1783 * Note that the faulting process may involve evicting existing objects
1784 * from the GTT and/or fence registers to make room. So performance may
1785 * suffer if the GTT working set is large or there are few fence registers
1788 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1789 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1791 int i915_gem_fault(struct vm_fault
*vmf
)
1793 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1794 struct vm_area_struct
*area
= vmf
->vma
;
1795 struct drm_i915_gem_object
*obj
= to_intel_bo(area
->vm_private_data
);
1796 struct drm_device
*dev
= obj
->base
.dev
;
1797 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1798 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1799 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1800 struct i915_vma
*vma
;
1801 pgoff_t page_offset
;
1805 /* We don't use vmf->pgoff since that has the fake offset */
1806 page_offset
= (vmf
->address
- area
->vm_start
) >> PAGE_SHIFT
;
1808 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1810 /* Try to flush the object off the GPU first without holding the lock.
1811 * Upon acquiring the lock, we will perform our sanity checks and then
1812 * repeat the flush holding the lock in the normal manner to catch cases
1813 * where we are gazumped.
1815 ret
= i915_gem_object_wait(obj
,
1816 I915_WAIT_INTERRUPTIBLE
,
1817 MAX_SCHEDULE_TIMEOUT
,
1822 ret
= i915_gem_object_pin_pages(obj
);
1826 intel_runtime_pm_get(dev_priv
);
1828 ret
= i915_mutex_lock_interruptible(dev
);
1832 /* Access to snoopable pages through the GTT is incoherent. */
1833 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev_priv
)) {
1838 /* If the object is smaller than a couple of partial vma, it is
1839 * not worth only creating a single partial vma - we may as well
1840 * clear enough space for the full object.
1842 flags
= PIN_MAPPABLE
;
1843 if (obj
->base
.size
> 2 * MIN_CHUNK_PAGES
<< PAGE_SHIFT
)
1844 flags
|= PIN_NONBLOCK
| PIN_NONFAULT
;
1846 /* Now pin it into the GTT as needed */
1847 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, flags
);
1849 /* Use a partial view if it is bigger than available space */
1850 struct i915_ggtt_view view
=
1851 compute_partial_view(obj
, page_offset
, MIN_CHUNK_PAGES
);
1853 /* Userspace is now writing through an untracked VMA, abandon
1854 * all hope that the hardware is able to track future writes.
1856 obj
->frontbuffer_ggtt_origin
= ORIGIN_CPU
;
1858 vma
= i915_gem_object_ggtt_pin(obj
, &view
, 0, 0, PIN_MAPPABLE
);
1865 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1869 ret
= i915_vma_get_fence(vma
);
1873 /* Mark as being mmapped into userspace for later revocation */
1874 assert_rpm_wakelock_held(dev_priv
);
1875 if (list_empty(&obj
->userfault_link
))
1876 list_add(&obj
->userfault_link
, &dev_priv
->mm
.userfault_list
);
1878 /* Finally, remap it using the new GTT offset */
1879 ret
= remap_io_mapping(area
,
1880 area
->vm_start
+ (vma
->ggtt_view
.partial
.offset
<< PAGE_SHIFT
),
1881 (ggtt
->mappable_base
+ vma
->node
.start
) >> PAGE_SHIFT
,
1882 min_t(u64
, vma
->size
, area
->vm_end
- area
->vm_start
),
1886 __i915_vma_unpin(vma
);
1888 mutex_unlock(&dev
->struct_mutex
);
1890 intel_runtime_pm_put(dev_priv
);
1891 i915_gem_object_unpin_pages(obj
);
1896 * We eat errors when the gpu is terminally wedged to avoid
1897 * userspace unduly crashing (gl has no provisions for mmaps to
1898 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1899 * and so needs to be reported.
1901 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1902 ret
= VM_FAULT_SIGBUS
;
1907 * EAGAIN means the gpu is hung and we'll wait for the error
1908 * handler to reset everything when re-faulting in
1909 * i915_mutex_lock_interruptible.
1916 * EBUSY is ok: this just means that another thread
1917 * already did the job.
1919 ret
= VM_FAULT_NOPAGE
;
1926 ret
= VM_FAULT_SIGBUS
;
1929 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1930 ret
= VM_FAULT_SIGBUS
;
1937 * i915_gem_release_mmap - remove physical page mappings
1938 * @obj: obj in question
1940 * Preserve the reservation of the mmapping with the DRM core code, but
1941 * relinquish ownership of the pages back to the system.
1943 * It is vital that we remove the page mapping if we have mapped a tiled
1944 * object through the GTT and then lose the fence register due to
1945 * resource pressure. Similarly if the object has been moved out of the
1946 * aperture, than pages mapped into userspace must be revoked. Removing the
1947 * mapping will then trigger a page fault on the next user access, allowing
1948 * fixup by i915_gem_fault().
1951 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1953 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1955 /* Serialisation between user GTT access and our code depends upon
1956 * revoking the CPU's PTE whilst the mutex is held. The next user
1957 * pagefault then has to wait until we release the mutex.
1959 * Note that RPM complicates somewhat by adding an additional
1960 * requirement that operations to the GGTT be made holding the RPM
1963 lockdep_assert_held(&i915
->drm
.struct_mutex
);
1964 intel_runtime_pm_get(i915
);
1966 if (list_empty(&obj
->userfault_link
))
1969 list_del_init(&obj
->userfault_link
);
1970 drm_vma_node_unmap(&obj
->base
.vma_node
,
1971 obj
->base
.dev
->anon_inode
->i_mapping
);
1973 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1974 * memory transactions from userspace before we return. The TLB
1975 * flushing implied above by changing the PTE above *should* be
1976 * sufficient, an extra barrier here just provides us with a bit
1977 * of paranoid documentation about our requirement to serialise
1978 * memory writes before touching registers / GSM.
1983 intel_runtime_pm_put(i915
);
1986 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
)
1988 struct drm_i915_gem_object
*obj
, *on
;
1992 * Only called during RPM suspend. All users of the userfault_list
1993 * must be holding an RPM wakeref to ensure that this can not
1994 * run concurrently with themselves (and use the struct_mutex for
1995 * protection between themselves).
1998 list_for_each_entry_safe(obj
, on
,
1999 &dev_priv
->mm
.userfault_list
, userfault_link
) {
2000 list_del_init(&obj
->userfault_link
);
2001 drm_vma_node_unmap(&obj
->base
.vma_node
,
2002 obj
->base
.dev
->anon_inode
->i_mapping
);
2005 /* The fence will be lost when the device powers down. If any were
2006 * in use by hardware (i.e. they are pinned), we should not be powering
2007 * down! All other fences will be reacquired by the user upon waking.
2009 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2010 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2012 /* Ideally we want to assert that the fence register is not
2013 * live at this point (i.e. that no piece of code will be
2014 * trying to write through fence + GTT, as that both violates
2015 * our tracking of activity and associated locking/barriers,
2016 * but also is illegal given that the hw is powered down).
2018 * Previously we used reg->pin_count as a "liveness" indicator.
2019 * That is not sufficient, and we need a more fine-grained
2020 * tool if we want to have a sanity check here.
2026 GEM_BUG_ON(!list_empty(®
->vma
->obj
->userfault_link
));
2031 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2033 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2036 err
= drm_gem_create_mmap_offset(&obj
->base
);
2040 /* Attempt to reap some mmap space from dead objects */
2042 err
= i915_gem_wait_for_idle(dev_priv
, I915_WAIT_INTERRUPTIBLE
);
2046 i915_gem_drain_freed_objects(dev_priv
);
2047 err
= drm_gem_create_mmap_offset(&obj
->base
);
2051 } while (flush_delayed_work(&dev_priv
->gt
.retire_work
));
2056 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2058 drm_gem_free_mmap_offset(&obj
->base
);
2062 i915_gem_mmap_gtt(struct drm_file
*file
,
2063 struct drm_device
*dev
,
2067 struct drm_i915_gem_object
*obj
;
2070 obj
= i915_gem_object_lookup(file
, handle
);
2074 ret
= i915_gem_object_create_mmap_offset(obj
);
2076 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2078 i915_gem_object_put(obj
);
2083 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2085 * @data: GTT mapping ioctl data
2086 * @file: GEM object info
2088 * Simply returns the fake offset to userspace so it can mmap it.
2089 * The mmap call will end up in drm_gem_mmap(), which will set things
2090 * up so we can get faults in the handler above.
2092 * The fault handler will take care of binding the object into the GTT
2093 * (since it may have been evicted to make room for something), allocating
2094 * a fence register, and mapping the appropriate aperture address into
2098 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2099 struct drm_file
*file
)
2101 struct drm_i915_gem_mmap_gtt
*args
= data
;
2103 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2106 /* Immediately discard the backing storage */
2108 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2110 i915_gem_object_free_mmap_offset(obj
);
2112 if (obj
->base
.filp
== NULL
)
2115 /* Our goal here is to return as much of the memory as
2116 * is possible back to the system as we are called from OOM.
2117 * To do this we must instruct the shmfs to drop all of its
2118 * backing pages, *now*.
2120 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2121 obj
->mm
.madv
= __I915_MADV_PURGED
;
2124 /* Try to discard unwanted pages */
2125 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2127 struct address_space
*mapping
;
2129 lockdep_assert_held(&obj
->mm
.lock
);
2130 GEM_BUG_ON(obj
->mm
.pages
);
2132 switch (obj
->mm
.madv
) {
2133 case I915_MADV_DONTNEED
:
2134 i915_gem_object_truncate(obj
);
2135 case __I915_MADV_PURGED
:
2139 if (obj
->base
.filp
== NULL
)
2142 mapping
= obj
->base
.filp
->f_mapping
,
2143 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2147 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
,
2148 struct sg_table
*pages
)
2150 struct sgt_iter sgt_iter
;
2153 __i915_gem_object_release_shmem(obj
, pages
, true);
2155 i915_gem_gtt_finish_pages(obj
, pages
);
2157 if (i915_gem_object_needs_bit17_swizzle(obj
))
2158 i915_gem_object_save_bit_17_swizzle(obj
, pages
);
2160 for_each_sgt_page(page
, sgt_iter
, pages
) {
2162 set_page_dirty(page
);
2164 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
2165 mark_page_accessed(page
);
2169 obj
->mm
.dirty
= false;
2171 sg_free_table(pages
);
2175 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object
*obj
)
2177 struct radix_tree_iter iter
;
2180 radix_tree_for_each_slot(slot
, &obj
->mm
.get_page
.radix
, &iter
, 0)
2181 radix_tree_delete(&obj
->mm
.get_page
.radix
, iter
.index
);
2184 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
2185 enum i915_mm_subclass subclass
)
2187 struct sg_table
*pages
;
2189 if (i915_gem_object_has_pinned_pages(obj
))
2192 GEM_BUG_ON(obj
->bind_count
);
2193 if (!READ_ONCE(obj
->mm
.pages
))
2196 /* May be called by shrinker from within get_pages() (on another bo) */
2197 mutex_lock_nested(&obj
->mm
.lock
, subclass
);
2198 if (unlikely(atomic_read(&obj
->mm
.pages_pin_count
)))
2201 /* ->put_pages might need to allocate memory for the bit17 swizzle
2202 * array, hence protect them from being reaped by removing them from gtt
2204 pages
= fetch_and_zero(&obj
->mm
.pages
);
2207 if (obj
->mm
.mapping
) {
2210 ptr
= ptr_mask_bits(obj
->mm
.mapping
);
2211 if (is_vmalloc_addr(ptr
))
2214 kunmap(kmap_to_page(ptr
));
2216 obj
->mm
.mapping
= NULL
;
2219 __i915_gem_object_reset_page_iter(obj
);
2221 obj
->ops
->put_pages(obj
, pages
);
2223 mutex_unlock(&obj
->mm
.lock
);
2226 static void i915_sg_trim(struct sg_table
*orig_st
)
2228 struct sg_table new_st
;
2229 struct scatterlist
*sg
, *new_sg
;
2232 if (orig_st
->nents
== orig_st
->orig_nents
)
2235 if (sg_alloc_table(&new_st
, orig_st
->nents
, GFP_KERNEL
| __GFP_NOWARN
))
2238 new_sg
= new_st
.sgl
;
2239 for_each_sg(orig_st
->sgl
, sg
, orig_st
->nents
, i
) {
2240 sg_set_page(new_sg
, sg_page(sg
), sg
->length
, 0);
2241 /* called before being DMA mapped, no need to copy sg->dma_* */
2242 new_sg
= sg_next(new_sg
);
2244 GEM_BUG_ON(new_sg
); /* Should walk exactly nents and hit the end */
2246 sg_free_table(orig_st
);
2251 static struct sg_table
*
2252 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2254 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2255 const unsigned long page_count
= obj
->base
.size
/ PAGE_SIZE
;
2257 struct address_space
*mapping
;
2258 struct sg_table
*st
;
2259 struct scatterlist
*sg
;
2260 struct sgt_iter sgt_iter
;
2262 unsigned long last_pfn
= 0; /* suppress gcc warning */
2263 unsigned int max_segment
;
2267 /* Assert that the object is not currently in any GPU domain. As it
2268 * wasn't in the GTT, there shouldn't be any way it could have been in
2271 GEM_BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2272 GEM_BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2274 max_segment
= swiotlb_max_segment();
2276 max_segment
= rounddown(UINT_MAX
, PAGE_SIZE
);
2278 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2280 return ERR_PTR(-ENOMEM
);
2283 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2285 return ERR_PTR(-ENOMEM
);
2288 /* Get the list of pages out of our struct file. They'll be pinned
2289 * at this point until we release them.
2291 * Fail silently without starting the shrinker
2293 mapping
= obj
->base
.filp
->f_mapping
;
2294 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2295 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2298 for (i
= 0; i
< page_count
; i
++) {
2299 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2301 i915_gem_shrink(dev_priv
,
2304 I915_SHRINK_UNBOUND
|
2305 I915_SHRINK_PURGEABLE
);
2306 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2309 /* We've tried hard to allocate the memory by reaping
2310 * our own buffer, now let the real VM do its job and
2311 * go down in flames if truly OOM.
2313 page
= shmem_read_mapping_page(mapping
, i
);
2315 ret
= PTR_ERR(page
);
2320 sg
->length
>= max_segment
||
2321 page_to_pfn(page
) != last_pfn
+ 1) {
2325 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2327 sg
->length
+= PAGE_SIZE
;
2329 last_pfn
= page_to_pfn(page
);
2331 /* Check that the i965g/gm workaround works. */
2332 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2334 if (sg
) /* loop terminated early; short sg table */
2337 /* Trim unused sg entries to avoid wasting memory. */
2340 ret
= i915_gem_gtt_prepare_pages(obj
, st
);
2342 /* DMA remapping failed? One possible cause is that
2343 * it could not reserve enough large entries, asking
2344 * for PAGE_SIZE chunks instead may be helpful.
2346 if (max_segment
> PAGE_SIZE
) {
2347 for_each_sgt_page(page
, sgt_iter
, st
)
2351 max_segment
= PAGE_SIZE
;
2354 dev_warn(&dev_priv
->drm
.pdev
->dev
,
2355 "Failed to DMA remap %lu pages\n",
2361 if (i915_gem_object_needs_bit17_swizzle(obj
))
2362 i915_gem_object_do_bit_17_swizzle(obj
, st
);
2369 for_each_sgt_page(page
, sgt_iter
, st
)
2374 /* shmemfs first checks if there is enough memory to allocate the page
2375 * and reports ENOSPC should there be insufficient, along with the usual
2376 * ENOMEM for a genuine allocation failure.
2378 * We use ENOSPC in our driver to mean that we have run out of aperture
2379 * space and so want to translate the error from shmemfs back to our
2380 * usual understanding of ENOMEM.
2385 return ERR_PTR(ret
);
2388 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2389 struct sg_table
*pages
)
2391 lockdep_assert_held(&obj
->mm
.lock
);
2393 obj
->mm
.get_page
.sg_pos
= pages
->sgl
;
2394 obj
->mm
.get_page
.sg_idx
= 0;
2396 obj
->mm
.pages
= pages
;
2398 if (i915_gem_object_is_tiled(obj
) &&
2399 to_i915(obj
->base
.dev
)->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
2400 GEM_BUG_ON(obj
->mm
.quirked
);
2401 __i915_gem_object_pin_pages(obj
);
2402 obj
->mm
.quirked
= true;
2406 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2408 struct sg_table
*pages
;
2410 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj
));
2412 if (unlikely(obj
->mm
.madv
!= I915_MADV_WILLNEED
)) {
2413 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2417 pages
= obj
->ops
->get_pages(obj
);
2418 if (unlikely(IS_ERR(pages
)))
2419 return PTR_ERR(pages
);
2421 __i915_gem_object_set_pages(obj
, pages
);
2425 /* Ensure that the associated pages are gathered from the backing storage
2426 * and pinned into our object. i915_gem_object_pin_pages() may be called
2427 * multiple times before they are released by a single call to
2428 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2429 * either as a result of memory pressure (reaping pages under the shrinker)
2430 * or as the object is itself released.
2432 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2436 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
2440 if (unlikely(!obj
->mm
.pages
)) {
2441 err
= ____i915_gem_object_get_pages(obj
);
2445 smp_mb__before_atomic();
2447 atomic_inc(&obj
->mm
.pages_pin_count
);
2450 mutex_unlock(&obj
->mm
.lock
);
2454 /* The 'mapping' part of i915_gem_object_pin_map() below */
2455 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
,
2456 enum i915_map_type type
)
2458 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2459 struct sg_table
*sgt
= obj
->mm
.pages
;
2460 struct sgt_iter sgt_iter
;
2462 struct page
*stack_pages
[32];
2463 struct page
**pages
= stack_pages
;
2464 unsigned long i
= 0;
2468 /* A single page can always be kmapped */
2469 if (n_pages
== 1 && type
== I915_MAP_WB
)
2470 return kmap(sg_page(sgt
->sgl
));
2472 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2473 /* Too big for stack -- allocate temporary array instead */
2474 pages
= drm_malloc_gfp(n_pages
, sizeof(*pages
), GFP_TEMPORARY
);
2479 for_each_sgt_page(page
, sgt_iter
, sgt
)
2482 /* Check that we have the expected number of pages */
2483 GEM_BUG_ON(i
!= n_pages
);
2487 pgprot
= PAGE_KERNEL
;
2490 pgprot
= pgprot_writecombine(PAGE_KERNEL_IO
);
2493 addr
= vmap(pages
, n_pages
, 0, pgprot
);
2495 if (pages
!= stack_pages
)
2496 drm_free_large(pages
);
2501 /* get, pin, and map the pages of the object into kernel space */
2502 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
2503 enum i915_map_type type
)
2505 enum i915_map_type has_type
;
2510 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
2512 ret
= mutex_lock_interruptible(&obj
->mm
.lock
);
2514 return ERR_PTR(ret
);
2517 if (!atomic_inc_not_zero(&obj
->mm
.pages_pin_count
)) {
2518 if (unlikely(!obj
->mm
.pages
)) {
2519 ret
= ____i915_gem_object_get_pages(obj
);
2523 smp_mb__before_atomic();
2525 atomic_inc(&obj
->mm
.pages_pin_count
);
2528 GEM_BUG_ON(!obj
->mm
.pages
);
2530 ptr
= ptr_unpack_bits(obj
->mm
.mapping
, has_type
);
2531 if (ptr
&& has_type
!= type
) {
2537 if (is_vmalloc_addr(ptr
))
2540 kunmap(kmap_to_page(ptr
));
2542 ptr
= obj
->mm
.mapping
= NULL
;
2546 ptr
= i915_gem_object_map(obj
, type
);
2552 obj
->mm
.mapping
= ptr_pack_bits(ptr
, type
);
2556 mutex_unlock(&obj
->mm
.lock
);
2560 atomic_dec(&obj
->mm
.pages_pin_count
);
2566 static bool ban_context(const struct i915_gem_context
*ctx
)
2568 return (i915_gem_context_is_bannable(ctx
) &&
2569 ctx
->ban_score
>= CONTEXT_SCORE_BAN_THRESHOLD
);
2572 static void i915_gem_context_mark_guilty(struct i915_gem_context
*ctx
)
2574 ctx
->guilty_count
++;
2575 ctx
->ban_score
+= CONTEXT_SCORE_GUILTY
;
2576 if (ban_context(ctx
))
2577 i915_gem_context_set_banned(ctx
);
2579 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2580 ctx
->name
, ctx
->ban_score
,
2581 yesno(i915_gem_context_is_banned(ctx
)));
2583 if (!i915_gem_context_is_banned(ctx
) || IS_ERR_OR_NULL(ctx
->file_priv
))
2586 ctx
->file_priv
->context_bans
++;
2587 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2588 ctx
->name
, ctx
->file_priv
->context_bans
);
2591 static void i915_gem_context_mark_innocent(struct i915_gem_context
*ctx
)
2593 ctx
->active_count
++;
2596 struct drm_i915_gem_request
*
2597 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2599 struct drm_i915_gem_request
*request
;
2601 /* We are called by the error capture and reset at a random
2602 * point in time. In particular, note that neither is crucially
2603 * ordered with an interrupt. After a hang, the GPU is dead and we
2604 * assume that no more writes can happen (we waited long enough for
2605 * all writes that were in transaction to be flushed) - adding an
2606 * extra delay for a recent interrupt is pointless. Hence, we do
2607 * not need an engine->irq_seqno_barrier() before the seqno reads.
2609 list_for_each_entry(request
, &engine
->timeline
->requests
, link
) {
2610 if (__i915_gem_request_completed(request
))
2613 GEM_BUG_ON(request
->engine
!= engine
);
2620 static bool engine_stalled(struct intel_engine_cs
*engine
)
2622 if (!engine
->hangcheck
.stalled
)
2625 /* Check for possible seqno movement after hang declaration */
2626 if (engine
->hangcheck
.seqno
!= intel_engine_get_seqno(engine
)) {
2627 DRM_DEBUG_DRIVER("%s pardoned\n", engine
->name
);
2634 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
)
2636 struct intel_engine_cs
*engine
;
2637 enum intel_engine_id id
;
2640 /* Ensure irq handler finishes, and not run again. */
2641 for_each_engine(engine
, dev_priv
, id
) {
2642 struct drm_i915_gem_request
*request
;
2644 tasklet_kill(&engine
->irq_tasklet
);
2646 if (engine_stalled(engine
)) {
2647 request
= i915_gem_find_active_request(engine
);
2648 if (request
&& request
->fence
.error
== -EIO
)
2649 err
= -EIO
; /* Previous reset failed! */
2653 i915_gem_revoke_fences(dev_priv
);
2658 static void skip_request(struct drm_i915_gem_request
*request
)
2660 void *vaddr
= request
->ring
->vaddr
;
2663 /* As this request likely depends on state from the lost
2664 * context, clear out all the user operations leaving the
2665 * breadcrumb at the end (so we get the fence notifications).
2667 head
= request
->head
;
2668 if (request
->postfix
< head
) {
2669 memset(vaddr
+ head
, 0, request
->ring
->size
- head
);
2672 memset(vaddr
+ head
, 0, request
->postfix
- head
);
2674 dma_fence_set_error(&request
->fence
, -EIO
);
2677 static void engine_skip_context(struct drm_i915_gem_request
*request
)
2679 struct intel_engine_cs
*engine
= request
->engine
;
2680 struct i915_gem_context
*hung_ctx
= request
->ctx
;
2681 struct intel_timeline
*timeline
;
2682 unsigned long flags
;
2684 timeline
= i915_gem_context_lookup_timeline(hung_ctx
, engine
);
2686 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2687 spin_lock(&timeline
->lock
);
2689 list_for_each_entry_continue(request
, &engine
->timeline
->requests
, link
)
2690 if (request
->ctx
== hung_ctx
)
2691 skip_request(request
);
2693 list_for_each_entry(request
, &timeline
->requests
, link
)
2694 skip_request(request
);
2696 spin_unlock(&timeline
->lock
);
2697 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2700 /* Returns true if the request was guilty of hang */
2701 static bool i915_gem_reset_request(struct drm_i915_gem_request
*request
)
2703 /* Read once and return the resolution */
2704 const bool guilty
= engine_stalled(request
->engine
);
2706 /* The guilty request will get skipped on a hung engine.
2708 * Users of client default contexts do not rely on logical
2709 * state preserved between batches so it is safe to execute
2710 * queued requests following the hang. Non default contexts
2711 * rely on preserved state, so skipping a batch loses the
2712 * evolution of the state and it needs to be considered corrupted.
2713 * Executing more queued batches on top of corrupted state is
2714 * risky. But we take the risk by trying to advance through
2715 * the queued requests in order to make the client behaviour
2716 * more predictable around resets, by not throwing away random
2717 * amount of batches it has prepared for execution. Sophisticated
2718 * clients can use gem_reset_stats_ioctl and dma fence status
2719 * (exported via sync_file info ioctl on explicit fences) to observe
2720 * when it loses the context state and should rebuild accordingly.
2722 * The context ban, and ultimately the client ban, mechanism are safety
2723 * valves if client submission ends up resulting in nothing more than
2728 i915_gem_context_mark_guilty(request
->ctx
);
2729 skip_request(request
);
2731 i915_gem_context_mark_innocent(request
->ctx
);
2732 dma_fence_set_error(&request
->fence
, -EAGAIN
);
2738 static void i915_gem_reset_engine(struct intel_engine_cs
*engine
)
2740 struct drm_i915_gem_request
*request
;
2742 if (engine
->irq_seqno_barrier
)
2743 engine
->irq_seqno_barrier(engine
);
2745 request
= i915_gem_find_active_request(engine
);
2746 if (request
&& i915_gem_reset_request(request
)) {
2747 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2748 engine
->name
, request
->global_seqno
);
2750 /* If this context is now banned, skip all pending requests. */
2751 if (i915_gem_context_is_banned(request
->ctx
))
2752 engine_skip_context(request
);
2755 /* Setup the CS to resume from the breadcrumb of the hung request */
2756 engine
->reset_hw(engine
, request
);
2759 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
)
2761 struct intel_engine_cs
*engine
;
2762 enum intel_engine_id id
;
2764 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2766 i915_gem_retire_requests(dev_priv
);
2768 for_each_engine(engine
, dev_priv
, id
)
2769 i915_gem_reset_engine(engine
);
2771 i915_gem_restore_fences(dev_priv
);
2773 if (dev_priv
->gt
.awake
) {
2774 intel_sanitize_gt_powersave(dev_priv
);
2775 intel_enable_gt_powersave(dev_priv
);
2776 if (INTEL_GEN(dev_priv
) >= 6)
2777 gen6_rps_busy(dev_priv
);
2781 static void nop_submit_request(struct drm_i915_gem_request
*request
)
2783 dma_fence_set_error(&request
->fence
, -EIO
);
2784 i915_gem_request_submit(request
);
2785 intel_engine_init_global_seqno(request
->engine
, request
->global_seqno
);
2788 static void engine_set_wedged(struct intel_engine_cs
*engine
)
2790 struct drm_i915_gem_request
*request
;
2791 unsigned long flags
;
2793 /* We need to be sure that no thread is running the old callback as
2794 * we install the nop handler (otherwise we would submit a request
2795 * to hardware that will never complete). In order to prevent this
2796 * race, we wait until the machine is idle before making the swap
2797 * (using stop_machine()).
2799 engine
->submit_request
= nop_submit_request
;
2801 /* Mark all executing requests as skipped */
2802 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2803 list_for_each_entry(request
, &engine
->timeline
->requests
, link
)
2804 dma_fence_set_error(&request
->fence
, -EIO
);
2805 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2807 /* Mark all pending requests as complete so that any concurrent
2808 * (lockless) lookup doesn't try and wait upon the request as we
2811 intel_engine_init_global_seqno(engine
,
2812 intel_engine_last_submit(engine
));
2815 * Clear the execlists queue up before freeing the requests, as those
2816 * are the ones that keep the context and ringbuffer backing objects
2820 if (i915
.enable_execlists
) {
2821 unsigned long flags
;
2823 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2825 i915_gem_request_put(engine
->execlist_port
[0].request
);
2826 i915_gem_request_put(engine
->execlist_port
[1].request
);
2827 memset(engine
->execlist_port
, 0, sizeof(engine
->execlist_port
));
2828 engine
->execlist_queue
= RB_ROOT
;
2829 engine
->execlist_first
= NULL
;
2831 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2835 static int __i915_gem_set_wedged_BKL(void *data
)
2837 struct drm_i915_private
*i915
= data
;
2838 struct intel_engine_cs
*engine
;
2839 enum intel_engine_id id
;
2841 for_each_engine(engine
, i915
, id
)
2842 engine_set_wedged(engine
);
2847 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
)
2849 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2850 set_bit(I915_WEDGED
, &dev_priv
->gpu_error
.flags
);
2852 stop_machine(__i915_gem_set_wedged_BKL
, dev_priv
, NULL
);
2854 i915_gem_context_lost(dev_priv
);
2855 i915_gem_retire_requests(dev_priv
);
2857 mod_delayed_work(dev_priv
->wq
, &dev_priv
->gt
.idle_work
, 0);
2861 i915_gem_retire_work_handler(struct work_struct
*work
)
2863 struct drm_i915_private
*dev_priv
=
2864 container_of(work
, typeof(*dev_priv
), gt
.retire_work
.work
);
2865 struct drm_device
*dev
= &dev_priv
->drm
;
2867 /* Come back later if the device is busy... */
2868 if (mutex_trylock(&dev
->struct_mutex
)) {
2869 i915_gem_retire_requests(dev_priv
);
2870 mutex_unlock(&dev
->struct_mutex
);
2873 /* Keep the retire handler running until we are finally idle.
2874 * We do not need to do this test under locking as in the worst-case
2875 * we queue the retire worker once too often.
2877 if (READ_ONCE(dev_priv
->gt
.awake
)) {
2878 i915_queue_hangcheck(dev_priv
);
2879 queue_delayed_work(dev_priv
->wq
,
2880 &dev_priv
->gt
.retire_work
,
2881 round_jiffies_up_relative(HZ
));
2886 i915_gem_idle_work_handler(struct work_struct
*work
)
2888 struct drm_i915_private
*dev_priv
=
2889 container_of(work
, typeof(*dev_priv
), gt
.idle_work
.work
);
2890 struct drm_device
*dev
= &dev_priv
->drm
;
2891 struct intel_engine_cs
*engine
;
2892 enum intel_engine_id id
;
2893 bool rearm_hangcheck
;
2895 if (!READ_ONCE(dev_priv
->gt
.awake
))
2899 * Wait for last execlists context complete, but bail out in case a
2900 * new request is submitted.
2902 wait_for(READ_ONCE(dev_priv
->gt
.active_requests
) ||
2903 intel_execlists_idle(dev_priv
), 10);
2905 if (READ_ONCE(dev_priv
->gt
.active_requests
))
2909 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
2911 if (!mutex_trylock(&dev
->struct_mutex
)) {
2912 /* Currently busy, come back later */
2913 mod_delayed_work(dev_priv
->wq
,
2914 &dev_priv
->gt
.idle_work
,
2915 msecs_to_jiffies(50));
2920 * New request retired after this work handler started, extend active
2921 * period until next instance of the work.
2923 if (work_pending(work
))
2926 if (dev_priv
->gt
.active_requests
)
2929 if (wait_for(intel_execlists_idle(dev_priv
), 10))
2930 DRM_ERROR("Timeout waiting for engines to idle\n");
2932 for_each_engine(engine
, dev_priv
, id
)
2933 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2935 GEM_BUG_ON(!dev_priv
->gt
.awake
);
2936 dev_priv
->gt
.awake
= false;
2937 rearm_hangcheck
= false;
2939 if (INTEL_GEN(dev_priv
) >= 6)
2940 gen6_rps_idle(dev_priv
);
2941 intel_runtime_pm_put(dev_priv
);
2943 mutex_unlock(&dev
->struct_mutex
);
2946 if (rearm_hangcheck
) {
2947 GEM_BUG_ON(!dev_priv
->gt
.awake
);
2948 i915_queue_hangcheck(dev_priv
);
2952 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
)
2954 struct drm_i915_gem_object
*obj
= to_intel_bo(gem
);
2955 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
2956 struct i915_vma
*vma
, *vn
;
2958 mutex_lock(&obj
->base
.dev
->struct_mutex
);
2959 list_for_each_entry_safe(vma
, vn
, &obj
->vma_list
, obj_link
)
2960 if (vma
->vm
->file
== fpriv
)
2961 i915_vma_close(vma
);
2963 if (i915_gem_object_is_active(obj
) &&
2964 !i915_gem_object_has_active_reference(obj
)) {
2965 i915_gem_object_set_active_reference(obj
);
2966 i915_gem_object_get(obj
);
2968 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
2971 static unsigned long to_wait_timeout(s64 timeout_ns
)
2974 return MAX_SCHEDULE_TIMEOUT
;
2976 if (timeout_ns
== 0)
2979 return nsecs_to_jiffies_timeout(timeout_ns
);
2983 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2984 * @dev: drm device pointer
2985 * @data: ioctl data blob
2986 * @file: drm file pointer
2988 * Returns 0 if successful, else an error is returned with the remaining time in
2989 * the timeout parameter.
2990 * -ETIME: object is still busy after timeout
2991 * -ERESTARTSYS: signal interrupted the wait
2992 * -ENONENT: object doesn't exist
2993 * Also possible, but rare:
2994 * -EAGAIN: GPU wedged
2996 * -ENODEV: Internal IRQ fail
2997 * -E?: The add request failed
2999 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3000 * non-zero timeout parameter the wait ioctl will wait for the given number of
3001 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3002 * without holding struct_mutex the object may become re-busied before this
3003 * function completes. A similar but shorter * race condition exists in the busy
3007 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3009 struct drm_i915_gem_wait
*args
= data
;
3010 struct drm_i915_gem_object
*obj
;
3014 if (args
->flags
!= 0)
3017 obj
= i915_gem_object_lookup(file
, args
->bo_handle
);
3021 start
= ktime_get();
3023 ret
= i915_gem_object_wait(obj
,
3024 I915_WAIT_INTERRUPTIBLE
| I915_WAIT_ALL
,
3025 to_wait_timeout(args
->timeout_ns
),
3026 to_rps_client(file
));
3028 if (args
->timeout_ns
> 0) {
3029 args
->timeout_ns
-= ktime_to_ns(ktime_sub(ktime_get(), start
));
3030 if (args
->timeout_ns
< 0)
3031 args
->timeout_ns
= 0;
3034 i915_gem_object_put(obj
);
3038 static int wait_for_timeline(struct i915_gem_timeline
*tl
, unsigned int flags
)
3042 for (i
= 0; i
< ARRAY_SIZE(tl
->engine
); i
++) {
3043 ret
= i915_gem_active_wait(&tl
->engine
[i
].last_request
, flags
);
3051 int i915_gem_wait_for_idle(struct drm_i915_private
*i915
, unsigned int flags
)
3055 if (flags
& I915_WAIT_LOCKED
) {
3056 struct i915_gem_timeline
*tl
;
3058 lockdep_assert_held(&i915
->drm
.struct_mutex
);
3060 list_for_each_entry(tl
, &i915
->gt
.timelines
, link
) {
3061 ret
= wait_for_timeline(tl
, flags
);
3066 ret
= wait_for_timeline(&i915
->gt
.global_timeline
, flags
);
3074 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3077 /* If we don't have a page list set up, then we're not pinned
3078 * to GPU, and we can ignore the cache flush because it'll happen
3079 * again at bind time.
3085 * Stolen memory is always coherent with the GPU as it is explicitly
3086 * marked as wc by the system, or the system is cache-coherent.
3088 if (obj
->stolen
|| obj
->phys_handle
)
3091 /* If the GPU is snooping the contents of the CPU cache,
3092 * we do not need to manually clear the CPU cache lines. However,
3093 * the caches are only snooped when the render cache is
3094 * flushed/invalidated. As we always have to emit invalidations
3095 * and flushes when moving into and out of the RENDER domain, correct
3096 * snooping behaviour occurs naturally as the result of our domain
3099 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3100 obj
->cache_dirty
= true;
3104 trace_i915_gem_object_clflush(obj
);
3105 drm_clflush_sg(obj
->mm
.pages
);
3106 obj
->cache_dirty
= false;
3109 /** Flushes the GTT write domain for the object if it's dirty. */
3111 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3113 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3115 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3118 /* No actual flushing is required for the GTT write domain. Writes
3119 * to it "immediately" go to main memory as far as we know, so there's
3120 * no chipset flush. It also doesn't land in render cache.
3122 * However, we do have to enforce the order so that all writes through
3123 * the GTT land before any writes to the device, such as updates to
3126 * We also have to wait a bit for the writes to land from the GTT.
3127 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3128 * timing. This issue has only been observed when switching quickly
3129 * between GTT writes and CPU reads from inside the kernel on recent hw,
3130 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3131 * system agents we cannot reproduce this behaviour).
3134 if (INTEL_GEN(dev_priv
) >= 6 && !HAS_LLC(dev_priv
))
3135 POSTING_READ(RING_ACTHD(dev_priv
->engine
[RCS
]->mmio_base
));
3137 intel_fb_obj_flush(obj
, false, write_origin(obj
, I915_GEM_DOMAIN_GTT
));
3139 obj
->base
.write_domain
= 0;
3140 trace_i915_gem_object_change_domain(obj
,
3141 obj
->base
.read_domains
,
3142 I915_GEM_DOMAIN_GTT
);
3145 /** Flushes the CPU write domain for the object if it's dirty. */
3147 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3149 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3152 i915_gem_clflush_object(obj
, obj
->pin_display
);
3153 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3155 obj
->base
.write_domain
= 0;
3156 trace_i915_gem_object_change_domain(obj
,
3157 obj
->base
.read_domains
,
3158 I915_GEM_DOMAIN_CPU
);
3162 * Moves a single object to the GTT read, and possibly write domain.
3163 * @obj: object to act on
3164 * @write: ask for write access or read only
3166 * This function returns when the move is complete, including waiting on
3170 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3172 uint32_t old_write_domain
, old_read_domains
;
3175 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3177 ret
= i915_gem_object_wait(obj
,
3178 I915_WAIT_INTERRUPTIBLE
|
3180 (write
? I915_WAIT_ALL
: 0),
3181 MAX_SCHEDULE_TIMEOUT
,
3186 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3189 /* Flush and acquire obj->pages so that we are coherent through
3190 * direct access in memory with previous cached writes through
3191 * shmemfs and that our cache domain tracking remains valid.
3192 * For example, if the obj->filp was moved to swap without us
3193 * being notified and releasing the pages, we would mistakenly
3194 * continue to assume that the obj remained out of the CPU cached
3197 ret
= i915_gem_object_pin_pages(obj
);
3201 i915_gem_object_flush_cpu_write_domain(obj
);
3203 /* Serialise direct access to this object with the barriers for
3204 * coherent writes from the GPU, by effectively invalidating the
3205 * GTT domain upon first access.
3207 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3210 old_write_domain
= obj
->base
.write_domain
;
3211 old_read_domains
= obj
->base
.read_domains
;
3213 /* It should now be out of any other write domains, and we can update
3214 * the domain values for our changes.
3216 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3217 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3219 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3220 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3221 obj
->mm
.dirty
= true;
3224 trace_i915_gem_object_change_domain(obj
,
3228 i915_gem_object_unpin_pages(obj
);
3233 * Changes the cache-level of an object across all VMA.
3234 * @obj: object to act on
3235 * @cache_level: new cache level to set for the object
3237 * After this function returns, the object will be in the new cache-level
3238 * across all GTT and the contents of the backing storage will be coherent,
3239 * with respect to the new cache-level. In order to keep the backing storage
3240 * coherent for all users, we only allow a single cache level to be set
3241 * globally on the object and prevent it from being changed whilst the
3242 * hardware is reading from the object. That is if the object is currently
3243 * on the scanout it will be set to uncached (or equivalent display
3244 * cache coherency) and all non-MOCS GPU access will also be uncached so
3245 * that all direct access to the scanout remains coherent.
3247 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3248 enum i915_cache_level cache_level
)
3250 struct i915_vma
*vma
;
3253 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3255 if (obj
->cache_level
== cache_level
)
3258 /* Inspect the list of currently bound VMA and unbind any that would
3259 * be invalid given the new cache-level. This is principally to
3260 * catch the issue of the CS prefetch crossing page boundaries and
3261 * reading an invalid PTE on older architectures.
3264 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3265 if (!drm_mm_node_allocated(&vma
->node
))
3268 if (i915_vma_is_pinned(vma
)) {
3269 DRM_DEBUG("can not change the cache level of pinned objects\n");
3273 if (i915_gem_valid_gtt_space(vma
, cache_level
))
3276 ret
= i915_vma_unbind(vma
);
3280 /* As unbinding may affect other elements in the
3281 * obj->vma_list (due to side-effects from retiring
3282 * an active vma), play safe and restart the iterator.
3287 /* We can reuse the existing drm_mm nodes but need to change the
3288 * cache-level on the PTE. We could simply unbind them all and
3289 * rebind with the correct cache-level on next use. However since
3290 * we already have a valid slot, dma mapping, pages etc, we may as
3291 * rewrite the PTE in the belief that doing so tramples upon less
3292 * state and so involves less work.
3294 if (obj
->bind_count
) {
3295 /* Before we change the PTE, the GPU must not be accessing it.
3296 * If we wait upon the object, we know that all the bound
3297 * VMA are no longer active.
3299 ret
= i915_gem_object_wait(obj
,
3300 I915_WAIT_INTERRUPTIBLE
|
3303 MAX_SCHEDULE_TIMEOUT
,
3308 if (!HAS_LLC(to_i915(obj
->base
.dev
)) &&
3309 cache_level
!= I915_CACHE_NONE
) {
3310 /* Access to snoopable pages through the GTT is
3311 * incoherent and on some machines causes a hard
3312 * lockup. Relinquish the CPU mmaping to force
3313 * userspace to refault in the pages and we can
3314 * then double check if the GTT mapping is still
3315 * valid for that pointer access.
3317 i915_gem_release_mmap(obj
);
3319 /* As we no longer need a fence for GTT access,
3320 * we can relinquish it now (and so prevent having
3321 * to steal a fence from someone else on the next
3322 * fence request). Note GPU activity would have
3323 * dropped the fence as all snoopable access is
3324 * supposed to be linear.
3326 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3327 ret
= i915_vma_put_fence(vma
);
3332 /* We either have incoherent backing store and
3333 * so no GTT access or the architecture is fully
3334 * coherent. In such cases, existing GTT mmaps
3335 * ignore the cache bit in the PTE and we can
3336 * rewrite it without confusing the GPU or having
3337 * to force userspace to fault back in its mmaps.
3341 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3342 if (!drm_mm_node_allocated(&vma
->node
))
3345 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3351 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
&&
3352 cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3353 obj
->cache_dirty
= true;
3355 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3356 vma
->node
.color
= cache_level
;
3357 obj
->cache_level
= cache_level
;
3362 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3363 struct drm_file
*file
)
3365 struct drm_i915_gem_caching
*args
= data
;
3366 struct drm_i915_gem_object
*obj
;
3370 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3376 switch (obj
->cache_level
) {
3377 case I915_CACHE_LLC
:
3378 case I915_CACHE_L3_LLC
:
3379 args
->caching
= I915_CACHING_CACHED
;
3383 args
->caching
= I915_CACHING_DISPLAY
;
3387 args
->caching
= I915_CACHING_NONE
;
3395 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3396 struct drm_file
*file
)
3398 struct drm_i915_private
*i915
= to_i915(dev
);
3399 struct drm_i915_gem_caching
*args
= data
;
3400 struct drm_i915_gem_object
*obj
;
3401 enum i915_cache_level level
;
3404 switch (args
->caching
) {
3405 case I915_CACHING_NONE
:
3406 level
= I915_CACHE_NONE
;
3408 case I915_CACHING_CACHED
:
3410 * Due to a HW issue on BXT A stepping, GPU stores via a
3411 * snooped mapping may leave stale data in a corresponding CPU
3412 * cacheline, whereas normally such cachelines would get
3415 if (!HAS_LLC(i915
) && !HAS_SNOOP(i915
))
3418 level
= I915_CACHE_LLC
;
3420 case I915_CACHING_DISPLAY
:
3421 level
= HAS_WT(i915
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3427 obj
= i915_gem_object_lookup(file
, args
->handle
);
3431 if (obj
->cache_level
== level
)
3434 ret
= i915_gem_object_wait(obj
,
3435 I915_WAIT_INTERRUPTIBLE
,
3436 MAX_SCHEDULE_TIMEOUT
,
3437 to_rps_client(file
));
3441 ret
= i915_mutex_lock_interruptible(dev
);
3445 ret
= i915_gem_object_set_cache_level(obj
, level
);
3446 mutex_unlock(&dev
->struct_mutex
);
3449 i915_gem_object_put(obj
);
3454 * Prepare buffer for display plane (scanout, cursors, etc).
3455 * Can be called from an uninterruptible phase (modesetting) and allows
3456 * any flushes to be pipelined (for pageflips).
3459 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3461 const struct i915_ggtt_view
*view
)
3463 struct i915_vma
*vma
;
3464 u32 old_read_domains
, old_write_domain
;
3467 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3469 /* Mark the pin_display early so that we account for the
3470 * display coherency whilst setting up the cache domains.
3474 /* The display engine is not coherent with the LLC cache on gen6. As
3475 * a result, we make sure that the pinning that is about to occur is
3476 * done with uncached PTEs. This is lowest common denominator for all
3479 * However for gen6+, we could do better by using the GFDT bit instead
3480 * of uncaching, which would allow us to flush all the LLC-cached data
3481 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3483 ret
= i915_gem_object_set_cache_level(obj
,
3484 HAS_WT(to_i915(obj
->base
.dev
)) ?
3485 I915_CACHE_WT
: I915_CACHE_NONE
);
3488 goto err_unpin_display
;
3491 /* As the user may map the buffer once pinned in the display plane
3492 * (e.g. libkms for the bootup splash), we have to ensure that we
3493 * always use map_and_fenceable for all scanout buffers. However,
3494 * it may simply be too big to fit into mappable, in which case
3495 * put it anyway and hope that userspace can cope (but always first
3496 * try to preserve the existing ABI).
3498 vma
= ERR_PTR(-ENOSPC
);
3499 if (!view
|| view
->type
== I915_GGTT_VIEW_NORMAL
)
3500 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
,
3501 PIN_MAPPABLE
| PIN_NONBLOCK
);
3503 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3506 /* Valleyview is definitely limited to scanning out the first
3507 * 512MiB. Lets presume this behaviour was inherited from the
3508 * g4x display engine and that all earlier gen are similarly
3509 * limited. Testing suggests that it is a little more
3510 * complicated than this. For example, Cherryview appears quite
3511 * happy to scanout from anywhere within its global aperture.
3514 if (HAS_GMCH_DISPLAY(i915
))
3515 flags
= PIN_MAPPABLE
;
3516 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
, flags
);
3519 goto err_unpin_display
;
3521 vma
->display_alignment
= max_t(u64
, vma
->display_alignment
, alignment
);
3523 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3524 if (obj
->cache_dirty
|| obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3525 i915_gem_clflush_object(obj
, true);
3526 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
3529 old_write_domain
= obj
->base
.write_domain
;
3530 old_read_domains
= obj
->base
.read_domains
;
3532 /* It should now be out of any other write domains, and we can update
3533 * the domain values for our changes.
3535 obj
->base
.write_domain
= 0;
3536 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3538 trace_i915_gem_object_change_domain(obj
,
3550 i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
)
3552 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
3554 if (WARN_ON(vma
->obj
->pin_display
== 0))
3557 if (--vma
->obj
->pin_display
== 0)
3558 vma
->display_alignment
= I915_GTT_MIN_ALIGNMENT
;
3560 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3561 i915_gem_object_bump_inactive_ggtt(vma
->obj
);
3563 i915_vma_unpin(vma
);
3567 * Moves a single object to the CPU read, and possibly write domain.
3568 * @obj: object to act on
3569 * @write: requesting write or read-only access
3571 * This function returns when the move is complete, including waiting on
3575 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3577 uint32_t old_write_domain
, old_read_domains
;
3580 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3582 ret
= i915_gem_object_wait(obj
,
3583 I915_WAIT_INTERRUPTIBLE
|
3585 (write
? I915_WAIT_ALL
: 0),
3586 MAX_SCHEDULE_TIMEOUT
,
3591 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3594 i915_gem_object_flush_gtt_write_domain(obj
);
3596 old_write_domain
= obj
->base
.write_domain
;
3597 old_read_domains
= obj
->base
.read_domains
;
3599 /* Flush the CPU cache if it's still invalid. */
3600 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3601 i915_gem_clflush_object(obj
, false);
3603 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3606 /* It should now be out of any other write domains, and we can update
3607 * the domain values for our changes.
3609 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3611 /* If we're writing through the CPU, then the GPU read domains will
3612 * need to be invalidated at next use.
3615 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3616 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3619 trace_i915_gem_object_change_domain(obj
,
3626 /* Throttle our rendering by waiting until the ring has completed our requests
3627 * emitted over 20 msec ago.
3629 * Note that if we were to use the current jiffies each time around the loop,
3630 * we wouldn't escape the function with any frames outstanding if the time to
3631 * render a frame was over 20ms.
3633 * This should get us reasonable parallelism between CPU and GPU but also
3634 * relatively low latency when blocking on a particular request to finish.
3637 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3639 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3640 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3641 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
3642 struct drm_i915_gem_request
*request
, *target
= NULL
;
3645 /* ABI: return -EIO if already wedged */
3646 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
3649 spin_lock(&file_priv
->mm
.lock
);
3650 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3651 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3655 * Note that the request might not have been submitted yet.
3656 * In which case emitted_jiffies will be zero.
3658 if (!request
->emitted_jiffies
)
3664 i915_gem_request_get(target
);
3665 spin_unlock(&file_priv
->mm
.lock
);
3670 ret
= i915_wait_request(target
,
3671 I915_WAIT_INTERRUPTIBLE
,
3672 MAX_SCHEDULE_TIMEOUT
);
3673 i915_gem_request_put(target
);
3675 return ret
< 0 ? ret
: 0;
3679 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3680 const struct i915_ggtt_view
*view
,
3685 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3686 struct i915_address_space
*vm
= &dev_priv
->ggtt
.base
;
3687 struct i915_vma
*vma
;
3690 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3692 vma
= i915_vma_instance(obj
, vm
, view
);
3693 if (unlikely(IS_ERR(vma
)))
3696 if (i915_vma_misplaced(vma
, size
, alignment
, flags
)) {
3697 if (flags
& PIN_NONBLOCK
&&
3698 (i915_vma_is_pinned(vma
) || i915_vma_is_active(vma
)))
3699 return ERR_PTR(-ENOSPC
);
3701 if (flags
& PIN_MAPPABLE
) {
3702 /* If the required space is larger than the available
3703 * aperture, we will not able to find a slot for the
3704 * object and unbinding the object now will be in
3705 * vain. Worse, doing so may cause us to ping-pong
3706 * the object in and out of the Global GTT and
3707 * waste a lot of cycles under the mutex.
3709 if (vma
->fence_size
> dev_priv
->ggtt
.mappable_end
)
3710 return ERR_PTR(-E2BIG
);
3712 /* If NONBLOCK is set the caller is optimistically
3713 * trying to cache the full object within the mappable
3714 * aperture, and *must* have a fallback in place for
3715 * situations where we cannot bind the object. We
3716 * can be a little more lax here and use the fallback
3717 * more often to avoid costly migrations of ourselves
3718 * and other objects within the aperture.
3720 * Half-the-aperture is used as a simple heuristic.
3721 * More interesting would to do search for a free
3722 * block prior to making the commitment to unbind.
3723 * That caters for the self-harm case, and with a
3724 * little more heuristics (e.g. NOFAULT, NOEVICT)
3725 * we could try to minimise harm to others.
3727 if (flags
& PIN_NONBLOCK
&&
3728 vma
->fence_size
> dev_priv
->ggtt
.mappable_end
/ 2)
3729 return ERR_PTR(-ENOSPC
);
3732 WARN(i915_vma_is_pinned(vma
),
3733 "bo is already pinned in ggtt with incorrect alignment:"
3734 " offset=%08x, req.alignment=%llx,"
3735 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3736 i915_ggtt_offset(vma
), alignment
,
3737 !!(flags
& PIN_MAPPABLE
),
3738 i915_vma_is_map_and_fenceable(vma
));
3739 ret
= i915_vma_unbind(vma
);
3741 return ERR_PTR(ret
);
3744 ret
= i915_vma_pin(vma
, size
, alignment
, flags
| PIN_GLOBAL
);
3746 return ERR_PTR(ret
);
3751 static __always_inline
unsigned int __busy_read_flag(unsigned int id
)
3753 /* Note that we could alias engines in the execbuf API, but
3754 * that would be very unwise as it prevents userspace from
3755 * fine control over engine selection. Ahem.
3757 * This should be something like EXEC_MAX_ENGINE instead of
3760 BUILD_BUG_ON(I915_NUM_ENGINES
> 16);
3761 return 0x10000 << id
;
3764 static __always_inline
unsigned int __busy_write_id(unsigned int id
)
3766 /* The uABI guarantees an active writer is also amongst the read
3767 * engines. This would be true if we accessed the activity tracking
3768 * under the lock, but as we perform the lookup of the object and
3769 * its activity locklessly we can not guarantee that the last_write
3770 * being active implies that we have set the same engine flag from
3771 * last_read - hence we always set both read and write busy for
3774 return id
| __busy_read_flag(id
);
3777 static __always_inline
unsigned int
3778 __busy_set_if_active(const struct dma_fence
*fence
,
3779 unsigned int (*flag
)(unsigned int id
))
3781 struct drm_i915_gem_request
*rq
;
3783 /* We have to check the current hw status of the fence as the uABI
3784 * guarantees forward progress. We could rely on the idle worker
3785 * to eventually flush us, but to minimise latency just ask the
3788 * Note we only report on the status of native fences.
3790 if (!dma_fence_is_i915(fence
))
3793 /* opencode to_request() in order to avoid const warnings */
3794 rq
= container_of(fence
, struct drm_i915_gem_request
, fence
);
3795 if (i915_gem_request_completed(rq
))
3798 return flag(rq
->engine
->exec_id
);
3801 static __always_inline
unsigned int
3802 busy_check_reader(const struct dma_fence
*fence
)
3804 return __busy_set_if_active(fence
, __busy_read_flag
);
3807 static __always_inline
unsigned int
3808 busy_check_writer(const struct dma_fence
*fence
)
3813 return __busy_set_if_active(fence
, __busy_write_id
);
3817 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3818 struct drm_file
*file
)
3820 struct drm_i915_gem_busy
*args
= data
;
3821 struct drm_i915_gem_object
*obj
;
3822 struct reservation_object_list
*list
;
3828 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3832 /* A discrepancy here is that we do not report the status of
3833 * non-i915 fences, i.e. even though we may report the object as idle,
3834 * a call to set-domain may still stall waiting for foreign rendering.
3835 * This also means that wait-ioctl may report an object as busy,
3836 * where busy-ioctl considers it idle.
3838 * We trade the ability to warn of foreign fences to report on which
3839 * i915 engines are active for the object.
3841 * Alternatively, we can trade that extra information on read/write
3844 * !reservation_object_test_signaled_rcu(obj->resv, true);
3845 * to report the overall busyness. This is what the wait-ioctl does.
3849 seq
= raw_read_seqcount(&obj
->resv
->seq
);
3851 /* Translate the exclusive fence to the READ *and* WRITE engine */
3852 args
->busy
= busy_check_writer(rcu_dereference(obj
->resv
->fence_excl
));
3854 /* Translate shared fences to READ set of engines */
3855 list
= rcu_dereference(obj
->resv
->fence
);
3857 unsigned int shared_count
= list
->shared_count
, i
;
3859 for (i
= 0; i
< shared_count
; ++i
) {
3860 struct dma_fence
*fence
=
3861 rcu_dereference(list
->shared
[i
]);
3863 args
->busy
|= busy_check_reader(fence
);
3867 if (args
->busy
&& read_seqcount_retry(&obj
->resv
->seq
, seq
))
3877 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3878 struct drm_file
*file_priv
)
3880 return i915_gem_ring_throttle(dev
, file_priv
);
3884 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3885 struct drm_file
*file_priv
)
3887 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3888 struct drm_i915_gem_madvise
*args
= data
;
3889 struct drm_i915_gem_object
*obj
;
3892 switch (args
->madv
) {
3893 case I915_MADV_DONTNEED
:
3894 case I915_MADV_WILLNEED
:
3900 obj
= i915_gem_object_lookup(file_priv
, args
->handle
);
3904 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
3908 if (obj
->mm
.pages
&&
3909 i915_gem_object_is_tiled(obj
) &&
3910 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
3911 if (obj
->mm
.madv
== I915_MADV_WILLNEED
) {
3912 GEM_BUG_ON(!obj
->mm
.quirked
);
3913 __i915_gem_object_unpin_pages(obj
);
3914 obj
->mm
.quirked
= false;
3916 if (args
->madv
== I915_MADV_WILLNEED
) {
3917 GEM_BUG_ON(obj
->mm
.quirked
);
3918 __i915_gem_object_pin_pages(obj
);
3919 obj
->mm
.quirked
= true;
3923 if (obj
->mm
.madv
!= __I915_MADV_PURGED
)
3924 obj
->mm
.madv
= args
->madv
;
3926 /* if the object is no longer attached, discard its backing storage */
3927 if (obj
->mm
.madv
== I915_MADV_DONTNEED
&& !obj
->mm
.pages
)
3928 i915_gem_object_truncate(obj
);
3930 args
->retained
= obj
->mm
.madv
!= __I915_MADV_PURGED
;
3931 mutex_unlock(&obj
->mm
.lock
);
3934 i915_gem_object_put(obj
);
3939 frontbuffer_retire(struct i915_gem_active
*active
,
3940 struct drm_i915_gem_request
*request
)
3942 struct drm_i915_gem_object
*obj
=
3943 container_of(active
, typeof(*obj
), frontbuffer_write
);
3945 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
3948 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3949 const struct drm_i915_gem_object_ops
*ops
)
3951 mutex_init(&obj
->mm
.lock
);
3953 INIT_LIST_HEAD(&obj
->global_link
);
3954 INIT_LIST_HEAD(&obj
->userfault_link
);
3955 INIT_LIST_HEAD(&obj
->obj_exec_link
);
3956 INIT_LIST_HEAD(&obj
->vma_list
);
3957 INIT_LIST_HEAD(&obj
->batch_pool_link
);
3961 reservation_object_init(&obj
->__builtin_resv
);
3962 obj
->resv
= &obj
->__builtin_resv
;
3964 obj
->frontbuffer_ggtt_origin
= ORIGIN_GTT
;
3965 init_request_active(&obj
->frontbuffer_write
, frontbuffer_retire
);
3967 obj
->mm
.madv
= I915_MADV_WILLNEED
;
3968 INIT_RADIX_TREE(&obj
->mm
.get_page
.radix
, GFP_KERNEL
| __GFP_NOWARN
);
3969 mutex_init(&obj
->mm
.get_page
.lock
);
3971 i915_gem_info_add_obj(to_i915(obj
->base
.dev
), obj
->base
.size
);
3974 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3975 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
|
3976 I915_GEM_OBJECT_IS_SHRINKABLE
,
3977 .get_pages
= i915_gem_object_get_pages_gtt
,
3978 .put_pages
= i915_gem_object_put_pages_gtt
,
3981 struct drm_i915_gem_object
*
3982 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
)
3984 struct drm_i915_gem_object
*obj
;
3985 struct address_space
*mapping
;
3989 /* There is a prevalence of the assumption that we fit the object's
3990 * page count inside a 32bit _signed_ variable. Let's document this and
3991 * catch if we ever need to fix it. In the meantime, if you do spot
3992 * such a local variable, please consider fixing!
3994 if (WARN_ON(size
>> PAGE_SHIFT
> INT_MAX
))
3995 return ERR_PTR(-E2BIG
);
3997 if (overflows_type(size
, obj
->base
.size
))
3998 return ERR_PTR(-E2BIG
);
4000 obj
= i915_gem_object_alloc(dev_priv
);
4002 return ERR_PTR(-ENOMEM
);
4004 ret
= drm_gem_object_init(&dev_priv
->drm
, &obj
->base
, size
);
4008 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4009 if (IS_I965GM(dev_priv
) || IS_I965G(dev_priv
)) {
4010 /* 965gm cannot relocate objects above 4GiB. */
4011 mask
&= ~__GFP_HIGHMEM
;
4012 mask
|= __GFP_DMA32
;
4015 mapping
= obj
->base
.filp
->f_mapping
;
4016 mapping_set_gfp_mask(mapping
, mask
);
4018 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4020 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4021 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4023 if (HAS_LLC(dev_priv
)) {
4024 /* On some devices, we can have the GPU use the LLC (the CPU
4025 * cache) for about a 10% performance improvement
4026 * compared to uncached. Graphics requests other than
4027 * display scanout are coherent with the CPU in
4028 * accessing this cache. This means in this mode we
4029 * don't need to clflush on the CPU side, and on the
4030 * GPU side we only need to flush internal caches to
4031 * get data visible to the CPU.
4033 * However, we maintain the display planes as UC, and so
4034 * need to rebind when first used as such.
4036 obj
->cache_level
= I915_CACHE_LLC
;
4038 obj
->cache_level
= I915_CACHE_NONE
;
4040 trace_i915_gem_object_create(obj
);
4045 i915_gem_object_free(obj
);
4046 return ERR_PTR(ret
);
4049 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4051 /* If we are the last user of the backing storage (be it shmemfs
4052 * pages or stolen etc), we know that the pages are going to be
4053 * immediately released. In this case, we can then skip copying
4054 * back the contents from the GPU.
4057 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
4060 if (obj
->base
.filp
== NULL
)
4063 /* At first glance, this looks racy, but then again so would be
4064 * userspace racing mmap against close. However, the first external
4065 * reference to the filp can only be obtained through the
4066 * i915_gem_mmap_ioctl() which safeguards us against the user
4067 * acquiring such a reference whilst we are in the middle of
4068 * freeing the object.
4070 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4073 static void __i915_gem_free_objects(struct drm_i915_private
*i915
,
4074 struct llist_node
*freed
)
4076 struct drm_i915_gem_object
*obj
, *on
;
4078 mutex_lock(&i915
->drm
.struct_mutex
);
4079 intel_runtime_pm_get(i915
);
4080 llist_for_each_entry(obj
, freed
, freed
) {
4081 struct i915_vma
*vma
, *vn
;
4083 trace_i915_gem_object_destroy(obj
);
4085 GEM_BUG_ON(i915_gem_object_is_active(obj
));
4086 list_for_each_entry_safe(vma
, vn
,
4087 &obj
->vma_list
, obj_link
) {
4088 GEM_BUG_ON(!i915_vma_is_ggtt(vma
));
4089 GEM_BUG_ON(i915_vma_is_active(vma
));
4090 vma
->flags
&= ~I915_VMA_PIN_MASK
;
4091 i915_vma_close(vma
);
4093 GEM_BUG_ON(!list_empty(&obj
->vma_list
));
4094 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj
->vma_tree
));
4096 list_del(&obj
->global_link
);
4098 intel_runtime_pm_put(i915
);
4099 mutex_unlock(&i915
->drm
.struct_mutex
);
4101 llist_for_each_entry_safe(obj
, on
, freed
, freed
) {
4102 GEM_BUG_ON(obj
->bind_count
);
4103 GEM_BUG_ON(atomic_read(&obj
->frontbuffer_bits
));
4105 if (obj
->ops
->release
)
4106 obj
->ops
->release(obj
);
4108 if (WARN_ON(i915_gem_object_has_pinned_pages(obj
)))
4109 atomic_set(&obj
->mm
.pages_pin_count
, 0);
4110 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
4111 GEM_BUG_ON(obj
->mm
.pages
);
4113 if (obj
->base
.import_attach
)
4114 drm_prime_gem_destroy(&obj
->base
, NULL
);
4116 reservation_object_fini(&obj
->__builtin_resv
);
4117 drm_gem_object_release(&obj
->base
);
4118 i915_gem_info_remove_obj(i915
, obj
->base
.size
);
4121 i915_gem_object_free(obj
);
4125 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
)
4127 struct llist_node
*freed
;
4129 freed
= llist_del_all(&i915
->mm
.free_list
);
4130 if (unlikely(freed
))
4131 __i915_gem_free_objects(i915
, freed
);
4134 static void __i915_gem_free_work(struct work_struct
*work
)
4136 struct drm_i915_private
*i915
=
4137 container_of(work
, struct drm_i915_private
, mm
.free_work
);
4138 struct llist_node
*freed
;
4140 /* All file-owned VMA should have been released by this point through
4141 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4142 * However, the object may also be bound into the global GTT (e.g.
4143 * older GPUs without per-process support, or for direct access through
4144 * the GTT either for the user or for scanout). Those VMA still need to
4148 while ((freed
= llist_del_all(&i915
->mm
.free_list
)))
4149 __i915_gem_free_objects(i915
, freed
);
4152 static void __i915_gem_free_object_rcu(struct rcu_head
*head
)
4154 struct drm_i915_gem_object
*obj
=
4155 container_of(head
, typeof(*obj
), rcu
);
4156 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
4158 /* We can't simply use call_rcu() from i915_gem_free_object()
4159 * as we need to block whilst unbinding, and the call_rcu
4160 * task may be called from softirq context. So we take a
4161 * detour through a worker.
4163 if (llist_add(&obj
->freed
, &i915
->mm
.free_list
))
4164 schedule_work(&i915
->mm
.free_work
);
4167 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4169 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4171 if (obj
->mm
.quirked
)
4172 __i915_gem_object_unpin_pages(obj
);
4174 if (discard_backing_storage(obj
))
4175 obj
->mm
.madv
= I915_MADV_DONTNEED
;
4177 /* Before we free the object, make sure any pure RCU-only
4178 * read-side critical sections are complete, e.g.
4179 * i915_gem_busy_ioctl(). For the corresponding synchronized
4180 * lookup see i915_gem_object_lookup_rcu().
4182 call_rcu(&obj
->rcu
, __i915_gem_free_object_rcu
);
4185 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object
*obj
)
4187 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
4189 GEM_BUG_ON(i915_gem_object_has_active_reference(obj
));
4190 if (i915_gem_object_is_active(obj
))
4191 i915_gem_object_set_active_reference(obj
);
4193 i915_gem_object_put(obj
);
4196 static void assert_kernel_context_is_current(struct drm_i915_private
*dev_priv
)
4198 struct intel_engine_cs
*engine
;
4199 enum intel_engine_id id
;
4201 for_each_engine(engine
, dev_priv
, id
)
4202 GEM_BUG_ON(engine
->last_retired_context
&&
4203 !i915_gem_context_is_kernel(engine
->last_retired_context
));
4206 int i915_gem_suspend(struct drm_i915_private
*dev_priv
)
4208 struct drm_device
*dev
= &dev_priv
->drm
;
4211 intel_suspend_gt_powersave(dev_priv
);
4213 mutex_lock(&dev
->struct_mutex
);
4215 /* We have to flush all the executing contexts to main memory so
4216 * that they can saved in the hibernation image. To ensure the last
4217 * context image is coherent, we have to switch away from it. That
4218 * leaves the dev_priv->kernel_context still active when
4219 * we actually suspend, and its image in memory may not match the GPU
4220 * state. Fortunately, the kernel_context is disposable and we do
4221 * not rely on its state.
4223 ret
= i915_gem_switch_to_kernel_context(dev_priv
);
4227 ret
= i915_gem_wait_for_idle(dev_priv
,
4228 I915_WAIT_INTERRUPTIBLE
|
4233 i915_gem_retire_requests(dev_priv
);
4234 GEM_BUG_ON(dev_priv
->gt
.active_requests
);
4236 assert_kernel_context_is_current(dev_priv
);
4237 i915_gem_context_lost(dev_priv
);
4238 mutex_unlock(&dev
->struct_mutex
);
4240 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4241 cancel_delayed_work_sync(&dev_priv
->gt
.retire_work
);
4243 /* As the idle_work is rearming if it detects a race, play safe and
4244 * repeat the flush until it is definitely idle.
4246 while (flush_delayed_work(&dev_priv
->gt
.idle_work
))
4249 i915_gem_drain_freed_objects(dev_priv
);
4251 /* Assert that we sucessfully flushed all the work and
4252 * reset the GPU back to its idle, low power state.
4254 WARN_ON(dev_priv
->gt
.awake
);
4255 WARN_ON(!intel_execlists_idle(dev_priv
));
4258 * Neither the BIOS, ourselves or any other kernel
4259 * expects the system to be in execlists mode on startup,
4260 * so we need to reset the GPU back to legacy mode. And the only
4261 * known way to disable logical contexts is through a GPU reset.
4263 * So in order to leave the system in a known default configuration,
4264 * always reset the GPU upon unload and suspend. Afterwards we then
4265 * clean up the GEM state tracking, flushing off the requests and
4266 * leaving the system in a known idle state.
4268 * Note that is of the upmost importance that the GPU is idle and
4269 * all stray writes are flushed *before* we dismantle the backing
4270 * storage for the pinned objects.
4272 * However, since we are uncertain that resetting the GPU on older
4273 * machines is a good idea, we don't - just in case it leaves the
4274 * machine in an unusable condition.
4276 if (HAS_HW_CONTEXTS(dev_priv
)) {
4277 int reset
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
4278 WARN_ON(reset
&& reset
!= -ENODEV
);
4284 mutex_unlock(&dev
->struct_mutex
);
4288 void i915_gem_resume(struct drm_i915_private
*dev_priv
)
4290 struct drm_device
*dev
= &dev_priv
->drm
;
4292 WARN_ON(dev_priv
->gt
.awake
);
4294 mutex_lock(&dev
->struct_mutex
);
4295 i915_gem_restore_gtt_mappings(dev_priv
);
4297 /* As we didn't flush the kernel context before suspend, we cannot
4298 * guarantee that the context image is complete. So let's just reset
4299 * it and start again.
4301 dev_priv
->gt
.resume(dev_priv
);
4303 mutex_unlock(&dev
->struct_mutex
);
4306 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
)
4308 if (INTEL_GEN(dev_priv
) < 5 ||
4309 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4312 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4313 DISP_TILE_SURFACE_SWIZZLING
);
4315 if (IS_GEN5(dev_priv
))
4318 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4319 if (IS_GEN6(dev_priv
))
4320 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4321 else if (IS_GEN7(dev_priv
))
4322 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4323 else if (IS_GEN8(dev_priv
))
4324 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4329 static void init_unused_ring(struct drm_i915_private
*dev_priv
, u32 base
)
4331 I915_WRITE(RING_CTL(base
), 0);
4332 I915_WRITE(RING_HEAD(base
), 0);
4333 I915_WRITE(RING_TAIL(base
), 0);
4334 I915_WRITE(RING_START(base
), 0);
4337 static void init_unused_rings(struct drm_i915_private
*dev_priv
)
4339 if (IS_I830(dev_priv
)) {
4340 init_unused_ring(dev_priv
, PRB1_BASE
);
4341 init_unused_ring(dev_priv
, SRB0_BASE
);
4342 init_unused_ring(dev_priv
, SRB1_BASE
);
4343 init_unused_ring(dev_priv
, SRB2_BASE
);
4344 init_unused_ring(dev_priv
, SRB3_BASE
);
4345 } else if (IS_GEN2(dev_priv
)) {
4346 init_unused_ring(dev_priv
, SRB0_BASE
);
4347 init_unused_ring(dev_priv
, SRB1_BASE
);
4348 } else if (IS_GEN3(dev_priv
)) {
4349 init_unused_ring(dev_priv
, PRB1_BASE
);
4350 init_unused_ring(dev_priv
, PRB2_BASE
);
4355 i915_gem_init_hw(struct drm_i915_private
*dev_priv
)
4357 struct intel_engine_cs
*engine
;
4358 enum intel_engine_id id
;
4361 dev_priv
->gt
.last_init_time
= ktime_get();
4363 /* Double layer security blanket, see i915_gem_init() */
4364 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4366 if (HAS_EDRAM(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
4367 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4369 if (IS_HASWELL(dev_priv
))
4370 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev_priv
) ?
4371 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4373 if (HAS_PCH_NOP(dev_priv
)) {
4374 if (IS_IVYBRIDGE(dev_priv
)) {
4375 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4376 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4377 I915_WRITE(GEN7_MSG_CTL
, temp
);
4378 } else if (INTEL_GEN(dev_priv
) >= 7) {
4379 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4380 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4381 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4385 i915_gem_init_swizzling(dev_priv
);
4388 * At least 830 can leave some of the unused rings
4389 * "active" (ie. head != tail) after resume which
4390 * will prevent c3 entry. Makes sure all unused rings
4393 init_unused_rings(dev_priv
);
4395 BUG_ON(!dev_priv
->kernel_context
);
4397 ret
= i915_ppgtt_init_hw(dev_priv
);
4399 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4403 /* Need to do basic initialisation of all rings first: */
4404 for_each_engine(engine
, dev_priv
, id
) {
4405 ret
= engine
->init_hw(engine
);
4410 intel_mocs_init_l3cc_table(dev_priv
);
4412 /* We can't enable contexts until all firmware is loaded */
4413 ret
= intel_guc_setup(dev_priv
);
4418 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4422 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
)
4424 if (INTEL_INFO(dev_priv
)->gen
< 6)
4427 /* TODO: make semaphores and Execlists play nicely together */
4428 if (i915
.enable_execlists
)
4434 #ifdef CONFIG_INTEL_IOMMU
4435 /* Enable semaphores on SNB when IO remapping is off */
4436 if (INTEL_INFO(dev_priv
)->gen
== 6 && intel_iommu_gfx_mapped
)
4443 int i915_gem_init(struct drm_i915_private
*dev_priv
)
4447 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4449 if (!i915
.enable_execlists
) {
4450 dev_priv
->gt
.resume
= intel_legacy_submission_resume
;
4451 dev_priv
->gt
.cleanup_engine
= intel_engine_cleanup
;
4453 dev_priv
->gt
.resume
= intel_lr_context_resume
;
4454 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4457 /* This is just a security blanket to placate dragons.
4458 * On some systems, we very sporadically observe that the first TLBs
4459 * used by the CS may be stale, despite us poking the TLB reset. If
4460 * we hold the forcewake during initialisation these problems
4461 * just magically go away.
4463 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4465 i915_gem_init_userptr(dev_priv
);
4467 ret
= i915_gem_init_ggtt(dev_priv
);
4471 ret
= i915_gem_context_init(dev_priv
);
4475 ret
= intel_engines_init(dev_priv
);
4479 ret
= i915_gem_init_hw(dev_priv
);
4481 /* Allow engine initialisation to fail by marking the GPU as
4482 * wedged. But we only want to do this where the GPU is angry,
4483 * for all other failure, such as an allocation failure, bail.
4485 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4486 i915_gem_set_wedged(dev_priv
);
4491 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4492 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4498 i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
)
4500 struct intel_engine_cs
*engine
;
4501 enum intel_engine_id id
;
4503 for_each_engine(engine
, dev_priv
, id
)
4504 dev_priv
->gt
.cleanup_engine(engine
);
4508 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
4512 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
4513 !IS_CHERRYVIEW(dev_priv
))
4514 dev_priv
->num_fence_regs
= 32;
4515 else if (INTEL_INFO(dev_priv
)->gen
>= 4 ||
4516 IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
4517 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
))
4518 dev_priv
->num_fence_regs
= 16;
4520 dev_priv
->num_fence_regs
= 8;
4522 if (intel_vgpu_active(dev_priv
))
4523 dev_priv
->num_fence_regs
=
4524 I915_READ(vgtif_reg(avail_rs
.fence_num
));
4526 /* Initialize fence registers to zero */
4527 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
4528 struct drm_i915_fence_reg
*fence
= &dev_priv
->fence_regs
[i
];
4530 fence
->i915
= dev_priv
;
4532 list_add_tail(&fence
->link
, &dev_priv
->mm
.fence_list
);
4534 i915_gem_restore_fences(dev_priv
);
4536 i915_gem_detect_bit_6_swizzle(dev_priv
);
4540 i915_gem_load_init(struct drm_i915_private
*dev_priv
)
4544 dev_priv
->objects
= KMEM_CACHE(drm_i915_gem_object
, SLAB_HWCACHE_ALIGN
);
4545 if (!dev_priv
->objects
)
4548 dev_priv
->vmas
= KMEM_CACHE(i915_vma
, SLAB_HWCACHE_ALIGN
);
4549 if (!dev_priv
->vmas
)
4552 dev_priv
->requests
= KMEM_CACHE(drm_i915_gem_request
,
4553 SLAB_HWCACHE_ALIGN
|
4554 SLAB_RECLAIM_ACCOUNT
|
4555 SLAB_DESTROY_BY_RCU
);
4556 if (!dev_priv
->requests
)
4559 dev_priv
->dependencies
= KMEM_CACHE(i915_dependency
,
4560 SLAB_HWCACHE_ALIGN
|
4561 SLAB_RECLAIM_ACCOUNT
);
4562 if (!dev_priv
->dependencies
)
4565 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4566 INIT_LIST_HEAD(&dev_priv
->gt
.timelines
);
4567 err
= i915_gem_timeline_init__global(dev_priv
);
4568 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4570 goto err_dependencies
;
4572 INIT_LIST_HEAD(&dev_priv
->context_list
);
4573 INIT_WORK(&dev_priv
->mm
.free_work
, __i915_gem_free_work
);
4574 init_llist_head(&dev_priv
->mm
.free_list
);
4575 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4576 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4577 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4578 INIT_LIST_HEAD(&dev_priv
->mm
.userfault_list
);
4579 INIT_DELAYED_WORK(&dev_priv
->gt
.retire_work
,
4580 i915_gem_retire_work_handler
);
4581 INIT_DELAYED_WORK(&dev_priv
->gt
.idle_work
,
4582 i915_gem_idle_work_handler
);
4583 init_waitqueue_head(&dev_priv
->gpu_error
.wait_queue
);
4584 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4586 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4588 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4590 dev_priv
->mm
.interruptible
= true;
4592 atomic_set(&dev_priv
->mm
.bsd_engine_dispatch_index
, 0);
4594 spin_lock_init(&dev_priv
->fb_tracking
.lock
);
4599 kmem_cache_destroy(dev_priv
->dependencies
);
4601 kmem_cache_destroy(dev_priv
->requests
);
4603 kmem_cache_destroy(dev_priv
->vmas
);
4605 kmem_cache_destroy(dev_priv
->objects
);
4610 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
)
4612 WARN_ON(!llist_empty(&dev_priv
->mm
.free_list
));
4614 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4615 i915_gem_timeline_fini(&dev_priv
->gt
.global_timeline
);
4616 WARN_ON(!list_empty(&dev_priv
->gt
.timelines
));
4617 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4619 kmem_cache_destroy(dev_priv
->dependencies
);
4620 kmem_cache_destroy(dev_priv
->requests
);
4621 kmem_cache_destroy(dev_priv
->vmas
);
4622 kmem_cache_destroy(dev_priv
->objects
);
4624 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4628 int i915_gem_freeze(struct drm_i915_private
*dev_priv
)
4630 intel_runtime_pm_get(dev_priv
);
4632 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4633 i915_gem_shrink_all(dev_priv
);
4634 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4636 intel_runtime_pm_put(dev_priv
);
4641 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
4643 struct drm_i915_gem_object
*obj
;
4644 struct list_head
*phases
[] = {
4645 &dev_priv
->mm
.unbound_list
,
4646 &dev_priv
->mm
.bound_list
,
4650 /* Called just before we write the hibernation image.
4652 * We need to update the domain tracking to reflect that the CPU
4653 * will be accessing all the pages to create and restore from the
4654 * hibernation, and so upon restoration those pages will be in the
4657 * To make sure the hibernation image contains the latest state,
4658 * we update that state just before writing out the image.
4660 * To try and reduce the hibernation image, we manually shrink
4661 * the objects as well.
4664 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4665 i915_gem_shrink(dev_priv
, -1UL, I915_SHRINK_UNBOUND
);
4667 for (p
= phases
; *p
; p
++) {
4668 list_for_each_entry(obj
, *p
, global_link
) {
4669 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4670 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4673 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4678 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4680 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4681 struct drm_i915_gem_request
*request
;
4683 /* Clean up our request list when the client is going away, so that
4684 * later retire_requests won't dereference our soon-to-be-gone
4687 spin_lock(&file_priv
->mm
.lock
);
4688 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
)
4689 request
->file_priv
= NULL
;
4690 spin_unlock(&file_priv
->mm
.lock
);
4692 if (!list_empty(&file_priv
->rps
.link
)) {
4693 spin_lock(&to_i915(dev
)->rps
.client_lock
);
4694 list_del(&file_priv
->rps
.link
);
4695 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
4699 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4701 struct drm_i915_file_private
*file_priv
;
4706 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4710 file
->driver_priv
= file_priv
;
4711 file_priv
->dev_priv
= to_i915(dev
);
4712 file_priv
->file
= file
;
4713 INIT_LIST_HEAD(&file_priv
->rps
.link
);
4715 spin_lock_init(&file_priv
->mm
.lock
);
4716 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4718 file_priv
->bsd_engine
= -1;
4720 ret
= i915_gem_context_open(dev
, file
);
4728 * i915_gem_track_fb - update frontbuffer tracking
4729 * @old: current GEM buffer for the frontbuffer slots
4730 * @new: new GEM buffer for the frontbuffer slots
4731 * @frontbuffer_bits: bitmask of frontbuffer slots
4733 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4734 * from @old and setting them in @new. Both @old and @new can be NULL.
4736 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
4737 struct drm_i915_gem_object
*new,
4738 unsigned frontbuffer_bits
)
4740 /* Control of individual bits within the mask are guarded by
4741 * the owning plane->mutex, i.e. we can never see concurrent
4742 * manipulation of individual bits. But since the bitfield as a whole
4743 * is updated using RMW, we need to use atomics in order to update
4746 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE
* I915_MAX_PIPES
>
4747 sizeof(atomic_t
) * BITS_PER_BYTE
);
4750 WARN_ON(!(atomic_read(&old
->frontbuffer_bits
) & frontbuffer_bits
));
4751 atomic_andnot(frontbuffer_bits
, &old
->frontbuffer_bits
);
4755 WARN_ON(atomic_read(&new->frontbuffer_bits
) & frontbuffer_bits
);
4756 atomic_or(frontbuffer_bits
, &new->frontbuffer_bits
);
4760 /* Allocate a new GEM object and fill it with the supplied data */
4761 struct drm_i915_gem_object
*
4762 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
4763 const void *data
, size_t size
)
4765 struct drm_i915_gem_object
*obj
;
4766 struct sg_table
*sg
;
4770 obj
= i915_gem_object_create(dev_priv
, round_up(size
, PAGE_SIZE
));
4774 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
4778 ret
= i915_gem_object_pin_pages(obj
);
4783 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
4784 obj
->mm
.dirty
= true; /* Backing store is now out of date */
4785 i915_gem_object_unpin_pages(obj
);
4787 if (WARN_ON(bytes
!= size
)) {
4788 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
4796 i915_gem_object_put(obj
);
4797 return ERR_PTR(ret
);
4800 struct scatterlist
*
4801 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
4803 unsigned int *offset
)
4805 struct i915_gem_object_page_iter
*iter
= &obj
->mm
.get_page
;
4806 struct scatterlist
*sg
;
4807 unsigned int idx
, count
;
4810 GEM_BUG_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
);
4811 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
4813 /* As we iterate forward through the sg, we record each entry in a
4814 * radixtree for quick repeated (backwards) lookups. If we have seen
4815 * this index previously, we will have an entry for it.
4817 * Initial lookup is O(N), but this is amortized to O(1) for
4818 * sequential page access (where each new request is consecutive
4819 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4820 * i.e. O(1) with a large constant!
4822 if (n
< READ_ONCE(iter
->sg_idx
))
4825 mutex_lock(&iter
->lock
);
4827 /* We prefer to reuse the last sg so that repeated lookup of this
4828 * (or the subsequent) sg are fast - comparing against the last
4829 * sg is faster than going through the radixtree.
4834 count
= __sg_page_count(sg
);
4836 while (idx
+ count
<= n
) {
4837 unsigned long exception
, i
;
4840 /* If we cannot allocate and insert this entry, or the
4841 * individual pages from this range, cancel updating the
4842 * sg_idx so that on this lookup we are forced to linearly
4843 * scan onwards, but on future lookups we will try the
4844 * insertion again (in which case we need to be careful of
4845 * the error return reporting that we have already inserted
4848 ret
= radix_tree_insert(&iter
->radix
, idx
, sg
);
4849 if (ret
&& ret
!= -EEXIST
)
4853 RADIX_TREE_EXCEPTIONAL_ENTRY
|
4854 idx
<< RADIX_TREE_EXCEPTIONAL_SHIFT
;
4855 for (i
= 1; i
< count
; i
++) {
4856 ret
= radix_tree_insert(&iter
->radix
, idx
+ i
,
4858 if (ret
&& ret
!= -EEXIST
)
4863 sg
= ____sg_next(sg
);
4864 count
= __sg_page_count(sg
);
4871 mutex_unlock(&iter
->lock
);
4873 if (unlikely(n
< idx
)) /* insertion completed by another thread */
4876 /* In case we failed to insert the entry into the radixtree, we need
4877 * to look beyond the current sg.
4879 while (idx
+ count
<= n
) {
4881 sg
= ____sg_next(sg
);
4882 count
= __sg_page_count(sg
);
4891 sg
= radix_tree_lookup(&iter
->radix
, n
);
4894 /* If this index is in the middle of multi-page sg entry,
4895 * the radixtree will contain an exceptional entry that points
4896 * to the start of that range. We will return the pointer to
4897 * the base page and the offset of this page within the
4901 if (unlikely(radix_tree_exception(sg
))) {
4902 unsigned long base
=
4903 (unsigned long)sg
>> RADIX_TREE_EXCEPTIONAL_SHIFT
;
4905 sg
= radix_tree_lookup(&iter
->radix
, base
);
4917 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, unsigned int n
)
4919 struct scatterlist
*sg
;
4920 unsigned int offset
;
4922 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
4924 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
4925 return nth_page(sg_page(sg
), offset
);
4928 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
4930 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
4935 page
= i915_gem_object_get_page(obj
, n
);
4937 set_page_dirty(page
);
4943 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
4946 struct scatterlist
*sg
;
4947 unsigned int offset
;
4949 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
4950 return sg_dma_address(sg
) + (offset
<< PAGE_SHIFT
);