2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_gem_clflush.h"
33 #include "i915_vgpu.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36 #include "intel_frontbuffer.h"
37 #include "intel_mocs.h"
38 #include <linux/dma-fence-array.h>
39 #include <linux/kthread.h>
40 #include <linux/reservation.h>
41 #include <linux/shmem_fs.h>
42 #include <linux/slab.h>
43 #include <linux/stop_machine.h>
44 #include <linux/swap.h>
45 #include <linux/pci.h>
46 #include <linux/dma-buf.h>
48 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
);
50 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
55 if (!(obj
->cache_coherent
& I915_BO_CACHE_COHERENT_FOR_WRITE
))
58 return obj
->pin_display
;
62 insert_mappable_node(struct i915_ggtt
*ggtt
,
63 struct drm_mm_node
*node
, u32 size
)
65 memset(node
, 0, sizeof(*node
));
66 return drm_mm_insert_node_in_range(&ggtt
->base
.mm
, node
,
67 size
, 0, I915_COLOR_UNEVICTABLE
,
68 0, ggtt
->mappable_end
,
73 remove_mappable_node(struct drm_mm_node
*node
)
75 drm_mm_remove_node(node
);
78 /* some bookkeeping */
79 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
82 spin_lock(&dev_priv
->mm
.object_stat_lock
);
83 dev_priv
->mm
.object_count
++;
84 dev_priv
->mm
.object_memory
+= size
;
85 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
88 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
91 spin_lock(&dev_priv
->mm
.object_stat_lock
);
92 dev_priv
->mm
.object_count
--;
93 dev_priv
->mm
.object_memory
-= size
;
94 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
98 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
106 * userspace. If it takes that long something really bad is going on and
107 * we should simply try to bail out and fail as gracefully as possible.
109 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
110 !i915_reset_backoff(error
),
113 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
115 } else if (ret
< 0) {
122 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
124 struct drm_i915_private
*dev_priv
= to_i915(dev
);
127 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
131 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
139 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
140 struct drm_file
*file
)
142 struct drm_i915_private
*dev_priv
= to_i915(dev
);
143 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
144 struct drm_i915_gem_get_aperture
*args
= data
;
145 struct i915_vma
*vma
;
148 pinned
= ggtt
->base
.reserved
;
149 mutex_lock(&dev
->struct_mutex
);
150 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
151 if (i915_vma_is_pinned(vma
))
152 pinned
+= vma
->node
.size
;
153 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
154 if (i915_vma_is_pinned(vma
))
155 pinned
+= vma
->node
.size
;
156 mutex_unlock(&dev
->struct_mutex
);
158 args
->aper_size
= ggtt
->base
.total
;
159 args
->aper_available_size
= args
->aper_size
- pinned
;
164 static struct sg_table
*
165 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
167 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
168 drm_dma_handle_t
*phys
;
170 struct scatterlist
*sg
;
174 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
175 return ERR_PTR(-EINVAL
);
177 /* Always aligning to the object size, allows a single allocation
178 * to handle all possible callers, and given typical object sizes,
179 * the alignment of the buddy allocation will naturally match.
181 phys
= drm_pci_alloc(obj
->base
.dev
,
182 roundup_pow_of_two(obj
->base
.size
),
183 roundup_pow_of_two(obj
->base
.size
));
185 return ERR_PTR(-ENOMEM
);
188 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
192 page
= shmem_read_mapping_page(mapping
, i
);
198 src
= kmap_atomic(page
);
199 memcpy(vaddr
, src
, PAGE_SIZE
);
200 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
207 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
209 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
211 st
= ERR_PTR(-ENOMEM
);
215 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
217 st
= ERR_PTR(-ENOMEM
);
223 sg
->length
= obj
->base
.size
;
225 sg_dma_address(sg
) = phys
->busaddr
;
226 sg_dma_len(sg
) = obj
->base
.size
;
228 obj
->phys_handle
= phys
;
232 drm_pci_free(obj
->base
.dev
, phys
);
236 static void __start_cpu_write(struct drm_i915_gem_object
*obj
)
238 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
239 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
240 if (cpu_write_needs_clflush(obj
))
241 obj
->cache_dirty
= true;
245 __i915_gem_object_release_shmem(struct drm_i915_gem_object
*obj
,
246 struct sg_table
*pages
,
249 GEM_BUG_ON(obj
->mm
.madv
== __I915_MADV_PURGED
);
251 if (obj
->mm
.madv
== I915_MADV_DONTNEED
)
252 obj
->mm
.dirty
= false;
255 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0 &&
256 !(obj
->cache_coherent
& I915_BO_CACHE_COHERENT_FOR_READ
))
257 drm_clflush_sg(pages
);
259 __start_cpu_write(obj
);
263 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
,
264 struct sg_table
*pages
)
266 __i915_gem_object_release_shmem(obj
, pages
, false);
269 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
270 char *vaddr
= obj
->phys_handle
->vaddr
;
273 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
277 page
= shmem_read_mapping_page(mapping
, i
);
281 dst
= kmap_atomic(page
);
282 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
283 memcpy(dst
, vaddr
, PAGE_SIZE
);
286 set_page_dirty(page
);
287 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
288 mark_page_accessed(page
);
292 obj
->mm
.dirty
= false;
295 sg_free_table(pages
);
298 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
302 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
304 i915_gem_object_unpin_pages(obj
);
307 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
308 .get_pages
= i915_gem_object_get_pages_phys
,
309 .put_pages
= i915_gem_object_put_pages_phys
,
310 .release
= i915_gem_object_release_phys
,
313 static const struct drm_i915_gem_object_ops i915_gem_object_ops
;
315 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
317 struct i915_vma
*vma
;
318 LIST_HEAD(still_in_list
);
321 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
328 ret
= i915_gem_object_wait(obj
,
329 I915_WAIT_INTERRUPTIBLE
|
332 MAX_SCHEDULE_TIMEOUT
,
337 i915_gem_retire_requests(to_i915(obj
->base
.dev
));
339 while ((vma
= list_first_entry_or_null(&obj
->vma_list
,
342 list_move_tail(&vma
->obj_link
, &still_in_list
);
343 ret
= i915_vma_unbind(vma
);
347 list_splice(&still_in_list
, &obj
->vma_list
);
353 i915_gem_object_wait_fence(struct dma_fence
*fence
,
356 struct intel_rps_client
*rps
)
358 struct drm_i915_gem_request
*rq
;
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE
!= 0x1);
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &fence
->flags
))
365 if (!dma_fence_is_i915(fence
))
366 return dma_fence_wait_timeout(fence
,
367 flags
& I915_WAIT_INTERRUPTIBLE
,
370 rq
= to_request(fence
);
371 if (i915_gem_request_completed(rq
))
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
390 if (INTEL_GEN(rq
->i915
) >= 6)
391 gen6_rps_boost(rq
, rps
);
396 timeout
= i915_wait_request(rq
, flags
, timeout
);
399 if (flags
& I915_WAIT_LOCKED
&& i915_gem_request_completed(rq
))
400 i915_gem_request_retire_upto(rq
);
406 i915_gem_object_wait_reservation(struct reservation_object
*resv
,
409 struct intel_rps_client
*rps
)
411 unsigned int seq
= __read_seqcount_begin(&resv
->seq
);
412 struct dma_fence
*excl
;
413 bool prune_fences
= false;
415 if (flags
& I915_WAIT_ALL
) {
416 struct dma_fence
**shared
;
417 unsigned int count
, i
;
420 ret
= reservation_object_get_fences_rcu(resv
,
421 &excl
, &count
, &shared
);
425 for (i
= 0; i
< count
; i
++) {
426 timeout
= i915_gem_object_wait_fence(shared
[i
],
432 dma_fence_put(shared
[i
]);
435 for (; i
< count
; i
++)
436 dma_fence_put(shared
[i
]);
439 prune_fences
= count
&& timeout
>= 0;
441 excl
= reservation_object_get_excl_rcu(resv
);
444 if (excl
&& timeout
>= 0) {
445 timeout
= i915_gem_object_wait_fence(excl
, flags
, timeout
, rps
);
446 prune_fences
= timeout
>= 0;
451 /* Oportunistically prune the fences iff we know they have *all* been
452 * signaled and that the reservation object has not been changed (i.e.
453 * no new fences have been added).
455 if (prune_fences
&& !__read_seqcount_retry(&resv
->seq
, seq
)) {
456 if (reservation_object_trylock(resv
)) {
457 if (!__read_seqcount_retry(&resv
->seq
, seq
))
458 reservation_object_add_excl_fence(resv
, NULL
);
459 reservation_object_unlock(resv
);
466 static void __fence_set_priority(struct dma_fence
*fence
, int prio
)
468 struct drm_i915_gem_request
*rq
;
469 struct intel_engine_cs
*engine
;
471 if (!dma_fence_is_i915(fence
))
474 rq
= to_request(fence
);
476 if (!engine
->schedule
)
479 engine
->schedule(rq
, prio
);
482 static void fence_set_priority(struct dma_fence
*fence
, int prio
)
484 /* Recurse once into a fence-array */
485 if (dma_fence_is_array(fence
)) {
486 struct dma_fence_array
*array
= to_dma_fence_array(fence
);
489 for (i
= 0; i
< array
->num_fences
; i
++)
490 __fence_set_priority(array
->fences
[i
], prio
);
492 __fence_set_priority(fence
, prio
);
497 i915_gem_object_wait_priority(struct drm_i915_gem_object
*obj
,
501 struct dma_fence
*excl
;
503 if (flags
& I915_WAIT_ALL
) {
504 struct dma_fence
**shared
;
505 unsigned int count
, i
;
508 ret
= reservation_object_get_fences_rcu(obj
->resv
,
509 &excl
, &count
, &shared
);
513 for (i
= 0; i
< count
; i
++) {
514 fence_set_priority(shared
[i
], prio
);
515 dma_fence_put(shared
[i
]);
520 excl
= reservation_object_get_excl_rcu(obj
->resv
);
524 fence_set_priority(excl
, prio
);
531 * Waits for rendering to the object to be completed
532 * @obj: i915 gem object
533 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
534 * @timeout: how long to wait
535 * @rps: client (user process) to charge for any waitboosting
538 i915_gem_object_wait(struct drm_i915_gem_object
*obj
,
541 struct intel_rps_client
*rps
)
544 #if IS_ENABLED(CONFIG_LOCKDEP)
545 GEM_BUG_ON(debug_locks
&&
546 !!lockdep_is_held(&obj
->base
.dev
->struct_mutex
) !=
547 !!(flags
& I915_WAIT_LOCKED
));
549 GEM_BUG_ON(timeout
< 0);
551 timeout
= i915_gem_object_wait_reservation(obj
->resv
,
554 return timeout
< 0 ? timeout
: 0;
557 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
559 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
565 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
566 struct drm_i915_gem_pwrite
*args
,
567 struct drm_file
*file
)
569 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
570 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
572 /* We manually control the domain here and pretend that it
573 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
575 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
576 if (copy_from_user(vaddr
, user_data
, args
->size
))
579 drm_clflush_virt_range(vaddr
, args
->size
);
580 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
582 intel_fb_obj_flush(obj
, ORIGIN_CPU
);
586 void *i915_gem_object_alloc(struct drm_i915_private
*dev_priv
)
588 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
591 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
593 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
594 kmem_cache_free(dev_priv
->objects
, obj
);
598 i915_gem_create(struct drm_file
*file
,
599 struct drm_i915_private
*dev_priv
,
603 struct drm_i915_gem_object
*obj
;
607 size
= roundup(size
, PAGE_SIZE
);
611 /* Allocate the new object */
612 obj
= i915_gem_object_create(dev_priv
, size
);
616 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
617 /* drop reference from allocate - handle holds it now */
618 i915_gem_object_put(obj
);
627 i915_gem_dumb_create(struct drm_file
*file
,
628 struct drm_device
*dev
,
629 struct drm_mode_create_dumb
*args
)
631 /* have to work out size/pitch and return them */
632 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
633 args
->size
= args
->pitch
* args
->height
;
634 return i915_gem_create(file
, to_i915(dev
),
635 args
->size
, &args
->handle
);
638 static bool gpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
640 return !(obj
->cache_level
== I915_CACHE_NONE
||
641 obj
->cache_level
== I915_CACHE_WT
);
645 * Creates a new mm object and returns a handle to it.
646 * @dev: drm device pointer
647 * @data: ioctl data blob
648 * @file: drm file pointer
651 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
652 struct drm_file
*file
)
654 struct drm_i915_private
*dev_priv
= to_i915(dev
);
655 struct drm_i915_gem_create
*args
= data
;
657 i915_gem_flush_free_objects(dev_priv
);
659 return i915_gem_create(file
, dev_priv
,
660 args
->size
, &args
->handle
);
663 static inline enum fb_op_origin
664 fb_write_origin(struct drm_i915_gem_object
*obj
, unsigned int domain
)
666 return (domain
== I915_GEM_DOMAIN_GTT
?
667 obj
->frontbuffer_ggtt_origin
: ORIGIN_CPU
);
671 flush_write_domain(struct drm_i915_gem_object
*obj
, unsigned int flush_domains
)
673 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
675 if (!(obj
->base
.write_domain
& flush_domains
))
678 /* No actual flushing is required for the GTT write domain. Writes
679 * to it "immediately" go to main memory as far as we know, so there's
680 * no chipset flush. It also doesn't land in render cache.
682 * However, we do have to enforce the order so that all writes through
683 * the GTT land before any writes to the device, such as updates to
686 * We also have to wait a bit for the writes to land from the GTT.
687 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
688 * timing. This issue has only been observed when switching quickly
689 * between GTT writes and CPU reads from inside the kernel on recent hw,
690 * and it appears to only affect discrete GTT blocks (i.e. on LLC
691 * system agents we cannot reproduce this behaviour).
695 switch (obj
->base
.write_domain
) {
696 case I915_GEM_DOMAIN_GTT
:
697 if (!HAS_LLC(dev_priv
)) {
698 intel_runtime_pm_get(dev_priv
);
699 spin_lock_irq(&dev_priv
->uncore
.lock
);
700 POSTING_READ_FW(RING_HEAD(dev_priv
->engine
[RCS
]->mmio_base
));
701 spin_unlock_irq(&dev_priv
->uncore
.lock
);
702 intel_runtime_pm_put(dev_priv
);
705 intel_fb_obj_flush(obj
,
706 fb_write_origin(obj
, I915_GEM_DOMAIN_GTT
));
709 case I915_GEM_DOMAIN_CPU
:
710 i915_gem_clflush_object(obj
, I915_CLFLUSH_SYNC
);
713 case I915_GEM_DOMAIN_RENDER
:
714 if (gpu_write_needs_clflush(obj
))
715 obj
->cache_dirty
= true;
719 obj
->base
.write_domain
= 0;
723 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
724 const char *gpu_vaddr
, int gpu_offset
,
727 int ret
, cpu_offset
= 0;
730 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
731 int this_length
= min(cacheline_end
- gpu_offset
, length
);
732 int swizzled_gpu_offset
= gpu_offset
^ 64;
734 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
735 gpu_vaddr
+ swizzled_gpu_offset
,
740 cpu_offset
+= this_length
;
741 gpu_offset
+= this_length
;
742 length
-= this_length
;
749 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
750 const char __user
*cpu_vaddr
,
753 int ret
, cpu_offset
= 0;
756 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
757 int this_length
= min(cacheline_end
- gpu_offset
, length
);
758 int swizzled_gpu_offset
= gpu_offset
^ 64;
760 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
761 cpu_vaddr
+ cpu_offset
,
766 cpu_offset
+= this_length
;
767 gpu_offset
+= this_length
;
768 length
-= this_length
;
775 * Pins the specified object's pages and synchronizes the object with
776 * GPU accesses. Sets needs_clflush to non-zero if the caller should
777 * flush the object from the CPU cache.
779 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
780 unsigned int *needs_clflush
)
784 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
787 if (!i915_gem_object_has_struct_page(obj
))
790 ret
= i915_gem_object_wait(obj
,
791 I915_WAIT_INTERRUPTIBLE
|
793 MAX_SCHEDULE_TIMEOUT
,
798 ret
= i915_gem_object_pin_pages(obj
);
802 if (obj
->cache_coherent
& I915_BO_CACHE_COHERENT_FOR_READ
||
803 !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
804 ret
= i915_gem_object_set_to_cpu_domain(obj
, false);
811 flush_write_domain(obj
, ~I915_GEM_DOMAIN_CPU
);
813 /* If we're not in the cpu read domain, set ourself into the gtt
814 * read domain and manually flush cachelines (if required). This
815 * optimizes for the case when the gpu will dirty the data
816 * anyway again before the next pread happens.
818 if (!obj
->cache_dirty
&&
819 !(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
820 *needs_clflush
= CLFLUSH_BEFORE
;
823 /* return with the pages pinned */
827 i915_gem_object_unpin_pages(obj
);
831 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object
*obj
,
832 unsigned int *needs_clflush
)
836 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
839 if (!i915_gem_object_has_struct_page(obj
))
842 ret
= i915_gem_object_wait(obj
,
843 I915_WAIT_INTERRUPTIBLE
|
846 MAX_SCHEDULE_TIMEOUT
,
851 ret
= i915_gem_object_pin_pages(obj
);
855 if (obj
->cache_coherent
& I915_BO_CACHE_COHERENT_FOR_WRITE
||
856 !static_cpu_has(X86_FEATURE_CLFLUSH
)) {
857 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
864 flush_write_domain(obj
, ~I915_GEM_DOMAIN_CPU
);
866 /* If we're not in the cpu write domain, set ourself into the
867 * gtt write domain and manually flush cachelines (as required).
868 * This optimizes for the case when the gpu will use the data
869 * right away and we therefore have to clflush anyway.
871 if (!obj
->cache_dirty
) {
872 *needs_clflush
|= CLFLUSH_AFTER
;
875 * Same trick applies to invalidate partially written
876 * cachelines read before writing.
878 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
))
879 *needs_clflush
|= CLFLUSH_BEFORE
;
883 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
884 obj
->mm
.dirty
= true;
885 /* return with the pages pinned */
889 i915_gem_object_unpin_pages(obj
);
894 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
897 if (unlikely(swizzled
)) {
898 unsigned long start
= (unsigned long) addr
;
899 unsigned long end
= (unsigned long) addr
+ length
;
901 /* For swizzling simply ensure that we always flush both
902 * channels. Lame, but simple and it works. Swizzled
903 * pwrite/pread is far from a hotpath - current userspace
904 * doesn't use it at all. */
905 start
= round_down(start
, 128);
906 end
= round_up(end
, 128);
908 drm_clflush_virt_range((void *)start
, end
- start
);
910 drm_clflush_virt_range(addr
, length
);
915 /* Only difference to the fast-path function is that this can handle bit17
916 * and uses non-atomic copy and kmap functions. */
918 shmem_pread_slow(struct page
*page
, int offset
, int length
,
919 char __user
*user_data
,
920 bool page_do_bit17_swizzling
, bool needs_clflush
)
927 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
928 page_do_bit17_swizzling
);
930 if (page_do_bit17_swizzling
)
931 ret
= __copy_to_user_swizzled(user_data
, vaddr
, offset
, length
);
933 ret
= __copy_to_user(user_data
, vaddr
+ offset
, length
);
936 return ret
? - EFAULT
: 0;
940 shmem_pread(struct page
*page
, int offset
, int length
, char __user
*user_data
,
941 bool page_do_bit17_swizzling
, bool needs_clflush
)
946 if (!page_do_bit17_swizzling
) {
947 char *vaddr
= kmap_atomic(page
);
950 drm_clflush_virt_range(vaddr
+ offset
, length
);
951 ret
= __copy_to_user_inatomic(user_data
, vaddr
+ offset
, length
);
952 kunmap_atomic(vaddr
);
957 return shmem_pread_slow(page
, offset
, length
, user_data
,
958 page_do_bit17_swizzling
, needs_clflush
);
962 i915_gem_shmem_pread(struct drm_i915_gem_object
*obj
,
963 struct drm_i915_gem_pread
*args
)
965 char __user
*user_data
;
967 unsigned int obj_do_bit17_swizzling
;
968 unsigned int needs_clflush
;
969 unsigned int idx
, offset
;
972 obj_do_bit17_swizzling
= 0;
973 if (i915_gem_object_needs_bit17_swizzle(obj
))
974 obj_do_bit17_swizzling
= BIT(17);
976 ret
= mutex_lock_interruptible(&obj
->base
.dev
->struct_mutex
);
980 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
981 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
986 user_data
= u64_to_user_ptr(args
->data_ptr
);
987 offset
= offset_in_page(args
->offset
);
988 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
989 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
993 if (offset
+ length
> PAGE_SIZE
)
994 length
= PAGE_SIZE
- offset
;
996 ret
= shmem_pread(page
, offset
, length
, user_data
,
997 page_to_phys(page
) & obj_do_bit17_swizzling
,
1003 user_data
+= length
;
1007 i915_gem_obj_finish_shmem_access(obj
);
1012 gtt_user_read(struct io_mapping
*mapping
,
1013 loff_t base
, int offset
,
1014 char __user
*user_data
, int length
)
1016 void __iomem
*vaddr
;
1017 unsigned long unwritten
;
1019 /* We can use the cpu mem copy function because this is X86. */
1020 vaddr
= io_mapping_map_atomic_wc(mapping
, base
);
1021 unwritten
= __copy_to_user_inatomic(user_data
,
1022 (void __force
*)vaddr
+ offset
,
1024 io_mapping_unmap_atomic(vaddr
);
1026 vaddr
= io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1027 unwritten
= copy_to_user(user_data
,
1028 (void __force
*)vaddr
+ offset
,
1030 io_mapping_unmap(vaddr
);
1036 i915_gem_gtt_pread(struct drm_i915_gem_object
*obj
,
1037 const struct drm_i915_gem_pread
*args
)
1039 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1040 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1041 struct drm_mm_node node
;
1042 struct i915_vma
*vma
;
1043 void __user
*user_data
;
1047 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1051 intel_runtime_pm_get(i915
);
1052 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1053 PIN_MAPPABLE
| PIN_NONBLOCK
);
1055 node
.start
= i915_ggtt_offset(vma
);
1056 node
.allocated
= false;
1057 ret
= i915_vma_put_fence(vma
);
1059 i915_vma_unpin(vma
);
1064 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1067 GEM_BUG_ON(!node
.allocated
);
1070 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1074 mutex_unlock(&i915
->drm
.struct_mutex
);
1076 user_data
= u64_to_user_ptr(args
->data_ptr
);
1077 remain
= args
->size
;
1078 offset
= args
->offset
;
1080 while (remain
> 0) {
1081 /* Operation in this page
1083 * page_base = page offset within aperture
1084 * page_offset = offset within page
1085 * page_length = bytes to copy for this page
1087 u32 page_base
= node
.start
;
1088 unsigned page_offset
= offset_in_page(offset
);
1089 unsigned page_length
= PAGE_SIZE
- page_offset
;
1090 page_length
= remain
< page_length
? remain
: page_length
;
1091 if (node
.allocated
) {
1093 ggtt
->base
.insert_page(&ggtt
->base
,
1094 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1095 node
.start
, I915_CACHE_NONE
, 0);
1098 page_base
+= offset
& PAGE_MASK
;
1101 if (gtt_user_read(&ggtt
->mappable
, page_base
, page_offset
,
1102 user_data
, page_length
)) {
1107 remain
-= page_length
;
1108 user_data
+= page_length
;
1109 offset
+= page_length
;
1112 mutex_lock(&i915
->drm
.struct_mutex
);
1114 if (node
.allocated
) {
1116 ggtt
->base
.clear_range(&ggtt
->base
,
1117 node
.start
, node
.size
);
1118 remove_mappable_node(&node
);
1120 i915_vma_unpin(vma
);
1123 intel_runtime_pm_put(i915
);
1124 mutex_unlock(&i915
->drm
.struct_mutex
);
1130 * Reads data from the object referenced by handle.
1131 * @dev: drm device pointer
1132 * @data: ioctl data blob
1133 * @file: drm file pointer
1135 * On error, the contents of *data are undefined.
1138 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1139 struct drm_file
*file
)
1141 struct drm_i915_gem_pread
*args
= data
;
1142 struct drm_i915_gem_object
*obj
;
1145 if (args
->size
== 0)
1148 if (!access_ok(VERIFY_WRITE
,
1149 u64_to_user_ptr(args
->data_ptr
),
1153 obj
= i915_gem_object_lookup(file
, args
->handle
);
1157 /* Bounds check source. */
1158 if (range_overflows_t(u64
, args
->offset
, args
->size
, obj
->base
.size
)) {
1163 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
1165 ret
= i915_gem_object_wait(obj
,
1166 I915_WAIT_INTERRUPTIBLE
,
1167 MAX_SCHEDULE_TIMEOUT
,
1168 to_rps_client(file
));
1172 ret
= i915_gem_object_pin_pages(obj
);
1176 ret
= i915_gem_shmem_pread(obj
, args
);
1177 if (ret
== -EFAULT
|| ret
== -ENODEV
)
1178 ret
= i915_gem_gtt_pread(obj
, args
);
1180 i915_gem_object_unpin_pages(obj
);
1182 i915_gem_object_put(obj
);
1186 /* This is the fast write path which cannot handle
1187 * page faults in the source data
1191 ggtt_write(struct io_mapping
*mapping
,
1192 loff_t base
, int offset
,
1193 char __user
*user_data
, int length
)
1195 void __iomem
*vaddr
;
1196 unsigned long unwritten
;
1198 /* We can use the cpu mem copy function because this is X86. */
1199 vaddr
= io_mapping_map_atomic_wc(mapping
, base
);
1200 unwritten
= __copy_from_user_inatomic_nocache((void __force
*)vaddr
+ offset
,
1202 io_mapping_unmap_atomic(vaddr
);
1204 vaddr
= io_mapping_map_wc(mapping
, base
, PAGE_SIZE
);
1205 unwritten
= copy_from_user((void __force
*)vaddr
+ offset
,
1207 io_mapping_unmap(vaddr
);
1214 * This is the fast pwrite path, where we copy the data directly from the
1215 * user into the GTT, uncached.
1216 * @obj: i915 GEM object
1217 * @args: pwrite arguments structure
1220 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object
*obj
,
1221 const struct drm_i915_gem_pwrite
*args
)
1223 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1224 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
1225 struct drm_mm_node node
;
1226 struct i915_vma
*vma
;
1228 void __user
*user_data
;
1231 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1235 intel_runtime_pm_get(i915
);
1236 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0,
1237 PIN_MAPPABLE
| PIN_NONBLOCK
);
1239 node
.start
= i915_ggtt_offset(vma
);
1240 node
.allocated
= false;
1241 ret
= i915_vma_put_fence(vma
);
1243 i915_vma_unpin(vma
);
1248 ret
= insert_mappable_node(ggtt
, &node
, PAGE_SIZE
);
1251 GEM_BUG_ON(!node
.allocated
);
1254 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1258 mutex_unlock(&i915
->drm
.struct_mutex
);
1260 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1262 user_data
= u64_to_user_ptr(args
->data_ptr
);
1263 offset
= args
->offset
;
1264 remain
= args
->size
;
1266 /* Operation in this page
1268 * page_base = page offset within aperture
1269 * page_offset = offset within page
1270 * page_length = bytes to copy for this page
1272 u32 page_base
= node
.start
;
1273 unsigned int page_offset
= offset_in_page(offset
);
1274 unsigned int page_length
= PAGE_SIZE
- page_offset
;
1275 page_length
= remain
< page_length
? remain
: page_length
;
1276 if (node
.allocated
) {
1277 wmb(); /* flush the write before we modify the GGTT */
1278 ggtt
->base
.insert_page(&ggtt
->base
,
1279 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
1280 node
.start
, I915_CACHE_NONE
, 0);
1281 wmb(); /* flush modifications to the GGTT (insert_page) */
1283 page_base
+= offset
& PAGE_MASK
;
1285 /* If we get a fault while copying data, then (presumably) our
1286 * source page isn't available. Return the error and we'll
1287 * retry in the slow path.
1288 * If the object is non-shmem backed, we retry again with the
1289 * path that handles page fault.
1291 if (ggtt_write(&ggtt
->mappable
, page_base
, page_offset
,
1292 user_data
, page_length
)) {
1297 remain
-= page_length
;
1298 user_data
+= page_length
;
1299 offset
+= page_length
;
1301 intel_fb_obj_flush(obj
, ORIGIN_CPU
);
1303 mutex_lock(&i915
->drm
.struct_mutex
);
1305 if (node
.allocated
) {
1307 ggtt
->base
.clear_range(&ggtt
->base
,
1308 node
.start
, node
.size
);
1309 remove_mappable_node(&node
);
1311 i915_vma_unpin(vma
);
1314 intel_runtime_pm_put(i915
);
1315 mutex_unlock(&i915
->drm
.struct_mutex
);
1320 shmem_pwrite_slow(struct page
*page
, int offset
, int length
,
1321 char __user
*user_data
,
1322 bool page_do_bit17_swizzling
,
1323 bool needs_clflush_before
,
1324 bool needs_clflush_after
)
1330 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1331 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1332 page_do_bit17_swizzling
);
1333 if (page_do_bit17_swizzling
)
1334 ret
= __copy_from_user_swizzled(vaddr
, offset
, user_data
,
1337 ret
= __copy_from_user(vaddr
+ offset
, user_data
, length
);
1338 if (needs_clflush_after
)
1339 shmem_clflush_swizzled_range(vaddr
+ offset
, length
,
1340 page_do_bit17_swizzling
);
1343 return ret
? -EFAULT
: 0;
1346 /* Per-page copy function for the shmem pwrite fastpath.
1347 * Flushes invalid cachelines before writing to the target if
1348 * needs_clflush_before is set and flushes out any written cachelines after
1349 * writing if needs_clflush is set.
1352 shmem_pwrite(struct page
*page
, int offset
, int len
, char __user
*user_data
,
1353 bool page_do_bit17_swizzling
,
1354 bool needs_clflush_before
,
1355 bool needs_clflush_after
)
1360 if (!page_do_bit17_swizzling
) {
1361 char *vaddr
= kmap_atomic(page
);
1363 if (needs_clflush_before
)
1364 drm_clflush_virt_range(vaddr
+ offset
, len
);
1365 ret
= __copy_from_user_inatomic(vaddr
+ offset
, user_data
, len
);
1366 if (needs_clflush_after
)
1367 drm_clflush_virt_range(vaddr
+ offset
, len
);
1369 kunmap_atomic(vaddr
);
1374 return shmem_pwrite_slow(page
, offset
, len
, user_data
,
1375 page_do_bit17_swizzling
,
1376 needs_clflush_before
,
1377 needs_clflush_after
);
1381 i915_gem_shmem_pwrite(struct drm_i915_gem_object
*obj
,
1382 const struct drm_i915_gem_pwrite
*args
)
1384 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1385 void __user
*user_data
;
1387 unsigned int obj_do_bit17_swizzling
;
1388 unsigned int partial_cacheline_write
;
1389 unsigned int needs_clflush
;
1390 unsigned int offset
, idx
;
1393 ret
= mutex_lock_interruptible(&i915
->drm
.struct_mutex
);
1397 ret
= i915_gem_obj_prepare_shmem_write(obj
, &needs_clflush
);
1398 mutex_unlock(&i915
->drm
.struct_mutex
);
1402 obj_do_bit17_swizzling
= 0;
1403 if (i915_gem_object_needs_bit17_swizzle(obj
))
1404 obj_do_bit17_swizzling
= BIT(17);
1406 /* If we don't overwrite a cacheline completely we need to be
1407 * careful to have up-to-date data by first clflushing. Don't
1408 * overcomplicate things and flush the entire patch.
1410 partial_cacheline_write
= 0;
1411 if (needs_clflush
& CLFLUSH_BEFORE
)
1412 partial_cacheline_write
= boot_cpu_data
.x86_clflush_size
- 1;
1414 user_data
= u64_to_user_ptr(args
->data_ptr
);
1415 remain
= args
->size
;
1416 offset
= offset_in_page(args
->offset
);
1417 for (idx
= args
->offset
>> PAGE_SHIFT
; remain
; idx
++) {
1418 struct page
*page
= i915_gem_object_get_page(obj
, idx
);
1422 if (offset
+ length
> PAGE_SIZE
)
1423 length
= PAGE_SIZE
- offset
;
1425 ret
= shmem_pwrite(page
, offset
, length
, user_data
,
1426 page_to_phys(page
) & obj_do_bit17_swizzling
,
1427 (offset
| length
) & partial_cacheline_write
,
1428 needs_clflush
& CLFLUSH_AFTER
);
1433 user_data
+= length
;
1437 intel_fb_obj_flush(obj
, ORIGIN_CPU
);
1438 i915_gem_obj_finish_shmem_access(obj
);
1443 * Writes data to the object referenced by handle.
1445 * @data: ioctl data blob
1448 * On error, the contents of the buffer that were to be modified are undefined.
1451 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1452 struct drm_file
*file
)
1454 struct drm_i915_gem_pwrite
*args
= data
;
1455 struct drm_i915_gem_object
*obj
;
1458 if (args
->size
== 0)
1461 if (!access_ok(VERIFY_READ
,
1462 u64_to_user_ptr(args
->data_ptr
),
1466 obj
= i915_gem_object_lookup(file
, args
->handle
);
1470 /* Bounds check destination. */
1471 if (range_overflows_t(u64
, args
->offset
, args
->size
, obj
->base
.size
)) {
1476 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1479 if (obj
->ops
->pwrite
)
1480 ret
= obj
->ops
->pwrite(obj
, args
);
1484 ret
= i915_gem_object_wait(obj
,
1485 I915_WAIT_INTERRUPTIBLE
|
1487 MAX_SCHEDULE_TIMEOUT
,
1488 to_rps_client(file
));
1492 ret
= i915_gem_object_pin_pages(obj
);
1497 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1498 * it would end up going through the fenced access, and we'll get
1499 * different detiling behavior between reading and writing.
1500 * pread/pwrite currently are reading and writing from the CPU
1501 * perspective, requiring manual detiling by the client.
1503 if (!i915_gem_object_has_struct_page(obj
) ||
1504 cpu_write_needs_clflush(obj
))
1505 /* Note that the gtt paths might fail with non-page-backed user
1506 * pointers (e.g. gtt mappings when moving data between
1507 * textures). Fallback to the shmem path in that case.
1509 ret
= i915_gem_gtt_pwrite_fast(obj
, args
);
1511 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1512 if (obj
->phys_handle
)
1513 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1515 ret
= i915_gem_shmem_pwrite(obj
, args
);
1518 i915_gem_object_unpin_pages(obj
);
1520 i915_gem_object_put(obj
);
1524 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object
*obj
)
1526 struct drm_i915_private
*i915
;
1527 struct list_head
*list
;
1528 struct i915_vma
*vma
;
1530 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
1531 if (!i915_vma_is_ggtt(vma
))
1534 if (i915_vma_is_active(vma
))
1537 if (!drm_mm_node_allocated(&vma
->node
))
1540 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
1543 i915
= to_i915(obj
->base
.dev
);
1544 list
= obj
->bind_count
? &i915
->mm
.bound_list
: &i915
->mm
.unbound_list
;
1545 list_move_tail(&obj
->global_link
, list
);
1549 * Called when user space prepares to use an object with the CPU, either
1550 * through the mmap ioctl's mapping or a GTT mapping.
1552 * @data: ioctl data blob
1556 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1557 struct drm_file
*file
)
1559 struct drm_i915_gem_set_domain
*args
= data
;
1560 struct drm_i915_gem_object
*obj
;
1561 uint32_t read_domains
= args
->read_domains
;
1562 uint32_t write_domain
= args
->write_domain
;
1565 /* Only handle setting domains to types used by the CPU. */
1566 if ((write_domain
| read_domains
) & I915_GEM_GPU_DOMAINS
)
1569 /* Having something in the write domain implies it's in the read
1570 * domain, and only that read domain. Enforce that in the request.
1572 if (write_domain
!= 0 && read_domains
!= write_domain
)
1575 obj
= i915_gem_object_lookup(file
, args
->handle
);
1579 /* Try to flush the object off the GPU without holding the lock.
1580 * We will repeat the flush holding the lock in the normal manner
1581 * to catch cases where we are gazumped.
1583 err
= i915_gem_object_wait(obj
,
1584 I915_WAIT_INTERRUPTIBLE
|
1585 (write_domain
? I915_WAIT_ALL
: 0),
1586 MAX_SCHEDULE_TIMEOUT
,
1587 to_rps_client(file
));
1591 /* Flush and acquire obj->pages so that we are coherent through
1592 * direct access in memory with previous cached writes through
1593 * shmemfs and that our cache domain tracking remains valid.
1594 * For example, if the obj->filp was moved to swap without us
1595 * being notified and releasing the pages, we would mistakenly
1596 * continue to assume that the obj remained out of the CPU cached
1599 err
= i915_gem_object_pin_pages(obj
);
1603 err
= i915_mutex_lock_interruptible(dev
);
1607 if (read_domains
& I915_GEM_DOMAIN_WC
)
1608 err
= i915_gem_object_set_to_wc_domain(obj
, write_domain
);
1609 else if (read_domains
& I915_GEM_DOMAIN_GTT
)
1610 err
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
);
1612 err
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
);
1614 /* And bump the LRU for this access */
1615 i915_gem_object_bump_inactive_ggtt(obj
);
1617 mutex_unlock(&dev
->struct_mutex
);
1619 if (write_domain
!= 0)
1620 intel_fb_obj_invalidate(obj
,
1621 fb_write_origin(obj
, write_domain
));
1624 i915_gem_object_unpin_pages(obj
);
1626 i915_gem_object_put(obj
);
1631 * Called when user space has done writes to this buffer
1633 * @data: ioctl data blob
1637 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1638 struct drm_file
*file
)
1640 struct drm_i915_gem_sw_finish
*args
= data
;
1641 struct drm_i915_gem_object
*obj
;
1643 obj
= i915_gem_object_lookup(file
, args
->handle
);
1647 /* Pinned buffers may be scanout, so flush the cache */
1648 i915_gem_object_flush_if_display(obj
);
1649 i915_gem_object_put(obj
);
1655 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1658 * @data: ioctl data blob
1661 * While the mapping holds a reference on the contents of the object, it doesn't
1662 * imply a ref on the object itself.
1666 * DRM driver writers who look a this function as an example for how to do GEM
1667 * mmap support, please don't implement mmap support like here. The modern way
1668 * to implement DRM mmap support is with an mmap offset ioctl (like
1669 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1670 * That way debug tooling like valgrind will understand what's going on, hiding
1671 * the mmap call in a driver private ioctl will break that. The i915 driver only
1672 * does cpu mmaps this way because we didn't know better.
1675 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1676 struct drm_file
*file
)
1678 struct drm_i915_gem_mmap
*args
= data
;
1679 struct drm_i915_gem_object
*obj
;
1682 if (args
->flags
& ~(I915_MMAP_WC
))
1685 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1688 obj
= i915_gem_object_lookup(file
, args
->handle
);
1692 /* prime objects have no backing filp to GEM mmap
1695 if (!obj
->base
.filp
) {
1696 i915_gem_object_put(obj
);
1700 addr
= vm_mmap(obj
->base
.filp
, 0, args
->size
,
1701 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1703 if (args
->flags
& I915_MMAP_WC
) {
1704 struct mm_struct
*mm
= current
->mm
;
1705 struct vm_area_struct
*vma
;
1707 if (down_write_killable(&mm
->mmap_sem
)) {
1708 i915_gem_object_put(obj
);
1711 vma
= find_vma(mm
, addr
);
1714 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1717 up_write(&mm
->mmap_sem
);
1719 /* This may race, but that's ok, it only gets set */
1720 WRITE_ONCE(obj
->frontbuffer_ggtt_origin
, ORIGIN_CPU
);
1722 i915_gem_object_put(obj
);
1723 if (IS_ERR((void *)addr
))
1726 args
->addr_ptr
= (uint64_t) addr
;
1731 static unsigned int tile_row_pages(struct drm_i915_gem_object
*obj
)
1733 return i915_gem_object_get_tile_row_size(obj
) >> PAGE_SHIFT
;
1737 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1739 * A history of the GTT mmap interface:
1741 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1742 * aligned and suitable for fencing, and still fit into the available
1743 * mappable space left by the pinned display objects. A classic problem
1744 * we called the page-fault-of-doom where we would ping-pong between
1745 * two objects that could not fit inside the GTT and so the memcpy
1746 * would page one object in at the expense of the other between every
1749 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1750 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1751 * object is too large for the available space (or simply too large
1752 * for the mappable aperture!), a view is created instead and faulted
1753 * into userspace. (This view is aligned and sized appropriately for
1756 * 2 - Recognise WC as a separate cache domain so that we can flush the
1757 * delayed writes via GTT before performing direct access via WC.
1761 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1762 * hangs on some architectures, corruption on others. An attempt to service
1763 * a GTT page fault from a snoopable object will generate a SIGBUS.
1765 * * the object must be able to fit into RAM (physical memory, though no
1766 * limited to the mappable aperture).
1771 * * a new GTT page fault will synchronize rendering from the GPU and flush
1772 * all data to system memory. Subsequent access will not be synchronized.
1774 * * all mappings are revoked on runtime device suspend.
1776 * * there are only 8, 16 or 32 fence registers to share between all users
1777 * (older machines require fence register for display and blitter access
1778 * as well). Contention of the fence registers will cause the previous users
1779 * to be unmapped and any new access will generate new page faults.
1781 * * running out of memory while servicing a fault may generate a SIGBUS,
1782 * rather than the expected SIGSEGV.
1784 int i915_gem_mmap_gtt_version(void)
1789 static inline struct i915_ggtt_view
1790 compute_partial_view(struct drm_i915_gem_object
*obj
,
1791 pgoff_t page_offset
,
1794 struct i915_ggtt_view view
;
1796 if (i915_gem_object_is_tiled(obj
))
1797 chunk
= roundup(chunk
, tile_row_pages(obj
));
1799 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1800 view
.partial
.offset
= rounddown(page_offset
, chunk
);
1802 min_t(unsigned int, chunk
,
1803 (obj
->base
.size
>> PAGE_SHIFT
) - view
.partial
.offset
);
1805 /* If the partial covers the entire object, just create a normal VMA. */
1806 if (chunk
>= obj
->base
.size
>> PAGE_SHIFT
)
1807 view
.type
= I915_GGTT_VIEW_NORMAL
;
1813 * i915_gem_fault - fault a page into the GTT
1816 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1817 * from userspace. The fault handler takes care of binding the object to
1818 * the GTT (if needed), allocating and programming a fence register (again,
1819 * only if needed based on whether the old reg is still valid or the object
1820 * is tiled) and inserting a new PTE into the faulting process.
1822 * Note that the faulting process may involve evicting existing objects
1823 * from the GTT and/or fence registers to make room. So performance may
1824 * suffer if the GTT working set is large or there are few fence registers
1827 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1828 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1830 int i915_gem_fault(struct vm_fault
*vmf
)
1832 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1833 struct vm_area_struct
*area
= vmf
->vma
;
1834 struct drm_i915_gem_object
*obj
= to_intel_bo(area
->vm_private_data
);
1835 struct drm_device
*dev
= obj
->base
.dev
;
1836 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1837 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1838 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1839 struct i915_vma
*vma
;
1840 pgoff_t page_offset
;
1844 /* We don't use vmf->pgoff since that has the fake offset */
1845 page_offset
= (vmf
->address
- area
->vm_start
) >> PAGE_SHIFT
;
1847 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1849 /* Try to flush the object off the GPU first without holding the lock.
1850 * Upon acquiring the lock, we will perform our sanity checks and then
1851 * repeat the flush holding the lock in the normal manner to catch cases
1852 * where we are gazumped.
1854 ret
= i915_gem_object_wait(obj
,
1855 I915_WAIT_INTERRUPTIBLE
,
1856 MAX_SCHEDULE_TIMEOUT
,
1861 ret
= i915_gem_object_pin_pages(obj
);
1865 intel_runtime_pm_get(dev_priv
);
1867 ret
= i915_mutex_lock_interruptible(dev
);
1871 /* Access to snoopable pages through the GTT is incoherent. */
1872 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev_priv
)) {
1877 /* If the object is smaller than a couple of partial vma, it is
1878 * not worth only creating a single partial vma - we may as well
1879 * clear enough space for the full object.
1881 flags
= PIN_MAPPABLE
;
1882 if (obj
->base
.size
> 2 * MIN_CHUNK_PAGES
<< PAGE_SHIFT
)
1883 flags
|= PIN_NONBLOCK
| PIN_NONFAULT
;
1885 /* Now pin it into the GTT as needed */
1886 vma
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 0, flags
);
1888 /* Use a partial view if it is bigger than available space */
1889 struct i915_ggtt_view view
=
1890 compute_partial_view(obj
, page_offset
, MIN_CHUNK_PAGES
);
1892 /* Userspace is now writing through an untracked VMA, abandon
1893 * all hope that the hardware is able to track future writes.
1895 obj
->frontbuffer_ggtt_origin
= ORIGIN_CPU
;
1897 vma
= i915_gem_object_ggtt_pin(obj
, &view
, 0, 0, PIN_MAPPABLE
);
1904 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1908 ret
= i915_vma_get_fence(vma
);
1912 /* Mark as being mmapped into userspace for later revocation */
1913 assert_rpm_wakelock_held(dev_priv
);
1914 if (list_empty(&obj
->userfault_link
))
1915 list_add(&obj
->userfault_link
, &dev_priv
->mm
.userfault_list
);
1917 /* Finally, remap it using the new GTT offset */
1918 ret
= remap_io_mapping(area
,
1919 area
->vm_start
+ (vma
->ggtt_view
.partial
.offset
<< PAGE_SHIFT
),
1920 (ggtt
->mappable_base
+ vma
->node
.start
) >> PAGE_SHIFT
,
1921 min_t(u64
, vma
->size
, area
->vm_end
- area
->vm_start
),
1925 __i915_vma_unpin(vma
);
1927 mutex_unlock(&dev
->struct_mutex
);
1929 intel_runtime_pm_put(dev_priv
);
1930 i915_gem_object_unpin_pages(obj
);
1935 * We eat errors when the gpu is terminally wedged to avoid
1936 * userspace unduly crashing (gl has no provisions for mmaps to
1937 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1938 * and so needs to be reported.
1940 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1941 ret
= VM_FAULT_SIGBUS
;
1946 * EAGAIN means the gpu is hung and we'll wait for the error
1947 * handler to reset everything when re-faulting in
1948 * i915_mutex_lock_interruptible.
1955 * EBUSY is ok: this just means that another thread
1956 * already did the job.
1958 ret
= VM_FAULT_NOPAGE
;
1965 ret
= VM_FAULT_SIGBUS
;
1968 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1969 ret
= VM_FAULT_SIGBUS
;
1976 * i915_gem_release_mmap - remove physical page mappings
1977 * @obj: obj in question
1979 * Preserve the reservation of the mmapping with the DRM core code, but
1980 * relinquish ownership of the pages back to the system.
1982 * It is vital that we remove the page mapping if we have mapped a tiled
1983 * object through the GTT and then lose the fence register due to
1984 * resource pressure. Similarly if the object has been moved out of the
1985 * aperture, than pages mapped into userspace must be revoked. Removing the
1986 * mapping will then trigger a page fault on the next user access, allowing
1987 * fixup by i915_gem_fault().
1990 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1992 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
1994 /* Serialisation between user GTT access and our code depends upon
1995 * revoking the CPU's PTE whilst the mutex is held. The next user
1996 * pagefault then has to wait until we release the mutex.
1998 * Note that RPM complicates somewhat by adding an additional
1999 * requirement that operations to the GGTT be made holding the RPM
2002 lockdep_assert_held(&i915
->drm
.struct_mutex
);
2003 intel_runtime_pm_get(i915
);
2005 if (list_empty(&obj
->userfault_link
))
2008 list_del_init(&obj
->userfault_link
);
2009 drm_vma_node_unmap(&obj
->base
.vma_node
,
2010 obj
->base
.dev
->anon_inode
->i_mapping
);
2012 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2013 * memory transactions from userspace before we return. The TLB
2014 * flushing implied above by changing the PTE above *should* be
2015 * sufficient, an extra barrier here just provides us with a bit
2016 * of paranoid documentation about our requirement to serialise
2017 * memory writes before touching registers / GSM.
2022 intel_runtime_pm_put(i915
);
2025 void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv
)
2027 struct drm_i915_gem_object
*obj
, *on
;
2031 * Only called during RPM suspend. All users of the userfault_list
2032 * must be holding an RPM wakeref to ensure that this can not
2033 * run concurrently with themselves (and use the struct_mutex for
2034 * protection between themselves).
2037 list_for_each_entry_safe(obj
, on
,
2038 &dev_priv
->mm
.userfault_list
, userfault_link
) {
2039 list_del_init(&obj
->userfault_link
);
2040 drm_vma_node_unmap(&obj
->base
.vma_node
,
2041 obj
->base
.dev
->anon_inode
->i_mapping
);
2044 /* The fence will be lost when the device powers down. If any were
2045 * in use by hardware (i.e. they are pinned), we should not be powering
2046 * down! All other fences will be reacquired by the user upon waking.
2048 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2049 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2051 /* Ideally we want to assert that the fence register is not
2052 * live at this point (i.e. that no piece of code will be
2053 * trying to write through fence + GTT, as that both violates
2054 * our tracking of activity and associated locking/barriers,
2055 * but also is illegal given that the hw is powered down).
2057 * Previously we used reg->pin_count as a "liveness" indicator.
2058 * That is not sufficient, and we need a more fine-grained
2059 * tool if we want to have a sanity check here.
2065 GEM_BUG_ON(!list_empty(®
->vma
->obj
->userfault_link
));
2070 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2072 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2075 err
= drm_gem_create_mmap_offset(&obj
->base
);
2079 /* Attempt to reap some mmap space from dead objects */
2081 err
= i915_gem_wait_for_idle(dev_priv
, I915_WAIT_INTERRUPTIBLE
);
2085 i915_gem_drain_freed_objects(dev_priv
);
2086 err
= drm_gem_create_mmap_offset(&obj
->base
);
2090 } while (flush_delayed_work(&dev_priv
->gt
.retire_work
));
2095 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2097 drm_gem_free_mmap_offset(&obj
->base
);
2101 i915_gem_mmap_gtt(struct drm_file
*file
,
2102 struct drm_device
*dev
,
2106 struct drm_i915_gem_object
*obj
;
2109 obj
= i915_gem_object_lookup(file
, handle
);
2113 ret
= i915_gem_object_create_mmap_offset(obj
);
2115 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2117 i915_gem_object_put(obj
);
2122 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2124 * @data: GTT mapping ioctl data
2125 * @file: GEM object info
2127 * Simply returns the fake offset to userspace so it can mmap it.
2128 * The mmap call will end up in drm_gem_mmap(), which will set things
2129 * up so we can get faults in the handler above.
2131 * The fault handler will take care of binding the object into the GTT
2132 * (since it may have been evicted to make room for something), allocating
2133 * a fence register, and mapping the appropriate aperture address into
2137 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2138 struct drm_file
*file
)
2140 struct drm_i915_gem_mmap_gtt
*args
= data
;
2142 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2145 /* Immediately discard the backing storage */
2147 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2149 i915_gem_object_free_mmap_offset(obj
);
2151 if (obj
->base
.filp
== NULL
)
2154 /* Our goal here is to return as much of the memory as
2155 * is possible back to the system as we are called from OOM.
2156 * To do this we must instruct the shmfs to drop all of its
2157 * backing pages, *now*.
2159 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2160 obj
->mm
.madv
= __I915_MADV_PURGED
;
2161 obj
->mm
.pages
= ERR_PTR(-EFAULT
);
2164 /* Try to discard unwanted pages */
2165 void __i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2167 struct address_space
*mapping
;
2169 lockdep_assert_held(&obj
->mm
.lock
);
2170 GEM_BUG_ON(obj
->mm
.pages
);
2172 switch (obj
->mm
.madv
) {
2173 case I915_MADV_DONTNEED
:
2174 i915_gem_object_truncate(obj
);
2175 case __I915_MADV_PURGED
:
2179 if (obj
->base
.filp
== NULL
)
2182 mapping
= obj
->base
.filp
->f_mapping
,
2183 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2187 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
,
2188 struct sg_table
*pages
)
2190 struct sgt_iter sgt_iter
;
2193 __i915_gem_object_release_shmem(obj
, pages
, true);
2195 i915_gem_gtt_finish_pages(obj
, pages
);
2197 if (i915_gem_object_needs_bit17_swizzle(obj
))
2198 i915_gem_object_save_bit_17_swizzle(obj
, pages
);
2200 for_each_sgt_page(page
, sgt_iter
, pages
) {
2202 set_page_dirty(page
);
2204 if (obj
->mm
.madv
== I915_MADV_WILLNEED
)
2205 mark_page_accessed(page
);
2209 obj
->mm
.dirty
= false;
2211 sg_free_table(pages
);
2215 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object
*obj
)
2217 struct radix_tree_iter iter
;
2220 radix_tree_for_each_slot(slot
, &obj
->mm
.get_page
.radix
, &iter
, 0)
2221 radix_tree_delete(&obj
->mm
.get_page
.radix
, iter
.index
);
2224 void __i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
,
2225 enum i915_mm_subclass subclass
)
2227 struct sg_table
*pages
;
2229 if (i915_gem_object_has_pinned_pages(obj
))
2232 GEM_BUG_ON(obj
->bind_count
);
2233 if (!READ_ONCE(obj
->mm
.pages
))
2236 /* May be called by shrinker from within get_pages() (on another bo) */
2237 mutex_lock_nested(&obj
->mm
.lock
, subclass
);
2238 if (unlikely(atomic_read(&obj
->mm
.pages_pin_count
)))
2241 /* ->put_pages might need to allocate memory for the bit17 swizzle
2242 * array, hence protect them from being reaped by removing them from gtt
2244 pages
= fetch_and_zero(&obj
->mm
.pages
);
2247 if (obj
->mm
.mapping
) {
2250 ptr
= page_mask_bits(obj
->mm
.mapping
);
2251 if (is_vmalloc_addr(ptr
))
2254 kunmap(kmap_to_page(ptr
));
2256 obj
->mm
.mapping
= NULL
;
2259 __i915_gem_object_reset_page_iter(obj
);
2262 obj
->ops
->put_pages(obj
, pages
);
2265 mutex_unlock(&obj
->mm
.lock
);
2268 static bool i915_sg_trim(struct sg_table
*orig_st
)
2270 struct sg_table new_st
;
2271 struct scatterlist
*sg
, *new_sg
;
2274 if (orig_st
->nents
== orig_st
->orig_nents
)
2277 if (sg_alloc_table(&new_st
, orig_st
->nents
, GFP_KERNEL
| __GFP_NOWARN
))
2280 new_sg
= new_st
.sgl
;
2281 for_each_sg(orig_st
->sgl
, sg
, orig_st
->nents
, i
) {
2282 sg_set_page(new_sg
, sg_page(sg
), sg
->length
, 0);
2283 /* called before being DMA mapped, no need to copy sg->dma_* */
2284 new_sg
= sg_next(new_sg
);
2286 GEM_BUG_ON(new_sg
); /* Should walk exactly nents and hit the end */
2288 sg_free_table(orig_st
);
2294 static struct sg_table
*
2295 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2297 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2298 const unsigned long page_count
= obj
->base
.size
/ PAGE_SIZE
;
2300 struct address_space
*mapping
;
2301 struct sg_table
*st
;
2302 struct scatterlist
*sg
;
2303 struct sgt_iter sgt_iter
;
2305 unsigned long last_pfn
= 0; /* suppress gcc warning */
2306 unsigned int max_segment
= i915_sg_segment_size();
2310 /* Assert that the object is not currently in any GPU domain. As it
2311 * wasn't in the GTT, there shouldn't be any way it could have been in
2314 GEM_BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2315 GEM_BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2317 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2319 return ERR_PTR(-ENOMEM
);
2322 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2324 return ERR_PTR(-ENOMEM
);
2327 /* Get the list of pages out of our struct file. They'll be pinned
2328 * at this point until we release them.
2330 * Fail silently without starting the shrinker
2332 mapping
= obj
->base
.filp
->f_mapping
;
2333 noreclaim
= mapping_gfp_constraint(mapping
, ~__GFP_RECLAIM
);
2334 noreclaim
|= __GFP_NORETRY
| __GFP_NOWARN
;
2338 for (i
= 0; i
< page_count
; i
++) {
2339 const unsigned int shrink
[] = {
2340 I915_SHRINK_BOUND
| I915_SHRINK_UNBOUND
| I915_SHRINK_PURGEABLE
,
2343 gfp_t gfp
= noreclaim
;
2346 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2347 if (likely(!IS_ERR(page
)))
2351 ret
= PTR_ERR(page
);
2355 i915_gem_shrink(dev_priv
, 2 * page_count
, NULL
, *s
++);
2358 /* We've tried hard to allocate the memory by reaping
2359 * our own buffer, now let the real VM do its job and
2360 * go down in flames if truly OOM.
2362 * However, since graphics tend to be disposable,
2363 * defer the oom here by reporting the ENOMEM back
2367 /* reclaim and warn, but no oom */
2368 gfp
= mapping_gfp_mask(mapping
);
2370 /* Our bo are always dirty and so we require
2371 * kswapd to reclaim our pages (direct reclaim
2372 * does not effectively begin pageout of our
2373 * buffers on its own). However, direct reclaim
2374 * only waits for kswapd when under allocation
2375 * congestion. So as a result __GFP_RECLAIM is
2376 * unreliable and fails to actually reclaim our
2377 * dirty pages -- unless you try over and over
2378 * again with !__GFP_NORETRY. However, we still
2379 * want to fail this allocation rather than
2380 * trigger the out-of-memory killer and for
2381 * this we want __GFP_RETRY_MAYFAIL.
2383 gfp
|= __GFP_RETRY_MAYFAIL
;
2388 sg
->length
>= max_segment
||
2389 page_to_pfn(page
) != last_pfn
+ 1) {
2393 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2395 sg
->length
+= PAGE_SIZE
;
2397 last_pfn
= page_to_pfn(page
);
2399 /* Check that the i965g/gm workaround works. */
2400 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2402 if (sg
) /* loop terminated early; short sg table */
2405 /* Trim unused sg entries to avoid wasting memory. */
2408 ret
= i915_gem_gtt_prepare_pages(obj
, st
);
2410 /* DMA remapping failed? One possible cause is that
2411 * it could not reserve enough large entries, asking
2412 * for PAGE_SIZE chunks instead may be helpful.
2414 if (max_segment
> PAGE_SIZE
) {
2415 for_each_sgt_page(page
, sgt_iter
, st
)
2419 max_segment
= PAGE_SIZE
;
2422 dev_warn(&dev_priv
->drm
.pdev
->dev
,
2423 "Failed to DMA remap %lu pages\n",
2429 if (i915_gem_object_needs_bit17_swizzle(obj
))
2430 i915_gem_object_do_bit_17_swizzle(obj
, st
);
2437 for_each_sgt_page(page
, sgt_iter
, st
)
2442 /* shmemfs first checks if there is enough memory to allocate the page
2443 * and reports ENOSPC should there be insufficient, along with the usual
2444 * ENOMEM for a genuine allocation failure.
2446 * We use ENOSPC in our driver to mean that we have run out of aperture
2447 * space and so want to translate the error from shmemfs back to our
2448 * usual understanding of ENOMEM.
2453 return ERR_PTR(ret
);
2456 void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj
,
2457 struct sg_table
*pages
)
2459 lockdep_assert_held(&obj
->mm
.lock
);
2461 obj
->mm
.get_page
.sg_pos
= pages
->sgl
;
2462 obj
->mm
.get_page
.sg_idx
= 0;
2464 obj
->mm
.pages
= pages
;
2466 if (i915_gem_object_is_tiled(obj
) &&
2467 to_i915(obj
->base
.dev
)->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
2468 GEM_BUG_ON(obj
->mm
.quirked
);
2469 __i915_gem_object_pin_pages(obj
);
2470 obj
->mm
.quirked
= true;
2474 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2476 struct sg_table
*pages
;
2478 if (unlikely(obj
->mm
.madv
!= I915_MADV_WILLNEED
)) {
2479 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2483 pages
= obj
->ops
->get_pages(obj
);
2484 if (unlikely(IS_ERR(pages
)))
2485 return PTR_ERR(pages
);
2487 __i915_gem_object_set_pages(obj
, pages
);
2491 /* Ensure that the associated pages are gathered from the backing storage
2492 * and pinned into our object. i915_gem_object_pin_pages() may be called
2493 * multiple times before they are released by a single call to
2494 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2495 * either as a result of memory pressure (reaping pages under the shrinker)
2496 * or as the object is itself released.
2498 int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2502 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
2506 if (unlikely(IS_ERR_OR_NULL(obj
->mm
.pages
))) {
2507 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj
));
2509 err
= ____i915_gem_object_get_pages(obj
);
2513 smp_mb__before_atomic();
2515 atomic_inc(&obj
->mm
.pages_pin_count
);
2518 mutex_unlock(&obj
->mm
.lock
);
2522 /* The 'mapping' part of i915_gem_object_pin_map() below */
2523 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
,
2524 enum i915_map_type type
)
2526 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2527 struct sg_table
*sgt
= obj
->mm
.pages
;
2528 struct sgt_iter sgt_iter
;
2530 struct page
*stack_pages
[32];
2531 struct page
**pages
= stack_pages
;
2532 unsigned long i
= 0;
2536 /* A single page can always be kmapped */
2537 if (n_pages
== 1 && type
== I915_MAP_WB
)
2538 return kmap(sg_page(sgt
->sgl
));
2540 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2541 /* Too big for stack -- allocate temporary array instead */
2542 pages
= kvmalloc_array(n_pages
, sizeof(*pages
), GFP_KERNEL
);
2547 for_each_sgt_page(page
, sgt_iter
, sgt
)
2550 /* Check that we have the expected number of pages */
2551 GEM_BUG_ON(i
!= n_pages
);
2556 /* fallthrough to use PAGE_KERNEL anyway */
2558 pgprot
= PAGE_KERNEL
;
2561 pgprot
= pgprot_writecombine(PAGE_KERNEL_IO
);
2564 addr
= vmap(pages
, n_pages
, 0, pgprot
);
2566 if (pages
!= stack_pages
)
2572 /* get, pin, and map the pages of the object into kernel space */
2573 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
2574 enum i915_map_type type
)
2576 enum i915_map_type has_type
;
2581 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
2583 ret
= mutex_lock_interruptible(&obj
->mm
.lock
);
2585 return ERR_PTR(ret
);
2587 pinned
= !(type
& I915_MAP_OVERRIDE
);
2588 type
&= ~I915_MAP_OVERRIDE
;
2590 if (!atomic_inc_not_zero(&obj
->mm
.pages_pin_count
)) {
2591 if (unlikely(IS_ERR_OR_NULL(obj
->mm
.pages
))) {
2592 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj
));
2594 ret
= ____i915_gem_object_get_pages(obj
);
2598 smp_mb__before_atomic();
2600 atomic_inc(&obj
->mm
.pages_pin_count
);
2603 GEM_BUG_ON(!obj
->mm
.pages
);
2605 ptr
= page_unpack_bits(obj
->mm
.mapping
, &has_type
);
2606 if (ptr
&& has_type
!= type
) {
2612 if (is_vmalloc_addr(ptr
))
2615 kunmap(kmap_to_page(ptr
));
2617 ptr
= obj
->mm
.mapping
= NULL
;
2621 ptr
= i915_gem_object_map(obj
, type
);
2627 obj
->mm
.mapping
= page_pack_bits(ptr
, type
);
2631 mutex_unlock(&obj
->mm
.lock
);
2635 atomic_dec(&obj
->mm
.pages_pin_count
);
2642 i915_gem_object_pwrite_gtt(struct drm_i915_gem_object
*obj
,
2643 const struct drm_i915_gem_pwrite
*arg
)
2645 struct address_space
*mapping
= obj
->base
.filp
->f_mapping
;
2646 char __user
*user_data
= u64_to_user_ptr(arg
->data_ptr
);
2650 /* Before we instantiate/pin the backing store for our use, we
2651 * can prepopulate the shmemfs filp efficiently using a write into
2652 * the pagecache. We avoid the penalty of instantiating all the
2653 * pages, important if the user is just writing to a few and never
2654 * uses the object on the GPU, and using a direct write into shmemfs
2655 * allows it to avoid the cost of retrieving a page (either swapin
2656 * or clearing-before-use) before it is overwritten.
2658 if (READ_ONCE(obj
->mm
.pages
))
2661 /* Before the pages are instantiated the object is treated as being
2662 * in the CPU domain. The pages will be clflushed as required before
2663 * use, and we can freely write into the pages directly. If userspace
2664 * races pwrite with any other operation; corruption will ensue -
2665 * that is userspace's prerogative!
2669 offset
= arg
->offset
;
2670 pg
= offset_in_page(offset
);
2673 unsigned int len
, unwritten
;
2678 len
= PAGE_SIZE
- pg
;
2682 err
= pagecache_write_begin(obj
->base
.filp
, mapping
,
2689 unwritten
= copy_from_user(vaddr
+ pg
, user_data
, len
);
2692 err
= pagecache_write_end(obj
->base
.filp
, mapping
,
2693 offset
, len
, len
- unwritten
,
2710 static bool ban_context(const struct i915_gem_context
*ctx
,
2713 return (i915_gem_context_is_bannable(ctx
) &&
2714 score
>= CONTEXT_SCORE_BAN_THRESHOLD
);
2717 static void i915_gem_context_mark_guilty(struct i915_gem_context
*ctx
)
2722 atomic_inc(&ctx
->guilty_count
);
2724 score
= atomic_add_return(CONTEXT_SCORE_GUILTY
, &ctx
->ban_score
);
2725 banned
= ban_context(ctx
, score
);
2726 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2727 ctx
->name
, score
, yesno(banned
));
2731 i915_gem_context_set_banned(ctx
);
2732 if (!IS_ERR_OR_NULL(ctx
->file_priv
)) {
2733 atomic_inc(&ctx
->file_priv
->context_bans
);
2734 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2735 ctx
->name
, atomic_read(&ctx
->file_priv
->context_bans
));
2739 static void i915_gem_context_mark_innocent(struct i915_gem_context
*ctx
)
2741 atomic_inc(&ctx
->active_count
);
2744 struct drm_i915_gem_request
*
2745 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2747 struct drm_i915_gem_request
*request
, *active
= NULL
;
2748 unsigned long flags
;
2750 /* We are called by the error capture and reset at a random
2751 * point in time. In particular, note that neither is crucially
2752 * ordered with an interrupt. After a hang, the GPU is dead and we
2753 * assume that no more writes can happen (we waited long enough for
2754 * all writes that were in transaction to be flushed) - adding an
2755 * extra delay for a recent interrupt is pointless. Hence, we do
2756 * not need an engine->irq_seqno_barrier() before the seqno reads.
2758 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2759 list_for_each_entry(request
, &engine
->timeline
->requests
, link
) {
2760 if (__i915_gem_request_completed(request
,
2761 request
->global_seqno
))
2764 GEM_BUG_ON(request
->engine
!= engine
);
2765 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
,
2766 &request
->fence
.flags
));
2771 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2776 static bool engine_stalled(struct intel_engine_cs
*engine
)
2778 if (!engine
->hangcheck
.stalled
)
2781 /* Check for possible seqno movement after hang declaration */
2782 if (engine
->hangcheck
.seqno
!= intel_engine_get_seqno(engine
)) {
2783 DRM_DEBUG_DRIVER("%s pardoned\n", engine
->name
);
2791 * Ensure irq handler finishes, and not run again.
2792 * Also return the active request so that we only search for it once.
2794 struct drm_i915_gem_request
*
2795 i915_gem_reset_prepare_engine(struct intel_engine_cs
*engine
)
2797 struct drm_i915_gem_request
*request
= NULL
;
2799 /* Prevent the signaler thread from updating the request
2800 * state (by calling dma_fence_signal) as we are processing
2801 * the reset. The write from the GPU of the seqno is
2802 * asynchronous and the signaler thread may see a different
2803 * value to us and declare the request complete, even though
2804 * the reset routine have picked that request as the active
2805 * (incomplete) request. This conflict is not handled
2808 kthread_park(engine
->breadcrumbs
.signaler
);
2810 /* Prevent request submission to the hardware until we have
2811 * completed the reset in i915_gem_reset_finish(). If a request
2812 * is completed by one engine, it may then queue a request
2813 * to a second via its engine->irq_tasklet *just* as we are
2814 * calling engine->init_hw() and also writing the ELSP.
2815 * Turning off the engine->irq_tasklet until the reset is over
2816 * prevents the race.
2818 tasklet_kill(&engine
->execlists
.irq_tasklet
);
2819 tasklet_disable(&engine
->execlists
.irq_tasklet
);
2821 if (engine
->irq_seqno_barrier
)
2822 engine
->irq_seqno_barrier(engine
);
2824 request
= i915_gem_find_active_request(engine
);
2825 if (request
&& request
->fence
.error
== -EIO
)
2826 request
= ERR_PTR(-EIO
); /* Previous reset failed! */
2831 int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv
)
2833 struct intel_engine_cs
*engine
;
2834 struct drm_i915_gem_request
*request
;
2835 enum intel_engine_id id
;
2838 for_each_engine(engine
, dev_priv
, id
) {
2839 request
= i915_gem_reset_prepare_engine(engine
);
2840 if (IS_ERR(request
)) {
2841 err
= PTR_ERR(request
);
2845 engine
->hangcheck
.active_request
= request
;
2848 i915_gem_revoke_fences(dev_priv
);
2853 static void skip_request(struct drm_i915_gem_request
*request
)
2855 void *vaddr
= request
->ring
->vaddr
;
2858 /* As this request likely depends on state from the lost
2859 * context, clear out all the user operations leaving the
2860 * breadcrumb at the end (so we get the fence notifications).
2862 head
= request
->head
;
2863 if (request
->postfix
< head
) {
2864 memset(vaddr
+ head
, 0, request
->ring
->size
- head
);
2867 memset(vaddr
+ head
, 0, request
->postfix
- head
);
2869 dma_fence_set_error(&request
->fence
, -EIO
);
2872 static void engine_skip_context(struct drm_i915_gem_request
*request
)
2874 struct intel_engine_cs
*engine
= request
->engine
;
2875 struct i915_gem_context
*hung_ctx
= request
->ctx
;
2876 struct intel_timeline
*timeline
;
2877 unsigned long flags
;
2879 timeline
= i915_gem_context_lookup_timeline(hung_ctx
, engine
);
2881 spin_lock_irqsave(&engine
->timeline
->lock
, flags
);
2882 spin_lock(&timeline
->lock
);
2884 list_for_each_entry_continue(request
, &engine
->timeline
->requests
, link
)
2885 if (request
->ctx
== hung_ctx
)
2886 skip_request(request
);
2888 list_for_each_entry(request
, &timeline
->requests
, link
)
2889 skip_request(request
);
2891 spin_unlock(&timeline
->lock
);
2892 spin_unlock_irqrestore(&engine
->timeline
->lock
, flags
);
2895 /* Returns the request if it was guilty of the hang */
2896 static struct drm_i915_gem_request
*
2897 i915_gem_reset_request(struct intel_engine_cs
*engine
,
2898 struct drm_i915_gem_request
*request
)
2900 /* The guilty request will get skipped on a hung engine.
2902 * Users of client default contexts do not rely on logical
2903 * state preserved between batches so it is safe to execute
2904 * queued requests following the hang. Non default contexts
2905 * rely on preserved state, so skipping a batch loses the
2906 * evolution of the state and it needs to be considered corrupted.
2907 * Executing more queued batches on top of corrupted state is
2908 * risky. But we take the risk by trying to advance through
2909 * the queued requests in order to make the client behaviour
2910 * more predictable around resets, by not throwing away random
2911 * amount of batches it has prepared for execution. Sophisticated
2912 * clients can use gem_reset_stats_ioctl and dma fence status
2913 * (exported via sync_file info ioctl on explicit fences) to observe
2914 * when it loses the context state and should rebuild accordingly.
2916 * The context ban, and ultimately the client ban, mechanism are safety
2917 * valves if client submission ends up resulting in nothing more than
2921 if (engine_stalled(engine
)) {
2922 i915_gem_context_mark_guilty(request
->ctx
);
2923 skip_request(request
);
2925 /* If this context is now banned, skip all pending requests. */
2926 if (i915_gem_context_is_banned(request
->ctx
))
2927 engine_skip_context(request
);
2930 * Since this is not the hung engine, it may have advanced
2931 * since the hang declaration. Double check by refinding
2932 * the active request at the time of the reset.
2934 request
= i915_gem_find_active_request(engine
);
2936 i915_gem_context_mark_innocent(request
->ctx
);
2937 dma_fence_set_error(&request
->fence
, -EAGAIN
);
2939 /* Rewind the engine to replay the incomplete rq */
2940 spin_lock_irq(&engine
->timeline
->lock
);
2941 request
= list_prev_entry(request
, link
);
2942 if (&request
->link
== &engine
->timeline
->requests
)
2944 spin_unlock_irq(&engine
->timeline
->lock
);
2951 void i915_gem_reset_engine(struct intel_engine_cs
*engine
,
2952 struct drm_i915_gem_request
*request
)
2954 engine
->irq_posted
= 0;
2957 request
= i915_gem_reset_request(engine
, request
);
2960 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2961 engine
->name
, request
->global_seqno
);
2964 /* Setup the CS to resume from the breadcrumb of the hung request */
2965 engine
->reset_hw(engine
, request
);
2968 void i915_gem_reset(struct drm_i915_private
*dev_priv
)
2970 struct intel_engine_cs
*engine
;
2971 enum intel_engine_id id
;
2973 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
2975 i915_gem_retire_requests(dev_priv
);
2977 for_each_engine(engine
, dev_priv
, id
) {
2978 struct i915_gem_context
*ctx
;
2980 i915_gem_reset_engine(engine
, engine
->hangcheck
.active_request
);
2981 ctx
= fetch_and_zero(&engine
->last_retired_context
);
2983 engine
->context_unpin(engine
, ctx
);
2986 i915_gem_restore_fences(dev_priv
);
2988 if (dev_priv
->gt
.awake
) {
2989 intel_sanitize_gt_powersave(dev_priv
);
2990 intel_enable_gt_powersave(dev_priv
);
2991 if (INTEL_GEN(dev_priv
) >= 6)
2992 gen6_rps_busy(dev_priv
);
2996 void i915_gem_reset_finish_engine(struct intel_engine_cs
*engine
)
2998 tasklet_enable(&engine
->execlists
.irq_tasklet
);
2999 kthread_unpark(engine
->breadcrumbs
.signaler
);
3002 void i915_gem_reset_finish(struct drm_i915_private
*dev_priv
)
3004 struct intel_engine_cs
*engine
;
3005 enum intel_engine_id id
;
3007 lockdep_assert_held(&dev_priv
->drm
.struct_mutex
);
3009 for_each_engine(engine
, dev_priv
, id
) {
3010 engine
->hangcheck
.active_request
= NULL
;
3011 i915_gem_reset_finish_engine(engine
);
3015 static void nop_submit_request(struct drm_i915_gem_request
*request
)
3017 GEM_BUG_ON(!i915_terminally_wedged(&request
->i915
->gpu_error
));
3018 dma_fence_set_error(&request
->fence
, -EIO
);
3019 i915_gem_request_submit(request
);
3020 intel_engine_init_global_seqno(request
->engine
, request
->global_seqno
);
3023 static void engine_set_wedged(struct intel_engine_cs
*engine
)
3025 /* We need to be sure that no thread is running the old callback as
3026 * we install the nop handler (otherwise we would submit a request
3027 * to hardware that will never complete). In order to prevent this
3028 * race, we wait until the machine is idle before making the swap
3029 * (using stop_machine()).
3031 engine
->submit_request
= nop_submit_request
;
3033 /* Mark all executing requests as skipped */
3034 engine
->cancel_requests(engine
);
3036 /* Mark all pending requests as complete so that any concurrent
3037 * (lockless) lookup doesn't try and wait upon the request as we
3040 intel_engine_init_global_seqno(engine
,
3041 intel_engine_last_submit(engine
));
3044 static int __i915_gem_set_wedged_BKL(void *data
)
3046 struct drm_i915_private
*i915
= data
;
3047 struct intel_engine_cs
*engine
;
3048 enum intel_engine_id id
;
3050 for_each_engine(engine
, i915
, id
)
3051 engine_set_wedged(engine
);
3053 set_bit(I915_WEDGED
, &i915
->gpu_error
.flags
);
3054 wake_up_all(&i915
->gpu_error
.reset_queue
);
3059 void i915_gem_set_wedged(struct drm_i915_private
*dev_priv
)
3061 stop_machine(__i915_gem_set_wedged_BKL
, dev_priv
, NULL
);
3064 bool i915_gem_unset_wedged(struct drm_i915_private
*i915
)
3066 struct i915_gem_timeline
*tl
;
3069 lockdep_assert_held(&i915
->drm
.struct_mutex
);
3070 if (!test_bit(I915_WEDGED
, &i915
->gpu_error
.flags
))
3073 /* Before unwedging, make sure that all pending operations
3074 * are flushed and errored out - we may have requests waiting upon
3075 * third party fences. We marked all inflight requests as EIO, and
3076 * every execbuf since returned EIO, for consistency we want all
3077 * the currently pending requests to also be marked as EIO, which
3078 * is done inside our nop_submit_request - and so we must wait.
3080 * No more can be submitted until we reset the wedged bit.
3082 list_for_each_entry(tl
, &i915
->gt
.timelines
, link
) {
3083 for (i
= 0; i
< ARRAY_SIZE(tl
->engine
); i
++) {
3084 struct drm_i915_gem_request
*rq
;
3086 rq
= i915_gem_active_peek(&tl
->engine
[i
].last_request
,
3087 &i915
->drm
.struct_mutex
);
3091 /* We can't use our normal waiter as we want to
3092 * avoid recursively trying to handle the current
3093 * reset. The basic dma_fence_default_wait() installs
3094 * a callback for dma_fence_signal(), which is
3095 * triggered by our nop handler (indirectly, the
3096 * callback enables the signaler thread which is
3097 * woken by the nop_submit_request() advancing the seqno
3098 * and when the seqno passes the fence, the signaler
3099 * then signals the fence waking us up).
3101 if (dma_fence_default_wait(&rq
->fence
, true,
3102 MAX_SCHEDULE_TIMEOUT
) < 0)
3107 /* Undo nop_submit_request. We prevent all new i915 requests from
3108 * being queued (by disallowing execbuf whilst wedged) so having
3109 * waited for all active requests above, we know the system is idle
3110 * and do not have to worry about a thread being inside
3111 * engine->submit_request() as we swap over. So unlike installing
3112 * the nop_submit_request on reset, we can do this from normal
3113 * context and do not require stop_machine().
3115 intel_engines_reset_default_submission(i915
);
3116 i915_gem_contexts_lost(i915
);
3118 smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
3119 clear_bit(I915_WEDGED
, &i915
->gpu_error
.flags
);
3125 i915_gem_retire_work_handler(struct work_struct
*work
)
3127 struct drm_i915_private
*dev_priv
=
3128 container_of(work
, typeof(*dev_priv
), gt
.retire_work
.work
);
3129 struct drm_device
*dev
= &dev_priv
->drm
;
3131 /* Come back later if the device is busy... */
3132 if (mutex_trylock(&dev
->struct_mutex
)) {
3133 i915_gem_retire_requests(dev_priv
);
3134 mutex_unlock(&dev
->struct_mutex
);
3137 /* Keep the retire handler running until we are finally idle.
3138 * We do not need to do this test under locking as in the worst-case
3139 * we queue the retire worker once too often.
3141 if (READ_ONCE(dev_priv
->gt
.awake
)) {
3142 i915_queue_hangcheck(dev_priv
);
3143 queue_delayed_work(dev_priv
->wq
,
3144 &dev_priv
->gt
.retire_work
,
3145 round_jiffies_up_relative(HZ
));
3150 i915_gem_idle_work_handler(struct work_struct
*work
)
3152 struct drm_i915_private
*dev_priv
=
3153 container_of(work
, typeof(*dev_priv
), gt
.idle_work
.work
);
3154 struct drm_device
*dev
= &dev_priv
->drm
;
3155 bool rearm_hangcheck
;
3157 if (!READ_ONCE(dev_priv
->gt
.awake
))
3161 * Wait for last execlists context complete, but bail out in case a
3162 * new request is submitted.
3164 wait_for(intel_engines_are_idle(dev_priv
), 10);
3165 if (READ_ONCE(dev_priv
->gt
.active_requests
))
3169 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
3171 if (!mutex_trylock(&dev
->struct_mutex
)) {
3172 /* Currently busy, come back later */
3173 mod_delayed_work(dev_priv
->wq
,
3174 &dev_priv
->gt
.idle_work
,
3175 msecs_to_jiffies(50));
3180 * New request retired after this work handler started, extend active
3181 * period until next instance of the work.
3183 if (work_pending(work
))
3186 if (dev_priv
->gt
.active_requests
)
3189 if (wait_for(intel_engines_are_idle(dev_priv
), 10))
3190 DRM_ERROR("Timeout waiting for engines to idle\n");
3192 intel_engines_mark_idle(dev_priv
);
3193 i915_gem_timelines_mark_idle(dev_priv
);
3195 GEM_BUG_ON(!dev_priv
->gt
.awake
);
3196 dev_priv
->gt
.awake
= false;
3197 rearm_hangcheck
= false;
3199 if (INTEL_GEN(dev_priv
) >= 6)
3200 gen6_rps_idle(dev_priv
);
3201 intel_runtime_pm_put(dev_priv
);
3203 mutex_unlock(&dev
->struct_mutex
);
3206 if (rearm_hangcheck
) {
3207 GEM_BUG_ON(!dev_priv
->gt
.awake
);
3208 i915_queue_hangcheck(dev_priv
);
3212 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
)
3214 struct drm_i915_private
*i915
= to_i915(gem
->dev
);
3215 struct drm_i915_gem_object
*obj
= to_intel_bo(gem
);
3216 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
3217 struct i915_lut_handle
*lut
, *ln
;
3219 mutex_lock(&i915
->drm
.struct_mutex
);
3221 list_for_each_entry_safe(lut
, ln
, &obj
->lut_list
, obj_link
) {
3222 struct i915_gem_context
*ctx
= lut
->ctx
;
3223 struct i915_vma
*vma
;
3225 GEM_BUG_ON(ctx
->file_priv
== ERR_PTR(-EBADF
));
3226 if (ctx
->file_priv
!= fpriv
)
3229 vma
= radix_tree_delete(&ctx
->handles_vma
, lut
->handle
);
3230 GEM_BUG_ON(vma
->obj
!= obj
);
3232 /* We allow the process to have multiple handles to the same
3233 * vma, in the same fd namespace, by virtue of flink/open.
3235 GEM_BUG_ON(!vma
->open_count
);
3236 if (!--vma
->open_count
&& !i915_vma_is_ggtt(vma
))
3237 i915_vma_close(vma
);
3239 list_del(&lut
->obj_link
);
3240 list_del(&lut
->ctx_link
);
3242 kmem_cache_free(i915
->luts
, lut
);
3243 __i915_gem_object_release_unless_active(obj
);
3246 mutex_unlock(&i915
->drm
.struct_mutex
);
3249 static unsigned long to_wait_timeout(s64 timeout_ns
)
3252 return MAX_SCHEDULE_TIMEOUT
;
3254 if (timeout_ns
== 0)
3257 return nsecs_to_jiffies_timeout(timeout_ns
);
3261 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3262 * @dev: drm device pointer
3263 * @data: ioctl data blob
3264 * @file: drm file pointer
3266 * Returns 0 if successful, else an error is returned with the remaining time in
3267 * the timeout parameter.
3268 * -ETIME: object is still busy after timeout
3269 * -ERESTARTSYS: signal interrupted the wait
3270 * -ENONENT: object doesn't exist
3271 * Also possible, but rare:
3272 * -EAGAIN: incomplete, restart syscall
3274 * -ENODEV: Internal IRQ fail
3275 * -E?: The add request failed
3277 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3278 * non-zero timeout parameter the wait ioctl will wait for the given number of
3279 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3280 * without holding struct_mutex the object may become re-busied before this
3281 * function completes. A similar but shorter * race condition exists in the busy
3285 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3287 struct drm_i915_gem_wait
*args
= data
;
3288 struct drm_i915_gem_object
*obj
;
3292 if (args
->flags
!= 0)
3295 obj
= i915_gem_object_lookup(file
, args
->bo_handle
);
3299 start
= ktime_get();
3301 ret
= i915_gem_object_wait(obj
,
3302 I915_WAIT_INTERRUPTIBLE
| I915_WAIT_ALL
,
3303 to_wait_timeout(args
->timeout_ns
),
3304 to_rps_client(file
));
3306 if (args
->timeout_ns
> 0) {
3307 args
->timeout_ns
-= ktime_to_ns(ktime_sub(ktime_get(), start
));
3308 if (args
->timeout_ns
< 0)
3309 args
->timeout_ns
= 0;
3312 * Apparently ktime isn't accurate enough and occasionally has a
3313 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3314 * things up to make the test happy. We allow up to 1 jiffy.
3316 * This is a regression from the timespec->ktime conversion.
3318 if (ret
== -ETIME
&& !nsecs_to_jiffies(args
->timeout_ns
))
3319 args
->timeout_ns
= 0;
3321 /* Asked to wait beyond the jiffie/scheduler precision? */
3322 if (ret
== -ETIME
&& args
->timeout_ns
)
3326 i915_gem_object_put(obj
);
3330 static int wait_for_timeline(struct i915_gem_timeline
*tl
, unsigned int flags
)
3334 for (i
= 0; i
< ARRAY_SIZE(tl
->engine
); i
++) {
3335 ret
= i915_gem_active_wait(&tl
->engine
[i
].last_request
, flags
);
3343 static int wait_for_engines(struct drm_i915_private
*i915
)
3345 if (wait_for(intel_engines_are_idle(i915
), 50)) {
3346 DRM_ERROR("Failed to idle engines, declaring wedged!\n");
3347 i915_gem_set_wedged(i915
);
3354 int i915_gem_wait_for_idle(struct drm_i915_private
*i915
, unsigned int flags
)
3358 /* If the device is asleep, we have no requests outstanding */
3359 if (!READ_ONCE(i915
->gt
.awake
))
3362 if (flags
& I915_WAIT_LOCKED
) {
3363 struct i915_gem_timeline
*tl
;
3365 lockdep_assert_held(&i915
->drm
.struct_mutex
);
3367 list_for_each_entry(tl
, &i915
->gt
.timelines
, link
) {
3368 ret
= wait_for_timeline(tl
, flags
);
3373 i915_gem_retire_requests(i915
);
3374 GEM_BUG_ON(i915
->gt
.active_requests
);
3376 ret
= wait_for_engines(i915
);
3378 ret
= wait_for_timeline(&i915
->gt
.global_timeline
, flags
);
3384 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object
*obj
)
3387 * We manually flush the CPU domain so that we can override and
3388 * force the flush for the display, and perform it asyncrhonously.
3390 flush_write_domain(obj
, ~I915_GEM_DOMAIN_CPU
);
3391 if (obj
->cache_dirty
)
3392 i915_gem_clflush_object(obj
, I915_CLFLUSH_FORCE
);
3393 obj
->base
.write_domain
= 0;
3396 void i915_gem_object_flush_if_display(struct drm_i915_gem_object
*obj
)
3398 if (!READ_ONCE(obj
->pin_display
))
3401 mutex_lock(&obj
->base
.dev
->struct_mutex
);
3402 __i915_gem_object_flush_for_display(obj
);
3403 mutex_unlock(&obj
->base
.dev
->struct_mutex
);
3407 * Moves a single object to the WC read, and possibly write domain.
3408 * @obj: object to act on
3409 * @write: ask for write access or read only
3411 * This function returns when the move is complete, including waiting on
3415 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object
*obj
, bool write
)
3419 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3421 ret
= i915_gem_object_wait(obj
,
3422 I915_WAIT_INTERRUPTIBLE
|
3424 (write
? I915_WAIT_ALL
: 0),
3425 MAX_SCHEDULE_TIMEOUT
,
3430 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_WC
)
3433 /* Flush and acquire obj->pages so that we are coherent through
3434 * direct access in memory with previous cached writes through
3435 * shmemfs and that our cache domain tracking remains valid.
3436 * For example, if the obj->filp was moved to swap without us
3437 * being notified and releasing the pages, we would mistakenly
3438 * continue to assume that the obj remained out of the CPU cached
3441 ret
= i915_gem_object_pin_pages(obj
);
3445 flush_write_domain(obj
, ~I915_GEM_DOMAIN_WC
);
3447 /* Serialise direct access to this object with the barriers for
3448 * coherent writes from the GPU, by effectively invalidating the
3449 * WC domain upon first access.
3451 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_WC
) == 0)
3454 /* It should now be out of any other write domains, and we can update
3455 * the domain values for our changes.
3457 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_WC
) != 0);
3458 obj
->base
.read_domains
|= I915_GEM_DOMAIN_WC
;
3460 obj
->base
.read_domains
= I915_GEM_DOMAIN_WC
;
3461 obj
->base
.write_domain
= I915_GEM_DOMAIN_WC
;
3462 obj
->mm
.dirty
= true;
3465 i915_gem_object_unpin_pages(obj
);
3470 * Moves a single object to the GTT read, and possibly write domain.
3471 * @obj: object to act on
3472 * @write: ask for write access or read only
3474 * This function returns when the move is complete, including waiting on
3478 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3482 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3484 ret
= i915_gem_object_wait(obj
,
3485 I915_WAIT_INTERRUPTIBLE
|
3487 (write
? I915_WAIT_ALL
: 0),
3488 MAX_SCHEDULE_TIMEOUT
,
3493 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3496 /* Flush and acquire obj->pages so that we are coherent through
3497 * direct access in memory with previous cached writes through
3498 * shmemfs and that our cache domain tracking remains valid.
3499 * For example, if the obj->filp was moved to swap without us
3500 * being notified and releasing the pages, we would mistakenly
3501 * continue to assume that the obj remained out of the CPU cached
3504 ret
= i915_gem_object_pin_pages(obj
);
3508 flush_write_domain(obj
, ~I915_GEM_DOMAIN_GTT
);
3510 /* Serialise direct access to this object with the barriers for
3511 * coherent writes from the GPU, by effectively invalidating the
3512 * GTT domain upon first access.
3514 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3517 /* It should now be out of any other write domains, and we can update
3518 * the domain values for our changes.
3520 GEM_BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3521 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3523 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3524 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3525 obj
->mm
.dirty
= true;
3528 i915_gem_object_unpin_pages(obj
);
3533 * Changes the cache-level of an object across all VMA.
3534 * @obj: object to act on
3535 * @cache_level: new cache level to set for the object
3537 * After this function returns, the object will be in the new cache-level
3538 * across all GTT and the contents of the backing storage will be coherent,
3539 * with respect to the new cache-level. In order to keep the backing storage
3540 * coherent for all users, we only allow a single cache level to be set
3541 * globally on the object and prevent it from being changed whilst the
3542 * hardware is reading from the object. That is if the object is currently
3543 * on the scanout it will be set to uncached (or equivalent display
3544 * cache coherency) and all non-MOCS GPU access will also be uncached so
3545 * that all direct access to the scanout remains coherent.
3547 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3548 enum i915_cache_level cache_level
)
3550 struct i915_vma
*vma
;
3553 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3555 if (obj
->cache_level
== cache_level
)
3558 /* Inspect the list of currently bound VMA and unbind any that would
3559 * be invalid given the new cache-level. This is principally to
3560 * catch the issue of the CS prefetch crossing page boundaries and
3561 * reading an invalid PTE on older architectures.
3564 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3565 if (!drm_mm_node_allocated(&vma
->node
))
3568 if (i915_vma_is_pinned(vma
)) {
3569 DRM_DEBUG("can not change the cache level of pinned objects\n");
3573 if (i915_gem_valid_gtt_space(vma
, cache_level
))
3576 ret
= i915_vma_unbind(vma
);
3580 /* As unbinding may affect other elements in the
3581 * obj->vma_list (due to side-effects from retiring
3582 * an active vma), play safe and restart the iterator.
3587 /* We can reuse the existing drm_mm nodes but need to change the
3588 * cache-level on the PTE. We could simply unbind them all and
3589 * rebind with the correct cache-level on next use. However since
3590 * we already have a valid slot, dma mapping, pages etc, we may as
3591 * rewrite the PTE in the belief that doing so tramples upon less
3592 * state and so involves less work.
3594 if (obj
->bind_count
) {
3595 /* Before we change the PTE, the GPU must not be accessing it.
3596 * If we wait upon the object, we know that all the bound
3597 * VMA are no longer active.
3599 ret
= i915_gem_object_wait(obj
,
3600 I915_WAIT_INTERRUPTIBLE
|
3603 MAX_SCHEDULE_TIMEOUT
,
3608 if (!HAS_LLC(to_i915(obj
->base
.dev
)) &&
3609 cache_level
!= I915_CACHE_NONE
) {
3610 /* Access to snoopable pages through the GTT is
3611 * incoherent and on some machines causes a hard
3612 * lockup. Relinquish the CPU mmaping to force
3613 * userspace to refault in the pages and we can
3614 * then double check if the GTT mapping is still
3615 * valid for that pointer access.
3617 i915_gem_release_mmap(obj
);
3619 /* As we no longer need a fence for GTT access,
3620 * we can relinquish it now (and so prevent having
3621 * to steal a fence from someone else on the next
3622 * fence request). Note GPU activity would have
3623 * dropped the fence as all snoopable access is
3624 * supposed to be linear.
3626 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3627 ret
= i915_vma_put_fence(vma
);
3632 /* We either have incoherent backing store and
3633 * so no GTT access or the architecture is fully
3634 * coherent. In such cases, existing GTT mmaps
3635 * ignore the cache bit in the PTE and we can
3636 * rewrite it without confusing the GPU or having
3637 * to force userspace to fault back in its mmaps.
3641 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3642 if (!drm_mm_node_allocated(&vma
->node
))
3645 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3651 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3652 vma
->node
.color
= cache_level
;
3653 i915_gem_object_set_cache_coherency(obj
, cache_level
);
3654 obj
->cache_dirty
= true; /* Always invalidate stale cachelines */
3659 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3660 struct drm_file
*file
)
3662 struct drm_i915_gem_caching
*args
= data
;
3663 struct drm_i915_gem_object
*obj
;
3667 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
3673 switch (obj
->cache_level
) {
3674 case I915_CACHE_LLC
:
3675 case I915_CACHE_L3_LLC
:
3676 args
->caching
= I915_CACHING_CACHED
;
3680 args
->caching
= I915_CACHING_DISPLAY
;
3684 args
->caching
= I915_CACHING_NONE
;
3692 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3693 struct drm_file
*file
)
3695 struct drm_i915_private
*i915
= to_i915(dev
);
3696 struct drm_i915_gem_caching
*args
= data
;
3697 struct drm_i915_gem_object
*obj
;
3698 enum i915_cache_level level
;
3701 switch (args
->caching
) {
3702 case I915_CACHING_NONE
:
3703 level
= I915_CACHE_NONE
;
3705 case I915_CACHING_CACHED
:
3707 * Due to a HW issue on BXT A stepping, GPU stores via a
3708 * snooped mapping may leave stale data in a corresponding CPU
3709 * cacheline, whereas normally such cachelines would get
3712 if (!HAS_LLC(i915
) && !HAS_SNOOP(i915
))
3715 level
= I915_CACHE_LLC
;
3717 case I915_CACHING_DISPLAY
:
3718 level
= HAS_WT(i915
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3724 obj
= i915_gem_object_lookup(file
, args
->handle
);
3728 if (obj
->cache_level
== level
)
3731 ret
= i915_gem_object_wait(obj
,
3732 I915_WAIT_INTERRUPTIBLE
,
3733 MAX_SCHEDULE_TIMEOUT
,
3734 to_rps_client(file
));
3738 ret
= i915_mutex_lock_interruptible(dev
);
3742 ret
= i915_gem_object_set_cache_level(obj
, level
);
3743 mutex_unlock(&dev
->struct_mutex
);
3746 i915_gem_object_put(obj
);
3751 * Prepare buffer for display plane (scanout, cursors, etc).
3752 * Can be called from an uninterruptible phase (modesetting) and allows
3753 * any flushes to be pipelined (for pageflips).
3756 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3758 const struct i915_ggtt_view
*view
)
3760 struct i915_vma
*vma
;
3763 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3765 /* Mark the pin_display early so that we account for the
3766 * display coherency whilst setting up the cache domains.
3770 /* The display engine is not coherent with the LLC cache on gen6. As
3771 * a result, we make sure that the pinning that is about to occur is
3772 * done with uncached PTEs. This is lowest common denominator for all
3775 * However for gen6+, we could do better by using the GFDT bit instead
3776 * of uncaching, which would allow us to flush all the LLC-cached data
3777 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3779 ret
= i915_gem_object_set_cache_level(obj
,
3780 HAS_WT(to_i915(obj
->base
.dev
)) ?
3781 I915_CACHE_WT
: I915_CACHE_NONE
);
3784 goto err_unpin_display
;
3787 /* As the user may map the buffer once pinned in the display plane
3788 * (e.g. libkms for the bootup splash), we have to ensure that we
3789 * always use map_and_fenceable for all scanout buffers. However,
3790 * it may simply be too big to fit into mappable, in which case
3791 * put it anyway and hope that userspace can cope (but always first
3792 * try to preserve the existing ABI).
3794 vma
= ERR_PTR(-ENOSPC
);
3795 if (!view
|| view
->type
== I915_GGTT_VIEW_NORMAL
)
3796 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
,
3797 PIN_MAPPABLE
| PIN_NONBLOCK
);
3799 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3802 /* Valleyview is definitely limited to scanning out the first
3803 * 512MiB. Lets presume this behaviour was inherited from the
3804 * g4x display engine and that all earlier gen are similarly
3805 * limited. Testing suggests that it is a little more
3806 * complicated than this. For example, Cherryview appears quite
3807 * happy to scanout from anywhere within its global aperture.
3810 if (HAS_GMCH_DISPLAY(i915
))
3811 flags
= PIN_MAPPABLE
;
3812 vma
= i915_gem_object_ggtt_pin(obj
, view
, 0, alignment
, flags
);
3815 goto err_unpin_display
;
3817 vma
->display_alignment
= max_t(u64
, vma
->display_alignment
, alignment
);
3819 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3820 __i915_gem_object_flush_for_display(obj
);
3821 intel_fb_obj_flush(obj
, ORIGIN_DIRTYFB
);
3823 /* It should now be out of any other write domains, and we can update
3824 * the domain values for our changes.
3826 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3836 i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
)
3838 lockdep_assert_held(&vma
->vm
->i915
->drm
.struct_mutex
);
3840 if (WARN_ON(vma
->obj
->pin_display
== 0))
3843 if (--vma
->obj
->pin_display
== 0)
3844 vma
->display_alignment
= I915_GTT_MIN_ALIGNMENT
;
3846 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3847 i915_gem_object_bump_inactive_ggtt(vma
->obj
);
3849 i915_vma_unpin(vma
);
3853 * Moves a single object to the CPU read, and possibly write domain.
3854 * @obj: object to act on
3855 * @write: requesting write or read-only access
3857 * This function returns when the move is complete, including waiting on
3861 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3865 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3867 ret
= i915_gem_object_wait(obj
,
3868 I915_WAIT_INTERRUPTIBLE
|
3870 (write
? I915_WAIT_ALL
: 0),
3871 MAX_SCHEDULE_TIMEOUT
,
3876 flush_write_domain(obj
, ~I915_GEM_DOMAIN_CPU
);
3878 /* Flush the CPU cache if it's still invalid. */
3879 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3880 i915_gem_clflush_object(obj
, I915_CLFLUSH_SYNC
);
3881 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3884 /* It should now be out of any other write domains, and we can update
3885 * the domain values for our changes.
3887 GEM_BUG_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3889 /* If we're writing through the CPU, then the GPU read domains will
3890 * need to be invalidated at next use.
3893 __start_cpu_write(obj
);
3898 /* Throttle our rendering by waiting until the ring has completed our requests
3899 * emitted over 20 msec ago.
3901 * Note that if we were to use the current jiffies each time around the loop,
3902 * we wouldn't escape the function with any frames outstanding if the time to
3903 * render a frame was over 20ms.
3905 * This should get us reasonable parallelism between CPU and GPU but also
3906 * relatively low latency when blocking on a particular request to finish.
3909 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3911 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3912 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3913 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
3914 struct drm_i915_gem_request
*request
, *target
= NULL
;
3917 /* ABI: return -EIO if already wedged */
3918 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
3921 spin_lock(&file_priv
->mm
.lock
);
3922 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_link
) {
3923 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3927 list_del(&target
->client_link
);
3928 target
->file_priv
= NULL
;
3934 i915_gem_request_get(target
);
3935 spin_unlock(&file_priv
->mm
.lock
);
3940 ret
= i915_wait_request(target
,
3941 I915_WAIT_INTERRUPTIBLE
,
3942 MAX_SCHEDULE_TIMEOUT
);
3943 i915_gem_request_put(target
);
3945 return ret
< 0 ? ret
: 0;
3949 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3950 const struct i915_ggtt_view
*view
,
3955 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3956 struct i915_address_space
*vm
= &dev_priv
->ggtt
.base
;
3957 struct i915_vma
*vma
;
3960 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3962 vma
= i915_vma_instance(obj
, vm
, view
);
3963 if (unlikely(IS_ERR(vma
)))
3966 if (i915_vma_misplaced(vma
, size
, alignment
, flags
)) {
3967 if (flags
& PIN_NONBLOCK
&&
3968 (i915_vma_is_pinned(vma
) || i915_vma_is_active(vma
)))
3969 return ERR_PTR(-ENOSPC
);
3971 if (flags
& PIN_MAPPABLE
) {
3972 /* If the required space is larger than the available
3973 * aperture, we will not able to find a slot for the
3974 * object and unbinding the object now will be in
3975 * vain. Worse, doing so may cause us to ping-pong
3976 * the object in and out of the Global GTT and
3977 * waste a lot of cycles under the mutex.
3979 if (vma
->fence_size
> dev_priv
->ggtt
.mappable_end
)
3980 return ERR_PTR(-E2BIG
);
3982 /* If NONBLOCK is set the caller is optimistically
3983 * trying to cache the full object within the mappable
3984 * aperture, and *must* have a fallback in place for
3985 * situations where we cannot bind the object. We
3986 * can be a little more lax here and use the fallback
3987 * more often to avoid costly migrations of ourselves
3988 * and other objects within the aperture.
3990 * Half-the-aperture is used as a simple heuristic.
3991 * More interesting would to do search for a free
3992 * block prior to making the commitment to unbind.
3993 * That caters for the self-harm case, and with a
3994 * little more heuristics (e.g. NOFAULT, NOEVICT)
3995 * we could try to minimise harm to others.
3997 if (flags
& PIN_NONBLOCK
&&
3998 vma
->fence_size
> dev_priv
->ggtt
.mappable_end
/ 2)
3999 return ERR_PTR(-ENOSPC
);
4002 WARN(i915_vma_is_pinned(vma
),
4003 "bo is already pinned in ggtt with incorrect alignment:"
4004 " offset=%08x, req.alignment=%llx,"
4005 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
4006 i915_ggtt_offset(vma
), alignment
,
4007 !!(flags
& PIN_MAPPABLE
),
4008 i915_vma_is_map_and_fenceable(vma
));
4009 ret
= i915_vma_unbind(vma
);
4011 return ERR_PTR(ret
);
4014 ret
= i915_vma_pin(vma
, size
, alignment
, flags
| PIN_GLOBAL
);
4016 return ERR_PTR(ret
);
4021 static __always_inline
unsigned int __busy_read_flag(unsigned int id
)
4023 /* Note that we could alias engines in the execbuf API, but
4024 * that would be very unwise as it prevents userspace from
4025 * fine control over engine selection. Ahem.
4027 * This should be something like EXEC_MAX_ENGINE instead of
4030 BUILD_BUG_ON(I915_NUM_ENGINES
> 16);
4031 return 0x10000 << id
;
4034 static __always_inline
unsigned int __busy_write_id(unsigned int id
)
4036 /* The uABI guarantees an active writer is also amongst the read
4037 * engines. This would be true if we accessed the activity tracking
4038 * under the lock, but as we perform the lookup of the object and
4039 * its activity locklessly we can not guarantee that the last_write
4040 * being active implies that we have set the same engine flag from
4041 * last_read - hence we always set both read and write busy for
4044 return id
| __busy_read_flag(id
);
4047 static __always_inline
unsigned int
4048 __busy_set_if_active(const struct dma_fence
*fence
,
4049 unsigned int (*flag
)(unsigned int id
))
4051 struct drm_i915_gem_request
*rq
;
4053 /* We have to check the current hw status of the fence as the uABI
4054 * guarantees forward progress. We could rely on the idle worker
4055 * to eventually flush us, but to minimise latency just ask the
4058 * Note we only report on the status of native fences.
4060 if (!dma_fence_is_i915(fence
))
4063 /* opencode to_request() in order to avoid const warnings */
4064 rq
= container_of(fence
, struct drm_i915_gem_request
, fence
);
4065 if (i915_gem_request_completed(rq
))
4068 return flag(rq
->engine
->uabi_id
);
4071 static __always_inline
unsigned int
4072 busy_check_reader(const struct dma_fence
*fence
)
4074 return __busy_set_if_active(fence
, __busy_read_flag
);
4077 static __always_inline
unsigned int
4078 busy_check_writer(const struct dma_fence
*fence
)
4083 return __busy_set_if_active(fence
, __busy_write_id
);
4087 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4088 struct drm_file
*file
)
4090 struct drm_i915_gem_busy
*args
= data
;
4091 struct drm_i915_gem_object
*obj
;
4092 struct reservation_object_list
*list
;
4098 obj
= i915_gem_object_lookup_rcu(file
, args
->handle
);
4102 /* A discrepancy here is that we do not report the status of
4103 * non-i915 fences, i.e. even though we may report the object as idle,
4104 * a call to set-domain may still stall waiting for foreign rendering.
4105 * This also means that wait-ioctl may report an object as busy,
4106 * where busy-ioctl considers it idle.
4108 * We trade the ability to warn of foreign fences to report on which
4109 * i915 engines are active for the object.
4111 * Alternatively, we can trade that extra information on read/write
4114 * !reservation_object_test_signaled_rcu(obj->resv, true);
4115 * to report the overall busyness. This is what the wait-ioctl does.
4119 seq
= raw_read_seqcount(&obj
->resv
->seq
);
4121 /* Translate the exclusive fence to the READ *and* WRITE engine */
4122 args
->busy
= busy_check_writer(rcu_dereference(obj
->resv
->fence_excl
));
4124 /* Translate shared fences to READ set of engines */
4125 list
= rcu_dereference(obj
->resv
->fence
);
4127 unsigned int shared_count
= list
->shared_count
, i
;
4129 for (i
= 0; i
< shared_count
; ++i
) {
4130 struct dma_fence
*fence
=
4131 rcu_dereference(list
->shared
[i
]);
4133 args
->busy
|= busy_check_reader(fence
);
4137 if (args
->busy
&& read_seqcount_retry(&obj
->resv
->seq
, seq
))
4147 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4148 struct drm_file
*file_priv
)
4150 return i915_gem_ring_throttle(dev
, file_priv
);
4154 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4155 struct drm_file
*file_priv
)
4157 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4158 struct drm_i915_gem_madvise
*args
= data
;
4159 struct drm_i915_gem_object
*obj
;
4162 switch (args
->madv
) {
4163 case I915_MADV_DONTNEED
:
4164 case I915_MADV_WILLNEED
:
4170 obj
= i915_gem_object_lookup(file_priv
, args
->handle
);
4174 err
= mutex_lock_interruptible(&obj
->mm
.lock
);
4178 if (obj
->mm
.pages
&&
4179 i915_gem_object_is_tiled(obj
) &&
4180 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4181 if (obj
->mm
.madv
== I915_MADV_WILLNEED
) {
4182 GEM_BUG_ON(!obj
->mm
.quirked
);
4183 __i915_gem_object_unpin_pages(obj
);
4184 obj
->mm
.quirked
= false;
4186 if (args
->madv
== I915_MADV_WILLNEED
) {
4187 GEM_BUG_ON(obj
->mm
.quirked
);
4188 __i915_gem_object_pin_pages(obj
);
4189 obj
->mm
.quirked
= true;
4193 if (obj
->mm
.madv
!= __I915_MADV_PURGED
)
4194 obj
->mm
.madv
= args
->madv
;
4196 /* if the object is no longer attached, discard its backing storage */
4197 if (obj
->mm
.madv
== I915_MADV_DONTNEED
&& !obj
->mm
.pages
)
4198 i915_gem_object_truncate(obj
);
4200 args
->retained
= obj
->mm
.madv
!= __I915_MADV_PURGED
;
4201 mutex_unlock(&obj
->mm
.lock
);
4204 i915_gem_object_put(obj
);
4209 frontbuffer_retire(struct i915_gem_active
*active
,
4210 struct drm_i915_gem_request
*request
)
4212 struct drm_i915_gem_object
*obj
=
4213 container_of(active
, typeof(*obj
), frontbuffer_write
);
4215 intel_fb_obj_flush(obj
, ORIGIN_CS
);
4218 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4219 const struct drm_i915_gem_object_ops
*ops
)
4221 mutex_init(&obj
->mm
.lock
);
4223 INIT_LIST_HEAD(&obj
->global_link
);
4224 INIT_LIST_HEAD(&obj
->userfault_link
);
4225 INIT_LIST_HEAD(&obj
->vma_list
);
4226 INIT_LIST_HEAD(&obj
->lut_list
);
4227 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4231 reservation_object_init(&obj
->__builtin_resv
);
4232 obj
->resv
= &obj
->__builtin_resv
;
4234 obj
->frontbuffer_ggtt_origin
= ORIGIN_GTT
;
4235 init_request_active(&obj
->frontbuffer_write
, frontbuffer_retire
);
4237 obj
->mm
.madv
= I915_MADV_WILLNEED
;
4238 INIT_RADIX_TREE(&obj
->mm
.get_page
.radix
, GFP_KERNEL
| __GFP_NOWARN
);
4239 mutex_init(&obj
->mm
.get_page
.lock
);
4241 i915_gem_info_add_obj(to_i915(obj
->base
.dev
), obj
->base
.size
);
4244 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4245 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
|
4246 I915_GEM_OBJECT_IS_SHRINKABLE
,
4248 .get_pages
= i915_gem_object_get_pages_gtt
,
4249 .put_pages
= i915_gem_object_put_pages_gtt
,
4251 .pwrite
= i915_gem_object_pwrite_gtt
,
4254 struct drm_i915_gem_object
*
4255 i915_gem_object_create(struct drm_i915_private
*dev_priv
, u64 size
)
4257 struct drm_i915_gem_object
*obj
;
4258 struct address_space
*mapping
;
4259 unsigned int cache_level
;
4263 /* There is a prevalence of the assumption that we fit the object's
4264 * page count inside a 32bit _signed_ variable. Let's document this and
4265 * catch if we ever need to fix it. In the meantime, if you do spot
4266 * such a local variable, please consider fixing!
4268 if (size
>> PAGE_SHIFT
> INT_MAX
)
4269 return ERR_PTR(-E2BIG
);
4271 if (overflows_type(size
, obj
->base
.size
))
4272 return ERR_PTR(-E2BIG
);
4274 obj
= i915_gem_object_alloc(dev_priv
);
4276 return ERR_PTR(-ENOMEM
);
4278 ret
= drm_gem_object_init(&dev_priv
->drm
, &obj
->base
, size
);
4282 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4283 if (IS_I965GM(dev_priv
) || IS_I965G(dev_priv
)) {
4284 /* 965gm cannot relocate objects above 4GiB. */
4285 mask
&= ~__GFP_HIGHMEM
;
4286 mask
|= __GFP_DMA32
;
4289 mapping
= obj
->base
.filp
->f_mapping
;
4290 mapping_set_gfp_mask(mapping
, mask
);
4291 GEM_BUG_ON(!(mapping_gfp_mask(mapping
) & __GFP_RECLAIM
));
4293 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4295 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4296 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4298 if (HAS_LLC(dev_priv
))
4299 /* On some devices, we can have the GPU use the LLC (the CPU
4300 * cache) for about a 10% performance improvement
4301 * compared to uncached. Graphics requests other than
4302 * display scanout are coherent with the CPU in
4303 * accessing this cache. This means in this mode we
4304 * don't need to clflush on the CPU side, and on the
4305 * GPU side we only need to flush internal caches to
4306 * get data visible to the CPU.
4308 * However, we maintain the display planes as UC, and so
4309 * need to rebind when first used as such.
4311 cache_level
= I915_CACHE_LLC
;
4313 cache_level
= I915_CACHE_NONE
;
4315 i915_gem_object_set_cache_coherency(obj
, cache_level
);
4317 trace_i915_gem_object_create(obj
);
4322 i915_gem_object_free(obj
);
4323 return ERR_PTR(ret
);
4326 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4328 /* If we are the last user of the backing storage (be it shmemfs
4329 * pages or stolen etc), we know that the pages are going to be
4330 * immediately released. In this case, we can then skip copying
4331 * back the contents from the GPU.
4334 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
)
4337 if (obj
->base
.filp
== NULL
)
4340 /* At first glance, this looks racy, but then again so would be
4341 * userspace racing mmap against close. However, the first external
4342 * reference to the filp can only be obtained through the
4343 * i915_gem_mmap_ioctl() which safeguards us against the user
4344 * acquiring such a reference whilst we are in the middle of
4345 * freeing the object.
4347 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4350 static void __i915_gem_free_objects(struct drm_i915_private
*i915
,
4351 struct llist_node
*freed
)
4353 struct drm_i915_gem_object
*obj
, *on
;
4355 mutex_lock(&i915
->drm
.struct_mutex
);
4356 intel_runtime_pm_get(i915
);
4357 llist_for_each_entry(obj
, freed
, freed
) {
4358 struct i915_vma
*vma
, *vn
;
4360 trace_i915_gem_object_destroy(obj
);
4362 GEM_BUG_ON(i915_gem_object_is_active(obj
));
4363 list_for_each_entry_safe(vma
, vn
,
4364 &obj
->vma_list
, obj_link
) {
4365 GEM_BUG_ON(i915_vma_is_active(vma
));
4366 vma
->flags
&= ~I915_VMA_PIN_MASK
;
4367 i915_vma_close(vma
);
4369 GEM_BUG_ON(!list_empty(&obj
->vma_list
));
4370 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj
->vma_tree
));
4372 list_del(&obj
->global_link
);
4374 intel_runtime_pm_put(i915
);
4375 mutex_unlock(&i915
->drm
.struct_mutex
);
4379 llist_for_each_entry_safe(obj
, on
, freed
, freed
) {
4380 GEM_BUG_ON(obj
->bind_count
);
4381 GEM_BUG_ON(atomic_read(&obj
->frontbuffer_bits
));
4382 GEM_BUG_ON(!list_empty(&obj
->lut_list
));
4384 if (obj
->ops
->release
)
4385 obj
->ops
->release(obj
);
4387 if (WARN_ON(i915_gem_object_has_pinned_pages(obj
)))
4388 atomic_set(&obj
->mm
.pages_pin_count
, 0);
4389 __i915_gem_object_put_pages(obj
, I915_MM_NORMAL
);
4390 GEM_BUG_ON(obj
->mm
.pages
);
4392 if (obj
->base
.import_attach
)
4393 drm_prime_gem_destroy(&obj
->base
, NULL
);
4395 reservation_object_fini(&obj
->__builtin_resv
);
4396 drm_gem_object_release(&obj
->base
);
4397 i915_gem_info_remove_obj(i915
, obj
->base
.size
);
4400 i915_gem_object_free(obj
);
4404 static void i915_gem_flush_free_objects(struct drm_i915_private
*i915
)
4406 struct llist_node
*freed
;
4408 freed
= llist_del_all(&i915
->mm
.free_list
);
4409 if (unlikely(freed
))
4410 __i915_gem_free_objects(i915
, freed
);
4413 static void __i915_gem_free_work(struct work_struct
*work
)
4415 struct drm_i915_private
*i915
=
4416 container_of(work
, struct drm_i915_private
, mm
.free_work
);
4417 struct llist_node
*freed
;
4419 /* All file-owned VMA should have been released by this point through
4420 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4421 * However, the object may also be bound into the global GTT (e.g.
4422 * older GPUs without per-process support, or for direct access through
4423 * the GTT either for the user or for scanout). Those VMA still need to
4427 while ((freed
= llist_del_all(&i915
->mm
.free_list
))) {
4428 __i915_gem_free_objects(i915
, freed
);
4434 static void __i915_gem_free_object_rcu(struct rcu_head
*head
)
4436 struct drm_i915_gem_object
*obj
=
4437 container_of(head
, typeof(*obj
), rcu
);
4438 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
4440 /* We can't simply use call_rcu() from i915_gem_free_object()
4441 * as we need to block whilst unbinding, and the call_rcu
4442 * task may be called from softirq context. So we take a
4443 * detour through a worker.
4445 if (llist_add(&obj
->freed
, &i915
->mm
.free_list
))
4446 schedule_work(&i915
->mm
.free_work
);
4449 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4451 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4453 if (obj
->mm
.quirked
)
4454 __i915_gem_object_unpin_pages(obj
);
4456 if (discard_backing_storage(obj
))
4457 obj
->mm
.madv
= I915_MADV_DONTNEED
;
4459 /* Before we free the object, make sure any pure RCU-only
4460 * read-side critical sections are complete, e.g.
4461 * i915_gem_busy_ioctl(). For the corresponding synchronized
4462 * lookup see i915_gem_object_lookup_rcu().
4464 call_rcu(&obj
->rcu
, __i915_gem_free_object_rcu
);
4467 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object
*obj
)
4469 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
4471 if (!i915_gem_object_has_active_reference(obj
) &&
4472 i915_gem_object_is_active(obj
))
4473 i915_gem_object_set_active_reference(obj
);
4475 i915_gem_object_put(obj
);
4478 static void assert_kernel_context_is_current(struct drm_i915_private
*dev_priv
)
4480 struct intel_engine_cs
*engine
;
4481 enum intel_engine_id id
;
4483 for_each_engine(engine
, dev_priv
, id
)
4484 GEM_BUG_ON(engine
->last_retired_context
&&
4485 !i915_gem_context_is_kernel(engine
->last_retired_context
));
4488 void i915_gem_sanitize(struct drm_i915_private
*i915
)
4490 if (i915_terminally_wedged(&i915
->gpu_error
)) {
4491 mutex_lock(&i915
->drm
.struct_mutex
);
4492 i915_gem_unset_wedged(i915
);
4493 mutex_unlock(&i915
->drm
.struct_mutex
);
4497 * If we inherit context state from the BIOS or earlier occupants
4498 * of the GPU, the GPU may be in an inconsistent state when we
4499 * try to take over. The only way to remove the earlier state
4500 * is by resetting. However, resetting on earlier gen is tricky as
4501 * it may impact the display and we are uncertain about the stability
4502 * of the reset, so this could be applied to even earlier gen.
4504 if (INTEL_GEN(i915
) >= 5) {
4505 int reset
= intel_gpu_reset(i915
, ALL_ENGINES
);
4506 WARN_ON(reset
&& reset
!= -ENODEV
);
4510 int i915_gem_suspend(struct drm_i915_private
*dev_priv
)
4512 struct drm_device
*dev
= &dev_priv
->drm
;
4515 intel_runtime_pm_get(dev_priv
);
4516 intel_suspend_gt_powersave(dev_priv
);
4518 mutex_lock(&dev
->struct_mutex
);
4520 /* We have to flush all the executing contexts to main memory so
4521 * that they can saved in the hibernation image. To ensure the last
4522 * context image is coherent, we have to switch away from it. That
4523 * leaves the dev_priv->kernel_context still active when
4524 * we actually suspend, and its image in memory may not match the GPU
4525 * state. Fortunately, the kernel_context is disposable and we do
4526 * not rely on its state.
4528 ret
= i915_gem_switch_to_kernel_context(dev_priv
);
4532 ret
= i915_gem_wait_for_idle(dev_priv
,
4533 I915_WAIT_INTERRUPTIBLE
|
4535 if (ret
&& ret
!= -EIO
)
4538 assert_kernel_context_is_current(dev_priv
);
4539 i915_gem_contexts_lost(dev_priv
);
4540 mutex_unlock(&dev
->struct_mutex
);
4542 intel_guc_suspend(dev_priv
);
4544 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4545 cancel_delayed_work_sync(&dev_priv
->gt
.retire_work
);
4547 /* As the idle_work is rearming if it detects a race, play safe and
4548 * repeat the flush until it is definitely idle.
4550 while (flush_delayed_work(&dev_priv
->gt
.idle_work
))
4553 /* Assert that we sucessfully flushed all the work and
4554 * reset the GPU back to its idle, low power state.
4556 WARN_ON(dev_priv
->gt
.awake
);
4557 if (WARN_ON(!intel_engines_are_idle(dev_priv
)))
4558 i915_gem_set_wedged(dev_priv
); /* no hope, discard everything */
4561 * Neither the BIOS, ourselves or any other kernel
4562 * expects the system to be in execlists mode on startup,
4563 * so we need to reset the GPU back to legacy mode. And the only
4564 * known way to disable logical contexts is through a GPU reset.
4566 * So in order to leave the system in a known default configuration,
4567 * always reset the GPU upon unload and suspend. Afterwards we then
4568 * clean up the GEM state tracking, flushing off the requests and
4569 * leaving the system in a known idle state.
4571 * Note that is of the upmost importance that the GPU is idle and
4572 * all stray writes are flushed *before* we dismantle the backing
4573 * storage for the pinned objects.
4575 * However, since we are uncertain that resetting the GPU on older
4576 * machines is a good idea, we don't - just in case it leaves the
4577 * machine in an unusable condition.
4579 i915_gem_sanitize(dev_priv
);
4581 intel_runtime_pm_put(dev_priv
);
4585 mutex_unlock(&dev
->struct_mutex
);
4586 intel_runtime_pm_put(dev_priv
);
4590 void i915_gem_resume(struct drm_i915_private
*dev_priv
)
4592 struct drm_device
*dev
= &dev_priv
->drm
;
4594 WARN_ON(dev_priv
->gt
.awake
);
4596 mutex_lock(&dev
->struct_mutex
);
4597 i915_gem_restore_gtt_mappings(dev_priv
);
4599 /* As we didn't flush the kernel context before suspend, we cannot
4600 * guarantee that the context image is complete. So let's just reset
4601 * it and start again.
4603 dev_priv
->gt
.resume(dev_priv
);
4605 mutex_unlock(&dev
->struct_mutex
);
4608 void i915_gem_init_swizzling(struct drm_i915_private
*dev_priv
)
4610 if (INTEL_GEN(dev_priv
) < 5 ||
4611 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4614 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4615 DISP_TILE_SURFACE_SWIZZLING
);
4617 if (IS_GEN5(dev_priv
))
4620 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4621 if (IS_GEN6(dev_priv
))
4622 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4623 else if (IS_GEN7(dev_priv
))
4624 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4625 else if (IS_GEN8(dev_priv
))
4626 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4631 static void init_unused_ring(struct drm_i915_private
*dev_priv
, u32 base
)
4633 I915_WRITE(RING_CTL(base
), 0);
4634 I915_WRITE(RING_HEAD(base
), 0);
4635 I915_WRITE(RING_TAIL(base
), 0);
4636 I915_WRITE(RING_START(base
), 0);
4639 static void init_unused_rings(struct drm_i915_private
*dev_priv
)
4641 if (IS_I830(dev_priv
)) {
4642 init_unused_ring(dev_priv
, PRB1_BASE
);
4643 init_unused_ring(dev_priv
, SRB0_BASE
);
4644 init_unused_ring(dev_priv
, SRB1_BASE
);
4645 init_unused_ring(dev_priv
, SRB2_BASE
);
4646 init_unused_ring(dev_priv
, SRB3_BASE
);
4647 } else if (IS_GEN2(dev_priv
)) {
4648 init_unused_ring(dev_priv
, SRB0_BASE
);
4649 init_unused_ring(dev_priv
, SRB1_BASE
);
4650 } else if (IS_GEN3(dev_priv
)) {
4651 init_unused_ring(dev_priv
, PRB1_BASE
);
4652 init_unused_ring(dev_priv
, PRB2_BASE
);
4656 static int __i915_gem_restart_engines(void *data
)
4658 struct drm_i915_private
*i915
= data
;
4659 struct intel_engine_cs
*engine
;
4660 enum intel_engine_id id
;
4663 for_each_engine(engine
, i915
, id
) {
4664 err
= engine
->init_hw(engine
);
4672 int i915_gem_init_hw(struct drm_i915_private
*dev_priv
)
4676 dev_priv
->gt
.last_init_time
= ktime_get();
4678 /* Double layer security blanket, see i915_gem_init() */
4679 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4681 if (HAS_EDRAM(dev_priv
) && INTEL_GEN(dev_priv
) < 9)
4682 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4684 if (IS_HASWELL(dev_priv
))
4685 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev_priv
) ?
4686 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4688 if (HAS_PCH_NOP(dev_priv
)) {
4689 if (IS_IVYBRIDGE(dev_priv
)) {
4690 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4691 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4692 I915_WRITE(GEN7_MSG_CTL
, temp
);
4693 } else if (INTEL_GEN(dev_priv
) >= 7) {
4694 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4695 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4696 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4700 i915_gem_init_swizzling(dev_priv
);
4703 * At least 830 can leave some of the unused rings
4704 * "active" (ie. head != tail) after resume which
4705 * will prevent c3 entry. Makes sure all unused rings
4708 init_unused_rings(dev_priv
);
4710 BUG_ON(!dev_priv
->kernel_context
);
4712 ret
= i915_ppgtt_init_hw(dev_priv
);
4714 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4718 /* Need to do basic initialisation of all rings first: */
4719 ret
= __i915_gem_restart_engines(dev_priv
);
4723 intel_mocs_init_l3cc_table(dev_priv
);
4725 /* We can't enable contexts until all firmware is loaded */
4726 ret
= intel_uc_init_hw(dev_priv
);
4731 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4735 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
)
4737 if (INTEL_INFO(dev_priv
)->gen
< 6)
4740 /* TODO: make semaphores and Execlists play nicely together */
4741 if (i915_modparams
.enable_execlists
)
4747 /* Enable semaphores on SNB when IO remapping is off */
4748 if (IS_GEN6(dev_priv
) && intel_vtd_active())
4754 int i915_gem_init(struct drm_i915_private
*dev_priv
)
4758 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4760 dev_priv
->mm
.unordered_timeline
= dma_fence_context_alloc(1);
4762 if (!i915_modparams
.enable_execlists
) {
4763 dev_priv
->gt
.resume
= intel_legacy_submission_resume
;
4764 dev_priv
->gt
.cleanup_engine
= intel_engine_cleanup
;
4766 dev_priv
->gt
.resume
= intel_lr_context_resume
;
4767 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4770 /* This is just a security blanket to placate dragons.
4771 * On some systems, we very sporadically observe that the first TLBs
4772 * used by the CS may be stale, despite us poking the TLB reset. If
4773 * we hold the forcewake during initialisation these problems
4774 * just magically go away.
4776 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4778 ret
= i915_gem_init_userptr(dev_priv
);
4782 ret
= i915_gem_init_ggtt(dev_priv
);
4786 ret
= i915_gem_contexts_init(dev_priv
);
4790 ret
= intel_engines_init(dev_priv
);
4794 ret
= i915_gem_init_hw(dev_priv
);
4796 /* Allow engine initialisation to fail by marking the GPU as
4797 * wedged. But we only want to do this where the GPU is angry,
4798 * for all other failure, such as an allocation failure, bail.
4800 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4801 i915_gem_set_wedged(dev_priv
);
4806 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4807 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4812 void i915_gem_init_mmio(struct drm_i915_private
*i915
)
4814 i915_gem_sanitize(i915
);
4818 i915_gem_cleanup_engines(struct drm_i915_private
*dev_priv
)
4820 struct intel_engine_cs
*engine
;
4821 enum intel_engine_id id
;
4823 for_each_engine(engine
, dev_priv
, id
)
4824 dev_priv
->gt
.cleanup_engine(engine
);
4828 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
4832 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
4833 !IS_CHERRYVIEW(dev_priv
))
4834 dev_priv
->num_fence_regs
= 32;
4835 else if (INTEL_INFO(dev_priv
)->gen
>= 4 ||
4836 IS_I945G(dev_priv
) || IS_I945GM(dev_priv
) ||
4837 IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
))
4838 dev_priv
->num_fence_regs
= 16;
4840 dev_priv
->num_fence_regs
= 8;
4842 if (intel_vgpu_active(dev_priv
))
4843 dev_priv
->num_fence_regs
=
4844 I915_READ(vgtif_reg(avail_rs
.fence_num
));
4846 /* Initialize fence registers to zero */
4847 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
4848 struct drm_i915_fence_reg
*fence
= &dev_priv
->fence_regs
[i
];
4850 fence
->i915
= dev_priv
;
4852 list_add_tail(&fence
->link
, &dev_priv
->mm
.fence_list
);
4854 i915_gem_restore_fences(dev_priv
);
4856 i915_gem_detect_bit_6_swizzle(dev_priv
);
4860 i915_gem_load_init(struct drm_i915_private
*dev_priv
)
4864 dev_priv
->objects
= KMEM_CACHE(drm_i915_gem_object
, SLAB_HWCACHE_ALIGN
);
4865 if (!dev_priv
->objects
)
4868 dev_priv
->vmas
= KMEM_CACHE(i915_vma
, SLAB_HWCACHE_ALIGN
);
4869 if (!dev_priv
->vmas
)
4872 dev_priv
->luts
= KMEM_CACHE(i915_lut_handle
, 0);
4873 if (!dev_priv
->luts
)
4876 dev_priv
->requests
= KMEM_CACHE(drm_i915_gem_request
,
4877 SLAB_HWCACHE_ALIGN
|
4878 SLAB_RECLAIM_ACCOUNT
|
4879 SLAB_TYPESAFE_BY_RCU
);
4880 if (!dev_priv
->requests
)
4883 dev_priv
->dependencies
= KMEM_CACHE(i915_dependency
,
4884 SLAB_HWCACHE_ALIGN
|
4885 SLAB_RECLAIM_ACCOUNT
);
4886 if (!dev_priv
->dependencies
)
4889 dev_priv
->priorities
= KMEM_CACHE(i915_priolist
, SLAB_HWCACHE_ALIGN
);
4890 if (!dev_priv
->priorities
)
4891 goto err_dependencies
;
4893 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4894 INIT_LIST_HEAD(&dev_priv
->gt
.timelines
);
4895 err
= i915_gem_timeline_init__global(dev_priv
);
4896 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4898 goto err_priorities
;
4900 INIT_WORK(&dev_priv
->mm
.free_work
, __i915_gem_free_work
);
4901 init_llist_head(&dev_priv
->mm
.free_list
);
4902 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4903 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4904 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4905 INIT_LIST_HEAD(&dev_priv
->mm
.userfault_list
);
4906 INIT_DELAYED_WORK(&dev_priv
->gt
.retire_work
,
4907 i915_gem_retire_work_handler
);
4908 INIT_DELAYED_WORK(&dev_priv
->gt
.idle_work
,
4909 i915_gem_idle_work_handler
);
4910 init_waitqueue_head(&dev_priv
->gpu_error
.wait_queue
);
4911 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4913 atomic_set(&dev_priv
->mm
.bsd_engine_dispatch_index
, 0);
4915 spin_lock_init(&dev_priv
->fb_tracking
.lock
);
4920 kmem_cache_destroy(dev_priv
->priorities
);
4922 kmem_cache_destroy(dev_priv
->dependencies
);
4924 kmem_cache_destroy(dev_priv
->requests
);
4926 kmem_cache_destroy(dev_priv
->luts
);
4928 kmem_cache_destroy(dev_priv
->vmas
);
4930 kmem_cache_destroy(dev_priv
->objects
);
4935 void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv
)
4937 i915_gem_drain_freed_objects(dev_priv
);
4938 WARN_ON(!llist_empty(&dev_priv
->mm
.free_list
));
4939 WARN_ON(dev_priv
->mm
.object_count
);
4941 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4942 i915_gem_timeline_fini(&dev_priv
->gt
.global_timeline
);
4943 WARN_ON(!list_empty(&dev_priv
->gt
.timelines
));
4944 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
4946 kmem_cache_destroy(dev_priv
->priorities
);
4947 kmem_cache_destroy(dev_priv
->dependencies
);
4948 kmem_cache_destroy(dev_priv
->requests
);
4949 kmem_cache_destroy(dev_priv
->luts
);
4950 kmem_cache_destroy(dev_priv
->vmas
);
4951 kmem_cache_destroy(dev_priv
->objects
);
4953 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4957 int i915_gem_freeze(struct drm_i915_private
*dev_priv
)
4959 /* Discard all purgeable objects, let userspace recover those as
4960 * required after resuming.
4962 i915_gem_shrink_all(dev_priv
);
4967 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
4969 struct drm_i915_gem_object
*obj
;
4970 struct list_head
*phases
[] = {
4971 &dev_priv
->mm
.unbound_list
,
4972 &dev_priv
->mm
.bound_list
,
4976 /* Called just before we write the hibernation image.
4978 * We need to update the domain tracking to reflect that the CPU
4979 * will be accessing all the pages to create and restore from the
4980 * hibernation, and so upon restoration those pages will be in the
4983 * To make sure the hibernation image contains the latest state,
4984 * we update that state just before writing out the image.
4986 * To try and reduce the hibernation image, we manually shrink
4987 * the objects as well, see i915_gem_freeze()
4990 i915_gem_shrink(dev_priv
, -1UL, NULL
, I915_SHRINK_UNBOUND
);
4991 i915_gem_drain_freed_objects(dev_priv
);
4993 mutex_lock(&dev_priv
->drm
.struct_mutex
);
4994 for (p
= phases
; *p
; p
++) {
4995 list_for_each_entry(obj
, *p
, global_link
)
4996 __start_cpu_write(obj
);
4998 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
5003 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5005 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5006 struct drm_i915_gem_request
*request
;
5008 /* Clean up our request list when the client is going away, so that
5009 * later retire_requests won't dereference our soon-to-be-gone
5012 spin_lock(&file_priv
->mm
.lock
);
5013 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_link
)
5014 request
->file_priv
= NULL
;
5015 spin_unlock(&file_priv
->mm
.lock
);
5018 int i915_gem_open(struct drm_i915_private
*i915
, struct drm_file
*file
)
5020 struct drm_i915_file_private
*file_priv
;
5025 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5029 file
->driver_priv
= file_priv
;
5030 file_priv
->dev_priv
= i915
;
5031 file_priv
->file
= file
;
5033 spin_lock_init(&file_priv
->mm
.lock
);
5034 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5036 file_priv
->bsd_engine
= -1;
5038 ret
= i915_gem_context_open(i915
, file
);
5046 * i915_gem_track_fb - update frontbuffer tracking
5047 * @old: current GEM buffer for the frontbuffer slots
5048 * @new: new GEM buffer for the frontbuffer slots
5049 * @frontbuffer_bits: bitmask of frontbuffer slots
5051 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5052 * from @old and setting them in @new. Both @old and @new can be NULL.
5054 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5055 struct drm_i915_gem_object
*new,
5056 unsigned frontbuffer_bits
)
5058 /* Control of individual bits within the mask are guarded by
5059 * the owning plane->mutex, i.e. we can never see concurrent
5060 * manipulation of individual bits. But since the bitfield as a whole
5061 * is updated using RMW, we need to use atomics in order to update
5064 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE
* I915_MAX_PIPES
>
5065 sizeof(atomic_t
) * BITS_PER_BYTE
);
5068 WARN_ON(!(atomic_read(&old
->frontbuffer_bits
) & frontbuffer_bits
));
5069 atomic_andnot(frontbuffer_bits
, &old
->frontbuffer_bits
);
5073 WARN_ON(atomic_read(&new->frontbuffer_bits
) & frontbuffer_bits
);
5074 atomic_or(frontbuffer_bits
, &new->frontbuffer_bits
);
5078 /* Allocate a new GEM object and fill it with the supplied data */
5079 struct drm_i915_gem_object
*
5080 i915_gem_object_create_from_data(struct drm_i915_private
*dev_priv
,
5081 const void *data
, size_t size
)
5083 struct drm_i915_gem_object
*obj
;
5088 obj
= i915_gem_object_create(dev_priv
, round_up(size
, PAGE_SIZE
));
5092 GEM_BUG_ON(obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
);
5094 file
= obj
->base
.filp
;
5097 unsigned int len
= min_t(typeof(size
), size
, PAGE_SIZE
);
5099 void *pgdata
, *vaddr
;
5101 err
= pagecache_write_begin(file
, file
->f_mapping
,
5108 memcpy(vaddr
, data
, len
);
5111 err
= pagecache_write_end(file
, file
->f_mapping
,
5125 i915_gem_object_put(obj
);
5126 return ERR_PTR(err
);
5129 struct scatterlist
*
5130 i915_gem_object_get_sg(struct drm_i915_gem_object
*obj
,
5132 unsigned int *offset
)
5134 struct i915_gem_object_page_iter
*iter
= &obj
->mm
.get_page
;
5135 struct scatterlist
*sg
;
5136 unsigned int idx
, count
;
5139 GEM_BUG_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
);
5140 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj
));
5142 /* As we iterate forward through the sg, we record each entry in a
5143 * radixtree for quick repeated (backwards) lookups. If we have seen
5144 * this index previously, we will have an entry for it.
5146 * Initial lookup is O(N), but this is amortized to O(1) for
5147 * sequential page access (where each new request is consecutive
5148 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
5149 * i.e. O(1) with a large constant!
5151 if (n
< READ_ONCE(iter
->sg_idx
))
5154 mutex_lock(&iter
->lock
);
5156 /* We prefer to reuse the last sg so that repeated lookup of this
5157 * (or the subsequent) sg are fast - comparing against the last
5158 * sg is faster than going through the radixtree.
5163 count
= __sg_page_count(sg
);
5165 while (idx
+ count
<= n
) {
5166 unsigned long exception
, i
;
5169 /* If we cannot allocate and insert this entry, or the
5170 * individual pages from this range, cancel updating the
5171 * sg_idx so that on this lookup we are forced to linearly
5172 * scan onwards, but on future lookups we will try the
5173 * insertion again (in which case we need to be careful of
5174 * the error return reporting that we have already inserted
5177 ret
= radix_tree_insert(&iter
->radix
, idx
, sg
);
5178 if (ret
&& ret
!= -EEXIST
)
5182 RADIX_TREE_EXCEPTIONAL_ENTRY
|
5183 idx
<< RADIX_TREE_EXCEPTIONAL_SHIFT
;
5184 for (i
= 1; i
< count
; i
++) {
5185 ret
= radix_tree_insert(&iter
->radix
, idx
+ i
,
5187 if (ret
&& ret
!= -EEXIST
)
5192 sg
= ____sg_next(sg
);
5193 count
= __sg_page_count(sg
);
5200 mutex_unlock(&iter
->lock
);
5202 if (unlikely(n
< idx
)) /* insertion completed by another thread */
5205 /* In case we failed to insert the entry into the radixtree, we need
5206 * to look beyond the current sg.
5208 while (idx
+ count
<= n
) {
5210 sg
= ____sg_next(sg
);
5211 count
= __sg_page_count(sg
);
5220 sg
= radix_tree_lookup(&iter
->radix
, n
);
5223 /* If this index is in the middle of multi-page sg entry,
5224 * the radixtree will contain an exceptional entry that points
5225 * to the start of that range. We will return the pointer to
5226 * the base page and the offset of this page within the
5230 if (unlikely(radix_tree_exception(sg
))) {
5231 unsigned long base
=
5232 (unsigned long)sg
>> RADIX_TREE_EXCEPTIONAL_SHIFT
;
5234 sg
= radix_tree_lookup(&iter
->radix
, base
);
5246 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, unsigned int n
)
5248 struct scatterlist
*sg
;
5249 unsigned int offset
;
5251 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj
));
5253 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
5254 return nth_page(sg_page(sg
), offset
);
5257 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5259 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
,
5264 page
= i915_gem_object_get_page(obj
, n
);
5266 set_page_dirty(page
);
5272 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
,
5275 struct scatterlist
*sg
;
5276 unsigned int offset
;
5278 sg
= i915_gem_object_get_sg(obj
, n
, &offset
);
5279 return sg_dma_address(sg
) + (offset
<< PAGE_SHIFT
);
5282 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
, int align
)
5284 struct sg_table
*pages
;
5287 if (align
> obj
->base
.size
)
5290 if (obj
->ops
== &i915_gem_phys_ops
)
5293 if (obj
->ops
!= &i915_gem_object_ops
)
5296 err
= i915_gem_object_unbind(obj
);
5300 mutex_lock(&obj
->mm
.lock
);
5302 if (obj
->mm
.madv
!= I915_MADV_WILLNEED
) {
5307 if (obj
->mm
.quirked
) {
5312 if (obj
->mm
.mapping
) {
5317 pages
= obj
->mm
.pages
;
5318 obj
->ops
= &i915_gem_phys_ops
;
5320 err
= ____i915_gem_object_get_pages(obj
);
5324 /* Perma-pin (until release) the physical set of pages */
5325 __i915_gem_object_pin_pages(obj
);
5327 if (!IS_ERR_OR_NULL(pages
))
5328 i915_gem_object_ops
.put_pages(obj
, pages
);
5329 mutex_unlock(&obj
->mm
.lock
);
5333 obj
->ops
= &i915_gem_object_ops
;
5334 obj
->mm
.pages
= pages
;
5336 mutex_unlock(&obj
->mm
.lock
);
5340 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5341 #include "selftests/scatterlist.c"
5342 #include "selftests/mock_gem_device.c"
5343 #include "selftests/huge_gem_object.c"
5344 #include "selftests/i915_gem_object.c"
5345 #include "selftests/i915_gem_coherency.c"