2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
44 static __must_check
int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
48 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static unsigned long i915_gem_shrinker_count(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker
*shrinker
,
59 struct shrink_control
*sc
);
60 static int i915_gem_shrinker_oom(struct notifier_block
*nb
,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
65 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
66 enum i915_cache_level level
)
68 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
73 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
76 return obj
->pin_display
;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
82 i915_gem_release_mmap(obj
);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj
->fence_dirty
= false;
88 obj
->fence_reg
= I915_FENCE_REG_NONE
;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
95 spin_lock(&dev_priv
->mm
.object_stat_lock
);
96 dev_priv
->mm
.object_count
++;
97 dev_priv
->mm
.object_memory
+= size
;
98 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
104 spin_lock(&dev_priv
->mm
.object_stat_lock
);
105 dev_priv
->mm
.object_count
--;
106 dev_priv
->mm
.object_memory
-= size
;
107 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
111 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret
< 0) {
139 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
148 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
152 WARN_ON(i915_verify_lists(dev
));
157 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
158 struct drm_file
*file
)
160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
161 struct drm_i915_gem_get_aperture
*args
= data
;
162 struct drm_i915_gem_object
*obj
;
166 mutex_lock(&dev
->struct_mutex
);
167 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
168 if (i915_gem_obj_is_pinned(obj
))
169 pinned
+= i915_gem_obj_ggtt_size(obj
);
170 mutex_unlock(&dev
->struct_mutex
);
172 args
->aper_size
= dev_priv
->gtt
.base
.total
;
173 args
->aper_available_size
= args
->aper_size
- pinned
;
179 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
181 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
182 char *vaddr
= obj
->phys_handle
->vaddr
;
184 struct scatterlist
*sg
;
187 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
190 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
194 page
= shmem_read_mapping_page(mapping
, i
);
196 return PTR_ERR(page
);
198 src
= kmap_atomic(page
);
199 memcpy(vaddr
, src
, PAGE_SIZE
);
200 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
203 page_cache_release(page
);
207 i915_gem_chipset_flush(obj
->base
.dev
);
209 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
213 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
220 sg
->length
= obj
->base
.size
;
222 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
223 sg_dma_len(sg
) = obj
->base
.size
;
226 obj
->has_dma_mapping
= true;
231 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
235 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
237 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
239 /* In the event of a disaster, abandon all caches and
242 WARN_ON(ret
!= -EIO
);
243 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
246 if (obj
->madv
== I915_MADV_DONTNEED
)
250 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
251 char *vaddr
= obj
->phys_handle
->vaddr
;
254 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
258 page
= shmem_read_mapping_page(mapping
, i
);
262 dst
= kmap_atomic(page
);
263 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
264 memcpy(dst
, vaddr
, PAGE_SIZE
);
267 set_page_dirty(page
);
268 if (obj
->madv
== I915_MADV_WILLNEED
)
269 mark_page_accessed(page
);
270 page_cache_release(page
);
276 sg_free_table(obj
->pages
);
279 obj
->has_dma_mapping
= false;
283 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
285 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
288 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
289 .get_pages
= i915_gem_object_get_pages_phys
,
290 .put_pages
= i915_gem_object_put_pages_phys
,
291 .release
= i915_gem_object_release_phys
,
295 drop_pages(struct drm_i915_gem_object
*obj
)
297 struct i915_vma
*vma
, *next
;
300 drm_gem_object_reference(&obj
->base
);
301 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
302 if (i915_vma_unbind(vma
))
305 ret
= i915_gem_object_put_pages(obj
);
306 drm_gem_object_unreference(&obj
->base
);
312 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
315 drm_dma_handle_t
*phys
;
318 if (obj
->phys_handle
) {
319 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
325 if (obj
->madv
!= I915_MADV_WILLNEED
)
328 if (obj
->base
.filp
== NULL
)
331 ret
= drop_pages(obj
);
335 /* create a new object */
336 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
340 obj
->phys_handle
= phys
;
341 obj
->ops
= &i915_gem_phys_ops
;
343 return i915_gem_object_get_pages(obj
);
347 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
348 struct drm_i915_gem_pwrite
*args
,
349 struct drm_file
*file_priv
)
351 struct drm_device
*dev
= obj
->base
.dev
;
352 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
353 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
356 /* We manually control the domain here and pretend that it
357 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
359 ret
= i915_gem_object_wait_rendering(obj
, false);
363 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
364 unsigned long unwritten
;
366 /* The physical object once assigned is fixed for the lifetime
367 * of the obj, so we can safely drop the lock and continue
370 mutex_unlock(&dev
->struct_mutex
);
371 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
372 mutex_lock(&dev
->struct_mutex
);
377 drm_clflush_virt_range(vaddr
, args
->size
);
378 i915_gem_chipset_flush(dev
);
382 void *i915_gem_object_alloc(struct drm_device
*dev
)
384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
385 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
388 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
390 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
391 kmem_cache_free(dev_priv
->slab
, obj
);
395 i915_gem_create(struct drm_file
*file
,
396 struct drm_device
*dev
,
400 struct drm_i915_gem_object
*obj
;
404 size
= roundup(size
, PAGE_SIZE
);
408 /* Allocate the new object */
409 obj
= i915_gem_alloc_object(dev
, size
);
413 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
414 /* drop reference from allocate - handle holds it now */
415 drm_gem_object_unreference_unlocked(&obj
->base
);
424 i915_gem_dumb_create(struct drm_file
*file
,
425 struct drm_device
*dev
,
426 struct drm_mode_create_dumb
*args
)
428 /* have to work out size/pitch and return them */
429 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
430 args
->size
= args
->pitch
* args
->height
;
431 return i915_gem_create(file
, dev
,
432 args
->size
, &args
->handle
);
436 * Creates a new mm object and returns a handle to it.
439 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
440 struct drm_file
*file
)
442 struct drm_i915_gem_create
*args
= data
;
444 return i915_gem_create(file
, dev
,
445 args
->size
, &args
->handle
);
449 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
450 const char *gpu_vaddr
, int gpu_offset
,
453 int ret
, cpu_offset
= 0;
456 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
457 int this_length
= min(cacheline_end
- gpu_offset
, length
);
458 int swizzled_gpu_offset
= gpu_offset
^ 64;
460 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
461 gpu_vaddr
+ swizzled_gpu_offset
,
466 cpu_offset
+= this_length
;
467 gpu_offset
+= this_length
;
468 length
-= this_length
;
475 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
476 const char __user
*cpu_vaddr
,
479 int ret
, cpu_offset
= 0;
482 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
483 int this_length
= min(cacheline_end
- gpu_offset
, length
);
484 int swizzled_gpu_offset
= gpu_offset
^ 64;
486 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
487 cpu_vaddr
+ cpu_offset
,
492 cpu_offset
+= this_length
;
493 gpu_offset
+= this_length
;
494 length
-= this_length
;
501 * Pins the specified object's pages and synchronizes the object with
502 * GPU accesses. Sets needs_clflush to non-zero if the caller should
503 * flush the object from the CPU cache.
505 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
515 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
516 /* If we're not in the cpu read domain, set ourself into the gtt
517 * read domain and manually flush cachelines (if required). This
518 * optimizes for the case when the gpu will dirty the data
519 * anyway again before the next pread happens. */
520 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
522 ret
= i915_gem_object_wait_rendering(obj
, true);
526 i915_gem_object_retire(obj
);
529 ret
= i915_gem_object_get_pages(obj
);
533 i915_gem_object_pin_pages(obj
);
538 /* Per-page copy function for the shmem pread fastpath.
539 * Flushes invalid cachelines before reading the target if
540 * needs_clflush is set. */
542 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
543 char __user
*user_data
,
544 bool page_do_bit17_swizzling
, bool needs_clflush
)
549 if (unlikely(page_do_bit17_swizzling
))
552 vaddr
= kmap_atomic(page
);
554 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
556 ret
= __copy_to_user_inatomic(user_data
,
557 vaddr
+ shmem_page_offset
,
559 kunmap_atomic(vaddr
);
561 return ret
? -EFAULT
: 0;
565 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
568 if (unlikely(swizzled
)) {
569 unsigned long start
= (unsigned long) addr
;
570 unsigned long end
= (unsigned long) addr
+ length
;
572 /* For swizzling simply ensure that we always flush both
573 * channels. Lame, but simple and it works. Swizzled
574 * pwrite/pread is far from a hotpath - current userspace
575 * doesn't use it at all. */
576 start
= round_down(start
, 128);
577 end
= round_up(end
, 128);
579 drm_clflush_virt_range((void *)start
, end
- start
);
581 drm_clflush_virt_range(addr
, length
);
586 /* Only difference to the fast-path function is that this can handle bit17
587 * and uses non-atomic copy and kmap functions. */
589 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
590 char __user
*user_data
,
591 bool page_do_bit17_swizzling
, bool needs_clflush
)
598 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
600 page_do_bit17_swizzling
);
602 if (page_do_bit17_swizzling
)
603 ret
= __copy_to_user_swizzled(user_data
,
604 vaddr
, shmem_page_offset
,
607 ret
= __copy_to_user(user_data
,
608 vaddr
+ shmem_page_offset
,
612 return ret
? - EFAULT
: 0;
616 i915_gem_shmem_pread(struct drm_device
*dev
,
617 struct drm_i915_gem_object
*obj
,
618 struct drm_i915_gem_pread
*args
,
619 struct drm_file
*file
)
621 char __user
*user_data
;
624 int shmem_page_offset
, page_length
, ret
= 0;
625 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
627 int needs_clflush
= 0;
628 struct sg_page_iter sg_iter
;
630 user_data
= to_user_ptr(args
->data_ptr
);
633 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
635 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
639 offset
= args
->offset
;
641 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
642 offset
>> PAGE_SHIFT
) {
643 struct page
*page
= sg_page_iter_page(&sg_iter
);
648 /* Operation in this page
650 * shmem_page_offset = offset within page in shmem file
651 * page_length = bytes to copy for this page
653 shmem_page_offset
= offset_in_page(offset
);
654 page_length
= remain
;
655 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
656 page_length
= PAGE_SIZE
- shmem_page_offset
;
658 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
659 (page_to_phys(page
) & (1 << 17)) != 0;
661 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
662 user_data
, page_do_bit17_swizzling
,
667 mutex_unlock(&dev
->struct_mutex
);
669 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
670 ret
= fault_in_multipages_writeable(user_data
, remain
);
671 /* Userspace is tricking us, but we've already clobbered
672 * its pages with the prefault and promised to write the
673 * data up to the first fault. Hence ignore any errors
674 * and just continue. */
679 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
680 user_data
, page_do_bit17_swizzling
,
683 mutex_lock(&dev
->struct_mutex
);
689 remain
-= page_length
;
690 user_data
+= page_length
;
691 offset
+= page_length
;
695 i915_gem_object_unpin_pages(obj
);
701 * Reads data from the object referenced by handle.
703 * On error, the contents of *data are undefined.
706 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
707 struct drm_file
*file
)
709 struct drm_i915_gem_pread
*args
= data
;
710 struct drm_i915_gem_object
*obj
;
716 if (!access_ok(VERIFY_WRITE
,
717 to_user_ptr(args
->data_ptr
),
721 ret
= i915_mutex_lock_interruptible(dev
);
725 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
726 if (&obj
->base
== NULL
) {
731 /* Bounds check source. */
732 if (args
->offset
> obj
->base
.size
||
733 args
->size
> obj
->base
.size
- args
->offset
) {
738 /* prime objects have no backing filp to GEM pread/pwrite
741 if (!obj
->base
.filp
) {
746 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
748 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
751 drm_gem_object_unreference(&obj
->base
);
753 mutex_unlock(&dev
->struct_mutex
);
757 /* This is the fast write path which cannot handle
758 * page faults in the source data
762 fast_user_write(struct io_mapping
*mapping
,
763 loff_t page_base
, int page_offset
,
764 char __user
*user_data
,
767 void __iomem
*vaddr_atomic
;
769 unsigned long unwritten
;
771 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
772 /* We can use the cpu mem copy function because this is X86. */
773 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
774 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
776 io_mapping_unmap_atomic(vaddr_atomic
);
781 * This is the fast pwrite path, where we copy the data directly from the
782 * user into the GTT, uncached.
785 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
786 struct drm_i915_gem_object
*obj
,
787 struct drm_i915_gem_pwrite
*args
,
788 struct drm_file
*file
)
790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
792 loff_t offset
, page_base
;
793 char __user
*user_data
;
794 int page_offset
, page_length
, ret
;
796 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
800 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
804 ret
= i915_gem_object_put_fence(obj
);
808 user_data
= to_user_ptr(args
->data_ptr
);
811 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
814 /* Operation in this page
816 * page_base = page offset within aperture
817 * page_offset = offset within page
818 * page_length = bytes to copy for this page
820 page_base
= offset
& PAGE_MASK
;
821 page_offset
= offset_in_page(offset
);
822 page_length
= remain
;
823 if ((page_offset
+ remain
) > PAGE_SIZE
)
824 page_length
= PAGE_SIZE
- page_offset
;
826 /* If we get a fault while copying data, then (presumably) our
827 * source page isn't available. Return the error and we'll
828 * retry in the slow path.
830 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
831 page_offset
, user_data
, page_length
)) {
836 remain
-= page_length
;
837 user_data
+= page_length
;
838 offset
+= page_length
;
842 i915_gem_object_ggtt_unpin(obj
);
847 /* Per-page copy function for the shmem pwrite fastpath.
848 * Flushes invalid cachelines before writing to the target if
849 * needs_clflush_before is set and flushes out any written cachelines after
850 * writing if needs_clflush is set. */
852 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
853 char __user
*user_data
,
854 bool page_do_bit17_swizzling
,
855 bool needs_clflush_before
,
856 bool needs_clflush_after
)
861 if (unlikely(page_do_bit17_swizzling
))
864 vaddr
= kmap_atomic(page
);
865 if (needs_clflush_before
)
866 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
868 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
869 user_data
, page_length
);
870 if (needs_clflush_after
)
871 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
873 kunmap_atomic(vaddr
);
875 return ret
? -EFAULT
: 0;
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
882 char __user
*user_data
,
883 bool page_do_bit17_swizzling
,
884 bool needs_clflush_before
,
885 bool needs_clflush_after
)
891 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
892 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
894 page_do_bit17_swizzling
);
895 if (page_do_bit17_swizzling
)
896 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
900 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
903 if (needs_clflush_after
)
904 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
906 page_do_bit17_swizzling
);
909 return ret
? -EFAULT
: 0;
913 i915_gem_shmem_pwrite(struct drm_device
*dev
,
914 struct drm_i915_gem_object
*obj
,
915 struct drm_i915_gem_pwrite
*args
,
916 struct drm_file
*file
)
920 char __user
*user_data
;
921 int shmem_page_offset
, page_length
, ret
= 0;
922 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
923 int hit_slowpath
= 0;
924 int needs_clflush_after
= 0;
925 int needs_clflush_before
= 0;
926 struct sg_page_iter sg_iter
;
928 user_data
= to_user_ptr(args
->data_ptr
);
931 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
933 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
934 /* If we're not in the cpu write domain, set ourself into the gtt
935 * write domain and manually flush cachelines (if required). This
936 * optimizes for the case when the gpu will use the data
937 * right away and we therefore have to clflush anyway. */
938 needs_clflush_after
= cpu_write_needs_clflush(obj
);
939 ret
= i915_gem_object_wait_rendering(obj
, false);
943 i915_gem_object_retire(obj
);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
948 needs_clflush_before
=
949 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
951 ret
= i915_gem_object_get_pages(obj
);
955 i915_gem_object_pin_pages(obj
);
957 offset
= args
->offset
;
960 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
961 offset
>> PAGE_SHIFT
) {
962 struct page
*page
= sg_page_iter_page(&sg_iter
);
963 int partial_cacheline_write
;
968 /* Operation in this page
970 * shmem_page_offset = offset within page in shmem file
971 * page_length = bytes to copy for this page
973 shmem_page_offset
= offset_in_page(offset
);
975 page_length
= remain
;
976 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
977 page_length
= PAGE_SIZE
- shmem_page_offset
;
979 /* If we don't overwrite a cacheline completely we need to be
980 * careful to have up-to-date data by first clflushing. Don't
981 * overcomplicate things and flush the entire patch. */
982 partial_cacheline_write
= needs_clflush_before
&&
983 ((shmem_page_offset
| page_length
)
984 & (boot_cpu_data
.x86_clflush_size
- 1));
986 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
987 (page_to_phys(page
) & (1 << 17)) != 0;
989 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
990 user_data
, page_do_bit17_swizzling
,
991 partial_cacheline_write
,
992 needs_clflush_after
);
997 mutex_unlock(&dev
->struct_mutex
);
998 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
999 user_data
, page_do_bit17_swizzling
,
1000 partial_cacheline_write
,
1001 needs_clflush_after
);
1003 mutex_lock(&dev
->struct_mutex
);
1009 remain
-= page_length
;
1010 user_data
+= page_length
;
1011 offset
+= page_length
;
1015 i915_gem_object_unpin_pages(obj
);
1019 * Fixup: Flush cpu caches in case we didn't flush the dirty
1020 * cachelines in-line while writing and the object moved
1021 * out of the cpu write domain while we've dropped the lock.
1023 if (!needs_clflush_after
&&
1024 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1025 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1026 i915_gem_chipset_flush(dev
);
1030 if (needs_clflush_after
)
1031 i915_gem_chipset_flush(dev
);
1037 * Writes data to the object referenced by handle.
1039 * On error, the contents of the buffer that were to be modified are undefined.
1042 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1043 struct drm_file
*file
)
1045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1046 struct drm_i915_gem_pwrite
*args
= data
;
1047 struct drm_i915_gem_object
*obj
;
1050 if (args
->size
== 0)
1053 if (!access_ok(VERIFY_READ
,
1054 to_user_ptr(args
->data_ptr
),
1058 if (likely(!i915
.prefault_disable
)) {
1059 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1065 intel_runtime_pm_get(dev_priv
);
1067 ret
= i915_mutex_lock_interruptible(dev
);
1071 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1072 if (&obj
->base
== NULL
) {
1077 /* Bounds check destination. */
1078 if (args
->offset
> obj
->base
.size
||
1079 args
->size
> obj
->base
.size
- args
->offset
) {
1084 /* prime objects have no backing filp to GEM pread/pwrite
1087 if (!obj
->base
.filp
) {
1092 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1095 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1096 * it would end up going through the fenced access, and we'll get
1097 * different detiling behavior between reading and writing.
1098 * pread/pwrite currently are reading and writing from the CPU
1099 * perspective, requiring manual detiling by the client.
1101 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1102 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1103 cpu_write_needs_clflush(obj
)) {
1104 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1105 /* Note that the gtt paths might fail with non-page-backed user
1106 * pointers (e.g. gtt mappings when moving data between
1107 * textures). Fallback to the shmem path in that case. */
1110 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1111 if (obj
->phys_handle
)
1112 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1114 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1118 drm_gem_object_unreference(&obj
->base
);
1120 mutex_unlock(&dev
->struct_mutex
);
1122 intel_runtime_pm_put(dev_priv
);
1128 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1131 if (i915_reset_in_progress(error
)) {
1132 /* Non-interruptible callers can't handle -EAGAIN, hence return
1133 * -EIO unconditionally for these. */
1137 /* Recovery complete, but the reset failed ... */
1138 if (i915_terminally_wedged(error
))
1142 * Check if GPU Reset is in progress - we need intel_ring_begin
1143 * to work properly to reinit the hw state while the gpu is
1144 * still marked as reset-in-progress. Handle this with a flag.
1146 if (!error
->reload_in_reset
)
1154 * Compare arbitrary request against outstanding lazy request. Emit on match.
1157 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1161 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1164 if (req
== req
->ring
->outstanding_lazy_request
)
1165 ret
= i915_add_request(req
->ring
);
1170 static void fake_irq(unsigned long data
)
1172 wake_up_process((struct task_struct
*)data
);
1175 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1176 struct intel_engine_cs
*ring
)
1178 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1181 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
1183 if (file_priv
== NULL
)
1186 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1190 * __i915_wait_request - wait until execution of request has finished
1192 * @reset_counter: reset sequence associated with the given request
1193 * @interruptible: do an interruptible wait (normally yes)
1194 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1196 * Note: It is of utmost importance that the passed in seqno and reset_counter
1197 * values have been read by the caller in an smp safe manner. Where read-side
1198 * locks are involved, it is sufficient to read the reset_counter before
1199 * unlocking the lock that protects the seqno. For lockless tricks, the
1200 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1203 * Returns 0 if the request was found within the alloted time. Else returns the
1204 * errno with remaining time filled in timeout argument.
1206 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1207 unsigned reset_counter
,
1210 struct drm_i915_file_private
*file_priv
)
1212 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1213 struct drm_device
*dev
= ring
->dev
;
1214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1215 const bool irq_test_in_progress
=
1216 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1218 unsigned long timeout_expire
;
1222 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1224 if (i915_gem_request_completed(req
, true))
1227 timeout_expire
= timeout
?
1228 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1230 if (INTEL_INFO(dev
)->gen
>= 6 && ring
->id
== RCS
&& can_wait_boost(file_priv
)) {
1231 gen6_rps_boost(dev_priv
);
1233 mod_delayed_work(dev_priv
->wq
,
1234 &file_priv
->mm
.idle_work
,
1235 msecs_to_jiffies(100));
1238 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1241 /* Record current time in case interrupted by signal, or wedged */
1242 trace_i915_gem_request_wait_begin(req
);
1243 before
= ktime_get_raw_ns();
1245 struct timer_list timer
;
1247 prepare_to_wait(&ring
->irq_queue
, &wait
,
1248 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1250 /* We need to check whether any gpu reset happened in between
1251 * the caller grabbing the seqno and now ... */
1252 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1253 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1254 * is truely gone. */
1255 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1261 if (i915_gem_request_completed(req
, false)) {
1266 if (interruptible
&& signal_pending(current
)) {
1271 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1276 timer
.function
= NULL
;
1277 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1278 unsigned long expire
;
1280 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1281 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1282 mod_timer(&timer
, expire
);
1287 if (timer
.function
) {
1288 del_singleshot_timer_sync(&timer
);
1289 destroy_timer_on_stack(&timer
);
1292 now
= ktime_get_raw_ns();
1293 trace_i915_gem_request_wait_end(req
);
1295 if (!irq_test_in_progress
)
1296 ring
->irq_put(ring
);
1298 finish_wait(&ring
->irq_queue
, &wait
);
1301 s64 tres
= *timeout
- (now
- before
);
1303 *timeout
= tres
< 0 ? 0 : tres
;
1306 * Apparently ktime isn't accurate enough and occasionally has a
1307 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1308 * things up to make the test happy. We allow up to 1 jiffy.
1310 * This is a regrssion from the timespec->ktime conversion.
1312 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1320 * Waits for a request to be signaled, and cleans up the
1321 * request and object lists appropriately for that event.
1324 i915_wait_request(struct drm_i915_gem_request
*req
)
1326 struct drm_device
*dev
;
1327 struct drm_i915_private
*dev_priv
;
1329 unsigned reset_counter
;
1332 BUG_ON(req
== NULL
);
1334 dev
= req
->ring
->dev
;
1335 dev_priv
= dev
->dev_private
;
1336 interruptible
= dev_priv
->mm
.interruptible
;
1338 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1340 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1344 ret
= i915_gem_check_olr(req
);
1348 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1349 i915_gem_request_reference(req
);
1350 ret
= __i915_wait_request(req
, reset_counter
,
1351 interruptible
, NULL
, NULL
);
1352 i915_gem_request_unreference(req
);
1357 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1362 /* Manually manage the write flush as we may have not yet
1363 * retired the buffer.
1365 * Note that the last_write_req is always the earlier of
1366 * the two (read/write) requests, so if we haved successfully waited,
1367 * we know we have passed the last write.
1369 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
1375 * Ensures that all rendering to the object has completed and the object is
1376 * safe to unbind from the GTT or access from the CPU.
1378 static __must_check
int
1379 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1382 struct drm_i915_gem_request
*req
;
1385 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1389 ret
= i915_wait_request(req
);
1393 return i915_gem_object_wait_rendering__tail(obj
);
1396 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1397 * as the object state may change during this call.
1399 static __must_check
int
1400 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1401 struct drm_i915_file_private
*file_priv
,
1404 struct drm_i915_gem_request
*req
;
1405 struct drm_device
*dev
= obj
->base
.dev
;
1406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1407 unsigned reset_counter
;
1410 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1411 BUG_ON(!dev_priv
->mm
.interruptible
);
1413 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1417 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1421 ret
= i915_gem_check_olr(req
);
1425 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1426 i915_gem_request_reference(req
);
1427 mutex_unlock(&dev
->struct_mutex
);
1428 ret
= __i915_wait_request(req
, reset_counter
, true, NULL
, file_priv
);
1429 mutex_lock(&dev
->struct_mutex
);
1430 i915_gem_request_unreference(req
);
1434 return i915_gem_object_wait_rendering__tail(obj
);
1438 * Called when user space prepares to use an object with the CPU, either
1439 * through the mmap ioctl's mapping or a GTT mapping.
1442 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1443 struct drm_file
*file
)
1445 struct drm_i915_gem_set_domain
*args
= data
;
1446 struct drm_i915_gem_object
*obj
;
1447 uint32_t read_domains
= args
->read_domains
;
1448 uint32_t write_domain
= args
->write_domain
;
1451 /* Only handle setting domains to types used by the CPU. */
1452 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1455 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1458 /* Having something in the write domain implies it's in the read
1459 * domain, and only that read domain. Enforce that in the request.
1461 if (write_domain
!= 0 && read_domains
!= write_domain
)
1464 ret
= i915_mutex_lock_interruptible(dev
);
1468 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1469 if (&obj
->base
== NULL
) {
1474 /* Try to flush the object off the GPU without holding the lock.
1475 * We will repeat the flush holding the lock in the normal manner
1476 * to catch cases where we are gazumped.
1478 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1484 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1485 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1487 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1490 drm_gem_object_unreference(&obj
->base
);
1492 mutex_unlock(&dev
->struct_mutex
);
1497 * Called when user space has done writes to this buffer
1500 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1501 struct drm_file
*file
)
1503 struct drm_i915_gem_sw_finish
*args
= data
;
1504 struct drm_i915_gem_object
*obj
;
1507 ret
= i915_mutex_lock_interruptible(dev
);
1511 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1512 if (&obj
->base
== NULL
) {
1517 /* Pinned buffers may be scanout, so flush the cache */
1518 if (obj
->pin_display
)
1519 i915_gem_object_flush_cpu_write_domain(obj
, true);
1521 drm_gem_object_unreference(&obj
->base
);
1523 mutex_unlock(&dev
->struct_mutex
);
1528 * Maps the contents of an object, returning the address it is mapped
1531 * While the mapping holds a reference on the contents of the object, it doesn't
1532 * imply a ref on the object itself.
1536 * DRM driver writers who look a this function as an example for how to do GEM
1537 * mmap support, please don't implement mmap support like here. The modern way
1538 * to implement DRM mmap support is with an mmap offset ioctl (like
1539 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1540 * That way debug tooling like valgrind will understand what's going on, hiding
1541 * the mmap call in a driver private ioctl will break that. The i915 driver only
1542 * does cpu mmaps this way because we didn't know better.
1545 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1546 struct drm_file
*file
)
1548 struct drm_i915_gem_mmap
*args
= data
;
1549 struct drm_gem_object
*obj
;
1552 if (args
->flags
& ~(I915_MMAP_WC
))
1555 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1558 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1562 /* prime objects have no backing filp to GEM mmap
1566 drm_gem_object_unreference_unlocked(obj
);
1570 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1571 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1573 if (args
->flags
& I915_MMAP_WC
) {
1574 struct mm_struct
*mm
= current
->mm
;
1575 struct vm_area_struct
*vma
;
1577 down_write(&mm
->mmap_sem
);
1578 vma
= find_vma(mm
, addr
);
1581 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1584 up_write(&mm
->mmap_sem
);
1586 drm_gem_object_unreference_unlocked(obj
);
1587 if (IS_ERR((void *)addr
))
1590 args
->addr_ptr
= (uint64_t) addr
;
1596 * i915_gem_fault - fault a page into the GTT
1597 * vma: VMA in question
1600 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1601 * from userspace. The fault handler takes care of binding the object to
1602 * the GTT (if needed), allocating and programming a fence register (again,
1603 * only if needed based on whether the old reg is still valid or the object
1604 * is tiled) and inserting a new PTE into the faulting process.
1606 * Note that the faulting process may involve evicting existing objects
1607 * from the GTT and/or fence registers to make room. So performance may
1608 * suffer if the GTT working set is large or there are few fence registers
1611 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1613 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1614 struct drm_device
*dev
= obj
->base
.dev
;
1615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1616 pgoff_t page_offset
;
1619 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1621 intel_runtime_pm_get(dev_priv
);
1623 /* We don't use vmf->pgoff since that has the fake offset */
1624 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1627 ret
= i915_mutex_lock_interruptible(dev
);
1631 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1633 /* Try to flush the object off the GPU first without holding the lock.
1634 * Upon reacquiring the lock, we will perform our sanity checks and then
1635 * repeat the flush holding the lock in the normal manner to catch cases
1636 * where we are gazumped.
1638 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1642 /* Access to snoopable pages through the GTT is incoherent. */
1643 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1648 /* Now bind it into the GTT if needed */
1649 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1653 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1657 ret
= i915_gem_object_get_fence(obj
);
1661 /* Finally, remap it using the new GTT offset */
1662 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1665 if (!obj
->fault_mappable
) {
1666 unsigned long size
= min_t(unsigned long,
1667 vma
->vm_end
- vma
->vm_start
,
1671 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1672 ret
= vm_insert_pfn(vma
,
1673 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1679 obj
->fault_mappable
= true;
1681 ret
= vm_insert_pfn(vma
,
1682 (unsigned long)vmf
->virtual_address
,
1685 i915_gem_object_ggtt_unpin(obj
);
1687 mutex_unlock(&dev
->struct_mutex
);
1692 * We eat errors when the gpu is terminally wedged to avoid
1693 * userspace unduly crashing (gl has no provisions for mmaps to
1694 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1695 * and so needs to be reported.
1697 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1698 ret
= VM_FAULT_SIGBUS
;
1703 * EAGAIN means the gpu is hung and we'll wait for the error
1704 * handler to reset everything when re-faulting in
1705 * i915_mutex_lock_interruptible.
1712 * EBUSY is ok: this just means that another thread
1713 * already did the job.
1715 ret
= VM_FAULT_NOPAGE
;
1722 ret
= VM_FAULT_SIGBUS
;
1725 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1726 ret
= VM_FAULT_SIGBUS
;
1730 intel_runtime_pm_put(dev_priv
);
1735 * i915_gem_release_mmap - remove physical page mappings
1736 * @obj: obj in question
1738 * Preserve the reservation of the mmapping with the DRM core code, but
1739 * relinquish ownership of the pages back to the system.
1741 * It is vital that we remove the page mapping if we have mapped a tiled
1742 * object through the GTT and then lose the fence register due to
1743 * resource pressure. Similarly if the object has been moved out of the
1744 * aperture, than pages mapped into userspace must be revoked. Removing the
1745 * mapping will then trigger a page fault on the next user access, allowing
1746 * fixup by i915_gem_fault().
1749 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1751 if (!obj
->fault_mappable
)
1754 drm_vma_node_unmap(&obj
->base
.vma_node
,
1755 obj
->base
.dev
->anon_inode
->i_mapping
);
1756 obj
->fault_mappable
= false;
1760 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1762 struct drm_i915_gem_object
*obj
;
1764 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1765 i915_gem_release_mmap(obj
);
1769 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1773 if (INTEL_INFO(dev
)->gen
>= 4 ||
1774 tiling_mode
== I915_TILING_NONE
)
1777 /* Previous chips need a power-of-two fence region when tiling */
1778 if (INTEL_INFO(dev
)->gen
== 3)
1779 gtt_size
= 1024*1024;
1781 gtt_size
= 512*1024;
1783 while (gtt_size
< size
)
1790 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1791 * @obj: object to check
1793 * Return the required GTT alignment for an object, taking into account
1794 * potential fence register mapping.
1797 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1798 int tiling_mode
, bool fenced
)
1801 * Minimum alignment is 4k (GTT page size), but might be greater
1802 * if a fence register is needed for the object.
1804 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1805 tiling_mode
== I915_TILING_NONE
)
1809 * Previous chips need to be aligned to the size of the smallest
1810 * fence register that can contain the object.
1812 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1815 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1817 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1820 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1823 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1825 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1829 /* Badly fragmented mmap space? The only way we can recover
1830 * space is by destroying unwanted objects. We can't randomly release
1831 * mmap_offsets as userspace expects them to be persistent for the
1832 * lifetime of the objects. The closest we can is to release the
1833 * offsets on purgeable objects by truncating it and marking it purged,
1834 * which prevents userspace from ever using that object again.
1836 i915_gem_shrink(dev_priv
,
1837 obj
->base
.size
>> PAGE_SHIFT
,
1839 I915_SHRINK_UNBOUND
|
1840 I915_SHRINK_PURGEABLE
);
1841 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1845 i915_gem_shrink_all(dev_priv
);
1846 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1848 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1853 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1855 drm_gem_free_mmap_offset(&obj
->base
);
1859 i915_gem_mmap_gtt(struct drm_file
*file
,
1860 struct drm_device
*dev
,
1864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1865 struct drm_i915_gem_object
*obj
;
1868 ret
= i915_mutex_lock_interruptible(dev
);
1872 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1873 if (&obj
->base
== NULL
) {
1878 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1883 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1884 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1889 ret
= i915_gem_object_create_mmap_offset(obj
);
1893 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1896 drm_gem_object_unreference(&obj
->base
);
1898 mutex_unlock(&dev
->struct_mutex
);
1903 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1905 * @data: GTT mapping ioctl data
1906 * @file: GEM object info
1908 * Simply returns the fake offset to userspace so it can mmap it.
1909 * The mmap call will end up in drm_gem_mmap(), which will set things
1910 * up so we can get faults in the handler above.
1912 * The fault handler will take care of binding the object into the GTT
1913 * (since it may have been evicted to make room for something), allocating
1914 * a fence register, and mapping the appropriate aperture address into
1918 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1919 struct drm_file
*file
)
1921 struct drm_i915_gem_mmap_gtt
*args
= data
;
1923 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1927 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1929 return obj
->madv
== I915_MADV_DONTNEED
;
1932 /* Immediately discard the backing storage */
1934 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1936 i915_gem_object_free_mmap_offset(obj
);
1938 if (obj
->base
.filp
== NULL
)
1941 /* Our goal here is to return as much of the memory as
1942 * is possible back to the system as we are called from OOM.
1943 * To do this we must instruct the shmfs to drop all of its
1944 * backing pages, *now*.
1946 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1947 obj
->madv
= __I915_MADV_PURGED
;
1950 /* Try to discard unwanted pages */
1952 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1954 struct address_space
*mapping
;
1956 switch (obj
->madv
) {
1957 case I915_MADV_DONTNEED
:
1958 i915_gem_object_truncate(obj
);
1959 case __I915_MADV_PURGED
:
1963 if (obj
->base
.filp
== NULL
)
1966 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1967 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1971 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1973 struct sg_page_iter sg_iter
;
1976 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1978 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1980 /* In the event of a disaster, abandon all caches and
1981 * hope for the best.
1983 WARN_ON(ret
!= -EIO
);
1984 i915_gem_clflush_object(obj
, true);
1985 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1988 if (i915_gem_object_needs_bit17_swizzle(obj
))
1989 i915_gem_object_save_bit_17_swizzle(obj
);
1991 if (obj
->madv
== I915_MADV_DONTNEED
)
1994 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1995 struct page
*page
= sg_page_iter_page(&sg_iter
);
1998 set_page_dirty(page
);
2000 if (obj
->madv
== I915_MADV_WILLNEED
)
2001 mark_page_accessed(page
);
2003 page_cache_release(page
);
2007 sg_free_table(obj
->pages
);
2012 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2014 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2016 if (obj
->pages
== NULL
)
2019 if (obj
->pages_pin_count
)
2022 BUG_ON(i915_gem_obj_bound_any(obj
));
2024 /* ->put_pages might need to allocate memory for the bit17 swizzle
2025 * array, hence protect them from being reaped by removing them from gtt
2027 list_del(&obj
->global_list
);
2029 ops
->put_pages(obj
);
2032 i915_gem_object_invalidate(obj
);
2038 i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2039 long target
, unsigned flags
)
2042 struct list_head
*list
;
2045 { &dev_priv
->mm
.unbound_list
, I915_SHRINK_UNBOUND
},
2046 { &dev_priv
->mm
.bound_list
, I915_SHRINK_BOUND
},
2049 unsigned long count
= 0;
2052 * As we may completely rewrite the (un)bound list whilst unbinding
2053 * (due to retiring requests) we have to strictly process only
2054 * one element of the list at the time, and recheck the list
2055 * on every iteration.
2057 * In particular, we must hold a reference whilst removing the
2058 * object as we may end up waiting for and/or retiring the objects.
2059 * This might release the final reference (held by the active list)
2060 * and result in the object being freed from under us. This is
2061 * similar to the precautions the eviction code must take whilst
2064 * Also note that although these lists do not hold a reference to
2065 * the object we can safely grab one here: The final object
2066 * unreferencing and the bound_list are both protected by the
2067 * dev->struct_mutex and so we won't ever be able to observe an
2068 * object on the bound_list with a reference count equals 0.
2070 for (phase
= phases
; phase
->list
; phase
++) {
2071 struct list_head still_in_list
;
2073 if ((flags
& phase
->bit
) == 0)
2076 INIT_LIST_HEAD(&still_in_list
);
2077 while (count
< target
&& !list_empty(phase
->list
)) {
2078 struct drm_i915_gem_object
*obj
;
2079 struct i915_vma
*vma
, *v
;
2081 obj
= list_first_entry(phase
->list
,
2082 typeof(*obj
), global_list
);
2083 list_move_tail(&obj
->global_list
, &still_in_list
);
2085 if (flags
& I915_SHRINK_PURGEABLE
&&
2086 !i915_gem_object_is_purgeable(obj
))
2089 drm_gem_object_reference(&obj
->base
);
2091 /* For the unbound phase, this should be a no-op! */
2092 list_for_each_entry_safe(vma
, v
,
2093 &obj
->vma_list
, vma_link
)
2094 if (i915_vma_unbind(vma
))
2097 if (i915_gem_object_put_pages(obj
) == 0)
2098 count
+= obj
->base
.size
>> PAGE_SHIFT
;
2100 drm_gem_object_unreference(&obj
->base
);
2102 list_splice(&still_in_list
, phase
->list
);
2108 static unsigned long
2109 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
2111 i915_gem_evict_everything(dev_priv
->dev
);
2112 return i915_gem_shrink(dev_priv
, LONG_MAX
,
2113 I915_SHRINK_BOUND
| I915_SHRINK_UNBOUND
);
2117 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2119 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2121 struct address_space
*mapping
;
2122 struct sg_table
*st
;
2123 struct scatterlist
*sg
;
2124 struct sg_page_iter sg_iter
;
2126 unsigned long last_pfn
= 0; /* suppress gcc warning */
2129 /* Assert that the object is not currently in any GPU domain. As it
2130 * wasn't in the GTT, there shouldn't be any way it could have been in
2133 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2134 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2136 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2140 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2141 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2146 /* Get the list of pages out of our struct file. They'll be pinned
2147 * at this point until we release them.
2149 * Fail silently without starting the shrinker
2151 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2152 gfp
= mapping_gfp_mask(mapping
);
2153 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2154 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2157 for (i
= 0; i
< page_count
; i
++) {
2158 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2160 i915_gem_shrink(dev_priv
,
2163 I915_SHRINK_UNBOUND
|
2164 I915_SHRINK_PURGEABLE
);
2165 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2168 /* We've tried hard to allocate the memory by reaping
2169 * our own buffer, now let the real VM do its job and
2170 * go down in flames if truly OOM.
2172 i915_gem_shrink_all(dev_priv
);
2173 page
= shmem_read_mapping_page(mapping
, i
);
2177 #ifdef CONFIG_SWIOTLB
2178 if (swiotlb_nr_tbl()) {
2180 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2185 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2189 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2191 sg
->length
+= PAGE_SIZE
;
2193 last_pfn
= page_to_pfn(page
);
2195 /* Check that the i965g/gm workaround works. */
2196 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2198 #ifdef CONFIG_SWIOTLB
2199 if (!swiotlb_nr_tbl())
2204 if (i915_gem_object_needs_bit17_swizzle(obj
))
2205 i915_gem_object_do_bit_17_swizzle(obj
);
2207 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2208 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2209 i915_gem_object_pin_pages(obj
);
2215 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2216 page_cache_release(sg_page_iter_page(&sg_iter
));
2220 /* shmemfs first checks if there is enough memory to allocate the page
2221 * and reports ENOSPC should there be insufficient, along with the usual
2222 * ENOMEM for a genuine allocation failure.
2224 * We use ENOSPC in our driver to mean that we have run out of aperture
2225 * space and so want to translate the error from shmemfs back to our
2226 * usual understanding of ENOMEM.
2228 if (PTR_ERR(page
) == -ENOSPC
)
2231 return PTR_ERR(page
);
2234 /* Ensure that the associated pages are gathered from the backing storage
2235 * and pinned into our object. i915_gem_object_get_pages() may be called
2236 * multiple times before they are released by a single call to
2237 * i915_gem_object_put_pages() - once the pages are no longer referenced
2238 * either as a result of memory pressure (reaping pages under the shrinker)
2239 * or as the object is itself released.
2242 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2244 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2245 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2251 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2252 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2256 BUG_ON(obj
->pages_pin_count
);
2258 ret
= ops
->get_pages(obj
);
2262 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2267 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2268 struct intel_engine_cs
*ring
)
2270 struct drm_i915_gem_request
*req
;
2271 struct intel_engine_cs
*old_ring
;
2273 BUG_ON(ring
== NULL
);
2275 req
= intel_ring_get_request(ring
);
2276 old_ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2278 if (old_ring
!= ring
&& obj
->last_write_req
) {
2279 /* Keep the request relative to the current ring */
2280 i915_gem_request_assign(&obj
->last_write_req
, req
);
2283 /* Add a reference if we're newly entering the active list. */
2285 drm_gem_object_reference(&obj
->base
);
2289 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2291 i915_gem_request_assign(&obj
->last_read_req
, req
);
2294 void i915_vma_move_to_active(struct i915_vma
*vma
,
2295 struct intel_engine_cs
*ring
)
2297 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2298 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2302 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2304 struct i915_vma
*vma
;
2306 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2307 BUG_ON(!obj
->active
);
2309 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2310 if (!list_empty(&vma
->mm_list
))
2311 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2314 intel_fb_obj_flush(obj
, true);
2316 list_del_init(&obj
->ring_list
);
2318 i915_gem_request_assign(&obj
->last_read_req
, NULL
);
2319 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2320 obj
->base
.write_domain
= 0;
2322 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2325 drm_gem_object_unreference(&obj
->base
);
2327 WARN_ON(i915_verify_lists(dev
));
2331 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2333 if (obj
->last_read_req
== NULL
)
2336 if (i915_gem_request_completed(obj
->last_read_req
, true))
2337 i915_gem_object_move_to_inactive(obj
);
2341 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2344 struct intel_engine_cs
*ring
;
2347 /* Carefully retire all requests without writing to the rings */
2348 for_each_ring(ring
, dev_priv
, i
) {
2349 ret
= intel_ring_idle(ring
);
2353 i915_gem_retire_requests(dev
);
2355 /* Finally reset hw state */
2356 for_each_ring(ring
, dev_priv
, i
) {
2357 intel_ring_init_seqno(ring
, seqno
);
2359 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2360 ring
->semaphore
.sync_seqno
[j
] = 0;
2366 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2374 /* HWS page needs to be set less than what we
2375 * will inject to ring
2377 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2381 /* Carefully set the last_seqno value so that wrap
2382 * detection still works
2384 dev_priv
->next_seqno
= seqno
;
2385 dev_priv
->last_seqno
= seqno
- 1;
2386 if (dev_priv
->last_seqno
== 0)
2387 dev_priv
->last_seqno
--;
2393 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2397 /* reserve 0 for non-seqno */
2398 if (dev_priv
->next_seqno
== 0) {
2399 int ret
= i915_gem_init_seqno(dev
, 0);
2403 dev_priv
->next_seqno
= 1;
2406 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2410 int __i915_add_request(struct intel_engine_cs
*ring
,
2411 struct drm_file
*file
,
2412 struct drm_i915_gem_object
*obj
)
2414 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2415 struct drm_i915_gem_request
*request
;
2416 struct intel_ringbuffer
*ringbuf
;
2417 u32 request_ring_position
, request_start
;
2420 request
= ring
->outstanding_lazy_request
;
2421 if (WARN_ON(request
== NULL
))
2424 if (i915
.enable_execlists
) {
2425 struct intel_context
*ctx
= request
->ctx
;
2426 ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
2428 ringbuf
= ring
->buffer
;
2430 request_start
= intel_ring_get_tail(ringbuf
);
2432 * Emit any outstanding flushes - execbuf can fail to emit the flush
2433 * after having emitted the batchbuffer command. Hence we need to fix
2434 * things up similar to emitting the lazy request. The difference here
2435 * is that the flush _must_ happen before the next request, no matter
2438 if (i915
.enable_execlists
) {
2439 ret
= logical_ring_flush_all_caches(ringbuf
);
2443 ret
= intel_ring_flush_all_caches(ring
);
2448 /* Record the position of the start of the request so that
2449 * should we detect the updated seqno part-way through the
2450 * GPU processing the request, we never over-estimate the
2451 * position of the head.
2453 request_ring_position
= intel_ring_get_tail(ringbuf
);
2455 if (i915
.enable_execlists
) {
2456 ret
= ring
->emit_request(ringbuf
);
2460 ret
= ring
->add_request(ring
);
2465 request
->head
= request_start
;
2466 request
->tail
= request_ring_position
;
2468 /* Whilst this request exists, batch_obj will be on the
2469 * active_list, and so will hold the active reference. Only when this
2470 * request is retired will the the batch_obj be moved onto the
2471 * inactive_list and lose its active reference. Hence we do not need
2472 * to explicitly hold another reference here.
2474 request
->batch_obj
= obj
;
2476 if (!i915
.enable_execlists
) {
2477 /* Hold a reference to the current context so that we can inspect
2478 * it later in case a hangcheck error event fires.
2480 request
->ctx
= ring
->last_context
;
2482 i915_gem_context_reference(request
->ctx
);
2485 request
->emitted_jiffies
= jiffies
;
2486 list_add_tail(&request
->list
, &ring
->request_list
);
2487 request
->file_priv
= NULL
;
2490 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2492 spin_lock(&file_priv
->mm
.lock
);
2493 request
->file_priv
= file_priv
;
2494 list_add_tail(&request
->client_list
,
2495 &file_priv
->mm
.request_list
);
2496 spin_unlock(&file_priv
->mm
.lock
);
2499 trace_i915_gem_request_add(request
);
2500 ring
->outstanding_lazy_request
= NULL
;
2502 i915_queue_hangcheck(ring
->dev
);
2504 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2505 queue_delayed_work(dev_priv
->wq
,
2506 &dev_priv
->mm
.retire_work
,
2507 round_jiffies_up_relative(HZ
));
2508 intel_mark_busy(dev_priv
->dev
);
2514 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2516 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2521 spin_lock(&file_priv
->mm
.lock
);
2522 list_del(&request
->client_list
);
2523 request
->file_priv
= NULL
;
2524 spin_unlock(&file_priv
->mm
.lock
);
2527 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2528 const struct intel_context
*ctx
)
2530 unsigned long elapsed
;
2532 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2534 if (ctx
->hang_stats
.banned
)
2537 if (ctx
->hang_stats
.ban_period_seconds
&&
2538 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2539 if (!i915_gem_context_is_default(ctx
)) {
2540 DRM_DEBUG("context hanging too fast, banning!\n");
2542 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2543 if (i915_stop_ring_allow_warn(dev_priv
))
2544 DRM_ERROR("gpu hanging too fast, banning!\n");
2552 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2553 struct intel_context
*ctx
,
2556 struct i915_ctx_hang_stats
*hs
;
2561 hs
= &ctx
->hang_stats
;
2564 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2566 hs
->guilty_ts
= get_seconds();
2568 hs
->batch_pending
++;
2572 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2574 list_del(&request
->list
);
2575 i915_gem_request_remove_from_client(request
);
2577 i915_gem_request_unreference(request
);
2580 void i915_gem_request_free(struct kref
*req_ref
)
2582 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2584 struct intel_context
*ctx
= req
->ctx
;
2587 if (i915
.enable_execlists
) {
2588 struct intel_engine_cs
*ring
= req
->ring
;
2590 if (ctx
!= ring
->default_context
)
2591 intel_lr_context_unpin(ring
, ctx
);
2594 i915_gem_context_unreference(ctx
);
2600 struct drm_i915_gem_request
*
2601 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2603 struct drm_i915_gem_request
*request
;
2605 list_for_each_entry(request
, &ring
->request_list
, list
) {
2606 if (i915_gem_request_completed(request
, false))
2615 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2616 struct intel_engine_cs
*ring
)
2618 struct drm_i915_gem_request
*request
;
2621 request
= i915_gem_find_active_request(ring
);
2623 if (request
== NULL
)
2626 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2628 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2630 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2631 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2634 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2635 struct intel_engine_cs
*ring
)
2637 while (!list_empty(&ring
->active_list
)) {
2638 struct drm_i915_gem_object
*obj
;
2640 obj
= list_first_entry(&ring
->active_list
,
2641 struct drm_i915_gem_object
,
2644 i915_gem_object_move_to_inactive(obj
);
2648 * Clear the execlists queue up before freeing the requests, as those
2649 * are the ones that keep the context and ringbuffer backing objects
2652 while (!list_empty(&ring
->execlist_queue
)) {
2653 struct intel_ctx_submit_request
*submit_req
;
2655 submit_req
= list_first_entry(&ring
->execlist_queue
,
2656 struct intel_ctx_submit_request
,
2658 list_del(&submit_req
->execlist_link
);
2659 intel_runtime_pm_put(dev_priv
);
2660 i915_gem_context_unreference(submit_req
->ctx
);
2665 * We must free the requests after all the corresponding objects have
2666 * been moved off active lists. Which is the same order as the normal
2667 * retire_requests function does. This is important if object hold
2668 * implicit references on things like e.g. ppgtt address spaces through
2671 while (!list_empty(&ring
->request_list
)) {
2672 struct drm_i915_gem_request
*request
;
2674 request
= list_first_entry(&ring
->request_list
,
2675 struct drm_i915_gem_request
,
2678 i915_gem_free_request(request
);
2681 /* This may not have been flushed before the reset, so clean it now */
2682 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2685 void i915_gem_restore_fences(struct drm_device
*dev
)
2687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2690 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2691 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2694 * Commit delayed tiling changes if we have an object still
2695 * attached to the fence, otherwise just clear the fence.
2698 i915_gem_object_update_fence(reg
->obj
, reg
,
2699 reg
->obj
->tiling_mode
);
2701 i915_gem_write_fence(dev
, i
, NULL
);
2706 void i915_gem_reset(struct drm_device
*dev
)
2708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2709 struct intel_engine_cs
*ring
;
2713 * Before we free the objects from the requests, we need to inspect
2714 * them for finding the guilty party. As the requests only borrow
2715 * their reference to the objects, the inspection must be done first.
2717 for_each_ring(ring
, dev_priv
, i
)
2718 i915_gem_reset_ring_status(dev_priv
, ring
);
2720 for_each_ring(ring
, dev_priv
, i
)
2721 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2723 i915_gem_context_reset(dev
);
2725 i915_gem_restore_fences(dev
);
2729 * This function clears the request list as sequence numbers are passed.
2732 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2734 if (list_empty(&ring
->request_list
))
2737 WARN_ON(i915_verify_lists(ring
->dev
));
2739 /* Move any buffers on the active list that are no longer referenced
2740 * by the ringbuffer to the flushing/inactive lists as appropriate,
2741 * before we free the context associated with the requests.
2743 while (!list_empty(&ring
->active_list
)) {
2744 struct drm_i915_gem_object
*obj
;
2746 obj
= list_first_entry(&ring
->active_list
,
2747 struct drm_i915_gem_object
,
2750 if (!i915_gem_request_completed(obj
->last_read_req
, true))
2753 i915_gem_object_move_to_inactive(obj
);
2757 while (!list_empty(&ring
->request_list
)) {
2758 struct drm_i915_gem_request
*request
;
2759 struct intel_ringbuffer
*ringbuf
;
2761 request
= list_first_entry(&ring
->request_list
,
2762 struct drm_i915_gem_request
,
2765 if (!i915_gem_request_completed(request
, true))
2768 trace_i915_gem_request_retire(request
);
2770 /* This is one of the few common intersection points
2771 * between legacy ringbuffer submission and execlists:
2772 * we need to tell them apart in order to find the correct
2773 * ringbuffer to which the request belongs to.
2775 if (i915
.enable_execlists
) {
2776 struct intel_context
*ctx
= request
->ctx
;
2777 ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
2779 ringbuf
= ring
->buffer
;
2781 /* We know the GPU must have read the request to have
2782 * sent us the seqno + interrupt, so use the position
2783 * of tail of the request to update the last known position
2786 ringbuf
->last_retired_head
= request
->tail
;
2788 i915_gem_free_request(request
);
2791 if (unlikely(ring
->trace_irq_req
&&
2792 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2793 ring
->irq_put(ring
);
2794 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2797 WARN_ON(i915_verify_lists(ring
->dev
));
2801 i915_gem_retire_requests(struct drm_device
*dev
)
2803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2804 struct intel_engine_cs
*ring
;
2808 for_each_ring(ring
, dev_priv
, i
) {
2809 i915_gem_retire_requests_ring(ring
);
2810 idle
&= list_empty(&ring
->request_list
);
2811 if (i915
.enable_execlists
) {
2812 unsigned long flags
;
2814 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2815 idle
&= list_empty(&ring
->execlist_queue
);
2816 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2818 intel_execlists_retire_requests(ring
);
2823 mod_delayed_work(dev_priv
->wq
,
2824 &dev_priv
->mm
.idle_work
,
2825 msecs_to_jiffies(100));
2831 i915_gem_retire_work_handler(struct work_struct
*work
)
2833 struct drm_i915_private
*dev_priv
=
2834 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2835 struct drm_device
*dev
= dev_priv
->dev
;
2838 /* Come back later if the device is busy... */
2840 if (mutex_trylock(&dev
->struct_mutex
)) {
2841 idle
= i915_gem_retire_requests(dev
);
2842 mutex_unlock(&dev
->struct_mutex
);
2845 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2846 round_jiffies_up_relative(HZ
));
2850 i915_gem_idle_work_handler(struct work_struct
*work
)
2852 struct drm_i915_private
*dev_priv
=
2853 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2855 intel_mark_idle(dev_priv
->dev
);
2859 * Ensures that an object will eventually get non-busy by flushing any required
2860 * write domains, emitting any outstanding lazy request and retiring and
2861 * completed requests.
2864 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2866 struct intel_engine_cs
*ring
;
2870 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2872 ret
= i915_gem_check_olr(obj
->last_read_req
);
2876 i915_gem_retire_requests_ring(ring
);
2883 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2884 * @DRM_IOCTL_ARGS: standard ioctl arguments
2886 * Returns 0 if successful, else an error is returned with the remaining time in
2887 * the timeout parameter.
2888 * -ETIME: object is still busy after timeout
2889 * -ERESTARTSYS: signal interrupted the wait
2890 * -ENONENT: object doesn't exist
2891 * Also possible, but rare:
2892 * -EAGAIN: GPU wedged
2894 * -ENODEV: Internal IRQ fail
2895 * -E?: The add request failed
2897 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2898 * non-zero timeout parameter the wait ioctl will wait for the given number of
2899 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2900 * without holding struct_mutex the object may become re-busied before this
2901 * function completes. A similar but shorter * race condition exists in the busy
2905 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2908 struct drm_i915_gem_wait
*args
= data
;
2909 struct drm_i915_gem_object
*obj
;
2910 struct drm_i915_gem_request
*req
;
2911 unsigned reset_counter
;
2914 if (args
->flags
!= 0)
2917 ret
= i915_mutex_lock_interruptible(dev
);
2921 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2922 if (&obj
->base
== NULL
) {
2923 mutex_unlock(&dev
->struct_mutex
);
2927 /* Need to make sure the object gets inactive eventually. */
2928 ret
= i915_gem_object_flush_active(obj
);
2932 if (!obj
->active
|| !obj
->last_read_req
)
2935 req
= obj
->last_read_req
;
2937 /* Do this after OLR check to make sure we make forward progress polling
2938 * on this IOCTL with a timeout <=0 (like busy ioctl)
2940 if (args
->timeout_ns
<= 0) {
2945 drm_gem_object_unreference(&obj
->base
);
2946 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2947 i915_gem_request_reference(req
);
2948 mutex_unlock(&dev
->struct_mutex
);
2950 ret
= __i915_wait_request(req
, reset_counter
, true, &args
->timeout_ns
,
2952 mutex_lock(&dev
->struct_mutex
);
2953 i915_gem_request_unreference(req
);
2954 mutex_unlock(&dev
->struct_mutex
);
2958 drm_gem_object_unreference(&obj
->base
);
2959 mutex_unlock(&dev
->struct_mutex
);
2964 * i915_gem_object_sync - sync an object to a ring.
2966 * @obj: object which may be in use on another ring.
2967 * @to: ring we wish to use the object on. May be NULL.
2969 * This code is meant to abstract object synchronization with the GPU.
2970 * Calling with NULL implies synchronizing the object with the CPU
2971 * rather than a particular GPU ring.
2973 * Returns 0 if successful, else propagates up the lower layer error.
2976 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2977 struct intel_engine_cs
*to
)
2979 struct intel_engine_cs
*from
;
2983 from
= i915_gem_request_get_ring(obj
->last_read_req
);
2985 if (from
== NULL
|| to
== from
)
2988 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2989 return i915_gem_object_wait_rendering(obj
, false);
2991 idx
= intel_ring_sync_index(from
, to
);
2993 seqno
= i915_gem_request_get_seqno(obj
->last_read_req
);
2994 /* Optimization: Avoid semaphore sync when we are sure we already
2995 * waited for an object with higher seqno */
2996 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
2999 ret
= i915_gem_check_olr(obj
->last_read_req
);
3003 trace_i915_gem_ring_sync_to(from
, to
, obj
->last_read_req
);
3004 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
3006 /* We use last_read_req because sync_to()
3007 * might have just caused seqno wrap under
3010 from
->semaphore
.sync_seqno
[idx
] =
3011 i915_gem_request_get_seqno(obj
->last_read_req
);
3016 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3018 u32 old_write_domain
, old_read_domains
;
3020 /* Force a pagefault for domain tracking on next user access */
3021 i915_gem_release_mmap(obj
);
3023 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3026 /* Wait for any direct GTT access to complete */
3029 old_read_domains
= obj
->base
.read_domains
;
3030 old_write_domain
= obj
->base
.write_domain
;
3032 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3033 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3035 trace_i915_gem_object_change_domain(obj
,
3040 int i915_vma_unbind(struct i915_vma
*vma
)
3042 struct drm_i915_gem_object
*obj
= vma
->obj
;
3043 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3046 if (list_empty(&vma
->vma_link
))
3049 if (!drm_mm_node_allocated(&vma
->node
)) {
3050 i915_gem_vma_destroy(vma
);
3057 BUG_ON(obj
->pages
== NULL
);
3059 ret
= i915_gem_object_finish_gpu(obj
);
3062 /* Continue on if we fail due to EIO, the GPU is hung so we
3063 * should be safe and we need to cleanup or else we might
3064 * cause memory corruption through use-after-free.
3067 if (i915_is_ggtt(vma
->vm
) &&
3068 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3069 i915_gem_object_finish_gtt(obj
);
3071 /* release the fence reg _after_ flushing */
3072 ret
= i915_gem_object_put_fence(obj
);
3077 trace_i915_vma_unbind(vma
);
3079 vma
->unbind_vma(vma
);
3081 list_del_init(&vma
->mm_list
);
3082 if (i915_is_ggtt(vma
->vm
)) {
3083 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3084 obj
->map_and_fenceable
= false;
3085 } else if (vma
->ggtt_view
.pages
) {
3086 sg_free_table(vma
->ggtt_view
.pages
);
3087 kfree(vma
->ggtt_view
.pages
);
3088 vma
->ggtt_view
.pages
= NULL
;
3092 drm_mm_remove_node(&vma
->node
);
3093 i915_gem_vma_destroy(vma
);
3095 /* Since the unbound list is global, only move to that list if
3096 * no more VMAs exist. */
3097 if (list_empty(&obj
->vma_list
)) {
3098 /* Throw away the active reference before
3099 * moving to the unbound list. */
3100 i915_gem_object_retire(obj
);
3102 i915_gem_gtt_finish_object(obj
);
3103 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3106 /* And finally now the object is completely decoupled from this vma,
3107 * we can drop its hold on the backing storage and allow it to be
3108 * reaped by the shrinker.
3110 i915_gem_object_unpin_pages(obj
);
3115 int i915_gpu_idle(struct drm_device
*dev
)
3117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3118 struct intel_engine_cs
*ring
;
3121 /* Flush everything onto the inactive list. */
3122 for_each_ring(ring
, dev_priv
, i
) {
3123 if (!i915
.enable_execlists
) {
3124 ret
= i915_switch_context(ring
, ring
->default_context
);
3129 ret
= intel_ring_idle(ring
);
3137 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3138 struct drm_i915_gem_object
*obj
)
3140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3142 int fence_pitch_shift
;
3144 if (INTEL_INFO(dev
)->gen
>= 6) {
3145 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3146 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3148 fence_reg
= FENCE_REG_965_0
;
3149 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3152 fence_reg
+= reg
* 8;
3154 /* To w/a incoherency with non-atomic 64-bit register updates,
3155 * we split the 64-bit update into two 32-bit writes. In order
3156 * for a partial fence not to be evaluated between writes, we
3157 * precede the update with write to turn off the fence register,
3158 * and only enable the fence as the last step.
3160 * For extra levels of paranoia, we make sure each step lands
3161 * before applying the next step.
3163 I915_WRITE(fence_reg
, 0);
3164 POSTING_READ(fence_reg
);
3167 u32 size
= i915_gem_obj_ggtt_size(obj
);
3170 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3172 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3173 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3174 if (obj
->tiling_mode
== I915_TILING_Y
)
3175 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3176 val
|= I965_FENCE_REG_VALID
;
3178 I915_WRITE(fence_reg
+ 4, val
>> 32);
3179 POSTING_READ(fence_reg
+ 4);
3181 I915_WRITE(fence_reg
+ 0, val
);
3182 POSTING_READ(fence_reg
);
3184 I915_WRITE(fence_reg
+ 4, 0);
3185 POSTING_READ(fence_reg
+ 4);
3189 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3190 struct drm_i915_gem_object
*obj
)
3192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3196 u32 size
= i915_gem_obj_ggtt_size(obj
);
3200 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3201 (size
& -size
) != size
||
3202 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3203 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3204 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3206 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3211 /* Note: pitch better be a power of two tile widths */
3212 pitch_val
= obj
->stride
/ tile_width
;
3213 pitch_val
= ffs(pitch_val
) - 1;
3215 val
= i915_gem_obj_ggtt_offset(obj
);
3216 if (obj
->tiling_mode
== I915_TILING_Y
)
3217 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3218 val
|= I915_FENCE_SIZE_BITS(size
);
3219 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3220 val
|= I830_FENCE_REG_VALID
;
3225 reg
= FENCE_REG_830_0
+ reg
* 4;
3227 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3229 I915_WRITE(reg
, val
);
3233 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3234 struct drm_i915_gem_object
*obj
)
3236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3240 u32 size
= i915_gem_obj_ggtt_size(obj
);
3243 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3244 (size
& -size
) != size
||
3245 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3246 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3247 i915_gem_obj_ggtt_offset(obj
), size
);
3249 pitch_val
= obj
->stride
/ 128;
3250 pitch_val
= ffs(pitch_val
) - 1;
3252 val
= i915_gem_obj_ggtt_offset(obj
);
3253 if (obj
->tiling_mode
== I915_TILING_Y
)
3254 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3255 val
|= I830_FENCE_SIZE_BITS(size
);
3256 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3257 val
|= I830_FENCE_REG_VALID
;
3261 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3262 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3265 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3267 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3270 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3271 struct drm_i915_gem_object
*obj
)
3273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3275 /* Ensure that all CPU reads are completed before installing a fence
3276 * and all writes before removing the fence.
3278 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3281 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3282 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3283 obj
->stride
, obj
->tiling_mode
);
3286 i830_write_fence_reg(dev
, reg
, obj
);
3287 else if (IS_GEN3(dev
))
3288 i915_write_fence_reg(dev
, reg
, obj
);
3289 else if (INTEL_INFO(dev
)->gen
>= 4)
3290 i965_write_fence_reg(dev
, reg
, obj
);
3292 /* And similarly be paranoid that no direct access to this region
3293 * is reordered to before the fence is installed.
3295 if (i915_gem_object_needs_mb(obj
))
3299 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3300 struct drm_i915_fence_reg
*fence
)
3302 return fence
- dev_priv
->fence_regs
;
3305 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3306 struct drm_i915_fence_reg
*fence
,
3309 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3310 int reg
= fence_number(dev_priv
, fence
);
3312 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3315 obj
->fence_reg
= reg
;
3317 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3319 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3321 list_del_init(&fence
->lru_list
);
3323 obj
->fence_dirty
= false;
3327 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3329 if (obj
->last_fenced_req
) {
3330 int ret
= i915_wait_request(obj
->last_fenced_req
);
3334 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3341 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3343 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3344 struct drm_i915_fence_reg
*fence
;
3347 ret
= i915_gem_object_wait_fence(obj
);
3351 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3354 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3356 if (WARN_ON(fence
->pin_count
))
3359 i915_gem_object_fence_lost(obj
);
3360 i915_gem_object_update_fence(obj
, fence
, false);
3365 static struct drm_i915_fence_reg
*
3366 i915_find_fence_reg(struct drm_device
*dev
)
3368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3369 struct drm_i915_fence_reg
*reg
, *avail
;
3372 /* First try to find a free reg */
3374 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3375 reg
= &dev_priv
->fence_regs
[i
];
3379 if (!reg
->pin_count
)
3386 /* None available, try to steal one or wait for a user to finish */
3387 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3395 /* Wait for completion of pending flips which consume fences */
3396 if (intel_has_pending_fb_unpin(dev
))
3397 return ERR_PTR(-EAGAIN
);
3399 return ERR_PTR(-EDEADLK
);
3403 * i915_gem_object_get_fence - set up fencing for an object
3404 * @obj: object to map through a fence reg
3406 * When mapping objects through the GTT, userspace wants to be able to write
3407 * to them without having to worry about swizzling if the object is tiled.
3408 * This function walks the fence regs looking for a free one for @obj,
3409 * stealing one if it can't find any.
3411 * It then sets up the reg based on the object's properties: address, pitch
3412 * and tiling format.
3414 * For an untiled surface, this removes any existing fence.
3417 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3419 struct drm_device
*dev
= obj
->base
.dev
;
3420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3421 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3422 struct drm_i915_fence_reg
*reg
;
3425 /* Have we updated the tiling parameters upon the object and so
3426 * will need to serialise the write to the associated fence register?
3428 if (obj
->fence_dirty
) {
3429 ret
= i915_gem_object_wait_fence(obj
);
3434 /* Just update our place in the LRU if our fence is getting reused. */
3435 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3436 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3437 if (!obj
->fence_dirty
) {
3438 list_move_tail(®
->lru_list
,
3439 &dev_priv
->mm
.fence_list
);
3442 } else if (enable
) {
3443 if (WARN_ON(!obj
->map_and_fenceable
))
3446 reg
= i915_find_fence_reg(dev
);
3448 return PTR_ERR(reg
);
3451 struct drm_i915_gem_object
*old
= reg
->obj
;
3453 ret
= i915_gem_object_wait_fence(old
);
3457 i915_gem_object_fence_lost(old
);
3462 i915_gem_object_update_fence(obj
, reg
, enable
);
3467 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3468 unsigned long cache_level
)
3470 struct drm_mm_node
*gtt_space
= &vma
->node
;
3471 struct drm_mm_node
*other
;
3474 * On some machines we have to be careful when putting differing types
3475 * of snoopable memory together to avoid the prefetcher crossing memory
3476 * domains and dying. During vm initialisation, we decide whether or not
3477 * these constraints apply and set the drm_mm.color_adjust
3480 if (vma
->vm
->mm
.color_adjust
== NULL
)
3483 if (!drm_mm_node_allocated(gtt_space
))
3486 if (list_empty(>t_space
->node_list
))
3489 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3490 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3493 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3494 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3501 * Finds free space in the GTT aperture and binds the object there.
3503 static struct i915_vma
*
3504 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3505 struct i915_address_space
*vm
,
3508 const struct i915_ggtt_view
*view
)
3510 struct drm_device
*dev
= obj
->base
.dev
;
3511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3512 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3513 unsigned long start
=
3514 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3516 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3517 struct i915_vma
*vma
;
3520 fence_size
= i915_gem_get_gtt_size(dev
,
3523 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3525 obj
->tiling_mode
, true);
3526 unfenced_alignment
=
3527 i915_gem_get_gtt_alignment(dev
,
3529 obj
->tiling_mode
, false);
3532 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3534 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3535 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3536 return ERR_PTR(-EINVAL
);
3539 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3541 /* If the object is bigger than the entire aperture, reject it early
3542 * before evicting everything in a vain attempt to find space.
3544 if (obj
->base
.size
> end
) {
3545 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3547 flags
& PIN_MAPPABLE
? "mappable" : "total",
3549 return ERR_PTR(-E2BIG
);
3552 ret
= i915_gem_object_get_pages(obj
);
3554 return ERR_PTR(ret
);
3556 i915_gem_object_pin_pages(obj
);
3558 vma
= i915_gem_obj_lookup_or_create_vma_view(obj
, vm
, view
);
3563 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3567 DRM_MM_SEARCH_DEFAULT
,
3568 DRM_MM_CREATE_DEFAULT
);
3570 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3579 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3581 goto err_remove_node
;
3584 ret
= i915_gem_gtt_prepare_object(obj
);
3586 goto err_remove_node
;
3588 trace_i915_vma_bind(vma
, flags
);
3589 ret
= i915_vma_bind(vma
, obj
->cache_level
,
3590 flags
& PIN_GLOBAL
? GLOBAL_BIND
: 0);
3592 goto err_finish_gtt
;
3594 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3595 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3600 i915_gem_gtt_finish_object(obj
);
3602 drm_mm_remove_node(&vma
->node
);
3604 i915_gem_vma_destroy(vma
);
3607 i915_gem_object_unpin_pages(obj
);
3612 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3615 /* If we don't have a page list set up, then we're not pinned
3616 * to GPU, and we can ignore the cache flush because it'll happen
3617 * again at bind time.
3619 if (obj
->pages
== NULL
)
3623 * Stolen memory is always coherent with the GPU as it is explicitly
3624 * marked as wc by the system, or the system is cache-coherent.
3626 if (obj
->stolen
|| obj
->phys_handle
)
3629 /* If the GPU is snooping the contents of the CPU cache,
3630 * we do not need to manually clear the CPU cache lines. However,
3631 * the caches are only snooped when the render cache is
3632 * flushed/invalidated. As we always have to emit invalidations
3633 * and flushes when moving into and out of the RENDER domain, correct
3634 * snooping behaviour occurs naturally as the result of our domain
3637 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3640 trace_i915_gem_object_clflush(obj
);
3641 drm_clflush_sg(obj
->pages
);
3646 /** Flushes the GTT write domain for the object if it's dirty. */
3648 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3650 uint32_t old_write_domain
;
3652 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3655 /* No actual flushing is required for the GTT write domain. Writes
3656 * to it immediately go to main memory as far as we know, so there's
3657 * no chipset flush. It also doesn't land in render cache.
3659 * However, we do have to enforce the order so that all writes through
3660 * the GTT land before any writes to the device, such as updates to
3665 old_write_domain
= obj
->base
.write_domain
;
3666 obj
->base
.write_domain
= 0;
3668 intel_fb_obj_flush(obj
, false);
3670 trace_i915_gem_object_change_domain(obj
,
3671 obj
->base
.read_domains
,
3675 /** Flushes the CPU write domain for the object if it's dirty. */
3677 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
3680 uint32_t old_write_domain
;
3682 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3685 if (i915_gem_clflush_object(obj
, force
))
3686 i915_gem_chipset_flush(obj
->base
.dev
);
3688 old_write_domain
= obj
->base
.write_domain
;
3689 obj
->base
.write_domain
= 0;
3691 intel_fb_obj_flush(obj
, false);
3693 trace_i915_gem_object_change_domain(obj
,
3694 obj
->base
.read_domains
,
3699 * Moves a single object to the GTT read, and possibly write domain.
3701 * This function returns when the move is complete, including waiting on
3705 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3707 uint32_t old_write_domain
, old_read_domains
;
3708 struct i915_vma
*vma
;
3711 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3714 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3718 i915_gem_object_retire(obj
);
3720 /* Flush and acquire obj->pages so that we are coherent through
3721 * direct access in memory with previous cached writes through
3722 * shmemfs and that our cache domain tracking remains valid.
3723 * For example, if the obj->filp was moved to swap without us
3724 * being notified and releasing the pages, we would mistakenly
3725 * continue to assume that the obj remained out of the CPU cached
3728 ret
= i915_gem_object_get_pages(obj
);
3732 i915_gem_object_flush_cpu_write_domain(obj
, false);
3734 /* Serialise direct access to this object with the barriers for
3735 * coherent writes from the GPU, by effectively invalidating the
3736 * GTT domain upon first access.
3738 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3741 old_write_domain
= obj
->base
.write_domain
;
3742 old_read_domains
= obj
->base
.read_domains
;
3744 /* It should now be out of any other write domains, and we can update
3745 * the domain values for our changes.
3747 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3748 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3750 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3751 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3756 intel_fb_obj_invalidate(obj
, NULL
);
3758 trace_i915_gem_object_change_domain(obj
,
3762 /* And bump the LRU for this access */
3763 vma
= i915_gem_obj_to_ggtt(obj
);
3764 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3765 list_move_tail(&vma
->mm_list
,
3766 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3771 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3772 enum i915_cache_level cache_level
)
3774 struct drm_device
*dev
= obj
->base
.dev
;
3775 struct i915_vma
*vma
, *next
;
3778 if (obj
->cache_level
== cache_level
)
3781 if (i915_gem_obj_is_pinned(obj
)) {
3782 DRM_DEBUG("can not change the cache level of pinned objects\n");
3786 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3787 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3788 ret
= i915_vma_unbind(vma
);
3794 if (i915_gem_obj_bound_any(obj
)) {
3795 ret
= i915_gem_object_finish_gpu(obj
);
3799 i915_gem_object_finish_gtt(obj
);
3801 /* Before SandyBridge, you could not use tiling or fence
3802 * registers with snooped memory, so relinquish any fences
3803 * currently pointing to our region in the aperture.
3805 if (INTEL_INFO(dev
)->gen
< 6) {
3806 ret
= i915_gem_object_put_fence(obj
);
3811 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3812 if (drm_mm_node_allocated(&vma
->node
)) {
3813 ret
= i915_vma_bind(vma
, cache_level
,
3814 vma
->bound
& GLOBAL_BIND
);
3820 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3821 vma
->node
.color
= cache_level
;
3822 obj
->cache_level
= cache_level
;
3824 if (cpu_write_needs_clflush(obj
)) {
3825 u32 old_read_domains
, old_write_domain
;
3827 /* If we're coming from LLC cached, then we haven't
3828 * actually been tracking whether the data is in the
3829 * CPU cache or not, since we only allow one bit set
3830 * in obj->write_domain and have been skipping the clflushes.
3831 * Just set it to the CPU cache for now.
3833 i915_gem_object_retire(obj
);
3834 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3836 old_read_domains
= obj
->base
.read_domains
;
3837 old_write_domain
= obj
->base
.write_domain
;
3839 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3840 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3842 trace_i915_gem_object_change_domain(obj
,
3850 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3851 struct drm_file
*file
)
3853 struct drm_i915_gem_caching
*args
= data
;
3854 struct drm_i915_gem_object
*obj
;
3857 ret
= i915_mutex_lock_interruptible(dev
);
3861 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3862 if (&obj
->base
== NULL
) {
3867 switch (obj
->cache_level
) {
3868 case I915_CACHE_LLC
:
3869 case I915_CACHE_L3_LLC
:
3870 args
->caching
= I915_CACHING_CACHED
;
3874 args
->caching
= I915_CACHING_DISPLAY
;
3878 args
->caching
= I915_CACHING_NONE
;
3882 drm_gem_object_unreference(&obj
->base
);
3884 mutex_unlock(&dev
->struct_mutex
);
3888 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3889 struct drm_file
*file
)
3891 struct drm_i915_gem_caching
*args
= data
;
3892 struct drm_i915_gem_object
*obj
;
3893 enum i915_cache_level level
;
3896 switch (args
->caching
) {
3897 case I915_CACHING_NONE
:
3898 level
= I915_CACHE_NONE
;
3900 case I915_CACHING_CACHED
:
3901 level
= I915_CACHE_LLC
;
3903 case I915_CACHING_DISPLAY
:
3904 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3910 ret
= i915_mutex_lock_interruptible(dev
);
3914 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3915 if (&obj
->base
== NULL
) {
3920 ret
= i915_gem_object_set_cache_level(obj
, level
);
3922 drm_gem_object_unreference(&obj
->base
);
3924 mutex_unlock(&dev
->struct_mutex
);
3928 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3930 struct i915_vma
*vma
;
3932 vma
= i915_gem_obj_to_ggtt(obj
);
3936 /* There are 2 sources that pin objects:
3937 * 1. The display engine (scanouts, sprites, cursors);
3938 * 2. Reservations for execbuffer;
3940 * We can ignore reservations as we hold the struct_mutex and
3941 * are only called outside of the reservation path.
3943 return vma
->pin_count
;
3947 * Prepare buffer for display plane (scanout, cursors, etc).
3948 * Can be called from an uninterruptible phase (modesetting) and allows
3949 * any flushes to be pipelined (for pageflips).
3952 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3954 struct intel_engine_cs
*pipelined
)
3956 u32 old_read_domains
, old_write_domain
;
3957 bool was_pin_display
;
3960 if (pipelined
!= i915_gem_request_get_ring(obj
->last_read_req
)) {
3961 ret
= i915_gem_object_sync(obj
, pipelined
);
3966 /* Mark the pin_display early so that we account for the
3967 * display coherency whilst setting up the cache domains.
3969 was_pin_display
= obj
->pin_display
;
3970 obj
->pin_display
= true;
3972 /* The display engine is not coherent with the LLC cache on gen6. As
3973 * a result, we make sure that the pinning that is about to occur is
3974 * done with uncached PTEs. This is lowest common denominator for all
3977 * However for gen6+, we could do better by using the GFDT bit instead
3978 * of uncaching, which would allow us to flush all the LLC-cached data
3979 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3981 ret
= i915_gem_object_set_cache_level(obj
,
3982 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3984 goto err_unpin_display
;
3986 /* As the user may map the buffer once pinned in the display plane
3987 * (e.g. libkms for the bootup splash), we have to ensure that we
3988 * always use map_and_fenceable for all scanout buffers.
3990 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, PIN_MAPPABLE
);
3992 goto err_unpin_display
;
3994 i915_gem_object_flush_cpu_write_domain(obj
, true);
3996 old_write_domain
= obj
->base
.write_domain
;
3997 old_read_domains
= obj
->base
.read_domains
;
3999 /* It should now be out of any other write domains, and we can update
4000 * the domain values for our changes.
4002 obj
->base
.write_domain
= 0;
4003 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4005 trace_i915_gem_object_change_domain(obj
,
4012 WARN_ON(was_pin_display
!= is_pin_display(obj
));
4013 obj
->pin_display
= was_pin_display
;
4018 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
4020 i915_gem_object_ggtt_unpin(obj
);
4021 obj
->pin_display
= is_pin_display(obj
);
4025 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
4029 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
4032 ret
= i915_gem_object_wait_rendering(obj
, false);
4036 /* Ensure that we invalidate the GPU's caches and TLBs. */
4037 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4042 * Moves a single object to the CPU read, and possibly write domain.
4044 * This function returns when the move is complete, including waiting on
4048 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4050 uint32_t old_write_domain
, old_read_domains
;
4053 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4056 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4060 i915_gem_object_retire(obj
);
4061 i915_gem_object_flush_gtt_write_domain(obj
);
4063 old_write_domain
= obj
->base
.write_domain
;
4064 old_read_domains
= obj
->base
.read_domains
;
4066 /* Flush the CPU cache if it's still invalid. */
4067 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4068 i915_gem_clflush_object(obj
, false);
4070 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4073 /* It should now be out of any other write domains, and we can update
4074 * the domain values for our changes.
4076 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4078 /* If we're writing through the CPU, then the GPU read domains will
4079 * need to be invalidated at next use.
4082 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4083 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4087 intel_fb_obj_invalidate(obj
, NULL
);
4089 trace_i915_gem_object_change_domain(obj
,
4096 /* Throttle our rendering by waiting until the ring has completed our requests
4097 * emitted over 20 msec ago.
4099 * Note that if we were to use the current jiffies each time around the loop,
4100 * we wouldn't escape the function with any frames outstanding if the time to
4101 * render a frame was over 20ms.
4103 * This should get us reasonable parallelism between CPU and GPU but also
4104 * relatively low latency when blocking on a particular request to finish.
4107 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4110 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4111 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4112 struct drm_i915_gem_request
*request
, *target
= NULL
;
4113 unsigned reset_counter
;
4116 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4120 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4124 spin_lock(&file_priv
->mm
.lock
);
4125 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4126 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4131 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4133 i915_gem_request_reference(target
);
4134 spin_unlock(&file_priv
->mm
.lock
);
4139 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4141 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4143 mutex_lock(&dev
->struct_mutex
);
4144 i915_gem_request_unreference(target
);
4145 mutex_unlock(&dev
->struct_mutex
);
4151 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4153 struct drm_i915_gem_object
*obj
= vma
->obj
;
4156 vma
->node
.start
& (alignment
- 1))
4159 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4162 if (flags
& PIN_OFFSET_BIAS
&&
4163 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4170 i915_gem_object_pin_view(struct drm_i915_gem_object
*obj
,
4171 struct i915_address_space
*vm
,
4174 const struct i915_ggtt_view
*view
)
4176 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4177 struct i915_vma
*vma
;
4181 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4184 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4187 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4190 vma
= i915_gem_obj_to_vma_view(obj
, vm
, view
);
4192 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4195 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4196 WARN(vma
->pin_count
,
4197 "bo is already pinned with incorrect alignment:"
4198 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4199 " obj->map_and_fenceable=%d\n",
4200 i915_gem_obj_offset_view(obj
, vm
, view
->type
),
4202 !!(flags
& PIN_MAPPABLE
),
4203 obj
->map_and_fenceable
);
4204 ret
= i915_vma_unbind(vma
);
4212 bound
= vma
? vma
->bound
: 0;
4213 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4214 vma
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
,
4217 return PTR_ERR(vma
);
4220 if (flags
& PIN_GLOBAL
&& !(vma
->bound
& GLOBAL_BIND
)) {
4221 ret
= i915_vma_bind(vma
, obj
->cache_level
, GLOBAL_BIND
);
4226 if ((bound
^ vma
->bound
) & GLOBAL_BIND
) {
4227 bool mappable
, fenceable
;
4228 u32 fence_size
, fence_alignment
;
4230 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4233 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4238 fenceable
= (vma
->node
.size
== fence_size
&&
4239 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4241 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
4242 dev_priv
->gtt
.mappable_end
);
4244 obj
->map_and_fenceable
= mappable
&& fenceable
;
4247 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4250 if (flags
& PIN_MAPPABLE
)
4251 obj
->pin_mappable
|= true;
4257 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
4259 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
4262 BUG_ON(vma
->pin_count
== 0);
4263 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
4265 if (--vma
->pin_count
== 0)
4266 obj
->pin_mappable
= false;
4270 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4272 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4273 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4274 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4276 WARN_ON(!ggtt_vma
||
4277 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4278 ggtt_vma
->pin_count
);
4279 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4286 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4288 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4289 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4290 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4291 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4296 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4297 struct drm_file
*file
)
4299 struct drm_i915_gem_busy
*args
= data
;
4300 struct drm_i915_gem_object
*obj
;
4303 ret
= i915_mutex_lock_interruptible(dev
);
4307 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4308 if (&obj
->base
== NULL
) {
4313 /* Count all active objects as busy, even if they are currently not used
4314 * by the gpu. Users of this interface expect objects to eventually
4315 * become non-busy without any further actions, therefore emit any
4316 * necessary flushes here.
4318 ret
= i915_gem_object_flush_active(obj
);
4320 args
->busy
= obj
->active
;
4321 if (obj
->last_read_req
) {
4322 struct intel_engine_cs
*ring
;
4323 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4324 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
4325 args
->busy
|= intel_ring_flag(ring
) << 16;
4328 drm_gem_object_unreference(&obj
->base
);
4330 mutex_unlock(&dev
->struct_mutex
);
4335 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4336 struct drm_file
*file_priv
)
4338 return i915_gem_ring_throttle(dev
, file_priv
);
4342 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4343 struct drm_file
*file_priv
)
4345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4346 struct drm_i915_gem_madvise
*args
= data
;
4347 struct drm_i915_gem_object
*obj
;
4350 switch (args
->madv
) {
4351 case I915_MADV_DONTNEED
:
4352 case I915_MADV_WILLNEED
:
4358 ret
= i915_mutex_lock_interruptible(dev
);
4362 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4363 if (&obj
->base
== NULL
) {
4368 if (i915_gem_obj_is_pinned(obj
)) {
4374 obj
->tiling_mode
!= I915_TILING_NONE
&&
4375 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4376 if (obj
->madv
== I915_MADV_WILLNEED
)
4377 i915_gem_object_unpin_pages(obj
);
4378 if (args
->madv
== I915_MADV_WILLNEED
)
4379 i915_gem_object_pin_pages(obj
);
4382 if (obj
->madv
!= __I915_MADV_PURGED
)
4383 obj
->madv
= args
->madv
;
4385 /* if the object is no longer attached, discard its backing storage */
4386 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4387 i915_gem_object_truncate(obj
);
4389 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4392 drm_gem_object_unreference(&obj
->base
);
4394 mutex_unlock(&dev
->struct_mutex
);
4398 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4399 const struct drm_i915_gem_object_ops
*ops
)
4401 INIT_LIST_HEAD(&obj
->global_list
);
4402 INIT_LIST_HEAD(&obj
->ring_list
);
4403 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4404 INIT_LIST_HEAD(&obj
->vma_list
);
4405 INIT_LIST_HEAD(&obj
->batch_pool_list
);
4409 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4410 obj
->madv
= I915_MADV_WILLNEED
;
4412 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4415 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4416 .get_pages
= i915_gem_object_get_pages_gtt
,
4417 .put_pages
= i915_gem_object_put_pages_gtt
,
4420 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4423 struct drm_i915_gem_object
*obj
;
4424 struct address_space
*mapping
;
4427 obj
= i915_gem_object_alloc(dev
);
4431 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4432 i915_gem_object_free(obj
);
4436 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4437 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4438 /* 965gm cannot relocate objects above 4GiB. */
4439 mask
&= ~__GFP_HIGHMEM
;
4440 mask
|= __GFP_DMA32
;
4443 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4444 mapping_set_gfp_mask(mapping
, mask
);
4446 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4448 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4449 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4452 /* On some devices, we can have the GPU use the LLC (the CPU
4453 * cache) for about a 10% performance improvement
4454 * compared to uncached. Graphics requests other than
4455 * display scanout are coherent with the CPU in
4456 * accessing this cache. This means in this mode we
4457 * don't need to clflush on the CPU side, and on the
4458 * GPU side we only need to flush internal caches to
4459 * get data visible to the CPU.
4461 * However, we maintain the display planes as UC, and so
4462 * need to rebind when first used as such.
4464 obj
->cache_level
= I915_CACHE_LLC
;
4466 obj
->cache_level
= I915_CACHE_NONE
;
4468 trace_i915_gem_object_create(obj
);
4473 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4475 /* If we are the last user of the backing storage (be it shmemfs
4476 * pages or stolen etc), we know that the pages are going to be
4477 * immediately released. In this case, we can then skip copying
4478 * back the contents from the GPU.
4481 if (obj
->madv
!= I915_MADV_WILLNEED
)
4484 if (obj
->base
.filp
== NULL
)
4487 /* At first glance, this looks racy, but then again so would be
4488 * userspace racing mmap against close. However, the first external
4489 * reference to the filp can only be obtained through the
4490 * i915_gem_mmap_ioctl() which safeguards us against the user
4491 * acquiring such a reference whilst we are in the middle of
4492 * freeing the object.
4494 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4497 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4499 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4500 struct drm_device
*dev
= obj
->base
.dev
;
4501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4502 struct i915_vma
*vma
, *next
;
4504 intel_runtime_pm_get(dev_priv
);
4506 trace_i915_gem_object_destroy(obj
);
4508 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4512 ret
= i915_vma_unbind(vma
);
4513 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4514 bool was_interruptible
;
4516 was_interruptible
= dev_priv
->mm
.interruptible
;
4517 dev_priv
->mm
.interruptible
= false;
4519 WARN_ON(i915_vma_unbind(vma
));
4521 dev_priv
->mm
.interruptible
= was_interruptible
;
4525 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4526 * before progressing. */
4528 i915_gem_object_unpin_pages(obj
);
4530 WARN_ON(obj
->frontbuffer_bits
);
4532 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4533 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4534 obj
->tiling_mode
!= I915_TILING_NONE
)
4535 i915_gem_object_unpin_pages(obj
);
4537 if (WARN_ON(obj
->pages_pin_count
))
4538 obj
->pages_pin_count
= 0;
4539 if (discard_backing_storage(obj
))
4540 obj
->madv
= I915_MADV_DONTNEED
;
4541 i915_gem_object_put_pages(obj
);
4542 i915_gem_object_free_mmap_offset(obj
);
4546 if (obj
->base
.import_attach
)
4547 drm_prime_gem_destroy(&obj
->base
, NULL
);
4549 if (obj
->ops
->release
)
4550 obj
->ops
->release(obj
);
4552 drm_gem_object_release(&obj
->base
);
4553 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4556 i915_gem_object_free(obj
);
4558 intel_runtime_pm_put(dev_priv
);
4561 struct i915_vma
*i915_gem_obj_to_vma_view(struct drm_i915_gem_object
*obj
,
4562 struct i915_address_space
*vm
,
4563 const struct i915_ggtt_view
*view
)
4565 struct i915_vma
*vma
;
4566 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4567 if (vma
->vm
== vm
&& vma
->ggtt_view
.type
== view
->type
)
4573 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4575 struct i915_address_space
*vm
= NULL
;
4576 WARN_ON(vma
->node
.allocated
);
4578 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4579 if (!list_empty(&vma
->exec_list
))
4584 if (!i915_is_ggtt(vm
))
4585 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4587 list_del(&vma
->vma_link
);
4593 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4596 struct intel_engine_cs
*ring
;
4599 for_each_ring(ring
, dev_priv
, i
)
4600 dev_priv
->gt
.stop_ring(ring
);
4604 i915_gem_suspend(struct drm_device
*dev
)
4606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4609 mutex_lock(&dev
->struct_mutex
);
4610 ret
= i915_gpu_idle(dev
);
4614 i915_gem_retire_requests(dev
);
4616 /* Under UMS, be paranoid and evict. */
4617 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4618 i915_gem_evict_everything(dev
);
4620 i915_gem_stop_ringbuffers(dev
);
4621 mutex_unlock(&dev
->struct_mutex
);
4623 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4624 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4625 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4627 /* Assert that we sucessfully flushed all the work and
4628 * reset the GPU back to its idle, low power state.
4630 WARN_ON(dev_priv
->mm
.busy
);
4635 mutex_unlock(&dev
->struct_mutex
);
4639 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4641 struct drm_device
*dev
= ring
->dev
;
4642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4643 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4644 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4647 if (!HAS_L3_DPF(dev
) || !remap_info
)
4650 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4655 * Note: We do not worry about the concurrent register cacheline hang
4656 * here because no other code should access these registers other than
4657 * at initialization time.
4659 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4660 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4661 intel_ring_emit(ring
, reg_base
+ i
);
4662 intel_ring_emit(ring
, remap_info
[i
/4]);
4665 intel_ring_advance(ring
);
4670 void i915_gem_init_swizzling(struct drm_device
*dev
)
4672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4674 if (INTEL_INFO(dev
)->gen
< 5 ||
4675 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4678 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4679 DISP_TILE_SURFACE_SWIZZLING
);
4684 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4686 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4687 else if (IS_GEN7(dev
))
4688 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4689 else if (IS_GEN8(dev
))
4690 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4696 intel_enable_blt(struct drm_device
*dev
)
4701 /* The blitter was dysfunctional on early prototypes */
4702 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4703 DRM_INFO("BLT not supported on this pre-production hardware;"
4704 " graphics performance will be degraded.\n");
4711 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4713 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4715 I915_WRITE(RING_CTL(base
), 0);
4716 I915_WRITE(RING_HEAD(base
), 0);
4717 I915_WRITE(RING_TAIL(base
), 0);
4718 I915_WRITE(RING_START(base
), 0);
4721 static void init_unused_rings(struct drm_device
*dev
)
4724 init_unused_ring(dev
, PRB1_BASE
);
4725 init_unused_ring(dev
, SRB0_BASE
);
4726 init_unused_ring(dev
, SRB1_BASE
);
4727 init_unused_ring(dev
, SRB2_BASE
);
4728 init_unused_ring(dev
, SRB3_BASE
);
4729 } else if (IS_GEN2(dev
)) {
4730 init_unused_ring(dev
, SRB0_BASE
);
4731 init_unused_ring(dev
, SRB1_BASE
);
4732 } else if (IS_GEN3(dev
)) {
4733 init_unused_ring(dev
, PRB1_BASE
);
4734 init_unused_ring(dev
, PRB2_BASE
);
4738 int i915_gem_init_rings(struct drm_device
*dev
)
4740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4743 ret
= intel_init_render_ring_buffer(dev
);
4748 ret
= intel_init_bsd_ring_buffer(dev
);
4750 goto cleanup_render_ring
;
4753 if (intel_enable_blt(dev
)) {
4754 ret
= intel_init_blt_ring_buffer(dev
);
4756 goto cleanup_bsd_ring
;
4759 if (HAS_VEBOX(dev
)) {
4760 ret
= intel_init_vebox_ring_buffer(dev
);
4762 goto cleanup_blt_ring
;
4765 if (HAS_BSD2(dev
)) {
4766 ret
= intel_init_bsd2_ring_buffer(dev
);
4768 goto cleanup_vebox_ring
;
4771 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4773 goto cleanup_bsd2_ring
;
4778 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4780 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4782 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4784 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4785 cleanup_render_ring
:
4786 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4792 i915_gem_init_hw(struct drm_device
*dev
)
4794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4795 struct intel_engine_cs
*ring
;
4798 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4801 if (dev_priv
->ellc_size
)
4802 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4804 if (IS_HASWELL(dev
))
4805 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4806 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4808 if (HAS_PCH_NOP(dev
)) {
4809 if (IS_IVYBRIDGE(dev
)) {
4810 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4811 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4812 I915_WRITE(GEN7_MSG_CTL
, temp
);
4813 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4814 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4815 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4816 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4820 i915_gem_init_swizzling(dev
);
4823 * At least 830 can leave some of the unused rings
4824 * "active" (ie. head != tail) after resume which
4825 * will prevent c3 entry. Makes sure all unused rings
4828 init_unused_rings(dev
);
4830 for_each_ring(ring
, dev_priv
, i
) {
4831 ret
= ring
->init_hw(ring
);
4836 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4837 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4840 * XXX: Contexts should only be initialized once. Doing a switch to the
4841 * default context switch however is something we'd like to do after
4842 * reset or thaw (the latter may not actually be necessary for HW, but
4843 * goes with our code better). Context switching requires rings (for
4844 * the do_switch), but before enabling PPGTT. So don't move this.
4846 ret
= i915_gem_context_enable(dev_priv
);
4847 if (ret
&& ret
!= -EIO
) {
4848 DRM_ERROR("Context enable failed %d\n", ret
);
4849 i915_gem_cleanup_ringbuffer(dev
);
4854 ret
= i915_ppgtt_init_hw(dev
);
4855 if (ret
&& ret
!= -EIO
) {
4856 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4857 i915_gem_cleanup_ringbuffer(dev
);
4863 int i915_gem_init(struct drm_device
*dev
)
4865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4868 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4869 i915
.enable_execlists
);
4871 mutex_lock(&dev
->struct_mutex
);
4873 if (IS_VALLEYVIEW(dev
)) {
4874 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4875 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4876 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4877 VLV_GTLC_ALLOWWAKEACK
), 10))
4878 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4881 if (!i915
.enable_execlists
) {
4882 dev_priv
->gt
.do_execbuf
= i915_gem_ringbuffer_submission
;
4883 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4884 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4885 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4887 dev_priv
->gt
.do_execbuf
= intel_execlists_submission
;
4888 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4889 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4890 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4893 ret
= i915_gem_init_userptr(dev
);
4897 i915_gem_init_global_gtt(dev
);
4899 ret
= i915_gem_context_init(dev
);
4903 ret
= dev_priv
->gt
.init_rings(dev
);
4907 ret
= i915_gem_init_hw(dev
);
4909 /* Allow ring initialisation to fail by marking the GPU as
4910 * wedged. But we only want to do this where the GPU is angry,
4911 * for all other failure, such as an allocation failure, bail.
4913 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4914 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4919 mutex_unlock(&dev
->struct_mutex
);
4925 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4928 struct intel_engine_cs
*ring
;
4931 for_each_ring(ring
, dev_priv
, i
)
4932 dev_priv
->gt
.cleanup_ring(ring
);
4936 init_ring_lists(struct intel_engine_cs
*ring
)
4938 INIT_LIST_HEAD(&ring
->active_list
);
4939 INIT_LIST_HEAD(&ring
->request_list
);
4942 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4943 struct i915_address_space
*vm
)
4945 if (!i915_is_ggtt(vm
))
4946 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
4947 vm
->dev
= dev_priv
->dev
;
4948 INIT_LIST_HEAD(&vm
->active_list
);
4949 INIT_LIST_HEAD(&vm
->inactive_list
);
4950 INIT_LIST_HEAD(&vm
->global_link
);
4951 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
4955 i915_gem_load(struct drm_device
*dev
)
4957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4961 kmem_cache_create("i915_gem_object",
4962 sizeof(struct drm_i915_gem_object
), 0,
4966 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4967 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4969 INIT_LIST_HEAD(&dev_priv
->context_list
);
4970 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4971 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4972 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4973 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4974 init_ring_lists(&dev_priv
->ring
[i
]);
4975 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4976 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4977 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4978 i915_gem_retire_work_handler
);
4979 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4980 i915_gem_idle_work_handler
);
4981 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4983 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4984 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) && IS_GEN3(dev
)) {
4985 I915_WRITE(MI_ARB_STATE
,
4986 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4989 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4991 /* Old X drivers will take 0-2 for front, back, depth buffers */
4992 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4993 dev_priv
->fence_reg_start
= 3;
4995 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4996 dev_priv
->num_fence_regs
= 32;
4997 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4998 dev_priv
->num_fence_regs
= 16;
5000 dev_priv
->num_fence_regs
= 8;
5002 /* Initialize fence registers to zero */
5003 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5004 i915_gem_restore_fences(dev
);
5006 i915_gem_detect_bit_6_swizzle(dev
);
5007 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5009 dev_priv
->mm
.interruptible
= true;
5011 dev_priv
->mm
.shrinker
.scan_objects
= i915_gem_shrinker_scan
;
5012 dev_priv
->mm
.shrinker
.count_objects
= i915_gem_shrinker_count
;
5013 dev_priv
->mm
.shrinker
.seeks
= DEFAULT_SEEKS
;
5014 register_shrinker(&dev_priv
->mm
.shrinker
);
5016 dev_priv
->mm
.oom_notifier
.notifier_call
= i915_gem_shrinker_oom
;
5017 register_oom_notifier(&dev_priv
->mm
.oom_notifier
);
5019 i915_gem_batch_pool_init(dev
, &dev_priv
->mm
.batch_pool
);
5021 mutex_init(&dev_priv
->fb_tracking
.lock
);
5024 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5026 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5028 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
5030 /* Clean up our request list when the client is going away, so that
5031 * later retire_requests won't dereference our soon-to-be-gone
5034 spin_lock(&file_priv
->mm
.lock
);
5035 while (!list_empty(&file_priv
->mm
.request_list
)) {
5036 struct drm_i915_gem_request
*request
;
5038 request
= list_first_entry(&file_priv
->mm
.request_list
,
5039 struct drm_i915_gem_request
,
5041 list_del(&request
->client_list
);
5042 request
->file_priv
= NULL
;
5044 spin_unlock(&file_priv
->mm
.lock
);
5048 i915_gem_file_idle_work_handler(struct work_struct
*work
)
5050 struct drm_i915_file_private
*file_priv
=
5051 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
5053 atomic_set(&file_priv
->rps_wait_boost
, false);
5056 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5058 struct drm_i915_file_private
*file_priv
;
5061 DRM_DEBUG_DRIVER("\n");
5063 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5067 file
->driver_priv
= file_priv
;
5068 file_priv
->dev_priv
= dev
->dev_private
;
5069 file_priv
->file
= file
;
5071 spin_lock_init(&file_priv
->mm
.lock
);
5072 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5073 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
5074 i915_gem_file_idle_work_handler
);
5076 ret
= i915_gem_context_open(dev
, file
);
5084 * i915_gem_track_fb - update frontbuffer tracking
5085 * old: current GEM buffer for the frontbuffer slots
5086 * new: new GEM buffer for the frontbuffer slots
5087 * frontbuffer_bits: bitmask of frontbuffer slots
5089 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5090 * from @old and setting them in @new. Both @old and @new can be NULL.
5092 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5093 struct drm_i915_gem_object
*new,
5094 unsigned frontbuffer_bits
)
5097 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5098 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5099 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5103 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5104 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5105 new->frontbuffer_bits
|= frontbuffer_bits
;
5109 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
5111 if (!mutex_is_locked(mutex
))
5114 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5115 return mutex
->owner
== task
;
5117 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5122 static bool i915_gem_shrinker_lock(struct drm_device
*dev
, bool *unlock
)
5124 if (!mutex_trylock(&dev
->struct_mutex
)) {
5125 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5128 if (to_i915(dev
)->mm
.shrinker_no_lock_stealing
)
5138 static int num_vma_bound(struct drm_i915_gem_object
*obj
)
5140 struct i915_vma
*vma
;
5143 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5144 if (drm_mm_node_allocated(&vma
->node
))
5150 static unsigned long
5151 i915_gem_shrinker_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5153 struct drm_i915_private
*dev_priv
=
5154 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5155 struct drm_device
*dev
= dev_priv
->dev
;
5156 struct drm_i915_gem_object
*obj
;
5157 unsigned long count
;
5160 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5164 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
5165 if (obj
->pages_pin_count
== 0)
5166 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5168 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5169 if (!i915_gem_obj_is_pinned(obj
) &&
5170 obj
->pages_pin_count
== num_vma_bound(obj
))
5171 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5175 mutex_unlock(&dev
->struct_mutex
);
5180 /* All the new VM stuff */
5181 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object
*o
,
5182 struct i915_address_space
*vm
,
5183 enum i915_ggtt_view_type view
)
5185 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5186 struct i915_vma
*vma
;
5188 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5190 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5191 if (vma
->vm
== vm
&& vma
->ggtt_view
.type
== view
)
5192 return vma
->node
.start
;
5195 WARN(1, "%s vma for this object not found.\n",
5196 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5200 bool i915_gem_obj_bound_view(struct drm_i915_gem_object
*o
,
5201 struct i915_address_space
*vm
,
5202 enum i915_ggtt_view_type view
)
5204 struct i915_vma
*vma
;
5206 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5207 if (vma
->vm
== vm
&&
5208 vma
->ggtt_view
.type
== view
&&
5209 drm_mm_node_allocated(&vma
->node
))
5215 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5217 struct i915_vma
*vma
;
5219 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5220 if (drm_mm_node_allocated(&vma
->node
))
5226 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5227 struct i915_address_space
*vm
)
5229 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5230 struct i915_vma
*vma
;
5232 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5234 BUG_ON(list_empty(&o
->vma_list
));
5236 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5238 return vma
->node
.size
;
5243 static unsigned long
5244 i915_gem_shrinker_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5246 struct drm_i915_private
*dev_priv
=
5247 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5248 struct drm_device
*dev
= dev_priv
->dev
;
5249 unsigned long freed
;
5252 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5255 freed
= i915_gem_shrink(dev_priv
,
5258 I915_SHRINK_UNBOUND
|
5259 I915_SHRINK_PURGEABLE
);
5260 if (freed
< sc
->nr_to_scan
)
5261 freed
+= i915_gem_shrink(dev_priv
,
5262 sc
->nr_to_scan
- freed
,
5264 I915_SHRINK_UNBOUND
);
5266 mutex_unlock(&dev
->struct_mutex
);
5272 i915_gem_shrinker_oom(struct notifier_block
*nb
, unsigned long event
, void *ptr
)
5274 struct drm_i915_private
*dev_priv
=
5275 container_of(nb
, struct drm_i915_private
, mm
.oom_notifier
);
5276 struct drm_device
*dev
= dev_priv
->dev
;
5277 struct drm_i915_gem_object
*obj
;
5278 unsigned long timeout
= msecs_to_jiffies(5000) + 1;
5279 unsigned long pinned
, bound
, unbound
, freed_pages
;
5280 bool was_interruptible
;
5283 while (!i915_gem_shrinker_lock(dev
, &unlock
) && --timeout
) {
5284 schedule_timeout_killable(1);
5285 if (fatal_signal_pending(current
))
5289 pr_err("Unable to purge GPU memory due lock contention.\n");
5293 was_interruptible
= dev_priv
->mm
.interruptible
;
5294 dev_priv
->mm
.interruptible
= false;
5296 freed_pages
= i915_gem_shrink_all(dev_priv
);
5298 dev_priv
->mm
.interruptible
= was_interruptible
;
5300 /* Because we may be allocating inside our own driver, we cannot
5301 * assert that there are no objects with pinned pages that are not
5302 * being pointed to by hardware.
5304 unbound
= bound
= pinned
= 0;
5305 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5306 if (!obj
->base
.filp
) /* not backed by a freeable object */
5309 if (obj
->pages_pin_count
)
5310 pinned
+= obj
->base
.size
;
5312 unbound
+= obj
->base
.size
;
5314 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5315 if (!obj
->base
.filp
)
5318 if (obj
->pages_pin_count
)
5319 pinned
+= obj
->base
.size
;
5321 bound
+= obj
->base
.size
;
5325 mutex_unlock(&dev
->struct_mutex
);
5327 if (freed_pages
|| unbound
|| bound
)
5328 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5329 freed_pages
<< PAGE_SHIFT
, pinned
);
5330 if (unbound
|| bound
)
5331 pr_err("%lu and %lu bytes still available in the "
5332 "bound and unbound GPU page lists.\n",
5335 *(unsigned long *)ptr
+= freed_pages
;
5339 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
5341 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
5342 struct i915_vma
*vma
;
5344 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5345 if (vma
->vm
== ggtt
&&
5346 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)